97SD3240 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks Logic Diagram (One Amplifier) Memory FEATURES: DESCRIPTION: • 1.25 Gigabit ( 8-Meg X 40-Bit X 4-Banks) • RAD-PAK® radiation-hardened against natural space radiation • Total Dose Hardness: >100 krad (Si), depending upon space mission • Excellent Single Event Effects: SELTH > 85 MeV/mg/cm2 @ 25°C • JEDEC Standard 3.3V Power Supply • Clock Frequency: 100 MHz Operation • Operating tremperature: -55 to +125 °C • Auto Refresh • Single pulsed RAS • 2 Burst Sequence variations Sequential (BL =1/2/4/8) Interleave (BL = 1/2/4/8) • Programmable CAS latency: 2/3 • Power Down and Clock Suspend Modes • LVTTL Compatible Inputs and Outputs • Package: 132 Lead Quad Stack Pack Flat Package Maxwell Technologies’ Synchronous Dynamic Random Access Memory (SDRAM) is ideally suited for space applications requiring high performance computing and high density memory storage. As microprocessors increase in speed and demand for higher density memory escalates, SDRAM has proven to be the ultimate solution by providing bit-counts up to 1.25 Gigabits and speeds up to 100 Megahertz. SDRAMs represent a significant advantage in memory technology over traditional DRAMs including the ability to burst data synchronously at high rates with automatic column-address generation, the ability to interleave between banks masking precharge time Maxwell Technologies’ patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding for a lifetime in orbit or space mission. In a typical GEO orbit, RAD-PAK® provides greater than 100 krads(Si) radiation dose tolerance. This product is available with screening up to Maxwell Technologies self-defined Class K. 08.25.15 Rev 6 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com All data sheets are subject to change without notice 1 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Pinout Description Memory The 97SD3240 Consists of 5, 8-Meg X 8-Bit X 4-Banks, die. The 132 Pin 3-layer stack package contains twodie in layer one and two die in layer two and one die in layer three. CLK1 clocks die 1, 3 and 5, while CLK2 clocks die 2 and 4. CKE 1-5, CS 1-5 and DQM 1-5 correspond to one of the die: CKE1, CS1 and DQM1 control D0 - D7 CKE2, CS2 and DQM2 control D8 - D15 CKE3, CS3 and DQM3 control D16 - D23 CKE4, CS4 and DQM4 control D24 - D31 CKE5, CS5 and DQM5 control D32 - D39 08.25.15 Rev 6 All data sheets are subject to change without notice 2 ©2015 Maxwell Technologies All rights reserved. 97SD3240 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM ‘ TABLE 1. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MAX UNIT Voltage on any pin relative to VSS VIN VOUT -0.5 to VCC + 0.5 (< 4.6(max)) V Supply voltage relative to VSS VCC -0.5 to +4.6 V Short circuit output current IOUT 50 mA Weight Mass 53 Grams Tjc 3.8 °C/W Operating Temperature TOPR -55 to +125 °C Storage Temperature TSTG -65 to +150 °C Thermal Resistance TABLE 2. RECOMMENDED OPERATING CONDITIONS (VCC = 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) SYMBOL M IN M AX VCC, VCCQ1,2 3.0 3.6 VSS, VSSQ3 0 0 Input High Voltage VIH1,4 2.0 VCC + 0.3 Input Low Voltage VIL1,5 -0.3 0.8 1. All voltage referred to VSS 2. The supply voltage with all VCC and VCCQ pins must be on the same level 3. The supply voltage with all V SS and V SSQ pins must be on the same level 4. VIH (max) = VCC+2.0V for pulse width <3ns at VCC 5. VIL (min) = VSS-2.0V for pulse width <3ns at VSS UNIT V V V V Memory PARAMETER Supply Voltage TABLE 3. DELTA LIMITS PARAMETER DESCRIPTION VARIATION1 ICC1 Operating Current ±10% ICC2P ICC2PS ICC2N ICC2NS Power Down Standby Current ±10% ICC3P ICC3PS ICC3N ICC3NS Active Standby Current 1. ±10% of value specified in Table 4 ±10% TABLE 4. DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER Operating Current1,2,3 Standby Current in Power Down4 SYMBOL TEST CONDITIONS SUBGROUPS ICC1 Burst length CAS Latency = 2 =1 CAS Latency = 3 tRC = min 1, 2, 3 CKE = VIL tCK = 12 ns 1, 2, 3 ICC2P 08.25.15 Rev 6 MIN MAX UNITS 575 mA 575 15 mA All data sheets are subject to change without notice 3 ©2015 Maxwell Technologies All rights reserved. 97SD3240 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM TABLE 4. DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL TEST CONDITIONS SUBGROUPS Standby Current in Power Down ( input signal stable)5 ICC2PS CKE = VIL tCK = 0 Standby Current in non power down6 ICC2N Standby Current in non power down7 ( Input signal stable) UNITS 1, 2, 3 10 mA CKE, CS = VIH tCK = 12 ns 1, 2, 3 100 mA ICC2NS CKE = VIH tCK = 0 1, 2, 3 45 mA Active standby current in1,2,4 power down ICC3P CKE = VIL tCK = 12 ns 1, 2, 3 20 mA Active standby current in power down (input signal stable)2,5 ICC3PS CKE = VIL tCK = 0 1, 2, 3 15 mA Active standby power in non power down1,2,6 ICC3N CKE, CS1-6 = VIH tCK = 12 ns 1, 2, 3 150 mA Active standby current in non power down ( input signal stable)2,7 ICC3NS CKE = VIH tCK = 0 1, 2, 3 75 mA Burst Operating Current1,2,8 CAS Latency = 2 CAS Latency = 3 ICC4 tCK = min BL = 4 1, 2, 3 Refresh Current3 ICC5 tRC = min 1, 2, 3 1100 mA ICC6 VIH>VCC - 0.2V VIL < 0.2 V 1, 2, 3 15 mA Input Leakage Current - CLK ILI 0<VLI<VCC 1, 2, 3 -3 3 uA Input Leakage Current - All Other ILI 0<VLI<VCC 1, 2, 3 -5 5 uA Output Leakage Current ILO 0<VLO<VCC 1, 2, 3 -1.5 1.5 uA Output high voltage VOH IOH = -4mA 1, 2, 3 2.4 Self Refresh Memory MAX current9 MIN mA 550 725 V IOL = 4 mA 1, 2, 3 0.4 V Output low voltage VOL 1. ICC1 depends on output load conditions when the device is selected. ICC1(max) is specified with the output open. 2. One Bank Operation 3. Input signals are changed once per clock. 4. After power down mode, CLK operating current. 5. After power down mode, no CLK operating current. 6. Input signals are changed once per two clocks. 7. Input signals for VIH or VIL are fixed. 8. Input signals are changed once per four clocks. 9. After self refresh mode set, self refresh current. Use Self Refresh for temperatures less than 70 °C ONLY. 08.25.15 Rev 6 All data sheets are subject to change without notice 4 ©2015 Maxwell Technologies All rights reserved. 97SD3240 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM TABLE 5. AC Electrical Characteristics (VCC =3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) SYMBOL SUBGROUPS System clock cycle time1 (CAS latency = 2) (CAS latency = 3) tCK 9, 10, 11 CLK high pulse width1,7 tCKH 9, 10, 11 2.5 ns width1,7, tCKL 9, 10, 11 2.5 ns tAC 9, 10, 11 PARAMETER CLK low pulse Access time from (CAS latency = 2) (CAS latency = 3) CLK1,2 Data-out hold time1,2,3 MIN TYPICAL MAX UNIT ns 10 7.5 ns 6 6 tOH 9, 10, 11 2.7 ns impedance1,2,3,7 tLZ 9, 10, 11 2 ns impedance1,47, tHZ 9, 10, 11 tAS, tCS, tDS, tCES 9, 10, 11 1.5 ns tCESP 9, 10, 11 1.5 ns tAH, tCH, tDH tCEH 9, 10, 11 1.5 ns Ref/Active to Ref/Active command period1 tRC 9, 10, 11 70 ns Active to Precharge command period1 tRAS 9, 10, 11 50 tRCD 9, 10, 11 20 ns tRP 9, 10, 11 20 ns tDPL 9, 10, 11 20 ns tRRD 9, 10, 11 20 ns tT 9, 10, 11 1 CLK to Data-out low CLK to Data-out high (CAS latency = 2, 3) Input setup time1,5,6 Input hold time1,6 Active command to column command (same bank) 1 Precharge to Active command period1 Write recovery or data-in to precharge lead Active( a) to Active (b) command Transition time(rise and period1 fall)7 Refresh Period time1 tREF 120000 ns ns 5 ns ms 9, 10, 11 16 6.4 @ 105 °C 32 168 @ 85 °C 64 Memory CKE setup time for power down exit1 5.4 @ 70 °C 128 1. AC measurement assumes tT=1ns. Reference level for timing of input signals is 1.5V. 2. Access time is measured at 1.5V. 3. tLZ(min) definesthe time at which the outputs achieve the low impedance state. 4. tHZ(min) defines the time at which the outputs achieve the high impedance state. 5. tCES defines CKE setup time to CLK rising edge except for the power down exit command. 6. tAS/tAH: Address, tCS/tCH: /RAS, /CAS, /WE, DQM 7. Guarenteed by design (Not tested). 8. Guarenteed by Device Charactreization Testing. (Not 100% Tested) 08.25.15 Rev 6 All data sheets are subject to change without notice 5 ©2015 Maxwell Technologies All rights reserved. 97SD3240 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM TABLE 6. CAPACITANCE1 PARAMETER SYMBOL MAX UNIT Input Capacitance (CLK) CI1 17.5 pF Input Capacitance (all other inputs) CI2 19 pF CO 4 pF Output Capacitance (DQ) 1. Guarenteed by design. Memory 08.25.15 Rev 6 All data sheets are subject to change without notice 6 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Pin Functions: CLK (INPUT PIN): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS 1-5 (INPUT PINS): When CS 1-5 are low, the command input cycle becomes valid. When CS 1-5 are High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS AND WE (INPUT PINS): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. BA0/BA1 (INPUT PINS): BA0/BA1 are bank select signals (BS). The memory array of the 97SD3240 is divided into bank 0, bank 1, bank 2 and bank 3. The 97SD3240 contains 8192-row X 1024-column X 40-bit. If BA0 and BA1 is Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is High and BA1 is Low, bank 2 is selected. If BAO is High and BA1 is High, bank 3 is selected. CKE 1-5 (INPUT PIN): This pin determines whether or not the next CLK is valid. If CKE 1-5 is High, the next CLK rising edge is valid. If CKE 1-5 is Low, the next CLK rising edge is invalid. This pin is used for powerdown mode, clock suspend mode and self refresh mode1. DQM 1-5 (INPUT PINS): DQM 1-5 control input/output buffers Read operation: If DQM 1-5 are High, the output buffer becomes High-Z. If the DQM 1-5 are Low, the output buffer becomes Low-Z. ( The latency of DQM 1-5 during reading is 2 clock cycles.) Write operation: If DQM 1-5 are High, the previous data is held ( the new data is not written). If the DQM 1-5 areLow, the data is written. ( The latency of DQM 1-5 during writing is 0 clock cycles.) DQ0 TO DQ39 (DQ PINS): Data is input to and output from these pins ( DQ0 to DQ39). VCC AND VCCQ (POWER SUPPLY PINS): 3.3V is applied. ( VCC is for the internal circuit and VCCQ is for the output buffer.) VSS AND VSSQ (POWER SUPPLY PINS): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) 1. Self refresh mode should only be used at temperatures below 70°C. 08.25.15 Rev 6 All data sheets are subject to change without notice 7 ©2015 Maxwell Technologies All rights reserved. Memory A0 TO A12 (INPUT PINS): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BS) is pre charged. 97SD3240 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM Command Operation Command Truth Table The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins: SYMBOL N-1 N CS RAS CAS WE BA0/ BA1 A10 A0 TO A12 Ignore command DESL H x H x x x x x x No Operation NOP H x L H H H x x x Column Address and Read command READ H x L H L H V L V Read with auto-precharge READ A H x L H L H V H V Column Address and write command WRIT H x L H L L V L V Write with auto-precharge WRIT A H x L H L L V H V Row address strobe and bank active ACTV H x L L H H V V V Precharge select bank PRE H x L L H L V L x Precharge all banks PALL H x L L H L x H x Refresh REF/ SELF H L L L L H x x x Mode register set MRS H x L L L L V V V Memory COMMAND Note: H: VIH L: VIL x VIH or VIL V: Valid address input Ignore command (DESL): When this command is set (CS = High), the SDRAM ignores command input at the clock. However, the internal status is held. No Operation (NOP): This command is not an execution command. However, the internal operations continue. Column address strobe and read command (READ): This command starts a read operation. In addition, the start address of a burst read is determined by the column address (AY0 to AY9) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. Read with auto-precharge (READ A): This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4, or 8. 08.25.15 Rev 6 All data sheets are subject to change without notice 8 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Column address strobe and write command (WRIT): This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY9) and the bank select address (BA0/BA1) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY9) and bank select address(BA0/BA1). Write with auto-precharge (WRIT A): This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. Row address strobe and bank activate ( ACTV): This command activates the bank that is selected by BA0/BA1 (BS) and determines the row address (AX0 to AX12). When BA0 and BA1 are Low, bank 0 is activated. When BA0 is Low, and BA1 is High, bank 1 is activated. When BA0 is High and BA1 is Low, bank 2 is activated. When BA0 and BA1 are High, bank 3 is activated. Precharge select bank (PRE): This command starts precharge operation for the bank selected by BA0/ BA1. If BA0 and BA1 are Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is High and BA1 is Low, bank 2 is selected. If BA0 and BA1 are High, bank 3 is selected. Refresh (REF/SELF): This command starts the refresh operation. There are two types of refresh operations; one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set (MRS): The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A12, BA0 andBA1) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. 08.25.15 Rev 6 All data sheets are subject to change without notice 9 ©2015 Maxwell Technologies All rights reserved. Memory Precharge all banks (PALL): This command starts a precharge operation for all banks. 97SD3240 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM DQM Truth Table COMMAND Byte (DQ0 to DQ39) write enable/output enable Byte (DQ0 to DQ39) write inhibit/output disable SYMBOL CKE = N-1 CKE = N DQM ENB H x L MASK H x H Note: H: VIH L: VIL x VIH or VIL Write: IDID is Needed Read: IDOD is Needed The SDRAM can mask input/output data by means of DQM. During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other hand, when DQM is set High, the output buffer becomes High-Z, disabling data output. CKE Truth Table CURRENT STATE COMMAND N-1 N CS RAS CAS WE ADDRESS Active Clock suspended mode entry H L x x x x x Any Clock Suspend L L x x x x x Clock Suspend Clock Suspend mode exit L H x x x x x Idle Auto-refresh command (REF) H H L L L H x Idle Self-refresh entry (SELF) H L L L L H x H L L H H H x H L HL x x x x L H L H H H x L H L H H H x L H H x x x x Idle Power down entry Self Refresh Self Refresh exit (SELFX) Power down Power down exit Note: H:VIH L:VIL x VIH or VIL 08.25.15 Rev 6 All data sheets are subject to change without notice 10 ©2015 Maxwell Technologies All rights reserved. Memory During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held ( the new data is not written). Desired data can be masked during burst read or burst write by setting DQM.. For more details, refer to the DQM control section of the SDRAM operating instructions. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to Low. If a command is input in the clock suspend mode entry cycle, the command is valid. The clock suspend mode change depending on the current status (1 clock before) as described below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ with Auto-precharge suspend: The data being output is held ( and continues to be output). WRITE suspend and WRIT with Auto-precharge suspended: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. IDLE: In this state, all banks are not selected, and have completed precharge operation. Auto-refresh command (REF): When this command is input from the IDLE state, the SDRAM starts autorefresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 8192 cycles are required to refresh the entire memory contents. Before executing the auto-refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh. Self Refresh entry (SELF)1: When this command is input during the IDLE state, the SDRAM starts selfrefresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since selfrefresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the SDRAM enters power down mode. In power down mode, power consumption is suppresses by cutting off the initial input circuit. Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM can exit from selfrefresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state. Power down exit: When this command is executed at power down mode, the SDRAM can exit from power down mode. After exiting from power down mode, the SDRAM enters the IDLE state. 1. Self refresh mode should only be used at temperatures below 70°C. 08.25.15 Rev 6 All data sheets are subject to change without notice 11 ©2015 Maxwell Technologies All rights reserved. Memory Clock suspend mode exit: The SDRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. 97SD3240 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM Function Truth Table The following function table shows the operations that are performed when each command is issued in each mode of the SDRAM. The following table assumes that CKE is High. CS RAS CAS WE ADDRESS COMMAND OPERATION Precharge H x x x x DESL Enter IDLE after tRP L H H H x NOP Enter IDLE after tRP L H L H BA, CA, A10 READ/READ A ILLEGAL1 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL1 L L H H BA, RA ACTV ILLEGAL1 L L H L BA, A10 PRE, PALL NOP2 L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H x x x x DESL NOP L H H H x NOP NOP L H L H BA, CA, A10 READ/READ A ILLEGAL3 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL3 L L H H BA, RA ACTV Bank and row active L L H L BA, A10 PRE, PALL NOP L L L H x REF, SELF Refresh L L L L MODE MRS Mode register set H x x x x DESL NOP L H H H x NOP NOP L H L H BA, CA, A10 READ/READ A Begin read L H L L BA, CA, A10 WRIT/WRIT A Begin write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank4 L L H L BA, A10 PRE, PALL Precharge L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Idle Row active 08.25.15 Rev 6 All data sheets are subject to change without notice Memory CURRENT STATE 12 ©2015 Maxwell Technologies All rights reserved. 97SD3240 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM CS RAS CAS WE ADDRESS COMMAND OPERATION READ H x x x x DESL Continue burst to end L H H H x NOP Continue burst to end L H L H BA, CA, A10 READ/READ A Continue burst read to CAS latency and new read L H L L BA, CA, A10 WRIT/WRIT A Term burst read/start write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank4 L L H L BA, A10 PRE, PALL Term burst read and Precharge L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H x x x x DESL Continue burst to end and precharge L H H H x NOP Continue burst to end and precharge L H L H BA, CA, A10 READ/READ A ILLEGAL1 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL1 L L H H BA, RA ACTV Other bank active ILLEGAL on same bank4 L L H L BA, A10 PRE, PALL ILLEGAL1 L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H x x x x DESL Continue burst to end L H H H x NOP Continue burst to end L H L H BA, CA, A10 READ/READ A Term burst and new read L H L L BA, CA, A10 WRIT/WRIT A Term burst and new write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank4 L L H L BA, A10 PRE, PALL Term burst write and precharge5 L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Read with autoprecharge Write 08.25.15 Rev 6 All data sheets are subject to change without notice Memory CURRENT STATE 13 ©2015 Maxwell Technologies All rights reserved. 97SD3240 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM CS RAS CAS WE ADDRESS COMMAND OPERATION Write with autoprecharge H x x x x DESL Continue burst to end and precharge L H H H x NOP Continue burst to end and precharge L H L H BA, CA, A10 READ/READ A ILLEGAL1 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL1 L L H H BA, RA ACTV Other bank active ILLEGAL on same bank4 L L H L BA, A10 PRE, PALL ILLEGAL1 L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H x x x x DESL Enter IDLE after tRC L H H H x NOP Enter IDLE after tRC L H L H BA, CA, A10 READ/READ A ILLEGAL3 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL3 L L H H BA, RA ACTV ILLEGAL3 L L H L BA, A10 PRE, PALL ILLEGAL3 L L L H x REF, SELF ILLEGAL MODE MRS ILLEGAL Refresh ( autorefresh) L L L L 1. Illegal for same bank, except for another bank Memory CURRENT STATE 2. NOP for same bank, except for another bank 3. Illegal for all banks 4. If tRRD is not satisfied, this operation is illegal 5. An interval of tDPL is required between the final valid data input and the precharge command From PRECHARGE state, command operation To [DESL], [NOP]: When these commands are executed, the SDRAM enters the IDLE state after tRP has elapsed from the completion of precharge. From IDLE state, command operation To [DESL], [NOP], [PRE], or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh). To [MRS]: The synchronous DRAM enters the mode register set cycle. From ROW ACTIVE state, command operation To [DESL], [NOP]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) 08.25.15 Rev 6 All data sheets are subject to change without notice 14 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 To [ACTV]: This command makes the other bank active. ( However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of tRAS is required.) From READ state, command operation To [DESL], [NOP]: These commands continue read operations until the operation is completed. To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode. From WRITE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode. From WRITE with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM enters precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active result in an illegal command. From REFRESH state, command operation To [DESL], [NOP]: After an auto-refresh cycle (after tRC) the SDRAM automatically enters the IDLE state. 08.25.15 Rev 6 All data sheets are subject to change without notice 15 ©2015 Maxwell Technologies All rights reserved. Memory From READ with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM then enters precharge mode. To [ACTV]: This command makes other banks active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Simplified State Diagram Memory 08.25.15 Rev 6 All data sheets are subject to change without notice 16 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Mode Register Configuration The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. BA0, BA1, A11, A10, A12, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and burst write: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set. Memory A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. A2, A1, A0: (BL): These pins specify the burst length. 08.25.15 Rev 6 All data sheets are subject to change without notice 17 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Burst Sequence Memory 08.25.15 Rev 6 All data sheets are subject to change without notice 18 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Operation of the SDRAM The following section shows operation examples of 97SD3240. Note: The SDRAM should be used according to the product capability ( See Pin Description and AC Characteristics.) Read/Write Operations: Bank Active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. The output buffer becomes Low-Z in the (CAS latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. When the burst length is 1, 2, 4, or 8, the DOUT buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The CAS latency and burst length must be specified at the mode register. 08.25.15 Rev 6 All data sheets are subject to change without notice 19 ©2015 Maxwell Technologies All rights reserved. Memory The burst length can be set to 1, 2, 4, or 8. The start address for a burst read is specified by the column address and the bank select address (BA0/BA1) at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the CAS latency. The CAS latency can be set to 2 or 3. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 CAS Latency Memory Burst Length 08.25.15 Rev 6 All data sheets are subject to change without notice 20 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Write Operation: Burst write or single write mode is selected by the OPCODE (BA1, BA0, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4, or 8, like burst read operations. The write start address is specified by the column address and the bank select address (BA0/BA1) at the write command set cycle. Memory 2. Single write: A single write operation is enabled by setting OPCODE ( A9, A8) to (1, 0). In a single write operation, data is only written to the column address and the bank select address (BA0/BA1) specified by the write command set cycle without regard to the burst length setting. ( The latency of data input is 0 clock.) 08.25.15 Rev 6 All data sheets are subject to change without notice 21 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Auto Precharge Read with auto-precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by IARP is required before execution of the next command. CAS latency Precharge start cycle 3 2 cycles before the final data is output 2 1 cycle before the final data is output Burst Read (Burst Length = 4) Memory 08.25.15 Rev 6 All data sheets are subject to change without notice 22 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Write with auto-precharge: In this operation, since precharge is automatically preformed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of IAPW is required between the final valid data input and input of next command. Burst Write (Burst Length = 4) Memory Single Write 08.25.15 Rev 6 All data sheets are subject to change without notice 23 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Command Intervals READ command to READ command interval 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by second command will be valid. READ to READ Command Interval (Same ROW address in same bank) Memory 2. Same bank, different ROW address: When the ROW address changes on the same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval ( Different Bank) 08.25.15 Rev 6 All data sheets are subject to change without notice 24 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after as interval of no less than 1 clock. In the case of burst writes, the second write command has priority. Write to Write Command Interval (Same ROW address in same bank) 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. WRITE to WRITE Command Interval (Different bank) 08.25.15 Rev 6 All data sheets are subject to change without notice 25 ©2015 Maxwell Technologies All rights reserved. Memory 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Read command to Write command Interval: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High so the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1) Memory READ to WRITE Command Interval (2) 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, DQM must be set High so that the output buffer becomes High-Z before data input. 08.25.15 Rev 6 All data sheets are subject to change without notice 26 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Write command to READ command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed. WRITE to READ Command Interval (1) Memory Write to READ Command Interval (2) 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). 08.25.15 Rev 6 All data sheets are subject to change without notice 27 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Read with Auto Precharge to READ command interval 1. Different bank: When some banks are in the active state, the second read command ( another bank) is executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. The interval auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Read Command Interval (Different Bank) Memory 2. Same Bank: The consecutive read command (the same bank) is illegal. Write with Auto Precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts at the next clock of the second command. Write with Auto Precharge to Write Command Interval (Different bank) 08.25.15 Rev 6 All data sheets are subject to change without notice 28 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 2. Same bank: The consecutive write command ( the same bank) is illegal. Read with Auto Precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Write Command Interval (Different bank) Memory 2. Same bank: The consecutive write command from read with auto precharge ( the same bank) is illegal. It is necessary to separate the two commands with a bank active command. Write with Auto Precharege to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed. The internal auto precharge of one bank starts at the next clock of the second command. Write with Auto Precharge to Read command Interval (Different bank) 08.25.15 Rev 6 All data sheets are subject to change without notice 29 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Read command to Precharge command Interval (same bank) When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer than becomes High-Z after the clock defined by IHZP , there is a case of interruption to burst read data. Output will be interrupted if the precharge command is input during burst read. To read all data by burst read, the clocks defined by IEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE command Interval (same bank: To output all data) CAS Latency = 2, Burst Length = 4 CAS Latency = 3, Burst Length = 4 08.25.15 Rev 6 All data sheets are subject to change without notice 30 ©2015 Maxwell Technologies All rights reserved. Memory 2. Same Bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Recharge command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = 1, 2, 4, 8 Memory CAS Latency = 3, Burst Length = 1, 2, 4, 8 d to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the data must be masked by means of DQM for assurance of the clock defined by tDPL. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation) 08.25.15 Rev 6 All data sheets are subject to change without notice 31 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Memory Burst Length = 4 (To write to all data) Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than tRC. 2. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. 08.25.15 Rev 6 All data sheets are subject to change without notice 32 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Bank Active to Bank Active for Same Bank Bank Active to Bank Active for Different Bank Memory 08.25.15 Rev 6 All data sheets are subject to change without notice 33 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Mode register set to Bank-active interval: The interval between setting the mode register and executing a bank-active command must be no less than IRSA. Memory DQM Control The DQM mask the bytes of the DQ data. The timing of DQM is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z and the corresponding data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks. Writing: Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to High, the corresponding data is not written, and previous data is held. The latency of DQM during writing is 0 clock. Reading 08.25.15 Rev 6 All data sheets are subject to change without notice 34 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Writing Auto-Refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 8192 cycles/6.4 ms. (8192 cycles are requires to refresh all the ROW addresses.) The output buffer becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. Self-refresh1: After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute autorefresh to all refresh addresses in or within 6.4ms period on the condition (1) and (2) below. (1) Enter self-refresh mode within 7.8 us after either burst refresh or distributed refresh at equal interval until all refresh addresses are completed. (2) Start burst refresh or distributed refresh at equal interval to all refresh addreses within 7.8 us after exiting from self-refresh mode. Others Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power-down mode, power consumption is suppressed by deactivating the input initial circuit. Power-down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the 1. Self refresh mode should only be used at temperatures below 70°C. 08.25.15 Rev 6 All data sheets are subject to change without notice 35 ©2015 Maxwell Technologies All rights reserved. Memory Refresh 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 power-down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed. Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For more details, refer to the “CKE Truth Table”. Power-up sequence: The SDRAM should use the following sequence during power-up: The CLK, CKE, CS, DQM and DQ pins stay low until power stabilizes. The CLK pin is stable within 100ms after power stabilizes before the following initialization sequence. The CKE and DQM is driven high between when power stabilizes and the initialization sequence. This SDRAM has VCC clamp diodes for CLK, CKE, CS, DQM and DQ pins. If these pins go high before power up, the large current flows from these pins to VCC through the diodes. 08.25.15 Rev 6 All data sheets are subject to change without notice 36 ©2015 Maxwell Technologies All rights reserved. Memory Initialization sequence: When 200ms or more has past after the power up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS) to initialize the mode register. It is recommended that by keeping DQM and CKE High, the output buffer becomes High-Z during initialization sequence, to avoid DQ bus contention on a memory system formed with a number of devices. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Memory 132-LEAD QUAD RAD-STACK PACKAGE SYMBOL DIMENSION (INCHES) MIN NOM MAX A .385 .398 .411 b .006 .008 .010 c .005 .006 .008 D 1.337 1.350 1.363 D1 .795 .800 .805 e .025 S1 .266 F1 .997 1.000 1.003 L 2.485 2.500 2.505 L1 1.685 1.700 1.715 A1 .355 .368 .381 X 1.030 1.040 1.050 Y .965 .975 .985 Z .060 .065 .070 U 1.160 1.260 1.360 V 1.160 1.160 1.360 N 132 Note: All dimensions in inches. 08.25.15 Rev 6 All data sheets are subject to change without notice 37 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 Important Notice: These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Techoogies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 08.25.15 Rev 6 All data sheets are subject to change without notice 38 ©2015 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 97SD3240 PRODUCT ORDERING OPTIONS Model Number 97SD3240 RP Q X Option Details Feature MCM1 K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing @ -55°C, +25°C, +125°C) E = Engineering (testing @ +25°C) Package Q = Quad Flat Package Radiation Feature RP = RAD-PAK® package Base Product Nomenclature 1.25Gb(8-Meg X 40-Bit X 4Banks) SDRAM 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows. 08.25.15 Rev 6 All data sheets are subject to change without notice 39 ©2015 Maxwell Technologies All rights reserved. Memory Screening Flow