TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 D D D D D D D D D D D Supports Segmentation and Reassembly of AAL5 Packets in Accordance With ITU-T Specifications I.361 and I.363 (11/93 Update) Integrated 32-Bit PCI Bus 2.1 (06/95) Interface for Transferring Packet Data to and From Host Memory Provides Simultaneous Segmentation of up to 2048 Packets Provides Simultaneous Reassembly of up to 2048 Packets Provides Full VPI/VCI Support (12 VPI Bits and 16 VCI Bits) for Transmit and Receive Operations Supports Constant-Bit-Rate (CBR) Traffic via High-Priority Mechanism or Local Static Scheduler Table Backward Compatible With the TNETA1570 in 32-Bit PCI Mode Provides Support for Available-Bit-Rate (ABR) Traffic via External Coprocessor Interface (COPI) Provides Support for VBR-nrt Traffic via External COPI Transmit-Channel Sleep Mode Prevents the SAR Polling Channels When No Packets Are Queued High-Performance Features Include Use of Sideband Signals to Reduce Polling Across the PCI Bus D D D D D D D D D D D D D Host Accesses to the PHY-Layer Device Can Be Performed Indirectly via the TNETA1575 Local Peripheral Bus Local Peripheral Bus Maps the PHY Device Into the TNETA1575 PCI-Bus Address Space Supports Easy Access to AAL5 Trailer Information Supports Buffer Scatter/Gather (Transmit and Receive Buffer Chaining) Optional Early Segmentation of Packets, So Segmentation Begins Once a Transmit Buffer Is Filled, Instead of Waiting for the Entire Packet to Be Available in Host Memory Calculates the HEC Byte for the Header of an Outgoing Cell Checks the HEC Byte of an Incoming Cell UTOPIA Level 1-Compliant Cell Interface Internal 32-Cell Receive FIFO Cell Interface Can Be Programmed to Operate as Either a Physical (PHY-Layer) Interface or as a SAR/Switch (ATM-Layer) Interface Provides Reassembly Time Out for Incoming Packets Provides an Internal Loopback Capability From Transmit to Receive Supports Boundary Scan Through a Five-Wire JTAG Interface in Accordance With IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993) description The TNETA1575 is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with a peripheral component interconnect (PCI)-bus interface and a coprocessor interface (COPI). The TNETA1575 continues the line of Texas Instruments (TI) ATM SAR devices directed toward the classical LAN-to-ATM translation market segment. Features have been extended to include the COPI interface, which interfaces to an external scheduler with high-performance features to eliminate polling on the PCI bus. The TNETA1575 is designed for the emerging class of high-performance enterprise networking hubs that utilize ATM in the backplane, in addition to the traditional frame-/packet-based bus systems. Some of the features required for this application include: high level of virtual channel/virtual path support, support for isochronous services, early segmentation, and high-performance, 32-bit PCI-bus support. The feature set required by cell-operating enterprise hubs is different from the sets being offered by other SAR devices, which are directed primarily toward the adapter card market. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Thundercell and TI are trademarks of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 61 239 63 237 65 235 67 233 69 231 71 229 73 227 75 225 77 223 79 221 81 219 83 217 85 215 87 213 89 211 91 209 93 207 95 205 97 203 99 201 101 199 103 197 105 195 107 193 109 191 111 189 113 187 115 185 117 183 179 177 175 173 171 169 167 165 163 161 159 157 155 153 181 CMDATA3 GND CMDATA2 CMDATA1 CMDATA0 VCC(5V) GND LINTR RCCX TCCX VCC DAX GND COPFULL LRESET LBDATA0 LBDATA1 GND LBDATA2 VCC LBDATA3 LBDATA4 LBDATA5 LBDATA6 GND LBDATA7 LBREADY VCC(5V) LBCS2 LBR/W GND LBAD0 LBAD1 LBAD2 LBAD3 VCC LBAD4 GND LBAD5 LBAD6 LBAD7 LBAD8 GND LBAD9 VCC LBAD10 LBAD11 PSB6 GND PSB5 PSB4 PSB3 VCC PSB2 GND TXQUERDY SBLENGTH LBINTR VCC(5V) PAD0 PSERR PPAR PCBE1 GND PAD15 PAD14 PAD13 V CC PAD12 GND PAD11 PAD10 PAD9 PAD8 GND PCBE0 V CC PAD7 PAD6 PAD5 GND PAD4 PAD3 PAD2 V CC PAD1 GND 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 119 PAD29 GND PAD28 PAD27 VCC(5V) PAD26 PAD25 GND PAD24 PCBE3 PIDSEL V CC PAD23 PAD22 GND PAD21 PAD20 PAD19 PAD18 GND PAD17 PAD16 V CC PCBE2 PFRAME GND PIRDY PTRDY PDEVSEL PSTOP GND PPERR VCC(5V) CMSELHI CMBS1 CMBS2 ATMCLK2 VCC RESCLK RESEN VCC(5V) RESCLAV RESSOC RESPAR RESDATA7 RESDATA6 RESDATA5 RESDATA4 GND RESDATA3 RESDATA2 RESDATA1 RESDATA0 RESPERR ATMCLK1 PHY/ATM SEGDATA7 SEGDATA6 SEGDATA5 SEGDATA4 GND SEGDATA3 SEGDATA2 SEGDATA1 SEGDATA0 VCC SEGPAR SEGCLK SEGEN SEGSOC SEGCLAV LBCS1 VCC(5V) TESTMODE TRST TCK TMS TDO TDI GND HPSACK HPSREQ PSB1 PSB0 PINTA PRST PCLK VCC PGNT GND PREQ PAD31 PAD30 59 VCC CMSELLO CMAD15 CMAD14 GND CMAD13 CMAD12 CMAD11 CMAD10 CMAD9 CMAD8 VCC CMAD7 GND CMAD6 CMAD5 CMAD4 CMAD3 CMAD2 CMAD1 GND CMAD0 VCC CMWE CMOE CMDATA31 CMDATA30 CMDATA29 GND CMDATA28 CMDATA27 CMDATA26 VCC(5V) CMDATA25 CMDATA24 CMDATA23 GND CMDATA22 CMDATA21 CMDATA20 CMDATA19 CMDATA18 CMDATA17 VCC CMDATA16 GND CMDATA15 CMDATA14 CMDATA13 CMDATA12 CMDATA11 CMDATA10 GND CMDATA9 VCC CMDATA8 CMDATA7 CMDATA6 CMDATA5 CMDATA4 PGC PACKAGE (TOP VIEW) description (continued) The connection parameter cell-delay variation tolerance (CDVT) is not supported by the TNETA1575 scheduler on CBR connections. This data sheet provides information on the hardware specifications of the TNETA1575 device. The document contains information on the device interfaces, timing diagrams, electrical characteristics, terminal and package information, and an overview of the device operation. All the information on the TNETA1575 data structures, configuration, and features is provided in the TNETA1575 Programmer’s Reference Guide, literature number SDNU015. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 Terminal Functions PCI-bus interface TERMINAL I/O DESCRIPTION NAME NO. PAD31–PAD0 119–121, 123–124, 126–127, 129, 133–134, 136–139, 141–142, 158–160, 162, 164–167, 171–173, 175–177, 179, 181 I/O (3 state) PCBE3–PCBE0 130, 144, 156, 169 I/O (3 state) PCLK 114 I (TTL) PDEVSEL 149 I/O (3 state) PCI device select. When actively driven, PDEVSEL indicates that the address of the driving device is decoded as the target of the current access. As an input, PDEVSEL indicates whether any device on the bus is selected. PFRAME 145 I/O (3 state) PCI frame. PFRAME is driven by the current master to indicate the beginning and duration of an access. PFRAME is asserted at the beginning of the bus transaction and remains asserted during data transfer. When PFRAME is deasserted, the transaction is in the final data phase. PGNT 116 I (TTL) PCI-bus grant. PGNT indicates to the agent that the arbiter has granted access to the bus. PGNT is a point-to-point signal and every master has its own. PIDSEL 131 I (TTL) PCI initialization and device select. PIDSEL is used as a chip select during configuration read and write transactions. PINTA 112 O (open drain) PCI interrupt. PINTA is an interrupt request from PCI SAR. PINTA indicates to the host that a condition has occurred that may require attention. The TNETA1575 uses only a single interrupt line. I/O (3 state) PCI initiator ready. PIRDY indicates the initiating agent’s (bus master) ability to complete the current data phase of the transaction. During a write, PIRDY indicates valid data on PAD31–PAD0. During a read, PIRDY indicates the master is prepared to accept the data. PIRDY is used with PTRDY. Wait cycles are inserted until both PIRDY and PTRDY are asserted. PIRDY 147 PCI address bus and data bus. PAD31–PAD0 are multiplexed on the same PCI terminals. During the first phase of the address phase of a transaction, PAD31–PAD0 contain a 32-bit physical address. This phase is the clock cycle when PFRAME is asserted. During the data phase, PAD7–PAD0 contain the least-significant byte and PAD31–PAD24 contain the most-significant byte. Write data is stable when PIRDY is asserted. Read data is stable when PTRDY is asserted. Data is transferred during those clock cycles when both PIRDY and PTRDY are asserted. PCI-bus command and byte enable. PCBE3–PCBE0 lines are multiplexed on the same PCI terminals. During the address phase of a transaction, PCBE3–PCBE0 lines define the bus command. During the data phase, PCBE3–PCBE0 lines define which bytes are valid. PCI clock. PCLK provides timing for all transactions on the PCI interface. PPAR† 155 I/O (3 state) PCI parity. PPAR is even parity across PAD31–PAD0 and PCBE3–PCBE0. For data phases, PPAR is valid one clock after either PIRDY is asserted on a write or PTRDY is asserted on read Once asserted, asserted PPAR remains valid until one clock after the completion of the current a read. data phase. The master drives the PPAR for address- and write-data phases, and the target drives PPAR for the read-data phase. PPERR‡ 152 I/O (3 state) PCI parity error. PPERR reports a data-parity error on all commands except special cycle. An agent cannot report a PPERR until it has claimed the access by asserting PDEVSEL and completed a data phase. † If the host does not desire to implement parity in the system, terminal 155 is connected through a resistor to a valid logic level and the SERR enable bit in the PCI command register is set to 0. ‡ If the host does not desire to implement parity in the system, terminal 152 is connected through a 1-MΩ pullup resister and the SERR enable bit in the PCI command register is set to 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 Terminal Functions (Continued) PCI-bus interface (continued) TERMINAL I/O DESCRIPTION 118 O (CMOS) PCI request. PREQ indicates to the arbiter that this agent desires use of the bus. Every master has its own PREQ. 113 I (TTL) NAME NO. PREQ PRST PCI reset. PRST forces the PCI sequence of each device to a known state. PCI sideband. PSB1–PSB0 lines define the size of the transfer when the TNETA1575 is the bus master. The definitions of these signals are as follows: PSB1–PSB0 110–111 O (CMOS) 00: 01: 10: 11: 4-byte transfer 16-byte transfer (except for receive-completion ring) Payload transfer Transfer to receive-completion ring (20-byte transfer) ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PSB1–PSB0 are synchronous to the address phase of the bus-master operations by the TNETA1575. The sideband signals do not change upon a bus retry after disconnect. PSB2 PSB3 PSB4 PSB5 4 187 189 190 191 I (TTL) PCI sideband 2. PSB2 is an indication from the host to the SAR that the host has read an entry from the receive-completion ring without an interrupt. The SAR uses this signal to increment the receive-completion-ring entry counter. Pulse duration is for one clock cycle synchronous to the PCI clock. This input terminal has an internal 100-µA pulldown active terminator. This is a 3.3-V tolerant input signal. If it is driven by a 5-V signal, it must be connected to an external voltage divider consisting of a 36-kΩ down resistor and a 24-kΩ up resistor to ensure that the input is not driven above 3.3 V. O (CMOS) PCI sideband 3. PSB3 is an indication from the SAR to the host that the SAR is reading an entry from sideband-controlled free-buffer ring 1. PSB3 is synchronous to the address phase of bus-master operations by the SAR. PSB3 does not change upon a bus retry after disconnect. Pulse duration is for one clock cycle synchronous to the PCI-address phase. I (TTL) PCI sideband 4. PSB4 is an indication from the host to the SAR that the host has written a new entry into sideband-controlled free-buffer ring 1. The SAR uses this signal to increment the sideband-controlled free-buffer ring-1 entry counter. Pulse duration is for one clock cycle synchronous to the PCI clock. This input terminal has an internal 100-µA pulldown active terminator. This is a 3.3-V tolerant input signal. If it is driven by a 5-V signal, it must be connected to an external voltage divider consisting of a 36-kΩ down resistor and a 24-kΩ up resistor to ensure that the input is not driven above 3.3 V. O (CMOS) PCI sideband 5. PSB5 is an indication from the SAR to the host that the SAR is reading an entry from sideband-controlled free-buffer ring 2. PSB5 is synchronous to the address phase of bus-master operations by the SAR. PSB5 does not change upon a bus retry after disconnect. Pulse duration is for one clock cycle synchronous to the PCI-address phase. PSB6 193 I (TTL) PCI sideband 6. PSB6 is an indication from the host to the SAR that the host has written a new entry into sideband-controlled free-buffer ring 2. The SAR uses this signal to increment the sideband-controlled free-buffer ring-2 entry counter. Pulse duration is for one clock cycle synchronous to the PCI clock. This input terminal has an internal 100-µA pulldown active terminator. This is a 3.3-V tolerant input signal. If it is driven by a 5-V signal, it must be connected to an external voltage divider consisting of a 36-kΩ down resistor and a 24-kΩ up resistor to ensure that the input is not driven above 3.3 V. PSERR 154 I/O (open drain) PCI system error. PSERR reports address-parity errors and data-parity errors on special-cycle commands. PSTOP 150 I/O (3 state) PCI stop. PSTOP indicates that the current target is requesting the master to stop the current transaction. PTRDY 148 I/O (3 state) PCI target ready. PTRDY indicates the target agent’s (selected device) ability to complete the current data phase of the transaction. During a read, PTRDY indicates that valid data is present on PAD31–PAD0. During a write, PTRDY indicates that the target is prepared to accept data. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 Terminal Functions (Continued) PCI-bus interface (continued) ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL I/O DESCRIPTION 184 O (CMOS) Sideband length. SBLENGTH indicates to the host when the TNETA1575 is bursting eight free-buffer entries by asserting SBLENGTH high, or that it is bursting one entry when inactive low. Pulse duration is for one clock cycle synchronous to the PCI-address phase. 185 O (CMOS) Transmit queue ready. TXQUERDY indicates to the host when the transmit queue register is available for a write access by the host. TXQUERDY is a PCI-sideband signal and is synchronous with the PCI clock. NAME NO. SBLENGTH TXQUERDY cell-segmentation interface TERMINAL NAME NO. SEGCLAV 98 I/O DESCRIPTION Segmentation cell available O (CMOS) PHY mode SEGCLAV (RXEMPTY/RXCLAV) indicates that a complete cell is available. ATM mode SEGCLAV (TXENB) is active low when SEGDATA contains a valid byte. Segmentation clock SEGCLK 95 I (TTL) PHY mode SEGCLK (RXCLK) is used to synchronize transfers on SEGDATA. SEGCLK is sourced from the UTOPIA interface. ATM mode SEGCLK (TXCLK) is used to synchronize transfers on SEGDATA. SEGCLK is sourced from the ATMCLK. Segmentation data SEGDATA7– SEGDATA0 84–87, 89–92 O (CMOS) PHY mode SEGDATA7–SEGDATA0 (RXDATA) is byte-wide true data that is sourced by the TNETA1575. SEGDATA7 is the most significant bit. ATM mode SEGDATA7–SEGDATA0 (TXDATA) is byte-wide true data that is sourced by the TNETA1575. SEGDATA7 is the most significant bit. Segmentation enable SEGEN 96 I (TTL) PHY mode SEGEN (RXENB) indicates that a valid byte of SEGDATA will be sent during the next clock cycle. ATM mode SEGEN (TXFULL/TXCLAV) indicates that at least one byte of SEGDATA will be accepted. Segmentation parity SEGPAR 94 O (CMOS) PHY mode SEGPAR (RXPAR) is the odd-parity bit over SEGDATA7–SEGDATA0. ATM mode SEGPAR (TXPAR) is the odd-parity bit over SEGDATA7–SEGDATA0. Segmentation start of cell SEGSOC 97 O (CMOS) PHY mode SEGSOC (RXSOC) is active high when SEGDATA contains the first valid byte of the cell and is sourced by the TNETA1575. ATM mode SEGSOC (TXSOC) is active high when SEGDATA contains the first valid byte of the cell and is sourced by the TNETA1575. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 Terminal Functions (Continued) high-priority segmentation (request and acknowledge) TERMINAL NAME NO. HPSACK 108 HPSREQ 109 I/O DESCRIPTION O (CMOS) High-priority segmentation acknowledge. HPSACK is asserted for one PCI-bus clock cycle to acknowledge that HPSREQ is detected. I (TTL) High-priority segmentation request. HPSREQ is sampled at each new segmentation opportunity and is synchronous to the PCI-bus clock. When HPSREQ is active, TNETA1575 initiates the procedure for transmitting a cell from TX DMA channel 1. To ensure that the high-priority segmentation request is processed, HPSREQ remains active until HPSACK is set low. HPSREQ is deasserted within two PCI-bus clock cycles of when HPSACK is asserted. cell-reassembly interface TERMINAL NAME NO. I/O DESCRIPTION Reassembly cell available RESCLAV 69 O (CMOS) PHY mode RESCLAV (TXFULL/TXCLAV) indicates that a transfer of a complete cell can be accepted. ATM mode RESCLAV (RXENB) indicates that a valid byte RESDATA will be sent during the next clock cycle. Reassembly clock RESCLK 66 I (TTL) PHY mode RESCLK (TXCLK) is used to synchronize transfers on RESDATA. The UTOPIA interface is used as the source for RESCLK. ATM mode RESCLK (RXCLK) is used to synchronize transfers on RESDATA. ATMCLK is used as the source for RESCLK. Reassembly data RESDATA7– RESDATA7 RESDATA0 72–75, 72 75 77–80 I (TTL) PHY mode RESDATA7–RESDATA0 (TXDATA). RESDATA7 is the most significant bit. ATM mode RESDATA7–RESDATA0 (RXDATA). RESDATA7 is the most significant bit. Reassembly enable RESEN 67 I (TTL) PHY mode RESEN (TXENB) goes active low when RESDATA contains a valid byte. ATM mode RESEN (RXEMPTY/RXCLAV) indicates that transfer of a complete cell can be accepted. Reassembly parity RESPAR 71 I (TTL) PHY mode RESPAR (TXPAR) is the odd-parity bit over RESDATA7–RESDATA0. ATM mode RESPAR (RXPAR) is the odd-parity bit over RESDATA7–RESDATA0. Reassembly parity error (not required by UTOPIA) RESPERR 81 O (CMOS) PHY mode ATM mode RESPERR indicates that parityy error was present at the previous rising g edge g of RESCLK. Reassembly start of cell RESSOC 6 70 I (TTL) PHY mode RESSOC (TXSOC) is received when RESDATA contains the first valid byte of the cell. ATM mode RESSOC (RXSOC) is received when RESDATA contains the first valid byte of the cell. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 Terminal Functions (Continued) control-memory interface TERMINAL NAME NO. I/O DESCRIPTION 58–57, 55–50, 48, 46–41, 39 O (CMOS) Control-memory address. CMAD15–CMAD0 contain a 16-bit physical address to the control memory. CMBS1 62 O (CMOS) Control memory bank select 1. CMBS1 selects bank 1, containing 32K × 32 SRAM addresses in the lower 64K addresses, when active low. CMBS2 63 O (CMOS) Control memory bank select 2. CMBS2 selects bank 2, containing 32K × 32 SRAM addresses in the lower 64K addresses, when active low. 35–33, 31–29, 27–25, 23–18, 16, 14–9, 7, 5–1, 240, 238–236 I (TTL) O (CMOS) Control-memory data. CMDATA31–CMDATA0 contain 32-bit data to/from the control memory. ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CMAD15– CMAD0 CMDATA31– CMDATA0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CMOE 36 O (CMOS) Control-memory output enable. When CMOE is active low, the address is valid and data is read on the rising edge of CMOE. CMSELHI 61 O (CMOS) Control memory select high. CMSELHI selects the upper 64K control-memory addresses when active low. CMSELL0 59 O (CMOS) Control memory select low. CMSELL0 selects the lower 64K control-memory addresses when active low. CMWE 37 O (CMOS) Control-memory write enable. When CMWE is active low, the address and data are valid. traffic coprocessor interface ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL I/O DESCRIPTION 232 O (CMOS) Receive-cell status indication. RCCX indicates to the traffic coprocessor that a cell was received on the UTOPIA interface, and the RX DMA channel was assigned to the cell. TCCX 231 O (CMOS) Transmit-cell status indication. TCCX indicates to the traffic coprocessor that a cell was transmitted from the SAR, and the TX DMA channel was assigned to the cell. DAX 229 O (CMOS) Data availability indication. DAX indicates to the traffic coprocessor when data is available on a particular channel or when the SAR has completed segmentation of a packet. LRESET 226 O (CMOS) Local reset. LRESET provides a reset indication to the traffic coprocessor. LRESET is derived from the PCI-bus reset input. NAME NO. RCCX LINTR 233 I (TTL) Local interrupt. LINTR provides an interrupt indication from the traffic coprocessor to the SAR. When LINTR goes active low, the SAR sets a bit in the status register and generates a PCI interrupt unless the interrupt is masked through the interrupt mask register. This terminal has an internal 100-µA pullup active terminator. This signal must be connected to an external 2.2-kΩ pullup resistor that is connected to a 3.3-V voltage source. COPFULL 227 I (TTL) Coprocessor full. COPFULL indicates that the traffic coprocessor RX FIFO is about to fill up. A 100-µA pulldown active terminator is connected to this input. The pulldown is disabled when the COPPRES bit is set in the SAR configuration register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 Terminal Functions (Continued) local-bus interface ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL I/O DESCRIPTION 194–195, 197, 199–202, 204, 206–209 O (CMOS) Local-bus address. LBAD11–LBAD0 are driven by the TNETA1575 and are used to address the peripheral attached to the local bus. Terminal 194 is the most significant bit. LBR/W 211 O (CMOS) Local-bus read/write. LBR/W is an active-low signal that indicates a write operation and is driven by the TNETA1575. A read operation is indicated as active high. LBCS1 99 O (CMOS) Local-bus chip select 1. LBCS1 is an active-low signal that is used to select an external peripheral on the TNETA1575 local bus. LBCS2 212 O (CMOS) Local-bus chip select. 2 LBCS2 is an active-low signal that is used to select an external peripheral on the TNETA1575 local bus. 214 I (TTL) (with internal pullup) Local-bus ready. LBREADY is driven by a local-bus slave device. The TNETA1575 has two modes of operation on this input terminal. The default mode causes the TNETA1575 to complete the bus transaction after eight PCI-bus cycles, regardless of LBREADY. Alternatively, the TNETA1575 can be placed in a mode using LBREADY. This is a 3.3-V tolerant input signal. If it is driven by a 5-V signal, it must be connected to an external voltage divider consisting of a 36-kΩ down resistor and a 24-kΩ up resistor to ensure that the input is not driven above 3.3 V. 183 I (TTL) (with internal pullup) Local-bus interrupt. LBINTR is an active-low interrupt that is generated and driven by a local-bus device. This signal must be connected to an external 2.2-kΩ pullup resistor that is connected to a 3.3-V voltage source. 215, 217–220, 222, 224–225 I/O (TTL input / CMOS output) and (with internal pullup) Local-bus data. LBDATA7–LBDATA0 are used to transfer data to and from a local-bus slave device, and are driven by the TNETA1575 or a local-bus slave device. LBDATA7, (terminal 215) is the most significant bit. NAME NO. LBAD11– LBAD0 LBREADY LBINTR LBDATA7– LBDATA0 boundary-scan interface TERMINAL I/O DESCRIPTION NAME NO. TCK 103 I (TTL) Test clock. TCK clocks the test-access-port (TAP) operation. TDI 106 I (TTL) Test data input. TDI shifts serial-test data and instructions into the device during TAP operation. TDO 105 O (TTL) Test data output. TDO shifts serial-test data and instructions out of the device during TAP operation. TMS 104 I (TTL) Test-mode select. TMS controls the state of the TAP controller. TRST 102 I (TTL) Test reset. TRST asynchronously forces the TAP controller to a known state. This terminal must be tied low when the JTAG port is not being used. I/O DESCRIPTION I (TTL) Test mode. TESTMODE is used for device testing. High is for test mode and low is for normal operation. test signal TERMINAL 8 NAME NO. TESTMODE 101 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 Terminal Functions (Continued) miscellaneous signals TERMINAL NAME NO. I/O DESCRIPTION ATM clock1 ATMCLK1 82 PHY mode ATMCLK1 is driven low and can be left as a no connection (NC). ATM mode The ATMCLK1 is used as the clock source to provide for data transfers/ synchronization across the transmit UTOPIA interface between the SAR and external devices not connected to the PCI-host interface. The ATMCLK1 is connected to SEGCLK in the ATM mode. If the TNETA1585 is not used, the ATMCLK1 also can be used as the clock source for the receive UTOPIA interface. The clock generated by the interface is 33 MHz (nominal), using the PCI clock. O (CMOS) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ATMCLK2 64 O (CMOS) ATM clock2. ATMCLK2 is an auxiliary ATM clock that is used as the clock source to the TNETA1585 or a similar-type device. When the TNETA1585 is used, ATMCLK2 is also connected to the RESCLK input. The clock generated by the interface is 33 MHz (nominal), using the PCI clock. PHY/ATM 83 I (TTL) PHY/ATM mode select. PHY/ATM selects ATM mode when low and the PHY mode when high. power and ground TERMINAL DESCRIPTION NAME NO. GND 8, 15, 24, 32, 40, 47, 56, 76, 88, 107, 117, 122, 128, 135, 140, 146, 151, 157, 163, 168, 174, 180, 186, 192, 198, 203, 210, 216, 223, 228, 234, 239 Ground. GND is the 0-V reference for the device. VCC 6, 17, 38, 49, 60, 65, 93, 115, 132, 143, 161, 170, 178, 188, 196, 205, 221, 230 Supply voltage. VCC is the 3.3-V supply for the digital logic. VCC(5V) 28, 68, 100, 125, 153, 182, 213, 235 POST OFFICE BOX 655303 Supply voltage. VCC(5V) is the 5-V supply for the clamp diodes used with the 5-V tolerant input and output buffers for protection. • DALLAS, TEXAS 75265 9 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 detail description The TNETA1575 device contains the following interfaces: PCI-host interface Cell interface Local-bus interface Control-memory interface Traffic coprocessor interface JTAG interface PCI-host interface The TNETA1575 incorporates a PCI revision 2.1 host interface. The following section describes the features and operation of the PCI-host interface. The TNETA1575 operates as a PCI-slave device for configuration cycles, accesses to internal registers, and accesses to the onboard control memory. It also acts as a PCI-master device for accessing data structures, which are contained in host memory. As a slave, the TNETA1575 incorporates the following features: Directly supports the memory read, memory write, configuration read, and configuration write PCI commands and aliases the memory read multiple, memory read line, and memory write and invalidate to the basic memory commands. Supports single data-cycle transfers and disconnects with retry after the first data cycle. Does not retry single data accesses to any data structures accessed via the SAR, i.e., registers, control memory, or coprocessor. Responds to accesses as a 32-bit agent with medium DEVSEL timing (single wait state) Utilizes a 1-M block of addresses, which is mapped into the host memory space using a single base-address register. Does not support resource locking. As a master, the TNETA1575 incorporates the following features: Utilizes the memory read, memory read line, memory read multiple, and memory write PCI bus commands. Initiates transactions as a 32-bit agent. Performs multiple data-cycle transfers, when possible, up to a maximum of 12 data cycles. The TNETA1575 asserts the IRDY signal one clock cycle after the FRAME signal is asserted. IRDY remains asserted during the burst cycle. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 As described in the PCI local-bus specification rev 2.1, the TNETA1575 provides a 64-byte configuration space that can be accessed by system software for configuration, initialization, and error handling. The TNETA1575 responds to type 0 configuration accesses. ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ A configuration map of the 64-byte configuration space is as follows: ADDRESS BYTE 3 BYTE 2 BYTE 1 BYTE 0 READ/WRITE 0x00 Device ID Vendor ID R 0x04 Status Command R/W 0x08 0x0C Class Code BIST† Header Type 0x10 Latency Timer Revision ID R Cache Line Size R/W Base Address 0 Base Address 1† R/W Base Address 2† Base Address 3† R/W R/W 0x24 Base Address 4† Base Address 5† 0x28 Cardbus CIS Pointer† 0x14 0x18 0x1C 0x20 R/W R/W R/W R 0x30 Subsystem Vendor ID† Expansion ROM Base Address† 0x34 Reserved (returns 0 when read) — 0x38 Reserved (returns 0 when read) — 0x2C Subsystem ID† R/W R/W 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line R/W 0x40 Reserved Reserved Reserved Reserved R/W 0x44–0xFF Reserved (returns 0 when read) R † Optional registers are not implemented for the TNETA1575, which return 0 when read. The control memory is accessed via the host PCI interface in full 32-bit words. Byte enable is not supported. All four bytes in a 32-bit word in the control memory are read or written in a single instruction. If none of the byte enables are asserted for a write instruction, none of the data in the 32-bit word is altered. If any byte enable is asserted, then the entire 32-bit word is overwritten. cell interface The TNETA1575 transfers and receives ATM cells through the cell interface. The cell interface is designed in accordance with the ATM forum UTOPIA level 1 specification and is configurable as either an 8-bit PHY or ATM interface. The ATM mode is chosen when the TNETA1575 interfaces with a framer such as the TNETA1500. The PHY mode is chosen when the TNETA1575 interfaces with a switch port. The operation of this dual ATM/PHY interface requires the use of two external terminals – ATMCLK and PHY/ATM. The ATMCLK output is a buffered version of the PCI clock. When PHY/ATM is high (PHY mode), the segmentation interface functions as a PHY-RX port and the reassembly interface functions as a PHY-TX port. The clock speed supported by the interface is a maximum of 33 MHz. In this mode, the ATMCLK output normally is not used by the cell interface. When PHY/ATM is low (ATM mode), the segmentation interface functions as an ATM-TX port and the reassembly interface functions as an ATM-RX port. The clock speed supported by the interface is a maximum of 33 MHz. In this mode, the ATMCLK can be used as the clock source to provide for data transfers/synchronization or another external-clock source(s) can be used. The interface operates as a synchronous 8-bit (byte-wide) data path. The interface functions with both octet-level and cell-level handshaking. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 segmentation interface, PHY mode The segmentation-unit interface on the TNETA1575 operates as the RX UTOPIA interface on a PHY device when the TNETA1575 is operating in PHY mode. The PHY/ATM input terminal has to be high to operate in PHY mode. This cell interface works on the low-to-high transition of SEGCLK to sample and generate signals. All signals are active high, unless noted with a bar above the signal name. ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ TNETA1575 SIGNAL NAME TNETA1575 TERMINAL NUMBER UTOPIA SIGNAL NAME SEGCLK 95 RXCLK SEGDATA7–SEGDATA0 84–87, 89–92 RXDATA7–RXDATA0 SEGPAR 94 RXPRTY SEGSOC 97 RXSOC SEGEN 96 RXENB SEGCLAV 98 RXCLAV/RXEMPTY reassembly interface, PHY mode The reassembly-unit interface on the TNETA1575 functions as the TX UTOPIA interface in a PHY device when the TNETA1575 is operating in PHY mode. This reassembly-cell interface works on the low-to-high transition of RESCLK to sample and generate signals. All signals are active high, unless noted with a bar above the signal name. ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ TNETA1575 SIGNAL NAME 12 TNETA1575 TERMINAL NUMBER UTOPIA SIGNAL NAME RESCLK 66 TXCLK RESDATA7–RESDATA0 72–75, 77–80 TXDATA7–TXDATA0 RESPAR 71 TXPRTY RESSOC 70 TXSOC RESEN 67 TXENB RESCLAV 69 TXCLAV/TXFULL RESPERR 81 N/A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 connecting the TNETA1575 to the UTOPIA bus (See Figure 1 and Note A) TNETA1575 PHY mode Switch Port or Other PHY Layer Devices ATMCLK1 (82) ATMCLK2 (64) RESCLK (66) TXClk TXData RESDATA7–RESDATA0 (72–75, 77–80) TXSoc RESSOC (70) TXEnb RESEN (67) TXFull/TXClav TXPrty RESCLAV (69) RESPAR (71) RESPERR (81) RXClk SEGCLK (95) RXData SEGDATA7–SEGDATA0 (84–87, 89–92) RXSoc RXEnb RXEmpty/RXClav RXPrty SEGSOC (97) SEGEN (96) SEGCLAV (98) SEGPAR (94) PHY/ATM (83) UTOPIA Bus VCC CLOCK (26) TNETA1585 PHY mode RXCLK (24) TXData7–TXData0 RXDATA7–RXDATA0 (10, 12–13, 15–18, 20) TXSoc RXSOC (21) TXEnb RXEMPTY/RXCLAV (22) TXFull/TXClav RXEN (23) CONFIG(9) GND NOTE A: Figures 1 and 2 show the interconnections needed to interface to a TNETA1585 device. If the TNETA1575 is operated without the external scheduler device, then the lines going to the TNETA1585 are ignored, and everything remains as depicted above. Figure 1. UTOPIA Bus Connections In PHY Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 segmentation interface in ATM mode The segmentation-unit interface on the TNETA1575 operates as a TX UTOPIA interface in an ATM-layer device. The PHY/ATM terminal must be driven low to make the TNETA1575 operate in ATM mode. This cell interface works on the low-to-high transition of SEGCLK to sample and generate signals. All signals are active high, unless noted with a bar above the signal name. ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ TNETA1575 SIGNAL NAME TNETA1575 TERMINAL NUMBER UTOPIA SIGNAL NAME SEGCLK 95 TXCLK SEGDATA7–SEGDATA0 84–87, 89–92 TXDATA7–TXDATA0 SEGPAR 94 TXPRTY SEGSOC 97 TXSOC SEGEN 96 TXCLAV/TXFULL SEGCLAV 98 TXENB reassembly interface in ATM mode The reassembly-unit interface on the TNETA1575 operates as the RX UTOPIA interface in an ATM device when the TNETA1575 is configured in ATM mode. This receive cell interface works on the low-to-high transition of RESCLK to sample and generate signals. All signals are active high, unless noted with a bar above the signal name. ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ TNETA1575 SIGNAL NAME 14 TNETA1575 TERMINAL NUMBER UTOPIA SIGNAL NAME RESCLK 66 RXCLK RESDATA7–RESDATA0 72–75, 77–80 RXDATA7–RXDATA0 RESPAR 71 RXPRTY RESSOC 70 RXSOC RESEN 67 RXCLAV/RXEMPTY RESCLAV 69 RXENB RESPERR 81 N/A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 connecting the TNETA1575 to the UTOPIA bus (see Figure 2 and Note A) TNETA1575 ATM mode TNETA1500 (120) RCKI (92–95, 98–101) RD7–RD0 (117) RXCELL (118) RXFE (119) RRE (65) TCKI (68–71, 74–77) TD7–TD0 (63) TXCELL (61) TXAF (64) TWE ATMCLK1 (82) ATMCLK2 (64) RESCLK (66) RXClk RXData RESDATA7–RESDATA0 (72–75, 77–80) RXSoc RXClav/RXEmpty RESSOC (70) RESEN (67) RXEnb RESCLAV (69) RESPAR (71) RESPERR (81) TXClk SEGCLK (95) TXData SEGDATA(7–0) (84–87, 89–92) TXSoc TXFull/TXClav TXEnb SEGSOC (97) SEGEN (96) SEGCLAV (98) SEGPAR (94) PHY/ATM (83) UTOPIA Bus GND CLOCK (26) TNETA1585 ATM mode RXCLK (24) RXData7–RXData0 RXDATA7–RXDATA0 (10, 12–13, 15–18, 20) RXSoc RXSOC (21) RXClav/RXEmpty RXEMPTY/RXCLAV (22) RXEN (23) CONFIG (9) GND NOTE A: Figures 1 and 2 show the interconnections needed to interface to a TNETA1585 device. If the TNETA1575 is operated without the external scheduler device, then the lines going to the TNETA1585 are ignored, and everything remains as depicted above. Figure 2. UTOPIA Bus Connections in ATM Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 local-bus interface This interface allows access to the registers in two devices on the local bus. The TNETA1575 accepts a ready signal from devices on the bus as a handshake. This accommodates slow devices, and also can be used to relax timing constraints on the register interface for PHY-layer devices. The local bus is accessed exclusively via PCI-bus transactions with TNETA1575 as the slave, with the exception of the local-bus interrupt signal. The 12-bit address of the local bus comprises the PCI-bus address lines (bits 13–2). These directly drive the local-bus address bits (11–0). The signals in this interface are defined in the terminal-function table of this document. control-memory interface Control memory contains the local data structures and state information used by the device to transmit and receive data on a virtual connection (VC) or channel. The scheduler table, transmit active-packet counters, free-buffer ring-pointer table, and TX/RX DMA state table are located in control memory. The scheduler table contains 2,048 entries, consisting of one word each. The transmit active-packet counters contain the number of packets that have been queued for transmit on each packet segmentation ring. The free-buffer ring-pointer table contains the pointers to the receive free-buffer rings. There are 256 entries in the free-buffer ring-pointer table (one entry for each free-buffer ring), and each entry consists of two words. The TX/RX DMA state table contains 2,048 entries, one entry for each transmit-/receive-channel pair. Each entry consists of 16 words; eight words for the transmit operation and eight words for the receive operation. The definitions and functional description of the TNETA1575 data structures are discussed in detail in the TNETA1575 Programmer’s Reference Guide, literature number SDNU015. These local data structures are located off the chip in external SRAM. The TNETA1575 is designed to operate with 15-ns (or faster) asynchronous SRAM devices. The total SRAM requirement to support a full implementation of control memory is approximately 37K × 32. The device can operate with a control-memory SRAM of size 32K × 32. A system design with the 32K × 32 SRAM size only supports up to 1,792 TX/RX-channel pairs. To support the entire range of 2,048 TX/RX-channel pairs, the TNETA1575 requires a SRAM configuration of 64K × 32. The control-memory map for the TNETA1575 device follows: ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ control-memory map SIZE (IN 32-BIT WORDS) CONTROL-MEMORY ADDRESS (HEX) PCI-OFFSET ADDRESS (HEX) Scheduler table 2,048 00000–007FF 00000–01FFC Active packet counters 02000–02FFC MEMORY BLOCK 1,024 00800–00BFF Reserved 512 00C00–00DFF 03000–037FC Free-buffer ring pointer-table 512 00E00–00FFF 03800–03FFC TX/RX DMA state table DMA lookup table† 32,768 01000–08FFF 04000–23FFC 4,096 09000–09FFF 24000–27FFF Local-bus device 1 (LBCS1) 4,096 0A000–0AFFF 28000–2BFFC Local-bus device 2 (LBCS2) 4,096 0B000–0BFFF 2C000–2FFFC Reserved 16,384 0C000–0FFFF 30000–3FFFC Traffic coprocessor memory space 65,536 10000–1FFFF † The DMA lookup table is physically located on the chip and is not located off of the chip in the control memory. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 40000–7FFFC TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 control-memory interface (continued) The SAR control-memory port is used to select both the external SRAM that stores the local-data structures and state information for the TNETA1575 and an external device that can be used to provide an external scheduler and other transmit data structures. The total control-memory address space consists of 128K locations, with 64K locations dedicated to the TNETA1575 SRAM, and the remaining 64K dedicated to an external device such as an external scheduler (see Figure 3). Control SRAM 64K × 32 CMSELLO = low, CMSELHI = high External Device 64K × 32 CMSELLO = high, CMSELHI = low Figure 3. Control-Memory Address Space Control memory select bit CMSELHI is used to select the upper 64K-address space. CMSELHI is active low when the higher 64K addresses are selected, and inactive when the lower 64K addresses are selected. The control-memory select bit CMSELLO is used to select the lower 64K-address space. In addition, when the CMSELLO terminal is active low and the lower 64K addresses are selected, the user can select between a single 64K × 32 SRAM bank or two 32K × 32 SRAM banks. The two terminals CMSB1 and CMSB2 are active low and allow the user to select between the two banks, as follows: 1. CMSELLO is active low and CMA15 is low to select bank 1 (CMSB1 is enabled). 2. CMSELLO is active low and CMA15 is high to select bank 2 (CMSB2 is enabled). There are 16 control-memory address terminals that are used to address the various blocks of control memory. Together with the two select terminal (CMSELLO and CMSELHI) and the two bank operating terminals, these 20 terminals provide for a total of 128K addressable-memory locations. ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ CONTROL-MEMORY ADDRESS SPACE SELECTED (HEXADECIMAL) CMSELLO CMSB1 CMSB2 CMSELHI 00000–07FFF L L H H 08000–0FFFF L H L H 10000–1FFFF H H H L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 traffic coprocessor interface The TNETA1575 provides a traffic coprocessor interface (COPI) to add flexibility to the segmentation scheduling algorithm. The COPI is implemented using the control-memory interface and three unidirectional serial channels that transfer information from the TNETA1575 to the coprocessor and COPI-full indicator signal. The TNETA1575 acts as an initiator of all transfers to and from the coprocessor. The primary method of communication between the TNETA1575 and a coprocessor is via the control-memory interface. It is intended that an external coprocessor be mapped into the control-memory space, starting at address 10000 and extending to address 1FFFF. This equates to a total address space of 64K 32-bit words that is reserved for use by the coprocessor. The mapping of the coprocessor in control memory provides a means for the TNETA1575 to initialize the coprocessor, to obtain information related to the scheduling of cells, and to obtain RM cell contents. In this document, the three serial channels and the COPI-full indicator signal are described. received cell-indication channel A serial-bit interface allows the TNETA1575 to signal to the coprocessor that a cell has been received on a particular DMA channel. This interface is necessary to avoid duplicating the hardware that is used to resolve a VPI/VCI to a DMA channel. When a cell is received, the VPI/VCI value from the header is extracted and is used as a key in a lookup algorithm. When the lookup is complete, the TNETA1575 sends a 13-bit frame to the coprocessor, which is formatted as follows: ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ DMA NUMBER GOOD/BAD CELL INDICATOR FRAMING (12–2) (1) (0) The frame is transmitted to the coprocessor through the RCCX terminal, starting with bit 0. When a frame is not actively being transmitted, the RCCX terminal is driven to a 0. transmitted cell-indication channel A single-bit interface allows the TNETA1575 to signal to the coprocessor that a cell will be transmitted on a particular DMA channel. This interface is necessary to facilitate statistics processing in the coprocessor and to aid in ATM-forum available-bit-rate (ABR) scheduling. As soon as the TNETA1575 determines that it has the data to send a cell, it simultaneously sends an 18-bit frame to the coprocessor, which is formatted as follows: ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ DMA NUMBER CLP INDICATOR CELL TYPE SCHEDULING SOURCE SEND ACKNOWLEDGE FRAMING (17–7) (6) (5–3) (2) (1) (0) The frame is transmitted to the coprocessor through the TCCX terminal, starting with bit 0. When a frame is not actively being transmitted, the TCCX terminal is driven to a 0. data-availability channel A single-bit interface allows the TNETA1575 to signal to the coprocessor when data is available or unavailable on a particular channel. When the host writes to the transmit queue register to notify the TNETA1575 that a packet has been queued, or if the TNETA1575 completes segmentation of the last packet on a particular DMA channel, a 13-bit frame is sent to the coprocessor, which is formatted as follows: ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ DMA NUMBER DATA AVAILABLE/UNAVAILABLE FRAMING (12–2) (1) (0) The frame is transmitted to the coprocessor through the DAX terminal, starting with bit 0. When a frame is not actively being transmitted, the DAX terminal is driven to a 0. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 COP – interface full-indication signal The COPI interface on the TNETA1575 provides a COPFULL input terminal that indicates when the traffic coprocessor interface receive FIFOs are within one cell of filling up. The TNETA1575 reacts by deasserting the UTOPIA receive enable signal (RESCLAV or RXENABLE, depending on whether PHY or ATM mode is selected) according to the UTOPIA specification. After the COPFULL input terminal goes inactive low, the TNETA1575 asserts the UTOPIA receive enable signal RESCLAV or RXENABLE, depending on whether PHY or ATM mode is selected on the UTOPIA interface. If this terminal is not connected, the TNETA1575 operates under normal conditions. TNETA1575 / TNETA1585 interconnect PMAD15 PMWE SRAM 64K × 32 or 32K × 32 PMOE SRAM 64K × 32 or 32K × 32 ADDR Parameter Memory DATA Control Memory ADDRESS (15–0) SELLO Figure 4 shows the interconnect of the TNETA1575 (SAR) and the TNETA1585 traffic cop, including information on connection of the control-memory interface, the coprocessor interface, and the cell interfaces. DATA (31–0) ADDRESS (15–0) CTRL CMSELHI TNETA1575 TNETA1585 LRESET ADDR LINTR TCCX RCCX DAX 8 RESDATA (7–0) RESSOC RESCLAV RESCLK RESEN ATM CLK TXUTOPIA COPFULL Local Bus PCI Bus CMOE CMWE Figure 4. TNETA1575 Interconnect to TNETA1585 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 JTAG interface The TNETA1575 supports boundary scan through a five-wire JTAG interface in accordance with IEEE Std 1149.1–1990 (includes IEEE Std 1149.1a–1993), IEEE Standard Test Access Port and Boundary-Scan Architecture. The maximum operating frequency is 10 MHz for the JTAG interface. JTAG instruction set. The TNETA1575 supports the following instructions: ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ INSTRUCTION OP CODE (BINARY FORMAT) Extest 000 Idcode 100 Sample/Preload 001 Bypass 111 Internal Scan 010 High Z 101 idcode VARIANT PART NUMBER MANUFACTURER LEAST SIGNIFICANT BIT Bit number 31–28 27–12 11–1 0 Binary code 0000 00000010111 1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Supply voltage range, VCC(5V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Input voltage range, standard TTL, 3-V PCI, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input voltage range, 5-V tolerant TTL, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC(5V) + 0.5 V Output voltage range, standard TTL, 3-V PCI, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, 5-V tolerant TTL, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to VCC + 0.5 V Input clamp current, TTL, IIK (VI < 0 or VI > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the GND terminals. 2. Applies for external input and bidirectional buffers without hysteresis. VI > VCC does not apply to fail-safe terminals. Use VI > VCC(5V) for 5-V tolerant terminals. 3. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. Use VO > VCC(5V) for 5-V tolerant terminals. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 recommended operating conditions VCC VCC(5V) MIN NOM MAX Supply voltage Commercial 3 3.3 3.6 V Supply voltage, 5-V tolerant TTL Commercial 4.5 5 5.5 V VI Input voltage VO Output voltage VIH High-level input voltage TTL, 3-V PCI 0 VCC 5-V tolerant TTL 0 TTL, 3-V PCI 0 VCC(5V) VCC 5-V tolerant TTL† 0 TTL VIL 2 TTL 0 VCC VCC(5V) 0.8 Low-level input voltage 3-V PCI 0 0.325 VCC 5-V tolerant TTL 0 0.8 0 70 5-V tolerant TTL 2 TA Operating free-air temperature † VCC must be applied to drive the output to a high-impedance state (Z) for 5-V tolerant operation. V V VCC VCC 0.475 VCC 3-V PCI UNIT V V °C electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VOH High-level output voltage TEST CONDITIONS TTL IOH = 8 mA IOH = 4 mA VCC–0.6 06 5 V tolerant TTL 5-V IOH = 8 mA IOH = 4 mA VCC–0.6 06 3-V PCI IOH = 8.6 VCC (mA) IOL = 8 mA TTL VOL Low-level output voltage 5 V tolerant TTL 5-V 3-V PCI TTL IIH High-level input current IOL = 4 mA IOL = 8 mA Low-level input current High-impedance-state output current UNIT V 0.5 VCC 0.4 0.4 IOL = 4 mA IOL = 8 VCC (mA) V 0.4 0.3 VCC See Note 4 5-V tolerant TTL VI = VIH (max), VI = VIH (min) 3-V PCI VI = VIH (max), See Note 4 VI = VIL ((min)), See Note 5 ±1 –760 µA ±1 ±1 5-V tolerant TTL ±1 µA ±1 3-V PCI IOZ MAX 0.4 TTL IIL MIN TTL ±20 5-V tolerant TTL ±20 3-V PCI ±20 µA NOTES: 4. These specifications apply only when the pulldown terminator is turned off. 5. These specifications apply only when the pullup terminator is turned off. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 recommended power-supply sequencing for mixed-voltage devices The recommended power-supply sequencing in a mixed-voltage system is as follows: • • When turning on the power supply, all 3.3-V and 5-V supplies should start ramping from 0 V and reach 95 percent of their end-point values within a 25-ms time window. All bus contention between the TNETA1575 and external devices is eliminated by the end of the 25-ms time window. The preferred order of supply ramping is to ramp the 3.3-V supply, followed by the 5-V supply. This order is not mandatory, but it allows a larger cumulative number of power-supply on events than does the reverse order. When turning off the power supply, all 3.3-V and 5-V supplies should start ramping from steady-state values and reach 5 percent of these values within a 25-ms time window. All bus contention between the TNETA1575 and external devices is eliminated by the end of the 25-ms time window. The preferred order of supply ramping is to ramp down the 5-V supply, followed by the 3.3-V supply. This order is not mandatory, but it allows a larger cumulative number of power supply off events than the reverse order. If these precautions and guidelines are not followed, the TNETA1575 device may experience failures. timing requirements PCI-bus interface NO. MIN fclock(PCLK) Clock frequency, PCLK† tsu(BUS) Setup time, bused signals valid before PCLK↑ (see Note 6) tsu(PGNT) tsu(PREQ) NOM MAX 33 UNIT MHz 7 ns Setup time, PGNT low before PCLK↑ (see Note 6) 10 ns Setup time, PREQ low before PCLK↑ (see Note 6) 12 ns th(IN) Hold time, inputs valid after PCLK↑ 0 ns † The UTOPIA-clock (ATMCLK) frequency cannot be greater than three times the PCI-clock (PCLK) frequency or less than one-third the PCI-clock (PCLK) frequency because synchronization can break down on the FIFOs and cells can be lost. If this relationship is maintained between the PCLK clock and the ATMCLK clock, the PCLK clock can operate at or below 33 MHz and cells are not lost. NOTE 6: PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused. operating characteristics over recommended operating conditions PCI-bus interface NO. MIN MAX td(BUSV) Delay time, PCLK↑ to bused signals valid (see Note 6) PARAMETER 2 11 UNIT ns td(PGNT) Delay time, PCLK↑ to PGNT low (see Note 6) 2 12 ns td(PREQ) Delay time, PCLK↑ to PREQ low (see Note 6) 2 12 ns ton(FLT–ACT) Turn-on time, float to active 2 toff(ACT–FLT) Turn-off time, active to float ton(RST) Turn-on time, power stable to reset active 1 ms ton(PCLK–RST) Turn-on time, PCLK stable to reset active 100 µs ns 28 ns toff(RST–OF) Turn-off time, reset active to output float 40 ns NOTE 6. PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Figure 5) PCI-bus interface NO. MIN MAX UNIT 1 tw(PCLKH) Pulse duration, PCLK high 12 ns 2 tw(PCLKL) Pulse duration, PCLK low 12 ns 3 tsu(PGNT) Setup time, PGNT low before PCLK↑ 10 ns 4 tsu(PAD) Setup time, PAD31–PAD0 valid before PCLK↑ 7 ns 5 tsu(PTRDY) Setup time, PTRDY low before PCLK↑ 7 ns 6 tsu(PDEVSEL) Setup time, PDEVSEL low before PCLK↑ 7 ns 7 th(PAD) Hold time, PAD31–PAD0 valid after PCLK↑ 0 ns 8 th(PTRDY) Hold time, PTRDY low after PCLK↑ 0 ns 9† th(PDEVSEL) Hold time, PDEVSEL low after PCLK↑ 1 † This 1-ns minimum hold time deviates from the 0-ns minimum hold time specified in PCI-Local Bus Specification (Revision 2.1). ns operating characteristics (see Figure 5) PCI-bus interface NO. MIN MAX td(PFRAME) td(PAD) Delay time, PCLK↑ to PFRAME↓ 2 11 ns Delay time, PCLK↑ to PAD31–PAD0 valid 2 11 ns td(PCBE) td(PIRDY) Delay time, PCLK↑ to PCBE3–PCBE0 valid 2 11 ns 13 Delay time, PCLK↑ to PIRDY↓ 2 11 ns 14 td(PREQ) Delay time, PCLK↑ to PREQ↓ 2 12 ns 10 11 12 PARAMETER UNIT 1 PCLK (input) 2 PREQ (output) 3 14 PGNT (input) 4 PFRAME (output) PCBE3– PCBE0 (output) 7 11 PAD31– PAD0 (I/O) Address Data 1 Data 2 Data 3 BE No.S-2 BE No.S-3 Data 4 10 12 Bus Command BE No. S-1 BE No. S-4 13 PIRDY (output) 5 PTRDY (input) 8 9 6 PDEVSEL (input) Data Phase Address Phase Figure 5. Read Operation (PCI SAR as Master) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Figure 6) PCI-bus interface NO. MIN 1 tsu(PGNT) Setup time, PGNT low before PCLK↑ 2 tsu(PTRDY) 3 tsu(PDEVSEL) 4 th(PTRDY) MAX UNIT 10 ns Setup time, PTRDY low before PCLK↑ 7 ns Setup time, PDEVSEL low before PCLK↑ 7 ns Hold time, PTRDY low after PCLK↑ 0 ns 5† th(PDEVSEL) Hold time, PDEVSEL low after PCLK↑ 1 † This 1-ns minimum hold time deviates from the 0-ns minimum hold time specified in PCI-Local Bus Specification (Revision 2.1). ns operating characteristics (see Figure 6) PCI-bus interface NO. MIN MAX 6 td(PREQ) Delay time, PCLK↑ to PREQ↓ PARAMETER 2 12 ns 7 td(PFRAME) Delay time, PCLK↑ to PFRAME↓ 2 11 ns 8 td(PCBE) Delay time, PCLK↑ to PCBE valid 2 11 ns 9 td(PIRDY) Delay time, PCLK↑ to PIRDY↓ 2 11 ns 10 td(PAD) Delay time, PCLK↑ to PAD31–PAD0 valid 2 11 ns 11 td(PSB) Delay time, PCLK↑ to PSB1–PSB0 valid 2 11 ns PCLK (input) PREQ (output) PGNT (input) PAD31– PAD0 (output) 1 6 10 Address Data 1 Data 2 Data 3 Data 4 7 PFRAME (output) PCBE3– PCBE0 (output) 8 Bus Command BE No. S-1 BE No. S-2 BE No. S-3 BE No. S-4 9 PIRDY (output) 4 2 PTRDY (input) 5 3 PDEVSEL (input) Address Phase Data Phase 11 PSB1–PSB0 (output) Figure 6. Write Operation (PCI SAR as Master) 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Figure 7) PCI-bus interface NO. MIN MAX UNIT 1 tsu(PIDSEL) Setup time, PIDSEL high before PCLK↑ 7 ns 2 tsu(PAD) Setup time, PAD31–PAD0 valid before PCLK↑ 7 ns 3 tsu(PCBE) Setup time, PCBE3–PCBE0 valid before PCLK↑ 7 ns 4 tsu(PIRDY) Setup time, PIRDY low before PCLK↑ 7 ns 5† th(PIDSEL) Hold time, PIDSEL high after PCLK↑ 1 ns 6 th(PAD) Hold time, PAD31–PAD0 valid after PCLK↑ 0 ns 7† th(PCBE) Hold time, PCBE3–PCBE0 valid after PCLK↑ 1 ns 8† th(PIRDY) Hold time, PIRDY low after PCLK↑ 1 † This 1-ns minimum hold time deviates from the 0-ns minimum hold time specified in PCI-Local Bus Specification (Revision 2.1). ns operating characteristics (see Figure 7) PCI-bus interface NO. MIN MAX 9 td(PAD) Delay time, PCLK↑ to PAD31–PAD0 valid PARAMETER 2 11 ns 10 td(PTRDY) Delay time, PCLK↑ to PTRDY↓ 2 11 ns 11 td(PDEVSEL) Delay time, PCLK↑ to PDEVSEL↓ 2 11 ns PCLK (input) 1 5 PIDSEL (input) 2 PAD31– PAD0 (I/O) UNIT 9 6 Address Data PFRAME (input) PCBE3– PCBE0 (input) 3 7 Bus Cmd BE 4 8 PIRDY (input) 10 PTRDY (output) 11 PDEVSEL (output) Address Phase Data Phase Figure 7. Read Operation (PCI SAR as Slave) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Figure 8) PCI-bus interface NO. MIN MAX UNIT 1 tsu(PIDSEL) Setup time, PIDSEL high before PCLK↑ 7 ns 2 tsu(PAD) Setup time, PAD31–PAD0 valid before PCLK↑ 7 ns 3 tsu(PFRAME) Setup time, PFRAME low before PCLK↑ 7 ns 4 tsu(PIRDY) Setup time, PIRDY low before PCLK↑ 7 ns 5† th(PIDSEL) Hold time, PIDSEL high after PCLK↑ 1 ns 6† th(PIRDY) Hold time, PIRDY low after PCLK↑ 1 † This 1-ns minimum hold time deviates from the 0-ns minimum hold time specified in PCI-Local Bus Specification (Revision 2.1). ns operating characteristics (see Figure 8) PCI-bus interface NO. 7 PARAMETER td(PTRDY) Delay time, PCLK↑ to PTRDY↓ MIN MAX 2 11 1 PCLK (input) 5 PIDSEL (input) 2 PAD31– PAD0 (I/O) Address Data 3 PFRAME (input) PCBE3– PCBE0 (input) Bus Cmd BE 4 6 PIRDY (input) 7 PTRDY (output) PDEVSEL (output) Address Phase Figure 8. Write Operation (PCI SAR as Slave) 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 operating characteristics (see Figure 9) PCI sideband NO. MIN MAX 1 td(PAD) Delay time, PCLK high to PAD31–PAD0 valid PARAMETER 2 11 UNIT ns 2 td(PSB) Delay time, PCLK high to PSB1–PSB0 valid 2 11 ns PCLK (input) PREQ (output) PGNT (input) 1 PAD31–PAD0) (I/O) ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Address Data1 Data2 Data3 Data4 2 PSB1–PSB0) (outputs) PFRAME (I/O) PIRDY (I/O) PTRDY (I/O) PDEVSEL (I/O) Address Phase Data Phase Figure 9. Master Write Operation and PCI-Sideband (PSB1–PSB0 Signals) Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Figure 10) PCI sideband NO. MIN MAX 1 td(PAD) Delay time, PCLK high to PAD31–PAD0 valid 2 11 2 tsu(PSB2) Setup time, PSB2 high before PCLK↑ 7 ns 2 tsu(PSB4) Setup time, PSB4 high before PCLK↑ 7 ns 2 tsu(PSB6) Setup time, PSB6 high before PCLK↑ 7 ns 3† th(PSB2) Hold time, PSB2 high after PCLK↑ 1 ns 3† th(PSB4) Hold time, PSB4 high after PCLK↑ 1 ns 3† th(PSB6) Hold time, PSB6 high after PCLK↑ 1 † This 1-ns minimum hold time deviates from the 0-ns minimum hold time specified in PCI-Local Bus Specification (Revision 2.1). PCLK (input) PREQ (output) PGNT (input) 1 PAD31–PAD0 (I/O) Address 2 Data1 Data2 Data3 Data4 3 PSB2, PSB4, PSB6 (inputs) PFRAME (I/O) PIRDY (I/O) PTRDY (I/O) PDEVSEL (I/O) Address Phase Data Phase Figure 10. Master Write Operation and PCI Sideband (PSB2, PSB4,and PSB6 Signals) Timing 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 operating characteristics (see Figure 11) PCI bus (TXQUERDY) NO. 1 PARAMETER td(TXQUERDY) MIN Delay time, PCLK high to TXQUERDY inactive MAX 15 UNIT ns PCLK (input) PIDSEL (input) PAD31–PAD0 (I/O) Address Data1 1 TXQUERDY (output) PFRAME (I/O) PIRDY (I/O) PTRDY (I/O) PDEVSEL (I/O) Figure 11. Write Operation to the TXQUERDY Register and Timing (TXQUERDY Going Inactive) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 operating characteristics (see Figure 12) control-memory interface – write operation NO. MIN MAX 1 td(CMAD) Delay time, from PCLK↑ to CMAD15–CMAD0 valid PARAMETER 2 15 UNIT ns 2 td(CMDATA) Delay time, from PCLK↑ to CMDATA31–CMDATA0 valid 5 15 ns 3 td(CMOE) Delay time, from PCLK↑ to CMOE↑ 5 15 ns 4 td(CMWE)1 Delay time, from PCLK↓ to CMWE↓ 5 15 ns 5 td(CMWE)2 Delay time, from PCLK↓ to CMWE↑ 5 15 ns PCLK (input) ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ Ï ÏÏ Ï ÏÏ Ï ÏÏÏÏÏÏÏÏÏ ÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏ 1 CMAD15CMAD0 (output) Valid 2 CMDATA31CMDATA0 (output) Valid 3 CMOE (output) 4 5 CMWE (output) Figure 12. Control-Memory Interface – Write Operation 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 operating characteristics (see Figure 13) control-memory interface (write operation) data bus enable and disable times NO. MIN MAX 1 ten(PH-CE) Enable time, from PCLK↑ to CMDATA31–CMDATA0 enabled PARAMETER 5 10 ns 2 tdis(PH-CZ) Disable time, from PCLK↑ to CMDATA31–CMDATA0 disabled (Z state) 6 11 ns PCLK (input) CMAD15CMAD0 (output) ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏ ÏÏ ÏÏ ÏÏ 1 CMDATA31CMDATA0 (output) Z UNIT 2 Valid Z CMOE (output) CMWE (output) Figure 13. Control-Memory Interface (Write Operation) – Data Bus Enable and Disable Times POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Figure 14) control-memory interface – read operation NO. MIN MAX UNIT 1 tsu(CMDATA) Setup time, CMDATA31–CMDATA0 valid before PCLK↑ 3 ns 2 th(CMDATA) Hold time, CMDATA31–CMDATA0 valid after PCLK↑ 3 ns operating characteristics (see Figure 14) control-memory interface read operation NO. PARAMETER MAX UNIT 3 td(CMAD) Delay time, from PCLK↑ to CMAD15–CMAD0 valid 5 15 ns 4 td(CMOE) Delay time, from PCLK↑ to CMOE↓ 8 15 ns PCLK (input) CMDATA31CMDATA0 (input) ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ 1 Valid ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 2 3 CMAD15CMAD0 (output) Valid 4 CMOE (output) CMWE (output) H Figure 14. Control-Memory Interface – Read Operation 32 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 operating characteristics (see Figure 15 ) traffic coprocessor interface outputs NO. PARAMETER MIN MAX 1 td(RCCX) Delay time, ATMCLK1↑ to RCCX valid 2 11 ns 2 td(TCCX) Delay time, ATMCLK1↑ to TCCX valid 2 11 ns 3 td(DAX) Delay time, ATMCLK1↑ to DAX valid 2 11 ns ATMCLK1 (output) UNIT ... 2 RCCX (output) DMA Number (11 Bits) Frame GCI 2 TCCX (output) Send Frame ACK Sch. Source Cell Type (3 Bits) CLP ... DMA Number (11 Bits) 3 DAX (output) DMA Number (11 Bits) Frame DAV Figure 15. Traffic Coprocessor Interface Outputs operating characteristics (see Figure 16 ) ATMCLK1/ATMCLK2 clock timing NO. MIN MAX 1 td(ATMCLK1) Delay time, PCLK↑ to ATMCLK1↑ PARAMETER 3 7 ns 2 td(ATMCLK2) Delay time, PCLK↑ to ATMCLK2↑ 3 7 ns 1 UNIT 2 PCLK (input) ATMCLK1 (output) ATMCLK2 (output) Figure 16. ATMCLK1/ATMCLK2 Clock Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Figure 17) traffic coprocessor interface inputs NO. MIN UNIT tsu(COPFULL) Setup time, COPFULL high before RESCLK↑ 4 ns 2 th(COPFULL) Hold time, COPFULL high after RESCLK↑ 1 ns RESCLK (input) ... 1 COPFULL (input) Figure 17. Traffic Coprocessor Interface Inputs 34 MAX 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Note 7 and Figure 18) UTOPIA interface NO. MIN MAX UNIT fclock(ACLK) Clock frequency, ATMCLK† 1 tw(SEGCLKH) Pulse duration, SEGCLK high 12 ns 2 tw(SEGCLKL) Pulse duration, SEGCLK low 12 ns 3 tsu(SEGEN) Setup time, SEGEN low before SEGCLK↑ 10 ns 0.33 fclock(PCLK) 3 fclock(PCLK) MHz 4 th(SEGEN) Hold time, SEGEN low after SEGCLK↑ 1 ns † The UTOPIA-clock (ATMCLK) frequency cannot be greater than three times the PCI-clock (PCLK) frequency or less than one-third the PCI-clock (PCLK) frequency because synchronization can break down on the FIFOs and cells can be lost. If this relationship is maintained between the PCLK clock and the ATMCLK clock, the PCLK clock can operate at or below 33 MHz and cells are not lost. NOTE 7: All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK. operating characteristics (see Note 7 and Figure 18) UTOPIA interface NO. MIN MAX 5 td(SEGCLAV) Delay time, SEGCLK↑ to SEGCLAV↓ PARAMETER 1 20 UNIT ns 6 td(SEGSOC) Delay time, SEGCLK↑ to SEGSOC↑ 1 20 ns 7 td(SEGDATA) Delay time, SEGCLK↑ to SEGDATA7–SEGDATA0 valid 1 20 ns 8 td(SEGPAR) Delay time, SEGCLK↑ to SEGPAR valid 1 20 ns NOTE 7. All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK. 1 2 SEGCLK (input) 5 SEGCLAV (output) 6 SEGSOC (output) 7 SEGDATA7– SEGDATA0 (output) SEGEN (input) Byte 1 Byte 2 Byte 3 Byte 48 Input Ignored Byte 49 Byte 50 Byte 51 4 3 8 SEGPAR (output) Figure 18. Segmentation-Cell Interface (PHY/ATM Low) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Note 7 and Figure 19) UTOPIA interface NO. MIN MAX UNIT 1 tw(SEGCLKH) Pulse duration, SEGCLK high 12 ns 2 tw(SEGCLKL) Pulse duration, SEGCLK low 12 ns 3 tsu(SEGEN) Setup time, SEGEN high before SEGCLK↑ 10 ns 4 th(SEGEN) Hold time, SEGEN high after SEGCLK↑ 1 ns NOTE 7. All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK. operating characteristics (see Note 7 and Figure 19) UTOPIA interface NO. PARAMETER MIN MAX 5 td(SEGSOC) Delay time, SEGCLK↑ to SEGSOC↑ 1 20 ns 6 td(SEGDATA) Delay time, SEGCLK↑ to SEGDATA7–SEGDATA0 valid 1 20 ns 7 td(SEGPAR) Delay time, SEGCLK↑ to SEGPAR↑ 1 20 ns 8 td(SEGCLAV)1 Delay time, SEGCLK↑ to SEGCLAV↑ 1 20 ns 9 td(SEGCLAV)2 Delay time, SEGCLK↑ to SEGCLAV↓ 1 20 ns NOTE 7. All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK. 1 2 SEGCLK (input) 3 4 SEGEN (input) 5 SEGSOC (output) SEGDATA7– SEGDATA0 (output) Byte 53 9 ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ 6 Byte 1 Byte 2 Byte 3 Byte 4 8 SEGCLAV (output) 7 If necessary SEGPAR (output) Figure 19. Segmentation-Cell Interface (PHY/ATM High) 36 UNIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Byte 5 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Note 8 and Figure 20) UTOPIA interface NO. MIN MAX UNIT 1 tw(RESCLKH) Pulse duration, RESCLK high 12 ns 2 tw(RESCLKL) Pulse duration, RESCLK low 12 ns 3 tsu(RESSOC) Setup time, RESSOC high before RESCLK↑ 10 ns 4 tsu(RESEN) Setup time, RESEN low before RESCLK↑ 10 ns 5 tsu(RESDATA) Setup time, RESDATA7–RESDATA0 valid before RESCLK↑ 10 ns 6 tsu(RESPAR) Setup time, RESPAR valid before RESCLK↑ 10 ns 7 th(RESSOC) Hold time, RESSOC high after RESCLK↑ 1 ns 8 th(RESEN) Hold time, RESEN low after RESCLK↑ 1 ns NOTE 8: All output signals are generated on the rising edge of RESCLK. operating characteristics (see Note 8 and Figure 20) UTOPIA interface NO. PARAMETER MIN MAX 9 td(RESCLAV) Delay time, RESCLK ↑ to RESCLAV↑ 1 20 UNIT ns 10 td(RESPERR)1 Delay time, RESCLK ↑ to RESPERR↓ 1 20 ns 11 td(RESPERR)2 Delay time, RESCLK ↑ to RESPERR↑ 1 20 ns NOTE 8. All output signals are generated on the rising edge of RESCLK. 1 2 RESCLK (input) 9 RESCLAV (output) 3 RESSOC (input) RESDATA7– RESDATA0 (input) ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Byte 53 4 RESEN (input) RESPAR (input) 7 5 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 8 6 Parity Error No Parity Error 10 RESPERR (output) 11 Figure 20. Reassembly-Cell Interface – PHY/ATM Low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 timing requirements (see Note 9 and Figure 21) UTOPIA interface NO. 1 2 3 4 5 6 7 8 9 10 MIN MAX UNIT tw(RESCLKH) tw(RESCLKL) Pulse duration, RESCLK high 12 ns Pulse duration, RESCLK low 12 ns tsu(RESEN) tsu(RESSOC) Setup time, RESEN high before RESCLK↑ 10 ns Setup time, RESSOC high before RESCLK↑ 10 ns tsu(RESDATA) tsu(RESPAR) Setup time, RESDATA7–RESDATA0 valid before RESCLK↑ 10 ns Setup time, RESPAR valid before RESCLK↑ 10 ns th(RESEN) th(RESSOC) Hold time, RESEN high after RESCLK↑ 1 ns Hold time, RESSOC high after RESCLK↑ 1 ns th(RESDATA) th(RESPAR) Hold time, RESDATA7–RESDATA0 valid after RESCLK↑ 1 ns Hold time, RESPAR valid after RESCLK↑ 1 ns NOTE 9: All output signals are generated on the rising edge of RESCLK. All input signals are sampled on the rising edge of RESCLK. operating characteristics (see Note 9 and Figure 21) UTOPIA interface NO. 11 12 PARAMETER td(RESCLAV) td(RESPERR)1 MIN MAX Delay time, RESCLK↑ to RESCLAV↓ 1 20 ns Delay time, RESCLK↑ to RESPERR↓ 1 20 ns 13 UNIT td(RESPERR)2 Delay time, RESCLK↑ to RESPERR↑ 1 20 ns NOTE 9. All output signals are generated on the rising edge of RESCLK. All input signals are sampled on the rising edge of RESCLK. 1 2 RESCLK (input) 3 7 RESEN (input) 4 8 5 9 RESSOC (input) RESDATA7– RESDATA0 (input) Byte 1 Byte 2 Byte 3 Byte 48 Byte 49 11 Input Ignored If necessary RESCLAV (output) 6 RESPAR (input) 10 Parity Error No Parity Error 12 13 RESPERR (output) Figure 21. Reassembly-Cell Interface – PHY/ATM High 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Byte 50 Byte 51 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 operating characteristics (see Note 10 and Figure 22) local-bus interface – read operation NO. PARAMETER 1 td(LBCS1)1 Delay time, LBR/W↑ to LBCS1↓ 2 td(LBREADY) Delay time, LBREADY↓ to LBCS1↑ MIN MAX 57 67 UNIT ns 115 125 ns NOTE 10: If LBREADY does not go low within eight PCI-clock cycles after LBCS1 goes active low, TNETA1575 latches in the data of the LBDATA7–LBDATA0 bus and terminates the read operation. PCLK (input) LBR/W (output) LBAD11–LBAD0 (output) LBDATA7–LBDATA0 (input) LBREADY (input) ÏÏÏ ÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ 1 2 LBCS1 (output) Figure 22. Local-Bus Interface – Read Operation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 operating characteristics (see Note 11 and Figure 23) local-bus interface – write operation NO. PARAMETER 1 td(LBCS1)1 Delay time, LBR/W↓ to LBCS1↓ 2 td(LBCS1)2 Delay time, LBAD11–LBAD0 valid to LBCS1↓ 3 td(LBCS1)3 Delay time, LBDATA7–LBDATA0 valid to LBCS1↓ 4 td(LBAD) Delay time, LBCS1↑ to LBAD11–LBAD0 invalid MIN MAX 57 67 UNIT ns 145 155 ns 57 67 ns 265 275 ns NOTE 11: The LBCS1 is asserted low for eight PCI-clock cycles during a write operation to allow access to slow devices. PCLK (input) LBR/W (output) ÏÏÏ ÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏ ÏÏ ÏÏÏÏ ÏÏÏÏ LBAD11–LBAD0 (output) LBDATA7–LBDATA0 (output) 3 4 1 2 LBCS1 (output) Figure 23. Local-Bus Interface – Write Operation 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 APPLICATIONS INFORMATION introduction The TNETA1575 implements a range of features targeted for cell-operating enterprise hubs. The growth in acceptance of ATM in the backbone transfers quickly to the backplane (the collapsed backbone). The TNETA1575 also is suited for lower-cost applications such as stackable hubs. The growth in acceptance of ATM in the backbone can lead to an increase in demand for ATM connectivity in the installed base of stackable classical-LAN operating products. To support these applications, a different SAR architecture is required that includes the following characteristics: • • • • • • • • Cell interface that can go beyond 155-Mbit/s transfer rates. This increases the number of front-end legacy interfaces that can be supported by a single SAR device. Direct support for constant-bit-rate (CBR) traffic via a dedicated input, a scheduling mechanism and priority-queue scheme make isochronous services available to enterprise hubs and to stackable hubs. The connection parameter cell-delay variation tolerance (CDVT) is not supported by the TNETA1575 scheduler. Support for the full range of virtual paths and virtual channels, and 2K-ABR channels that are required to enable the deployment of large and scaleable virtual LANs Support for an internal scheduler. The COPI is used to interface to an external scheduler, which would provide support for all the ATM classes of service. High-performance features. On the transmit side, these include the transmit-channel sleep mode, which prevents polling of transmit channels with no data queued. On the receive side, these include features that utilize PCI-bus sideband signals to eliminate polling across the PCI bus completely. Early segmentation. This is very important to systems that require reduced latency (isochronous hubs). Early segmentation enables multimedia applications to take full advantage of ATM facilities. Support for the full range of virtual paths and virtual channels. This is a requirement for the collapsed backbones that are a part of virtual LANs, and the feature offers support for multimedia applications. An option to program the UTOPIA-cell interface as either a PHY or ATM-layer system. This option provides the TNETA1575 a capability to function as a PHY where the cell switch is distributed or as an ATM-layer interface for adapter cards or ATM uplinks. system-level overview The TNETA1575 and the TNETA1585 provide a flexible, high-performance solution that implements the ATM forum’s available-bit-rate (ABR) service category, as specified in the ATM-forum traffic management 4.0 interoperability specification. A summary of these two devices follows: TNETA1575 HyperSAR-PLUS The TNETA1575 is a SAR engine based on TI’s TNETA1570 architecture. Its primary interfaces are: • • • • • 32-bit PCI for host transfers UTOPIA for cell transfers COPI for traffic-COP flow-control management Control memory for status information Local-bus interface for accessing the PHY device via the SAR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 APPLICATIONS INFORMATION system-level overview (continued) The TNETA1575 has the following internal FIFO capabilities: • • A transmit FIFO for internal interfacing between the segmentation engine and the cell transmit block. The TX FIFO holds four cells. A receive FIFO for internal interfacing between the reassembly engine and the cell receive block. The RX FIFO holds 32 cells. TNETA1585 traffic coprocessor† The TNETA1585 is an ABR scheduler that conforms to the ATM-forum’s interoperability specifications. Other than scheduling cells, the primary function is to handle the processing of resource management (RM) cells in both the transmit and receive directions. A system-level interconnect of the chip set, with associated systems, is shown in Figure 24. Control Memory Control Memory Interface PCI Bus Interface Host Controller Parameter Memory Interface ThunderCELLt TNETA1575 Local Bus ThunderCELLt COPI Interface TNETA1585 UTOPIA Interface ThunderCELLt PCI Memory Controller Parameter Memory Fiber/Copper Transceiver TNETA1500 32-Bit PCI Figure 24. System-Level Chip Set (TNETA1575, TNETA1585, and TNETA1500) † Vendors can develop their own second-tier schedulers, which conform to the coprocessor interface as defined in this data sheet, in advance of the availability of the TNETA1585 device. 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 MECHANICAL DATA PGC (S-PQFP-G240) PLASTIC QUAD FLATPACK 180 121 120 181 0,27 0,17 0,08 M 0,50 0,16 NOM 61 240 1 60 29,50 TYP 32,20 SQ 31,80 34,80 SQ 34,40 Gage Plane 0,25 3,80 TYP 0,25 MIN 0°– 7° 0,75 0,50 Seating Plane 0,08 4,20 MAX 4040026 / B 10/94 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43 PACKAGE OPTION ADDENDUM www.ti.com 2-Mar-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TNETA1575PGC OBSOLETE QFP PGC Pins Package Eco Plan (2) Qty 240 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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