AN1902 - APPLICATION NOTE ® VIPower: HF CONVERTER BASED ON VK06TL DEVICES TO DRIVE 58W TL TUBES N. AIELLO - S. MESSINA This document describes a reference design for Lighting Ballast dedicated to drive 58W T8 tubes. The board accepts DC input voltage (up to 430V) realizing the cathodes preheating, the EoL protection and the maximum current limitation. It is based on the new VK06 device that integrates the controller and the Power stage on the same chip. It is housed in SO-16 and SIP-9 packages. INTRODUCTION The European Community has agreed on a new directive for banning electromagnetic control gear for fluorescent lamps. The aim is to improve the system efficiency (EEI-Energy Efficiency Index) reducing the environmental impact. This new directive divides the ballast in different classes from A1 to D. A1 is the most efficient system, D the least efficient. c u d A1 → Dimmable electronic ■ A2 → Low-loss electronic ■ e t le A3 → Standard electronic B1 → Extra low-loss magnetic ■ B2 → Low-loss magnetic ■ ■ C → Normal-loss magnetic ■ D → High-loss magnetic ■ ) s ( ct ) s t( o r P o s b O - Since 1998, the energy classification has become compulsory and it has been inserted in a Cenelec standard. It means: - since April 2002, all ballasts with an EEI of D are banned; u d o - starting from October 2005, all ballasts with an EEI of C will be banned. Thus the market is asking for cost effectiveness, good performance, low noise and compact ballasts to feed this kind of applications. The VK06 is a very suitable device, satisfying all the requirements with few external components. The proposed reference design can supply 58W T8 FL tube with preheating function and EoL protection. Being the design reference focused on the converter realization (we don’t cover the PFC stage) it has been set to give out the right output power when 400V dc voltage is applied. r P e t e l o s b O 1. VK06 DESCRIPTION The VK06 is a monolithic device made by using the VIPower® M3-3 STMicroelectronics proprietary technology that integrates in the same chip a vertical flow Power stage and a BCD based control circuit. The Power stage is made by a high voltage Bipolar transistor together with a low voltage n-channel MOS transistor in emitter switching configuration Its performances are a good trade-off between the Bipolar transistor low drop/high breakdown voltages and the MOS transistor high switching speed. The block diagram is shown in figure 1. March 2004 1/32 AN1902 - APPLICATION NOTE In the control part the following sections can be analyzed: 1) Supply 2) Oscillator/Trigger 3) Diac 4) Protections Figure 1: VK06 Internal Block diagram VCC Vcc charge CLAMP Supply COLL Vdd Vcc Vcc sec on/off SEC Bipolar Driver Delay on Vref1 Gate Driver diac on/off DIAC DIAC Vcc Vcc Vref2 Vref4 Vdd latch Vdd Reset CAP1 protection COLL Vcc Vcc Over Temperature Detector protection Vref3 e t le Vref6 CAP2 o r P Vcc Vdd CapPREH Reset Preheating c u d Over Current Detector CAP1 GND o s b O - ) s t( Rsense Vref5 CapEOL 1.1 SUPPLY (Figure 2) The device is supplied from the VCC pin connected to an R-C network. From VCC both the control and the power stage are supplied. At start up the supply capacitor is charged through a resistor and only few hundreds µA are needed. During the operation the device is self-supplied recovering on VCC the charge taken from the Power Bipolar base at turn-off. The voltage on VCC is internally clamped at ~6.8V. ) s ( ct u d o Figure 2: Internal Supply Block r P e DC BUS Ic VCC Vcc charge CLAMP COLL t e l o s b O Vcc Ic Bipolar Driver Gate Driver R sense GND 2/32 AN1902 - APPLICATION NOTE 1.2 OSCILLATOR/TRIGGER (Figure 3) It fixes the converter working frequencies (preheating, ignition, and steady-state). The tON (conduction time) is set using SEC, CAP1, CAP2 and CapPREH pins. The device is triggered ON when the voltage on SEC reaches ~2.2V. When this condition is detected the Power stage is switched ON and internal current generators start to give constant currents to CAP1 and CapPREH. The device will be switched OFF when one of the two following conditions is present: the voltage across CAP1 is equal to the internal voltage reference (~2.3V), the voltage on SEC is lower than 0.9V. Using a capacitor on CapPREH and the two frequency capacitors on CAP1 and CAP2 it is possible to have both preheating and steady state frequencies. Until the voltage on CapPREH is lower than 4.2V only the Cfpreh (capacitor connected to CAP1) will be charged setting the preheating frequency. When 4.2V on CapPREH pin is overcome, an internal switch puts in parallel Cfpreh with the Cfst capacitors (connected between CAP1 and CAP2) lowering the frequency to the steady-state one. The value of CapPREH fixes the preheating duration. In all the operative conditions the frequency capacitors will be discharged when the voltage on SEC becomes lower than 0.9V. During the lamp ignition the frequency control is realized through the secondary windings wound on the primary choke and connected to the SEC pins. In this phase the voltage on SEC reaches 0.9V before the tON is set by the frequency capacitors. The system oscillate at its resonance frequency (higher than steady state one) allowing the tube ignition. After the tube ignition the tON will be set by the frequency capacitors. An internal delay at Power turn-on avoids the hard switching condition. c u d e t le Figure 3: Internal oscillator/trigger block SEC 2.2V Vdd ) s ( ct CapPREH o r P e t e l o so Vcc b O - Cappreh o r P Gate Driver 2.3V Reset CAP1 Vcc du Delay on ) s t( Vdd 4.2V CAP2 CAP1 Cfst Cfpreh s b O 1.3 DIAC (Figure 4) Through the DIAC pin two functions are achieved: start of oscillations and reset of the preheating capacitor CapPREH. 1) Start of oscillation: in OFF condition (voltage on the SEC pin lower than 2.2V) the device can be turned ON when the voltage across DIAC overcomes ~28V. An HV diode keeps the DIAC low when the Power stage is ON. 2) Reset of preheating capacitor: in order to guarantee the right preheating timing the preheating capacitor must be discharged before starting oscillations. To realize this function a switch on CapPREH 3/32 AN1902 - APPLICATION NOTE pin is activated when the voltage across DIAC pin overcomes ~12V. On the other side the diac can activate the circuit only when the voltage on CapPREH becomes lower than ~0.6V. Figure 4: Internal diac block DC BUS Vcc sec on/off SEC Vref1 DIAC diac on/off DIAC Vcc 0.6V COLL CapPREH Cappreh Reset Preheating c u d o r P ) s t( 1.4 PROTECTIONS (see figure 5) The device is protected against over-current and over-temperature. Both protections are activated connecting on the CapEOL pin a capacitor that fixes the timing. The over-current protection works as follows: an internal Rsense checks the current through the Power stage and if it exceeds ~1.5A, an internal generator gives current to CapEOL pin. When the voltage across CapEOL pin reaches ~4.3V the Power stage is kept OFF, the diac is deactivated and the current consumption from VCC is lowered. At the same time another current generator is activated latching the device in OFF state. The thermal protection is activated when the junction temperature exceeds ~150°C. This block, when activated, acts on the same EoL circuit latching the device. e t le ) s ( ct o s b O - Figure 5:. Internal protections block u d o r P e t e l o s b O DIAC COLL diac on/off DIAC Gate Driver Vcc Vdd Over Current Detector latch Vcc Vcc Over Temperature Detector protection 4.3V CapEOL Capeol 4/32 Rsense Vref AN1902 - APPLICATION NOTE 2. PACKAGES The VK06 is assembled in two different packages in order to cover both the surface mounting and the through-hole PCB. The packages are the SO-16 narrow and the SIP-9 (see figure 6). Figure 6: Package outline and pin configuration 9 16 8 9 1 1 SO16 PACKAGE SIP9 PACKAGE N° pin Name N° pin Name 1 CAP1 1 CAP1 2 CapPREH 2 CapPREH 3 GND 3 GND 4 DIAC 4 5 SEC 5 6 VCC 6 7 CAP2 7 8 CapEOL 9÷16 COLL c u d DIAC COLL. e t le so ) s t( o r P SEC VCC 8 CAP2 9 CapEOL b O - In figure 7 the SO-16 thermal characterization is reported. In this package eight pins are connected to the tab to reduce the junction-pin thermal resistance whereas the case-ambient thermal resistance is related to the copper area on the PCB (device heat-sink). The device has been characterized at three different ) s ( ct copper areas: 0.5, 1 and 2 cm2; at three different power dissipations: 0.25, 0.5 and 1W and measuring the devices case temperatures. u d o r P e Figure 7: SO-16 Rth case-ambient Vs. PCB Copper Area s b O t e l o Rth case-ambient 160 °C/W 150 140 130 120 110 100 90 80 70 60 50 0 0.5 1 1W 0.5W 1.5 Cm2 2 0.25W 5/32 AN1902 - APPLICATION NOTE In Figure 8 the SIP-9 thermal characterization (no heat-sink) is reported. Figure 8: SIP-9 Rth case-ambient (no heat-sink) Rth case-ambient 46 [°C/W] 45 44 43 42 41 40 39 0 0.25 0.5 0.75 1 1.25 1.5 1.75 [W] 2 c u d ) s t( 3. CONVERTER DESCRIPTION In figure 9 the electrical scheme, realizing a voltage-feed converter based on VK06 is reported. The two windings Ls connected to the SEC pins are wound on the choke Lp. Four different operative phases can be described: - start-up e t le - preheat - steady state - ignition Figure 9: Typical application circuit ct R14 VCC C15 t e l o bs O C10 C14 CapEOL Tube GND Ls C11 C9 Lp R3 COLL VCC CAP2 DIAC CAP1 CapPREH R10 SEC CapEOL GND Ls C6 D1 C1 Dz2 R1 C3 DC BUS R15 SEC C16 6/32 o s b O - DIAC CAP1 CapPREH r P e C12 COLL u d o CAP2 (s) o r P C7 Dz1 C8 R6 C4 Cbulk C2 AN1902 - APPLICATION NOTE 3.1 START-UP As soon as the system is supplied, the VCC capacitors C3 and C12 start to be charged from the DC bus respectively by means of the resistors R1 and R14-R10. At the same time, the low side diac capacitor C4 starts to be charged by the resistor R3. The network R15-C11 biases the high side DIAC. In normal operations the low side device is the one to go on the first time, while in the high side device the DIAC pin, clamped by Dz2, is used only to reset the preheating capacitor C9. As soon as the voltage on C4 reaches about 28.5V the diac block switch ON the device. At that time both devices must be biased with the minimum requested VCC voltage (~ 5V) in order to make the system oscillate properly. In figure 10 low side (LS) diac and VCC typical waveforms are shown. In the picture the VCC voltage reaches 6.8V after 4.2m sec remaining constant at this value (it is internally clamped) until the converter starts to oscillate. At that time the storage charge recovery will be responsible for the device supply, charging the VCC capacitor at the final voltage value (~6.8V). Figure 10: Typical start-up operation c u d LS DIAC pin voltage ) s ( ct e t le ) s t( o r P LS VCC pin voltage o s b O - u d o r P e t e l o For the diac and VCC biasing networks the following choices can be done: s b O R14=R10 ; R14+R10=R1; C3=C12 R15 >>R14 With this setting the converter midpoint will stay at Vdcbus/2 and the voltages across C3 and C12 will be the same for any DC bus voltage. For a proper start up phase the following condition has to be satisfied: VC3=VC12 ≥ 5V when V C4 =28.5V 7/32 AN1902 - APPLICATION NOTE Where: τVc3=R1 • C3 = (R14 + R10) • C12 τVc4=R3 • C4 (low side) The network R15-C11 must be chosen to have the complete discharge of C9 when the low side diac strikes the converter. The zener diode Dz2 (~18V) clamps the DIAC pin below the diac activation threshold. During oscillations the diac capacitors C4 and C11 will be discharged by the internal diodes connected between DIAC and Power collector while the VCC capacitor will be charged by the charge recovered from the Power stage (see figure 11). Figure 11: Typical waveforms after the diac strike Mid point voltage c u d e t le LS VCC pin voltage ) s t( o r P o s b O - LS DIAC pin voltage ) s ( ct u d o 3.2 PRE-HEAT Still referring to the figure 9, the capacitors C7-C9 (with C7=C9) fix the cathodes preheating time duration. The preheating frequency is set by the capacitors C10-C6 (with C10=C6). r P e t e l o 3.2.1 PRE-HEATING TIME CapPREH pin supplies a constant current IcapPREH~55µA. This current is supplied only during the tON. The preheating ends when 4.2V is reached on CapPREH. Assuming that s b O ∆VCapPREH = 4.2V I CapPREH ≅ 55 µA the preheating time tpreh will be: t 8/32 p reh ∆VCapPREH - = = C7 • -------------------------ICapPREH -------------------2 0.15 s /µF AN1902 - APPLICATION NOTE 3.2.2 PRE-HEATING FREQUENCY For the pre-heating frequency calculation the following considerations can be done: 1 f = T-1 --- T 2 tON + t storage + tdVdt t storage = con st ≈ 300 nsec = (storage duration of the device Power stage) tdV/dt is the duration of the snubber capacitor (C14) charge during the half-bridge mid-point commutation between ground and VDC bus. It can be calculated using the following relationship: tdV/dt= Csnubber x ∆V/ipeak where: ■ ∆V (DC bus voltage); ■ ipeak (peak current); ■ c u d Csnubber (snubber capacitance). ) s t( o r P tON is the conduction time fixed by the preheating frequency capacitor (C6) and device characteristics. It can be calculated according to the following formula: tON=K • C6 Where K=6.7µsec/nF (fixed by the VK06) e t le o s b O - 3.3 STEADY STATE The steady state frequency is set by the parallel of the capacitors C6-C16 for the low side and C10-C15 for the high side, where C16=C15. The same formulae of the preheat can be applied: 1 --- T 2 = t ON + t storage t storage = u d o + tdVd t 1 f = T-- ≈ 300n sec r P e const ) s ( ct t ON = K ( C 6 + C 16 ) t e l o 3.4 IGNITION The converter of figure 9 has two different resonance frequencies, the first one before the tube ignition the second one after the tube ignition. The converter operation from preheat to steady state is shown in figure 12. s b O 9/32 AN1902 - APPLICATION NOTE Figure 12: Load typical resonance curves Resonance frequency before the tube ignition(f1). Resonance frequency after the tube ignition (f2). 2 3 1 fsteady fpreh fign f Where the two frequencies are: c u d f1 1 = -----------------------------------------------2 π L P ( C 1 series C2 ) (before the tube ignition) f2 1 = ----------------------2π L C P 2 (after the tube ignition) e t le ) s t( o r P In good ballast design the cathode preheating is requested in order to increase the tube lifetime. It is obtained making high current flow through the cathodes for a fixed time. A simple rule for the preheating efficiency check is reported: o s b O - 1) measure the cathode resistance at the beginning of the preheating; ) s ( ct 2) measure this resistance at the end of the preheating; 3) if its value is increased 3-4 times, the cathodes will work at the right temperature during ignition. u d o During the preheating the current level has to be able to heat the cathodes without generating the ignition voltage on the start-up capacitor C1. Still referring to figure 12, the converter will operate as follows: it will start working at the preheating frequency (dot 1) that must be higher than the resonance frequency f1. It will remain in this condition for the time fixed by the preheating capacitor. After the preheating the device frequency control is taken by the two secondary windings moving the working frequency up to the dot 2 where the tube is supposed to ignite. Once the tube is ignited the converter resonance frequency is lowered to f2 and the converter can work at the steady state frequency (dot 3) fixed by the oscillator capacitors. In figure 13 the complete start-up sequence is shown. r P e t e l o s b O 10/32 AN1902 - APPLICATION NOTE Figure 13: Typical converter operation from start-up to steady state Preheating Steady-state c u d Ignition e t le 3.5. PROTECTIONS The converter is protected against: - End of Life (EoL) - Overtemperature - Overcurrent ) s ( ct ) s t( o r P o s b O - 3.5.1 End of Life If the tube is in EoL condition it will not ignite anymore forcing the converter to work at its resonance (f1) with very high current levels. This condition must be checked, stopping the oscillation, before the system destruction for high power dissipation. In the suggested converter (figure 9) the EoL condition is detected in the low side VK06 using the capacitor C8 connected to CapEOL pin. This pin is shorted (disabled) in the high side device. u d o r P e t e l o The protection is activated as follows: an internal Rsense checks the current through the Power stage. If this current exceeds ~1.5A an internal generator supplies current (iEOL about 350µA) to CapEOL pin. As soon as the voltage across CapEOL pin reaches ~4.3V (∆vEOL) the Power stage is switched OFF, the diac is deactivated and the current consumption from VCC is lowered. At the same time another current generator is activated latching the device. This condition is maintained until the DC bus voltage is present. The duration of EoL condition before latching is established by C8 according to the following considerations. s b O C 8 I M × tEOL = -------------------∆v E OL 11/32 AN1902 - APPLICATION NOTE where: IM = average current flowing into C8 during the period of oscillation. Referring to the figure 14, IM can be i EOL × tch arg e I M = ------------------------------= i E OL × tch arg e × f T f is the frequency during EoL condition (~ resonance frequency) Combining the equations we obtain: C8 i EOL × t ch arg e × f × t EOL = ------------------------------------------------------∆v EOL Figure 14: Device current during the EoL condition c u d ) s t( o r P LS Collector current 1.5A e t le o s b O - tcharge ) s ( ct u d o r P e t e l o s b O Figure 15 shows the operation during the EoL condition. The capacitor C8 is maintained discharged during the preheating phase and the oscillation are stopped as soon as it is charged to 4.3V 12/32 AN1902 - APPLICATION NOTE Figure 15: Operation during the EoL phase Choke Current LS CapEOL pin Voltage e t le 3.5.2 OVERTEMPERATURE c u d ) s t( o r P o s b O - A thermal protection is activated when the junction temperature exceeds ~150°C. Its effect is the same of the EoL detection. For the timing definition it must be considered that the current generator on CapEOL pin is activated during the tON of the device. The duration of the over-temperature condition before latching (tTH) can be calculated as follows ) s ( ct where: iEOL= 350µA; u d o t th = C8 ∆v EOL × -------------I E OL ---------2 r P e t e l o ∆vEOL =4.3V. s b O 3.5.3 OVERCURRENT The network D1, Dz1 and R6 connected between SEC and CAP1 pins realizes the overcurrent protection limiting the maximum accepted peak current. This function is very useful during the ignition and the EoL, where the converter, working very close to the resonance frequency (f1), can reach very high current levels (possibility of saturation of the transformer). This circuit is applied only on the low side VK06. It works anticipating the device switch OFF when a defined current level is reached, in other words the working frequency is increased. The modality is the following: an increasing in the current value causes an increase of the secondary winding voltage (we are working at the resonance frequency). As soon as this voltage exceeds the zener Dz1 + diode D1 breakdown, an amount of current will flow into 13/32 AN1902 - APPLICATION NOTE the frequency capacitor anticipating the device switch-OFF. The resistance R6 limits injected current realizing a delay in the capacitor charge. The diode D1 decouples SEC and CAP1 pins during the OFF state (negative voltage on SEC pin). In figure 15 the EoL intervention with the current limited at 2,4A is shown. 3.6 MORE ABOUT THE TRIGGER With high resistive tubes the voltage on the secondary windings could decrease very rapidly, reaching the SEC pin switch-OFF threshold (0.9V), before than the internal oscillator switch OFF the device. This cause an increase of the working frequency. The phenomenon can be explained as follows: the voltage drop on the choke Lp is equal to VDCbus/2 minus the drop on the impedance made by the tube and C1 that is proportional to the current. The voltage on the secondary windings is a fixed portion of the primary one. If the voltage on Lp becomes zero no voltage will be transferred on SEC pin and the device will be switched-OFF. The higher is the tube impedance the lower is the current level at which the situation can occur. In this case to guarantee the right frequency control, an R-C or R-C-D filter has to be inserted between the secondary winding and SEC (see figure 16). The values of R1f and C1f have to be chosen in order to maintain the voltage on SEC pin higher than ~0.9V during the fixed tON even if the voltage on the secondary winding becomes zero or negative. c u d ) s t( o r P On the other side it is important to have the SEC pin voltage higher than 2.2V before the end of the freewheeling diode conduction to avoid delay at Power switch-ON. Therefore the filter dimensioning is a trade-off between the charge and the discharge time constant. e t le The circuit reported in figure 16b can be used if different and independent time constants are necessary. Figure 16: External trigger circuits SEC R1f (s) t c u d o r P e t e l o s b O o s b O - VK06 a) VK06 b) C1f R2f SEC Df R1f C1f 3.7 CONVERTER FOR COLD IGNITION APPLICATIONS (NO PRE-HEAT) For applications where the pre-heating of the cathodes is not requested, it is possible to use a simplified converter as reported in figure 17. 14/32 AN1902 - APPLICATION NOTE Figure 17: Application circuit without preheat DC BUS R14 VCC COLL CAP2 C12 DIAC CAP1 CapPREH CapEOL C14 C1 SEC Tube GND Ls C10 Cbulk Lp C2 R1 CAP2 C6 c u d R10 DIAC CAP1 CapPREH CapEOL C3 R3 COLL VCC SEC GND Ls C4 C8 4. VK06 Design Reference e t le ) s ( ct ) s t( o r P o s b O - This design reference has been developed to help the VK06 users in the application board development. To point out the maximum VK06 performances we decided to drive a 58W T8 FL tube. Two different PCBs have been realized, the first one using only surface mounting components and the second one using only through hole components. In the figure 18a, 18b, 18c their photos are shown. u d o r P e t e l o s b O 15/32 AN1902 - APPLICATION NOTE Figure 18: VK06 demoboard: SMD components, top (a) and bottom (b) view; through-hole top view (c) a) c u d e t le ) s ( ct u d o r P e ) s t( o r P b) o s b O - c) t e l o s b O 4.1 Electrical scheme In figures 19 and 20 the electrical schemes for both trough hole and surface mounting demoboards are shown. 16/32 AN1902 - APPLICATION NOTE Figure 19: Through hole components demoboard electrical scheme F1 R14 R15 5 7 4 6 VK06TLS 8 1 R12 3 9 2 C14 C15 + C13 C12 C11 C10 C9 Dz2 c u d T1 58W C2 ro M1 P e let C1 R1 7 4 6 R4 ) s ( ct C3 u d o o s b O - ) s t( R10 5 3 VK06TLS 8 1 2 C16 C8 R8 R5 D1 Dz1 R6 C7 C4 C5 + C6 r P e t e l o s b O 17/32 AN1902 - APPLICATION NOTE Figure 20: SMD demoboard electrical scheme F1 R14 R17 R15 R13 R16 6 4 5 9÷16 VK06TL 1 7 3 C14 8 2 R12 C15 Dz2 C12 C13 M2 C10 C11 C9 c u d T1 C2 58W o r P R18 C1 R1 R2 R3 R4 ) s ( ct u d o C3 e t le o s b O - ) s t( R10 R9 9÷16 3 6 4 VK06TL 5 1 8 7 2 C16 C8 R8 R5 D1 Dz1 R6 C7 C4 C5 C6 r P e t e l o 4.2. COMPONENTS LIST The material lists for both PCB are reported in tables 1 and 2. s b O 18/32 AN1902 - APPLICATION NOTE Table 1: Components list of the VK06 demoboard with trough hole components Reference R1 R4 R5, R12 R6 R8 R10, R14 R15 C1 C2 C3, C12, C8 C4 C5, C13 C6, C10, C15, C16 C7, C9 C11 C14 D1 Dz1 Dz2 T1 IC1, IC2 Value 330kΩ 1/2W 5% 400V 1MΩ 1/2W 5% 400V 15kΩ 1/4W 5% 68kΩ 1/4W 5% 1MΩ 1/4W 5% 180kΩ 1/2W 5% 400V 2.2MΩ 1/2W 5% 400V 8.2nF 2000V 5% 100nF 400V 330nF 16V 10% 47nF 50V 10% 100 pF 100V 10% 1nF 2% 4.7µF16V 20% 10nF 50V 1nF 630V If=0.15A Vrrm=75V 36V 18V 1.8 mH 10% Description Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resonant capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Electrolytic capacitor Capacitor Snubber capacitor Rectifier diode Zener diode Zener diode Resonant Inductor Pulse Eldor 60010019 STMicroelectronics VK06TLS c u d e t le ) s t( o r P THROUGH HOLE COMPONENTS DEMOBOARD INDUCTOR SPECIFICATION MECHANICAL DRAWING (Bottom view) ) s ( ct o s b O - MECHANICAL DRAWING u d o r P e t e l o ELECTRICAL CONNECTION O bs ELECTRICAL CHARACTERISTICS Nominal Inductance (W1=1-8) L=1.8mH ± 10% Core EC 28 Turn ratio = W1/W2=W1/W3=10 2 = Lamp; 3 = Ground; 4 = Low Side SEC pin; 5 = Not connected; 8 = High Side SEC pin; 9 = Not connected; 11 = Mid Point 19/32 AN1902 - APPLICATION NOTE Table 2: Components list of the VK06 demoboard with SMD components Reference R17,R18 R19,R20 R15,R16 R8 R3,R4 R1,R2 R9,R10 R13,R14 R5,R12 R6 C5,C13 C6,C10, C15,C16 C7,C9 C3,C8,C12 C11 C4 C1 C2 C14 D1 Dz1 Dz2 T1 Value 0Ω 1MΩ 200V 5% 200V 1MΩ 5% 470kΩ 5% 200V 220kΩ 5% 0.25W 200V 100kΩ 5% 0.25W 200V 15kΩ 5% 68kΩ 5% 100pF 100V 10% 1nF 2% 16V 4.7uF 10% 16V 330nF10% 16V 10nF 50V 47nF 50V 10% 8.2nF 5% 2000V 100nF 400V 1nF 630V If=0.15A Vrrm=75V 36V 18V 1.8 mH 5% IC1, IC2 Description Zero ohm Resistor Resistor 1206 Resistor Resistor 1206 Resistor 1206 Resistor 1206 Resistor Resistor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Resonant capacitor Capacitor Snubber capacitor Rectifier diode Zener diode Zener diode Resonant Inductor VOGT: LL 010 205 31 TDK: SRW25EVD4-E01H003. STMicroelectronics VK06TL c u d e t le o s b O - ) s t( o r P SMD COMPONENTS DEMOBOARD INDUCTOR SPECIFICATION MECHANICAL DRAWING (Bottom view) ) s ( ct MECHANICAL DRAWING u d o r P e t e l o O bs ELECTRICAL CONNECTION ELECTRICAL CHARACTERISTICS Nominal Inductance (W1=1-8) L=1.8mH ± 5% Core EVD 25 Turn ratio = W1/W2=W1/W3=10 1 = Lamp; 2 = Ground 3 = Low Side SEC pin; 5 = High Side SEC pin; 8 = Mid point 20/32 AN1902 - APPLICATION NOTE 4.3. PCB DEFINITION In figures 21 and 22 the proposed PCB for both SMD and trough hole demoboards are shown. Figure 21: SMD PCB Bottom view (not in scale) c u d Figure 22: Through hole PCB Bottom view (not in scale) e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o The components placement on the PCB is important and few simple rules have to be followed for its realization. s b O 1) Frequency capacitor placement: These components must be connected as close as possible to the CAP1 pin. 2) Ground path: The ground paths (signal and power) must be separate in order to reduce interference on the logic part. In figure 23 an example of this rule is shown. 21/32 AN1902 - APPLICATION NOTE Figure 23: PCB Ground path Signal Ground Power Ground c u d ) s t( 4.4. EXPERIMENTAL RESULTS For the board testing it is important to connect on the input terminals an electrolytic capacitor (10µF, 450V), in order to bypass the parasitic inductance present in the connection wires between the DC supply voltage and the board (see figure 24). e t le Figure 24: Connection between the DC supply voltage and the board ) s ( ct u d o DC Power Supply o r P o s b O - VK06 Demoboard r P e t e l o s b O All the measurements have been done supplying the converter with 400V DC. 4.4.1 START-UP PHASE In figure 25 the start-up phase is shown. The voltages on the low side (LS) VCC and diac pins are reported. It is possible to notice that the VCC voltage reaches its clamp value (~6.8V) before the diac strike. In figure 26 the first oscillation cycles after the diac strike are shown. 22/32 AN1902 - APPLICATION NOTE Figure 25: Start-up phase LS DIAC pin voltage LS VCC pin voltage c u d Figure 26: First oscillation cycles after the diac strike LS collector current o r P o s b O - Mid point voltage ) s ( ct e t le ) s t( LS VCC pin voltage u d o r P e t e l o s b O LS DIAC pin voltage 4.4.2 PRE-HEATING PHASE The preheating frequency has to be fixed in order to reach a current level enough to heat the cathodes without tube ignition. Figure 27 shows the main waveforms of the LS device. 23/32 AN1902 - APPLICATION NOTE Figure 27: Operation during the pre-heat LS CAP1 pin voltage LS SEC pin voltage Choke current Mid point voltage c u d ) s t( o r P The preheating frequency is ~59KHz with a peak current of ~800mA. Being the resonance capacitor C1= 8.2nF, during the preheat its voltage is lower than the preheating specification of a 58W T8 tube (350V peak). e t le o s b O - Figure 28 shows the preheating timing. The choke current and the voltage on the CapPREH pin are reported. The preheating duration is ~0.84s (C7=4.7uF) ) s ( ct Figure 28: Pre-heating phase timing u d o r P e s b O t e l o Choke current LS CapPREH pin voltage 24/32 AN1902 - APPLICATION NOTE 4.4.3 IGNITION PHASE Figure 29 shows the main waveform during the ignition phase. The peak current is limited to ~2A thanks to the overcurrent protection network made by D1, Dz1 and R6 (see figures 19 and 20). In fact as soon as the voltage on the sec pin overcomes ~40V the frequency capacitors charge becomes faster (see CAP1 waveform) anticipating the device switch-off. Figure 29: Ignition phase LS CAP1 pin voltage LS SEC pin voltage Choke current c u d Mid point voltage e t le ) s t( o r P o s b O - 4.4.4 STEADY STATE Figure 30 shows the steady state phase main waveforms. The working frequency is ~34KHz with a peak current of ~700mA. ) s ( ct Figure 30: Steady state phase u d o r P e LS CAP1 pin voltage Choke current t e l o s b O Mid point voltage LS SEC pin voltage 25/32 AN1902 - APPLICATION NOTE 4.5 PROTECTIONS 4.5.1 End of Life In figure 31 the timing of the EoL protection is shown. Figure 31: End Of Life timing Choke current c u d e t le ) s t( o r P o s b O - The system operates as follows: after the start-up, the preheating phase starts and lasts ~0.84sec as in the normal operation. After the preheating phase the system could permanently work in free oscillation condition due to the EoL state. The protection stops the oscillation after ~50msec. ) s ( ct Figure 32: EoL: device turn-off u d o r P e t e l o Choke current LS CapPREH pin voltage s b O Mid point voltage 26/32 AN1902 - APPLICATION NOTE Figure 32 shows the particular of the LS device turn-off when the voltage on the LS CapPREH pin reaches the internal threshold. 4.6 THERMAL EVALUATION The thermal analysis has been performed measuring the devices temperatures in the SMD version demoboard. The heat sink copper area copper area is ~100mm2 for each device. The temperature has been measured with K type thermocouples put on the top of the SO-16 packages. The measurements have been performed at two different ambient temperatures: room temperature (about 25°C) and 50°C. The results are summarized in table 3. Table 3: Devices temperature Tambient 25ºC 50ºC Tcase 90ºC 115ºC c u d ) s t( 5. TUBE RECTIFICATION (not included in the reference demoboards) Below, a network for the rectification detection is described. The dimensioning is related to a 58W T8 tube. This is an anomalous condition happening during the steady state phase causing lamp overvoltage and not overcurrent, for this reasons it is not possible to detect it by the EoL protection. e t le o r P The proposed network realizes a lamp voltage sense. The timing and the device latch is realized using the same internal EoL circuit. o s b O - The circuit used to simulate the rectification condition has been realized according to E DIN IEC 61347-23/A1 2002-02 standard (see figure 33). Figure 33: Circuit for simulating the rectifying effects ) s ( ct u d o C r P e R1 t e l o O bs R2 5.6 5W 5.6 5W R1 100 10W D2 2 x BYV228 Tube T8 58W D1 2 x BYV228 D F E The points C,D,E,F must be connect to the VK06 converter output terminals. In figure 34 the circuit used for the tube rectification detection is shown. 27/32 AN1902 - APPLICATION NOTE Figure 34: Proposed circuit for detecting the rectifying effects DC Bus = 400V C T1 E D C2 C1 100 nF 8.2nF F Mid Point 1.8mH R DZ 27k 33V C 470 pF 630V R 560k D EOL Pin 0.2A, 75V R c u d 180k e t le The terminals C-E and D-F must be connected to the circuit of figure 33. ) s t( o r P The rectification condition is detected monitoring the voltage across the 180kΩ resistor. When the rectifying effects occur, the increase of the voltage across the lamp causes the increase of the voltage across the resistor R= 180kΩ over the threshold fixed by the network D-Dz-R. At that moment the EoL protection is activated. o s b O - During the preheating phase the voltage across the resistor R=180kΩ is higher than the steady state and the protection can be activated. For this reason a further circuit is needed for disabling the protection during the preheat. ) s ( ct u d o 6. CONVERTER FREQUENCY TOLERANCE VS. FREQUENCY CAPACITOR TOLERANCE r P e Following a practical example showing the variation of converter frequency versus the frequency capacitor tolerance. The analysis has been performed in steady state condition but it is also applicable to the pre-heat. A VK06TL based prototype board with the following setting has been used: t e l o VDC bus= 350V s b O CfreqLS = CfreqHS =C=1.22 nF (measured) Figure 35 shows the related steady state waveforms. 28/32 AN1902 - APPLICATION NOTE Figure 35: Test condition: CfreqLS = CfreqHS HS collector current LS collector current Mid point voltage c u d LS CAP1 pin voltage Following the measured parameters: f=52.2KHz duty cycle ≈ 50% P=45.5W With: ) s ( ct tONLS = tONHS = 8.36µs tstorageLS= tstorageHS =320ns dv/dt=920ns e t le ) s t( o r P o s b O - u d o r P e According to the theoretical relationship: tON=K*C with K=6.7µs/nF (5% internal guaranteed) (1) t e l o The expected tON is: tON= 6.7*1.22=8.2µs (inside 5% device tolerance) s b O - Experiment 1 Only the frequency capacitors have been changed: CfreqLS=C+6% CfreqHS=C-6% Figure 2 shows the related waveforms. 29/32 AN1902 - APPLICATION NOTE Figure 36: Test condition: 6% opposite variation on Cfreq LS collector current HS collector current c u d Mid point voltage LS CAP1 pin voltage e t le Following the measured parameters: frequency f=52.12KHz duty cycle ≈ 47.4% P=45.5W With: tONLS=8.8µs (+6%) ) s ( ct tONHS=7.72µs (-6%) tstorageLS = tstorageHS = 320ns ) s t( o r P o s b O - u d o dv/dt=920ns r P e It means that the opposite variation of the t ON causes a distortion of the duty cycle without variation on the frequency and power. t e l o - Experiment 2 CfreqLS=C+6% s b O CfreqHS=C+6% Figure 37 shows the related waveforms. 30/32 AN1902 - APPLICATION NOTE Figure 37: Test condition: +6% variation on Cfreq LS collector current HS collector current Mid point voltage c u d LS CAP1 pin voltage e t le Following the measured parameters: f=49.8KHz duty cycle ≈ 50% P= 46.2W With: TonLS= TonHS=8.8µs (+6%) ) s ( ct TstorageLS= tstorageHS =320ns dv/dt=920ns ) s t( o r P o s b O - u d o r P e The frequency variation respect to the initial condition (CfreqLS = CfreqHS = 1.22 nF) is 4.6% and it is less than the capacitor tolerance (6%). The power variation is instead ~1.6%. According to the relationship (1), the same results can be obtained if the tON variation is caused only by VK06TL internal tolerance. The worst case frequency variation will be anyway less than 5%. t e l o s b O 31/32 AN1902 - APPLICATION NOTE c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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