ut aliquip ex ea commodo consequat. Secure Boot Power Utilities Enterprise CSAC Protecting the Machines: Solving Processor Vulnerabilities We hear of security breaches in the news every day. Primarily because most electronic systems embed processors that do not validate code before its executed. Executing un-trusted code is what creates most of the problems we hear of in the news. This represents significant vulnerabilities to applications, systems, infrastructure as well as personal data. Microsemi’s Secure boot reference design can add security to a processor that doesn’t have any security built-in. In addition it can prevent root kit installations if used properly. Microsemi’s Secure Boot Reference Design can uniquely solve this problem due to three simple facts: 1.The worlds most secure SoC FPGA is used in conjuction with WhiteBoxCRYPTO™ to add security to a processor that has none 2.Internal secure flash memory (eNVM) can be used for storing 2nd stage boot and can be write protected to prevent rootkits from being installed 3.Fast I/Os and fast programmable logic which can emulate any memory interface that a processor needs, at speed Processors without Secure Boot Phase Phase 0 0 Boot Boot Loader Loader Phase Phase 2 2 BIOS BIOS Phase 1 Phase 1 nd 2 2nd Boot Boot Loader Loader Phase Phase 3 3 OS OS Phase Phase 4 4 Application(s) Application(s) Most processors boot and start executing; there is no verification at all of the various boot stages. Trust has not been established and cannot be extended to connected systems. Microsemi® Secure Boot Solution Validate Validate Phase Phase 1 1 Code Code Phase Phase 0 0 Immutable Immutable Boot Loader Loader Boot Validate Validate Phase Phase 2 2 Code Code Phase Phase 1 1 BIOS BIOS Validate Validate Phase Phase 3 3 Code Code Phase Phase 2 2 OS Loader Loader OS Initial Initial root-of-trust root-of-trust stems stems from from immutable immutable trusted hardware hardware trusted Validate Validate Phase Phase 4 4 Code Code Phase Phase 3 3 OS OS Phase Phase 4 4 Application(s) Application(s) Code Code for for phases phases 1-n 1-n is is validated validated by by already already trusted trusted system before before execution execution is is system transferred to to it it transferred Secure boot starts from a trusted source and a process of authenticating each successive stage is performed to create a chain-of-trust as depicted in the above figure. With the Secure Boot reference design, trust can be extended to connected systems. Main Main MPU MPU Encrypted NVM Encrypted NVM 1. BIOS 1. BIOS 2. OS OS Loader Loader 2. 3. 3. OS OS 4. Application 4. Application Code Code Hardware Hardware Root-of-Trust Root-of-Trust ® SmartFusion2 SmartFusion2® Secure Secure SoC SoC FPGA FPGA ® ™ ARM ARM® Cortex Cortex™-M3 -M3 Phase Phase 0 0 Code Code Challenge(s) Challenge(s) Response(s) Response(s) Phase 1-4 Code Target Target Processor Processor Main Main MPU MPU DDR DDR ut aliquip ex ea commodo consequat. Loader Secure Boot Power Utilities Enterprise Validate Phase 1 Code CSAC Validate Phase 2 Code Validate Phase 3 Code Validate Phase 4 Code Microsemi Secure Boot Reference Design Phase 0 Immutable Boot Loader Microsemi’s reference Phase 1 BIOS Phase 2 OS Loader Phase 3 OS Phase 4 Application(s) Incorporated (CRI). Also included is a public instance design is enabled by its of Microsemi’s WhiteboxCRYPTO security product, which SmartFusion2 SoC FPGAs or IGLOO2 FPGAs, which offer a number ofInitial advanced security features including enables transport of a symmetric encryption key in a root-of-trust Code for phases 1-n is stems from immutablefor cryptographic validated by already trustedplain text environment through strong obfuscation. on-chip oscillators, accelerators trusted hardware system before execution is services, secure key storage, a true random number transferred to it If you have a specific need for a reference design to generator, on-chip boot code storage in secure eNVM, securely boot your processor please send an email to and at-speed serial peripheral interface (SPI) flash [email protected]. Please provide your memory emulation to enable a secure boot of an external contact information, and your processor part number. All processor at speed. The devices also feature stronger downloads of Secure Boot Reference design files must design security than other FPGAs and include differential be approved by Microsemi. power analysis (DPA) resistant anti-tamper measures using technology licensed from Cryptography Research Main MPU Encrypted NVM 1. BIOS 2. OS Loader 3. OS 4. Application Code Hardware Root-of-Trust ARM® Cortex™-M3 OSC SPI SPI Flash Slave Phase 0 Code SmartFusion2® Secure SoC FPGA Master Main MPU Phase 0 Boot Code 0. Trusted Boot Code: Rootkit Free Challenge(s) PUF eNVM FPGA Main MPU Response(s) SPI Slave Master CPU PCIe USB SRAM Etc. RESET Power Enables POL DDR Phase 1-4 Code TRNG eSRAM Target Processor Tight integration with other board functions such as power management make bypassing the HW root-of-trust more difficult POL Code loaded into on-chip SRAM is validated before branching to it Power to Board For further information and reference design supporting additional processors please refer to: www.microsemi.com/products/fpga-soc/security/secure-boot SmartFusion2 SoC FPGAs: www.microsemi.com/smartfusion2 IGLOO2 FPGAs: www.microsemi.com/igloo2 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Tel: 408.433.0910 • Fax: 408.428.7896 www.microsemi.com E-mail: [email protected] ©2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.