SmartFusion2 SoC FPGA Advanced Development Kit UG0557 User Guide Table of Contents 1 - Introduction ...............................................................................................................4 SmartFusion2 Advanced Development Kit Contents .................................................................................... 4 SmartFusion2 Advanced Development Kit Web Resources ......................................................................... 4 Board Description .......................................................................................................................................... 4 2 – Installation and Settings ....................................................................................... 10 Software Installation .................................................................................................................................... 10 Hardware Installation ................................................................................................................................... 10 Power Sources ............................................................................................................................................ 14 3 – Key Components Description and Operation...................................................... 16 Powering Up the Board ............................................................................................................................... 16 Current Measurement .................................................................................................................................. 16 Memory Interface ......................................................................................................................................... 17 SERDES Interface ....................................................................................................................................... 19 USB Interface .............................................................................................................................................. 23 Marvell PHY (88E1340S) ............................................................................................................................ 23 Programming ............................................................................................................................................... 25 FTDI Interface .............................................................................................................................................. 26 System Reset .............................................................................................................................................. 26 Clock Oscillator ............................................................................................................................................ 27 Debugging ................................................................................................................................................... 28 Push-Button Switches ................................................................................................................................. 28 FMC Connectors.......................................................................................................................................... 30 4 – Pin List .................................................................................................................... 50 Pin List ......................................................................................................................................................... 50 5 – Placement of the Board Components .................................................................. 82 6 – Demo Design .......................................................................................................... 85 M2S150-ADV-DEV-KIT Board Demo Design .............................................................................................. 85 7 – Manufacturing Test ................................................................................................ 86 M2S150-ADV-DEV-KIT Power and Programming Test .............................................................................. 86 Running the Manufacturing Test ................................................................................................................. 89 List of Changes .......................................................................................................... 100 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 2 1 - Introduction Product Support......................................................................................................... 101 Customer Service ...................................................................................................................................... 101 Customer Technical Support Center ......................................................................................................... 101 Technical Support ...................................................................................................................................... 101 Website ...................................................................................................................................................... 101 Contacting the Customer Technical Support Center ................................................................................. 101 ITAR Technical Support ............................................................................................................................ 102 3 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 1 - Introduction ® The SmartFusion 2 system-on-chip (SoC) field programmable gate array (FPGA) Advanced Development Kit (M2S150-ADV-DEV-KIT) is RoHS compliant and enables you to develop applications that involve the following: • Microprocessor applications • Embedded ARM Cortex -M3 processor based systems ® ® • Motor control • Industrial automation • High speed I/O applications • Universal serial bus (USB) applications (OTG support) SmartFusion2 Advanced Development Kit Contents Table 1 shows the contents of the SmartFusion2 Advanced Development Kit. Table 1 · Kit Contents Quantity Description 1 SmartFusion2 Advanced Development Board with the M2S150TS-1FCG1152 device 1 USB A to Micro B cable 1 USB Micro A to A cable 1 USB A to Mini B cable 1 Peripheral component interconnect express (PCIe) edge card ribbon cable 1 12 V/5 A power adapter SmartFusion2 Advanced Development Kit Web Resources The SmartFusion2 Advanced Development Kit web resources: http://www.microsemi.com/products/fpga-soc/designresources/dev-kits/smartfusion2-kits Board Description The M2S150-ADV-DEV-KIT device offers a full-featured 150 K logic element (LE) SmartFusion2 SoC FPGA. This 150 K LE device has the following integrated on a single chip: • Reliable flash-based FPGA fabric • A 166 MHz Cortex-M3 processor • Advanced security processing accelerators • Digital signal processing (DSP) blocks • Static random-access memory (SRAM) • embedded nonvolatile memory (eNVM) • High-performance communication interfaces. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 4 1 - Introduction The SmartFusion2 Advanced Development Kit has numerous standard interfaces such as: • USB • x4 serializer and deserializer (SERDES) • DDR3 memory • JTAG • Inter-integrated circuit (I2C) • Serial peripheral interface (SPI) • Universal asynchronous receiver/transmitter (UART) • Dual Giga Bit Ethernet The SmartFusion2 memory management system supports 1 Giga Byte (4 × 256 MB) on-board DDR3 memory for data storage, 256 MB DDR3 memory for error detection and correction (ECC - SECDED), and 2 Giga bit (2 × 1Gb) SPI flash devices. The SERDES block can be accessed using the PCIe edge connector, high speed sub-miniature version-A (SMA) connectors or an on-board FPGA mezzanine card (FMC) connector-LPC (J60). The unused MSIOD signals are routed to the J60 connector from the SmartFusion2 device. The Advanced Development Kit has the current measurement feature, refer to Current Measurement section. The unused MSIO signals are routed to another onboard FMC connector - HPC (J30) and although the Bread board connector (J350) space available for bank 4 (MSIO) pins. The SmartFusion2 device can be programmed through embedded FlashPro5. 5 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Board Description Block Diagram Figure 1 shows the SmartFusion2 Advanced Development Kit block diagram. FMC connector-LPC (J60) FMC connector-HPC (J30) Banks-15,16 (MSIOD) Banks-0,3,5,6,8,11,14,17,18 (MSIO) DDR3 SDRAMs 4 x 256 MB DDR3 DDR3 SDRAM 256 MB (SECDED) Bread board Connector(J350) Bank4 (MSIO) SERDES0 MDDR (Bank2) PCIe edge connector (CON1) Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 SERDES1 SmartFusion2 M2S150TS-1FCG1152 Debug LEDs Lane 0 Lane 2 Lane 3 FMC connector (J30) Lane 0 Lane 1 SERDES2 Bank1 Lane 2 Lane 3 FMC connector-J60 Lane 0 Lane 1 Debug Switches SERDES3 Bank1 Lane 2 Lane 3 MDIO I2C0, I2C1 USB micro AB connector (P1) RJ45 ETM Header 1 Gb SPI Flash Mux FP4 Header Mux Header D Mux SC_SPI SPI1 JTAG RVI Header Mux 1 Gb SPI Flash Mux I2C port header (16 pin) H1 UART0 USB PHY USB3340 RJ45 JTAG SPI0 USB_D PHY 88E1340S Mux Buffer C A B FT4232 USB mini B connector (J33) Figure 1 · SmartFusion2 Advanced Development Kit Block Diagram UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 6 1 - Introduction Board Overview Figure 2 shows the snapshot of the SmartFusion2 Advanced Development Kit Board with engineering silicon. Figure 2 · SmartFusion2 Advanced Development Kit Board 7 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Board Description Board Key Components Table 2 describes the key components of the SmartFusion2 Advanced Development Kit board. Table 2 · SmartFusion2 Advanced Development Kit Board Components Name Description ® M2S150TS-1FCG1152 Microsemi SmartFusion2 device with a hard Cortex-M3 processor. DDR3 synchronous dynamic random access memory (SDRAM) • 4 × 256 MB (256 MB Micron DDR3 memories MT41K256M8DA-125 IT:K) for storing data. SPI flash • 1 Giga bit SPI flash Micron N25Q00AA13GSF40G connected to SPI port 0 of the SmartFusion2 microcontroller subsystem (MSS). • 256 MB (1 × 256 MB Micron DDR3 memory MT41K256M8DA-125 IT:K) for storing the ECC bits • Another 1 Giga bit SPI flash Micron N25Q00AA13GSF40G connected to the SmartFusion2 fabric. Ethernet Two RJ45 connectors (Ethernet jack with magnetics) interfacing with a Marvell 10/100/1000 BASE-T PHY chip 88E1304S in Serial Gigabit Media Independent Interface (SGMII) mode, interfacing with the Ethernet port of the SmartFusion2 MSS (on-chip MAC and external PHY). RVI header RVI header for application programming and debug from Keil ULINK or IAR J-Link. Embedded FlashPro5 Embedded FlashPro5 can be used for SmartFusion2 programming and debugging with Microsemi tools. Future Technology Devices International (FTDI) programmer FTDI programmer interface (J33) to program the external SPI flash. An FTDI chip is also used to change the JTAG_SEL signal (High or Low) remotely for switching between the RVI header and JTAG mode. Embedded trace macro (ETM) cell header ETM header for debug. PCIe edge connector PCI Express edge connector with four lanes Light-emitting diodes (LEDs) Eight active high LEDs that are connected to some of the user I/Os for debugging. Push–button reset Push-button system reset for the SmartFusion2 device. Push–button switches Four push-button switches for test and navigation. FMC connector - HPC (J30) FMC header to connect the external daughter boards. Connector array Socket 400 pins (40 × 10), 1.27mm pitch. The unused MSIO pins are routed from the SmartFusion2 device to the J30 connector. FMC connector - LPC (J60) FMC header to connect the external daughter boards. Connector array Socket 160 pins (40 × 4), 1.27 mm. The unused MSIOD pins are routed from the SmartFusion2 device to the J60 connector. USB interface USB Micro AB connector, interfacing with the high speed USB2.0 ULPI transceiver chip USB3320, interfacing with USB-D port of the SmartFusion2 MSS. DS1818 DS1818 (3.3 V) Econo Reset is simple three-pin voltage monitor and power-on reset that holds reset for 150 ms for stabilization after the power returns to tolerance. OSC-100 100 MHz clock oscillator (differential output) OSC-125 125 MHz clock oscillator (differential output) OSC-50 50 MHz clock oscillator UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 8 1 - Introduction Name Description OSC-32 32.768 KHz low power oscillator FT4232H USB to quad serial ports with a different configuration. TPS3808G09DBVR The TPS3808G09 supervisory circuit monitors system voltage of 0.9 V, asserting an open-drain Reset signal when the Sense voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. DS1818 DS1818 (3.3 V) Econo Reset is simple three-pin voltage monitor and power-on reset that holds reset for 150 ms for stabilization after the power returns to tolerance. I2C port Header 16 pin header is available for I2C0 and I2C1 interfaces of SmartFusion2. 9 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 2 – Installation and Settings Software Installation ® Download and install the Microsemi Libero System-on-Chip (SoC) software v11.4 or later, from the Microsemi website and register for a free Gold license. Libero v11.4 installer has FlashPro5 drivers. For instructions on how to install the Libero software and SoftConsole, refer to Libero Software Installation and Licensing Guide. For instructions on how to download and install Microsemi DirectCores, SGCores, and driver firmware cores, refer to Installing IP Cores and Drivers User’s Guide. These must be installed on the PC where the Libero software is installed while designing with Microsemi FPGAs and SoCs. ® SmartFusion2 is supported by the latest IAR Embedded Workbench™ from IAR Systems for ARM IPs. It is also supported by the latest Keil, MDK-ARM Microcontroller Advanced Development Kit. Hardware Installation Jumpers, Switches, LEDs, and DIP Switch Settings The recommended default jumpers, switches, LEDs, and DIP switch settings are shown in Table 3 through Table 5. • Table 3 - Jumper Settings • Table 4 - LEDs • Table 5 - Test Points Connect the jumpers with the default settings to enable the pre-programmed demo design. Note: Locations of all the jumpers and test points are searchable in Figure 20 (page 84) of 5 – Placement of the Board Components section. Table 3 · Jumper Settings Jumper Description Pin Default Settings Power Supply J123 J353 J354 J116 Jumper to select the core voltage (VDD_REG) to either 1.0 V or 1.2 V Pin 1–2 for 1.0 V core voltage Open Pin 2–3 for 1.2 V core voltage Close Jumper to select the core voltage (VCCIO_HPC_VADJ) to either 3.3 V or 2.5 V or 1.8 V or 1.5 V or 1.2V Pin 1–2 for 3.3 V Close Pin 3–4 for 2.5 V Open Pin 5–6 for 1.8 V Open Pin 7–8 for 1.5 V Open Pin 9-10 for 1.2 V Open Pin 1–2 for 2.5 V Close Pin 3–4 for 1.8 V Open Pin 5–6 for 1.5 V Open Pin 7-8 for 1.2 V Open Pin 1–2 for SW7 selection Close Pin 2-3 for “Enable_FT4232” signal control Open Jumper to select the core voltage (VCCIO_LPC_VADJ) to 2.5 V or 1.8 V or 1.5 V or 1.2V Jumpers to select either SW7 input or signal ENABLE_FT4232 from FT4232H chip. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 10 2 – Installation and Settings Jumper Description Pin Default Settings Jumper to select switch-side Mux inputs of A or B to the line side. Pin 1-2 (Input A to the line side) that is external clock required to source the line side through FMC connector. Open Pin 2-3 (Input B to the line side) that is external clock required to source the line side through SMA connectors. Open Pin 1-2 (Line side output enabled) Open Pin 2-3 (Line side output disabled) Open Pin 1-2 (Line side output enabled) Close Pin 2-3 (Line side output disabled) Open Pin 1-2 (Input A to the line side) that is on board 125 MHz differential clock oscillator output is routed to line side. Close Pin 2-3 (Input B to the line side) that is on board 100 MHz differential clock oscillator output is routed to line side. Open Pin 1-2 CONFIG [1] will connect to P2_LED[2] pin of 88E1340S. Open Pin 2-3 CONFIG [1] will connect to SmartFusion2- J8 pin MSIO80NB3. Open Clocks J10 J9 J8 J11 Jumper to select the output enables control for the line side outputs. Jumper to select the output enables control for the line side outputs. Jumper to select switch-side Mux inputs of A or B to the line side. Marvell PHY J14 Jumper to select either M2S_PHY_CONFIG1 for configuration CONFIG[1] PHY_CONFIG1 or Global hardware J15 Jumper to short AC test points for debugging (It is recommended not to connect, refer to Mavell PHY Datasheet) Two pin header Open J23 Jumper to provide the VBUS supply to USB when used in Host mode. Two pin header Open JTAG selection jumper to select between RVI header or FP4 header for application debug. Pin 1-2 FP4 for Soft Console/Flash Pro Close Programming J32 J121 J124 J125 J118 11 To select FTDI JTAG/ SPI Slave programming. To select JTAG programming via FP4 or FTDI To select FTDI SPI-0 or FTDI SPI-1 slave programming To select programming SPI-0 flash through FTDI SPI-0 (Port-B) or SmartFusion2 SPI-0 ™ Pin 2-3 RVI for Keil ULINK /IAR J-Link ® Open Pin 2-4 for JTAG_SEL pin to DD1 signal of FT4232H chip. Open Pin 1-2 FTDI JTAG programming Close Pin 2-3 FTDI SPI Slave Programming Open Pin 1-2 JTAG programming via FTDI Open Pin 2-3 JTAG programming via FP4 Close Pin 1-2 FTDI SPI-1 Slave programming Open Pin 2-3 FTDI SPI-0 Slave programming Open Pin 1-2 Programming SPI-0 flash via SmartFusion2 SPI-0. Close UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Hardware Installation Jumper J119 Description To select programming SPI-1 flash through FTDI SPI (Port-B) or SmartFusion2 SPI-1 Pin Default Settings Pin 2-3 Programming SPI-0 flash via FTDI SPI-0 (Port-B) and J125 pin 2-3 must be shorted. Open Pin 1-2 Programming SPI-1 flash via SmartFusion2 SPI-1. Close Pin 2-3 Programming SPI-1 flash via FTDI SPI (Port-B) and J125 pin 1-2 must be shorted. Open Table 4 · LEDs LED Description DS26 Indicates USB_5V supply. DS18 Indicates 0P75V_REG supply. DS19 Indicates 1P5V_REG supply. DS20 Indicates VDD_REG supply. DS21 Indicates 2P5V_LDO supply. DS22 Indicates VCCIO_LPC_VADJ supply. DS23 Indicates VCCIO_HPC_VADJ supply. DS24 Indicates 1P0V_PHY supply. DS25 Indicates 1P8V supply. DS28 Indicates 3P3V_LDO supply. DS17 Indicates 5P0V supply. DS29 Indicates 3P3V supply. DS16 Indicates 12P0V supply. DS27 Indicates VSS_BUS supply. DS8 Indicates that DS8 is connected to parallel LED output port 0 (P0_LED[0]) of Marvell PHY. DS9 Indicates that DS9 is connected to parallel LED output port 0 (P0_LED[2]) of Marvell PHY. DS10 Indicates that DS10 is connected to parallel LED output port 0 (P0_LED[3]) of Marvell PHY. DS14 Indicates that DS14 is connected to parallel LED output port 1 (P1_LED[0]) of Marvell PHY. DS13 Indicates that DS13 is connected to parallel LED output port 1 (P1_LED[1]) of Marvell PHY. DS12 Indicates that DS12 is connected to parallel LED output port 1 (P1_LED[2]) of Marvell PHY. DS11 Indicates that DS11 is connected to parallel LED output port 1 (P1_LED[3]) of Marvell PHY. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 12 2 – Installation and Settings Table 5 · Test Points Test Point Description TP20, TP33,TP16 GND TP7 VDD_REG TP12 12 V TP11 5V TP4 3.3 V TP29 VCCIO_HPC_VADJ TP28 VCCIO_LPC_VADJ TP30 3P3V_LDO TP31 2P5V_LDO TP9 1.5 V TP10 0.75 V TP14 1.8 V TP27 VDDIO for the USB device TP24 PHY 1.0 V 13 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Power Sources Power Sources Figure 3 shows the voltage rails (12 V, 5 V, 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V and 0.75 V) available in the SmartFusion2 Advanced Development Kit board. FMC HPC/2 A LX7165 U37 5 V/6 A PTH08T231 USB U58 FMC LPC/2 A LX7165 U60 3.3 V/1 A LX13043 PLL U61 0.75 V/1 A TPS51200 DDR3 VTT U32 1.5 V/2 A MIC69502 DDR3 U31 3.3 V/10 A PTH08T240 U27 12 V/5 A Power Jack- J42 1.8 V/2 A MIC69502 PHY/ USB U36 1.0 V/1.2 V/6 A PTH08T230 U26 VDDI17_18/2 A MIC69502 U41 2.5 V/1 A LX8240 PLL U62 1 V/1 A LX7186 PHY U28 Figure 3 · Voltage Rails in the SmartFusion2 Advanced Development Kit Board Voltage Rails Table 6 lists the major power supplies for normal operation of the M2S150-ADV-DEV-KIT Kit. Table 6 · I/O Voltage Rails SmartFusion2 Bank I/O Rail Voltage Bank0 VCCIO_HPC_VIO_B_M2S 3.3 V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V Bank1 2P5V_LDO 2.5 V Bank2 1P5V_REG 1.5 V Bank3 3P3V 3.3 V Bank4 3P3V 3.3 V Bank5 VCCIO_HPC_VIO_B_M2S 3.3 V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V Bank6 VCCIO_LPC_VADJ 2.5 V, 1.8 V, 1.5 V, or 1.2 V Bank7 3P3V 3.3 V UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 14 2 – Installation and Settings SmartFusion2 Bank I/O Rail Voltage Bank8 VCCIO_LPC_VADJ 2.5 V, 1.8 V, 1.5 V, or 1.2 V Bank9 2P5V_LDO 2.5 V Bank10 2P5V_LDO 2.5 V Bank11 VCCIO_HPC_VADJ 3.3 V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V Bank12 2P5V_LDO 2.5 V Bank13 2P5V_LDO 2.5 V Bank14 VCCIO_HPC_VADJ 3.3 V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V Bank15 VCCIO_LPC_VADJ 2.5 V, 1.8 V, 1.5 V, or 1.2 V Bank16 VCCIO_LPC_VADJ 2.5 V, 1.8 V, 1.5 V, or 1.2 V Bank17 VCCIO_HPC_VADJ 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V Bank18 VCCIO_HPC_VADJ 3.3 V, 2.5 V, 1.8 V, 1.5 V, or1.2 V VDD VDD_REG 1.2 V or 1.0 V VPP 3P3V_VPP 3.3 V VREF1 VREF1 0.75 V VREF2 0P75V_VTT_REF 0.75 V SERDES_x_PLL_VDDA PLL_SERDESx_VDDA 3.3 V SERDES_x_L01_VDDAPLL SERDESx_VDDPLL 2.5 V SERDES_x_VDD VDD_REG 1.2 V or 1.0 V 15 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 3 – Key Components Description and Operation This section describes the key component interfaces of the SmartFusion2 Advanced Development Kit. For device datasheets, refer to: http://www.microsemi.com/products/fpga-soc/design-resources/dev-kits/smartfusion2-kits Powering Up the Board The board is run a by 12 V power source using an external DC jack, refer to Figure 4. External DC Jack (12P0V_Ext) 1. Connect the 12 V power supply brick to J42 to supply power to the board. 2. Switch ON the SW7 power supply switch. 12P0V_Ext 12P0V_IN 12P0V SW7 2 1 3 W116 5 4 6 ENABLE_FT4232 Figure 4 · Powering Up the Board Current Measurement 1.0 V or 1.2 V Current Sensing for Normal Operation For applications that require current measurement, a high precision Operational Amplifier circuitry (U59 with gain 100) is provided on the board to measure the output voltage at test point TP17. The following steps describe how to measure the core power: 1. Measure the output voltage (Vout) at TP17. 2. I = (Vout/5) 3. Core Power consumed, P= (1.2 V)*I For example, when the voltage measured across TP17 is 0.5 V then the consumed core power is 0.12 W. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 16 3 – Key Components Description and Operation 12 V 5.0 V TP17 U59 1.2 V Gain 100 0.05Ω_1% 1 V or 1.2 V Regulator TP3 TP7 PTH08T230WAZ Figure 5 · Core Power Measurement Figure 5 shows the on board core power measurement circuitry. 1.2 V Current Sensing for Flash*Freeze The SmartFusion2 device consumes very less power in the Flash*Freeze mode. The voltage across the sense resistor (0.05 Ω) must be measured directly using a precision digital multi-meter that can read sub milli-volts. Use test points TP3 and TP7 to directly measure the voltage across the 1.2 V sense resistor. To convert the voltage measured across sense resistor to power, use the following equation: Note: Accuracy is ± 10%. 𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 = ( voltage_measured_in_milli_volts ) ∗ 1.2 0.05 EQ1 Memory Interface Dedicated I/Os are provided for the MSS DRR and fabric DDR for the SmartFusion2 device. Refer to Figure 5. DDR3 SDRAM Four chips having 256 MB DDR3 memory are provided as flexible volatile memories for storing user applications and a chip having 256 MB DDR3 memory is provided for ECC. You can enable SECDED feature using ECC. The DDR3 interface is implemented in Bank2. • MT41K256M8: 32 Meg × 8 × 8 banks • Density: 256 MB • Clock rate: 800 MHz • Data rate: DDR3 – 1600 • Total capacity: 1 GB from four chips Note: For more information, refer to page 3 of Board Level Schematics document (provided separately). 17 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Memory Interface U2 CK, CK# Data DQ[7:0] MDDR - Bank2 DQS/DQS# Address A[15:0] DDR3 SDRAM 256 MB 256MX8 Control lines U3 CK, CK# Data DQ[15:8] MDDR - Bank2 DQS/DQS# Address A[15:0] DDR3 SDRAM 256 MB 256MX8 Control lines U4 CK, CK# Data DQ[23:16] MDDR - Bank2 DQS/DQS# Address A[15:0] DDR3 SDRAM 256 MB 256MX8 Control lines SmartFusion2 U5 CK, CK# Data DQ[31:24] MDDR - Bank2 DQS/DQS# Address A[15:0] DDR3 SDRAM 256 MB 256MX8 Control lines U6 MDDR CB[3:0] Address A[15:0] CK, CK# MDDR - Bank2 DDR3 SDRAM 256 MB 256MX8 Single bit error correction and dual bit error detection (SECDED) Control lines CBS/CBS# Figure 6 · Memory Interface UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 18 3 – Key Components Description and Operation SERDES Interface The Advanced Development Kit has x4 SERDES interfaces. The SERDES block can be accessed using the PCIe edge connector, high speed sub-miniature version-A (SMA) connectors, and/or an on-board FPGA mezzanine card (FMC) connector-LPC (J60). SERDES0 Interface The SERDES 0 (lane0/1/2/3) is directly routed to the PCIe connector. • SERDES0 reference clock 0 is directly routed from the PCIe connector. • SERDES0 reference clock 1 is directly routed from the 100 MHz differential clock source (LVDS clock oscillator) through the resistors. SERDES0 Lane0/ RXD SERDES0 Lane1/ RXD SERDES0 Lane2/ RXD SERDES0 Lane3/ RXD PCIe Edge connector SmartFusion2 SERDES0 Lane0/ TXD SERDES0 Lane1/ TXD SERDES0 Lane2/ TXD SERDES0 Lane3/ TXD SERDES0 REFCLK0 SERDES0 REFCLK1 100 MHz Diff clock source Figure 7 · SERDES0 Interface Note: • SERDES0 TXD pairs are capacitively coupled to the SmartFusion2 device. Series AC coupling capacitors are used to set the common mode voltage. • Mount R977 and R978 to source the clock from 100 MHz differential oscillator to the SERDES0 REFCLK 1. • For more information, refer to page 4 of Board Level Schematics document (provided separately). 19 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide SERDES Interface SERDES1 Interface The SERDES1 (lane 0/1/2/3) is routed to the FMC connector. • SERDES1 reference clock 0 is routed from the FMC connector. • SERDES1 reference clock 1 is routed from the FMC connector through the Clock buffer. The output of the clock buffer is additionally routed to the SmartFusion2 Advanced Development Kit board pins - AF18 and AG18. Refer to Figure 8. SERDES1 Lane0/ RXD SERDES1 Lane1/ RXD SERDES1 Lane2/ RXD SERDES1 Lane3/ RXD SmartFusion2 FMC Connector (HPC-J30) SERDES1 Lane0/ TXD SERDES1 Lane1/ TXD SERDES1 Lane2/ TXD SERDES1 Lane3/ TXD SERDES1 REFCLK0 SERDES1 REFCLK1 AJ20 AK20 Clock Buffer AF18 AG18 Figure 8 · SERDES1 Interface Note: • SERDES1 TXD pairs are capacitively coupled to the SmartFusion2 device. Series AC coupling capacitors are used to set the common mode voltage. • For more information, refer to page 5 of Board Level Schematics document (provided separately). UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 20 3 – Key Components Description and Operation SERDES2 Interface The SERDES2 (lane 0/1/2/3) is routed to the FMC connector. • SERDES2 reference clock 0 is routed from the FMC connector. • SERDES2 reference clock 1 is routed from the FMC connector through the Clock buffer. The output of the clock buffer is additionally routed to the SmartFusion2 Advanced Development Kit board pins - AE17 and AF17. Refer to Figure 9. SERDES2 Lane0/ RXD SERDES2 Lane1/ RXD SERDES2 Lane2/ RXD SERDES2 Lane3/ RXD SmartFusion2 FMC connector (HPC-J30) SERDES2 Lane0/ TXD SERDES2 Lane1/ TXD SERDES2 Lane2/ TXD SERDES2 Lane3/ TXD SERDES2 REFCLK0 AK12 SERDES2 REFCLK1 AJ12 Clock Buffer AE17 AF17 Figure 9 · SERDES2 Interface Note: • SERDES2 TXD pairs are capacitively coupled to the SmartFusion2 device. Series AC coupling capacitors are used to set the common mode voltage. • For more information, refer to page 6 of Board Level Schematics document (provided separately). 21 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide SERDES Interface SERDES3 Interface The SERDES3 Lane-0 is connected to the FMC connector, Lane-1 is connected to the SMA connectors, and Lane-2 and 3 are connected to the Marvell PHY device of port-0 and 1, respectively. • SERDES3 Reference clock 0 is connected from FMC connector or SMA connector options through MUX. • SERDES3 Reference clock 1 is connected from 125 MHz or 100 MHz options through MUX. Refer to Figure 10. SERDES3 Lane0/ RXD FMC Connector (LPC-J60) SERDES3 Lane0/ TXD SERDES3 Lane1/ RXD SERDES3 Lane1/ TXD SmartFusion2 0 1 SERDES3 Lane2/ RXD P0 Magnetics/ J19 Jack- RJ45 2 SERDES3 Lane2/ TXD 3 Marvell PHY 0 1 SERDES3 Lane3/ RXD P1 Magnetics/ J21 Jack- RJ45 2 SERDES3 Lane3/ TXD 3 3.3 V MUX Circuit- U7 J8 Enable SERDES3 REFCLK1 O/Ps Marvell PHY A 125MHz B 100MHz 3.3 V MUX Channle-0 J11 MUX Sel 3.3 V J9 Enable SERDES3 REFCLK0 A O/Ps FMC Connector B SMA 3.3 V MUX Channel-1 MUX Sel J10 Figure 10 · SERDES3 Interface Note: • SERDES3 TXD pairs are capacitively coupled to the SmartFusion2 device. Series AC coupling capacitors are used to set the common mode voltage. • For more information, refer to page 7 of Board Level Schematics document (provided separately). UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 22 3 – Key Components Description and Operation USB Interface The SMSC USB3320 is a high speed USB 2.0 ULPI transceiver. It uses the industry standard UTMI+ low pin count to connect the USB transceiver to the link. In the SmartFusion2 Advanced Development Kit, the USB interface operates in the Host, Device or OTG mode. For Device mode, J23 can be in open or short position. CPEN U12 U10 5P0V MAX1823B REFCLK Jumper 26 MHz XO VBUS SmartFusion2 Device Capable 20K J23 VBUS 2.2uF P1 VBUS ID USB- PHY USB3320 Micro-AB USB Connector DM Control lines Bank3 DP DATA[7:0] ESD Diodes Figure 11 · USB Interface Note: CPEN: External 5 V supply enables. It controls the external VBUS power switch. Table 7 · USB Interface Operating Modes Operating Mode Terminals USB – Host or OTG J23 - 1 and 2 - Close Note: For more information, refer to page 10 of Board Level Schematics document (provided separately). Marvell PHY (88E1340S) The SmartFusion2 Advanced Development Kit uses the on board Marvell Alaska PHY device (88E1340S) for Ethernet communications at 100 or 1000 Mbps. The 88E1340S device has four independent Giga Bit Ethernet transceivers, but the board uses only two transceivers. Each transceiver performs all the physical layer functions for 100BASE-TX and 1000BASE-T full or half-duplex Ethernet on the CAT5 twisted pair cable. The PHY device is connected to a user-provided Ethernet cable through an RJ45 connector with built-in magnetics. The 88E1340S device supports the quad SGMII for direct connection to a SmartFusion2 chip. Refer to Figure 12. It is configured through the CONFIG [3:0] and CLK_SEL [1:0] pins. 23 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Marvell PHY (88E1340S) CLK_SEL [1:0] is used to select the reference clock input option. On board, the status of the CLK_SEL0 pin is High and CLK_SEL1 pin is Low. REF_CLK is a 125 MHz reference differential clock input (Y11). It consists of LVDS differential inputs with a 100 Ω differential internal termination resistor. • RCLK – Giga Bit recovered clock • SCLK – 25 MHz synchronous input reference clock • Expected reference clock (REF_CLK) specifications 1. Voltage level: 3.3 (± 0.3)V 2. Differential LVDS − Symmetry: 50% (± 10%) − Rise/Fall Time: 1 ns Max - 20% to 80% of supply (3.3 V) − Output Voltage Levels: 0 = 0.90 Minimum, 1.10 Typical − Differential Output Voltage: 247 mV Minimum, 454 mV Maximum 1 = 1.43 Typical, 1.60 Maximum F3 Bank3 K7 E2 F2 MDC/ MDIO/ INT/ PHY_RST N10 L7 RCLK1 RCLK2 SERDES3 Lane2/ RXD P0_Out SERDES3 Lane2/ TXD P0_In SERDES3 Lane3/ RXD P1_Out SERDES3 Lane3/ TXD P1_In P0 0 1 2 Magnetics/ J19 Jack- RJ45 3 P1 0 1 2 Magnetics/ J21 Jack- RJ45 3 Marvell PHY 88E1340S SmartFusion2 K6 3.3 V MUX Circuit- U7 Enable SERDES3 REFCLK1 3.3 V Level 1.8 V Translator SCLK O/Ps 25 MHz XTAL_IN XTAL_OUT REF_CLK A 125MHz B 100MHz 3.3 V MUX J16 Channle-0 Header J8 MUX Sel J11 JTAG Figure 12 · SmartFusion2 Marvell PHY Interface Note: For more information, refer to page 8 and 9 of Board Level Schematics document (provided separately). UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 24 3 – Key Components Description and Operation Programming The SmartFusion2 SoC FPGAs support multiple programming interfaces and can address a wide range of platform requirements. A SmartFusion2 device can be programmed through the JTAG and SPI interfaces. The dedicated programming SPI port can operate in SPI Slave or SPI Master mode. For more details, refer to SmartFusion2 and IGLOO2 Programming User Guide. SmartFusion2 JTAG ETM Header 1Gb SPI Flash Mux FP4 Header Mux Header D SC_SPI SPI1 RVI Header MUX SPI0 MUX UART0 1Gb SPI Flash Mux JTAG Mux Buffer C A B USB Mini-B Connector for Programming OSCI Serial EEPROM OSCO FT4232 12 MHz Figure 13 · Programming Interface Table 8 · Programming Jumper Selection J121 J124 J125 J32 X X X L IAR Debugging X L X H FP4 JTAG programming H H X H FTDI JTAG programming (Embedded FlashPro5 programming) L X X H FTDI SPI slave programming X X L X FTDI SPI-0 Programming X X H X FTDI SPI-1 Programming JTAG_SEL: The JTAG state machine is multiplexed with the CM3 debug port. JTAG_SEL is used to switch between JTAG Programming (High) and CM3 Debug (Low). When using the CM3 debug port, an option is available to switch to serial wire debug port. FLASH_GOLDEN_N: Signal tied high always to the supply VCCIO_HPC_VADJ (3.3 V). It indicates the SPI goes to Slave mode. 25 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FTDI Interface RVI Header: A 10X2 RVI header is provided on the board for debugging. This header allows plugging in the Keil ULINK debugger or IAR J-Link debugger to easily debug or configure the Cortex-M3 processor during board powerup. FlashPro4 Programming Header: The SmartFusion2 device on this Advanced Development Kit can be programmed using a FlashPro4 programmer. In addition, SoftConsole uses FlashPro4 for software debugging. Note: • For more information, refer to pages 24, 25, 26 of Board Level Schematics document (provided separately). • For Jumper Settings, refer to Programming and Debugging. FTDI Interface The FT4232H chip is a USB 2.0 high speed (480 Mbps) to UART/MPSSE interface. • Single-chip USB to quad serial ports with different configurations. • Entire USB protocol is handled in the chip. USB specific firmware programming is not required. • USB 2.0 high speed (480 Mbps) and full speed (12 Mbps) compatible. • Two MPSSEs on channel A and channel B to simplify synchronous serial protocol (USB to JTAG, I2C, SPI, or bit-bang) design. • Fully assisted hardware or X-On or X-Off software handshaking. • +1.8 V (chip core) and +3.3 V I/O interfacing (+5 V tolerant). • For interface details refer to Figure 13. System Reset The M2S_RSTB signal (active low) is generated by SW6 (push-button switch), U21 chip (DS1818), or U22 chip (TPS3808G09). DEVRST_N is an input-only reset pad that allows assertion of a full reset to the chip at any time. DS1818 maintains reset till 150 ms after the 3.3 V supply returns to an intolerance condition. The TPS3808G09DBVR device monitors the voltage of VDD_REG. If the voltage at this terminal SENSE drops below the threshold voltage of 0.9 V, the M2S_RSTB signal is asserted. 3.3V 10K U21 3.3 V DS1818 Reset Reset# M2S_RSTB SW6 1uF U22 VDD_REG DEVRST_n SmartFusion2 Push button switch TPS3808G09DBVR Sense Reset# Figure 14 · System Reset Interface Note: For more information, refer to page 26 of Board Level Schematics document (provided separately). UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 26 3 – Key Components Description and Operation Clock Oscillator A 50 MHz clock oscillator with an accuracy of +/-50 ppm is available on the board, refer to Figure 15. This clock oscillator is connected to the FPGA fabric to provide a system reference clock. An on-chip SmartFusion2 PLL can be configured to generate a wide range of high precision clock frequencies. Table 9 · 50 MHz Clock SmartFusion2 Advanced Development Kit Board Pin SmartFusion2 Package Pin Number SmartFusion2 Device Pin Name P1 MSIO39PB4/CCC_NE0_CLKI1 50MHZ_SECLK_B4_P1 1P8V TRISTATE VDD Osc- 50MHz GND 0 OUT SmartFusion2 B7_50MHz_U7 Figure 15 · 50 MHz - Clock Oscillator Interface Note: For more information, refer to page 11 of Board Level Schematics document (provided separately). A 100 MHz LVDS Clock Oscillator operating at 3.3 Volts with an accuracy of +/-50 ppm is available on the board (Figure 16). This clock oscillator is connected to the FPGA fabric to M1 and N1 pins. Table 10 · 100 MHz Clock SmartFusion2 Advanced Development Kit Board Pin SmartFusion2 Package Pin Number SmartFusion2 Device Pin Name 100MHZ_DIFFCLK_P N1 MSIO40PB4/CCC_NE1_CLKI1 100MHZ_DIFFCLK_N M1 MSIO40NB4 3P3V 3P3V 0 OE VDD Osc – 100 MHz SmartFusion2 0 100MHZ_DIFFCLK_P OUT+ N1 0 GND OUT- 100MHZ_DIFFCLK_N M1 Figure 16 · 100 MHz - Clock Oscillator Interface Note: For more information, refer to page 11 of Board Level Schematics document (provided separately). 27 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Debugging Debugging User LEDs The board has eight active high LEDs that are connected to the SmartFusion2 device. You can use these LEDs to debug applications. Table 11 · LEDs SmartFusion2 Advanced Development Kit Board Pin SmartFusion2 Package Pin Number SmartFusion2 Device Pin Name DS0 D26 DDRIO149PB1/FDDR_DQS2 DS1 F26 DDRIO150PB1/FDDR_DQ18 DS2 A27 DDRIO148PB1/FDDR_DM_RDQS2 DS3 C26 DDRIO149NB1/FDDR_DQS2_N DS4 C28 DDRIO151PB1/FDDR_DQ16 DS5 B27 DDRIO148NB1/FDDR_DQ20 DS6 C27 DDRIO151NB1/FDDR_DQ17 DS7 E26 DDRIO150NB1/FDDR_DQ19 3.3 V 499 2K SmartFusion2 1K Figure 17 · LEDs Interface Note: For more information, refer to page 25 of Board Level Schematics document (provided separately). Push-Button Switches The SmartFusion2 Advanced Development Kit comes with five push-button tactile switches that are connected to the SmartFusion2 device. Table 12 · Push-Button Switches SmartFusion2 Advanced Development Kit Board Pin SmartFusion2 Package Pin Number SmartFusion2 Device Pin Name SWITCH1 J25 DDRIO156PB1/FDDR_DQ10 SWITCH2 H25 DDRIO156NB1/FDDR_DQ11 SWITCH3 J24 DDRIO157PB1/FDDR_DQ8 SWITCH4 H23 DDRIO157NB1/FDDR_DQ9 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 28 3 – Key Components Description and Operation SmartFusion2 Advanced Development Kit Board Pin SmartFusion2 Package Pin Number SW6 AE5 SmartFusion2 Device Pin Name System Reset 2.5 V SWITCH1 SWITCH2 SmartFusion2 SWITCH3 SWITCH4 Figure 18 · Switches Interface Note: For more information, refer to page 25 of Board Level Schematics document (provided separately). Slide Switches - DPDT SW7: Power ON or OFF switch from external DC Jack (J42), +12 V DC. DIP Switch - SPST SW5: A DIP switch that has eight connections to the SmartFusion2 device. Table 13 · DIP Switches SmartFusion2 Advanced Development Kit Pin SmartFusion2 Package Pin Number SmartFusion2 Device Pin Name DIP0 F25 DDRIO152PB1/FDDR_DQ14 DIP1 G25 DDRIO152NB1/FDDR_DQ15 DIP2 J23 DDRIO153PB1/FDDR_DQ12 DIP3 J22 DDRIO153NB1/FDDR_DQ13 DIP4 G27 DDRIO154PB1/FDDR_TMATCH_0_IN DIP5 H27 DDRIO154NB1/FDDR_DM_RDQS1 DIP6 F23 DDRIO155PB1/FDDR_DQS1 DIP7 G23 DDRIO155NB1/FDDR_DQS1_N 29 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors 4.7 K 4.7 K 2P5_LDO 1 SW5 DIP0 DIP1 DIP2 DIP3 SmartFusion2 DIP4 DIP5 DIP6 DIP7 Figure 19 · SPST Interface Note: For more information, refer to page 20 of Board Level Schematics document (provided separately). FMC Connectors The Advanced Development Kit has HPC (J30) and LPC (J60) FMC connectors on the board for the daughter cards for the future expansion of interfaces. FMC Connector - HPC (J30) The SmartFusion2 MSIOs from Bank 0, 3, 5, 6, 8, 11, 14, 17, 18, SERDES 1, and SERDES2 signals are routed to the FMC connector for the application to be developed. If the FMC daughter board is designed as per VITA standard, bank-0 and bank-5 I/Os get power from the FMC daughter board. If it is not designed as per VITA standard, bank-0 and bank-5 I/Os get power from the onboard U37 regulator by mounting R1216 resistor. Table 14 · FMC Connector - J30 Pin Out FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name A1 GND A2 FMC_HPC_SERDES2_RXD2_P AM13 SERDES_2_RXD2_P A3 FMC_HPC_SERDES2_RXD2_N AL13 SERDES_2_RXD2_N A4 GND A5 GND UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 30 3 – Key Components Description and Operation FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name A6 FMC_HPC_SERDES2_RXD1_P AM15 SERDES_2_RXD1_P A7 FMC_HPC_SERDES2_RXD1_N AL15 SERDES_2_RXD1_N A8 GND A9 GND A10 FMC_HPC_SERDES2_RXD0_P AM17 SERDES_2_RXD0_P A11 FMC_HPC_SERDES2_RXD0_N AL17 SERDES_2_RXD0_N A12 GND A13 GND A14 FMC_HPC_SERDES1_RXD3_P AL19 SERDES_1_RXD3_P A15 FMC_HPC_SERDES1_RXD3_N AM19 SERDES_1_RXD3_N A16 GND A17 GND A18 FMC_HPC_SERDES1_RXD2_P AL21 SERDES_1_RXD2_P A19 FMC_HPC_SERDES1_RXD2_N AM21 SERDES_1_RXD2_N A20 GND A21 GND A22 FMC_HPC_SERDES2_TXD2_P AN12 SERDES_2_TXD2_P A23 FMC_HPC_SERDES2_TXD2_N AP12 SERDES_2_TXD2_N A24 GND A25 GND A26 FMC_HPC_SERDES2_TXD1_P AN14 SERDES_2_TXD1_P A27 FMC_HPC_SERDES2_TXD1_N AP14 SERDES_2_TXD1_N A28 GND A29 GND A30 FMC_HPC_SERDES2_TXD0_P AN16 SERDES_2_TXD0_P A31 FMC_HPC_SERDES2_TXD0_N AP16 SERDES_2_TXD0_N A32 GND A33 GND A34 FMC_HPC_SERDES1_TXD3_P AP18 SERDES_1_TXD3_P A35 FMC_HPC_SERDES1_TXD3_N AN18 SERDES_1_TXD3_N 31 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name A36 GND A37 GND A38 FMC_HPC_SERDES1_TXD2_P AP20 SERDES_1_TXD2_P A39 FMC_HPC_SERDES1_TXD2_N AN20 SERDES_1_TXD2_N A40 GND B1 NC B2 GND B3 GND B4 - - NC - - B5 NC - - B6 GND B7 GND B8 NC - - B9 NC - - B10 GND B11 GND B12 FMC_HPC_SERDES1_RXD0_P AL25 SERDES_1_RXD0_P B13 FMC_HPC_SERDES1_RXD0_N AM25 SERDES_1_RXD0_N B14 GND B15 GND B16 FMC_HPC_SERDES1_RXD1_P AL23 SERDES_1_RXD1_P B17 FMC_HPC_SERDES1_RXD1_N AM23 SERDES_1_RXD1_N B18 GND B19 GND B20 FMC_HPC_SERDES1_REFCLK0_P AJ22 MSIOD271PB12/SERDES_1_REFCLK0_P B21 FMC_HPC_SERDES1_REFCLK0_N AK22 MSIOD271NB12/SERDES_1_REFCLK0_N B22 GND B23 GND B24 NC - - B25 NC - - UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 32 3 – Key Components Description and Operation FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name B26 GND B27 GND B28 NC - - B29 NC - - B30 GND B31 GND B32 FMC_HPC_SERDES1_TXD0_P AP24 SERDES_1_TXD0_P B33 FMC_HPC_SERDES1_TXD0_N AN24 SERDES_1_TXD0_N B34 GND B35 GND B36 FMC_HPC_SERDES1_TXD1_P AP22 SERDES_1_TXD1_P B37 FMC_HPC_SERDES1_TXD1_N AN22 SERDES_1_TXD1_N B38 GND B39 GND B40 NC C1 GND C2 FMC_HPC_SERDES2_TXD3_P AN10 SERDES_2_TXD3_P C3 FMC_HPC_SERDES2_TXD3_N AP10 SERDES_2_TXD3_N C4 GND C5 GND C6 FMC_HPC_SERDES2_RXD3_P AM11 SERDES_2_RXD3_P C7 FMC_HPC_SERDES2_RXD3_N AL11 SERDES_2_RXD3_N C8 GND C9 GND C10 HPC_LA06_M32_191P_B18 M32 MSIO191PB18 C11 HPC_LA06_M31_191N_B18 M31 MSIO191NB18 C12 GND C13 GND C14 HPC_LA10_T23_206P_B17 T23 MSIO206PB17 C15 HPC_LA10_T24_206N_B17 T24 MSIO206NB17 33 - - UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name C16 GND C17 GND C18 HPC_LA14_P29_198P_B17 P29 MSIO198PB17 C19 HPC_LA14_P28_198N_B17 P28 MSIO198NB17 C20 GND C21 GND C22 HPC_LA18_CC_U29_215P_B17 U29 MSIO215PB17/CCC_NW1_CLKI0 C23 HPC_LA18_CC_U30_215N_B17 U30 MSIO215NB17 C24 GND C25 GND C26 HPC_LA27_P34_208P_B17 P34 MSIO208PB17 C27 HPC_LA27_N34_208N_B17 N34 MSIO208NB17 C28 GND C29 GND C30 I2C0_SCL K10 MSIO81NB3/I2C_0_SCL/GPIO_31_B/USB_DATA1_C C31 I2C0_SDA K9 MSIO81PB3/I2C_0_SDA/GPIO_30_B/USB_DATA0_C C32 GND C33 GND C34 GND C35 12P0V C36 GND C37 12P0V C38 GND C39 3P3V C40 GND D1 HPC_PG_C2M_H6_77N_B3 H6 MSIO77NB3/MMUART_0_DSR/GPIO_20_B D2 GND D3 GND D4 FMC_HPC_SERDES2_REFCLK0_P AK14 MSIOD277PB10/SERDES_2_REFCLK0_P D5 FMC_HPC_SERDES2_REFCLK0_N AJ14 MSIOD277NB10/SERDES_2_REFCLK0_N UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 34 3 – Key Components Description and Operation FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name D6 GND D7 GND D8 HPC_LA01_CC_U27_216P_B17 U27 MSIO216PB17/CCC_NW0_CLKI0 D9 HPC_LA01_CC_U26_216N_B17 U26 MSIO216NB17 D10 GND D11 HPC_LA05_N23_186P_B18 N23 MSIO186PB18 D12 HPC_LA05_N24_186N_B18 N24 MSIO186NB18 D13 GND D14 HPC_LA09_R23_200P_B17 R23 MSIO200PB17 D15 HPC_LA09_R24_200N_B17 R24 MSIO200NB17 D16 GND D17 HPC_LA13_R26_202P_B17 R26 MSIO202PB17 D18 HPC_LA13_R25_202N_B17 R25 MSIO202NB17 D19 GND D20 HPC_LA17_CC_U31_213P_B17 U31 MSIO213PB17/GB6/CCC_NW1_CLKI1 D21 HPC_LA17_CC_U32_213N_B17 U32 MSIO213NB17 D22 GND D23 HPC_LA23_T33_212P_B17 T33 MSIO212PB17 D24 HPC_LA23_T32_212N_B17 T32 MSIO212NB17 D25 GND D26 HPC_LA26_L33_190P_B18 L33 MSIO190PB18 D27 HPC_LA26_L32_190N_B18 L32 MSIO190NB18 D28 GND D29 HPC_TCK D30 HPC_TDI D31 HPC_TDO D32 3P3V D33 HPC_TMS D34 HPC_TRST_L D35 GND 35 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name D36 3P3V D37 GND D38 3P3V D39 GND D40 3P3V E1 GND E2 HPC_HA01_CC_AF16_276P_B11 AF16 MSIO276PB11/GB11/VCCC_SE0_CLKI E3 HPC_HA01_CC_AG16_276N_B11 AG16 MSIO276NB11 E4 GND E5 GND E6 HPC_HA05_AA3_17P_B6 AA3 MSIO17PB6 E7 HPC_HA05_AA2_17N_B6 AA2 MSIO17NB6 E8 GND E9 HPC_HA09_AJ2_285P_B8 AJ2 MSIO285PB8 E10 HPC_HA09_AH3_285N_B8 AH3 MSIO285NB8 E11 GND E12 HPC_HA13_AH6_283P_B8 AH6 MSIO283PB8 E13 HPC_HA13_AH5_283N_B8 AH5 MSIO283NB8 E14 GND E15 HPC_HA16_AG7_284P_B8 AG7 MSIO284PB8 E16 HPC_HA16_AF7_284N_B8 AF7 MSIO284NB8 E17 GND E18 HPC_HA20_AB8_8P_B6 AB8 MSIO8PB6 E19 HPC_HA20_AB7_8N_B6 AB7 MSIO8NB6 E20 GND E21 HPC_HB03_W1_20P_B5 W1 MSIO20PB5 E22 HPC_HB03_W2_20N_B5 W2 MSIO20NB5 E23 GND E24 HPC_HB05_Y2_19P_B5 Y2 MSIO19PB5 E25 HPC_HB05_Y1_19N_B5 Y1 MSIO19NB5 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 36 3 – Key Components Description and Operation FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name E26 GND E27 HPC_HB09_V4_30P_B5 V4 MSIO30PB5/USB_DATA0_B E28 HPC_HB09_V5_30N_B5 V5 MSIO30NB5/USB_DATA1_B E29 GND E30 HPC_HB13_U2_29P_B5 U2 MSIO29PB5/USB_STP_B E31 HPC_HB13_U3_29N_B5 U3 MSIO29NB5/USB_NXT_B E32 GND E33 HPC_HB19_H31_175P_B0 H31 MSIO175PB0 E34 HPC_HB19_G31_175N_B0 G31 MSIO175NB0 E35 GND E36 HPC_HB21_L25_174P_B0 L25 MSIO174PB0 E37 HPC_HB21_L26_174N_B0 L26 MSIO174NB0 E38 GND E39 VCCIO_HPC_VADJ E40 GND F1 HPC_PG_M2C_J6_78P_B3 F2 GND F3 GND F4 HPC_HA00_CC_AJ4_282P_B8 AJ4 MSIO282PB8/VCCC_SE1_CLKI F5 HPC_HA00_CC_AJ3_282N_B8 AJ3 MSIO282NB8 F6 GND F7 HPC_HA04_AG3_287P_B8 AG3 MSIO287PB8 F8 HPC_HA04_AG4_287N_B8 AG4 MSIO287NB8 F9 GND F10 HPC_HA08_AD1_9P_B6 AD1 MSIO9PB6 F11 HPC_HA08_AC1_9N_B6 AC1 MSIO9NB6 F12 GND F13 HPC_HA12_AE4_4P_B6 AE4 MSIO4PB6 F14 HPC_HA12_AD4_4N_B6 AD4 MSIO4NB6 F15 GND 37 J6 MSIO78PB3/MMUART_0_RI/GPIO_21_B UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors FMC Pin NumberJ30 FMC Net Name F16 HPC_HA15_AA7_15P_B6 F17 HPC_HA15_Y7_15N_B6 F18 GND F19 SmartFusion2 Pin Number SmartFusion2 Pin name AA7 MSIO15PB6 Y7 MSIO15NB6 HPC_HA19_AB10_11P_B6 AB10 MSIO11PB6 F20 HPC_HA19_AA10_11N_B6 AA10 MSIO11NB6 F21 GND F22 HPC_HB02_V1_26P_B5 V1 MSIO26PB5/GPIO_27_A F23 HPC_HB02_U1_26N_B5 U1 MSIO26NB5/GPIO_28_A F24 GND F25 HPC_HB04_W3_25P_B5 W3 MSIO25PB5 F26 HPC_HB04_V3_25N_B5 V3 MSIO25NB5 F27 GND F28 HPC_HB08_Y6_18P_B5 Y6 MSIO18PB5 F29 HPC_HB08_Y5_18N_B5 Y5 MSIO18NB5 F30 GND F31 HPC_HB12_W8_27P_B5 W8 MSIO27PB5 F32 HPC_HB12_W9_27N_B5 W9 MSIO27NB5/USB_DATA7_B F33 GND F34 HPC_HB16_Y12_21P_B5 Y12 MSIO21PB5 F35 HPC_HB16_Y11_21N_B5 Y11 MSIO21NB5 F36 GND F37 HPC_HB20_W12_28P_B5 W12 MSIO28PB5/USB_XCLK_B F38 HPC_HB20_W11_28N_B5 W11 MSIO28NB5/USB_DIR_B F39 GND F40 VCCIO_HPC_VADJ G1 GND G2 HPC_CLK1_M2C_AH28_267P_B14 AH28 MSIO267PB14/CCC_SW0_CLKI2 G3 HPC_CLK1_M2C_AG27_267N_B14 AG27 MSIO267NB14 G4 GND G5 GND UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 38 3 – Key Components Description and Operation FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name G6 HPC_LA00_CC_U23_214P_B17 U23 MSIO214PB17/GB2/CCC_NW0_CLKI1 G7 HPC_LA00_CC_U24_214N_B17 U24 MSIO214NB17 G8 GND G9 HPC_LA03_N32_201P_B17 N32 MSIO201PB17 G10 HPC_LA03_N31_201N_B17 N31 MSIO201NB17 G11 GND G12 HPC_LA08_M25_181P_B18 M25 MSIO181PB18 G13 HPC_LA08_M24_181N_B18 M24 MSIO181NB18 G14 GND G15 HPC_LA12_M27_183P_B18 M27 MSIO183PB18 G16 HPC_LA12_M26_183N_B18 M26 MSIO183NB18 G17 GND G18 HPC_LA16_T28_209P_B17 T28 MSIO209PB17 G19 HPC_LA16_T27_209N_B17 T27 MSIO209NB17 G20 GND G21 HPC_LA20_R31_205P_B17 R31 MSIO205PB17 G22 HPC_LA20_R30_205N_B17 R30 MSIO205NB17 G23 GND G24 HPC_LA22_R33_207P_B17 R33 MSIO207PB17 G25 HPC_LA22_R32_207N_B17 R32 MSIO207NB17 G26 GND G27 HPC_LA25_M34_197P_B17 M34 MSIO197PB17 G28 HPC_LA25_L34_197N_B17 L34 MSIO197NB17 G29 GND G30 HPC_LA29_J34_194P_B18 J34 MSIO194PB18 G31 HPC_LA29_J33_194N_B18 J33 MSIO194NB18 G32 GND G33 HPC_LA31_H34_196P_B18 H34 MSIO196PB18 G34 HPC_LA31_G34_196N_B18 G34 MSIO196NB18 G35 GND 39 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name G36 HPC_LA33_E33_176P_B18 E33 MSIO176PB18 G37 HPC_LA33_D33_176N_B18 D33 MSIO176NB18 G38 GND G39 VCCIO_HPC_VADJ G40 GND H1 N36608719 H2 HPC_PRSNT_M2CL_J7_78N_B3 H3 GND H4 HPC_CLK0_M2C_AJ6_281P_B8 AJ6 MSIO281PB8/GB15/VCCC_SE1_CLKI H5 HPC_CLK0_M2C_AJ5_281N_B8 AJ5 MSIO281NB8 H6 GND H7 HPC_LA02_K31_179P_B18 K31 MSIO179PB18 H8 HPC_LA02_K30_179N_B18 K30 MSIO179NB18 H9 GND H10 HPC_LA04_L30_182P_B18 L30 MSIO182PB18 H11 HPC_LA04_L29_182N_B18 L29 MSIO182NB18 H12 GND H13 HPC_LA07_P23_192P_B18 P23 MSIO192PB18 H14 HPC_LA07_P24_192N_B18 P24 MSIO192NB18 H15 GND H16 HPC_LA11_T30_210P_B17 T30 MSIO210PB17 H17 HPC_LA11_T29_210N_B17 T29 MSIO210NB17 H18 GND H19 HPC_LA15_M30_188P_B18 M30 MSIO188PB18 H20 HPC_LA15_M29_188N_B18 M29 MSIO188NB18 H21 GND H22 HPC_LA19_P31_199P_B17 P31 MSIO199PB17 H23 HPC_LA19_P30_199N_B17 P30 MSIO199NB17 H24 GND H25 HPC_LA21_P33_203P_B17 P33 MSIO203PB17 J7 MSIO78NB3/MMUART_0_DCD/GPIO_22_B UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 40 3 – Key Components Description and Operation FMC Pin NumberJ30 FMC Net Name H26 HPC_LA21_N33_203N_B17 H27 GND H28 SmartFusion2 Pin Number SmartFusion2 Pin name N33 MSIO203NB17 HPC_LA24_K33_187P_B18 K33 MSIO187PB18 H29 HPC_LA24_K32_187N_B18 K32 MSIO187NB18 H30 GND H31 HPC_LA28_H33_184P_B18 H33 MSIO184PB18 H32 HPC_LA28_H32_184N_B18 H32 MSIO184NB18 H33 GND H34 HPC_LA30_F34_185P_B18 F34 MSIO185PB18 H35 HPC_LA30_F33_185N_B18 F33 MSIO185NB18 H36 GND H37 HPC_LA32_D34_180P_B18 D34 MSIO180PB18 H38 HPC_LA32_C34_180N_B18 C34 MSIO180NB18 H39 GND H40 VCCIO_HPC_VADJ J1 GND J2 HPC_CLK3_M2C_P AK12 MSIOD278PB10/SERDES_2_REFCLK1_P J2 HPC_CLK3_M2C_P AE17 MSIO275PB11/VCCC_SE0_CLKI J3 HPC_CLK3_M2C_N AJ12 MSIOD278NB10/SERDES_2_REFCLK1_N J3 HPC_CLK3_M2C_N AF17 MSIO275NB11 J4 GND J5 GND J6 HPC_HA03_AA4_12P_B6 AA4 MSIO12PB6 J7 HPC_HA03_AA5_12N_B6 AA5 MSIO12NB6 J8 GND J9 HPC_HA07_AC3_10P_B6 AC3 MSIO10PB6 J10 HPC_HA07_AB3_10N_B6 AB3 MSIO10NB6 J11 GND J12 HPC_HA11_AD3_5P_B6 AD3 MSIO5PB6 J13 HPC_HA11_AD2_5N_B6 AD2 MSIO5NB6 41 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name J14 GND J15 HPC_HA14_AG6_286P_B8 AG6 MSIO286PB8 J16 HPC_HA14_AG5_286N_B8 AG5 MSIO286NB8 J17 GND J18 HPC_HA18_AC9_3P_B6 AC9 MSIO3PB6 J19 HPC_HA18_AC8_3N_B6 AC8 MSIO3NB6 J20 GND J21 HPC_HA22_AA8_13P_B6 AA8 MSIO13PB6 J22 HPC_HA22_AA9_13N_B6 AA9 MSIO13NB6 J23 GND J24 HPC_HB01_R1_32P_B5 R1 MSIO32PB5/USB_DATA4_B J25 HPC_HB01_R2_32N_B5 R2 MSIO32NB5/USB_DATA5_B J26 GND J27 HPC_HB07_Y4_24P_B5 Y4 MSIO24PB5 J28 HPC_HB07_W4_24N_B5 W4 MSIO24NB5 J29 GND J30 HPC_HB11_W6_23P_B5 W6 MSIO23PB5 J31 HPC_HB11_W7_23N_B5 W7 MSIO23NB5 J32 GND J33 HPC_HB15_V9_34P_B5 V9 MSIO34PB5 J34 HPC_HB15_V10_34N_B5 V10 MSIO34NB5 J35 GND J36 HPC_HB18_T2_31P_B5 T2 MSIO31PB5/USB_DATA2_B J37 HPC_HB18_T3_31N_B5 T3 MSIO31NB5/USB_DATA3_B J38 GND J39 VCCIO_HPC_VIO_B_M2C_FMC J40 GND K1 N36626276 K2 GND K3 GND UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 42 3 – Key Components Description and Operation FMC Pin NumberJ30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name K4 HPC_CLK2_M2C_P AJ20 MSIOD272PB12/SERDES_1_REFCLK1_P K4 HPC_CLK2_M2C_P AF18 MSIO274PB11/CCC_SW1_CLKI2 K5 HPC_CLK2_M2C_N AK20 MSIOD272NB12/SERDES_1_REFCLK1_N K5 HPC_CLK2_M2C_N AG18 MSIO274NB11/CCC_SW1_CLKI3 K6 GND K7 HPC_HA02_AB2_16P_B6 AB2 MSIO16PB6 K8 HPC_HA02_AB1_16N_B6 AB1 MSIO16NB6 K9 GND K10 HPC_HA06_AC5_6P_B6 AC5 MSIO6PB6 K11 HPC_HA06_AC4_6N_B6 AC4 MSIO6NB6 K12 GND K13 HPC_HA10_AE6_288P_B8 AE6 MSIO288PB8 K14 HPC_HA10_AF5_288N_B8 AF5 MSIO288NB8 K15 GND K16 HPC_HA17_CC_AJ29_268P_B14 AJ29 MSIO268PB14/GB3/CCC_SW0_CLKI3 K17 HPC_HA17_CC_AJ28_268N_B14 AJ28 MSIO268NB14 K18 GND K19 HPC_HA21_AA12_14P_B6 AA12 MSIO14PB6 K20 HPC_HA21_AA11_14N_B6 AA11 MSIO14NB6 K21 GND K22 HPC_HA23_AB5_7P_B6 AB5 MSIO7PB6 K23 HPC_HA23_AB6_7N_B6 AB6 MSIO7NB6 K24 GND K25 HPC_HB00_CC_F32_172P_B0 F32 MSIO172PB0/GB0/CCC_NW0_CLKI3 K26 HPC_HB00_CC_E32_172N_B0 E32 MSIO172NB0 K27 GND K28 HPC_HB06_CC_J29_170P_B0 J29 MSIO170PB0/CCC_NW1_CLKI3 K29 HPC_HB06_CC_J28_170N_B0 J28 MSIO170NB0 K30 GND K31 HPC_HB10_Y10_22P_B5 Y10 MSIO22PB5 43 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors FMC Pin NumberJ30 FMC Net Name K32 HPC_HB10_Y9_22N_B5 K33 GND K34 SmartFusion2 Pin Number SmartFusion2 Pin name Y9 MSIO22NB5 HPC_HB14_V6_33P_B5 V6 MSIO33PB5/USB_DATA6_B K35 HPC_HB14_U6_33N_B5 U6 MSIO33NB5 K36 GND K37 HPC_HB17_CC_U5_37P_B5 U5 MSIO37PB5/GB9/VCCC_SE0_CLKI K38 HPC_HB17_CC_T5_37N_B5 T5 MSIO37NB5 K39 GND K40 VCCIO_HPC_VIO_B_M2C_FMC UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 44 3 – Key Components Description and Operation FMC Connector - J60 Pin Out The SmartFusion2 MSIODs from Bank 15, 16, and SERFDES3 lane-0 signals are routed to the FMC connector for the application to be developed. Table 15 · FMC Connector - J60 Pin Out FMC Pin Number J60 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin Name C1 GND C2 FMC_LPC_SERDES3_TXD0_P AN8 SERDES_3_TXD0_P C3 FMC_LPC_SERDES3_TXD0_N AP8 SERDES_3_TXD0_N C4 GND C5 GND C6 FMC_LPC_SERDES3_RXD0_P AM9 SERDES_3_RXD0_P C7 FMC_LPC_SERDES3_RXD0_N AL9 SERDES_3_RXD0_N C8 GND C9 GND C10 LPC_LA06_AF33_248P_B15 AF33 MSIOD248PB15 C11 LPC_LA06_AE33_248N_B15 AE33 MSIOD248NB15 C12 GND C13 GND C14 LPC_LA10_AE30_250P_B15 AE30 MSIOD250PB15 C15 LPC_LA10_AD30_250N_B15 AD30 MSIOD250NB15 C16 GND C17 GND C18 LPC_LA14_W23_227P_B16 W23 MSIOD227PB16 C19 LPC_LA14_W24_227N_B16 W24 MSIOD227NB16 C20 GND C21 GND C22 LPC_LA18_CC_AA32_228P_B16 AA32 MSIOD228PB16 C23 LPC_LA18_CC_Y32_228N_B16 Y32 MSIOD228NB16 C24 GND C25 GND C26 LPC_LA27_V29_223P_B16 V29 MSIOD223PB16 C27 LPC_LA27_V28_223N_B16 V28 MSIOD223NB16 C28 GND C29 GND C30 I2C1_SCL T8 MSIO45NB4/I2C_1_SCL/GPIO_1_A/USB_DATA4_A C31 I2C1_SDA T9 MSIO45PB4/I2C_1_SDA/GPIO_0_A/USB_DATA3_A C32 GND C33 GND C34 GND C35 12P0V C36 GND 45 - - UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors FMC Pin Number J60 FMC Net Name C37 12P0V C38 GND C39 3P3V C40 GND D1 LPC_PGC2M_N12_71P_B3 D2 GND D3 GND D4 SmartFusion2 Pin Number SmartFusion2 Pin Name - - - - N12 MSIO71PB3/MMUART_1_RTS/GPIO_11_B FMC_LPC_SERDES3_REFCLK0_P AJ10 MSIOD279PB9/SERDES_3_REFCLK0_P D5 FMC_LPC_SERDES3_REFCLK0_N AK10 MSIOD279NB9/SERDES_3_REFCLK0_N D6 GND D7 GND D8 LPC_LA01_CC_W34_219P_B16 W34 MSIOD219PB16/CCC_SW1_CLKI0 D9 LPC_LA01_CC_V34_219N_B16 V34 MSIOD219NB16 D10 GND D11 LPC_LA05_W29_226P_B16 W29 MSIOD226PB16 D12 LPC_LA05_W30_226N_B16 W30 MSIOD226NB16 D13 GND D14 LPC_LA09_Y28_231P_B16 Y28 MSIOD231PB16 D15 LPC_LA09_W28_231N_B16 W28 MSIOD231NB16 D16 GND D17 LPC_LA13_AC24_258P_B15 AC24 MSIOD258PB15 D18 LPC_LA13_AC23_258N_B15 AC23 MSIOD258NB15 D19 GND D20 LPC_LA17_CC_V23_220P_B16 V23 MSIOD220PB16/CCC_SW0_CLKI0 D21 LPC_LA17_CC_V24_220N_B16 V24 MSIOD220NB16 D22 GND D23 LPC_LA23_AG32_252P_B15 AG32 MSIOD252PB15 D24 LPC_LA23_AF32_252N_B15 AF32 MSIOD252NB15 D25 GND D26 LPC_LA26_V27_222P_B16 V27 MSIOD222PB16 D27 LPC_LA26_V26_222N_B16 V26 MSIOD222NB16 D28 GND D29 LPC_TCK - - D30 LPC_TDI - - D31 LPC_TDO - - D32 3P3V - - D33 LPC_TMS - - D34 LPC_TRST_L - - D35 GND UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 46 3 – Key Components Description and Operation FMC Pin Number J60 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin Name - - - - - - D36 3P3V D37 GND D38 3P3V D39 GND D40 3P3V G1 GND G2 LPC_CLK1_M2C_U34_217P_B16 U34 MSIOD217PB16/GB5/CCC_SW1_CLKI1 G3 LPC_CLK1_M2C_T34_217N_B16 T34 MSIOD217NB16 G4 GND G5 GND G6 LPC_LA00_CC_Y33_224P_B16 Y33 MSIOD224PB16 G7 LPC_LA00_CC_W33_224N_B16 W33 MSIOD224NB16 G8 GND G9 LPC_LA03_AC34_232P_B16 AC34 MSIOD232PB16 G10 LPC_LA03_AB34_232N_B16 AB34 MSIOD232NB16 G11 GND G12 LPC_LA08_AC32_233P_B16 AC32 MSIOD233PB16 G13 LPC_LA08_AC33_233N_B16 AC33 MSIOD233NB16 G14 GND G15 LPC_LA12_W26_229P_B16 W26 MSIOD229PB16 G16 LPC_LA12_W25_229N_B16 W25 MSIOD229NB16 G17 GND G18 LPC_LA16_Y23_234P_B16 Y23 MSIOD234PB16 G19 LPC_LA16_Y24_234N_B16 Y24 MSIOD234NB16 G20 GND G21 LPC_LA20_AF27_257P_B15 AF27 MSIOD257PB15 G22 LPC_LA20_AE27_257N_B15 AE27 MSIOD257NB15 G23 GND G24 LPC_LA22_AG34_244P_B15 AG34 MSIOD244PB15 G25 LPC_LA22_AF34_244N_B15 AF34 MSIOD244NB15 G26 GND G27 LPC_LA25_AH33_255P_B15 AH33 MSIOD255PB15 G28 LPC_LA25_AH34_255N_B15 AH34 MSIOD255NB15 G29 GND G30 LPC_LA29_AC27_245P_B15 AC27 MSIOD245PB15 G31 LPC_LA29_AB27_245N_B15 AB27 MSIOD245NB15 G32 GND G33 LPC_LA31_AB24_251P_B15 AB24 MSIOD251PB15 G34 LPC_LA31_AB23_251N_B15 AB23 MSIOD251NB15 47 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide FMC Connectors FMC Pin Number J60 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin Name G35 GND G36 LPC_LA33_AD24_261P_B15 AD24 MSIOD261PB15 G37 LPC_LA33_AD25_261N_B15 AD25 MSIOD261NB15 G38 GND G39 VCCIO_LPC_VADJ G40 GND H1 N36478604 H2 LPC_PRSNTM2CL_N11_71N_B3 H3 GND H4 - - - - N11 MSIO71NB3/MMUART_1_DTR/GPIO_12_B LPC_CLK0_M2C_V32_218P_B16 V32 MSIOD218PB16/GB1/CCC_SW0_CLKI1 H5 LPC_CLK0_M2C_V33_218N_B16 V33 MSIOD218NB16 H6 GND H7 LPC_LA02_AA33_225P_B16 AA33 MSIOD225PB16 H8 LPC_LA02_AA34_225N_B16 AA34 MSIOD225NB16 H9 GND H10 LPC_LA04_AD33_239P_B16 AD33 MSIOD239PB16 H11 LPC_LA04_AD34_239N_B16 AD34 MSIOD239NB16 H12 GND H13 LPC_LA07_AE31_247P_B15 AE31 MSIOD247PB15 H14 LPC_LA07_AE32_247N_B15 AE32 MSIOD247NB15 H15 GND H16 LPC_LA11_AF30_254P_B15 AF30 MSIOD254PB15 H17 LPC_LA11_AG31_254N_B15 AG31 MSIOD254NB15 H18 GND H19 LPC_LA15_AF28_256P_B15 AF28 MSIOD256PB15 H20 LPC_LA15_AE28_256N_B15 AE28 MSIOD256NB15 H21 GND H22 LPC_LA19_AG30_260P_B15 AG30 MSIOD260PB15 H23 LPC_LA19_AF29_260N_B15 AF29 MSIOD260NB15 H24 GND H25 LPC_LA21_W31_221P_B16 W31 MSIOD221PB16 H26 LPC_LA21_V31_221N_B16 V31 MSIOD221NB16 H27 GND H28 LPC_LA24_AD28_249P_B15 AD28 MSIOD249PB15 H29 LPC_LA24_AD29_249N_B15 AD29 MSIOD249NB15 H30 GND H31 LPC_LA28_AB25_246P_B15 AB25 MSIOD246PB15 H32 LPC_LA28_AB26_246N_B15 AB26 MSIOD246NB15 H33 GND UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 48 3 – Key Components Description and Operation FMC Pin Number J60 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin Name H34 LPC_LA30_AC25_253P_B15 AC25 MSIOD253PB15 H35 LPC_LA30_AC26_253N_B15 AC26 MSIOD253NB15 H36 GND H37 LPC_LA32_AE26_259P_B15 AE26 MSIOD259PB15 H38 LPC_LA32_AD26_259N_B15 AD26 MSIOD259NB15 H39 GND H40 VCCIO_LPC_VADJ 49 - - UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 4 – Pin List Pin List Table 17 lists the SmartFusion2 M2S150TS-1FCG1152 device pins. Table 16 · Pin List Package Pin M2S150TS-1FCG1152 Pin Name A2 DDRIO82PB2/MDDR_ADDR14 A3 DDRIO86NB2/MDDR_ADDR7 A4 VSS A5 DDRIO88NB2/MDDR_ADDR4 A6 DDRIO87PB2/MDDR_ADDR5 A7 VSS A8 DDRIO97PB2/MDDR_DQ28 A9 VSS A10 DDRIO101PB2/MDDR_DQ24 A11 VSS A12 DDRIO112PB2/MDDR_DQ10 A13 VSS A14 DDRIO115PB2/MDDR_DQ5 A15 VSS A16 DDRIO119PB2/MDDR_DQ0 A17 VSS A18 DDRIO126NB1/FDDR_ADDR15 A19 DDRIO130PB1/FDDR_ODT A20 VSS A21 DDRIO140PB1/FDDR_DQ30 A22 VSS A23 DDRIO141PB1/FDDR_DQ28 A24 VSS A25 DDRIO147PB1/FDDR_DQ21 A26 VSS A27 DDRIO148PB1/FDDR_DM_RDQS2 A28 VSS A29 DDRIO162PB1/FDDR_DQ2 A30 VSS A31 DDRIO164PB1/FDDR_DQ_ECC1 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 50 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name A32 VSS A33 DDRIO165PB1/FDDR_DQ_ECC3 AA1 VSS AA2 MSIO17NB6 AA3 MSIO17PB6 AA4 MSIO12PB6 AA5 MSIO12NB6 AA6 VDDI6 AA7 MSIO15PB6 AA8 MSIO13PB6 AA9 MSIO13NB6 AA10 MSIO11NB6 AA11 MSIO14NB6 AA12 MSIO14PB6 AA13 VDDI6 AA14 VSS AA15 VPP AA16 VSS AA17 VPP AA18 VSS AA19 VPP AA20 VSS AA21 CCC_SW1_PLL_VSSA AA22 CCC_SW0_PLL_VSSA AA23 CCC_SW0_PLL_VDDA AA24 VSS AA25 MSIOD241PB16 AA26 VDDI16 AA27 MSIOD238PB16 AA28 MSIOD238NB16 AA29 MSIOD237PB16 AA30 MSIOD237NB16 AA31 VSS AA32 MSIOD228PB16 AA33 MSIOD225PB16 AA34 MSIOD225NB16 AB1 MSIO16NB6 51 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name AB2 MSIO16PB6 AB3 MSIO10NB6 AB4 VSS AB5 MSIO7PB6 AB6 MSIO7NB6 AB7 MSIO8NB6 AB8 MSIO8PB6 AB9 VDDI6 AB10 MSIO11PB6 AB11 CCC_SE1_PLL_VDDA AB12 CCC_SE0_PLL_VDDA AB13 CCC_SE0_PLL_VSSA AB14 SERDES_3_VDD AB15 VSS AB16 SERDES_2_VDD AB17 VSS AB18 SERDES_1_VDD AB19 VSS AB20 SERDES_0_VDD AB21 VSS AB22 VDDI15 AB23 MSIOD251NB15 AB24 MSIOD251PB15 AB25 MSIOD246PB15 AB26 MSIOD246NB15 AB27 MSIOD245NB15 AB28 VSS AB29 MSIOD242PB16 AB30 MSIOD242NB16 AB31 MSIOD236PB16 AB32 MSIOD236NB16 AB33 VDDI16 AB34 MSIOD232NB16 AC1 MSIO9NB6 AC2 VDDI6 AC3 MSIO10PB6 AC4 MSIO6NB6 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 52 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name AC5 MSIO6PB6 AC6 FLASH_GOLDEN_N AC7 VSS AC8 MSIO3NB6 AC9 MSIO3PB6 AC10 SC_SPI_SS AC11 SC_SPI_SDO AC12 CCC_SE1_PLL_VSSA AC13 SERDES_3_VDD AC14 VSS AC15 SERDES_2_VDD AC16 VSS AC17 VDD AC18 VSS AC19 SERDES_1_VDD AC20 VSS AC21 SERDES_0_VDD AC22 VSS AC23 MSIOD258NB15 AC24 MSIOD258PB15 AC25 MSIOD253PB15 AC26 MSIOD253NB15 AC27 MSIOD245PB15 AC28 MSIOD243PB16 AC29 MSIOD243NB16 AC30 VDDI16 AC31 MSIOD240NB16 AC32 MSIOD233PB16 AC33 MSIOD233NB16 AC34 MSIOD232PB16 AD1 MSIO9PB6 AD2 MSIO5NB6 AD3 MSIO5PB6 AD4 MSIO4NB6 AD5 VDDI6 AD6 VDDI8 AD7 MSIO289NB8 53 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name AD8 SC_SPI_SDI AD9 SC_SPI_CLK AD10 VSS AD11 VSS AD12 SERDES_3_L23_VDDAIO AD13 VSS AD14 SERDES_2_L23_VDDAIO AD15 VSS AD16 SERDES_2_L01_VDDAIO AD17 VSS AD18 SERDES_1_L23_VDDAIO AD19 VSS AD20 SERDES_1_L01_VDDAIO AD21 VSS AD22 SERDES_0_L01_VDDAIO AD23 VSS AD24 MSIOD261PB15 AD25 MSIOD261NB15 AD26 MSIOD259NB15 AD27 VDDI15 AD28 MSIOD249PB15 AD29 MSIOD249NB15 AD30 MSIOD250NB15 AD31 MSIOD240PB16 AD32 VSS AD33 MSIOD239PB16 AD34 MSIOD239NB16 AE1 JTAG_TDI/M3_TDI AE2 JTAG_TMS/M3_TMS/M3_SWDIO AE3 VSS AE4 MSIO4PB6 AE5 DEVRST_N AE6 MSIO288PB8 AE7 MSIO289PB8 AE8 VSS AE9 VSS AE10 VSS UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 54 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name AE11 SERDES_3_L23_VDDAIO AE12 VSS AE13 SERDES_3_L01_VDDAIO AE14 VSS AE15 SERDES_2_L01_VDDAIO AE16 VSS AE17 MSIO275PB11/CCC_SE0_CLKI2 AE18 VSS AE19 SERDES_1_L23_VDDAIO AE20 VSS AE21 SERDES_0_L23_VDDAIO AE22 VSS AE23 SERDES_0_L01_VDDAIO AE24 VSS AE25 VSS AE26 MSIOD259PB15 AE27 MSIOD257NB15 AE28 MSIOD256NB15 AE29 VSS AE30 MSIOD250PB15 AE31 MSIOD247PB15 AE32 MSIOD247NB15 AE33 MSIOD248NB15 AE34 VDDI15 AF1 VDDI7 AF2 JTAG_TDO/M3_TDO/M3_SWO AF3 JTAG_TCK/M3_TCK AF4 VSS AF5 MSIO288NB8 AF6 VSS AF7 MSIO284NB8 AF8 VSS AF9 SERDES_3_PLL_VSSA AF10 SERDES_3_PLL_VDDA AF11 VSS AF12 SERDES_3_L01_VDDAIO AF13 VSS 55 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name AF14 SERDES_2_L23_VDDAIO AF15 VSS AF16 MSIO276PB11/GB11/CCC_SE0_CLKI3 AF17 MSIO275NB11 AF18 MSIO274PB11/GB7/CCC_SW1_CLKI2 AF19 VSS AF20 SERDES_1_L01_VDDAIO AF21 VSS AF22 SERDES_0_L23_VDDAIO AF23 VSS AF24 SERDES_0_L01_VDDAPLL AF25 SERDES_0_L01_REFRET AF26 VSS AF27 MSIOD257PB15 AF28 MSIOD256PB15 AF29 MSIOD260NB15 AF30 MSIOD254PB15 AF31 VDDI15 AF32 MSIOD252NB15 AF33 MSIOD248PB15 AF34 MSIOD244NB15 AG1 JTAG_TRSTB/M3_TRSTB AG2 JTAGSEL AG3 MSIO287PB8 AG4 MSIO287NB8 AG5 MSIO286NB8 AG6 MSIO286PB8 AG7 MSIO284PB8 AG8 VSS AG9 SERDES_3_L23_REXT AG10 SERDES_3_L23_VDDAPLL AG11 SERDES_3_L01_VDDAPLL AG12 VSS AG13 SERDES_2_PLL_VSSA AG14 VSS AG15 SERDES_2_L23_VDDAPLL AG16 MSIO276NB11 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 56 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name AG17 VDDI11 AG18 MSIO274NB11/CCC_SW1_CLKI3 AG19 SERDES_1_L23_VDDAPLL AG20 VSS AG21 SERDES_1_L01_VDDAPLL AG22 VSS AG23 SERDES_0_L23_VDDAPLL AG24 SERDES_0_L23_REFRET AG25 SERDES_0_L01_REXT AG26 VSS AG27 MSIO267NB14 AG28 MSIO263NB14 AG29 MSIO263PB14 AG30 MSIOD260PB15 AG31 MSIOD254NB15 AG32 MSIOD252PB15 AG33 VSS AG34 MSIOD244PB15 AH1 XTLOSC_AUX_EXTAL AH2 VSS AH3 MSIO285NB8 AH4 VDDI8 AH5 MSIO283NB8 AH6 MSIO283PB8 AH7 VDDI8 AH8 VSS AH9 SERDES_3_L23_REFRET AH10 SERDES_3_L01_REXT AH11 SERDES_3_L01_REFRET AH12 SERDES_2_PLL_VDDA AH13 SERDES_2_L23_REXT AH14 SERDES_2_L23_REFRET AH15 SERDES_2_L01_VDDAPLL AH16 SERDES_2_L01_REXT AH17 MSIO273PB11/PROBE_A AH18 SERDES_1_PLL_VSSA AH19 SERDES_1_L23_REXT 57 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name AH20 SERDES_1_L23_REFRET AH21 SERDES_1_L01_REFRET AH22 SERDES_1_L01_REXT AH23 SERDES_0_PLL_VSSA AH24 SERDES_0_PLL_VDDA AH25 SERDES_0_L23_REXT AH26 VSS AH27 VDDI14 AH28 MSIO267PB14/CCC_SW0_CLKI2 AH29 MSIO266PB14 AH30 MSIO265NB14 AH31 MSIO265PB14 AH32 MSIO264PB14 AH33 MSIOD255PB15 AH34 MSIOD255NB15 AJ1 XTLOSC_AUX_XTAL AJ2 MSIO285PB8 AJ3 MSIO282NB8 AJ4 MSIO282PB8/CCC_SE1_CLKI3 AJ5 MSIO281NB8 AJ6 MSIO281PB8/GB15/CCC_SE1_CLKI2 AJ7 VSS AJ8 MSIOD280PB9/SERDES_3_REFCLK1_P AJ9 VDDI9 AJ10 MSIOD279PB9/SERDES_3_REFCLK0_P AJ11 VSS AJ12 MSIOD278NB10/SERDES_2_REFCLK1_N AJ13 VDDI10 AJ14 MSIOD277NB10/SERDES_2_REFCLK0_N AJ15 VSS AJ16 SERDES_2_L01_REFRET AJ17 MSIO273NB11/PROBE_B AJ18 SERDES_1_PLL_VDDA AJ19 VSS AJ20 MSIOD272PB12/SERDES_1_REFCLK1_P AJ21 VDDI12 AJ22 MSIOD271PB12/SERDES_1_REFCLK0_P UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 58 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name AJ23 VSS AJ24 MSIOD270PB13/SERDES_0_REFCLK1_P AJ25 VDDI13 AJ26 MSIOD269PB13/SERDES_0_REFCLK0_P AJ27 VSS AJ28 MSIO268NB14 AJ29 MSIO268PB14/GB3/CCC_SW0_CLKI3 AJ30 MSIO266NB14 AJ31 VDDI14 AJ32 MSIO264NB14 AJ33 MSIO262NB14 AJ34 MSIO262PB14 AK1 XTLOSC_MAIN_EXTAL AK2 VSS AK3 VSS AK4 VSS AK5 VSS AK6 VSS AK7 VSS AK8 MSIOD280NB9/SERDES_3_REFCLK1_N AK9 VSS AK10 MSIOD279NB9/SERDES_3_REFCLK0_N AK11 VSS AK12 MSIOD278PB10/SERDES_2_REFCLK1_P AK13 VSS AK14 MSIOD277PB10/SERDES_2_REFCLK0_P AK15 VSS AK16 VSS AK17 VSS AK18 VSS AK19 VSS AK20 MSIOD272NB12/SERDES_1_REFCLK1_N AK21 VSS AK22 MSIOD271NB12/SERDES_1_REFCLK0_N AK23 VSS AK24 MSIOD270NB13/SERDES_0_REFCLK1_N AK25 VSS 59 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name AK26 MSIOD269NB13/SERDES_0_REFCLK0_N AK27 VSS AK28 VSS AK29 VSS AK30 VSS AK31 VSS AK32 VSS AK33 VSS AK34 VSS AL1 XTLOSC_MAIN_XTAL AL2 VSS AL3 SERDES_3_RXD3_N AL4 VSS AL5 SERDES_3_RXD2_N AL6 VSS AL7 SERDES_3_RXD1_N AL8 VSS AL9 SERDES_3_RXD0_N AL10 VSS AL11 SERDES_2_RXD3_N AL12 VSS AL13 SERDES_2_RXD2_N AL14 VSS AL15 SERDES_2_RXD1_N AL16 VSS AL17 SERDES_2_RXD0_N AL18 VSS AL19 SERDES_1_RXD3_P AL20 VSS AL21 SERDES_1_RXD2_P AL22 VSS AL23 SERDES_1_RXD1_P AL24 VSS AL25 SERDES_1_RXD0_P AL26 VSS AL27 SERDES_0_RXD3_P AL28 VSS UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 60 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name AL29 SERDES_0_RXD2_P AL30 VSS AL31 SERDES_0_RXD1_P AL32 VSS AL33 SERDES_0_RXD0_P AL34 VSS AM1 VSS AM2 VSS AM3 SERDES_3_RXD3_P AM4 VSS AM5 SERDES_3_RXD2_P AM6 VSS AM7 SERDES_3_RXD1_P AM8 VSS AM9 SERDES_3_RXD0_P AM10 VSS AM11 SERDES_2_RXD3_P AM12 VSS AM13 SERDES_2_RXD2_P AM14 VSS AM15 SERDES_2_RXD1_P AM16 VSS AM17 SERDES_2_RXD0_P AM18 VSS AM19 SERDES_1_RXD3_N AM20 VSS AM21 SERDES_1_RXD2_N AM22 VSS AM23 SERDES_1_RXD1_N AM24 VSS AM25 SERDES_1_RXD0_N AM26 VSS AM27 SERDES_0_RXD3_N AM28 VSS AM29 SERDES_0_RXD2_N AM30 VSS AM31 SERDES_0_RXD1_N 61 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name AM32 VSS AM33 SERDES_0_RXD0_N AM34 VSS AN1 VSS AN2 SERDES_3_TXD3_P AN3 VSS AN4 SERDES_3_TXD2_P AN5 VSS AN6 SERDES_3_TXD1_P AN7 VSS AN8 SERDES_3_TXD0_P AN9 VSS AN10 SERDES_2_TXD3_P AN11 VSS AN12 SERDES_2_TXD2_P AN13 VSS AN14 SERDES_2_TXD1_P AN15 VSS AN16 SERDES_2_TXD0_P AN17 VSS AN18 SERDES_1_TXD3_N AN19 VSS AN20 SERDES_1_TXD2_N AN21 VSS AN22 SERDES_1_TXD1_N AN23 VSS AN24 SERDES_1_TXD0_N AN25 VSS AN26 SERDES_0_TXD3_N AN27 VSS AN28 SERDES_0_TXD2_N AN29 VSS AN30 SERDES_0_TXD1_N AN31 VSS AN32 SERDES_0_TXD0_N AN33 VSS AN34 VSS UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 62 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name AP2 SERDES_3_TXD3_N AP3 VSS AP4 SERDES_3_TXD2_N AP5 VSS AP6 SERDES_3_TXD1_N AP7 VSS AP8 SERDES_3_TXD0_N AP9 VSS AP10 SERDES_2_TXD3_N AP11 VSS AP12 SERDES_2_TXD2_N AP13 VSS AP14 SERDES_2_TXD1_N AP15 VSS AP16 SERDES_2_TXD0_N AP17 VSS AP18 SERDES_1_TXD3_P AP19 VSS AP20 SERDES_1_TXD2_P AP21 VSS AP22 SERDES_1_TXD1_P AP23 VSS AP24 SERDES_1_TXD0_P AP25 VSS AP26 SERDES_0_TXD3_P AP27 VSS AP28 SERDES_0_TXD2_P AP29 VSS AP30 SERDES_0_TXD1_P AP31 VSS AP32 SERDES_0_TXD0_P AP33 VSS B1 VSS B2 DDRIO82NB2/MDDR_ADDR15 B3 DDRIO86PB2/MDDR_ODT B4 DDRIO88PB2/MDDR_ADDR3 B5 DDRIO87NB2/MDDR_ADDR6 63 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name B6 DDRIO89PB2/MDDR_ADDR1 B7 VDDI2 B8 DDRIO97NB2/MDDR_DQ29 B9 VDDI2 B10 DDRIO101NB2/MDDR_DQ25 B11 VDDI2 B12 DDRIO112NB2/MDDR_DQ11 B13 VDDI2 B14 DDRIO115NB2/MDDR_DQ6 B15 VDDI2 B16 DDRIO119NB2/MDDR_DQ1 B17 VDDI2 B18 DDRIO126PB1/FDDR_ADDR14 B19 DDRIO130NB1/FDDR_ADDR7 B20 VDDI1 B21 DDRIO140NB1/FDDR_DQ31 B22 VDDI1 B23 DDRIO141NB1/FDDR_DQ29 B24 VDDI1 B25 DDRIO147NB1/FDDR_DQ22 B26 VDDI1 B27 DDRIO148NB1/FDDR_DQ20 B28 VDDI1 B29 DDRIO162NB1/FDDR_DQ3 B30 VDDI1 B31 DDRIO164NB1/FDDR_DQ_ECC0 B32 VDDI1 B33 DDRIO165NB1/FDDR_DQ_ECC2 B34 VSS C1 DDRIO84NB2/MDDR_ADDR11 C2 DDRIO84PB2/MDDR_ADDR10 C3 VDDI2 C4 DDRIO83NB2/MDDR_ADDR13 C5 DDRIO92PB2/MDDR_CLK C6 DDRIO89NB2/MDDR_ADDR2 C7 DDRIO96PB2/MDDR_DQ30 C8 DDRIO99NB2/MDDR_DQS3_N UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 64 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name C9 DDRIO99PB2/MDDR_DQS3 C10 DDRIO100PB2/MDDR_DQ26 C11 DDRIO111NB2/MDDR_DQS1_N C12 DDRIO111PB2/MDDR_DQS1 C13 DDRIO113PB2/MDDR_DQ8 C14 DDRIO117NB2/MDDR_DQS0_N C15 DDRIO117PB2/MDDR_DQS0 C16 DDRIO118PB2/MDDR_DQ2 C17 DDRIO121PB2/MDDR_DQ_ECC3 C18 VDDI1 C19 DDRIO131NB1/FDDR_ADDR6 C20 DDRIO134NB1/FDDR_ADDR0 C21 DDRIO143NB1/FDDR_DQS3_N C22 DDRIO143PB1/FDDR_DQS3 C23 DDRIO144NB1/FDDR_DQ27 C24 DDRIO144PB1/FDDR_DQ26 C25 DDRIO146PB1/FDDR_DQ23 C26 DDRIO149NB1/FDDR_DQS2_N C27 DDRIO151NB1/FDDR_DQ17 C28 DDRIO151PB1/FDDR_DQ16 C29 DDRIO161NB1/FDDR_DQS0_N C30 DDRIO161PB1/FDDR_DQS0 C31 DDRIO167NB1/FDDR_DQS_ECC_N C32 DDRIO167PB1/FDDR_DQS_ECC C33 FDDR_IMP_CALIB C34 MSIO180NB18 D1 MSIO62NB3/USB_NXT_D D2 DDRIO85NB2/MDDR_ADDR9 D3 DDRIO85PB2/MDDR_ADDR8 D4 DDRIO83PB2/MDDR_ADDR12 D5 DDRIO92NB2/MDDR_CLK_N D6 VSS D7 DDRIO96NB2/MDDR_DQ31 D8 VSS D9 DDRIO100NB2/MDDR_DQ27 D10 VSS D11 DDRIO109PB2/MDDR_DQ12 65 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name D12 VSS D13 DDRIO113NB2/MDDR_DQ9 D14 VSS D15 DDRIO118NB2/MDDR_DQ3 D16 VSS D17 DDRIO121NB2/MDDR_DQ_ECC2 D18 DDRIO127PB1/FDDR_ADDR12 D19 DDRIO131PB1/FDDR_ADDR5 D20 DDRIO134PB1/FDDR_BA2 D21 VSS D22 DDRIO145PB1/FDDR_DQ24 D23 VSS D24 DDRIO146NB1/FDDR_TMATCH_1_OUT D25 VSS D26 DDRIO149PB1/FDDR_DQS2 D27 VSS D28 DDRIO159PB1/FDDR_DQ5 D29 VSS D30 DDRIO163NB1/FDDR_DQ1 D31 VSS D32 DDRIO169NB1 D33 MSIO176NB18 D34 MSIO180PB18 E1 MSIO62PB3/USB_STP_D E2 MSIO74PB3/USB_XCLK_C E3 MSIO74NB3/MMUART_1_TXD/GPIO_24_B/USB_DATA2_C E4 VSS E5 DDRIO91PB2/MDDR_BA0 E6 DDRIO90NB2/MDDR_ADDR0 E7 DDRIO95PB2/MDDR_RAS_N E8 VDDI2 E9 DDRIO98PB2/MDDR_TMATCH_1_IN E10 VDDI2 E11 DDRIO109NB2/MDDR_DQ13 E12 VDDI2 E13 DDRIO114NB2/MDDR_TMATCH_0_OUT E14 VDDI2 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 66 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name E15 DDRIO116NB2/MDDR_DQ4 E16 VDDI2 E17 DDRIO123NB2/MDDR_DQS_ECC_N E18 DDRIO127NB1/FDDR_ADDR13 E19 VSS E20 DDRIO136PB1/FDDR_CLK E21 VDDI1 E22 DDRIO145NB1/FDDR_DQ25 E23 VDDI1 E24 DDRIO142PB1/FDDR_TMATCH_1_IN E25 VDDI1 E26 DDRIO150NB1/FDDR_DQ19 E27 VDDI1 E28 DDRIO159NB1/FDDR_DQ6 E29 VDDI1 E30 DDRIO163PB1/FDDR_DQ0 E31 DDRIO169PB1/FDDR_TMATCH_ECC_OUT E32 MSIO172NB0 E33 MSIO176PB18 E34 VDDI18 F1 VDDI3 F2 MSIO73PB3/MMUART_1_RI/GPIO_15_B F3 MSIO73NB3/MMUART_1_DCD/GPIO_16_B F4 MSIO79PB3 F5 DDRIO91NB2/MDDR_BA1 F6 DDRIO90PB2/MDDR_BA2 F7 DDRIO95NB2/MDDR_WE_N F8 DDRIO98NB2/MDDR_DM_RDQS3 F9 DDRIO102NB2/MDDR_TMATCH_1_OUT F10 DDRIO108NB2/MDDR_DQ15 F11 DDRIO108PB2/MDDR_DQ14 F12 DDRIO110NB2/MDDR_DM_RDQS1 F13 DDRIO110PB2/MDDR_TMATCH_0_IN F14 DDRIO114PB2/MDDR_DQ7 F15 DDRIO116PB2/MDDR_DM_RDQS0 F16 DDRIO120PB2/MDDR_DQ_ECC1/GB12/CCC_NE1_CLKI2 F17 DDRIO123PB2/MDDR_DQS_ECC 67 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name F18 DDRIO128NB1/FDDR_ADDR11 F19 DDRIO132NB1/FDDR_ADDR4 F20 DDRIO136NB1/FDDR_CLK_N F21 DDRIO137NB1/FDDR_CAS_N F22 DDRIO137PB1/FDDR_RESET_N F23 DDRIO155PB1/FDDR_DQS1 F24 DDRIO142NB1/FDDR_DM_RDQS3 F25 DDRIO152PB1/FDDR_DQ14 F26 DDRIO150PB1/FDDR_DQ18 F27 DDRIO158NB1/FDDR_TMATCH_0_OUT F28 DDRIO158PB1/FDDR_DQ7 F29 DDRIO160NB1/FDDR_DQ4 F30 DDRIO166NB1/FDDR_DM_RDQS_ECC F31 DDRIO166PB1/FDDR_TMATCH_ECC_IN F32 MSIO172PB0/GB0/CCC_NW0_CLKI3 F33 MSIO185NB18 F34 MSIO185PB18 G1 MSIO61NB3/USB_DIR_D G2 MSIO69PB3/GPIO_7_B G3 MSIO69NB3/GPIO_8_B G4 VDDI3 G5 MSIO79NB3/MMUART_0_TXD/GPIO_27_B/USB_DIR_C G6 VDDI2 G7 DDRIO93NB2/MDDR_CAS_N G8 DDRIO93PB2/MDDR_RESET_N G9 VSS G10 DDRIO102PB2/MDDR_DQ23 G11 VSS G12 DDRIO105PB2/MDDR_DQS2 G13 VSS G14 DDRIO107PB2/MDDR_DQ16 G15 VSS G16 DDRIO120NB2/MDDR_DQ_ECC0/CCC_NE1_CLKI3 G17 VSS G18 DDRIO129NB1/FDDR_ADDR9 G19 DDRIO128PB1/FDDR_ADDR10 G20 DDRIO132PB1/FDDR_ADDR3 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 68 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name G21 DDRIO135PB1/FDDR_BA0 G22 VSS G23 DDRIO155NB1/FDDR_DQS1_N G24 VSS G25 DDRIO152NB1/FDDR_DQ15 G26 VSS G27 DDRIO154PB1/FDDR_TMATCH_0_IN G28 VSS G29 DDRIO160PB1/FDDR_DM_RDQS0 G30 MSIO171PB0/GB4/CCC_NW1_CLKI2 G31 MSIO175NB0 G32 VDDI0 G33 VSS G34 MSIO196NB18 H1 MSIO61PB3/USB_XCLK_D H2 VSS H3 MSIO70PB3/GPIO_9_B H4 MSIO70NB3/GPIO_10_B H5 MSIO77PB3/MMUART_0_CTS/GPIO_19_B/USB_DATA7_C H6 MSIO77NB3/MMUART_0_DSR/GPIO_20_B H7 MSIO80PB3/MMUART_0_RXD/GPIO_28_B/USB_STP_C H8 DDRIO94PB2/MDDR_CKE H9 VDDI2 H10 DDRIO103PB2/MDDR_DQ21 H11 VDDI2 H12 DDRIO105NB2/MDDR_DQS2_N H13 VDDI2 H14 DDRIO107NB2/MDDR_DQ17 H15 VDDI2 H16 DDRIO122PB2/MDDR_TMATCH_ECC_IN H17 VDDI2 H18 DDRIO129PB1/FDDR_ADDR8 H19 VSS H20 DDRIO135NB1/FDDR_BA1 H21 DDRIO138NB1/FDDR_CS_N H22 VDDI1 H23 DDRIO157NB1/FDDR_DQ9 69 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name H24 VDDI1 H25 DDRIO156NB1/FDDR_DQ11 H26 VDDI1 H27 DDRIO154NB1/FDDR_DM_RDQS1 H28 VDDI1 H29 MSIO171NB0 H30 VSS H31 MSIO175PB0 H32 MSIO184NB18 H33 MSIO184PB18 H34 MSIO196PB18 J1 MSIO56PB4/SPI_0_SS3/GPIO_10_A/USB_DATA7_A J2 MSIO56NB4/SPI_1_SS1/GPIO_14_A J3 MSIO65PB3/USB_DATA4_D J4 MSIO65NB3/USB_DATA5_D J5 VSS J6 MSIO78PB3/MMUART_0_RI/GPIO_21_B J7 MSIO78NB3/MMUART_0_DCD/GPIO_22_B J8 MSIO80NB3/MMUART_0_CLK/GPIO_29_B/USB_NXT_C J9 DDRIO94NB2/MDDR_CS_N J10 DDRIO103NB2/MDDR_DQ22 J11 DDRIO104NB2/MDDR_DQ20 J12 DDRIO104PB2/MDDR_DM_RDQS2 J13 DDRIO106NB2/MDDR_DQ19 J14 DDRIO106PB2/MDDR_DQ18 J15 DDRIO122NB2/MDDR_DM_RDQS_ECC J16 DDRIO125PB2/MDDR_TMATCH_ECC_OUT J17 DDRIO124NB2/GB8/CCC_NE0_CLKI3 J18 DDRIO124PB2/CCC_NE0_CLKI2 J19 DDRIO133NB1/FDDR_ADDR2 J20 DDRIO139PB1/FDDR_RAS_N J21 DDRIO138PB1/FDDR_CKE J22 DDRIO153NB1/FDDR_DQ13 J23 DDRIO153PB1/FDDR_DQ12 J24 DDRIO157PB1/FDDR_DQ8 J25 DDRIO156PB1/FDDR_DQ10 J26 DDRIO168NB1 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 70 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name J27 DDRIO168PB1 J28 MSIO170NB0 J29 MSIO170PB0/CCC_NW1_CLKI3 J30 MSIO177NB18 J31 MSIO177PB18 J32 VDDI18 J33 MSIO194NB18 J34 MSIO194PB18 K1 MSIO47PB4/SPI_0_SDO/GPIO_6_A/USB_STP_A K2 MSIO47NB4/SPI_0_SS0/GPIO_7_A/USB_NXT_A K3 VDDI4 K4 MSIO66PB3/USB_DATA6_D K5 MSIO66NB3/USB_DATA7_D/GPIO_23_B K6 MSIO72PB3/GPIO_13_B/MMUART_1_CTS K7 MSIO72NB3/MMUART_1_DSR/GPIO_14_B K8 VSS K9 MSIO81PB3/I2C_0_SDA/GPIO_30_B/USB_DATA0_C K10 MSIO81NB3/I2C_0_SCL/GPIO_31_B/USB_DATA1_C K11 MSS_MDDR_PLL_VSSA K12 MSS_MDDR_PLL_VDDA K13 VSS K14 VDDI2 K15 MDDR_IMP_CALIB K16 VSS K17 DDRIO125NB2 K18 VSS K19 DDRIO133PB1/FDDR_ADDR1 K20 DDRIO139NB1/FDDR_WE_N K21 VSS K22 VDDI1 K23 FDDR_PLL_VDDA K24 FDDR_PLL_VSSA K25 VSS K26 VDDI0 K27 MSIO173PB0/CCC_NW0_CLKI2 K28 MSIO173NB0 K29 VDDI18 71 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name K30 MSIO179NB18 K31 MSIO179PB18 K32 MSIO187NB18 K33 MSIO187PB18 K34 VSS L1 VSS L2 MSIO51PB4/SPI_1_SDO/GPIO_12_A L3 MSIO51NB4/SPI_1_SS0/GPIO_13_A L4 MSIO59PB4/GPIO_31_A L5 MSIO59NB4/GPIO_0_B L6 VDDI3 L7 MSIO68PB3/GPIO_5_B L8 MSIO68NB3/GPIO_6_B L9 MSIO75PB3/MMUART_1_CLK/GPIO_25_B/USB_DATA4_C L10 MSIO75NB3/MMUART_1_RXD/GPIO_26_B/USB_DATA3_C L11 VSS L12 CCC_NE0_PLL_VSSA L13 CCC_NE0_PLL_VDDA L14 VSS L15 VDDI2 L16 VSS L17 VDDI2 L18 VSS L19 VDDI1 L20 VSS L21 VDDI1 L22 VSS L23 CCC_NW0_PLL_VSSA L24 CCC_NW0_PLL_VDDA L25 MSIO174PB0 L26 MSIO174NB0 L27 MSIO178NB18 L28 MSIO178PB18 L29 MSIO182NB18 L30 MSIO182PB18 L31 VSS L32 MSIO190NB18 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 72 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name L33 MSIO190PB18 L34 MSIO197NB17 M1 MSIO40NB4 M2 MSIO48PB4/SPI_0_SS4/GPIO_19_A M3 MSIO48NB4/SPI_0_SS5/GPIO_20_A M4 VSS M5 MSIO55NB4/SPI_0_SS2/GPIO_9_A/USB_DATA6_A M6 MSIO60PB4/GPIO_1_B M7 MSIO60NB4/GPIO_2_B M8 MSIO63NB3/USB_DATA1_D M9 VDDI3 M10 MSIO76PB3/MMUART_0_RTS/GPIO_17_B/USB_DATA5_C M11 MSIO76NB3/MMUART_0_DTR/GPIO_18_B/USB_DATA6_C M12 CCC_NE1_PLL_VSSA M13 CCC_NE1_PLL_VDDA M14 VDDI2 M15 VSS M16 VDDI2 M17 VSS M18 VDDI1 M19 VSS M20 VDDI1 M21 VSS M22 CCC_NW1_PLL_VSSA M23 CCC_NW1_PLL_VDDA M24 MSIO181NB18 M25 MSIO181PB18 M26 MSIO183NB18 M27 MSIO183PB18 M28 VSS M29 MSIO188NB18 M30 MSIO188PB18 M31 MSIO191NB18 M32 MSIO191PB18 M33 VDDI17 M34 MSIO197PB17 N1 MSIO40PB4/CCC_NE1_CLKI1 73 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name N2 VDDI4 N3 MSIO49NB4/SPI_0_SS7/GPIO_22_A N4 MSIO49PB4/SPI_0_SS6/GPIO_21_A N5 MSIO55PB4/SPI_0_SS1/GPIO_8_A/USB_DATA5_A N6 MSIO53NB4/SPI_1_SS7/GPIO_24_A N7 VSS N8 MSIO63PB3/USB_DATA0_D N9 MSIO67PB3/GPIO_3_B N10 MSIO67NB3/GPIO_4_B N11 MSIO71NB3/MMUART_1_DTR/GPIO_12_B N12 MSIO71PB3/MMUART_1_RTS/GPIO_11_B N13 VDDI3 N14 VREF2 N15 VDDI2 N16 VREF2 N17 VREF2 N18 VREF1 N19 VDDI1 N20 VREF1 N21 VDDI1 N22 VREF1 N23 MSIO186PB18 N24 MSIO186NB18 N25 VSS N26 MSIO189NB18 N27 MSIO189PB18 N28 MSIO193NB18 N29 MSIO193PB18 N30 VDDI18 N31 MSIO201NB17 N32 MSIO201PB17 N33 MSIO203NB17 N34 MSIO208NB17 P1 MSIO39PB4/CCC_NE0_CLKI1 P2 MSIO39NB4 P3 MSIO43PB4 P4 MSIO43NB4/CAN_TX/GPIO_2_A/USB_DATA0_A UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 74 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name P5 VDDI4 P6 MSIO53PB4/SPI_1_SS6/GPIO_23_A P7 MSIO52NB4/SPI_1_SS5/GPIO_18_A P8 MSIO58PB4/GPIO_29_A P9 MSIO58NB4/GPIO_30_A P10 VSS P11 MSIO64NB3/USB_DATA3_D P12 MSIO64PB3/USB_DATA2_D P13 VSS P14 VDD P15 VSS P16 VDD P17 VSS P18 VDD P19 VSS P20 VDD P21 VSS P22 VDDI18 P23 MSIO192PB18 P24 MSIO192NB18 P25 MSIO195NB18 P26 MSIO195PB18 P27 VDDI18 P28 MSIO198NB17 P29 MSIO198PB17 P30 MSIO199NB17 P31 MSIO199PB17 P32 VSS P33 MSIO203PB17 P34 MSIO208PB17 R1 MSIO32PB5/USB_DATA4_B R2 MSIO32NB5/USB_DATA5_B R3 VSS R4 MSIO38NB5 R5 MSIO44PB4/CAN_RX/GPIO_3_A/USB_DATA1_A R6 MSIO44NB4/CAN_TX_EN_N/GPIO_4_A/USB_DATA2_A R7 MSIO52PB4/SPI_1_SS4/GPIO_17_A 75 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name R8 VDDI4 R9 MSIO54PB4/GPIO_25_A R10 MSIO54NB4/GPIO_26_A R11 MSIO57NB4/SPI_1_SS3/GPIO_16_A R12 MSIO57PB4/SPI_1_SS2/GPIO_15_A R13 VDDI4 R14 VSS R15 VDD R16 VSS R17 VDD R18 VSS R19 VDD R20 VSS R21 VDD R22 VSS R23 MSIO200PB17 R24 MSIO200NB17 R25 MSIO202NB17 R26 MSIO202PB17 R27 MSIO204NB17 R28 MSIO204PB17 R29 VSS R30 MSIO205NB17 R31 MSIO205PB17 R32 MSIO207NB17 R33 MSIO207PB17 R34 VDDI17 T1 VDDI5 T2 MSIO31PB5/USB_DATA2_B T3 MSIO31NB5/USB_DATA3_B T4 MSIO38PB5/GB13/CCC_SE1_CLKI0 T5 MSIO37NB5 T6 VSS T7 MSIO41NB4 T8 MSIO45NB4/I2C_1_SCL/GPIO_1_A/USB_DATA4_A T9 MSIO45PB4/I2C_1_SDA/GPIO_0_A/USB_DATA3_A T10 MSIO50NB4/SPI_1_SDI/GPIO_11_A UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 76 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name T11 MSIO50PB4/SPI_1_CLK T12 MSIO46NB4/SPI_0_SDI/GPIO_5_A/USB_DIR_A T13 VSS T14 VPP T15 VSS T16 VDD T17 VSS T18 VDD T19 VSS T20 VDD T21 VSS T22 VDDI17 T23 MSIO206PB17 T24 MSIO206NB17 T25 MSIO211NB17 T26 VSS T27 MSIO209NB17 T28 MSIO209PB17 T29 MSIO210NB17 T30 MSIO210PB17 T31 VDDI17 T32 MSIO212NB17 T33 MSIO212PB17 T34 MSIOD217NB16 U1 MSIO26NB5/GPIO_28_A U2 MSIO29PB5/USB_STP_B U3 MSIO29NB5/USB_NXT_B U4 VDDI5 U5 MSIO37PB5/GB9/CCC_SE0_CLKI0 U6 MSIO33NB5 U7 MSIO41PB4/GB10/CCC_SE0_CLKI1 U8 MSIO36NB5 U9 VSS U10 MSIO42PB4/GB14/CCC_SE1_CLKI1 U11 MSIO42NB4 U12 MSIO46PB4/SPI_0_CLK/USB_XCLK_A U13 VDDI4 77 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name U14 VSS U15 VDD U16 VSS U17 VDD U18 VSS U19 VDD U20 VSS U21 VDD U22 VSS U23 MSIO214PB17/GB2/CCC_NW0_CLKI1 U24 MSIO214NB17 U25 MSIO211PB17 U26 MSIO216NB17 U27 MSIO216PB17/CCC_NW0_CLKI0 U28 VDDI17 U29 MSIO215PB17/CCC_NW1_CLKI0 U30 MSIO215NB17 U31 MSIO213PB17/GB6/CCC_NW1_CLKI1 U32 MSIO213NB17 U33 VSS U34 MSIOD217PB16/GB5/CCC_SW1_CLKI1 V1 MSIO26PB5/GPIO_27_A V2 VSS V3 MSIO25NB5 V4 MSIO30PB5/USB_DATA0_B V5 MSIO30NB5/USB_DATA1_B V6 MSIO33PB5/USB_DATA6_B V7 VDDI5 V8 MSIO36PB5/CCC_NE1_CLKI0 V9 MSIO34PB5 V10 MSIO34NB5 V11 MSIO35NB5 V12 MSIO35PB5/CCC_NE0_CLKI0 V13 VSS V14 VPP V15 VSS V16 VDD UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 78 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name V17 VSS V18 VDD V19 VSS V20 VDD V21 VSS V22 VDDI16 V23 MSIOD220PB16/CCC_SW0_CLKI0 V24 MSIOD220NB16 V25 VDDI16 V26 MSIOD222NB16 V27 MSIOD222PB16 V28 MSIOD223NB16 V29 MSIOD223PB16 V30 VSS V31 MSIOD221NB16 V32 MSIOD218PB16/GB1/CCC_SW0_CLKI1 V33 MSIOD218NB16 V34 MSIOD219NB16 W1 MSIO20PB5 W2 MSIO20NB5 W3 MSIO25PB5 W4 MSIO24NB5 W5 VSS W6 MSIO23PB5 W7 MSIO23NB5 W8 MSIO27PB5 W9 MSIO27NB5/USB_DATA7_B W10 VDDI5 W11 MSIO28NB5/USB_DIR_B W12 MSIO28PB5/USB_XCLK_B W13 VDDI5 W14 VSS W15 VDD W16 VSS W17 VDD W18 VSS W19 VDD 79 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Pin List Package Pin M2S150TS-1FCG1152 Pin Name W20 VSS W21 VDD W22 VSS W23 MSIOD227PB16 W24 MSIOD227NB16 W25 MSIOD229NB16 W26 MSIOD229PB16 W27 VSS W28 MSIOD231NB16 W29 MSIOD226PB16 W30 MSIOD226NB16 W31 MSIOD221PB16 W32 VDDI16 W33 MSIOD224NB16 W34 MSIOD219PB16/CCC_SW1_CLKI0 Y1 MSIO19NB5 Y2 MSIO19PB5 Y3 VDDI5 Y4 MSIO24PB5 Y5 MSIO18NB5 Y6 MSIO18PB5 Y7 MSIO15NB6 Y8 VSS Y9 MSIO22NB5 Y10 MSIO22PB5 Y11 MSIO21NB5 Y12 MSIO21PB5 Y13 VSS Y14 VDD Y15 VSS Y16 VDD Y17 VSS Y18 VDD Y19 VSS Y20 VDD Y21 VSS Y22 CCC_SW1_PLL_VDDA UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 80 4 – Pin List Package Pin M2S150TS-1FCG1152 Pin Name Y23 MSIOD234PB16 Y24 MSIOD234NB16 Y25 MSIOD241NB16 Y26 MSIOD235PB16 Y27 MSIOD235NB16 Y28 MSIOD231PB16 Y29 VDDI16 Y30 MSIOD230PB16 Y31 MSIOD230NB16 Y32 MSIOD228NB16 Y33 MSIOD224PB16 Y34 VSS 81 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 5 – Placement of the Board Components Figure 20 and Figure 21 show the SmartFusion2 Advanced Development Kit components placement for the top and bottom sides. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 82 5 – Placement of the Board Components B1 U3 R313 U5 H L L L TRST_L TMS TDI TCK R253 DS29 R354 3P3V GND TP20 TP4 3P3V C1 H1 R283 R282 PRB GND R278 TP7 U26 R276 J123 C697 C696 R307 19 J38 TP3 J28 J29 GND U31 GND RMT VDD_REG R155 PRA R304 R260 U23 U34 VDD_REG_CS GND B C638 C600 U25 R255 SW4 B1 GND D8 1 R330 C596 L R162 C332 A1 R279 D7 B1 A FTDI 3 J125 J121 J124 TP35 R306 R305 TP9 GND 1P5V_REG C636 C637 R366 J119 TP21 H 20 2 B1 A1 B L 19 JTAG_SEL R161 H C604 C27 R222 B27 R224 R220 H J60 TRACE_ETM_HEADER R364 20 J36 RVI_HEADER L R318 R362 C593 F25 G25 J23 J22 G27 H27 F23 H R158 R159 H 9 1 SCL 2 H R277 C698 U59 U2 1 2P5V_LDO H1 SW2 A R310 U32 U6 1 C645 C646 C644 C641 C642 0P75V_REG 0 J32 A1 B U35 R363 J118 U24 10 VDD SDA A H40 1P5V SW3 L R361 TP10 TP22 K R272 C608 PLLMDDR 3P3V OP75V 1 C328 C467 A1 A1 A1 R210 PLL3 3P3V U1 R314 R316 C476 PLL1 B R292 FP4_HEADER J37 2 L Y11 C28 C26 A27 F26 D26 DS6 DS5 DS4 DS3 DS2 DS1 DS0 R149 C153 C156 C119 R213 VCCIO_LPC_ VADJ VCCIO_HPC_VADJ TDO C40 A1 SW1 B1 A 1P0V_PHY DS17 5P0V 1P8V 5 4 3 2 1 SW5 J116 SWT 5P0V C630 U13 R209 C691 TP11 R343 8 7 6 DS7 E26 R150 C460 C455 R266 Y20 U4 C562 L C610 3P3V_LDO C161 C233 C197 C118 C163 C371 R211 C463 R1211 C422 C518 C599 R1213 C468 C519 R1214 R1212 R1208 R1210 R1207 C471 R378 Y3 C554 R375 C528 C526 PLL4 C359 R1215 R1209 3P3V C484 C361 SERDES_3_REFCLK0_N C517 PLL_S3 R70 PLL5 A1 L H R47 R48 Y12 R369 U7 J13 C109 C150 C236 C235 C199 C159 C116 C465 3P3V Y4 C360 PLL2 R217 J10 R308 C640 C211 C210 C213 C212 C136 C135 C138 C137 C140 C139 C142 C141 C173 C172 C175 C174 C177 C176 C179 C178 C216 C215 C92 C91 C94 C93 C96 C95 C220 C89 C90 3P3V H J6 R69 2P5V S3_PLL_L23 C362 PLL0 L H J4 PLL_S0 PLLFDDR C113 C129 R54 R55 C643 A40 3P3V_VPP C102 C374 A1 CON1 SERDES3_RXN_1 C146 C257 C246 R78 R75 R303 J17 R352 R355 R356 TP26 GND C703 C704 VDDIO C705 SERDES3_RXP_1 www.microsemi.com G23 H L J351 U27 R281 TP17R300 R280 1.2 V CURRENT SENSE R808 B32 U60 1.5V 1.8V R332 J353 2.5V R351 R839 R373 R374 TP27 L6 C209 L5 3.3V 2.5V 1.8V 1.5V 1.2V J354 U11 C98 C382 PLL7 C699 R289 TP29 1.2V R288 S2_PLL_L23 H J8 J5 2P5V C692 J11 12V R267 D9 1 6 SERDES_3_REFCLK0_P J9 J12 VCCIO_HPC_VADJ C702 R133 R131 R134 U9 TDI VCCIO_LPC_ VADJ TP28 R294 R138 R127 R126 C315 CR2 R141 R143 R137 R139 J23 C606 U12 U10 C316 5 CR1 R136 C323 U49 R140 R142 R298 C701 C700 R130 R125 C672 B11 C325 GND SERDES3_TXP_1 SERDES3_TXN_1 J7 C183 S1_PLL_L23 C394 C521 GND P1 1 TDO R74 R72 R73 R71 R81 C624R76 R286 C626 C625 C671 TP1 R112 SPK_L U37 R840 R841 R842 TP2 SPK_R C324 C605 R396 DS26 C164 USB_5V C674 C673 TMS TCK R59 R42 MDIO C283 1 TRSTN R293 J16 C330 R372 R156 R111 J15 Y2 C292 C331 R113 R114 HSDACN HSDACP J30 R60 S0_PLL_L23 S0_PLL_L01 2P5V C103 R105 3P3V C302 R92 R218 C293 R91 R94 C295 R93 C297 R95 R96 C314 R121 R120 R115 J18 C308 R110 R109 MDC C307 R108 R106 C306 R107 C282 M2S150-ADV-DEV-KIT Rev-B DVP-101-000408-001 C148 R64 R41 C294 C296 N C305 R104 C304 C313 TP16 DS16 1 3 3P3V PLL_S1 C100 R40 U8 6 R191 R190 R189 R188 R184 R183 R182 R181 R179 PLL6 N J19 J21 S2_PLL_L01 TP31 2P5V GND R63 C181 TP33 R58 C144 TC21 TC20 TC19 TC18 TC16 TC17 R79 C255 R98 R97 TP12 2 12V 5 J54 R216 TP15 GND J22 4 A1 C530 U62 R331 K J42 3P3V_LDO DS11 P1_LED3 DS12 P1_LED2 DS13 P1_LED1 DS14 P1_LED0 DS8 P0_LED3 DS9 P0_LED2 DS10 P0_LED0 R99 R100 C303 C623 1P0V_PHY J14 GND TP32 S1_PLL_L01 R50 R46 ON 12V/5A TP30 C648 R311 R309 C647 R160 D15 R290 R291 R5484 R5483 R333 R334 C1579 D10 C214 U28 3P3V_LDO GND R270 R978 R975 R976 C1575 C1574 C1573 C1572 R178 Y6 ON SW7 U58 R301 R353 R116 R117 R118 R119 R103 R101 R102 C378 R325 U36 6 C666 C668 TP14 R164 R167 R168 R169 R170 R166 R165 R171 R329 R172 C670 R173 D13 R327 TP23 1P8V C667 L4 D14 R328 R326 C1566 R177 U17 J20 TP24 C351 R174 R175 R176 J33 U16 L3 1 CR4 5 CR3 U162 SW6 RST B R1217 C628 DS28 3P3V B1 R1518 LED9 RST C592 R1216 J350 K1 R977 R973 R974 R199 R198 R197 R196 R194 R193 R192 A1 DS27 C595 R243 U19 X1 C358 U18 R163 C357 A TRST_L TMS TDO TDI GND TCK R257 R986 R985 R984 R1519 R295 C926 R983 J352 K40 J34 Figure 20 · SmartFusion2 Advanced Development Kit Board Silkscreen Top View 83 SmartFusion2 SoC FPGA Advanced Development Kit User Guide D15 C353 C346 C301 C669 C300 C299 C310 C252 C274 C253 C254 C277 R80 C265 C309 C298 C36 R360 R28 C28 C64 R357 R27 C44 R32 C43 R5 R16 R29 R31 R833 C30 R24 R22 R26 R23 R19 R6 C21 R7 R8 R9 C86 R10 R18 R15 C87 R21 R20 R832 C2 C88 CON1 C104 C321 R132 R122 C319 C326 R123 R128 C327 C311 C312 C256 R89 R90 R88 R129 R124 R359 R358 C320 C80 C590 C338 C344 C356 C354 C352 C1577 C708 U15 C121 C477 C542 C510 R85 C435 R39 C229 C532 C486 C492 C291 C271 C318 C317 C322 C65 R77 R82 R135 C54 C290 C9 R37 C45 C59 C18 C11 C46 C4 C22 C75 C37 R84 C284 C289 C286 C275 C276 R287 C251 C262 C272 C250 C288 C260 C268 C287 C259 C270 C278 C281 C264 C273 C263 C279 C269 A1 R14 C70 C63 R12 C57 C29 R11 R13 C42 C85 C50 C71 C10 C3 C376 R214 C538 R215 C32 C15 C17 R1 3P3V R30 C56C8 C5 R296 R204 A32 C67 C77 C51 C47 3P3V C459 C395 C419 C583 C489 C569 C575 C584 C585 C472 C500 C560 C480 C586 C556 C516 C475 C448 C485 C506 C545 C453 C423 C513 C417 C509 C533 R202 C19 C508 C571 C437 R146 C494 C579 C568 C576 C582 R34 C570 C561 C580 C33 C39 C573 C16 C389 C424 C72 C418 C55C58 C66 C24 C427 C396 C430 C399 C76 R33 C449 C38 C405 C444 C495 C547 C466 C82 C79C12 C52 C48 C60 C35 R2 C503 C537 C497 C520 C464 C404 C409 C436 C388 C549 C457 C400 C434 R144 R145 C411 C27 C261 C280 C267 C266 R83 3P3V C525 C381 C350 D14 C258 C247 C248 C249 C285 R67 C219 R66 C217 C488 C441 C184 C544 C555 C456 C223 C432 R62 C574 C397 C504 C428 C425 C225 C522 C564 C401 C431 C493 C151 C155 C567 C191 C426 C230 C487 C445 C539 R61 C577 C407 C408 R263 C147 C551 C227 R264 C572 C587 C106 C228 C224 C529 C481 C410 C375 C469 C1 3P3V C412 C462 U21 R180 R251 C337 R187 R252 R195 C597 R299 C339 C347 C348 C1580 2P5V R38 C97 L1 C335 C342 U22 C349 C1576 C546 C364 C25 C81 R1517 R1516 C1568 C1567 C514 C474 C222 C7 C62 C14 C69 R4 C614 R212 C218 Y5 C369 C478 C473 R35 C74 C615 R285 C622 C621 C619 R379 C78 C68 C49 C639 C616 D8 C620 C617 R284 C368 C40 C83 C618 R302 R365 U30 R227 C678 C677 R232 R229 U29 R258 C601 C588 R231 R249 U33 R5478 R5477 C550 C386 R377 R254 C553 C416 C540 C406 C392 C433 C536 C558 C385 1 C440 R265 C452 U161 C1570 C1569 C180 C182 C541 R206 C53 R36 C20 C41 C84 C31 C162 C490 C482 C447 R261 R324 U20 R200 R1222 R1223 R376 C329 R297 C609 U40 U14 R153 R201 R320 R259 C603 R154 C198 C415 C333 C598 R262 R319 R380 R226 C589 R223 C676 R225 R246 R230 R228 R247 R321 R248 R234 U163 R233 C602 C523 C26 C23 C73 J13 C134 C234 C160 C120C226 C237 C108 C189 C193 C132 R3 C13 C61 C1109 C6 C130 R53 C34 R157 J12 C117 R219 C675 R221 R340 R339 C594 R49 R52 C502 C524 R56 R57 C185 C145 C143 C101 C149 C105 C99 C221 C548 C391 C384 C232 C557 C187 C154 C429 C231 C414 C152 C188 C110 C370 C552 C158 C543 J5 C365 J7 C190 C111 C393 C498 C380 C377 C534 C107 C194 C157 C438 C112 C421 C511 C114 C186 C483 C451 C383 C398 C515 C439 C413 C446 C443 J4 J6 C420 C390 C402 C192 C195 C115 C535 C531 C496 C581 C505 C527 C512 C372 2P5V S3_PLL_L01 C491 C566 C461 C363 C379 3P3V 2P5V C501 C367 C559 C565 C563 R68 R205 C578 C373 C450 R208 C479 R203 C403 C454 R207 C366 C458 C470 C196 C200 U38 C629 C631 R342 R341 R45 R51 C131 U39 R348 R347 C633 C387 C442 R65 C707 R43 R244 C340 C336 C345 L2 C1571 3P3V C133 R350 R349 R271 R269 C679 C680 C681 C682 C683 C684 C685 C686 R235 R236 R237 R238 R239 R240 R241 R242 C611 R268 R44 R1521 C355 R250 C591 R245 R86 R87 U61 C695 C693 C694 R312 R275 R1219 R1218 C612 R274 PLL_S2 R273 C706 R186 R185 Q1 C343 C627 R1520 C607 C613 R979 R981 R980 R982 R256 C341 R1220 R1221 5 – Placement of the Board Components Figure 21 · SmartFusion2 Advanced Development Kit Silkscreen Bottom View SmartFusion2 SoC FPGA Advanced Development Kit User Guide 84 6 – Demo Design M2S150-ADV-DEV-KIT Board Demo Design The SmartFusion2 M2S150-ADV-DEV-KIT comes with a preloaded demo design. This demo design demonstrates PCIe interface of the SmartFusion2 device. For more information on running the demo design, refer to the SmartFusion2 SoC FPGA PCIe Control Plane Demo Guide for Advanced Development Kit. Figure 22 · PCIe Demo Design Window UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 85 7 – Manufacturing Test The SmartFusion2 M2S150-ADV-DEV-KIT device contains a manufacturing test program that can be run to verify the functionality of the board. This program contains a list of options that can be run as diagnostics. After setting up the Tera Term and the board is powered up, the tests are displayed, refer to Figure 29. From the list of options, any test(s) can be selected to verify the functionality. Note: For more information on manufacturing the test procedures, associated files, and updated information, refer to //link to be provided// Before testing the SmartFusion2 Advanced Development Kit board: • Download SEC_KIT_MTD_top.stp file from http://www.microsemi.com/document-portal/doc_download/134344-smartfusion2-advanced-developmentkit-mtd • Download and install the FTD drivers from: http://www.ftdichip.com/Drivers/D2XX.htm M2S150-ADV-DEV-KIT Power and Programming Test Power Supply Validation The following steps describe how to test and validate the power supply to the board: 1. Connect the following jumpers on the SmartFusion2 Advanced Development Kit board: − J116 short pin 1-2 − J123 short pin 2-3 − J353 short pin 1-2 − J354 short pin 1-2 − J54 short pin 1-2 Note: Before making the jumper connections, switch off the power supply switch, SW7. 2. Connect the 12V/5 Amps power supply brick to the J42 jumper. 3. Switch ON the SW7 power supply switch. FPGA Programming M2S150-ADV-DEV-KIT has an embedded FlashPro5 programmer on the board. It does not require external programmer to program the device. The board can also be programmed using FlashPro4. To program the board using FlashPro4, connect the FlashPro4 header to J37 and change the J124 jumper position to pin 2-3. Programming the Device using Embedded FlashPro5 FlashPro 11.4 must be installed in the Host PC to program the device using embedded FlashPro5. The following steps describe how to program the device using embedded FlashPro5: 1. Connect the following jumpers on the SmartFusion2 Advanced Development Kit board: − Short Jumper J124 to 1-2 position. − Short Jumper J121 to 1-2 position. − Short Jumper J32 to 1-2 position. 2. Connect USB cable (mini USB to Type A USB cable) to J33 and other end of the cable to the USB port of the Host PC. 3. Open the FlashPro v11.4 software. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 86 7 – Manufacturing Test Figure 23 · FlashPro Window 4. Click New Project to create a new project. Refer to Figure 24. Figure 24 · Creating a New Project 5. 87 a. Enter the Project Name. b. Select Single device as the Programming mode and click OK. Click Configure Device. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide M2S150-ADV-DEV-KIT Power and Programming Test Figure 25 · Configuring the Device a. Click Browse and select the SEC_KIT_MTD_top.stp file from the Load Programming File window. 6. Click Program to program the device. 7. Press SW4 switch, the respective DS7 LED will glow. This confirms that the program is passed. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 88 7 – Manufacturing Test Running the Manufacturing Test Setting Up the Tera Term The following steps describe how to set up Tera Term to perform the manufacturing test: 1. Connect the USB cable (mini USB to Type A USB cable) to J33 and other end of the cable to the USB port of the Host PC. 2. Open Tera Term from the Start menu. Figure 26 · Tera Term New Connection Window 3. Select Serial. 4. Select a port from the Port drop-down list and click OK. Note: • When using the USB cable for Tera Term communication, four FlashPro5 COM ports (FlashPro5 Port) are available in the Port drop-down list. Select the Third FlashPro5 COM port to establish the connection with the Host PC. • If the FlashPro5 drivers are not installed properly, the Port drop-down list does not list the FlashPro5 COM ports. 89 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Running the Manufacturing Test Figure 27 · Tera Term New Connection Window 5. From the Setup menu, select Serial Port and enter the following Tera Term settings: − Baud rate = 57600 − Data = 8 − Parity = none − Stop = 1 − Flow control = none Figure 28 · Tera Term Serial Port Setup Window UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 90 7 – Manufacturing Test Jumper Settings Table 18 describes the jumper settings required to perform the tests on the SmartFusion2 Advanced Development Kit board. Table 17 · Jumper Settings Jumper Settings Interface RTC Test - I2C Test On Header (H1) short (10-6) and (11-7) DDR3 Memory Test - SPI0 Memory Test Short J118 pin 1-2 SPI1 Memory Test Short J119 pin 1-2 USB Device Test Connect Micro B to P1 and connect other end of the cable to the Host PC (type A). This cable is required for testing on board USB device interface. Short J23 pin 1-2 Connect Ethernet cable to J19 and connect other end of the cable to the Ethernet switch or network (1 Gbps) SGMII Test Short J11 pin 1-2 Short J8 pin 1-2 Short J14 pin 1-2 Connect (J4 to J5) and (J6 to J7) using SMA to SMA cable SERDES Loopback Test Loopback cable (5 Gbps data rate) Short J11 pin 1-2 Short J8 pin 1-2 91 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Running the Manufacturing Test Running the Manufacturing Test Program the board SEC_KIT_MTD_top.stp file and make the required Tera Term and jumper settings. For more information on settings, refer to Running the Manufacturing Test. The following steps describe how to run the manufacturing test: 1. Press the SW6 reset switch on the M2S150-ADV-DEV-KIT board to reset and begin the tests. Note: All the tests are listed in the Tera Term, when the setup is ready for the test, refer to Figure 29. If this message does not appear, press the SW6 reset switch again. If the message still does not appear, then check all the jumpers and the Tera Term settings. Figure 29 · Test Menu 2. Press 1 to run the RTC test. Figure 30 · Running RTC Test UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 92 7 – Manufacturing Test When the test is passed, a message is displayed. Refer to Figure 31. Figure 31 · RTC Test Passed 3. Press 2 to run the I2C loopback test. Wait for 5 seconds to complete the test. When the test is passed, a message is displayed. Refer to Figure 32. Figure 32 · I2C Test Passed 93 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Running the Manufacturing Test 4. Press 3 to run the DDR3 memory test. Wait for 30 seconds to complete the test. When the test is passed, a message is displayed. Refer to Figure 33. Figure 33 · DDR3 Memory Test Passed 5. Press 4 to run the SPI0 memory test. When the test is passed, a message is displayed. Refer to Figure 34. Figure 34 · SPI0 Memory Test Passed UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 94 7 – Manufacturing Test 6. Press 5 to run the SPI1 memory test. When the test is passed, a message is displayed. Refer to Figure 35. Figure 35 · SPI1 Memory Test Passed 7. Press 6 to run the USB device test. When the test is started, a message is displayed. Refer to Figure 36. Figure 36 · USB Device Test Passed 95 a. Press and hold the SW2 switch on the board and observe the mouse cursor moving to the right side. b. Press SW6 reset switch go back to the main menu. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Running the Manufacturing Test 8. Press 7 to run the SGMII test. When the test is started, the DS1 LED will be OFF. The DS10 LED will glow and the DS8 LED will start blinking. A message is displayed, refer to Figure 37. Figure 37 · SGMII Test a. If the message is not displayed or DS10 and DS8 LEDs do not blink, switch ON and OFF the SW7 power supply switch on the board, and run the DDR3 test by pressing 3. b. Press 7 to repeat the SGMII test. c. A confirmation message is displayed, Press n twice. Refer to Figure 38. When the test is passed, the IP address of the Host PC is displayed. d. Press the SW6 reset switch on the board to go back to the main. Figure 38 · SGMII Test Passed Note: IP address may vary from one PC to the other PC. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 96 7 – Manufacturing Test If the IP address is not displayed, perform the following steps to get the IP address. i. Press 7 to run the SGMII test. Refer to Figure 39. Figure 39 · SGMII Debug Test ii. Press 1 to restart the auto negotiation and press y to continue. Refer to Figure 40. iii. Press 2 to disable auto negotiation and press y to continue. Refer to Figure 41. Figure 40 · SGMII Debug Test Figure 41 · SGMII Debug Test 97 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide Running the Manufacturing Test iv. Press n twice for not to repeat the action and get the IP address. Refer to Figure 42. Figure 42 · SGMII Debug Test Passed v. 9. Press SW6 to go back to the main menu. Press 8 to run the SERDES loopback test. Refer to Figure 43. Make sure that the loopback cable is connected. Refer to Jumper Settings. Figure 43 · SERDES Loopback Test UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 98 7 – Manufacturing Test a. Press 1 to enable PRBS pattern for Lane 1. Refer to Figure 44. Figure 44 · SERDES Loopback Test b. Press 2 to read Status register for Lane 1. When the test is started, a message is displayed. Refer to Figure 45. Figure 45 · SERDES Loopback Passed c. 99 Press the SW6 reset switch to go back to the main menu. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide List of Changes The following table shows important changes made in this document for each revision. Revision Revision 2 (July 2015) Revision 1 (July 2014) Changes Page Updated the part number from M2S150-ADV-DEV-KIT-ES to M2S150-ADV-DEV-KIT throughout the document (SAR 66855). NA Updated the device number from M2S150T-1FCG1152ES to M2S150TS-1FCG1152 throughout the document (SAR 66855). NA Updated Manufacturing Test section by adding MTD files link (SAR 60671 and 68260). 86 Updated Power Supply Validation section with updated correct pin details (SAR 61171). 86 Updated FMC Connectors section (SAR 67950) 30 Initial release NA UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 100 Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world 408.643.6913 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues and various FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions. Technical Support For Microsemi SoC Products Support, visit http://www.microsemi.com/products/fpga-soc/designsupport/fpga-soc-support Website You can browse a variety of technical and non-technical information on the Microsemi SoC Products Group home page, at http://www.microsemi.com/soc/. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website. Email You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request. The technical support email address is [email protected]. My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases. 101 UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide ITAR Technical Support Outside the U.S. Customers needing assistance outside the US time zones can either contact technical support via email ([email protected]) or contact a local sales office. Sales office listings can be found at www.microsemi.com/soc/company/contact/default.aspx. ITAR Technical Support For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page. UG0557: SmartFusion2 SoC FPGA Advanced Development Kit User Guide 102 Microsemi Corporation (MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,600 employees globally. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: [email protected] © 2015 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. 50200557-2/07.15