DDR AXI Arbiter UG0644 User Guide Design Description Table of Contents Introduction ....................................................................................................................3 Hardware Implementation .............................................................................................4 Design Description......................................................................................................................................... 4 Inputs and Outputs ........................................................................................................................................ 7 Configuration Parameters ............................................................................................................................ 14 Timing Diagrams.......................................................................................................................................... 16 Resource Utilization ..................................................................................................................................... 18 List of Changes ............................................................................................................ 19 Product Support........................................................................................................... 20 Customer Service ........................................................................................................................................ 20 Customer Technical Support Center ........................................................................................................... 20 Technical Support ........................................................................................................................................ 20 Website ........................................................................................................................................................ 20 Contacting the Customer Technical Support Center ................................................................................... 20 ITAR Technical Support .............................................................................................................................. 21 2 UG0644: DDR AXI Arbiter User Guide Introduction Memories are an integral part of any typical video and graphics applications. It is used for buffering video pixel data. One common buffering example are display frame buffers in which the complete video pixel data for a particular display resolution is buffered in the memory. Dual data rate (DDR)-Synchronous DRAM (SDRAM) is one of the common memories used for buffering in video applications. It is used because of its speed which is required for fast processing in video systems. Figure 1 shows an example of a system-level diagram of DDR-SDRAM memory interfacing with video application. DDR-SDRAM Memory Interface DDR SDRAM Controller DDR-SDRAM Video IP Controller back-end bus Controller Bus Interface/Arbiter Video IP Figure 1 · Acceleration ® In Microsemi SmartFusion 2 System-on-Chip (SoC), there is two on-chip DDR controllers with 64-bit advanced extensible interface (AXI) and 32-bit advanced high-performance bus (AHB) slave interfaces towards the field programmable gate array (FPGA) fabric. You need to write an AXI or AHB master interface to read and write into the DDR-SDRAM memory interfaced to the on-chip DDR controllers. UG0644: DDR AXI Arbiter User Guide 3 Design Description Hardware Implementation Design Description The DDR AXI Arbiter provides the 64-bit AXI master interface to the DDR-SDRAM on-chip controllers of SmartFusion2 devices. The DDR AXI Arbiter has four read channels and two write channels towards the user logic. The block arbitrates between the four read channels to provide access to the AXI read channel in a round-robin manner. As long as the read Channel 1 masters read request is high, the AXI read channel is allocated to it. Read channel 1 has fixed output data width of 24-bit. Read Channels 2, 3, and 4 can be configured for either 8-bit, 24-bit or 32-bit data output width. This is selected by global configuration parameter. The block arbitrates between the two write channels to provide access to the AXI write channel in a round-robin manner. Both the write channels have equal priority. Write channel 1 and 2 can be configured as either 24-bit or 32-bit input data width. 4 UG0644: DDR AXI Arbiter User Guide Design Description Figure 2 shows the top-level pin-out diagram of the DDR AXI Arbiter. Figure 2 · Top-Level Block Diagram of Display Controller Block UG0644: DDR AXI Arbiter User Guide 5 Design Description Figure 3 shows the top-level block diagram of a system with DDR AXI Arbiter block ported into the SmartFusion2 device. DDR-SDRAM MDDR and FDDR Controller AXI DDR AXI Arbiter Write channel 2 Write channel 1 Read channel 4 Read channel 3 Read channel 2 Video Block Video Block Video Block Video Block Video Block Read channel 1 Video Block1Bandwidth critical Block Figure 3 · System-Level Block Diagram of DDR AXI Arbiter on the SmartFusion2 Device 6 UG0644: DDR AXI Arbiter User Guide Inputs and Outputs Inputs and Outputs Table 1 shows the input and output ports of the DDR AXI Arbiter. Table 1 · Input and Output Ports of the DDR AXI Arbiter Signal Name Direction Width RESET_N_I Input – Active low asynchronous reset signal to design SYS_CLOCK_I Input – System clock BUFF_READ_CLOCK_I Input – Write channel’s internal buffer read clock, must be double the SYS_CLOCK_I frequency rd_req_1_i Input – Read request from Master 1 rd_ack_o Output – Arbiter acknowledgment to read request from Master 1 rd_done_1_o Output – Read completion to Master 1 start_read_addr_1_i Input [(g_AXI_AWIDTH-1):0] bytes_to_read_1_i Input [(g_RD_CHANNEL1_AXI_BUFF_ AWIDTH + 3) - 1 : 0] Description DDR address from where read has to be started for read channel 1 Bytes to be read out from read channel 1 video_rdata_1_o Output [(g_RD_CHANNEL1_VIDEO_DAT A_WIDTH-1):0] rdata_valid_1_o Output – Read data valid from read channel 1 rd_req_2_i Input – Read request from Master 2 rd_ack_2_o Output – Arbiter acknowledgment to read request from Master 2 rd_done_2_o Output – Read completion to Master 2 start_read_addr_2_i Input [(g_AXI_AWIDTH-1):0] bytes_to_read_2_i Input [(g_RD_CHANNEL2_AXI_BUFF_ AWIDTH + 3) - 1 : 0] Video data output from read channel 1 DDR address from where read has to be started for read channel 2 Bytes to be read out from read channel 2 video_rdata_2_o Output [(g_RD_CHANNEL2_VIDEO_DAT A_WIDTH-1):0] rdata_valid_2_o Output – Read data valid from read channel 2 – Read request from Master 3 Video data output from read channel 2 rd_req_3_i Input rd_ack_3_o Output – Arbiter acknowledgment to read request from Master 3 rd_done_3_o Output – Read completion to Master 3 start_read_addr_3_i Input [(g_AXI_AWIDTH-1):0] bytes_to_read_3_i Input UG0644: DDR AXI Arbiter User Guide [(g_RD_CHANNEL3_AXI_BUFF_ AWIDTH + 3) - 1 : 0] DDR address from where read has to be started for read channel 3 Bytes to be read out from read channel 3 7 Inputs and Outputs Signal Name Direction Width video_rdata_3_o Output [(g_RD_CHANNEL3_VIDEO_DAT A_WIDTH-1):0] rdata_valid_3_o Output – Read data valid from read channel 3 rd_req_4_i Input – Read request from Master 4 rd_ack_4_o Output – Arbiter acknowledgment to read request from Master 4 rd_done_4_o Output start_read_addr_4_i Input bytes_to_read_4_i Input – [(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL4_AXI_BUFF_ AWIDTH + 3) - 1 : 0] Description Video data output from read channel 3 Read completion to Master 4 DDR address from where read has to be started for read channel 4 Bytes to be read out from read channel 4 video_rdata_4_o Output [(g_RD_CHANNEL4_VIDEO_DAT A_WIDTH-1):0] rdata_valid_4_o Output – Read data valid from read channel 4 wr_req_1_i Input – Write request from Master 1 wr_ack_1_o Output – Arbiter acknowledgment to write request from Master 1 wr_done_1_o Output – Write completion to Master 1 start_write_addr_1_i Input [(g_AXI_AWIDTH-1):0] bytes_to_write_1_i Input video_wdata_1_i Input [(g_WR_CHANNEL1_VIDEO_DAT A_WIDTH-1):0] Video data Input to write channel 1 wdata_valid_1_i Input – Write data valid to write channel 1 wr_req_2_i Input – Write request from Master 1 wr_ack_2_o Output – Arbiter acknowledgment to write request from Master 2 wr_done_2_o Output – Write completion to Master 2 start_write_addr_2_i Input [(g_AXI_AWIDTH-1):0] bytes_to_write_2_i Input video_wdata_2_i Input [(g_WR_CHANNEL2_VIDEO_DAT A_WIDTH-1):0] Video data Input to write channel 2 wdata_valid_2_i Input – Write data valid to write channel 2 8 [(g_WR_CHANNEL1_AXI_BUFF_ AWIDTH + 3) - 1 : 0] [(g_WR_CHANNEL2_AXI_BUFF_ AWIDTH + 3) - 1 : 0] Video data output from read channel 4 DDR address to which write has to happen from write channel 1 Bytes to be written from write channel 1 DDR address to which write has to happen from write channel 2 Bytes to be written from write channel 2 UG0644: DDR AXI Arbiter User Guide Inputs and Outputs Signal Name Direction Width Description m_arid_o Output [3:0] Read address ID. Identification tag for the read address group of signals. m_araddr_o Output [(g_AXI_AWIDTH-1):0] Read address. Provides the initial address of a read burst transaction. Only the start address of the burst is provided. AXI I/F signals Read Address Channel m_arlen_o Output [3:0] Burst length. Provides the exact number of transfers in a burst. This information determines the number of data transfers associated with the address m_arsize_o Output [2:0] Burst size. Size of each transfer in the burst m_arburst_o Output [1:0] Burst type. Coupled with the size information, details how the address for each transfer within the burst is calculated. Fixed to 2’b01 Incremental address burst m_arlock_o Output [1:0] Lock type. Provides additional information about the atomic characteristics of the transfer. Fixed to 2’b00 Normal Access m_arcache_o Output [3:0] Cache type. Provides additional information about the cacheable characteristics of the transfer. Fixed to 4’b0000 Non-cacheable and nonbufferable m_arprot_o Output [2:0] Protection type. Provides protection unit information for the transaction. Fixed to 3’b000 Normal, secure data access – m_arvalid_o Read address valid. When HIGH, the read address and control information is valid and remain high until the address acknowledge signal, m_arready, is high. Output ‘1’ = Address and control information valid ‘0’ = Address and control information not valid. – m_arready_i Input Read address ready. The slave is ready to accept an address and associated control signals: 1 = slave ready 0 = slave not ready. Read Data Channel m_rid_i Input [3:0] m_rdata_i Input [(g_AXI_DWIDTH-1):0] UG0644: DDR AXI Arbiter User Guide Read ID tag. ID tag of the read data group of signals. The m_rid value is generated by the Slave and must match the m_arid value of the read transaction to which it is responding. Read data. 9 Inputs and Outputs Signal Name Direction Description Width Read response. m_rresp_i Input m_rlast_i Input [1:0] – Read last. Last transfer in a read burst. – m_rvalid_i The status of the read transfer. Allowable responses are OKAY, EXOKAY, SLVERR, and DECERR. Input Read valid. Required read data is available and the read transfer can complete: 1 = read data available 0 = read data not available. – m_rready_o Output Read ready. Master can accept the read data and response information: 1= master ready 0 = master not ready. Write Address Channel m_awid_o m_awaddr_o m_awlen_o m_awsize_o Output Output Output Output [3:0] Write address ID. Identification tag for the write address group of signals. [(g_AXI_AWIDTH-1):0] Write address. Provides the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst. [3:0] Burst length. Provides the exact number of transfers in a burst. This information determines the number of data transfers associated with the address. [2:0] Burst size. Size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update. Fixed to 3’b011 8 bytes per data transfer or 64-bit transfer m_awburst_o Output [1:0] Burst type. Coupled with the size information, details how the address for each transfer within the burst is calculated. Fixed to 2’b01 Incremental address burst m_awlock_o Output [1:0] Lock type. Provides additional information about the atomic characteristics of the transfer. Fixed to 2’b00 Normal Access m_awcache_o Output [3:0] Cache type. Indicates the bufferable, cacheable, write-through, write-back, and allocate attributes of the transaction. Fixed to 4’b0000 Non-cacheable and nonbufferable m_awprot_o 10 Output [2:0] Protection type. Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a UG0644: DDR AXI Arbiter User Guide Inputs and Outputs Signal Name Direction Description Width data access or an instruction access. Fixed to 3’b000 Normal, secure data access – Write address valid. Indicates that valid write address and control information are available: m_awvalid_o 1 = address and control information available Output 0 = address and control information not available. The address and control information remain stable until the address acknowledge signal, m_awready, goes HIGH. – m_awready_i Input Write address ready. Indicates that the slave is ready to accept an address and associated control signals: 1 = slave ready 0 = slave not ready. Write Data Channel Write ID tag. ID tag of the write data transfer. The m_wid value must match the m_awid value of the write transaction. m_wid_o Output [3:0] m_wdata_o Output [(g_AXI_DWIDTH1):0]AXI_DWDITH parameter m_wstrb_o Output [7:0] m_wlast_o Output – Write last. Last transfer in a write burst. – Write valid. Valid write data and strobes are available: m_wvalid_o Output Write data Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus 1 = write data and strobes available 0 = write data and strobes not available. – m_wready_i Input Write ready. Slave can accept the write data: 1 = slave ready 0 = slave not ready. Write Response Channel Signals m_bid_i Input [3:0] Response ID. The identification tag of the write response. The m_bid value must match the m_awid value of the write transaction to which the slave is responding. m_bresp_i Input [1:0] Write response. Status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR. – m_bvalid_i Input Write response valid. Valid write response is available: 1 = write response available 0 = write response not available. UG0644: DDR AXI Arbiter User Guide 11 Inputs Mnd Outputs Signal Name Direction – m_bready_o Output Description Width Response ready. Master can accept the response information. 1 = master ready 0 = master not ready. Figure 4 · Internal Block Diagram of the DDR AXI Arbiter 12 UG0644: DDR AXI Arbiter User Guide Inputs and Outputs Each read channel gets triggered when it gets an high input signal on the read_req_i input. Then it samples the starting AXI address and the bytes to read inputs which are input from the external master. The channel acknowledges the external master by toggling the read_ack_input. The channel processes the inputs and generates the required AXI transactions to read the data from DDR-SDRAM. The data read out in 64-bit AXI format is stored into internal buffer. After the required data is read out and stored into the internal buffer, the un-packer module is enabled. The un-packer module unpacks each 64-bit word into the output data bit length required for that particular channel for example if the channel is configured as 32-bit output data width, each 64-bit word is sent out as two 32-bit output data words. For channel 1 which is a 24-bit channel, the un-packer unpacks each 64-bit word into 24-bit output data. As 64 is not a multiple of 24, the un-packer for read channel 1 combines a group of three 64-bit words to generate eight 24-bit data words. This puts a constraint on read channel 1 that the data bytes requested by the external master should be divisible by 8. Read channels 2, 3, and 4 can be configured as 8-bit, 24-bit, and 32-bit data width, which is determined by g_RD_CHANNEL(X) _VIDEO_DATA_WIDTH global configuration parameter. If they are configured as 24-bit, the above mentioned constraint will be applicable to each of them also. But if they are configured as 8-bit or 32-bit, there is no such constraint as 64 is multiple of 32 and 8. In these cases, each 64-bit word is unpacked into either two 32-bit data words or eight 8-bit data words. Read Channel 1 unpacks 64-bit data words read out of DDR-SDRAM to 24-bit output data words in batches of 48 64bit words, that is whenever 48 64-bit words are available in the internal buffer of read channel 1, the un-packer starts unpacking them to give 24-bit output data. If the requested data bytes to read are less than 48 64-bit words, the unpacker is only enabled after the complete data is read out of the DDR-SDRAM. In remaining three read channels, the un-packer starts sending out read data only after the complete requested number of bytes is read out from the DDRSDRAM. Note: When a read channel configured for 24-bit output width, the starting read address must be aligned to 24-bytes boundary. This is required to satisfy the constraint that the un-packer unpacks a group of three 64-bit words to produce eight 24-bit output words. All read channels generate the read done output to the external master after the requested bytes are sent to the external master. In case of write channels, the external master has to input the required data to the particular channel. The write channel takes the input data and packs them into 64-bit words and stores them in the internal storage. After the required data is stored, the external master has to provide the write request along with the starting address and bytes to write. On sampling these inputs, the write channel acknowledges the external master. After this, the channel generates the AXI write transactions to write the stored data into DDR-SDRAM. All write channels generate the write done output to the external master once the requested bytes are written into DDR-SDRAM. Write channels 1 and 2 can be configured as 8-bit, 24-bit, and 32-bit data width, which is determined by g_WR_CHANNEL(X)_VIDEO_DATA_WIDTH global configuration parameter. If they are configured as 24-bit, then the bytes to be written must be multiple of eight as the internal packer packs eight 24-bit data words to generate three 64-bit data words. But if they are configured as 8-bit or 32-bit, there is no such constraint. In all the read and write channels, the depth of the internal buffers is multiple of the display horizontal width. The internal buffer depth is calculated as follows: g_RD_CHANNEL(X)_HORIZOANTAL_RESOLUTION* g_RD_CHANNEL(X)_VIDEO_DATA_WIDTH * g_RD_CHANNEL(X)_BUFFER_LINE_STOARGE) / g_AXI_DWIDTH Where, X = Channel number The internal buffer width is determined by AXI data bus width that is, configuration parameter g_AXI_DWIDTH. ® ™ The AXI read and write transactions are performed according to the ARM AMBA AXI specifications. The transaction size for each data transfer is fixed to 64-bit. The block generates AXI transactions of fixed burst length of16 beats. The block also checks whether any single burst crosses the AXI address boundary of 4 KByte. If a single burst crosses the 4 KByte boundary, the burst is split into 2 burst at the 4 KByte boundary. UG0644: DDR AXI Arbiter User Guide 13 Configuration Parameters Configuration Parameters Table 2 shows the configuration parameters used in the hardware implementation of the DDR AXI Arbiter. These are generic parameters and can be varied based on the application requirements. Table 2 · Configuration Parameters Name Description g_AXI_AWIDTH AXI address bus width g_AXI_DWIDTH AXI data bus width g_RD_CHANNEL1_AXI_BUFF_AWIDTH Address bus width for the read Channel 1 internal buffer, which stores the AXI read data. g_RD_CHANNEL2_AXI_BUFF_AWIDTH Address bus width for the read Channel 2 internal buffer, which stores the AXI read data. g_RD_CHANNEL3_AXI_BUFF_AWIDTH Address bus width for the read Channel 3 internal buffer, which stores the AXI read data. g_RD_CHANNEL4_AXI_BUFF_AWIDTH Address bus width for the read Channel 4 internal buffer, which stores the AXI read data. g_WR_CHANNEL1_AXI_BUFF_AWIDTH Address bus width for the write Channel 1 internal buffer, which stores the AXI write data. g_WR_CHANNEL2_AXI_BUFF_AWIDTH Address bus width for the write Channel 2 internal buffer, which stores the AXI write data. g_RD_CHANNEL1_HORIZONTAL_RESOLUTION Video display horizontal resolution for read Channel 1 g_RD_CHANNEL2_HORIZONTAL_RESOLUTION Video display horizontal resolution for read Channel 2 g_RD_CHANNEL3_HORIZONTAL_RESOLUTION Video display horizontal resolution for read Channel 3 g_RD_CHANNEL4_HORIZONTAL_RESOLUTION Video display horizontal resolution for read Channel 4 g_WR_CHANNEL1_HORIZONTAL_RESOLUTION Video display horizontal resolution for write Channel 1 g_WR_CHANNEL2_HORIZONTAL_RESOLUTION Video display horizontal resolution for write Channel 2 g_RD_CHANNEL1_VIDEO_DATA_WIDTH Read Channel 1 video output bit width g_RD_CHANNEL2_VIDEO_DATA_WIDTH Read Channel 2 video output bit width g_RD_CHANNEL3_VIDEO_DATA_WIDTH Read Channel 3 video output bit width g_RD_CHANNEL4_VIDEO_DATA_WIDTH Read Channel 4 video output bit width g_WR_CHANNEL1_VIDEO_DATA_WIDTH Write Channel 1 video Input bit width. g_WR_CHANNEL2_VIDEO_DATA_WIDTH Write Channel 2 video Input bit width. g_RD_CHANNEL1_BUFFER_LINE_STOARGE Depth of the internal buffer for read Channel 1 in terms of number of display horizontal lines. The depth of the buffer is g_RD_CHANNEL1_HORIZONTAL_RESOLUTION * g_RD_CHANNEL1_VIDEO_DATA_WIDTH * g_RD_CHANNEL1_BUFFER_LINE_STOARGE) / g_AXI_DWIDTH g_RD_CHANNEL2_BUFFER_LINE_STOARGE Depth of the internal buffer for read Channel 2 in terms of number of display horizontal lines. The depth of the buffer is g_RD_CHANNEL2_HORIZONTAL_RESOLUTION * 14 UG0644: DDR AXI Arbiter User Guide Name Description g_RD_CHANNEL2_VIDEO_DATA_WIDTH * g_RD_CHANNEL2_BUFFER_LINE_STOARGE) / g_AXI_DWIDTH g_RD_CHANNEL3_BUFFER_LINE_STOARGE g_RD_CHANNEL4_BUFFER_LINE_STOARGE Depth of the internal buffer for read Channel 3 in terms of number of display horizontal lines. The depth of the buffer is g_RD_CHANNEL3_HORIZONTAL_RESOLUTION * g_RD_CHANNEL3_VIDEO_DATA_WIDTH * g_RD_CHANNEL3_BUFFER_LINE_STOARGE) / g_AXI_DWIDTH Depth of the internal buffer for read Channel 4 in terms of number of display horizontal lines. The depth of the buffer is g_RD_CHANNEL4_HORIZONTAL_RESOLUTION * g_RD_CHANNEL4_VIDEO_DATA_WIDTH * g_RD_CHANNEL4_BUFFER_LINE_STOARGE) / g_AXI_DWIDTH g_WR_CHANNEL1_BUFFER_LINE_STOARGE Depth of the internal buffer for write Channel 1 in terms of number of display horizontal lines. The depth of the buffer is g_WR_CHANNEL1_HORIZONTAL_RESOLUTION * g_WR_CHANNEL1_VIDEO_DATA_WIDTH * g_WR_CHANNEL1_BUFFER_LINE_STOARGE) / g_AXI_DWIDTH g_WR_CHANNEL2_BUFFER_LINE_STOARGE Depth of the internal buffer for write Channel 2 in terms of number of display horizontal lines. The depth of the buffer is g_WR_CHANNEL2_HORIZONTAL_RESOLUTION * g_WR_CHANNEL2_VIDEO_DATA_WIDTH * g_WR_CHANNEL2_BUFFER_LINE_STOARGE) / g_AXI_DWIDTH UG0644: DDR AXI Arbiter User Guide 15 Timing Diagrams Timing Diagrams Figure 5 shows the connection of the read and write request inputs, starting memory address, bytes to read or write inputs from external master, read or write acknowledgement, and read or write completion outputs. SYS_CLOCK_I start_read_addr_i/ start_write_addr_i ADDR1 ADDR0 bytes_to_read_i/ bytes_to_write_i Bytes1 Bytes0 read_req_i/ write_req_i read_ack_o/ write_ack_o read_done_o/ write_done_o Figure 5 · Timing diagram showing connection between start_read_addr_i/ start_write_addr_i, bytes_to_read_i/ bytes_to_write_i, read_req_i/ write_req_i, read_ack_o/write_ack_o, and read_done_o/write_done_o Figure 6 shows the connection between the write data input from the external master along with the data input valid for both write channels. SYS_CLOCK_I video_wdata_1_i/ video_wdata_2_i DATA0 DATA1 DATA2 DATA3 DATA4 DATAn-1 DATAn wdata_valid_1_i/ wdata_valid_2_i n -> g_WR_CHANNEL(X)_HORIZOANTAL_RESOLUTION Figure 6 · Timing Diagram of the video_wdata_x and wdata_valid_x inputs for the Write Channels 16 UG0644: DDR AXI Arbiter User Guide Timing Diagrams Figure 7 shows the connection between the read data output towards the external master along with the data output valid for all read channels 2, 3, and 4. SYS_CLOCK_I video_rdata_2_o/ video_rdata_3_o/ video_rdata_4_o DATA1 DATA2 DATA3 rdata_valid_2_o/ rdata_valid_3_o/ rdata_valid_4_o DATA4 DATAn-1 DATAn n -> g_RD_CHANNEL(X)_HORIZOANTAL_RESOLUTION Figure 7 · Timing Diagram of the video_rdata_x and rdata_valid_x outputs for all Read Channels 2, 3, and 4 Figure 8 shows the connection between the read data output for the read Channel 1 when g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION is greater than 128 (in this case = 256). SYS_CLOCK_I video_rdata_1_o DATA0 DATA1 DATA2 DATA3 DATA4 DATA126 DATA128 DATA127 DATA129 DATA130 DATA254 DATA255 rdata_valid_1_o g_RD_CHANNEL(X)_HORIZOANTAL_RESOLUTION = 256 Figure 8 · Timing Diagram of the video_rdata_1_o and rdata_valid_1_o outputs for Read Channel 1 when greater than 128 Figure 9 shows the connection between the read data output for the read Channel 1 when g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION is less than or equal to 128 (in this case = 64). SYS_CLOCK_I video_rdata_1_o DATA0 DATA1 DATA2 DATA3 DATA4 DATA62 DATA63 rdata_valid_1_o g_RD_CHANNEL(X)_HORIZOANTAL_RESOLUTION = 64 Figure 9 · Timing Diagram of the video_rdata_1_o and rdata_valid_1_o outputs for Read Channel 1 when less than or Equal to 128 UG0644: DDR AXI Arbiter User Guide 17 Resource Utilization Resource Utilization Table 3 shows the resource utilization of block controller implemented in the SmartFusion2 device. Table 3 · Resource Utilization for DDR AXI Arbiter Resource Usage DFFs 2270 4-input LUTs 4010 0 MACC 18 g_RD_CHANNEL(X)_HORIZONTAL_RESOLUTION =1280, g_RD_CHANNEL1_BUFFER_LINE_STOARGE = 2, g_RD_CHANNEL2_BUFFER_LINE_STOARGE = 1, g_RD_CHANNEL3_BUFFER_LINE_STOARGE = 1, g_RD_CHANNEL4_BUFFER_LINE_STOARGE = 1, g_WR_CHANNEL1_BUFFER_LINE_STOARGE = 1, RAM1Kx18 g_WR_CHANNEL2_BUFFER_LINE_STOARGE = 1, g_AXI_DWIDTH = 64, g_RD_CHANNEL1_VIDEO_DATA_WIDTH = 24, g_RD_CHANNEL2_VIDEO_DATA_WIDTH = 24, g_RD_CHANNEL3_VIDEO_DATA_WIDTH = 32, g_RD_CHANNEL4_VIDEO_DATA_WIDTH = 08, g_WR_CHANNEL1_VIDEO_DATA_WIDTH = 24, g_WR_CHANNEL2_VIDEO_DATA_WIDTH = 32) RAM64x18 18 0 UG0644: DDR AXI Arbiter User Guide Resource Utilization List of Changes The following table shows important changes made in this document for each revision. Revision Revision 2 (January 2016) Revision 1 (August 2015) Changes Page Updated Figure 1, Figure 4, Figure 7, and Figure 8 (SAR 76101). 3, 12, and 17 Updated Table 1, Table 2, and Table 3 (SAR 76101). 7, 14, and 18 Initial release. UG0644: DDR AXI Arbiter User Guide NA 19 Customer Service Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. 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Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; Enterprise Storage and Communication solutions, security technologies and scalable anti-tamper products; Ethernet Solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: [email protected] © 2016 Microsemi Corporation. All rights reserved. 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It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. 50200644-2/01.16