3 A, Low VIN, Low Noise, CMOS Linear Regulator ADP1763 Data Sheet TYPICAL APPLICATION CIRCUITS APPLICATIONS CIN 10µF PG RPULL-UP 100kΩ VIN COUT 10µF SENSE ON EN PG SS CSS 10nF VOUT = 1.5V VOUT OFF VADJ VREG CREG 1µF REFCAP CREF 1µF GND Figure 1. Fixed Output Operation ADP1763 VIN = 1.8V CIN 10µF PG RPULL-UP 100kΩ VIN VOUT COUT 10µF SENSE EN PG SS CSS 10nF VOUT = 1.5V VADJ REFCAP VREG CREG 1µF ON OFF GND CREF 1µF RADJ 10kΩ Figure 2. Adjustable Output Operation Table 1. Related Devices Regulation to noise sensitive applications such as radio frequency (RF) transceivers, analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuits, phase-locked loops (PLLs), voltage controlled oscillators (VCOs) and clocking integrated circuits Field-programmable gate array (FPGA) and digital signal processor (DSP) supplies Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP1763 is a low noise, low dropout (LDO) linear regulator. It is designed to operate from a single input supply with an input voltage as low as 1.10 V without the requirement of an external bias supply to increase efficiency and provide up to 3 A of output current. The low 95 mV typical dropout voltage at a 3 A load allows the ADP1763 to operate with a small headroom while maintaining regulation and providing better efficiency. The ADP1763 is optimized for stable operation with small 10 μF ceramic output capacitors. The ADP1763 delivers optimal transient performance with minimal board area. Rev. 0 ADP1763 VIN = 1.8V 12923-002 3 A maximum output current Low input voltage supply range VIN = 1.10 V to 1.98 V, no external bias supply required Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V Ultralow noise: 2 μV rms, 100 Hz to 100 kHz Noise spectral density 4 nV/√Hz at 10 kHz 3 nV/√Hz at 100 kHz Low dropout voltage: 95 mV typical at 3 A load Operating supply current: 4.5 mA typical at no load ±1.5% fixed output voltage accuracy over line, load, and temperature Excellent power supply rejection ratio (PSRR) performance 59 dB typical at 10 kHz at 3 A load 43 dB typical at 100 kHz at 3 A load Excellent load/line transient response Soft start to reduce inrush current Optimized for small 10 μF ceramic capacitors Current-limit and thermal overload protection Power-good indicator Precision enable 16-lead, 3 mm × 3 mm LFCSP package 12923-001 FEATURES Device ADP1761 ADP1762 ADP1740/ ADP1741 ADP1752/ ADP1753 ADP1754/ ADP1755 Input Voltage 1.10 V to 1.98 V 1.10 V to 1.98 V 1.6 V to 3.6 V 1.6 V to 3.6 V 1.6 V to 3.6 V Maximum Current 1A Fixed/ Adjustable Fixed/adjustable 2A Fixed/adjustable 2A Fixed/adjustable 0.8 A Fixed/adjustable 1.2 A Fixed/adjustable Package 16-lead LFCSP 16-lead LFCSP 16-lead LFCSP 16-lead LFCSP 16-lead LFCSP The ADP1763 is available in fixed output voltages ranging from 0.9 V to 1.5 V. The output of the adjustable output model can be set from 0.5 V to 1.5 V through an external resistor connected between VADJ and ground. The ADP1763 has an externally programmable soft start time by connecting a capacitor to the SS pin. Short-circuit and thermal overload protection circuits prevent damage in adverse conditions. The ADP1763 is available in a small 16-lead LFCSP package for the smallest footprint solution to meet a variety of applications. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADP1763 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Soft Start Function ..................................................................... 11 Applications ....................................................................................... 1 Adjustable Output Voltage ........................................................ 12 General Description ......................................................................... 1 Enable Feature ............................................................................ 12 Typical Application Circuits............................................................ 1 Power-Good (PG) Feature ........................................................ 12 Revision History ............................................................................... 2 Applications Information .............................................................. 13 Specifications..................................................................................... 3 Capacitor Selection .................................................................... 13 Input and Output Capacitor: Recommended Specifications.. 4 Undervoltage Lockout ............................................................... 14 Absolute Maximum Ratings............................................................ 5 Current-Limit and Thermal Overload Protection ................. 14 Thermal Data ................................................................................ 5 Paralleling ADP1763 for High Current Applications ............ 14 Thermal Resistance ...................................................................... 5 Thermal Considerations............................................................ 15 ESD Caution .................................................................................. 5 PCB Layout Considerations ...................................................... 17 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 18 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 18 Theory of Operation ...................................................................... 11 REVISION HISTORY 4/16—Revision 0: Initial Version Rev. 0 | Page 2 of 18 Data Sheet ADP1763 SPECIFICATIONS VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, ILOAD = 10 mA, CIN = 10 μF, COUT = 10 μF, CREF = 1 μF, CREG = 1 μF, TA = 25°C, Minimum and maximum limits at TJ = −40°C to +125°C, unless otherwise noted. Table 2. Parameter INPUT VOLTAGE SUPPLY RANGE CURRENT Operating Supply Current Shutdown Current OUTPUT NOISE1 Noise Spectral Density POWER SUPPLY REJECTION RATIO1 Symbol VIN Test Conditions/Comments TJ = −40°C to +125°C IGND ILOAD = 0 μA ILOAD = 10 mA ILOAD = 100 mA ILOAD = 3 A EN = GND TJ = −40°C to +85°C, VIN = (VOUT + 0.2 V) to 1.98 V TJ = 85°C to 125°C, VIN = (VOUT + 0.2 V) to 1.98 V 10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V 100 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V 10 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V 100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V 10 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V 100 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V VOUT = 0.9 V to 1.5 V, ILOAD = 100 mA At 10 kHz At 100 kHz ILOAD = 3 A, modulated VIN 10 kHz, VOUT = 1.3 V, VIN = 1.7 V 100 kHz, VOUT = 1.3 V, VIN = 1.7 V 1 MHz, VOUT = 1.3 V, VIN = 1.7 V 10 kHz, VOUT = 0.9 V, VIN = 1.3 V 100 kHz, VOUT = 0.9 V, VIN = 1.3 V 1 MHz, VOUT = 0.9 V, VIN = 1.3 V IGND-SD OUTNOISE OUTNSD PSRR OUTPUT VOLTAGE Output Voltage Range Fixed Output Voltage Accuracy Min 1.10 Typ Max 1.98 Unit V 4.5 4.9 5.5 12 2 8 8 8.5 16 180 mA mA mA mA μA μA 800 μA 12 2 15 2 21 2 μV rms μV rms μV rms μV rms μV rms μV rms 4 3 nV/√Hz nV/√Hz 59 43 37 62 45 33 dB dB dB dB dB dB TA = 25°C VOUT_FIXED VOUT_ADJ VOUT ADJUSTABLE PIN CURRENT IADJ ADJUSTABLE OUTPUT VOLTAGE GAIN FACTOR AD REGULATION Line Regulation Load Regulation2 DROPOUT VOLTAGE3 ∆VOUT/∆VIN ∆VOUT/∆IOUT VDROPOUT START-UP TIME1, 4 SOFT START CURRENT CURRENT-LIMIT THRESHOLD5 tSTART-UP ISS ILIMIT ILOAD = 100 mA, TA = 25°C 10 mA < ILOAD < 3 A, VIN = (VOUT + 0.2 V) to 1.98 V, TJ = 0°C to 85°C 10 mA < ILOAD < 3 A, VIN = (VOUT + 0.2 V) to 1.98 V TA = 25°C VIN = (VOUT + 0.2 V) to 1.98 V TA = 25°C VIN = (VOUT + 0.2 V) to 1.98 V VIN = (VOUT + 0.2 V) to 1.98 V ILOAD = 10 mA to 3 A ILOAD = 100 mA, VOUT ≥ 1.2 V ILOAD = 3 A, VOUT ≥ 1.2 V CSS = 10 nF, VOUT = 1.3 V 1.1 V ≤ VIN ≤ 1.98 V Rev. 0 | Page 3 of 18 0.9 0.5 −0.5 −1 1.5 1.5 +0.5 +1.5 V V % % −1.5 +1.5 % 50.5 51.0 μA μA 49.5 48.8 50.0 50.0 3.0 2.95 3.055 −0.15 8 3.3 0.12 12 95 0.6 10 4 +0.15 0.45 23 145 12 5 %/V %/A mV mV ms μA A ADP1763 Parameter THERMAL SHUTDOWN Threshold Hysteresis POWER-GOOD (PG) OUTPUT THRESHOLD Output Voltage Falling Rising PG OUTPUT Output Voltage Low Leakage Current Delay1 PRECISION EN INPUT Logic Input High Low Input Logic Hysteresis Input Leakage Current Input Delay Time UNDERVOLTAGE LOCKOUT Input Voltage Rising Falling Hysteresis Data Sheet Symbol Test Conditions/Comments TSSD TSSD-HYS TJ rising 150 15 °C °C PGFALL PGRISE 1.1 V ≤ VIN ≤ 1.98 V 1.1 V ≤ VIN ≤ 1.98 V −7.5 −5 % % PGLOW IPG-LKG PGDELAY 1.1 V ≤ VIN ≤ 1.98 V, IPG ≤ 1 mA 1.1 V ≤ VIN ≤ 1.98 V ENRISING to PGRISING 1.1 V ≤ VIN ≤ 1.98 V 0.01 0.75 ENHIGH ENLOW ENHYS IEN-LKG tIEN-DLY UVLO UVLORISE UVLOFALL UVLOHYS Min 595 550 EN = VIN or GND From EN rising from 0 V to VIN to 0.1 × VOUT TJ = −40°C to +125°C TJ = −40°C to +125°C 0.87 Typ Max Unit 0.35 1 V μA ms 625 580 45 0.01 100 690 630 mV mV mV μA μs 1.01 0.93 80 1.06 1 V V mV 1 Guaranteed by design and characterization; not production tested. Based on an endpoint calculation using 10 mA and 3 A loads. 3 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output voltages above 1.1 V. 4 Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of its nominal value. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. 2 INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS Table 3. Parameter CAPACITANCE1 Input Output Regulator Reference CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR) CIN, COUT CREG, CREF 1 Symbol CIN COUT CREG CREF RESR Test Conditions/Comments TA = −40°C to +125°C Min Typ 7.0 7.0 0.7 0.7 10 10 1 1 Max Unit μF μF μF μF TA = −40°C to +125°C 0.001 0.001 0.5 0.2 Ω Ω The minimum input and output capacitance must be >7.0 μF over the full range of the operating conditions. Consider the full range of the operating conditions in the application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. 0 | Page 4 of 18 Data Sheet ADP1763 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VIN to GND EN to GND VOUT to GND SENSE to GND VREG to GND REFCAP to GND VADJ to GND SS to GND PG to GND Storage Temperature Range Operating Temperature Range Operating Junction Temperature Lead Temperature (Soldering, 10 sec) Rating −0.3 V to +2.16 V −0.3 V to +3.96 V −0.3 V to VIN −0.3 V to VIN −0.3 V to VIN −0.3 V to VIN −0.3 V to VIN −0.3 V to VIN −0.3 V to +3.96 V −65°C to +150°C −40°C to +125°C 125°C 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL DATA Absolute maximum ratings apply only individually, not in combination. The ADP1763 may be damaged when junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction to ambient thermal resistance of the package (θJA). TJ is calculated using the following formula: The junction to ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θJA may vary, depending on PCB material, layout, and environmental conditions. The specified values of θJA are based on a 4-layer, 4 in × 3 in circuit board. For details about board construction, refer to JEDEC JESD51-7. ΨJB is the junction to board thermal characterization parameter with units of °C/W. ΨJB of the package is based on modeling and a calculation using a 4-layer board. The JEDEC JESD51-12 document, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than a single path, as in thermal resistance (θJB). Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package, factors that make ΨJB more useful in real-world applications. The maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD), using the following formula: TJ = TB + (PD × ΨJB) Refer to the JEDEC JESD51-8 and JESD51-12 documents for more detailed information about ΨJB. THERMAL RESISTANCE θJA and ΨJB are specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance for a 4-Layer 6400 mm2 Copper Size Package Type 16-Lead LFCSP ESD CAUTION TJ = TA + (PD × θJA) The junction to ambient thermal resistance (θJA) of the package is based on modeling and a calculation using a 4-layer board. Rev. 0 | Page 5 of 18 θJA 56 ΨJB 28.4 Unit °C/W ADP1763 Data Sheet 13 SENSE 14 SS 16 EN 15 PG PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 1 VIN 3 12 VOUT ADP1763 TOP VIEW (Not to Scale) 10 VOUT GND 7 VOUT VADJ 8 VREG 6 9 REFCAP 5 VIN 4 11 VOUT NOTES 1. THE EXPOSED PAD IS ELECTRICALLY CONNECTED TO GND. IT IS RECOMMENDED THAT THIS PAD BE CONNECTED TO A GROUND PLANE ON THE PCB. THE EXPOSED PAD IS ON THE BOTTOM OF THE PACKAGE. 12923-003 VIN 2 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 to 4 Mnemonic VIN 5 REFCAP 6 VREG 7 8 GND VADJ 9 to 12 VOUT 13 SENSE 14 15 SS PG 16 EN EP Description Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor. Note that all four VIN pins must be connected to the source supply. Reference Filter Capacitor. Connect a 1 μF capacitor from the REFCAP pin to ground. Do not connect a load to ground. Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect a load to ground. Ground. Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 kΩ external resistor between the VADJ pin and ground to set the output voltage to 1.5 V. For the fixed output option, leave this pin floating. Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor. Note that all four VOUT pins must be connected to the load. Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect VSENSE as close to the load as possible to minimize the effect of IR voltage drop between VOUT and the load. Soft Start Pin. A 10 nF capacitor connected to the SS pin and ground sets the start-up time to 0.6 ms. Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown mode, current-limit mode, or thermal shutdown mode, or if VOUT falls below 90% of the nominal output voltage, the PG pin immediately transitions low. Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For automatic startup, connect the EN pin to the VIN pin. Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected to a ground plane on the PCB. The exposed pad is on the bottom of the package. Rev. 0 | Page 6 of 18 Data Sheet ADP1763 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 1.5 V, VOUT = 1.3 V, TA = 25°C, unless otherwise noted. 14 1.301 1.299 12 10 8 6 4 1.297 2 –25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) 0 –50 12923-004 1.295 –50 NO LOAD ILOAD = 100mA ILOAD = 1A ILOAD = 3A –25 0 ILOAD = 10mA ILOAD = 500mA ILOAD = 2A 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) Figure 4. Output Voltage (VOUT) vs. Junction Temperature 12923-007 OUTPUT VOLTAGE (V) 1.303 16 NO LOAD ILOAD = 10mA ILOAD = 100mA ILOAD = 1A ILOAD = 2A ILOAD = 3A GROUND CURRENT (mA) 1.305 Figure 7. Ground Current vs. Junction Temperature 1.303 14 12 GROUND CURRENT (mA) OUTPUT VOLTAGE (V) 1.303 1.302 1.302 10 8 6 4 1 10 LOAD CURRENT (A) 0 0.01 GROUND CURRENT (mA) 12 1.304 1.302 1.300 10 8 6 4 2 1.6 2.0 14 = 100mA = 1A = 2A = 3A 1.306 1.298 1.5 10 Figure 8. Ground Current vs. Load Current 1.7 1.8 1.9 INPUT VOLTAGE (V) 2.0 12923-006 OUTPUT VOLTAGE (V) 1.308 ILOAD ILOAD ILOAD ILOAD 1 LOAD CURRENT (A) Figure 5. Output Voltage (VOUT) vs. Load Current 1.310 0.1 12923-008 0.1 12923-005 1.301 0.01 12923-009 2 Figure 6. Output Voltage vs. Input Voltage 0 1.5 NO LOAD ILOAD = 10mA ILOAD = 100mA ILOAD = 500mA ILOAD = 1A ILOAD = 2A ILOAD = 3A 1.6 1.7 1.8 1.9 INPUT VOLTAGE (V) Figure 9. Ground Current vs. Input Voltage Rev. 0 | Page 7 of 18 ADP1763 160 140 12 GROUND CURRENT (mA) 180 SHUTDOWN CURRENT (µA) 14 VIN = 1.5V VIN = 1.7V VIN = 1.9V VIN = 1.6V VIN = 1.8V VIN = 1.98V 120 100 80 60 40 10 8 6 4 20 2 0 –25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) 0 1.1 12923-010 –20 –50 NO LOAD ILOAD = 10mA ILOAD = 100mA ILOAD = 500mA ILOAD = 1A ILOAD = 2A ILOAD = 3A 1.2 1.3 1.4 1.5 1.6 INPUT VOLTAGE (V) Figure 10. Shutdown Current vs. Junction Temperature at Various Input Voltages (VIN) 12923-013 200 Data Sheet Figure 13. Ground Current vs. Input Voltage (in Dropout), VOUT = 1.3 V 100 90 3A/µs SLEW RATE DROPOUT VOLTAGE (mV) 80 70 2 LOAD 60 50 40 1 VOUT 30 20 1 10 LOAD CURRENT (A) Figure 11. Dropout Voltage vs. Load Current, VOUT = 1.3 V 1.35 OUTPUT VOLTAGE (V) 1.30 CH1 50.0mV 12923-011 0 0.1 B W CH2 2.00A M4.00µs T 18.70% A CH2 640mA 12923-014 10 Figure 14. Load Transient Response, COUT = 10 μF, VIN = 1.8 V, VOUT = 1.3 V ILOAD = 100mA ILOAD = 1A ILOAD = 2A ILOAD = 3A 3A/µs SLEW RATE 2 LOAD 1.25 1.20 1 VOUT 1.3 1.4 INPUT VOLTAGE (V) 1.5 Figure 12. Output Voltage vs. Input Voltage (in Dropout), VOUT = 1.3 V CH1 50.0mV B W CH2 2.00A M4.00µs T 18.70% A CH2 640mA 12923-015 1.10 1.2 12923-012 1.15 Figure 15. Load Transient Response, COUT = 47 μF, VIN = 1.8 V, VOUT = 1.3 V Rev. 0 | Page 8 of 18 Data Sheet ADP1763 –10 –30 VIN 2 VIN = 1.1V VIN = 1.2V VIN = 1.3V VIN = 1.4V VIN = 1.5V VIN = 1.6V –20 1V/µs SLEW RATE PSRR (dB) –40 VOUT 1 –50 –60 –70 –80 –90 CH2 500mV M2.00µs T 17.50% A CH2 1.68V –110 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 12923-019 CH1 5.00mV 12923-016 –100 Figure 19. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various Loads, VOUT = 0.9 V, Load Current = 3 A Figure 16. Line Transient Response, Load Current = 3 A, VIN = 1.5 V to 1.98 V Step, VOUT = 1.3 V –10 16 –20 14 –30 –40 10 8 PSRR (dB) NOISE (µV rms) 12 VOUT = 1.3V (100Hz TO 100kHz) VOUT = 1.3V (10Hz TO 100kHz) 6 –50 –60 –70 –80 VIN = 1.5V VIN = 1.6V VIN = 1.7V VIN = 1.8V VIN = 1.9V VIN = 1.98V –90 2 –100 1 10 LOAD CURRENT (A) –110 12923-017 0 0.1 1 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 17. Noise vs. Load Current for Various Output Voltages Figure 20. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various Loads, VOUT = 1.3 V, Load Current = 3 A –10 10k VIN = 1.7V VIN = 1.8V VIN = 1.9V VIN = 1.98V –20 –30 1k –40 PSRR (dB) 100 10 –50 –60 –70 –80 –90 1 100 –100 1k FREQUENCY (Hz) 10k 100k Figure 18. Noise Spectral Density vs. Frequency for Various Output Voltages, ILOAD = 100 mA Rev. 0 | Page 9 of 18 –110 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various Loads, VOUT = 1.5 V, Load Current = 3 A 12923-021 0.1 10 VOUT = 0.9V VOUT = 1.3V VOUT = 1.5V 12923-018 NOISE SPECTRAL DENSITY (nV/√Hz) 10 12923-020 4 ADP1763 –10 Data Sheet ILOAD = 500mA ILOAD = 1A ILOAD = 2A ILOAD = 3A –20 –30 PSRR (dB) –40 –50 –60 –70 –80 –90 –110 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 12923-022 –100 Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various Input Voltages, VOUT = 1.3 V, VIN = 1.7 V Rev. 0 | Page 10 of 18 Data Sheet ADP1763 THEORY OF OPERATION The ADP1763 is an LDO, low noise linear regulator that uses an advanced proprietary architecture to achieve high efficiency regulation. It also provides high PSRR and excellent line and load transient response using a small 10 F ceramic output capacitor. The device operates from a 1.10 V to 1.98 V input rail to provide up to 3 A of output current. Supply current in shutdown mode is typically 2 μA. ADP1763 VIN VREG VOUT INTERNAL BIAS SUPPLY SHORT-CIRCUIT, THERMAL PROJECT SENSE operating conditions. When EN is high, VOUT turns on. When EN is low, VOUT turns off. For automatic startup, tie EN to VIN. SOFT START FUNCTION For applications that require a controlled startup, the ADP1763 provides a programmable soft start function. The programmable soft start is useful for reducing inrush current upon startup and for providing voltage sequencing. To implement soft start, connect a small ceramic capacitor from SS to GND. At startup, a 10 μA current source charges this capacitor. The voltage at SS limits the ADP1763 start-up output voltage, providing a smooth ramp-up to the nominal output voltage. To calculate the start-up time for the fixed output and adjustable output, use the following equations: tSTART-UP_FIXED = tDELAY + VREF × (CSS/ISS) (1) tSTART-UP_ADJ = tDELAY + VADJ × (CSS/ISS) PG REFERENCE, BIAS GND SS BLOCK SS 12923-023 EN REFCAP where: tDELAY is a fixed delay of 100 μs. VREF is a 0.5 V internal reference for the fixed output model option. CSS is the soft start capacitance from SS to GND. ISS is the current sourced from SS (10 μA). VADJ is the voltage at the VADJ pin equal to RADJ × IADJ. 1.7 Figure 23. Functional Block Diagram, Fixed Output 1.5 ADP1763 INTERNAL BIAS SUPPLY SHORT-CIRCUIT, THERMAL PROJECT 1.1 SENSE VOUT, EN (V) VREG 1.3 VOUT VIN (2) IADJ EN 0.9 0.7 0.5 VADJ 0.3 0.1 –0.1 –0.2 SS BLOCK SS REFCAP 0.8 1.3 1.8 TIME (ms) 12923-024 GND 0.3 12923-025 EN CSS = 0nF CSS = 10nF CSS = 22nF PG Figure 25. Fixed VOUT Ramp-Up with External Soft Start Capacitor (VOUT, EN) vs. Time 2.0 Figure 24. Functional Block Diagram, Adjustable Output 1.0 0.5 EN VOUT = 0.5V; CSS VOUT = 0.5V; CSS VOUT = 1.5V; CSS VOUT = 1.5V; CSS 0 –0.5 –0.2 0.3 0.8 TIME (ms) 1.3 = 10nF = 22nF = 10nF = 22nF 1.8 12923-226 The ADP1763 is available in output voltages ranging from 0.9 V to 1.5 V for a fixed output. Contact a local Analog Devices, Inc., sales representative for other fixed voltage options. The adjustable output option can be set from 0.5 V to 1.5 V. The ADP1763 uses the EN pin to enable and disable the VOUT pin under normal 1.5 VOUT, EN (V) Internally, the ADP1763 consists of a reference, an error amplifier, and a pass device. The output current is delivered via the pass device, which is controlled by the error amplifier, forming a negative feedback system that ideally drives the feedback voltage to equal the reference voltage. If the feedback voltage is lower than the reference voltage, the negative feedback drives more current, increasing the output voltage. If the feedback voltage is higher than the reference voltage, the negative feedback drives less current, decreasing the output voltage. Figure 26. Adjustable VOUT Ramp-Up with External Soft Start Capacitor (VOUT, EN) vs. Time Rev. 0 | Page 11 of 18 ADP1763 Data Sheet ADJUSTABLE OUTPUT VOLTAGE POWER-GOOD (PG) FEATURE The output voltage of the ADP1763 can be set over a 0.5 V to 1.5 V range. Connect a resistor (RADJ) from the VADJ pin to ground to set the output voltage. To calculate the output voltage, use the following equation: The ADP1763 provides a power-good pin (PG) to indicate the status of the output. This open-drain output requires an external pull-up resistor that can be connected to VIN or VOUT. If the device is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below 90% of the nominal output voltage, PG immediately transitions low. During soft start, the rising threshold of the power-good signal is 95% of the nominal output voltage. VOUT = AD × (RADJ × IADJ) (3) where: AD is the gain factor with a typical value of 3.0 between the VADJ pin and the VOUT pin. IADJ is the 50.0 μA constant current out of the VADJ pin. ENABLE FEATURE The ADP1763 uses the EN pin to enable and disable the VOUT pins under normal operating conditions. As shown in Figure 27, when a rising voltage on EN crosses the active threshold, VOUT turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off. EN The open-drain output is held low when the ADP1763 has sufficient input voltage to turn on the internal PG transistor. An optional soft start delay can be detected. The PG transistor is terminated via a pull-up resistor to VOUT or VIN. Power-good accuracy is 92.5% of the nominal regulator output voltage when this voltage is rising, with a 95% trip point when this voltage is falling. Regulator input voltage brownouts or glitches trigger a power no good if VOUT falls below 92.5%. A normal power-down triggers a power good when VOUT is at 95%. VOUT VIN 1 VOUT 2 CH1 200mV B W CH2 200mV B W M4.0ms A CH1 T 8.26ms 768mV 12923-026 1 PG 4 As shown in Figure 28, the EN pin has hysteresis built in. This hysteresis prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. CH1 1.00V CH2 1.00V CH4 1.00V M100µs A CH4 T 228.0000µs 420mV 12923-027 Figure 27. Typical EN Pin Operation Figure 29. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.3 V) 1.4 1.3 1.2 VIN 1.0 0.9 1 0.8 VOUT 0.7 0.6 0.5 2 PG 0.4 0.3 0.2 0 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65 EN VOLTAGE (V) Figure 28. Output Voltage vs. Typical EN Pin Voltage, VOUT = 1.3 V CH1 1.00V CH2 1.00V CH4 1.00V M200µs A CH1 T 0.000000s 3.00V 12923-128 4 0.1 12923-127 OUTPUT VOLTAGE (V) 1.1 Figure 30. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.3 V) Rev. 0 | Page 12 of 18 Data Sheet ADP1763 APPLICATIONS INFORMATION CAPACITOR SELECTION Input and Output Capacitor Properties Output Capacitor Use any good quality ceramic capacitors with the ADP1763, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. The ADP1763 is designed for operation with small, space-saving ceramic capacitors, but it can function with most commonly used capacitors as long as care is taken with the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 10 μF capacitance with an ESR of 500 mΩ or less is recommended to ensure the stability of the ADP1763. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP1763 to large changes in load current. Figure 31 and Figure 32 show the transient responses for output capacitance values of 10 μF and 47 μF, respectively. 2 ILOAD Figure 33 shows the capacitance vs. bias voltage characteristics of an 0805 case, 10 μF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package size or voltage rating. 12 VOUT B W CH2 2.00A M1.00µs T 18.70% A CH2 640mA CAPACITANCE (µF) CH1 50.0mV 10 12923-030 1 8 6 4 Figure 31. Output Transient Response, COUT = 10 μF 0 0 1 2 3 4 5 6 DC BIAS VOLTAGE (V) ILOAD Figure 33. Capacitance vs. DC Bias Voltage 2 1 Use Equation 4 to determine the worst case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. VOUT CEFF = COUT × (1 − tempco) × (1 − TOL) CH2 2.00A M1.00µs T 19.00% A CH2 640mA (4) where: CEFF is the effective capacitance at the operating voltage. COUT is the output capacitor. Tempco is the worst case capacitor temperature coefficient. TOL is the worst case component tolerance. 12923-031 CH1 50.0mV 12923-032 2 Figure 32. Output Transient Response, COUT = 47 μF Input Bypass Capacitor Connecting a 10 μF capacitor from the VIN pin to the GND pin to ground reduces the circuit sensitivity to the PCB layout, especially when long input traces or a high source impedance is encountered. If output capacitance greater than 10 μF is required, it is recommended that the input capacitor be increased to match it. In this example, the worst case temperature coefficient (tempco) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT = 10 μF at 1.0 V, as shown in Figure 33. Substituting these values in Equation 4 yields Rev. 0 | Page 13 of 18 CEFF = 10 μF × (1 − 0.15) × (1 − 0.1) = 7.65 μF ADP1763 Data Sheet Consider the case where a hard short from VOUT to ground occurs. At first, the ADP1763 reaches the current limit so that only 4 A is conducted into the short circuit. If self heating of the junction becomes great enough to cause its temperature to rise above 150°C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135°C, the output turns on and conducts 4 A into the short circuit, again causing the junction temperature to rise above 150°C. This thermal oscillation between 135°C and 150°C causes a current oscillation between 4 A and 0 A that continues as long as the short circuit remains at the output. Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP1763, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. UNDERVOLTAGE LOCKOUT The ADP1763 has an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 1.06 V. The UVLO ensures that the ADP1763 inputs and the output behave in a predictable manner during power-up. Current-limit and thermal overload protections are intended to protect the device against accidental overload conditions. For reliable operation, limit device power dissipation externally so that junction temperatures do not exceed 125°C. CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The ADP1763 is protected against damage due to excessive power dissipation by current-limit and thermal overload protection circuits. The ADP1763 is designed to reach the current limit when the output load reaches 4 A (typical). When the output load exceeds 4 A, the output voltage is reduced to maintain a constant current limit. PARALLELING ADP1763 FOR HIGH CURRENT APPLICATIONS In applications where high output current is required while maintaining low noise and high PSRR performance, connect two ADP1763 devices in parallel to handle loads up to 5 A. Thermal overload protection is included, which limits the junction temperature to a maximum of 150°C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature begins to rise above 150°C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 135°C (typical), the output is turned on again, and the output current is restored to its nominal value. When paralleling the ADP1763, the two outputs must be of the same voltage setting to maintain stable current sharing between the two LDO regulators. To improve current sharing accuracy, add identical ballast resistors (RBALLAST) at the output of each regulator, as shown in Figure 34. Note that large ballast resistors improve current sharing accuracy but degrade the load regulation performance and increase the losses along the power line; therefore, it is recommended to keep the ballast resistors at a minimum. In addition, tie the VADJ, SS, and REFCAP pins of the LDO regulators together to minimize error between the two outputs. ADP1763 CIN 10µF VIN VOUT SS VADJ VREG CREG 1µF REFCAP GND ADP1763 CIN 10µF VIN VOUT RADJ 4.02kΩ CREF 1µF RBALLAST = 5mΩ COUT 10µF SENSE EN PG SS VADJ VREG CREG 1µF ENABLE EN PG VOUT = 1.2V/5A COUT 10µF SENSE RPULLUP 100kΩ CSS 1nF RBALLAST = 5mΩ REFCAP GND CREF 1µF 12923-133 VIN = 1.5V Figure 34. Two ADP1763 Devices Connected in Parallel to Achieve Higher Current Output Rev. 0 | Page 14 of 18 Data Sheet ADP1763 Use Equation 5 to calculate the output of the two paralleled ADP1763 LDOs. VOUT = 2 × AD × (RADJ × IADJ) (5) 140 where: AD is the gain factor with a typical value of 3.0 between the VADJ pin and the VOUT pin. IADJ is the 50.0 μA constant current out of the VADJ pin. TJ MAX θJA (°C/W), LFCSP 138.1 102.9 76.9 67.3 56 100 1A 80 40 100mA 20 10mA 0.4 0.6 0.8 1.0 1.2 1.4 1.6 12923-033 500mA 60 VIN – VOUT (V) Figure 35. 6400 mm2 of PCB Copper, TA = 25°C 140 TJ MAX 120 Table 8. Typical ΨJB Values Copper Size (mm2) 100 500 1000 2A 1A 100 80 500mA 60 40 100mA 20 10mA 0 0.2 ΨJB (°C/W) at 1 W 33.3 28.9 28.5 2A 3A 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VIN – VOUT (V) 12923-034 Table 7. Typical θJA Values 3A 0 0.2 JUNCTION TEMPERATURE (°C) To guarantee reliable operation, the junction temperature of the ADP1763 must not exceed 125°C. To ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistance between the junction and ambient air (θJA). The θJA value is dependent on the package assembly compounds used and the amount of copper to which the GND pin and the exposed pad (EPAD) of the package are soldered on the PCB. Table 7 shows typical θJA values for the 16-lead LFCSP for various PCB copper sizes. Table 8 shows typical ΨJB values for the 16-lead LFCSP. JUNCTION TEMPERATURE (°C) 120 THERMAL CONSIDERATIONS Copper Size (mm2) 25 100 500 1000 6400 Figure 35 through Figure 40 show junction temperature calculations for different ambient temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. Figure 36. 500 mm2 of PCB Copper, TA = 25°C 140 TJ MAX (6) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND) (7) where: VIN and VOUT are the input and output voltages, respectively. ILOAD is the load current. IGND is the ground current. 3A 1A 2A 100 500mA 80 60 100mA 40 10mA 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VIN – VOUT (V) As shown in Equation 6, for a given ambient temperature, and computed power dissipation, a minimum copper size requirement exists for the PCB to ensure that the junction temperature does not rise above 125°C. Rev. 0 | Page 15 of 18 Figure 37. 25 mm2 of PCB Copper, TA = 25°C 1.6 12923-035 TJ = TA + (PD × θJA) 120 JUNCTION TEMPERATURE (°C) To calculate the junction temperature of the ADP1763, use the following equation: ADP1763 Data Sheet 140 Figure 41 through Figure 44 show junction temperature calculations for different board temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. TJ MAX 1A 3A 2A 100 140 500mA TJ MAX 120 80 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) 120 100mA 60 10mA 40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VIN – VOUT (V) 12923-036 20 3A 100 2A 80 1A 60 500mA 40 100mA 20 10mA 0 0.2 140 0.4 0.6 0.8 TJ MAX 3A 2A 1.2 1.4 1.6 Figure 41. 500 mm2 of PCB Copper, TB = 25°C 1A 140 100 TJ MAX 500mA 120 80 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) 120 1.0 VIN – VOUT (V) 12923-039 Figure 38. 6400 mm2 of PCB Copper, TA = 50°C 100mA 60 10mA 40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VIN – VOUT (V) 12923-037 20 2A 3A 100 1A 80 500mA 60 100mA 10mA 40 20 140 120 0.4 0.6 TJ MAX 2A 1A 0.8 1 1.2 1.4 1.6 VIN – VOUT (V) Figure 42. 500 mm2 of PCB Copper, TB = 50°C 500mA 100 140 80 120 TJ MAX 100mA JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) 0 0.2 3A 12923-040 Figure 39. 500 mm2 of PCB Copper, TA = 50°C 60 10mA 40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VIN – VOUT (V) 1.6 12923-038 20 3A 100 2A 80 1A 60 500mA 40 100mA 20 10mA In cases where the board temperature is known, the thermal characterization parameter (ΨJB) can be used to estimate the junction temperature rise. The maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: TJ = TB + (PD × ΨJB) (8) Rev. 0 | Page 16 of 18 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VIN – VOUT (V) Figure 43. 1000 mm2 of PCB Copper, TB = 25°C 1.6 12923-041 Figure 40. 25 mm2 of PCB Copper, TA = 50°C Data Sheet ADP1763 140 Use of 0603 or 0805 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. TJ MAX JUNCTION TEMPERATURE (°C) 120 2A 3A 100 1A 80 500mA 60 100mA 10mA 40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VIN – VOUT (V) 12923-042 20 Figure 44. 1000 mm2 of PCB Copper, TB = 50°C, LFCSP 12923-043 TADP1763 = 112°C Figure 46. Evaluation Board 12923-145 12923-145 TB = 92°C Figure 45. Thermal Image of the ADP1763 Evaluation Board at ILOAD = 3 A, VIN = 1.5 V, VOUT = 1.3 V, TB = 92°C Figure 45 shows a thermal image of the ADP1763 evaluation board operating at a 3 A current load. The total power dissipation on the ADP1763 is 600 mW, which makes the temperature on the surface of the device higher by 30°C than the temperature of the evaluation board. Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of ADP1763. However, as shown in Table 8, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. 12923-044 PCB LAYOUT CONSIDERATIONS Figure 47. Typical Board Layout, Top Side Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Place the soft start capacitor (CSS) as close as possible to the SS pin. Place the reference capacitor (CREF) and regulator capacitor (CREG) as close as possible to the REFCAP pin and VREG pin, respectively. Connect the load as close as possible to the VOUT and SENSE pins. Rev. 0 | Page 17 of 18 12923-045 Use the following recommendations when designing PCBs: Figure 48. Typical Board Layout, Bottom Side ADP1763 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 0.30 0.23 0.18 0.50 BSC PIN 1 INDICATOR 16 13 1 12 1.75 1.60 SQ 1.45 EXPOSED PAD 9 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 4 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 08-16-2010-E 3.10 3.00 SQ 2.90 Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP1763ACPZ-R7 ADP1763ACPZ-0.9-R7 ADP1763ACPZ0.95-R7 ADP1763ACPZ-1.0-R7 ADP1763ACPZ-1.1-R7 ADP1763ACPZ-1.2-R7 ADP1763ACPZ1.25-R7 ADP1763ACPZ-1.3-R7 ADP1763ACPZ-1.5-R7 ADP1763-1.3-EVALZ ADP1763-ADJ-EVALZ 1 2 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Output Voltage (V)2 Adjustable 0.9 0.95 1.0 1.1 1.2 1.25 1.3 1.5 1.3 1.1 Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Evaluation Board Package Option CP-16-22 CP-16-22 CP-16-22 CP-16-22 CP-16-22 CP-16-22 CP-16-22 CP-16-22 CP-16-22 Branding LS0 LS1 LUQ LS2 LS3 LS4 LS5 LS6 LS7 Z = RoHS Compliant Part. For additional options, contact a local Analog Devices sales or distribution representative. Additional voltage output options available include the following: 0.5 V, 0.55 V, 0.6 V, 0.65 V, 0.7 V, 0.75 V, 0.8 V, 0.85 V, 1.05 V, 1.15 V, 1.35 V, 1.4 V, or 1.45 V. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12923-0-4/16(0) Rev. 0 | Page 18 of 18