ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com ADuCM320i/ADuCM322/ADuCM322i Reference Manual SCOPE This manual provides a detailed description of the ADuCM320i/ADuCM322/ADuCM322i functionality and features. FUNCTIONAL BLOCK DIAGRAMS XTALO XTALI ECLKIN BUF_VREF2V5 2.5V BAND GAP 1.8V LDO CLOCK SYSTEM 32.768kHz 16MHz OSC 80MHz PLL AIN0 AIN5 14-BIT SAR ADC MUX AIN6 DGNDx AVDDx AGNDx IOVDDx IOGNDx AIN15 INTERNAL CHANNELS: TEMPERATURE, AVDD, IOVDD MEMORY 2 × 128kB FLASH 32kB SRAM COMPARATOR VDAC0 VDAC VDAC7 VDAC IDAC0 IDAC IDAC3 IDAC ARM CORTEX-M3 PROCESSOR DMA NVIC ADuCM320i GPIO PORTS UART 2 × SPI 2 × I2C EXT IRQs MDIO PLA GENERALPURPOSE I/O PORTS 3 × GENERALPURPOSE TIMER WATCHDOG TIMER WAKE-UP TIMER PWM PWM0 TO PWM6 RESET SYSTEM SERIAL WIRE SWDIO PVDDx PGND 13437-001 SWCLK RESET Figure 1. ADuCM320i Functional Block Diagram BUF_VREF2V5 XTALO XTALI ECLKIN 2.5V BAND GAP 1.8V LDO CLOCK SYSTEM 32.768kHz 16MHz OSC 80MHz PLL AIN0 AIN5 AIN6 MUX SAR ADC DGNDx AVDDx AGNDx IOVDDx IOGNDx AIN15 ARM CORTEX-M3 PROCESSOR INTERNAL CHANNELS: TEMPERATURE, AVDD, IOVDD MEMORY 2 × 128kB FLASH 32kB SRAM COMPARATOR VDAC0 GENERALPURPOSE I/O PORTS 3 × GENERALPURPOSE TIMER WATCHDOG TIMER WAKE-UP TIMER PWM PWM0 TO PWM6 VDAC DMA NVIC VDAC7 GPIO PORTS UART 2 × SPI 2 × I2C EXT IRQs MDIO PLA VDAC ADuCM322/ ADuCM322i RESET SYSTEM SERIAL WIRE SWDIO PVDDx PGND RESET Figure 2. ADuCM322/ADuCM322i Functional Block Diagram PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 190 13437-102 SWCLK UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual TABLE OF CONTENTS Scope .................................................................................................. 1 Register Summary: ADC Circuit ............................................. 26 Functional Block Diagrams ............................................................. 1 Register Details: ADC Circuit .................................................. 27 Revision History ............................................................................... 4 Register Summary: Additional Registers ................................ 30 Using the ADuCM320i/ADuCM322/ADuCM322i Reference Manual ............................................................................................... 5 Register Details: Additional Registers ..................................... 31 Analog Comparator ....................................................................... 32 Number Notations ........................................................................ 5 Analog Comparator Features.................................................... 32 Register Access Conventions ...................................................... 5 Analog Comparator Overview ................................................. 32 Introduction to the ADuCM320i/ADuCM322/ADuCM322i ... 6 Analog Comparator Operation ................................................ 32 Main Features of the ADuCM320i/ADuCM322/ADuCM322i ......................................................................................................... 7 Register Summary: Analog Comparator ................................. 32 Memory Organization ................................................................. 7 Clocking Architecture ...................................................................... 9 Clocking Architecture Features .................................................. 9 Clocking Architecture Block Diagram ...................................... 9 Clocking Architecture Overview.............................................. 10 Register Summary: Clock Architecture ................................... 10 Clocking Architecture Operation............................................. 10 Register Details: Clock Architecture ........................................ 10 Power Management Unit ............................................................... 14 Power Management Unit Features ........................................... 14 Power Management Unit Overview......................................... 14 Power Management Unit Operation ........................................ 14 Code Examples ........................................................................... 15 Register Summary: Power Management Unit ........................ 16 Register Details: Power Management Unit ............................. 16 ARM Cortex-M3 Processor .......................................................... 17 ARM Cortex-M3 Processor Features....................................... 17 ARM Cortex-M3 Processor Overview .................................... 17 ARM Cortex-M3 Processor Operation ................................... 17 ARM Cortex-M3 Processor Related Documents................... 18 ADC Circuit .................................................................................... 19 ADC Circuit Features ................................................................ 19 ADC Circuit Block Diagram..................................................... 19 ADC Circuit Overview .............................................................. 20 ADC Circuit Operation ............................................................. 20 ADC Transfer Function ............................................................. 21 ADC Typical Setup Sequence ................................................... 22 ADC Input Buffer ....................................................................... 22 ADC Internal Channels ............................................................. 23 ADC Support Circuits ............................................................... 24 Register Details: Analog Comparator ...................................... 32 IDACs (ADuCM320i Only) .......................................................... 33 IDAC Features ............................................................................ 33 IDAC Block Diagram................................................................. 33 IDAC Overview .......................................................................... 33 Register Summary: IDAC ......................................................... 35 Register Details: IDAC............................................................... 35 VDACs ............................................................................................. 38 VDAC Features ........................................................................... 38 VDAC Block Diagram ............................................................... 38 VDAC Overview ........................................................................ 38 VDAC Operation ....................................................................... 38 Register Summary: VDAC ........................................................ 39 Register Details: VDAC ............................................................. 39 System Exceptions and Peripheral Interrupts............................. 45 Cortex-M3 and Fault Management ......................................... 45 External Interrupt Configuration ............................................ 48 Register Summary: External Interrupts .................................. 48 Register Details: External Interrupts ....................................... 48 Low Voltage Analog Die Interrupt Configuration................. 51 Register Summary: Low Voltage Die Interrupts .................... 51 Register Details: Low Voltage Die Interrupts ......................... 52 Reset ................................................................................................. 53 Reset Features ............................................................................. 53 Reset Operation .......................................................................... 53 Register Summary: Reset .......................................................... 54 Register Details: Reset ............................................................... 54 Direct Memory Access (DMA) Controller ................................. 55 DMA Features ............................................................................. 55 DMA Overview .......................................................................... 55 DMA Operation ......................................................................... 55 Rev. A | Page 2 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DMA Interrupts ..........................................................................56 SPI Transfer Initiation ..............................................................119 DMA Priority ...............................................................................56 SPI Interrupts ............................................................................121 Channel Control Data Structure ...............................................56 SPI Wire-OR’ed Mode (WOM) ...............................................122 Control Data Configuration ......................................................57 SPI CSERR Condition ..............................................................122 DMA Transfer Types (CHNL_CFG[2:0])................................58 SPI DMA ....................................................................................122 Address Calculation ....................................................................60 SPI and Power-Down Modes ..................................................123 Aborting DMA Transfers ...........................................................60 Register Summary: SPI0 ..........................................................124 Register Summary: DMA ...........................................................61 Register Details: SPI0................................................................124 Register Details: DMA ................................................................61 Register Summary: SPI1 ..........................................................128 Flash Controller ...............................................................................67 Register Details: SPI1................................................................128 Flash Controller Features ...........................................................67 UART Serial Interface ...................................................................132 Flash Controller Overview.........................................................67 UART Features ..........................................................................132 Flash Controller Operation........................................................67 UART Overview ........................................................................132 Flash Memory Operation ...........................................................69 UART Operation .......................................................................132 Register Summary: Flash Controller ........................................75 Register Summary: UART .......................................................136 Register Details: Flash Controller .............................................76 Register Details: UART ............................................................136 Silicon Identification .......................................................................84 Programmable Logic Array (PLA) .............................................141 Silicon Identification Memory Mapped Registers ..................84 PLA Features..............................................................................141 Digital Die ID Register ...............................................................84 PLA Overview ...........................................................................141 Low Voltage Die ID Register .....................................................84 PLA Operation ..........................................................................142 Digital Inputs/Outputs ...................................................................85 Register Summary: PLA ...........................................................145 Digital Inputs/Outputs Features................................................85 Register Details: PLA ................................................................145 Digital Inputs/Outputs Block Diagram ....................................85 General-Purpose Timers ..............................................................149 Digital Inputs/Outputs Overview .............................................85 General-Purpose Timers Features ..........................................149 Digital Inputs/Outputs Operation ............................................85 General-Purpose Timers Block Diagram ..............................149 Digital Port Multiplex .................................................................88 General-Purpose Timers Overview .......................................149 Register Summary: Digital Input/Output ................................90 General-Purpose Timer Operations ......................................150 Register Details: Digital Input/Output .....................................91 Register Summary: General-Purpose Timer 0 .....................152 I C Serial Interface ..........................................................................95 Register Details: General-Purpose Timer 0 ..........................152 I2C Features ..................................................................................95 Register Summary: General-Purpose Timer 1 .....................154 I2C Overview................................................................................95 Register Details: General-Purpose Timer 1 ..........................154 I2C Operation...............................................................................95 Register Summary: General-Purpose Timer 2 .....................156 I2C Operating Modes ..................................................................97 Register Details: General-Purpose Timer 2 ..........................156 Register Summary: I2C0 .......................................................... 100 Watchdog Timer............................................................................158 Register Details: I C0 ............................................................... 100 Watchdog Timer Features ........................................................158 Register Summary: I C1 .......................................................... 109 Watchdog Timer Block Diagram ............................................158 Register Details: I C1 ............................................................... 109 Watchdog Timer Overview .....................................................158 Serial Peripheral Interfaces ......................................................... 118 Watchdog Timer Operation ....................................................158 SPI Features ............................................................................... 118 Register Summary: Watchdog Timer .....................................159 SPI Overview ............................................................................ 118 Register Details: Watchdog Timer ..........................................159 SPI Operation ........................................................................... 118 Wake-Up Timer .............................................................................161 2 2 2 2 Rev. A | Page 3 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Wake-Up Timer Features ........................................................ 161 Management Data Input/Output (MDIO)................................ 176 Wake-Up Timer Block Diagram............................................. 161 MDIO Features ......................................................................... 176 Wake-Up Timer Overview ...................................................... 161 MDIO Overview....................................................................... 176 Wake-Up Timer Operation ..................................................... 161 MDIO Operation...................................................................... 176 Register Summary: Wake-Up Timer ..................................... 164 Register Summary: MDIO Interface (MDIO)...................... 178 Register Details: Wake-Up Timer .......................................... 164 Register Details: MDIO ........................................................... 178 Pulse Width Modulator (PWM)................................................. 168 Downloader ................................................................................... 181 PWM Features .......................................................................... 168 I2C Downloader (ADuCM320i/ADuCM322i Only)........... 181 PWM Overview ........................................................................ 168 MDIO Downloader (ADuCM322 Only) .............................. 181 PWM Operation ....................................................................... 168 Hardware Design Considerations .............................................. 186 PWM Interrupt Generation .................................................... 171 Typical System Configuration ................................................ 186 Register Summary: PWM ....................................................... 172 Serial Wire Debug Interface .................................................... 190 Register Details: PWM ............................................................ 172 REVISION HISTORY 2/16—Rev. 0 to Rev. A Changed ADuCM320i to ADuCM320i/ADuCM322/ADuCM322i ................... Throughout Changed CS to CS0/CS1 ............................................... Throughout Added Figure 2; Renumbered Sequentially .................................. 1 Changes to Advanced Interrupt Handling Section .................... 17 Changes to Table 11 ........................................................................ 26 Changes to Table 14 ........................................................................ 28 Changes to Table 20 ........................................................................ 31 Deleted Note 1, Table 64; Renumbered Sequentially ................. 53 Changes to Table 83 ........................................................................ 63 Changes to Protection, Integrity Section..................................... 67 Added Error Checking and Correcting (ECC) Error Handling Section, ECC Error During Reading Section, and ECC Error During Execution of Sign Command Section ............................ 71 Changes to Table 94 ........................................................................ 75 Changes to Table 95 ........................................................................ 76 Added ECC Enable/Disable, Error Response Register Section and Table 111................................................................................... 81 Added Flash 0 Error Address Register Section, Table 112, Flash 1 ECC Error Address Register Section, and Table 113 .... 82 Changes to Figure 18 and Figure 19 ............................................. 86 Changes to Table 120...................................................................... 88 Changes to Table 145.................................................................... 105 Changes to Table 167 ................................................................... 114 Changes to Table 183 ................................................................... 125 Changes to Table 191 ................................................................... 129 Changes to Table 205 ................................................................... 140 Changes to Table 211 ................................................................... 145 Added MDIO Interrupt Power Up Register Write Sequence Section............................................................................................ 178 Added I2C Downloader (ADuCM320i/ADuCM322i Only) Section, MDIO Downloader (ADuCM322 Only) Section, and Figure 39 ........................................................................................ 181 Added Flash Block Partitioning Section, Program Image Section, Debug Mode Section, and Choosing the Active Block Section............................................................................................ 182 Added Trial Run Mode Section, Normal Mode Section, Typical Sequence Section, and Table 301 ................................................ 183 Added Table 302 ........................................................................... 184 Added to Figure 40 ....................................................................... 185 Changes to Typical System Configurations Section ................ 186 Changes to Figure 41.................................................................... 187 Added Figure 42 ........................................................................... 188 Added Figure 43 ........................................................................... 189 8/15—Revision 0: Initial Version Rev. A | Page 4 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 USING THE ADUCM320i/ADUCM322/ADUCM322i REFERENCE MANUAL NUMBER NOTATIONS Table 1. Number Notations Notation Bit N V[x:y] 0xNN 0bNN NN Description Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0. Bit field representation covering Bit x to Bit y of a value or a field (V). Hexadecimal (Base 16) numbers are preceded by the prefix 0x. Binary (Base 2) numbers are preceded by the prefix 0b. Decimal (Base 10) numbers are represented using no additional prefixes or suffixes. REGISTER ACCESS CONVENTIONS Table 2. Register Access Conventions Mode RW RC R W Description Memory location has read and write access. Memory location is cleared after reading it. Memory location is read access only. A read always returns 0, unless otherwise specified. Memory location is write access only. Memory mapped register (MMR) bits that are not documented are reserved. When writing to MMRs with reserved bits, the reserved bits must be written with the value in the reset column of the relevant MMR description unless otherwise noted. Rev. A | Page 5 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual INTRODUCTION TO THE ADUCM320i/ADUCM322/ADUCM322i The ADuCM320i/ADuCM322/ADuCM322i are fully integrated, single-package devices that incorporate high performance analog peripherals together with digital peripherals controlled by an 80 MHz ARM® Cortex™-M3 processor and integral flash for code and data. The analog-to-digital converter (ADC) on the 14-bit ADuCM320i and the 12-bit ADuCM322/ADuCM322i provide 1 MSPS data acquisition on up to 16 input pins that can be programmed for single-ended or differential operation. Additionally, chip temperature and supply voltages can be measured. The ADC input voltage is 0 V to VREF. A sequencer is provided that allows a user selected set of ADC channels to be measured in sequence without software involvement during the sequence. The sequence can optionally repeat automatically at a userselectable rate. Up to eight voltage digital-to-analog converters (VDACs) are provided with output ranges programmable to one of two voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. For the ADuCM320i only, four current output DAC (IDAC) sources are provided. The output currents are programmable with a range from 0 mA to 150 mA. A low drift, band gap reference and a voltage comparator complete the analog input peripheral set. The microcontroller core is a low power ARM Cortex-M3 processor, a 32-bit RISC machine that offers up to 100 MIPS peak performance. Also integrated on chip are two 128 kB Flash/EE memory and 32 kB of SRAM. The flash comprises two separate 128 kB blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block. The ADuCM320i/ADuCM322/ADuCM322i operate from an on-chip oscillator or a 16 MHz external crystal and a phase-locked loop (PLL) at 80 MHz. This clock can optionally be divided down to reduce current consumption. Additional low power modes can be set via software. In the normal operating mode, the ADuCM320i/ADuCM322/ADuCM322i digital core consumes approximately 300 µA/MHz. The ADuCM320i/ADuCM322/ADuCM322i integrate a range of on-chip peripherals that can be configured via software control as required in the application. These peripherals include one universal asynchronous transmitter (UART), two I2Cs, two serial peripheral interface (SPI) serial input/output communication controllers, general-purpose input/output (GPIO) pins, 32-element programmable logic array (PLA), three general-purpose timers, one wake-up timer (WUT), and one system watchdog timer (WDT). In addition, 16-bit pulse-width modulators (PWMs) with seven output signals are provided. The ADuCM320i/ADuCM322/ADuCM322i include a management data input/output (MDIO) interface capable of operating up to 4 MHz. The capability to simultaneously execute from one flash block and write or erase the other flash block makes the ADuCM320i/ ADuCM322/ADuCM322i ideal for 40 G/100 G optical applications. User programming is eased by receiving interrupts after physical address (PHYADR), device address (DEVADD), and end of frame and by having PHYADR and DEVADD hardware comparators. GPIO pins on the device power up in input mode. In output mode, the software can choose between open-drain mode and push-pull mode. The outputs can drive at least 4 mA. The pull-ups can be enabled and disabled in the software. In GPIO mode, the inputs can always be enabled to monitor the pins. The GPIO pins can also be programmed to handle digital or analog peripheral signals, in which case, the pin characteristics are matched to the specific requirement. A large support ecosystem is available for the ARM Cortex-M3 processor to ease product development of the ADuCM320i/ADuCM322/ ADuCM322i. Access is via the ARM serial wire debug port. On-chip factory firmware supports in-circuit serial download via I2C (ADuCM320i/ADuCM322i) or MDIO (ADuCM322). These features are incorporated in a low cost, QuickStart™ development system supporting this precision analog microcontroller family. Rev. A | Page 6 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 MAIN FEATURES OF THE ADUCM320i/ADUCM322/ADUCM322i ADC • • Multichannel, 14-bit (ADuCM320i)/12-bit (ADuCM322/ADuCM322i), 1 MSPS successive approximation register (SAR) ADC Low drift, on-chip voltage reference DACs • • • Eight voltage output DACs: VDACs are 12-bit monotonic Four current output DACs: IDACs are 12-bit monotonic (ADuCM320i only) Low drift, on-chip 2.5 V voltage reference source: two buffered reference outputs Communication • • • • • UART: industry standard, 16450 UART peripheral and support for direct memory access (DMA) Two I2Cs: 2-byte transmit (Tx) and receive (Rx) FIFOs for the master and slave, and support for DMA Two SPIs: master or slave mode with separate 4-byte Rx and Tx FIFOs, and Rx and Tx DMA channels 16-bit PWM with seven output channels Multiple GPIO pins Processing • • • • • ARM Cortex-M3 processor, operating from an internal 80 MHz system clock Two 128 kB Flash/EE memory, 32 kB SRAM In-circuit programming and debug via serial wire In-circuit programming via I2C downloader (ADuCM320i/ADuCM322i only) In-circuit programming via MDIO downloader (ADuCM322 only) On-Chip Peripherals • • • • Three general-purpose timers Wake-up timer Watchdog timer 32-element PLA Package and Temperature Range • 6 mm × 6 mm, 96-ball BGA package, −40°C to +85°C (ADuCM320i only) and −40°C to +105°C (ADuCM322/ADuCM322i only) Tools • • Low cost development system Third-party compiler and emulator tool support Applications • • • • Optical networking: 10 G, 40 G, and 100 G modules Industrial control and automation systems Smart sensors, precision instrumentation Base station systems MEMORY ORGANIZATION The ADuCM320i/ADuCM322/ADuCM322i memory organization is described in this section. Features • • • • Cortex-M3 memory system features include predefined memory map, support for bit band operation for atomic operations, and unaligned data access. ADuCM320i/ADuCM322/ADuCM322i on-chip peripherals are accessed via memory mapped registers, situated in the bit band region. User memory sizes options: 32 kB SRAM and two 128 kB Flash/EE memory. On-chip kernel for manufacturer data and in-circuit download. Rev. A | Page 7 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual 0xFFFF FFFF VENDOR SPECIFIC 0xE010 0000 0xE00F FFFF PRIVATE PERIPHERAL BUS—EXTERNAL 0xE004 0000 0xE003 FFFF PRIVATE PERIPHERAL BUS—INTERNAL 0xE000 0000 0xE000 EF00 ADuCM320i/ADuCM322/ADuCM322i MMRs 0xE000 E000 0xDFFF FFFF EXTERNAL DEVICE 1GB (NOT AVAILABLE IN ADuCM320i) 0xA000 0000 0x9FFF FFFF EXTERNAL RAM 1GB (NOT AVAILABLE IN ADuCM320i) 0x6000 0000 0x5FFF FFFF PERIPHERAL 0.5GB 0x4000 0000 0x400A FFFF ADuCM320i/ADuCM322/ADuCM322i MMRs 0x4000 0000 0x3FFF FFFF SRAM 0.5GB 0x2000 0000 0x2000 7FFF ADuCM320i/ADuCM322/ADuCM322i 32kB SRAM 0x2000 0000 0x1FFF FFFF CODE 0.5GB 0x0004 0FFF 0x0000 0000 ADuCM320i/ADuCM322/ADuCM322i KERNEL SPACE 0x0004 0000 0x0000 0000 Figure 3. Cortex-M3 Memory Map Diagram Rev. A | Page 8 of 190 13437-002 0x0003 FFFF ADuCM320i/ADuCM322/ADuCM322i 256kB FLASH/EE MEMORY ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 CLOCKING ARCHITECTURE CLOCKING ARCHITECTURE FEATURES The ADuCM320i/ADuCM322/ADuCM322i integrates two on-chip oscillators and circuitry for an external crystal and external clock source: • • • • LFOSC is a 32 kHz low power internal oscillator that is used in low power modes. HFOSC is a 16 MHz internal oscillator that is used in active mode, which is the default input to the PLL. HFXTAL is a 16 MHz external crystal oscillator. External clock input (ECLKIN) via GPIO pin. CLOCKING ARCHITECTURE BLOCK DIAGRAM ÷4 0 HFXTAL 16MHz OSC ACLK (TO LOW VOLTAGE DIE, ADC) 80MHz SPLL 1 CLKCON0[11] CLKCON5[3] I2C0 CLKCON5[4] CDPCLK (CLKCON1[10:8]) I2C1 CLKCON5[5] 01 UART PCLK UCLK CLKCON5[6] HFOSC 16MHz OSC 00 ECLKIN P1.0 11 CDD2DCLK (CLKCON1[11]) D2D CLKCON5[0] SPI0 CLKCON5[1] CLKCON0[1:0] SPI1 CDHCLK (CLKCON1[2:0]) HCLK CORE WATCHDOG TIMER LFOSC (INTERNAL) PWM FLASH PCLK 01 11 00 WAKE-UP TIMER T4CON[9:10] PCLK HCLK 00 01 11 10 TIMER0CLK T0CON[5:6] PCLK HCLK 00 01 11 10 TIMER1CLK T1CON[5:6] 00 01 11 10 TIMER2CLK 13437-003 PCLK HCLK T2CON[5:6] Figure 4. Clocking Architecture Block Diagram Rev. A | Page 9 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual CLOCKING ARCHITECTURE OVERVIEW The system clock, UCLK, can be selected from a 16 MHz oscillator or from an 80 MHz PLL output (default). An external clock on P1.0 can also be used for test purposes. Internally, the system clock is divided into separate clocks: • • • • UCLK system clock HCLK for the flash, SRAM, and DMA PCLK for most peripherals ACLK for the analog section of the chip; this is based on UCLK/4 and goes to the low voltage analog die All ADC performance details are based on a 20 MHz ACLK. Performance at other clock speeds is not guaranteed. REGISTER SUMMARY: CLOCK ARCHITECTURE Table 3. Clocking Register Summary Address 0x40028000 0x40028004 0x40028014 0x40028018 Name CLKCON0 CLKCON1 CLKCON5 CLKSTAT0 Description Miscellaneous clock settings register Clock dividers register User clock gating control register Clocking status Reset 0x0041 0x0200 0x0040 0x0000 Access RW RW RW RW CLOCKING ARCHITECTURE OPERATION At power-up, the processor executes at 80 MHz, sourced from the 80 MHz PLL output. The clock source for the 80 MHz PLL is the internal 16 MHz oscillator by default. User code can select the clock source for the system clock and can divide the clock by a factor of 1 to 128, where the clock divider bits are controlled by CLKCON1[2:0], which allows slower code execution and reduced power consumption. When switching clock sources, a stable clock must always be connected to UCLK; otherwise, the system may halt before connecting the new clock. If the clock source for the 80 MHz SPLL needs to be changed from the internal 16 MHz oscillator to the external HFXTAL, use the following procedure: 1. 2. 3. 4. 5. Check that HFXTAL is stable by reading CLKSTAT0[14:12]. Change the system clock to the internal 16 MHz oscillator using CLKCON0[1:0]. Switch the input to the SPLL using CLKCON0[11]. Wait until the SPLL has locked by monitoring CLKSTAT0[2:0]. Change the system clock back to the SPLL clock. REGISTER DETAILS: CLOCK ARCHITECTURE Miscellaneous Clock Settings Register Address: 0x40028000, Reset: 0x0041, Name: CLKCON0 Table 4. Bit Descriptions for CLKCON0 Bit(s) 15 Bit Name HFXTALIE 14 13 RESERVED SPLLIE 12 11 RESERVED PLLMUX [10:8] RESERVED Description High frequency crystal interrupt enable. 0: an interrupt to the core does not generate on a HFXTALOK or HFXTALNOK. 1: an interrupt to the core generates on a HFXTALOK or HFXTALNOK. Reserved. SPLL interrupt enable. 0: SPLL interrupt does not generate. 1: SPLL interrupt generates. Reserved. PLL source selection. 0: internal oscillator is selected (HFOSC). 1: external oscillator is selected (HFXTAL). Reserved. Rev. A | Page 10 of 190 Reset 0x0 Access RW 0x0 0x0 RW RW 0x0 0x0 R RW 0x0 RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) [7:4] Bit Name CLKOUT [3:2] [1:0] RESERVED CLKMUX Description GPIO clock out selection. 0000: UCLK. 0001: LFOSC (32 kHz). 0010: HFOSC(16 MHz). 0100: core clock. 0101: PCLK. 1011: General-Purpose Timer 0 clock. 1100: wake-up timer clock. 1110: HFXTAL. All other combinations are reserved. Reserved. Clock selection. 00: high frequency internal oscillator (HFOSC). 01: SPLL is selected (80 MHz). 10: reserved. 11: external GPIO port is selected (ECLKIN). UG-868 Reset 0x4 Access RW 0x0 0x1 R RW Reset 0x0 0x0 Access R R 0x2 RW 0x0 0x0 R RW Clock Dividers Register Address: 0x40028004, Reset: 0x0200, Name: CLKCON1 Table 5. Bit Descriptions for CLKCON1 Bit(s) [15:12] 11 Bit Name RESERVED CDD2DCLK [10:8] CDPCLK [7:3] [2:0] RESERVED CDHCLK Description Reserved. D2DCLK divide bits. 0: D2D_CLK frequency is HCLK frequency. 1: D2D_CLK frequency is half of HCLK frequency. PCLK divide bits. PCLK divide bits. 000: Reserved. 001: Reserved. 010: DIV4. Divide by 4 (PCLK is quarter the frequency of root clock, 20 MHz). All ADC specifications based on this setting. Using any other setting may affect ADC performance. 011: DIV8. Divide by 8. 100: DIV16. Divide by 16. 101: DIV32. Divide by 32. 110: DIV64. Divide by 64. 111: DIV128. Divide by 128. Reserved. Always returns 0 when read. HCLK divide bits. 000: DIV1. Divide by 1 (HCLK is equal to root clock). 001: DIV2. Divide by 2 (HCLK is half the frequency of root clock). 010: DIV4. Divide by 4 (HCLK is quarter the frequency of root clock). 011: DIV8. Divide by 8. 100: DIV16. Divide by 16. 101: DIV32. Divide by 32. 110: DIV64. Divide by 64. 111: DIV128. Divide by 128. Rev. A | Page 11 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual User Clock Gating Control Register Address: 0x40028014, Reset: 0x0040, Name: CLKCON5 The user clock gating control register (CLKCON5) controls the gates of the peripheral UCLKs. Table 6. Bit Descriptions for CLKCON5 Bit(s) [15:7] 6 5 Bit Name RESERVED RESERVED UCLKUARTOFF 4 UCLKI2C1OFF 3 UCLKI2C0OFF 2 1 RESERVED UCLKSPI1OFF 0 UCLKSPI0OFF Description Reserved. Always returns 0 when read. Always set to 1. Do not write 0 to this bit. UART clock user control. This bit disables the UCLK_UART clock. It controls the gate on UCLK_UART in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the UCLK_UART is always off, and this bit has no effect. 0: clock on. 1: clock off. I2C1 clock user control. This bit disables the PCLK_I2C1 clock. It controls the gate on PCLK_I2C1 in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the I2C1 PCLK is always off, and this bit has no effect. 0: clock on. 1: clock off. I2C0 clock user control. This bit disables the PCLK_I2C0 clock. It controls the gate on PCLK_I2C0 in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the PCLK_I2C0 is always off, and this bit has no effect. 0: clock on. 1: clock off. Reserved. SPI1 clock user control. This bit disables the UCLK_SPI1 clock. It controls the gate on UCLK_SPI1 in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the UCLK_SPI1 is always off, and this bit has no effect. 0: clock on. 1: clock off. SPI0 clock user control. This bit disables the UCLK_SPI0 clock. It controls the gate on UCLK_SPI0 in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the UCLK_SPI0 is always off, and this bit has no effect. 0: clock on. 1: clock off. Rev. A | Page 12 of 190 Reset 0x0 0x1 0x0 Access R RW RW 0x0 RW 0x0 RW 0x0 0x0 R RW 0x0 RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Clocking Status Register Address: 0x40028018, Reset: 0x0000, Name: CLKSTAT0 The clock status register monitors PLL and oscillator status. Table 7. Bit Descriptions for CLKSTAT0 Bit(s) 15 14 Bit Name RESERVED HFXTALNOK 13 HFXTALOK 12 HFXTALSTATUS [11:3] 2 RESERVED SPLLUNLOCK 1 SPLLLOCK 0 SPLLSTATUS Description Reserved. Always returns 0 when read. HF crystal not stable. This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1 to this location to clear it. 0: HF crystal stable signal is not deasserted. 1: HF crystal stable signal is deasserted. HF crystal stable. This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1 to this location to clear it. 0: HF crystal stable signal is not asserted. 1: HF crystal stable signal is asserted. HF crystal status. 0: HF crystal is not stable or not enabled. 1: HF crystal is stable. Reserved. System PLL unlock. This bit is sticky. SPLLUNLOCK is set when the PLL loses its lock. SPLLUNLOCK is used as the interrupt source to signal the core that a lock was lost. Writing a 1 to this bit clears it. SPLLUNLOCK does not set again unless the system PLL gains a lock and subsequently loses it again. 0: no loss of PLL lock is detected. 1: a PLL loss of lock is detected. System PLL lock. This bit is sticky. SPLLLOCK is set when the PLL locks. SPLLLOCK is used as the interrupt source to signal the core that a lock was detected. Writing a 1 to this bit clears it. SPLLLOCK does not set again unless the system PLL loses lock and subsequently locks again. 0: no PLL lock event is detected. 1: a PLL lock event is detected. System PLL status. Indicates the current status of the PLL. Initially, the system PLL is unlocked. After a stabilization period, the PLL locks and is ready for use as the system clock source. This is a read only bit. A write has no effect. 0: the PLL is not locked or properly configured. The PLL is not ready for use as the system clock source. 1: the PLL is locked and is ready for use as the system clock source. Rev. A | Page 13 of 190 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 R 0x0 0x0 R RW 0x0 RW 0x0 R UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual POWER MANAGEMENT UNIT POWER MANAGEMENT UNIT FEATURES The power management unit (PMU) controls the different power modes of the ADuCM320i/ADuCM322/ADuCM322i. Four power modes are available: • • • • Active CORE_SLEEP SYS_SLEEP Hibernate POWER MANAGEMENT UNIT OVERVIEW The Cortex-M3 sleep modes are linked to the PMU modes and are described in this section. The PMU is in the always-on section. Each mode gives a power reduction benefit with a corresponding reduction in functionality. POWER MANAGEMENT UNIT OPERATION The debug tools can prevent the Cortex-M3 from fully entering its power saving modes by setting bits in the debug logic. Only a power-on reset resets the debug logic. Therefore, the device must be power cycled after using serial wire debug with application code containing the wait for interrupt (WFI) instruction. Power Mode: Active Mode, Mode 0 The system is fully active. Memories and all user enabled peripherals are clocked, and the Cortex-M3 processor executes instructions. Note that the Cortex-M3 processor manages its internal clocks and can be in a partial clock gated state. This clock gating affects only the internal Cortex-M3 processing core. Automatic clock gating is used on all blocks. User code can use a WFI command to put the Cortex-M3 processor into sleep mode; it is independent of the power mode settings of the PMU. When the ADuCM320i/ADuCM322/ADuCM322i wakes up from any of the low power modes, the devices return to Mode 0. Power Mode: CORE_SLEEP Mode, Mode 1 In CORE_SLEEP mode, the system gates the clock to the Cortex-M3 core after the Cortex-M3 enters sleep mode. The rest of the system remains active. No instructions can be executed; however, DMA transfers can continue to occur between peripherals and memories. The Cortex-M3 processor FCLK is active, and the device wakes up using the nested vectored interrupt controller (NVIC). Power Mode: SYS_SLEEP Mode, Mode 2 In SYS_SLEEP mode, the system gates the system bus clock (HCLK) and the peripheral bus clock (PCLK) after the Cortex-M3 enters sleep mode. The gating of these clocks stops all advanced high performance bus (AHB) attached masters/slaves and all peripherals attached to the advanced peripheral bus (APB). Peripheral clocks are all off, and they are no longer user programmable. The NVIC clock (FCLK) remains active, and the NVIC processes wake-up events. Power Mode: Hibernate Mode, Mode 3 In hibernate mode, the system disables power to all combinational logic and places sequential logic in retain mode. Because FCLK is stopped, the number of sources capable of waking up the system is restricted. The sources listed in Table 54 are the only sources able to wake up the system. Power Mode 1 to Power Mode 3 must be entered when the processor is not in an interrupt handler. If Power Mode 1 to Power Mode 3 are entered when the processor is in an interrupt handler, the power-down mode can only be exited by a reset or a higher priority interrupt source. Rev. A | Page 14 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual CODE EXAMPLES Code Example to Enter Power Saving Modes SCB->SCR = 0x04; pADI_PWRCTL->PWRKEY = 0x4859; pADI_PWRCTL->PWRKEY = 0xF27B; pADI_PWRCTL->PWRMOD = 0x3; __DSB(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __WFI(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); // sleep deep mode // key1 // key2 // Hibernate Code Example to Achieve Further Power Savings pADI_ADC->ADCCON = 0; pADI_IDAC0->IDACCON = 0x1; pADI_IDAC1->IDACCON = 0x1; pADI_IDAC2->IDACCON = 0x1; pADI_IDAC3->IDACCON = 0x1; pADI_VDAC0->DACCON = 0x100; pADI_VDAC1->DACCON = 0x100; pADI_VDAC2->DACCON = 0x100; pADI_VDAC3->DACCON = 0x100; pADI_VDAC4->DACCON = 0x100; pADI_VDAC5->DACCON = 0x100; pADI_VDAC6->DACCON = 0x100; pADI_VDAC7->DACCON = 0x100; pADI_CLKCTL->CLKCON0 &= 0xFFFC; pADI_CLKCTL->CLKCON1 = 0x505; pADI_CLKCTL->CLKCON5 = 0x7B; // // // // // // // // // // // // // // // // Power off the ADC Turn off IDAC0 Turn off IDAC1 Turn off IDAC2 Turn off IDAC3 Turn off VDAC0 Turn off VDAC1 Turn off VDAC2 Turn off VDAC3 Turn off VDAC4 Turn off VDAC5 Turn off VDAC6 Turn off VDAC7 Switch to 16MHz clock Slow down system clocks Turn off clocks to peripherals Rev. A | Page 15 of 190 UG-868 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: POWER MANAGEMENT UNIT Table 8. Power Management Register Summary Address 0x40002400 0x40002404 Name PWRMOD PWRKEY Description Power modes Key protection for PWRMOD Reset 0x0000 0x0000 Access RW RW Reset 0x0 0x0 Access R RW Reset 0x0 Access RW REGISTER DETAILS: POWER MANAGEMENT UNIT Power Modes Register Address: 0x40002400, Reset: 0x0000, Name: PWRMOD Table 9. Bit Descriptions for PWRMOD Bit(s) [14:2] [1:0] Bit Name RESERVED PWRMOD Description Reserved. These bits must write 0 by user code. Power modes control bits. When read, these bits contain the last power mode value entered by user code. Note that, to place the Cortex in sleep deep mode for hibernate, the Cortex-M3 system control register (Address 0xE000ED10) must be configured to 0x4 or 0x06. 00: active mode 01: CORE_SLEEP mode 10: SYS_SLEEP mode 11: hibernate mode Key Protection for PWRMOD Register Address: 0x40002404, Reset: 0x0000, Name: PWRKEY Table 10. Bit Descriptions for PWRKEY Bit(s) [15:0] Bit Name PWRKEY Description Power control key register. The PWRMOD register is key protected. Two writes to the key are necessary to change the value in the PWRMOD register: first 0x4859, then 0xF27B. Then, write to the PWRMOD register. A write to any other register before writing to PWRMOD returns the protection to the lock state. Rev. A | Page 16 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 ARM CORTEX-M3 PROCESSOR ARM CORTEX-M3 PROCESSOR FEATURES High Performance • • • • 1.25 DMIPS/MHz. Many instructions, including multiply, are single cycle. Separate data and instruction buses allow simultaneous data and instruction accesses to be performed. Optimized for single cycle flash usage. Low Power • • • Low standby current. Core implemented using advanced clock gating so that only the actively used logic consumes dynamic power. Power saving mode support (sleep and deep sleep modes). The design has separate clocks to allow unused parts of the processor to be stopped. Advanced Interrupt Handling • • • • • The nested vectored interrupt controller (NVIC) supports up to 240 interrupts. The ADuCM320i/ADuCM322/ADuCM322i supports 47 of these interrupts. The vectored interrupt feature greatly reduces interrupt latency because there is no need for software to determine which interrupt handler to serve. In addition, there is no need to have software to set up nested interrupt support. The ARM Cortex-M3 processor automatically pushes registers onto the stack at the entry interrupt and retrieves them at the exit interrupt. The pushing and retrieving helps reduce interrupt handling latency and allow interrupt handlers to be normal C functions. Dynamic priority control for each interrupt. Latency reduction using late arrival interrupt acceptance and tail-chain interrupt entry. Immediate execution of a nonmaskable interrupt request for safety critical applications. System Features • • Support for bit band operation and unaligned data access. Advanced fault handling features include various exception types and fault status registers. Debug Support • • • Serial wire debug interfaces (SW-DP). Flash patch and breakpoint (FPB) unit for implementing breakpoints. Limited to two hardware breakpoints. Data watchpoint and trigger (DWT) unit for implementing watchpoints trigger resources and system profiling. Limited to one hardware watchpoint. The DWT does not support data matching for watchpoint generation because it only has one comparator. ARM CORTEX-M3 PROCESSOR OVERVIEW The ADuCM320i/ADuCM322/ADuCM322i contain an embedded ARM Cortex-M3 processor, Revision r2p1. The ARM Cortex-M3 processor provides a high performance, low cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption while delivering outstanding computational performance and exceptional system response to interrupts. ARM CORTEX-M3 PROCESSOR OPERATION Several ARM Cortex-M3 processor components are flexible in their implementation. This section details the actual implementation of these components in the ADuCM320i/ADuCM322/ADuCM322i. Serial Wire Debug (SW/JTAG-DP) The ADuCM320i/ADuCM322/ADuCM322i only support the serial wire interface via the SWCLK and SWDIO pins. It does not support the 5-wire JTAG interface. ROM Table The ADuCM320i/ADuCM322/ADuCM322i implement the default ROM table. Rev. A | Page 17 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Nested Vectored Interrupt Controller Interrupts (NVICs) The ARM Cortex-M3 processor includes a NVIC, which offers several features: • • • • Nested interrupt support Vectored interrupt support Dynamic priority changes support Interrupt masking In addition, the NVIC has a nonmaskable interrupt (NMI) input. The NVIC is implemented on the ADuCM320i/ADuCM322/ADuCM322i, and more details are available in the System Exceptions and Peripheral Interrupts section. Wake-Up Interrupt Controller (WIC) The ADuCM320i/ADuCM322/ADuCM322i have a modified WIC that provides the lowest possible power-down current. More details on this feature are available in the Power Management Unit section. It is not recommended to enter power saving mode while servicing an interrupt. However, if the device does enter power saving mode while servicing an interrupt, it can only wake up by a higher priority interrupt source. µDMA The ADuCM320i/ADuCM322/ADuCM322i implement the ARM µDMA. More details are available in the Direct Memory Access (DMA) Controller section. ARM CORTEX-M3 PROCESSOR RELATED DOCUMENTS • • • • • • Cortex-M3 Revision r2p1 Technical Reference Manual (DDI 0337) ARM Processor Cortex-M3 (AT420) and Cortex-M3 with ETM AT425): Errata Notice ARMv7-M Architecture Reference Manual (DDI 0403) ARMv7-M Architecture Reference Manual Errata Markup ARM Debug Interface v5 Architecture Specification (IHI 0031) PrimeCell µDMA Controller (PL230) Technical Reference Manual Revision r0p0 (DDI 0417) Rev. A | Page 18 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 ADC CIRCUIT ADC CIRCUIT FEATURES The ADuCM320i/ADuCM322/ADuCM322i incorporate a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit (ADuCM320i) or 12-bit (ADuCM322/ADuCM322i) accurate. A flexible input multiplexer supports 16 external inputs and 11 internal channels. The internal channels include the following: • • • • • • • A temperature sensor channel. An internal 2.5 V reference. An external reference. Four IDAC channels. These are the voltage at each of the IDAC output pins (ADuCM320i only). PVDD2 supply voltage (ADuCM320i only). IOVDD/2 supply voltage. AVDD/2 supply voltage. For the ADuCM320i only, the input buffer can be selected for any channel to allow very low input current/input leakage specifications on these input channels. A high precision, low drift internal 2.5 V reference source is provided. An external reference can also be connected to the ADC_REFP and ADC_REFN pins. The programmable ADC update rate is from 19.55 kSPS to 1 MSPS. An internal digital comparator is available for the AIN4 channel. An interrupt can be generated if the digital comparator detects an ADC result above/below a user defined threshold. Each channel has its own distinct data register for its conversion result. For example, when AIN0 is selected, the result appears in ADCDAT0; if AIN7 is selected, the result appears in ADCDAT7. For a differential measurement, the result always appears in the data register of the positive channel. ADC CIRCUIT BLOCK DIAGRAM I AIN+ IBUF_BYP[1] CAPACITOR ARRAY CONTROL AIN0 P BUSY PRECHARGE AIN15 INTERNAL CHANNELS CAPACITOR ARRAY COMP CONTROL LOGIC P OUTPUT CODE ADCCHA CNV I IBUF_BYP[0] I = INPUT BUFFER P = PRECHARGE BUFFER Figure 5. ADC Circuit Block Diagram Rev. A | Page 19 of 190 13437-004 AIN– UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ADC CIRCUIT OVERVIEW The ADuCM320i/ADuCM322/ADuCM322i incorporates a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit (ADuCM320i) or 12-bit (ADuCM322/ADuCM322i) accurate. It can operate from a 2.9 V to 3.6 V supply and is capable of providing a throughput of up to 1 MSPS. This ADC block provides the user with a multichannel multiplexer, input buffer for high impedance input channels (ADuCM320i only), on-chip reference, and SAR ADC. The SAR ADC circuit is implemented on the low voltage analog die. The ARM Cortex-M3 processor interfaces to the ADC via an internal parallel die to die interface. Depending on the input signal configuration, the ADC can operate in one of the following two modes: • • Differential mode measures the difference between two signals. Single-ended mode measures any signal relative to AGND. The converter accepts an analog input range of 0 to VREF when operating in single-ended mode. In fully differential mode, the input signal must be balanced around a common-mode voltage (VCM) in the 0 V to AVDD range and with a maximum amplitude of 2 × VREF. AIN+ AVDD AIN– OUTPUT CODE FS (VREF ) 13437-105 0 –FS (–VREF ) Figure 6. Examples of Balanced Signals for Differential Mode A high precision, low drift, factory-calibrated 2.5 V reference is provided on-chip. An external reference can also be connected to the ADC_REFP and ADC_REFN pins. Single or continuous conversion modes can be initiated in the software. An external pin (alternate function of P2.4) can also generate a repetitive trigger for ADC conversions. ADC CIRCUIT OPERATION The SAR ADC is based on a charge redistribution DAC. The capacitive DAC consists of two identical arrays of 18 binary weighted capacitors that are connected to the two inputs of the comparator. The ADC converts the voltage applied to AIN+ and AIN− in the following three phases: 1. 2. 3. During the precharge phase, the precharge buffers connect the inputs to the capacitor arrays, which charges the capacitors quickly with minimal loading of the external input source. During the acquisition phase, the capacitor arrays are connected directly to the inputs to fully charge the capacitor arrays and eliminate any precharge buffer errors. The timing for the acquisition phase is set by ADCCNVC[25:16]. This value must be set to 500 ns. If the input buffer is not used when measuring AVDD/2, IOVDD/2, or temperature sensor channels, set this value to 1.5 µs. At the end of the acquisition phase, the internal CNV signal goes high and initiates the conversion phase. The conversion begins with the SW+ and SW− switches opening, which disconnects the two capacitor arrays from the analog inputs and connects the analog inputs to the AGND (−VREF) input. The conversion is completed by normal successive approximation. The ADC block operates from an internally generated 20 MHz clock. The ADC conversion rate is set by ADCCNVC[9:0]. Rev. A | Page 20 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 ADC TRANSFER FUNCTION Single-Ended Mode In single-ended mode, the input range is 0 to VREF. The output coding is straight binary with 1 LSB = FS/65,536 or VREF/65,536 = 2.5 V/65,536 = 38.14 µV The data values in ADCDATx are aligned such that the MSB is in ADCDATx[27] and, therefore, the LSB is in ADCDATx[12]. The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, …, FS − 3/2 LSB). The ideal input/output transfer characteristic is shown in Figure 7. ADCDATx[31:12] 0000 1111 1111 1111 1111 0000 1111 1111 1111 1110 OUTPUT CODE 0000 1111 1111 1111 1101 0000 1111 1111 1111 1100 1LSB = VREF 65536 0000 0000 0000 0000 0011 0000 0000 0000 0000 0010 0000 0000 0000 0000 0001 0V 1LSB VOLTAGE INPUT NOTES 1. IN ADCDATx, x IS 0 TO 27, AS SHOWN IN TABLE 10. VREF – 1LSB 13437-013 0000 0000 0000 0000 0000 Figure 7. ADC Transfer Function: Single-Ended Mode Differential Mode The amplitude of the differential signal is the difference between the signals applied to the AIN+ and AIN− pins (that is, AIN+ − AIN−). The maximum amplitude of the differential signal is, therefore, −VREF to +VREF p-p (2 × VREF), regardless of the common mode (CM). The common mode is the average of the two signals (AIN+ + AIN−)/2 and is, therefore, the voltage that the two inputs are centered on. This results in the span of each input being CM ± VREF/2. This voltage must be set up externally, and its range varies with VREF. The voltage at the AIN+ and AIN− pins must be within the allowed input voltage range. The output coding is twos complement in fully differential mode, with 1 LSB = 2 × VREF/65,536 or 2 × 2.5 V/65,536 = 76.29 µV where VREF = 2.5 V. The data values in ADCDATx are aligned such that the MSB is in ADCDATx[27] and, therefore, the LSB is in ADCDATx[13]. The ideal input/output transfer characteristic is shown in Figure 8. Rev. A | Page 21 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ADCDATx[31:12] 0000 0000 1111 1111 1110 0000 0000 1111 1111 1100 1LSB = 2 × VREF 65536 OUTPUT CODE 0000 0000 1111 1111 1010 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 1111 1111 1111 1111 1110 1111 0000 0000 0000 0100 1111 0000 0000 0000 0000 0LSB +VREF – 1LSB –VREF + 1LSB VOLTAGE INPUT (VIN+ – VIN–) NOTES 1. IN ADCDATx, x IS 0 TO 27, AS SHOWN IN TABLE 10. 13437-014 1111 0000 0000 0000 0010 Figure 8. ADC Transfer Function: Differential Mode ADC TYPICAL SETUP SEQUENCE After being configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 16-bit result in the ADC data registers. The following is an example sequence to set up the ADC and generate a single conversion on AIN0 using a single-ended measurement: 1. 2. 3. Configure the device as follows: ADCCON = 0x280; // Power up the ADC, enable reference buffer, idle mode. ADCCHA = 0x1100; // Select AIN0 as the positive ADC input (AIN+) and ADC_REFN as the negative ADC input (AIN−). ADCCNVC = 0xA00C8; // Select 100 kSPS ADC update rate and 500 ns acquisition time. ADCCON | = 0x2; // Enable single conversion. Wait for the low voltage die interrupt iADCRESULT = ADCDAT0; // Read the ADC result. Note that if the ADC is set from continuous conversion mode to idle mode after a full ADC sequence is completed, ADCSEQ[31] must be set to 1 before starting another sequence and reconfiguring the ADC back to continuous conversion mode to ensure that the sequencer restarts with the first selected channel in ADCSEQ. ADC INPUT BUFFER An optional input buffer can be enabled for any ADC input channel on the ADuCM320i only. The control register, IBUFCON, controls the input buffer switches as follows: • • IBUF_BYP (IBUFCON[1:0]) controls the bypass switches on the ADC input buffer. If the input buffer is required on either the positive or negative input, the bypass switch must be turned off. IBUF_PD (IBUFCON[3:2]) powers up or powers down the ADC input buffer. Rev. A | Page 22 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 ADC INTERNAL CHANNELS Temperature Sensor Settings The ADuCM320i/ADuCM322/ADuCM322i provide a voltage output from an on-chip band gap reference that is proportional to the absolute temperature of the low voltage die. This voltage output is routed through the front end of the ADC multiplexer (effectively, an additional ADC channel input), facilitating an internal temperature sensor channel that measures die temperature. The internal temperature sensor is not designed for use as an absolute ambient temperature calculator. Its intended use is as an approximate indicator of the temperature of the ADuCM320i/ADuCM322/ADuCM322i low voltage analog die. An ADC temperature sensor conversion differs from a standard ADC voltage. The ADC performance specifications do not apply to the temperature sensor. When the temperature sensor channel is selected, the ADC update rate must be 80 kSPS. The ADC automatically changes the ADC update rate to 80 kSPS when the temperature sensor, AVDD/2, or IOVDD/2 input channel is selected. If a different ADC sampling rate is required for other channels after the conversion on any of these three channels is completed, the ADCCNVC register must be updated. Note that when the sequencer is enabled and includes any of these three channels, the value in the ADCCNVC register does not change and the ADC sampling rate does not change. The temperature sensor settings are as follows. Enable the temperature sensor on the ADC; set ADCCHA[12:0] = 0x1116. To calculate the die temperature, use the following formula: T − TREF = (VADC − VTREF) × K where: T is the temperature result. TREF is 25°C. VADC is the average ADC result from two consecutive conversions. VTREF is the ADC result in millivolts that corresponds to TREF = 25°C. The user must measure this in their own application because this value varies from device to device. The typical value used for demonstration purposes is 1290 mV. K is the gain of the ADC in temperature sensor mode. The user must determine the gain by performing a two-point temperature calibration because this value varies from device to device. The typical value used for demonstration purposes only is 4.394 mV/°C. This 4.394 mV/°C value corresponds to 1/V TC. Using the default values from the ADuCM320i, the ADuCM322, the ADuCM322i data sheets without any calibration, the equation becomes T − 25°C = (VADC − 1290) × 1/K Therefore, assuming VADC at 25°C = 1290 mV and slope mV/C = 4.394 mV/C, T = ((VADC − 1290)/4.394) + 25 where: VADC is in millivolts. See the latest version of the ADuCM320i, the ADuCM322, the ADuCM322i data sheets for the most up to date figures. For increased accuracy, perform a two-point calibration at a controlled temperature value. The values used in this example for VTREF and K are not guaranteed values. The VTREF and K values vary from device to device; therefore, the user must derive the appropriate values by performing a calibration at ambient temperature. AVDD/2 and IOVDD/2 Supply Voltage Channels These supply voltage channels are measured via internal resistor dividers. Because the resistors used are high impedance and the divided voltage is not buffered, a slower ADC update rate must be used. The ADC automatically changes the ADC update rate to 80 kSPS when the temperature sensor, AVDD/2, or IOVDD/2 input channel is selected. If a different ADC sampling rate is required for other channels after the conversion on any of these three channels is completed, the ADCCNVC register must be updated. Note that when the sequencer is enabled and includes any of these three channels, the value in the ADCCNVC register does not change and the ADC sampling rate does not change. At rates above 80 kSPS, the accuracy is reduced on the ADuCM320i if the input buffer is disabled. Rev. A | Page 23 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ADC SUPPORT CIRCUITS IDAC Channels (ADuCM320i Only) The ADuCM320i allows the voltage on the IDAC output pins to be selected as inputs to the ADC. These channels are useful for determining the power consumed by each IDAC. ADC Digital Comparator A digital comparator is provided to allow an interrupt to be triggered if the ADC data result is above or below a programmable threshold. Only the AIN4 external input channel can be used with the digital comparator. To set up the ADC digital comparator, note the following: • • • • • • ADCCMP[17:2] set a 16-bit ADC threshold value. ADCCMP[1] configures the comparator to be triggered when the ADC result is above or below the threshold value. To enable the ADC comparator interrupt, set INTSEL[2] = 1 to enable the digital comparator to the Low Voltage Die Interrupt 1 signal. Similarly, set INTSEL[10] = 1 to enable the digital comparator interrupt to the Low Voltage Die Interrupt 0 signal. The comparator output is asserted when the value in ADCDAT4[27:12] rises above the value in ADCCMP[17:2] if ADCCMP[1] = 1. If ADCDAT4[27:12] remains above ADCCMP[17:2], no further comparator interrupts occur. The interrupt only occurs when the comparator circuit detects a rise above the threshold. Similarly, if ADCCMP[1] = 0, the comparator output is asserted when the value in ADCDAT4[27:12] falls below the value in ADCCMP[17:2]. If ADCDAT4[27:12] remains below ADCCMP[17:2], no further comparator interrupts occur. The interrupt only occurs when the comparator circuit detects a fall below the threshold value. ADC Channel Sequencer An ADC sequencer is provided to reduce the processor overhead of sampling and reading individual channels. The ADC sequencer allows the user to select the number and order of ADC input channels that the ADC samples and provides a single interrupt source that is asserted when the sequence ends. The sequencer can also be programmed to restart automatically without a delay or with a programmable delay between the end and start of sequences. Some additional details about the sequencer include the following. The sequencer reads the ADCSEQ[0:28] register to determine which channels need to be included and which need to be excluded from the execution sequence. ADCSEQ corresponds to the ADCCHA[4:0] for the list of ADC input channels. For example, to include AIN9, set ADCSEQ[9]. To enable the sequencer as the Low Voltage Die Interrupt 1 source, set INTSEL[1] = 1. To enable the sequencer as the Low Voltage Die Interrupt 0 source, set INTSEL[9] = 1. To start the sequencer, set ADCSEQ[31:30] = 0x3. The ADCSEQC[27:20] register bits set the delay between finishing one sequence of channels and starting another sequence. Normally, single-ended measurements are assumed by the ADC with AGND as the negative reference. However, for Channel 0, Channel 2, Channel 4, and Channel 6, a differential measurement can be selected by configuring the appropriate bits in ADCSEQC[19:0]. For example, ADCSEQC[4:0] selects the negative input when AIN0 is the positive. For single-ended measurements using the sequencer and AIN0, ADCSEQC[4:0] must be set to 0x11 for VREFN_NADC (ADC_REFN pin). On the ADuCM320i, take care when using the sequencer if the input buffer is enabled. The IBUFCON register controls the input buffer. If the input buffer is enabled, all channels sampled in a sequence are sampled with the input buffer enabled. It is recommended to split sequences into the following: • • • Sample unbuffered channels together in one sequence. Sample buffered channels in a separate sequence. If full accuracy results are required for the AVDD/2, IOVDD/2, or temperature channels, take care when measuring with the sequencer. With the input buffer disabled, the acquisition time must be set to 1.5 µs via ADCCONV[25:16] = 0x1E. Alternatively, enable the input buffer. Rev. A | Page 24 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 ADC Direct Memory Access (DMA) The ADC or the ADC sequencer can be selected as the source channel for the DMA controller. This reduces processor overhead by moving ADC results directly into SRAM with a single interrupt asserted when the required number of ADC conversions has been completely logged to memory. When using the ADC sequencer with the DMA controller, it is recommended to use DMA autorequest transfer types rather than basic transfer types. ADC Voltage Reference Selection The ADuCM320i/ADuCM322/ADuCM322i integrate a low drift, 2.5 V ADC reference source. By default, this internal reference is enabled and selected as the reference source for the ADC. When using the internal 2.5 V voltage reference, ensure the following: ADCCON[7] = 1 to power up the internal reference buffer AFEREFC[3] = 0 to select the internal reference as the ADC reference source It is also possible to select an external reference source through the ADC_REFP pin. To select an external voltage source as the ADC reference source, ensure the following: ADCCON[7] = 0 to power down the internal reference buffer AFEREFC[3] = 1 to select the external reference as the ADC reference source The external reference source must be capable of driving the 4.7 μF capacitor on the ADC_REFP pin. If switching from the external to internal reference voltage source, note that there is a power-on time specification given in the ADuCM320i, the ADuCM322, the ADuCM322i data sheets for the ADC reference buffer to fully power up after ADCCON[7] is set to 1. Figure 9 shows the block diagram of how the analog references are provided. 1.2V 2.5V GAIN STAGE AFEREFC[3] AFEREFC[2] BUF_VRFF2.5B DRIVER ADC BUFFER ADC CAPP 2.5V ADC ADCCON[7] VDAC DACxCON[1:0] Figure 9. System Reference Voltage Block Diagram Rev. A | Page 25 of 190 13437-005 AVDD MUX BG AFEREFC[1] MUX AFEREFC[0] UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: ADC CIRCUIT The CPU accesses the ADC circuit over a die to die interface (D2D), which increases the execution times of LDR and STR instructions. The 32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute. The 16-bit MMRs have addresses of 0x40082xxx and take 6 CPU cycles at 80 MHz to execute. Table 11. ADC Circuit Register Summary Address 0x40082174 0x40086000 0x40086004 0x40086008 0x4008600C 0x40086010 0x40086014 0x40086018 0x4008601C 0x40086020 0x40086024 0x40086028 0x4008602C 0x40086030 0x40086034 0x40086038 0x4008603C 0x40086040 0x40086044 0x40086048 0x4008604C 0x40086050 0x40086054 0x40086058 0x4008605C 0x40086060 0x40086064 0x40086068 0x4008606C 0x40086080 0x40086088 0x4008608C 0x40086090 0x40086094 0x40086098 0x4008609C Name ADCCON ADCDAT0 ADCDAT1 ADCDAT2 ADCDAT3 ADCDAT4 ADCDAT5 ADCDAT6 ADCDAT7 ADCDAT8 ADCDAT9 ADCDAT10 ADCDAT11 ADCDAT12 ADCDAT13 ADCDAT14 ADCDAT15 ADCDAT16 ADCDAT17 ADCDAT18 ADCDAT19 ADCDAT20 ADCDAT21 ADCDAT22 ADCDAT23 ADCDAT24 ADCDAT25 ADCDAT26 ADCDAT27 ADCCHA ADCSEQ ADCSEQC RESERVED RESERVED ADCCMP ADCCNVC Description ADC configuration ADC0 data and flags ADC1 data and flags ADC2 data and flags ADC3 data and flags ADC4 data and flags ADC5 data and flags ADC6 data and flags ADC7 data and flags ADC8 data and flags ADC9 data and flags ADC10 data and flags ADC11 data and flags ADC12 data and flags ADC13 data and flags ADC14 data and flags ADC15 data and flags ADC16 data and flags ADC17 data and flags ADC18 data and flags ADC19 data and flags ADC20 data and flags ADC21 data and flags ADC22 data and flags ADC23 data and flags ADC24 data and flags ADC25 data and flags ADC26 data and flags ADC27 data and flags ADC channel select ADC sequencer control ADC sequencer configuration Reserved Reserved Digital comparator configuration ADC conversion configuration Rev. A | Page 26 of 190 Reset 0x0280 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0x111F 0x00000000 0x0008C631 Not applicable Not applicable 0x00000 0x000A0014 Access RW R R R R R R R R R R R R R R R R R R R R R R R R R R R R RW RW RW Not applicable Not applicable RW RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER DETAILS: ADC CIRCUIT ADC Configuration Register Address: 0x40082174, Reset: 0x0280, Name: ADCCON Table 12. Bit Descriptions for ADCCON Bit(s) [15:11] 10 9 Bit Name RESERVED SOFT_RESET PUP 8 7 RESERVED REFB_PUP 6 RESTART_ADC 5 4 RESERVED SEQ_DMA 3 CNV_DMA [2:0] C_TYPE Description Reserved. Software reset ADC. ADC power up. 0: power down. 1: power up. Reserved. ADC reference buffer power up. 0: power down. 1: power up. Must be set to 1 for the ADC to operate normally. Restart ADC, reset analog part of ADC. Active high. 0: clear to 0 for normal ADC operation. 1: set to 1 to reset the ADC. Reserved. DMA request enable for ADC sequence conversion. 0: clear to 0 to disable ADC sequencer DMA access. 1: set to 1 to enable ADC sequencer DMA access. DMA request enable for ADC nonsequence conversion. 0: clear to 0 to disable ADC DMA access. 1: set to 1 to enable ADC DMA access. ADC conversion type. 000: no conversion. 001: DIO pin starts conversion (P2.4). 010: single conversion. 011: continuous conversion (use this mode for the sequencer). 100: PLA conversion. Reset 0x0 0x0 0x1 Access R W RW 0x0 0x1 R RW 0x0 W 0x0 0x0 R RW 0x0 RW 0x0 RW ADCx Data and Flags Register Address: 0x40086000 to 0x4008606C (Increments of 0x4), Reset: 0x00000000, Name: ADCDAT0 to ADCDAT27 At the end of each conversion, the ADC writes the data to the appropriate ADCDATx MMR, where x is 0 to 27. This process takes 2 ADC clock cycles, which at 20 MHz means 100 ns. During this time, the value in ADCDATx cannot be read reliably by the CPU. Therefore, during this time ADCDATx is forced to zero and specifically Bit ADCDATx[3] is zero. Therefore, if ADCDATx is read at random times, ADCDATx[3] must be checked and, if it is zero, ADCDATx must be read again. This second read must be at least 100 ns later, which is basically guaranteed by the time used to check the bit plus the time required to read the value via the D2D interface. Make sure that the second read does not coincide with any further conversion on that channel. Alternately, perform repeated reads until the read is successful. At 1 MSPS conversion speed, the read is valid 90% of the time, while at 100 kSPS, it is valid 99% of the time. When using interrupts, this problem does not occur unless the read happens exactly when a subsequent ADC conversion completes on that channel. This behavior is valid for all conversion modes (single conversions, repeated conversions, and sequencer conversions). Table 13. Bit Descriptions for ADCDAT0 to ADCDAT27 Bit(s) [31:4] Bit Name DAT 3 VALID 2 OLD [1:0] RESERVED Description ADCx data. The numeric value of the conversion is stored in bits 12 to 27. Bit 28 to Bit 31 are the extended sign bits. Bit 4 to Bit 11 are always zero. The format is twos complement (signed integer). Flag indicating if data is valid. 0: data is invalid. 1: data is valid. Flag data has already been read. 0: last data has not been read. 1: last data already read. Reserved. Rev. A | Page 27 of 190 Reset 0x0 Access RW 0x0 R 0x0 RW 0x0 RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ADC Channel Select Register Address: 0x40086080, Reset: 0x111F, Name: ADCCHA ADCCHA is the ADC channel select register for nonsequence operation. Table 14. Bit Descriptions for ADCCHA Bit(s) [15:13] [12:8] Bit Name RESERVED ADCCN [7:5] [4:0] RESERVED ADCCP Description Reserved. Selects channel for ADC negative input. 0x00: AIN0. 0x01: AIN1. 0x02: AIN2. 0x03: AIN3. 0x04: AIN4. 0x05: AIN5. 0x06: AIN6. 0x07: AIN7. 0x08: AIN8. 0x09: AIN9. 0x0A: AIN10. 0x0B: AIN11. 0x0C: AIN12. 0x0D: AIN13. 0x0E: AIN14. 0x0F: AIN15. 0x10: VREFP_NADC: connect ADC_REFP to negative input. 0x11: VREFN_NADC: connect ADC_REFN to negative input. Use this setting for single-ended measurements. 0x12: AGND. 0x13: PGND (ADuCM320i only). 0x14 to 0x1F: reserved. Reserved. Select ADC channel. 0x0: AIN0. 0x1: AIN1. 0x2: AIN2. 0x3: AIN3. 0x4: AIN4. 0x5: AIN5. 0x6: AIN6. 0x7: AIN7. 0x8: AIN8. 0x9: AIN9. 0xA: AIN10. 0xB: AIN11. 0xC: AIN12. 0xD: AIN13. 0xE: AIN14. 0xF: AIN15. 0x10: reserved. 0x11: reserved. 0x12: IDAC3 (ADuCM320i only). 0x13: IDAC1 (ADuCM320i only). 0x14: IDAC0 (ADuCM320i only). 0x15: IDAC2 (ADuCM320i only). 0x16: TEMP_SENSOR. Rev. A | Page 28 of 190 Reset 0x0 0x11 Access R RW 0x0 0x1F R RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) Bit Name UG-868 Description 0x17: VREFP_PADC: connect ADC_REFP to positive input. Note that this pin must not be measured relative to AGND. This selection is for measuring the differential voltage between the negative input and ADC_REFP. 0x18: PVDD_IDAC2: use this to measure the PVDD supply voltage for IDAC2 (ADuCM320i only). 0x19: IOVDD_2: use this to measure half of the IOVDD supply voltage. 0x1A: AVDD_2: use this to measure half of the AVDD supply voltage. 0x1B: VREFN_PADC: connect ADC_REFN to positive input. 0x1C to 0x1F: reserved. Reset Access Reset 0x0 Access W 0x0 W 0x0 0x0 R RW ADC Sequencer Control Register Address: 0x40086088, Reset: 0x00000000, Name: ADCSEQ Table 15. Bit Descriptions for ADCSEQ Bit(s) 31 Bit Name ST 30 EN 29 [28:0] RESERVED CH Description Sequence restart, used to force sequence to start at first channel when sequence is working. 1: Set to 1 to restart the sequencer. Cleared after writing 1. Sequence enable. 1: Set to 1 to enable the sequencer Reserved. Select channels included in sequence operation. Each bit corresponds to an ADC channel as defined by ADCCHA[4:0]. For example, a value of 0x33 (00110011) includes AIN0, AIN1, AIN4, and AIN5 in the sequence and excludes all other channels. For each channel: 0: channel is skipped. 1: channel is included in the sequence. ADC Sequencer Configuration Register Address: 0x4008608C, Reset: 0x0008C631, Name: ADCSEQC Table 16. Bit Descriptions for ADCSEQC Bit(s) [31:28] [27:20] Bit Name RESERVED T [19:15] DIF6 [14:10] DIF4 [9:5] DIF2 [4:0] DIF0 Description Reserved. Define programmable delay of 0 to 254 between sequences. A delay of 255 causes a halt after one sequence. Set ADCSEQ[30] if another sequence is required. Selects differential mode negative input for AIN6 in the sequence. See ADCCHA[12:8] for list of channels. 0x11: Channel 6 is single-ended. Selects differential mode negative input for AIN4 in the sequence. See ADCCHA[12:8] for list of channels. 0x11: Channel 4 is single-ended. Selects differential mode negative input for AIN2 in the sequence. See ADCCHA[12:8] for list of channels. 0x11: Channel 2 is single-ended. Selects differential mode negative input for AIN0 in the sequence. See ADCCHA[12:8] for list of channels. 0x11: Channel 0 is single-ended. Rev. A | Page 29 of 190 Reset 0x0 0x0 Access R RW 0x11 RW 0x11 RW 0x11 RW 0x11 RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Digital Comparator Configuration Register Address: 0x40086098, Reset: 0x00000, Name: ADCCMP Table 17. Bit Descriptions for ADCCMP Bit(s) [17:2] 1 Bit Name THR DIR 0 EN Description Digital compare threshold. Value to compare to Channel 4 data. Select digital comparator direction. 0: ADCTH less than Channel 4 data. 1: ADCTH larger than Channel 4 data. Digital comparator enable. 0: disable. 1: enable. Reset 0x0000 0x0 Access RW RW 0x0 RW ADC Conversion Configuration Register Address: 0x4008609C, Reset: 0x000A0014, Name: ADCCNVC When ADCCP is set to 22 (temperature sensor) or 25 (IOVDD/2) or 26 (AVDD/2), the ADCCNVC register automatically changes to 0x7D00FA − (80 kSPS) for single conversions. ADCCNVC must be set to the required conversion rate after sampling these three channels if a different sample rate is required for other ADC input channels. When the sequencer is enabled and includes any of these three channels, the value in ADCCNVC does not change, and the ADC sampling rate does not change. Table 18. Bit Descriptions for ADCCNVC Bit(s) [31:26] [25:16] Bit Name Reserved CNVD [15:10] [9:0] Reserved CNVC Description Do not overwrite. Configure ADC acquisition time and sampling time. Acquisition time = CNVD/20 MHz. Default acquisition time is 500 ns. For best SNR results, ensure the acquisition time is set to ≥500 ns for all ADC conversion rates. Do not overwrite. Configure conversion frequency. Conversion frequency = 20 MHz/CNVC. Reset 0x0 0xA Access RW RW 0x00 0x14 RW RW REGISTER SUMMARY: ADDITIONAL REGISTERS The CPU accesses these additional registers over a die to die interface (D2D), which increases the execution times of LDR and STR instructions. The 32-bit MMRs have addresses of 0x40087xxx and take 8 CPU cycles at 80 MHz to execute. The 8-bit MMRs have addresses of 0x40081xxx and take 5 CPU cycles at 80 MHz to execute. Table 19. Register Summary Address 0x40081400 0x40087830 0x40087834 Name IBUFCON AFETEMPC AFEREFC Description Input buffer control bit register Temperature sensor configuration register Reference configuration register Rev. A | Page 30 of 190 Reset 0x000F 0x00 0x00 Access RW RW RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER DETAILS: ADDITIONAL REGISTERS Input Buffer Control Bit Register Address: 0x40081400, Reset: 0x000F, Name: IBUFCON Table 20. Bit Descriptions for IBUFCON Bit(s) [15:4] [3:2] Bit Name RESERVED IBUF_PD [1:0] IBUF_BYP ADuCM320i Description Reserved. Power down P/N input buffer separately. 00: both sides powered on (ADuCM320i only). 01: N side powered down (ADuCM320i only). 10: P side powered down (ADuCM320i only). 11: both sides powered down. Bypass P/N input buffer separately. 00: bypass neither side (ADuCM320i only). 01: N side bypassed (ADuCM320i only). 10: P side bypassed (ADuCM320i only). 11: bypass both sides. ADuCM322/ADuCM322i Description Reserved. Reserved. These bits must write 0x3 to the user code on the ADuCM322/ADuCM322i. If an attempt is made to enable power on, the internal buffers ADC measurement will be distorted. Reset 0x0 0x3 Access RW RW Reserved. These bits must write 0x3 to user code on the ADuCM322 and the ADuCM322i. 0x3 RW Reset 0x0 0x0 Access R RW 0x0 RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW Temperature Sensor Configuration Register Address: 0x40087830, Reset: 0x00, Name: AFETEMPC Table 21. Bit Descriptions for AFETEMPC Bit(s) [7:2] 1 Bit Name RESERVED CHOP 0 PD Description Reserved. Temperature sensor chopping enable. Do not use chopping mode together with the sequencer. 0: disable chopping mode. 1: enable chopping mode. Temperature sensor power down. 0: power up temperature sensor. 1: power down temperature sensor. Reference Configuration Register Address: 0x40087834, Reset: 0x00, Name: AFEREFC Table 22. Bit Descriptions for AFEREFC Bit(s) 7:4 3 Bit Name RESERVED REF 2 B2MA_PDB 1 B2V5R_PD 0 BG_PD Description Reserved. Bypass the internal reference, and select the external reference. 0: select internal 2.5 V reference. 1: select external 2.5 V reference. Power down the reference 2 mA output driving Buffer B. 0: power down 2.5 V reference output driving Buffer B. 1: power up 2.5 V reference output driving Buffer B. 2.5 V reference buffer power down. 0: power up 2.5 V reference buffer. 1: power down 2.5 V reference buffer. Band gap power down. 0: power up 1.2 V band gap. 1: power down 1.2 V band gap. Rev. A | Page 31 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ANALOG COMPARATOR ANALOG COMPARATOR FEATURES The analog comparator compares two analog signals and gives an output indicating which of the input signals is bigger. This output can generate an interrupt. ANALOG COMPARATOR OVERVIEW The positive input of the comparator is shared with AIN6. The negative input of the comparator can be set by software to AVDD/2, AIN5, or DAC7. The comparator output is connected to the interrupt logic and can be used as described in the System Exceptions and Peripheral Interrupts section. ANALOG COMPARATOR OPERATION If required, change the hysteresis with AFECOMP[0], the comparator speed with AFECOMP[1:2], and the output polarity with AFECOMP[3]. Select the input source with AFECOMP[6:7]. Power up and enable the comparator with AFECOMP[8] and AFECOMP[4:5]. REGISTER SUMMARY: ANALOG COMPARATOR The CPU accesses the ADC circuit over a die to die interface (D2D) which increases the execution times of LDR and STR instructions. Accessing AFECOMP takes 8 CPU cycles at 80 MHz to execute. Table 23. Analog Comparator Register Summary Address 0x40087838 Name AFECOMP Description Analog comparator configuration register Reset 0x0000 Access RW REGISTER DETAILS: ANALOG COMPARATOR Analog Comparator Configuration Register Address: 0x40087838, Reset: 0x0000, Name: AFECOMP Table 24. Bit Descriptions for AFECOMP Bit(s) [15:9] 8 Bit Name RESERVED EN [7:6] INNEG [5:4] OUT 3 INV [2:1] SPEED 0 HYS Description Reserved. Powers up and enables comparator. 0: power down and disable comparator. 1: power up and enable comparator. Selects comparator negative input signal. 00: AVDD/2. 01: AIN5. 10: DAC7. 11: unused. Connects comparator output to interrupt logic. 0: do not connect output. 1: connect output to interrupt logic. Selects output logic state. 0: output is high if the positive input terminal of the amplifier (+ve) is above the negative input of the terminal of the amplifier (−ve). 1: output is high if +ve input is below −ve input. Selects comparator speed to falling output. Response time to rising output is 6 µs typical. 00: 6 µs. 01: 4 µs. 10: 4 µs. 11: 3 µs. Enables comparator hysteresis. 0: disable hysteresis. 1: enable hysteresis. Rev. A | Page 32 of 190 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 IDACs (ADUCM320i ONLY) IDAC FEATURES The ADuCM320i provides four IDACs, which are low noise, low drift current source outputs. IDAC0, IDAC1, IDAC2, and IDAC3 provide 0 mA to 150 mA full-scale output, bias current setting for optical laser. IDAC BLOCK DIAGRAM AGND LDO PVDD PVDD 3.3V CDAMP 10nF 2.5V OUT 11-BIT IDAC 5-BIT IDAC BUF 1.2V VREF IDAC3 BUF PGND 3.16kΩ RREF 5ppm 0.1% PGND PGND ADC INPUT MUX PGND 13437-008 PULL-DOWN 100µA SINK CURRENT Figure 10. Example IDAC Circuit—IDAC3 IDAC OVERVIEW Precision Current Generation and Fault Protection The reference current for the IDACs is generated by a precision internal band gap voltage reference (VBANDGAP) and an external precision resistor (RREF, 5 ppm, 0.1%). The reference current is equal to VBANDGAP ÷ RREF. The band gap voltage reference is a low drift, high accuracy voltage source that helps to minimize the overall IDAC gain error and gain error drift. The noise of the IDAC outputs is limited by the low-pass filter on the output stage; each IDAC requires a 10 nF capacitor between PVDD and its CDAMP pin. Figure 10 shows the typical architecture of the IDAC. The parallel 11-bit and 5-bit IDACs set the output current. The output of these IDACs are summed together and fed to a current mirror and then are gained up at the output stage. Production trimming of the low dropout (LDO) band gap reference aids performance. In addition, gain trimming and scaling of the current mirror and output stages are also included in the ATE test program. IDAC Shutdown IDAC0, IDAC1, IDAC2, and IDAC3 also have a small current sink capability to minimize the offset current when the data register is set to 0. The IDACxCON[1] bit can enable a pull-down current source to PGND. This pull-down current is typically 100 µA. IDAC Output Filter Each IDAC has a filter on the output stage to minimize noise. Each IDAC requires an external 10 nF capacitor between PVDD and its CDAMP pin, as per the ADuCM320i data sheet. The on-chip, programmable resistor is controlled by the IDACxCON[5:2] bits. Table 25. IDAC Filter Bandwidth Control Settings IDACxCON[5:2] 0000 0101 0110 0111 1000 1001 All other options are reserved R Value 60 Ω 5.6 kΩ 11.2 kΩ 22.2 kΩ 44.4 kΩ 104 kΩ Rev. A | Page 33 of 190 Cutoff Frequency (fC) 262 kHz 2.8 kHz 1.4 kHz 715 Hz 357 Hz 153 Hz UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual IDAC Data Register The IDAC output is controlled by an internal 11-bit and 5-bit DAC. 14-BIT IDAC OUTPUT 13 12 11 10 9 8 7 6 5 4 3 11-BIT DAC 27 26 25 24 23 22 21 20 19 18 17 16 15 2 1 0 14 13 12 IDACxDAT 5-BIT DAC 13437-009 The 11-bit DAC (IDACxDAT[27:17]) controls the most significant bits. The 5-bit DAC (IDACxDAT[16:12]) controls the LSBs. The two MSBs of the 5-bit DAC (IDACxDAT[16:15]) overlap the two LSBs of the 11-bit DAC (IDACxDAT[18:17]) as shown in Figure 11. Figure 11. 14-Bit IDAC Output The 11-bit DAC and the 5-bit DAC are guaranteed monotonic as individual DACs. This combination makes it possible to reach 14-bit resolution—up to 16,384 unique output values. However, monotonicity is only guaranteed for 11 bits (DNL < −1 LSB). IDACs Common Use Cases Case 1: Setting the Output Current of IDAC1 to Quarter Scale Set up IDAC1CON to 10xxxx00b: • • • • • • IDAC1CON[7] = 1: enable writes to the IDAC1DAT register. IDAC1CON[0] = 0: power up IDAC1. IDAC1CON[5:2] as per Table 25: set up the filter bandwidth as required. IDAC1CON[1] = 0: disable the IDAC1 pull-down current source. IDAC1DAT[3] = 0: clear the IDAC1 sync bit to allow immediate updating of the IDAC. IDAC1CON[6] = 0: disable the over temperature shutdown feature. Set up IDAC1DAT to give a current output of quarter scale: • • If IDAC1 is used in an open loop system or in a set and forget type operation, set IDAC1DAT = 0x03FE0000. Set IDAC1DAT[27:17] = 0x1FF. Set IDAC1DAT[16:12] = 0x00. • If IDAC1 is used in a closed loop system, set IDAC1DAT = 0x03FCF000. • Set IDAC1DAT[27:17] = 0x1FE. • Set IDAC1DAT[16:12] = [01111]b. • Adjust the 5-bit IDAC (IDAC1DAT[16:12]) up or down accordingly to attain the correct setting. Case 2: Turn on IDAC2 and Set Output to 0 mA with the Lowest Possible Offset Before powering up the IDACs, ensure that the internal reference is fully powered on. Set up the IDAC2CON register to 10xxxx00b: • • • • • IDAC2CON[7] = 1: enable writes to the IDAC2DAT register. IDAC2CON[0] = 0: power up IDAC2. IDAC2CON[5:2] as per Table 25: set up the filter bandwidth as required. IDAC2CON[1] = 0: enable the IDAC2 pull-down current sink. IDAC2CON[6] = 0: disable the overtemperature shutdown feature. Set up the IDAC2DAT register: • IDAC2DAT[27:12] = 0x0000: set the IDAC to zero scale. If any or all the IDACs are not used, connect the pins as follows: • • • • IREF: if no IDACs are used, connect a low cost 3.3 kΩ resistor to ground. If no PVDD supply is available, connect PVDDx of all IDACs to AVDD_REG1 (Ball F10). Make sure not to power up such IDACs to avoid loading AVDD_REG1 unnecessarily. Leave the CDAMPx pin of any unused IDACs unconnected. For the IDACx of individual unused IDACs: • Power down IDACx using the PD bit (IDACxCON = 1; this bit is powered down after a reset). • Set IDACxDAT = 0 (zero current; this bit is 0 after a reset). • Connect IDACx pin to PGND. Rev. A | Page 34 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER SUMMARY: IDAC The CPU accesses the IDAC circuit over a die to die interface (D2D), which increases the execution times of LDR and STR instructions. The 32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute. Table 26. IDAC Register Summary Address 0x40086800 0x40086804 0x40086808 0x4008680C 0x40086810 0x40086814 0x40086818 0x4008681C Name IDAC0DAT IDAC0CON IDAC1DAT IDAC1CON IDAC2DAT IDAC2CON IDAC3DAT IDAC3CON Description IDAC0 data register IDAC0 control register IDAC1 data register IDAC1 control register IDAC2 data register IDAC2 control register IDAC3 data register IDAC3 control register Reset 0x00000000 0x01 0x00000000 0x01 0x00000000 0x01 0x00000000 0x01 Access RW RW RW RW RW RW RW RW REGISTER DETAILS: IDAC IDAC0 Data Register Address: 0x40086800, Reset: 0x00000000, Name: IDAC0DAT Table 27. Bit Descriptions for IDAC0DAT Bit(s) [31:28] [27:17] [16:12] [11:4] 3 Bit Name RESERVED DATH DATL RESERVED SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 Description Reserved. Write 0. IDAC0 high data. IDAC0 low data. Reserved. IDAC3 sync bit. Setting the SYNC3 bits of all IDAC channels to 1 prevents IDAC3 from updating. When the SYNC3 bit of any of the IDAC channels is 0, IDAC3 updates immediately when it is written. IDAC2 sync bit. Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating. When the SYNC2 bit of any of the IDAC channels is 0, IDAC2 updates immediately when it is written. IDAC1 sync bit. Setting the SYNC1 bits of all IDAC channels to 1 prevents IDAC1 from updating. When the SYNC1 bit of any of the IDAC channels is 0, IDAC1 updates immediately when it is written. IDAC0 sync bit. Setting the SYNC0 bits of all IDAC channels to 1 prevents IDAC0 from updating. When the SYNC0 bit of any of the IDAC channels is 0, IDAC0 updates immediately when it is written. Reset 0x0 0x0 0x0 0x0 0x0 Access R RW RW R RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0x0 0x0 RW RW 0x1 RW IDAC0 Control Register Address: 0x40086804, Reset: 0x01, Name: IDAC0CON Table 28. Bit Descriptions for IDAC0CON Bit(s) 7 Bit Name CLRB 6 SHT_EN [5:2] 1 BW PUL 0 PD Description IDAC0 clear bit. 0: clear IDAC0DAT. 1: enable write. IDAC0 shutdown enable. Enables automatic shutdown in case of overtemperature. 0: disable this function. 1: enable this function. IDAC0 bandwidth. See the IDAC Output Filter section for more details. IDAC0 pull down. 0: disable the pull-down current source. 1: enable the pull-down current source. IDAC0 power down. 0: powers up IDAC0. 1: powers down IDAC0. Rev. A | Page 35 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual IDAC1 Data Register Address: 0x40086808, Reset: 0x00000000, Name: IDAC1DAT Table 29. Bit Descriptions for IDAC1DAT Bit(s) [31:28] [27:17] [16:12] [11:4] 3 Bit Name RESERVED DATH DATL RESERVED SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 Description Reserved. Write 0. IDAC1 high data. IDAC1 low data. Reserved. IDAC3 sync bit. Setting the SYNC3 bits of all IDAC channels to 1 prevents IDAC3 from updating. When the SYNC3 bit of any of the IDAC channels is 0, IDAC3 updates immediately when it is written. IDAC2 sync bit. Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating. When the SYNC2 bit of any of the IDAC channels is 0, IDAC2 updates immediately when it is written. IDAC1 sync bit. Setting the SYNC1 bits of all IDAC channels to 1 prevents IDAC1 from updating. When the SYNC1 bit of any of the IDAC channels is 0, IDAC1 updates immediately when it is written. IDAC0 sync bit. Setting the SYNC0 bits of all IDAC channels to 1 prevents IDAC0 from updating. When the SYNC0 bit of any of the IDAC channels is 0, IDAC0 updates immediately when it is written. Reset 0x0 0x0 0x0 0x0 0x0 Access R RW RW R RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0x0 0x0 RW RW 0x1 RW Reset 0x0 0x0 0x0 0x0 0x0 Access R RW RW R RW 0x0 RW 0x0 RW 0x0 RW IDAC1 Control Register Address: 0x4008680C, Reset: 0x01, Name: IDAC1CON Table 30. Bit Descriptions for IDAC1CON Bit(s) 7 Bit Name CLRB 6 SHT_EN [5:2] 1 BW PUL 0 PD Description IDAC1 clear bit. 0: clear IDAC1DAT. 1: enable write. IDAC1 shutdown enable. Enables automatic shutdown in case of overtemperature. 0: disable this function. 1: enable this function. IDAC1 bandwidth. See the IDAC Output Filter section for more details. IDAC1 pull down. 0: disable the pull-down current source. 1: enable the pull-down current source. IDAC1 power down. 0: powers up IDAC1. 1: powers down IDAC1. IDAC2 Data Register Address: 0x40086810, Reset: 0x00000000, Name: IDAC2DAT Table 31. Bit Descriptions for IDAC2DAT Bit(s) [31:28] [27:17] [16:12] [11:4] 3 Bit Name RESERVED DATH DATL RESERVED SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 Description Reserved. Write 0. IDAC2 high data. IDAC2 low data. Reserved. IDAC3 sync bit. Setting the SYNC3 bits of all IDAC channels to 1 prevents IDAC3 from updating. When the SYNC3 bit of any of the IDAC channels is 0, IDAC3 updates immediately when it is written. IDAC2 sync bit. Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating. When the SYNC2 bit of any of the IDAC channels is 0, IDAC2 updates immediately when it is written. IDAC1 sync bit. Setting the SYNC1 bits of all IDAC channels to 1 prevents IDAC1 from updating. When the SYNC1 bit of any of the IDAC channels is 0, IDAC1 updates immediately when it is written. IDAC0 sync bit. Setting the SYNC0 bits of all IDAC channels to 1 prevents IDAC0 from updating. When the SYNC0 bit of any of the IDAC channels is 0, IDAC0 updates immediately when it is written. Rev. A | Page 36 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 IDAC2 Control Register Address: 0x40086814, Reset: 0x01, Name: IDAC2CON Table 32. Bit Descriptions for IDAC2CON Bit(s) 7 Bit Name CLR 6 SHT_EN [5:2] 1 BW PUL 0 PD Description IDAC2 clear bit. 0: clear IDAC2DAT. 1: enable write. IDAC2 shutdown enable. Enables automatic shutdown in case of overtemperature. 0: disable this function. 1: enable this function. IDAC2 bandwidth. See the IDAC Output Filter section for more details. IDAC2 pull down. 0: disable the pull-down current source. 1: enable the pull-down current source. IDAC2 power down. 0: powers up IDAC2. 1: powers down IDAC2. Reset 0x0 Access RW 0x0 RW 0x0 0x0 RW RW 0x1 RW Reset 0x0 0x0 0x0 0x0 0x0 Access R RW RW R RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0x0 0x0 RW RW 0x1 RW IDAC3 Data Register Address: 0x40086818, Reset: 0x00000000, Name: IDAC3DAT Table 33. Bit Descriptions for IDAC3DAT Bit(s) [31:28] [27:17] [16:12] [11:4] 3 Bit Name RESERVED DATH DATL RESERVED SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 Description Reserved. Write 0. IDAC3 high data. IDAC3 low data. Reserved. IDAC3 sync bit. Setting the SYNC3 bits of all IDAC channels to 1 prevents IDAC3 from updating. When the SYNC3 bit of any of the IDAC channels is 0, IDAC3 updates immediately when it is written. IDAC2 sync bit. Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating. When the SYNC2 bit of any of the IDAC channels is 0, IDAC2 updates immediately when it is written. IDAC1 sync bit. Setting the SYNC1 bits of all IDAC channels to 1 prevents IDAC1 from updating. When the SYNC1 bit of any of the IDAC channels is 0, IDAC1 updates immediately when it is written. IDAC0 sync bit. Setting the SYNC0 bits of all IDAC channels to 1 prevents IDAC0 from updating. When the SYNC0 bit of any of the IDAC channels is 0, IDAC0 updates immediately when it is written. IDAC3 Control Register Address: 0x4008681C, Reset: 0x01, Name: IDAC3CON Table 34. Bit Descriptions for IDAC3CON Bit(s) 7 Bit Name CLR 6 SHT_EN [5:2] 1 BW PUL 0 PD Description IDAC3 Clear bit. 0: clear IDAC3DAT. 1: enable write. IDAC3 shutdown enable. Enables automatic shutdown in case of overtemperature. 0: disable this function. 1: enable this function. IDAC3 bandwidth. See the IDAC Output Filter section for more details. IDAC3 pull down. 0: disable the pull-down current source. 1: enable the pull-down current source. IDAC3 power down. 0: powers up IDAC3. 1: powers down IDAC3. Rev. A | Page 37 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual VDACs VDAC FEATURES The ADuCM320i/ADuCM322/ADuCM322i have eight VDACs. The specified load resistance is greater than 5 kΩ, and the specified capacitance is less than 100 pF. VDAC BLOCK DIAGRAM VREF STRING DAC DAC BUFFER 13437-010 DACOUT Figure 12. Output Mode Capacitor Load ≤ 100 pF VDAC OVERVIEW The ADuCM320i/ADuCM322/ADuCM322i have eight VDACs specified to drive 5 kΩ load, 500 µA maximum. The VDACs can select from two reference sources: • • 0 V to internal reference, VREF (0 V to 2.5 V) 0 V to AVDD (3.3 V) VDAC OPERATION The DAC is configurable through a control register and a data register. The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, as shown in Figure 12. The linearity specification of the DAC when driving a 5 kΩ resistive load to ground is guaranteed through the full transfer function except for Code 0 to Code 100; in 0 V to AVDD mode, the linearity specification is also not guaranteed for Code 3995 to Code 4095. Linearity degradation near ground and AVDD is caused by saturation of the output amplifier; a general representation of its effects (neglecting offset and gain error) is shown in Figure 13. The dotted line in Figure 13 indicates the ideal transfer function. The solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. Figure 13 represents a transfer function in 0 V to AVDD mode only. In 0 V to VREF mode, the lower nonlinearity is similar. However, the upper portion of the transfer function follows the ideal line all the way to the end, showing no signs of endpoint linearity errors. 0x00000000 0x0FFF0000 13437-016 AVDD Figure 13. DAC Endpoint Nonlinearities Due to Amplifier Saturation Rev. A | Page 38 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER SUMMARY: VDAC The CPU accesses the VDAC circuit over a die to die interface (D2D), which increases the execution times of LDR and STR instructions. The 32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute. The 16-bit MMRs have addresses of 0x40082xxx and take 6 CPU cycles at 80 MHz to execute. Table 35. VDAC Register Summary Address 0x40082400 0x40082404 0x40082408 0x4008240C 0x40082410 0x40082414 0x40082418 0x4008241C 0x40086404 0x40086408 0x4008640C 0x40086410 0x40086414 0x40086418 0x4008641C 0x40086420 Name DAC0CON DAC1CON DAC2CON DAC3CON DAC4CON DAC5CON DAC6CON DAC7CON DAC0DAT DAC1DAT DAC2DAT DAC3DAT DAC4DAT DAC5DAT DAC6DAT DAC7DAT Description DAC0 control register DAC1 control register DAC2 control register DAC3 control register DAC4 control register DAC5 control register DAC6 control register DAC7 control register DAC0 data register DAC1 data register DAC2 data register DAC3 data register DAC4 data register DAC5 data register DAC6 data register DAC7 data register Reset 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW REGISTER DETAILS: VDAC DAC0 Control Register Address: 0x40082400, Reset: 0x0100, Name: DAC0CON Table 36. Bit Descriptions for DAC0CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC0 power down. 0: DAC0 is powered up. 1: DAC0 is powered down and output is floating. Reserved. DAC0 enable. Must be set to 1. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC0 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Rev. A | Page 39 of 190 Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DAC1 Control Register Address: 0x40082404, Reset: 0x0100, Name: DAC1CON Table 37. Bit Descriptions for DAC1CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC1 power down. 0: DAC1 is powered up. 1: DAC1 is powered down and output is floating. Reserved. DAC1 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC1 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 RW DAC2 Control Register Address: 0x40082408, Reset: 0x0100, Name: DAC2CON Table 38. Bit Descriptions for DAC2CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC2 power down. 0: DAC2 is powered up. 1: DAC2 is powered down and output is floating. Reserved. DAC2 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC2 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. DAC3 Control Register Address: 0x4008240C, Reset: 0x0100, Name: DAC3CON Table 39. Bit Descriptions for DAC3CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] RESERVED Description Reserved. DAC3 power down. 0: DAC3 is powered up. 1: DAC3 is powered down and output is floating. Reserved. Rev. A | Page 40 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 4 Bit Name EN [3:2] [1:0] RESERVED RN Description DAC3 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately 1: DAC enable. Reserved. DAC3 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. UG-868 Reset 0x0 Access RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW DAC4 Control Register Address: 0x40082410, Reset: 0x0100, Name: DAC4CON Table 40. Bit Descriptions for DAC4CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC4 power down. 0: DAC4 is powered up. 1: DAC4 is powered down and output is floating. Reserved. DAC4 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC4 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. DAC5 Control Register Address: 0x40082414, Reset: 0x0100, Name: DAC5CON Table 41. Bit Descriptions for DAC5CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC5 power down. 0: DAC5 is powered up. 1: DAC5 is powered down and output is floating. Reserved. DAC5 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC5 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Rev. A | Page 41 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DAC6 Control Register Address: 0x40082418, Reset: 0x0100, Name: DAC6CON Table 42. Bit Descriptions for DAC6CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC6 power down. 0: DAC6 is powered up. 1: DAC6 is powered down and output is floating. Reserved. DAC6 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC6 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW DAC7 Control Register Address: 0x4008241C, Reset: 0x0100, Name: DAC7CON Table 43. Bit Descriptions for DAC7CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC7 power down. 0: DAC7 is powered up. 1: DAC7 is powered down and output is floating. Reserved. DAC7 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC7 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Rev. A | Page 42 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DAC0 Data Register Address: 0x40086404, Reset: 0x00000000, Name: DAC0DAT Table 44. Bit Descriptions for DAC0DAT Bit(s) [31:28] [27:16] [15:0 Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC0 data. Reserved. Write 0. Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R DAC1 Data Register Address: 0x40086408, Reset: 0x00000000, Name: DAC1DAT Table 45. Bit Descriptions for DAC1DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC1 data. Reserved. Write 0. DAC2 Data Register Address: 0x4008640C, Reset: 0x00000000, Name: DAC2DAT Table 46. Bit Descriptions for DAC2DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC2 data. Reserved. Write 0. DAC3 Data Register Address: 0x40086410, Reset: 0x00000000, Name: DAC3DAT Table 47. Bit Descriptions for DAC3DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC3 data. Reserved. Write 0. DAC4 Data Register Address: 0x40086414, Reset: 0x00000000, Name: DAC4DAT Table 48. Bit Descriptions for DAC4DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC4 data. Reserved. Write 0. DAC5 Data Register Address: 0x40086418, Reset: 0x00000000, Name: DAC5DAT Table 49. Bit Descriptions for DAC5DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC5 data. Reserved. Write 0. Rev. A | Page 43 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DAC6 Data Register Address: 0x4008641C, Reset: 0x00000000, Name: DAC6DAT Table 50. Bit Descriptions for DAC6DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC6 data. Reserved. Write 0. Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R DAC7 Data Register Address: 0x40086420, Reset: 0x00000000, Name: DAC7DAT Table 51. Bit Descriptions for DAC7DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC7 data. Reserved. Write 0. Rev. A | Page 44 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS CORTEX-M3 AND FAULT MANAGEMENT The ADuCM320i/ADuCM322/ADuCM322i integrate an ARM Cortex-M3 processor, which supports several system exceptions and interrupts generated by peripherals. Table 52 lists the ARM Cortex-M3 processor system exceptions. Table 52. System Exceptions Number 1 2 Type Reset NMI Priority −3 (highest) −2 3 4 5 Hard fault Memory management fault Bus fault −1 Programmable Programmable 6 7 to 10 11 12 13 14 Usage fault Reserved SVCALL Debug monitor Reserved PENDSV Programmable Not applicable. Programmable Programmable Not applicable Programmable 15 SYSTICK Programmable Description Any reset. Nonmaskable interrupt not connected on the ADuCM320i/ADuCM322/ ADuCM322i. All fault conditions if the corresponding fault handler is not enabled. Memory management fault; access to invalid locations. Prefetch fault, memory access fault, data abort, and other address/memory related faults. Same as undefined instruction executed or invalid state transition attempt. Not applicable. System service call with SVC instruction. Used for system function calls. Debug monitor (breakpoint, watchpoint, or external debug requests). Not applicable. Pendable request for system service. Used for queuing system calls until other tasks and interrupts are serviced. System tick timer. The NVIC controls the peripheral interrupts and are listed in Table 53. All interrupt sources can wake up the device from Mode 1. Only a limited number of interrupts can wake up the processor from the low power modes (Mode 2 and Mode 3), as shown in Table 53. When the device is woken up from Mode 2 or Mode 3, it returns to Mode 0. If the processor enters any power mode from Mode 1 to Mode 3 while the processor is in an interrupt handler, only an interrupt source with a higher priority than the current interrupt can wake up the device (higher value in IPRx registers). Two steps are usually required to configure an interrupt: • • Configuring a peripheral to generate an interrupt request to the NVIC. Configuring the NVIC for that peripheral request. Table 53. Interrupt Vector Table Position No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Vector Wake-up timer External Interrupt 0 External Interrupt 1 External Interrupt 2 Reserved External Interrupt 4 External Interrupt 5 Reserved External Interrupt 7 External Interrupt 8 Watchdog timer Reserved Reserved Low Voltage Die Interrupt 0 MDIO General-Purpose Timer 0 General-Purpose Timer 1 Flash controller UART SPI0 Wake-Up Processor from Mode 1 Yes Yes Yes Yes Wake-Up Processor from Mode 2 or Mode 3 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No Rev. A | Page 45 of 190 UG-868 Position No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Vector SPI1 I2C0 slave I2C0 master PLA 0 PLA 1 DMA error DMA Channel 0 (SPI0 Tx) done DMA Channel 1 (SPI0 Rx) done DMA Channel 2 (SPI1 Tx) done DMA Channel 3 (SPI1 Rx) done DMA Channel 4 (UART Tx) done DMA Channel 5 (UART Rx) done DMA Channel 6 (I2C0 slave Tx ) done DMA Channel 7 (I2C0 slave Rx) done DMA Channel 8 (I2C0 master) done DMA Channel 9 (I2C1 slave Tx) done DMA Channel 10 (I2C1 slave Rx) done DMA Channel 11 (I2C1 master) done DMA Channel 12 (ADC) done DMA Channel 13 (flash) done Reserved Reserved Reserved Reserved I2C1 slave I2C1 master PLA 2 PLA 3 General-Purpose Timer 2 Low Voltage Die Interrupt 1 PWM trip PWM Pair 0 PWM Pair 1 PWM Pair 2 PWM Pair 3 Wake-Up Processor from Mode 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Wake-Up Processor from Mode 2 or Mode 3 No No No No No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No Internal to the ARM Cortex-M3 processor, the highest user-programmable priority (0) is treated as fourth priority, which is after a reset, an NMI, and a hard fault. The ADuCM320i/ADuCM322/ADuCM322i implement three priority bits, which means that eight priority levels are available as programmable priorities. Note that 0 is the default priority for all the programmable priorities. If the same priority level is assigned to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both SPI0 and SPI1 are Priority Level 1, SPI0 has higher priority. To enable an interrupt for any peripheral listed from 0 to 31 in Table 53, set the appropriate bit in the ISER0 register. ISER0 is a 32-bit register, and each bit corresponds to the first 32 entries in Table 53. For example, to enable External Interrupt 4 interrupt source in the NVIC, set ISER0[5] = 1. Similarly, to disable External Interrupt 4, set ICER0[5] = 1. To enable an interrupt for any peripheral listed from 32 to 54 in Table 53, set the appropriate bit in the ISER1 register. ISER1 is a 32-bit register, and ISER1 Bit 0 to Bit 22 correspond to the entries 32 to 54 in Table 53. For example, to enable the PWM Pair 0 interrupt source in the NVIC, set ISER1[20] = 1. Similarly, to disable the PWM Pair 0 interrupt, set ICER1[20] = 1. Alternatively, CMSIS provides a number of useful NVIC functions in the core_cm3.h file. The NVIC_EnableIRQ(PWM_PAIR0_IRQn) function enables the PWM Pair 0 interrupt. The interrupt can be disabled by calling the NVIC_DisableIRQ(PWM_PAIR0_IRQn) function. To set the priority of a peripheral interrupt, the IPRx bits can be set appropriately or, alternatively, the NVIC_SetPriority() function can be called. For example, NVIC_SetPriority(TIMER0_IRQn, 2) configures the General-Purpose Timer 0 interrupt with a priority level of 2. Rev. A | Page 46 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Table 54 lists the registers to enable and disable relevant interrupts and set the priority levels. The registers in Table 54 are defined in the CMSIS core_cm3.h file, which is shipped with tools from third party vendors. Table 54. NVIC Registers Address 0xE000E004 0xE000E010 0xE000E014 0xE000E018 0xE000E01C 0xE000E100 0xE000E104 0xE000E180 Analog Devices Header File Name ICTR STCSR STRVR STCVR STCR ISER0 ISER1 ICER0 0xE000E184 ICER1 0xE000E200 0xE000E204 0xE000E280 0xE000E284 0xE000E300 0xE000E304 0xE000E400 0xE000E404 0xE000E408 0xE000E40C 0xE000E410 0xE000E414 0xE000E418 0xE000E41C 0xE000E420 0xE000E424 0xE000E428 0xE000E42C 0xE000E430 0xE000E434 0xE000ED00 0xE000ED04 0xE000ED08 0xE000ED0C 0xE000ED10 0xE000ED14 0xE000ED18 0xE000ED1C 0xE000ED20 0xE000ED24 0xE000ED28 0xE000ED2C 0xE000ED34 0xE000ED38 0xE000EF00 ISPR0 ISPR1 ICPR0 ICPR1 IABR0 IABR1 IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 IPR10 IPR11 IPR12 IPR13 CPUID ICSR VTOR AIRCR SCR CCR SHPR1 SHPR2 SHPR3 SHCRS CFSR HFSR MMAR BFAR STIR Description Shows the number of interrupt lines that the NVIC supports. SYSTICK control and status register. SYSTICK reload value register. SYSTICK current value register. SYSTICK calibration value register. Set IRQ0 to IRQ31 enable. Each bit corresponds to Interrupt 0 to Interrupt 31 in Table 53. Set IRQ32 to IRQ54 enable. Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 53. Clear IRQ0 to IRQ31 by setting appropriate bit. Each bit corresponds to Interrupt 0 to Interrupt 31 in Table 53. Clear IRQ32 to IRQ54 by setting appropriate bit. Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 53. Set IRQ0 to IRQ31 pending. Each bit corresponds to Interrupt 32 to Interrupt 38 in Table 53. Set IRQ32 to IRQ54 pending. Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 53. Clear IRQ0 to IRQ31 pending. Each bit corresponds to Interrupt 32 to Interrupt 38 in Table 53. Clear IRQ32 to IRQ54 pending. Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 53. IRQ0 to IRQ31 active bits. IRQ32 to IRQ54 active bits. IRQ0 to IRQ3 priority. IRQ4 to IRQ7 priority. IRQ8 to IRQ11 priority. IRQ12 to IRQ15 priority. IRQ16 to IRQ19 priority. IRQ20 to IRQ23 priority. IRQ24 to IRQ27 priority. IRQ28 to IRQ31 priority. IRQ32 to IRQ35 priority. IRQ36 to IRQ39 priority. IRQ40 to IRQ43 priority. IRQ44 to IRQ47 priority. IRQ48 to IRQ51 priority. IRQ52 to IRQ54 priority. CPUID base register. Interrupt control and status register. Vector table offset register. Application interrupt/reset control register. System control register. Configuration control register. System Handlers Register 1. System Handlers Register 2. System Handlers Register 3. System handler control and state. Configurable fault status. Hard fault status. Memory manage fault address register. Bus fault address. Software trigger interrupt register. Rev. A | Page 47 of 190 Access R RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW RW W UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual EXTERNAL INTERRUPT CONFIGURATION Seven external interrupts are implemented. These seven external interrupts can be separately configured to detect any combination of the following type of events: • • Edge: rising edge, falling edge, or both rising and falling edges. An interrupt signal (pulse) is sent to the NVIC upon detecting a transition from low to high, high to low, or on either high to low or low to high. Level: high or low. An interrupt signal is generated and remains asserted in the NVIC until the conditions generating the interrupt deassert. The level must be maintained for a minimum of one core clock cycle to be detected. The external interrupt detection unit block is in the always-on section and allows external interrupt to wake up the device when in hibernate mode. Ensure that the associated GPxIE register bit is enabled for the required external interrupt input. The GPxIE register enables the input path circuit for the external interrupt. For example, for External Interrupt 0, the following code disables the P0.3 output and enables the input path. The appended code also enables the External Interrupt 0 NVIC interrupt source: pADI_GP0->GPOE &= 0xf7; //Disable P0.3 output. pADI_GP0->GPIE |= 0x8; //Enable input path for P0.3 input. pADI_INTERRUPT->EI0CFG |= 0x8; //External IRQ0 enabled. NVIC_EnableIRQ(EINT0_IRQn); //Enable External Interrupt 0 source. REGISTER SUMMARY: EXTERNAL INTERRUPTS Table 55. External Interrupts Register Summary Address 0x40002420 0x40002424 0x40002428 0x40002430 Name EI0CFG EI1CFG EI2CFG EICLR Description External Interrupt Configuration 0 External Interrupt Configuration 1 External Interrupt Configuration 2 External interrupt clear Reset 0x0000 0x0000 0x0000 0x0000 Access RW RW RW RW REGISTER DETAILS: EXTERNAL INTERRUPTS External Interrupt Configuration Register 0 Address: 0x40002420, Reset: 0x0000, Name: EI0CFG Table 56. Bit Descriptions for EI0CFG Bit(s) [15:12] 11 Bit Name RESERVED IRQ2EN [10:8] IRQ2MDE 7 IRQ1EN Description Reserved. External Interrupt 2 enable bit. 0: External Interrupt 2 disabled. 1: External Interrupt 2 enabled. External Interrupt 2 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). External Interrupt 1 enable bit. 0: External Interrupt 0 disabled. 1: External Interrupt 0 enabled. Rev. A | Page 48 of 190 Reset 0 0x0 Access RW 0x0 RW 0x0 RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) [6:4] Bit Name IRQ1MDE 3 IRQOEN [2:0] IRQ0MDE Description External Interrupt 1 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). External Interrupt 0 enable bit. 0: External Interrupt 0 disabled. 1: External Interrupt 0 enabled. External Interrupt 0 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). UG-868 Reset 0x0 Access RW 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0 0x0 RW 0x0 RW External Interrupt Configuration Register 1 Address: 0x40002424, Reset: 0x0000, Name: EI1CFG Table 57. Bit Descriptions for EI1CFG Bit(s) 15 Bit Name IRQ7EN [14:12] IRQ7MDE [11:8] 7 RESERVED IRQ5EN [6:4] IRQ5MDE Description External Interrupt 7 enable bit. 0: External Interrupt 7 disabled. 1: External Interrupt 7 enabled. External Interrupt 7 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). Reserved. External Interrupt 5 enable bit. 0: External Interrupt 5 disabled. 1: External Interrupt 5 enabled. External Interrupt 5 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). Rev. A | Page 49 of 190 UG-868 Bit(s) 3 Bit Name IRQ4EN [2:0] IRQ4MDE ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description External Interrupt 4 enable bit. 0: External Interrupt 4 disabled. 1: External Interrupt 4 enabled. External Interrupt 4 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). Reset 0x0 Access RW 0x0 RW Reset 0x0 0x0 Access RW 0x0 RW Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW RW RW External Interrupt Configuration Register 2 Address: 0x40002428, Reset: 0x0000, Name: EI2CFG Table 58. Bit Descriptions for EI2CFG Bit(s) [15:4] 3 Bit Name Reserved IRQ8EN [2:0] IRQ8MDE Description Reserved External Interrupt 8 enable bit. 0: External Interrupt 8 disabled. 1: External Interrupt 8 enabled. External Interrupt 8 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). External Interrupt Clear Register Address: 0x40002430, Reset: 0x0000, Name: EICLR Table 59. Bit Descriptions for EICLR Bit(s) [15:9] 8 7 6 5 4 3 2 1 0 Bit Name RESERVED IRQ8 IRQ7 RESERVED IRQ5 IRQ4 RESERVED IRQ2 IRQ1 IRQ0 Description Reserved. External Interrupt 8. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. External Interrupt 7. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. Reserved. External Interrupt 5. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. External Interrupt 4. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. Reserved. External Interrupt 2. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. External Interrupt 1. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. External Interrupt 0. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. Rev. A | Page 50 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 LOW VOLTAGE ANALOG DIE INTERRUPT CONFIGURATION Two interrupt lines are available between the low voltage analog die and the interrupt controller on the digital die. These two interrupt lines are the outputs of two multiplexers of multiple interrupt sources from the low voltage analog die. The full list of interrupt sources from the low voltage analog die are as follows: • • • • • • • • ADC software conversion complete interrupt, which is asserted at the end of an ADC conversion when this interrupt source is enabled. ADC sequencer complete interrupt, which is the interrupt asserted by the ADC sequencer. Analog comparator interrupt. If the input signal is outside the selected threshold, this interrupt is asserted. Digital comparator interrupt. If the ADC result is outside the selected threshold, this interrupt is asserted. IDAC thermal shutdown interrupt. IDAC external reference resistor status interrupt. Read error correction and checking (ECC) interrupt source. ECC is available on the interface between the digital and analog die. If a read error occurs (for example, an error on the ADC result), this interrupt is asserted. Write ECC interrupt source. If the ECC returns an error on a value written to the low voltage die, this interrupt is asserted. Low Voltage Die Interrupt 1 is more flexible than Low Voltage Die Interrupt 0. There are two key differences. Low Voltage Die Interrupt 1 allows all seven different interrupt sources as configured by INTSEL[7:0] to be enabled. In the interrupt handler, the Low Voltage Die Interrupt 1 interrupt source can be determined by the INTSTA register. Low Voltage Die Interrupt 0 allows only one of the possible seven interrupt sources selected by INTSEL[15:8] to be enabled at a given time. The INTSTA register is not valid for Low Voltage Interrupt 0. To clear an interrupt, set the appropriate bit in the INTCLR register. Note that there is a delay period required after writing to INTCLR before the associated status bit in the INTSTA register is updated. If polling is used of the INTSTA register, the following example code can be used: pADI_LV_INT->INTCLR = 0x1; // Clear Irq source delay(10); ucLVIrqStatus = pADI_LV_INT->INTSTA; // Simple delay routine void delay (long int length) { while (length >0) length--; } REGISTER SUMMARY: LOW VOLTAGE DIE INTERRUPTS Table 60. Low Voltage Die Interrupts Register Summary Address 0x40083004 0x40083008 0x4008300C Name INTCLR INTSEL INTSTA Description Interrupt clear register Interrupt mask register Interrupt status register Rev. A | Page 51 of 190 Reset 0x0000 0x0000 0x0000 Access W RW R UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER DETAILS: LOW VOLTAGE DIE INTERRUPTS Interrupt Clear Register Address: 0x40083004, Reset: 0x0000, Name: INTCLR Table 61. Bit Descriptions for INTCLR Bit(s) 7 6 5 4 3 2 1 0 Bit Name CLR_WRECC_ERR CLR_RDECC_ERR CLR_IDAC_EXTRESLOW CLR_IDAC_TSHUT CLR_ACOMP CLR_DCOMP CLR_ADC_SEQ CLR_ADC_SOFTCONV Description Write 1 to this bit to clear the write ECC error interrupt flag. Write 1 to this bit to clear the read ECC error interrupt flag. Write 1 to this bit to clear the IDAC EXTRESLOW interrupt flag. Write 1 to this bit to clear the IDAC TSHUT interrupt flag. Write 1 to this bit to clear the analog compare interrupt flag. Write 1 to this bit to clear the digital compare interrupt flag. Write 1 to this bit to clear the ADC sequence conversion interrupt flag. Write 1 to this bit to clear the ADC software conversion interrupt flag. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access W W W W W W W W Interrupt Mask Register Address: 0x40083008, Reset: 0x0000, Name: INTSEL Table 62. Bit Descriptions for INTSEL Bit(s) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name SEL_WRECC_ERR_0 SEL_RDECC_ERR_0 SLE_IDAC_EXTRESLOW_0 SEL_IDAC_TSHUT_0 SEL_ACOMP_0 SEL_DCOMP_0 SEL_ADC_SEQ_0 SEL_ADC_SOFTCONV_0 SEL_WRECC_ERR_1 SEL_RDECC_ERR_1 SLE_IDAC_EXTRESLOW_1 SEL_IDAC_TSHUT_1 SEL_ACOMP_1 SEL_DCOMP_1 SEL_ADC_SEQ_1 SEL_ADC_SOFTCONV_1 Description Write 1 to this bit to enable write ECC error interrupt for Interrupt 0. Write 1 to this bit to enable read ECC error interrupt for Interrupt 0. Write 1 to this bit to enable IDAC EXTRESLOW interrupt for Interrupt 0. Write 1 to this bit to enable IDAC TSHUT interrupt for Interrupt 0. Write 1 to this bit to enable analog comparator interrupt for Interrupt 0. Write 1 to this bit to enable digital comparator interrupt for Interrupt 0. Write 1 to this bit to enable ADC sequence conversion interrupt for Interrupt 0. Write 1 to this bit to enable ADC software conversion interrupt for Interrupt 0. Write 1 to this bit to enable write ECC error interrupt for Interrupt 1. Write 1 to this bit to enable read ECC error interrupt for Interrupt 1. Write 1 to this bit to enable IDAC EXTRESLOW interrupt for Interrupt 1. Write 1 to this bit to enable IDAC TSHUT interrupt for Interrupt 1. Write 1 to this bit to enable analog comparator interrupt for Interrupt 1. Write 1 to this bit to enable digital comparator interrupt for Interrupt 1. Write 1 to this bit to enable ADC sequence conversion interrupt for Interrupt 1. Write 1 to this bit to enable ADC software conversion interrupt for Interrupt 1. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Interrupt Status Register Address: 0x4008300C, Reset: 0x0000, Name: INTSTA Table 63. Bit Descriptions for INTSTA Bit(s) 7 6 5 4 3 2 1 0 Bit Name WRECC_ERR RDECC_ERR IDAC_EXTRESLOW IDAC_TSHUT ACOMP DCOMP ADC_SEQ ADC_SOFTCONV Description Write data ECC error interrupt status Read data ECC error interrupt status IDAC EXTRESLOW interrupt status IDAC temperature thermal shutdown interrupt status Analog comparator interrupt status Digital comparator interrupt status ADC sequence interrupt status ADC software conversion interrupt status Rev. A | Page 52 of 190 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 RESET RESET FEATURES There are four kinds of resets: • • • • External reset Power-on reset Watchdog timeout Software system reset RESET OPERATION The software system reset is provided as part of the Cortex-M3 processor. To generate a software system reset, the NVIC_SystemReset() function must be called and this effectively writes 0x05FA to the top 16 bits of an AIRCR NVIC register. This function, along with other useful functions, are defined in the CMSIS header files that are shipped with the tools from third party vendors. The NVIC_SystemReset() function is defined in the core_cm3.h file. Analog peripherals have the option of maintaining their state after a software or watchdog reset. This function is enabled by default. It can be disabled using the LVRST register. Note that while debugging, the software tools generally only issue a software reset; therefore, an external reset is needed to return registers to their default values. The GPIO pins and PLA also have the option of maintaining their state after a software or watchdog reset. By default, this function is enabled. Writing a value of 0x1 to RSTCFG configures the GPIO pins and PLA to reset after a software or watchdog reset. Before writing to this register, 0x2009 must be written to RSTKEY followed by 0x0426. After the two keys are written to RSTKEY, RSTCFG must be immediately written. The RSTSTA register stores the cause for the reset until it is cleared by writing the RSTSTA register. RSTSTA can be used during a reset exception service routine to identify the source of the reset. The watchdog timer is enabled by default after a reset. The default timeout period is approximately 32 seconds. User code must disable the watchdog timer at the start of user code when debugging or if the watchdog timer is not required. pADI_WDT->T3CON = 0x00; // Disable watchdog timer Table 64. Device Reset Implications Reset SWRST WDRST External Reset Pin POR 1 Reset External Pins to Default State Yes/No1 Yes/No1 Yes Yes Execute Kernel Yes Yes Yes Yes Impact Reset All MMRs Except RSTSTA Yes/No1 Yes/No1 Yes Yes Reset All Peripherals Yes/No1 Yes/No1 Yes Yes GPIOs, PLA, and analog peripherals have the option of retaining their output state during a watchdog or software reset. Rev. A | Page 53 of 190 Valid SRAM Yes Yes Yes No RSTSTA After Reset Event RSTSTA[3] = 1 RSTSTA[2] = 1 RSTSTA[1] = 1 RSTSTA[0] = 1 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: RESET Table 65. Reset Register Summary Address 0x40002408 0x4000240C 0x40002440 0x40082C34 Name RSTCFG RSTKEY RSTSTA LVRST Description Reset configuration Key protection for RSTCFG Reset status Low voltage die reset configuration Reset 0x0000 0x0000 0x0000 0x0000 Access RW RW RW RW REGISTER DETAILS: RESET Reset Configuration Register Address: 0x40002408, Reset: 0x0000, Name: RSTCFG Table 66. Bit Descriptions for RSTCFG Bit(s) 0 Bit Name GPIO_PLA_RETAIN Description GPIO/PLA retain their status after watchdog or software reset. 1: GPIO/PLA do not retain status after watchdog or software reset. 0: GPIO/PLA retain status after watchdog or software reset. Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 0x0 Access R RW1C 0x0 RW1C 0x0 0x0 RW1C RW1C Reset 0x0 0x0 Access R RW Key Protection for RSTCFG Register Address: 0x4000240C, Reset: 0x0000, Name: RSTKEY Table 67. Bit Descriptions for RSTKEY Bit(s) [15:0] Bit Name RSTKEY Description Reset configuration key register. The RSTCFG register is key protected. Two writes to the key are necessary to change the value in the RSTCFG register: first 0x2009, then 0x0426. The RSTCFG register must then be written to. A write to any other register on the APB bus before writing to RSTCFG returns the protection to the lock state. Reset Status Register Address: 0x40002440, Reset: 0x0000, Name: RSTSTA Table 68. Bit Descriptions for RSTSTA Bit(s) [15:4] 3 Bit Name RESERVED SWRST 2 WDRST 1 0 EXTRST POR Description Reserved. Software reset. Set automatically to 1 when the Cortex-M3 system reset is generated. Cleared by writing 1 to the bit. Watchdog timeout. Set automatically to 1 when a watchdog timeout occurs. Cleared by writing 1 to the bit. External reset. Set automatically to 1 when an external reset occurs. Cleared by writing 1 to the bit. Power-on reset. Set automatically when a power-on reset occurs. Cleared by writing one to the bit. Low Voltage Die Reset Configuration Register Address: 0x40082C34, Reset: 0x0000, Name: LVRST Table 69. Bit Descriptions for LVRST Bit(s) [15:1] 0 Bit Name RESERVED RETAIN Description Reserved. Low voltage die retains status after watchdog or software reset. 0: low voltage die retains status after watchdog or software reset. 1: low voltage die does not retain status after watchdog or software reset. Rev. A | Page 54 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DIRECT MEMORY ACCESS (DMA) CONTROLLER DMA FEATURES The ADuCM320i/ADuCM322/ADuCM322i provide 14 dedicated and independent DMA channels. There are two programmable priority levels for each DMA channel. Each priority level arbitrates using a fixed priority that is determined by the DMA channel number. Channels with lower numbers have higher priority. For example, SPI0 transmit has the highest priority, and the next highest is the SPI0 receive. Each DMA channel can access a primary and/or alternate channel control structure. Multiple DMA transfer types are supported: • • • Memory to memory Memory to peripheral Peripheral to memory DMA OVERVIEW DMA provides high speed data transfer between peripherals and memory. Data can be moved quickly by DMA without any processor actions, which keeps processor resources free for other operations. The DMA controller has 14 channels in total. The 14 channels are dedicated to managing DMA requests from specific peripherals. Channels are assigned as shown in Table 70. Table 70. DMA Channel Assignment Channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Peripheral SPI0 Tx SPI0 Rx SPI1 Tx SPI1 Rx UART Tx UART Rx I2C0 slave Tx I2C0 slave Rx I2C0 master I2C1 slave Tx I2C1 slave Rx I2C1 master ADC Flash The channels are connected to dedicated hardware DMA requests; a software trigger is also supported on each channel. This configuration is done by software. Each DMA channel has a programmable priority level: default or high. Within a priority level, arbitration is performed using a fixed priority that is determined by the DMA channel number. Channels with lower numbers have higher priority. For example, SPI0 transmit has the highest priority, and the next highest is the SPI0 receive. The DMA controller supports multiple DMA transfer data widths: independent source and destination transfer size (byte, half word, and word). Source and destination addresses must be aligned on the data size. The DMA controller supports peripheral to memory, memory to peripheral, and memory to memory transfers and access to flash or SRAM as source and destination. DMA OPERATION The DMA controller performs direct memory transfer by sharing the system bus with the Cortex-M3 processor. The DMA request may stall the processor access to the system bus for some bus cycles when the processor and DMA are targeting the same destination (memory or peripheral). Rev. A | Page 55 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DMA INTERRUPTS An interrupt can be produced for each DMA channel when a transfer is complete. Separate interrupt enable bits are available in the NVIC for each of the DMA channels. The DMA controller fetches channel control data structures located in the SRAM memory to perform data transfers. When enabled to use DMA operation, the DMA capable peripherals request the DMA controller for transfer. At the end of the programmed number of DMA transfers for a channel, the DMA controller generates an interrupt corresponding to that channel. This interrupt indicates the completion of the DMA transfer. DMA PRIORITY The number and priority level determines the priority of a channel. Each channel can have two priority levels: default or high. All channels at high priority level have higher priority than all channels at default priority level. At the same priority level, a channel with a lower channel number has higher priority than a channel with a higher channel number. The DMA channel priority levels can be changed by writing into the appropriate bit in the DMAPRISET register. CHANNEL CONTROL DATA STRUCTURE Every channel has two control data structures associated with it: primary and alternate. For simple transfer modes, the DMA controller uses either the primary or the alternate data structure. For more complex data transfer modes, such as ping-pong or scatter-gather, the DMA controller uses both the primary and alternate data structures. Each control data structure (primary or alternate) occupies four 32-bit locations in the memory, as shown in Table 71. The entire channel control data structure is shown in Table 72. Table 71. Channel Control Data Structure Offset 0x00 0x04 0x08 0x0C Name SRC_END_PTR DST_END_PTR CHNL_CFG Reserved Description Source end pointer Destination end pointer Control data configuration Reserved Before the controller can perform a DMA transfer, the data structure related to the DMA channel must be programmed at the designated location in system memory, SRAM. • • • The source end pointer memory location contains the end address of the source data. The destination end pointer memory location contains the end address of the destination data. The control data configuration memory location contains the channel configuration control data. The programming determines the source and destination data size, number of transfers, and the number of arbitrations. Table 72. Memory Map of Primary and Alternate DMA Structures Channel Channel 13 … Channel 1 Channel 0 Primary Structures Register Description Offset Address Reserved; set to 0 0x0DC Control 0x0D8 Destination end pointer 0x0D4 Source end pointer 0x0D0 … … Reserved; set to 0 0x01C Control 0x018 Destination end pointer 0x014 Source end pointer 0x010 Reserved; set to 0 0x00C Control 0x008 Destination end pointer 0x004 Source end pointer 0x000 Alternate Structures Register Description Offset Address Reserved; set to 0 0x1DC Control 0x1D8 Destination end pointer 0x1D4 Source end pointer 0x1D0 … … Reserved; set to 0 0x11C Control 0x118 Destination end pointer 0x114 Source end pointer 0x110 Reserved; set to 0 0x10C Control 0x108 Destination end pointer 0x104 Source end pointer 0x100 The user must define DMA structures in their source code, as shown in the examples in the Example Code: Define DMA Structures section. After the structure has been defined, its start address must be assigned to the DMA base address pointer register, DMAPDBPTR. Each register for each DMA channel is then at the offset address, as specified in Table 72, plus the value in the DMAPDBPTR register. Rev. A | Page 56 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Example Code: Define DMA Structures To define DMA structures, use the following code: memset(dmaChanDesc,0x0,sizeof(dmaChanDesc)); // Set up the DMA base address pointer register. uiBasPtr = (unsigned int)&dmaChanDesc; // Set up the DMA base pointer. pADI_DMA->DMACFG = 1; // Enable DMA controller pADI_DMA->DMAPDBPTR = uiBasPtr; CONTROL DATA CONFIGURATION For each DMA transfer, the CHNL_CFG memory location provides the control information for the DMA transfer to the controller. Table 73. Control Data Configuration Bit(s) [31:30] Name DST_INC [29:28] DST_SIZE [27:26] SRC_INC Description Destination address increment. The address increment depends on the source data width as follows: Source Data Width DST_INC Destination Address Increment Byte 00 Byte. 01 Half word. 10 Word. 11 No increment. Address remains set to the value that the DST_END_PTR memory location contains. Half Word 00 Reserved. 01 Half word. 10 Word. 11 No increment. Address remains set to the value that the DST_END_PTR memory location contains. Word 00 Reserved. 01 Reserved. 10 Word. 11 No increment. Address remains set to the value that the DST_END_PTR memory location contains. Size of the destination data. Must match SRC_SIZE. 00: byte. 01: half word. 10: word. 11: reserved. Source address increment. The address increment depends on the source data width as follows: Source Data Width DST_INC Source Address Increment Byte 00 Byte. 01 Half word. 10 Word. 11 No increment. Address remains set to the value that the SRC_END_PTR memory location contains. Half Word 00 Reserved. 01 Half word. 10 Word. 11 No increment. Address remains set to the value that the SRC_END_PTR memory location contains. Word 00 Reserved. 01 Reserved. 10 Word. 11 No increment. Address remains set to the value that the SRC_END_PTR memory location contains. Rev. A | Page 57 of 190 UG-868 Bit(s) [25:24] Name SRC_SIZE [23:18] [17:14] Reserved R_POWER [13:4] N_MINUS_1 3 [2:0] Reserved CYCLE_CTRL ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description Size of the source data. 00: byte. 01: half word. 10: word. 11: reserved. Undefined. Write as 0. Set these bits to control how many DMA transfers can occur before the controller rearbitrates. Must be set to 0000 for all DMA transfers involving peripherals. Note that the operation of the DMA is indeterminate if a value other than 0000 is programmed in this location for DMA transfers involving peripherals. The number of configured transfers minus 1 for that channel. The 10-bit value indicates the number of DMA transfers (not the total number of bytes) minus one. The possible values are 0x000: 1 DMA transfer. 0x001: 2 DMA transfers. 0x002: 3 DMA transfers. … 0x3FF: 1024 DMA transfers. Undefined. Write as 0. The transfer types of the DMA cycle. 000: stop (invalid). 001: basic. 010: autorequest. 011: ping-pong. 100: memory scatter-gather primary. 101: memory scatter-gather alternate. 110: peripheral scatter-gather primary. 111: peripheral scatter-gather alternate. During the DMA transfer process, but before arbitration, CHNL_CFG is written back to system memory with the N_MINUS_1 field changed to reflect the number of transfers yet to be completed. When the DMA cycle is complete, the CYCLE_CTRL bits are made invalid to indicate the completion of the transfer. DMA TRANSFER TYPES (CHNL_CFG[2:0]) The DMA controller supports five types of DMA transfers. The various types are selected by programming the appropriate values into the CYCLE_CTRL bits (Bits[2:0]) in the CHNL_CFG location of the control data structure. Invalid (CHNL_CFG[2:0] = 000) CHNL_CFG[2:0] = 000 means no DMA transfer is enabled for the channel. After the controller completes a DMA cycle, it sets the cycle type to invalid to prevent it from repeating the same DMA cycle. Basic (CHNL_ CFG[2:0] = 001) In basic mode, the controller can be configured to use either the primary or alternate data structure. The peripheral must present a request for every data transfer. After the channel is enabled, when the controller receives a request, it performs the following operations: 1. 2. 3. The controller performs a transfer. If the number of transfers remaining is zero, the flow continues at Step 3. The controller arbitrates. a. If a higher priority channel is requesting service, the controller services that channel. b. If the peripheral or software signals a request to the controller, the controller continues at Step 1. At the end of the transfer, the controller generates the corresponding DMA channel interrupt in the NVIC Rev. A | Page 58 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Autorequest (CHNL_CFG[2:0] = 010) When the controller operates in autorequest mode, it is only necessary for the controller to receive a single request to enable it to complete the entire DMA cycle. This allows a large data transfer to occur without significantly increasing the latency for servicing higher priority requests or requiring multiple requests from the processor or peripheral. This mode is very useful for a memory to memory copy application. Autorequest is not suitable for peripheral use, except for the ADC sequencer mode, where a number of peripheral operations need to be completed. In this mode, the controller can be configured to use either the primary or alternate data structure. After the channel is enabled, when the controller receives a request, it performs the following operations: 1. 2. 3. The controller performs min(2R_POWER, N) transfers for the channel, where R_POWER is Bits[17:14] of the control data configuration register, and N is the number of transfers. If the number of transfers remaining is zero, the flow continues at Step 3. A request for the channel is automatically generated. The controller arbitrates. If the channel has the highest priority, the DMA cycle continues at Step 1. At the end of the transfer, the controller generates an interrupt for the corresponding DMA channel. Ping-Pong (CHNL_CFG[2:0] = 011) In ping-pong mode, the controller performs a DMA cycle using one of the data structures and then performs a DMA cycle using the other data structure. The controller continues to alternate between using the primary and alternate data structures until it reads a data structure that is invalid, or the host processor disables the channel. This mode is useful for transferring data from peripheral to memory using different buffers in the memory. In a typical application, the host must configure both primary and alternate data structures before starting the transfer. As the transfer progresses, the host can subsequently configure primary or alternate control data structures in the interrupt service routine when the corresponding transfer ends. The DMA controller interrupts the processor after the completion of transfers associated with each control data structure. The individual transfers using either the primary or alternate control data structure work the same as a basic DMA transfer. Memory Scatter-Gather (CHNL_CFG[2:0] = 100 or 101) In memory scatter-gather mode, the controller must be configured to use both the primary and alternate data structures. The controller uses the primary data structure to program the control configuration for the alternate data structure. The alternate data structure is used for actual data transfers, which are similar to an autorequest DMA transfer. The controller arbitrates after every primary transfer. The controller needs only one request to complete the entire transfer. This mode is used when performing multiple memory to memory copy tasks. The processor can configure all of the tasks simultaneously and does not need to intervene in between each task. The controller generates the corresponding DMA channel interrupt in the NVIC when the entire scatter-gather transaction completes using a basic cycle. In this mode, the controller receives an initial request and then performs four DMA transfers using the primary data structure to program the control structure of the alternate data structure. After this transfer completes, the controller starts a DMA cycle using the alternate data structure. After the cycle completes, the controller performs another four DMA transfers using the primary data structure. The controller continues to alternate between using the primary and alternate data structures until the processor configures the alternate data structure for a basic cycle, or the DMA reads an invalid data structure. Table 74 lists the fields of the CHNL_CFG memory location for the primary data structure, which must be programmed with constant values for the memory scatter-gather mode. Table 74. CHNL_CFG for Primary Data Structure in Memory Scatter-Gather Mode, CHNL_CFG[2:0] = 100 Bit(s) [31:30] [29:28] [27:26] [25:24] [23:18] [17:14] [13: 4] 3 [2:0] Name DST_INC DST_SIZE SRC_INC SRC_SIZE Reserved R_POWER N_MINUS_1 Reserved CYCLE_CTRL Description 10: configures the controller to use word increments for the address. 10: configures the controller to use word transfers. 10: configures the controller to use word increments for the address. 10: configures the controller to use word transfers. Undefined. Write as 0. 0010: indicates that the DMA controller is to perform four transfers. Configures the controller to perform N DMA transfers, where N is a multiple of 4. Undefined. Write as 0. 100: configures the controller to perform a memory scatter-gather DMA cycle. Rev. A | Page 59 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Peripheral Scatter-Gather (CHNL_CFG[2:0] = 110 or 111) In peripheral scatter-gather mode, the controller must be configured to use both the primary and alternate data structure. The controller uses the primary data structure to program the control structure of the alternate data structure. The alternate data structure is used for actual data transfers, and each transfer takes place using the alternate data structure with a basic DMA transfer. The controller does not arbitrate after every primary transfer. This mode is used when there are multiple peripheral-to-memory DMA tasks to be performed. The Cortex-M3 can configure all of the tasks simultaneously and does not need to intervene in between each task. This mode is very similar to memory scatter-gather mode except for arbitration and request requirements. The controller generates the corresponding DMA channel interrupt in the NVIC when the entire scatter-gather transaction completes using a basic cycle. In peripheral scatter-gather mode, the controller receives an initial request from a peripheral and then performs four DMA transfers using the primary data structure to program the alternate control data structure. The controller then immediately starts a DMA cycle using the alternate data structure without rearbitrating. After this cycle completes, the controller rearbitrates, and if it receives a request from the peripheral that has the highest priority, it performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure without rearbitrating. The controller continues to alternate between using the primary and alternate data structures until the processor configures the alternate data structure for a basic cycle, or the DMA reads an invalid data structure. Table 75 lists the fields of the CHNL_CFG memory location for the primary data structure, which must be programmed with constant values for the peripheral scatter-gather mode. Table 75. CHNL_CFG for Primary Data Structure in Peripheral Scatter-Gather Mode, CHNL_CFG[2:0] = 110 Bit(s) [31:30] [29:28] [27:26] [25:24] [23:18] [17:14] [13: 4] 3 [2:0] Name DST_INC DST_SIZE SRC_INC SRC_SIZE Reserved R_POWER N_MINUS_1 Reserved CYCLE_CTRL Description 10: configures the controller to use word increments for the address. 10: configures the controller to use word transfers. 10: configures the controller to use word increments for the address. 10: configures the controller to use word transfers. Undefined. Write as 0. 0010: indicates that the DMA controller performed four transfers without rearbitration. Configures the controller to perform N DMA transfers, where N is a multiple of 4. Undefined. Write as 0. 110: configures the controller to perform a memory scatter-gather DMA cycle. ADDRESS CALCULATION The DMA controller calculates the source read address based on the content of SRC_END_PTR, the source address increment setting in CHNL_CFG, and the current value of N_MINUS_1 (CHNL_CFG[13:4]). Similarly, the destination write address is calculated based on the content of DST_END_PTR, the destination address increment setting in CHNL_CFG, and the current value of N_MINUS_1 (CHNL_CFG[13:4]). Source Read Address = SRC_END_PTR − (N_MINUS_1 << (SRC_INC)) for SRC_INC = 0, 1, 2 Source Read Address = SRC_END_PTR for SRC_INC = 3 Destination Write Address = DST_END_PTR − (N_MINUS_1 << (DST_INC)) for DST_INC = 0, 1, 2 Destination Write Address = DST_END_PTR for DST_INC = 3 where N_MINUS_1 is the number of configured transfers minus 1 for that channel. ABORTING DMA TRANSFERS It is possible to abort a DMA transfer that is in progress by writing to the bit in the DMAENCLR register corresponding to the channel that needs to be aborted. Do not set DMACFG = 0 because this can corrupt the DMA structures. Rev. A | Page 60 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER SUMMARY: DMA Table 76. DMA Register Summary Address 0x40010000 0x40010004 0x40010008 0x4001000C 0x40010014 0x40010020 0x40010024 0x40010028 0x4001002C 0x40010030 0x40010034 0x40010038 0x4001003C 0x4001004C 0x40010800 0x40010804 Name DMASTA DMACFG DMAPDBPTR DMAADBPTR DMASWREQ DMARMSKSET DMARMSKCLR DMAENSET DMAENCLR DMAALTSET DMAALTCLR DMAPRISET DMAPRICLR DMAERRCLR DMABSSET DMABSCLR Description DMA status DMA configuration DMA channel primary control data base pointer DMA channel alternate control data base pointer DMA channel software request DMA channel request mask set DMA channel request mask clear DMA channel enable set DMA channel enable clear DMA channel primary-alternate set DMA channel primary-alternate clear DMA channel priority set DMA channel priority clear DMA per channel bus error DMA channel bytes swap enable set DMA channel bytes swap enable clear Reset 0x000F0000 0x00000000 0x00000000 0x00000100 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 RW R W RW R W RW W RW W RW W RW W RW RW W REGISTER DETAILS: DMA DMA Status Register Address: 0x40010000, Reset: 0x000F0000, Name: DMASTA Table 77. Bit Descriptions for DMASTA Bit(s) [31:21] [20:16] Bit Name RESERVED CHNLSM1 [15:8] [7:4] RESERVED STATE [3:1] 0 RESERVED MENABLE Description Reserved. Number of available DMA channels minus 1. Number of available DMA channels minus one. With 8 channels available, the register reads back 0x07. Reserved. Undefined. Current state of DMA controller. Current state of the DMA control state machine. Provides insight into the operation performed by the DMA at the time this register is read. 0000: idle. 0001: reading channel controller data. 0010: reading source data end pointer. 0011: reading destination end pointer. 0100: reading source data. 0101: writing destination data. 0110: waiting for DMA request to clear. 0111: writing channel controller data. 1000: stalled. 1001: done. 1010: peripheral scatter-gather transition. 1011: undefined. ... 1111: undefined. Reserved. Undefined. Enable status of the controller. 0: controller is disabled. 1: controller is enabled. Rev. A | Page 61 of 190 Reset 0x0 0xF Access R R 0x0 0x0 R R 0x0 0x0 R R UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DMA Configuration Register Address: 0x40010004, Reset: 0x00000000, Name: DMACFG Table 78. Bit Descriptions for DMACFG Bit(s) [31:1] 0 Bit Name RESERVED MENABLE Description Reserved. Undefined. Controller enable. 0: disable controller. 1: enable controller. Reset 0x0 0x0 Access W W DMA Channel Primary Control Data Base Pointer Register Address: 0x40010008, Reset: 0x00000000, Name: DMAPDBPTR The DMAPDBPTR register must be programmed to point to the primary channel control base pointer in the system memory. The amount of system memory that must be assigned to the DMA controller depends on the number of DMA channels used and whether the alternate channel control data structure is used. This register cannot be read when the DMA controller is in the reset state. Table 79. Bit Descriptions for DMAPDBPTR Bit(s) [31:0] Bit Name CTRLBASEPTR Description Pointer to the base address of the primary data structure. 5 + log(2) M LSBs are reserved and must be written 0. M is the number of channels. Reset 0x0 Access RW DMA Channel Alternate Control Data Base Pointer Register Address: 0x4001000C, Reset: 0x00000100, Name: DMAADBPTR The DMAADBPTR read only register returns the base address of the alternate channel control data structure. This register removes the necessity for application software to calculate the base address of the alternate data structure. This register cannot be read when the DMA controller is in the reset state. Table 80. Bit Descriptions for DMAADBPTR Bit(s) [31:0] Bit Name ALTCBPTR Description Base address of the alternate data structure Reset 0x100 Access R DMA Channel Software Request Register Address: 0x40010014, Reset: 0x00000000, Name: DMASWREQ The DMASWREQ register enables the generation of software DMA request. Each bit of the register represents the corresponding channel number in the DMA controller. M is the number of DMA channels. Table 81. Bit Descriptions for DMASWREQ Bit(s) [31:14] [13:0] Bit Name RESERVED CHSWREQ Description Reserved. Generate software request. Set the appropriate bit to generate a software DMA request on the corresponding DMA channel. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M – 1. When written: Bit [C] = 0: does not create a DMA request for Channel C. Bit [C] = 1: generates a DMA request for Channel C. These bits are automatically cleared by the hardware after the corresponding software request completes. Rev. A | Page 62 of 190 Reset 0x0 0x0 Access W W ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DMA Channel Request Mask Set Register Address: 0x40010020, Reset: 0x00000000, Name: DMARMSKSET Table 82. Bit Descriptions for DMARMSKSET Bit(s) [31:14] [13:0] Bit Name RESERVED CHREQMSET Description Reserved. Reserved, reads back 0. Mask requests from DMA channels. This register disables DMA requests from peripherals. Each bit of the register represents the corresponding channel number in the DMA controller. Set the appropriate bit to mask the request from the corresponding DMA channel. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M – 1. When read: Bit [C] = 0: requests are enabled for Channel C. Bit [C] = 1: requests are disabled for Channel C. When written: Bit [C] = 0: no effect. Use the DMARMSKCLR register to enable DMA requests. Bit [C] = 1: disables peripheral associated with Channel C from generating DMA requests. Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R W DMA Channel Request Mask Clear Register Address: 0x40010024, Reset: 0x00000000, Name: DMARMSKCLR Table 83. Bit Descriptions for DMARMSKCLR Bit(s) [31:14] [13:0] Bit Name RESERVED CHREQMCLR Description Reserved. Clear CHREQMSET bits in DMARMSKSET. This register enables DMA requests from peripherals by clearing the mask set in DMARMSKSET register. Each bit of the register represents the corresponding channel number in the DMA controller. Set the appropriate bit to clear the corresponding CHREQMSET bit in DMARMSKSET register. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M – 1. When written: Bit [C] = 0: no effect. Use the DMARMSKSET register to disable DMA requests. Bit [C] = 1: enables peripheral associated with Channel C to generate DMA requests. DMA Channel Enable Set Register Address: 0x40010028, Reset: 0x00000000, Name: DMAENSET Table 84. Bit Descriptions for DMAENSET Bit(s) [31:14] [13:0] Bit Name RESERVED CHENSET Description Reserved. Enable DMA channels. This register allows for the enabling of DMA channels. Reading the register returns the enable status of the channels. Each bit of the register represents the corresponding channel number in the DMA controller. Set the appropriate bit to enable the corresponding channel. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M – 1. When read: Bit [C] = 0: Channel C is disabled. Bit [C] = 1: Channel C is enabled. When written: Bit [C] = 0: no effect. Use the DMAENCLR register to disable the channel. Bit [C] = 1: enables Channel C. Rev. A | Page 63 of 190 Reset 0x0 0x0 Access R RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DMA Channel Enable Clear Register Address: 0x4001002C, Reset: 0x00000000, Name: DMAENCLR Table 85. Bit Descriptions for DMAENCLR Bit(s) [31:14] [13:0] Bit Name RESERVED CHENCLR Description Reserved. Undefined. Disable DMA channels. This register allows for the disabling of DMA channels. Reading the register returns the enable status of the channels. Each bit of the register represents the corresponding channel number in the DMA controller. Note that the controller disables a channel automatically, by setting the appropriate bit, when it completes the DMA cycle. Set the appropriate bit to disable the corresponding channel. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M – 1. When written: Bit [C] = 0: no effect. Use the DMAENSET register to enable the channel. Bit [C] = 1: disables Channel C. Reset 0x0 0x0 Access R W DMA Channel Primary-Alternate Set Register Address: 0x40010030, Reset: 0x00000000, Name: DMAALTSET The DMAALTSET register enables the user to configure the appropriate DMA channel to use the alternate control data structure. Reading the register returns the status of which data structure is in use for the corresponding DMA channel. Each bit of the register represents the corresponding channel number in the DMA controller. Note that the DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scatter-gather, and peripheral scatter-gather transfers. Table 86. Bit Descriptions for DMAALTSET Bit(s) [31:14] [13:0] Bit Name RESERVED CHPRIALTSET Description Reserved. Undefined. Control structure status/select alternate structure. Returns the channel control data structure status, or selects the alternate data structure for the corresponding DMA channel. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M − 1. When read: Bit [C] = 0: DMA Channel C is using the primary data structure. Bit [C] = 1: DMA Channel C is using the alternate data structure. When written: Bit [C] = 0: no effect. Use the DMAALTCLR register to set Bit [C] to 0. Bit [C] = 1: selects the alternate data structure for Channel C. Reset 0x0 0x0 Access R RW DMA Channel Primary-Alternate Clear Register Address: 0x40010034, Reset: 0x00000000, Name: DMAALTCLR The DMAALTCLR write only register enables the user to configure the appropriate DMA channel to use the primary control data structure. Each bit of the register represents the corresponding channel number in the DMA controller. Note that the DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scatter-gather and peripheral scatter-gather transfers. Table 87. Bit Descriptions for DMAALTCLR Bit(s) [31:14] [13:0] Bit Name RESERVED CHPRIALTCLR Description Reserved. Undefined. Select primary data structure. Set the appropriate bit to select the primary data structure for the corresponding DMA channel. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M – 1. When written: Bit [C] = 0: no effect. Use the DMAALTSET register to select the alternate data structure. Bit [C] = 1: selects the primary data structure for Channel C. Rev. A | Page 64 of 190 Reset 0x0 0x0 Access R W ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DMA Channel Priority Set Register Address: 0x40010038, Reset: 0x00000000, Name: DMAPRISET Table 88. Bit Descriptions for DMAPRISET Bit(s) [31:14] [13:0] Bit Name RESERVED CHPRISET Description Reserved. Undefined. Configure channel for high priority. This register enables the user to you to configure a DMA channel to use the high priority level. Reading the register returns the status of the channel priority mask. Each bit of the register represents the corresponding channel number in the DMA controller. Returns the channel priority mask status, or sets the channel priority to high. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M − 1. When read: Bit [C] = 0: DMA Channel C is using the default priority level. Bit [C] = 1: DMA Channel C is using a high priority level. When written: Bit [C] = 0: no effect. Use the DMAPRICLR register to set Channel C to the default priority level. Bit [C] = 1: Channel C uses the high priority level. Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R W Reset 0x0 0x0 Access R RW1C DMA Channel Priority Clear Register Address: 0x4001003C, Reset: 0x00000000, Name: DMAPRICLR Table 89. Bit Descriptions for DMAPRICLR Bit(s) [31:14] [13:0] Bit Name RESERVED CHPRICLR Description Reserved. Undefined. Configure channel for default priority level. The DMAPRICLR write only register enables the user to configure a DMA channel to use the default priority level. Each bit of the register represents the corresponding channel number in the DMA controller. Set the appropriate bit to select the default priority level for the specified DMA channel. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M – 1. When written: Bit [C] = 0: no effect. Use the DMAPRISET register to set Channel C to the high priority level. Bit [C] = 1: Channel C uses the default priority level. DMA Per Channel Bus Error Register Address: 0x4001004C, Reset: 0x00000000, Name: DMAERRCLR Table 90. Bit Descriptions for DMAERRCLR Bit(s) [31:14] [13:0] Bit Name RESERVED ERRCLR Description Reserved. Undefined. Bus error status. This register is used to read and clear the DMA bus error status. The error status is set if the controller encountered a bus error while performing a transfer or when it reads an invalid descriptor (whose cycle control is 3'b000). If a bus error occurs or invalid cycle control is read on a channel, that channel is automatically disabled by the controller. The other channels are unaffected. Write one to clear bits. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M − 1. When read: Bit [C] = 0: no bus error/invalid cycle control occurred. Bit [C] = 1: a bus error/invalid cycle control is pending. When written: Bit [C] = 0: no effect. Bit [C] = 1: bit is cleared. Rev. A | Page 65 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DMA Channel Bytes Swap Enable Set Register Address: 0x40010800, Reset: 0x00000000, Name: DMABSSET Table 91. Bit Descriptions for DMABSSET Bit(s) [31:14] [13:0] Bit Name RESERVED CHBSWAPSET Description Reserved. Undefined. Byte swap status. This register is used to configure a DMA channel to use byte. Each bit of the register represents the corresponding channel number in the DMA controller. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M – 1. When read: Bit [C] = 0: Channel C byte swap is disabled. Bit [C] = 1: Channel C byte swap is enabled. When written: Bit [C] = 0: no effect. Use the DMABSCLR register to disable byte swap on Channel C. Bit [C] = 1: enables byte swap on Channel C. Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R W DMA Channel Bytes Swap Enable Clear Register Address: 0x40010804, Reset: 0x00000000, Name: DMABSCLR Table 92. Bit Descriptions for DMABSCLR Bit(s) [31:14] [13:0] Bit Name RESERVED CHBSWAPCLR Description Reserved. Undefined. Disable byte swap. The DMABSCLR write only register enables the user to configure a DMA channel to not use byte swapping and use the default operation. Each bit of the register represents the corresponding channel number in the DMA controller. Bit 0 corresponds to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M − 1. When written: Bit [C] = 0: no effect. Use the DMABSSET register to enable byte swap on Channel C. Bit [C] = 1: disables byte swap on Channel C. Rev. A | Page 66 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 FLASH CONTROLLER FLASH CONTROLLER FEATURES The flash controller provides 256 kB Flash/EE memory in two blocks of 128 kB each (Flash 0 and Flash 1), as well as 4 kB information space, which contains factory code. FLASH CONTROLLER OVERVIEW The flash controller supports read on one flash block and erase/write operation on the other block. Peripheral DMA support is also provided for flash keyhole-based write. A kernel is present in the information space. The flash controller supports buffered read, executing code from a 64-bit read while fetching the next 64 bits. There is a 32-bit interface for MMR access. Flash program and erase timing are controlled via the fixed 16 MHz reference clock. The keyhole is open for access, command fail, command complete status bits. A cache is provided to speed up execution. Commands The commands include the following: • • • • • • Write command: 64 bits per write. Page erase commands. Mass erase commands for each flash block. Generation of signatures for single or multiple pages. Command abort supported, which is possible by writing to command MMR or by a system interrupt. Keys required for running commands such as a mass erase and the test commands. Protection, Integrity Protection, integrity includes the following: • • • • • • • • Write/read protection for user space. Read and write protection for information space. Ability to lock the SW-DP interface. Automatic signature check of information space on reset. User signature check of user space and information space. 8-bit error checking and correcting (ECC). 1-bit ECC error correction. 1-bit ECC errors and 2-bit or greater ECC errors can be configured to generate a flash ECC interrupt or a system exception. FLASH CONTROLLER OPERATION User Space Flash blocks (Flash 0 and Flash 1) of 128 kB each are available for user code and data. Generally, this can be a 256 kB block, from 0 to 0x3FFFF, except that it is not possible to execute from one flash block while erasing or writing parts of the same block. The top 24 bytes of user space in each flash block are reserved for a signature, the user write protection pattern, and the user flash failure analysis key (USERFAAKEY). If the user tries to read a portion of memory that is not available, a bus error returns. If a user tries to write via keyhole access to a portion of memory that is not available, an appropriate error flag sets. Information Space Information space of Flash 0 and Flash 1 is located at Address 0x40000 to Address 0x40FFF and is divided up between kernel space, test space, and calibration space. Information space is reserved for use by Analog Devices. Upon a reset, the hardware forces the device to execute from the start of the information space to copy the calibration and configuration values to the appropriate MMRs. When the kernel completes, it passes code execution to the start of user code. The hardware automatically checks the integrity of the kernel after reset. In the event of a failure, FEESTA[13] is set, and the user code cannot run. This bit can be read only via a serial wire read if the serial wire interface is enabled. Rev. A | Page 67 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual The user can not access the kernel code. A user can read 16 bytes of Flash 0 information space at Address 0x407E8 to Address 0x407F7. These locations contain ManfID0, ManfID1, and the next eight bytes, which are reserved. ManfID0 and ManfID1 contain traceability information to uniquely identify every device sold. The top two bytes at 0x407f4 identify the silicon version and the kernel revision. The first hexadecimal digit in the two bytes translates to the silicon revision, with 0x1 being the first silicon and each future revision incrementing by 1. The next two hexadecimal digits are the ASCII encoded version of the kernel. Prerelease versions start at Y; after release, this changes to the ASCII character 0 and increments upwards if any changes are necessary. The fourth hexadecimal digit represents the kernel minor revision, which starts at 0xE and is decremented for every minor change to the kernel. For example, 0x159A translates as follows: 1 indicates first silicon, 59 indicates Kernel Revision Y in ASCII code, and A indicates Minor Revision A. There are also hardware registers that identify the version of each silicon die. For more information, see the Silicon Identification section. ADDRESS 0x40FFF INFORMATION SPACE FLASH 1 0x40800 0x407FF INFORMATION SPACE FLASH 0 0x40000 0x3FFFF USER SPACE FLASH 1: 128kB 0x20000 USER SPACE FLASH 0: 128kB 0x00000 13437-112 0x1FFFF Figure 14. Information and User Space Memory Map Keys Write the 0xF123F456 value to the FEEKEY register to run certain user commands, to write to certain locations in flash, or to enable write access to the user setup register (FEECON1). Rev. A | Page 68 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 FLASH MEMORY OPERATION Keyhole Access Writing to flash is through keyhole access. Keyhole access consists of • • • Flash address Flash data MMR Command MMR Reserved Flash Locations The top six words of each flash block have special functionality, as listed in Figure 15 and Figure 16. Therefore, normal code or data cannot be placed in this space. SIGNATURE. ADDRESS 0x3FFFC. RESERVED. ADDRESS: 0x3FFF8. USER READ PROTECTION KEY 1. ADDRESS: 0x3FFF4. USER WRITE PROTECTION PATTERN 1 [31:0]. ADDRESS: 0x3FFF0. REST OF THE UPPERMOST PAGE IN USER SPACE. 13437-113 RESERVED. ADDRESS: 0x3FFEC. USERFAAKEY1 [31:0]. ADDRESS: 0x3FFE8. Figure 15. Uppermost Page in User Flash 1 Space SIGNATURE. ADDRESS 0x1FFFC. RESERVED. ADDRESS: 0x1FFF8. USER READ PROTECTION KEY 1. ADDRESS: 0x1FFF4. USER WRITE PROTECTION PATTERN 1 [31:0]. ADDRESS: 0x1FFF0. REST OF THE UPPERMOST PAGE IN USER SPACE. 13437-114 RESERVED. ADDRESS: 0x1FFEC. USERFAAKEY1 [31:0]. ADDRESS: 0x1FFE8. Figure 16. Uppermost Page in User Flash 0 Space Writing to Flash Each write programs 64 bits of data. To write to a flash location, the following sequence is required: 1. 2. 3. Write the address of the flash location to FEEFLADR. Write the 64 bits of data to FEEFLDATA0 and FEEFLDATA1. Write the write command to FEECMD. After the write command is given, the controller writes to flash. CMDDONE (FEESTA[2]) indicates that the command is completed. In addition, note that a 64-bit location can be written to only once unless it is erased again. Erasing Flash User code can call three flash erase commands: • • • MASSERASE0: this command erases the entire user Flash 0 memory. After entering the user protection key into FEEKEY, write the MASSERASE0 command to FEECMD. MASSERASE1: this command erases the entire user Flash 1 memory. After entering the user protection key into FEEKEY, write the MASSERASE1 command to FEECMD. PAGEERASE: this command erases 2 kB of flash. The page is selected by FEEADR0. After entering the user protection key into FEEKEY, load FEEADR0 with the page address to be erased. Finally, write the page erase command to FEECMD. CMDDONE (FEESTA[2]) indicates that the command is completed. During a page or mass erase sequence, the flash controller and flash block consume extra current for the duration of the flash erase sequence. Rev. A | Page 69 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Signature The signature checks the integrity of the flash device. The signature is calculated from the lowest 32-bit word to the second highest 32-bit word in the selected block. The signature is a 24-bit cyclic redundancy check (CRC) with an initial value of 0xFFFFFF and the following polynomial: x24 + x23 + x6 + x5 + x + 1 The data is pushed into the CRC polynomial until the specified end address is reached. A block can be a single page or multiple pages. The hardware assumes that the signature for a block is stored in the upper four bytes of the most significant page of a block; therefore, these 32 bits are not included when generating the signature. While the signature is being computed for a particular flash, all other accesses to the same flash are stalled. Note that FEEADR0/FEEADR1 addresses are byte addresses but only pages need to be identified because the lower 11 bits are ignored by the hardware. In addition, ensure that the addresses written to FEEADR0/FEEADR1 are both either in Flash 0 or Flash 1. The following code illustrates how the CRC is calculated, and how to compare it to the result of the sign command. int FeeCrc(int iLen,int *aiData) { int i1,i2,iCrc; iCrc = 0xffffffff; //Seed value. for(i1=0; i1<iLen; i1++) //Starting at lowest address. { for(i2=31; i2>=0; i2--) //MSB first. { iCrc <<= 1; //Left shift. if((*(aiData+i1))&(1<<i2)) iCrc ^= 0x00800063; if(iCrc&(1<<24)) //^= Polynomial. iCrc ^= 0x00800063; } } return(iCrc&0x00ffffff); //Return 24 bits. } int FeeSign(unsigned long ulStartAddr, unsigned long ulEndAddr) { if((pADI_FEE->FEESTA&1)!=0) return 0; pADI_FEE->FEEADR0 = ulStartAddr; pADI_FEE->FEEADR1 = ulEndAddr; pADI_FEE->FEEKEY = 0xF123F456; pADI_FEE->FEECMD = 0x2; return 1; } FeeSign(0x00800,0x00900); //SIGN for page1. if(FeeCrc(511,(int *)0x00800) != pADI_FEE->FEESIG) FlagError(); Else FlagSuccess(); Rev. A | Page 70 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Error Checking and Correcting (ECC) Error Handling During the signature check, the ECC is checked on each 72-bit flash read (64-bit flash read and 8-bit ECC). If errors are corrected by the ECC, the ERRDETECTED flag in the status register, FEESTA, is set after the signature check is completed. If errors are detected and cannot be corrected by ECC, the ERRDETECTED flag in FEESTA is set. A signature check is treated as a failure when the computed signature is not equal to the stored signature. During a read of the flash, if there is a 1-bit error, the error is corrected by default but neither ECC interrupts nor system exceptions are enabled. If interrupts or system exceptions are not enabled by the user, the appropriate flags in FEESTA are not set in the event of an ECC error. A 1-bit ECC interrupt or system exception can be enabled in the ECC enable/disable register (FEEECCCONFIG), if required. If the appropriate interrupts or system exceptions are enabled in the FEEECCCONFIG register, the appropriate flags are set in the status register. If there is a 2-bit ECC error and if interrupts or system exceptions are enabled in the FEEECCCONFIG register, an error is issued by the controller. If the appropriate interrupts or system exceptions are enabled in the FEEECCCONFIG register, the appropriate flags are set in the status register. An ECC error is signaled by the ECC error detection/correction hardware when a flash location is read. Depending on from which flash (Flash 0/Flash 1) the read happens, the appropriate flags are set in the status register (ECCREADERRFLSH0, ECCREADERRFLSH1, and so on). Note that 1-bit errors corrected meet full data sheet specifications. If a system exception is enabled, the device vectors to a hard fault or bus fault in the event of an ECC error. See the SHCSR register in the Cortex-M3 and Fault Management section to enable a bus fault. ECC Error During Read Two separate ECCREADERRFLSHx flags are present in the status register: FEESTA[10:9] and FEESTA[12:11] for Flash 0 and Flash 1. If the interrupt is configured to generate when an ECC error occurs, the address at which the error is detected is available for the user. If a system exception is configured, the BFAR register contains the address for which the ECC error is detected ECC Error During Execution of Sign Command If there is an ECC error during signature check, registers do not update. After the command is complete, the ECCERRCMD flags in FEESTA[8:7] are updated. No interrupt or system exception generates. Flash Protection Three types of flash protection are implemented: • • • Key protection User read protection User write protection Flash Protection: Key Protection Some of the flash controller MMRs are key protected to avoid accidental writes to these MMRs. The user key is 0xF123F456. This key must be entered to run certain user commands, to write to certain locations in flash, or to enable write access to FEECON1. Once entered, the key remains asserted unless a command is written to FEECMD. When the command starts, the key clears automatically. If this key is entered to enable write access to FEECON1 or to enable writes to certain locations in flash, it must be cleared by the user code afterwards. To clear the key, write any value other than 0xF123F456 to FEEKEY. Flash Protection: User Read Protection Disabling serial wire access provides user space read protection. A user can disable serial wire debug access by writing 0 to Bit 0 of the FEECON1 register. Serial wire debug access is disabled while the kernel is running; otherwise, serial wire debug access may prevent the kernel from running to completion. When the kernel exits to user code, it enables serial wire access unless either of the keys at 0x3FFF4 or 0x1FFF4 is set to 0x0000003A, which means that the device is always read protected after either key is in place and that no debug access can occur. This protection also prevents page erases or programming to flash via the I2C downloader protocol to prevent removing the protection. The I2C downloader mass erase command still works to completely erase all user code. If a block does not contain protection, it is erased before the block containing the protection to ensure that both blocks are erased before the protection is removed. Rev. A | Page 71 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Flash Protection: User Write Protection User write protection is provided to prevent accidental writes or page erases to pages in user space and to protect blocks of user code when programming extra code to flash. If a write or erase of a protected location is detected, the flash controller generates an interrupt if the command error/complete interrupt is enabled. The write protection for each block is stored near the top of each block. The top four bytes are for a signature, and the next eight bytes are reserved. The next 32-bit flash location contains the protection pattern, which is copied to FEEPRO0 and FEEPRO1 at startup, with each bit protecting a block of 4 kB of flash. If no protection is specified, protection can be set by writing to FEEPRO0 and FEEPRO1. This mechanism also prevents erasing or writing to protected pages via the I2C downloader. Flash Failure Analysis Key It may be necessary to perform failure analysis on devices that are returned by a user even though read protection is enabled. A method is provided to allow failure analysis of protected memory by a user flash failure analysis key (USERFAAKEY). The user must set the key as two 32-bit values near the top of each user flash block. Supplying this key to Analog Devices allows access to user code for debug purposes. See Figure 15 and Figure 16 for details. Flash Controller Abort Commands (erase, sign, or mass verify) and writes can be aborted upon receipt of an interrupt, as listed in Table 53. Aborts are also possible by writing an abort command to the FEECMD register. However, if flash is being programmed and the routine controlling the programming is in flash, it is not possible to use the abort command to abort the cycle because instructions cannot be read. Therefore, the ability to abort a cycle on the assertion of any system interrupt is provided. The FEEAENx register enables aborts upon receipt of an interrupt. Each bit in the FEEAENx registers corresponds to an interrupt listed in Table 53. Setting a bit in the FEEAENx register enables the corresponding interrupt to abort flash operations. When a command or write is aborted via a system interrupt, FEESTA[5:4] indicates an abort (FEESTA[5:4] = 11). Depending on the state that a write cycle is in when the abort asserts, the write cycle may or may not complete. If the write or erase cycle did not complete successfully, a fail status of the aborted can be read in the status register. If an immediate response to an interrupt is required during an erase or program cycle, the interrupt service routine and the interrupt vector table must be moved to SRAM or must be in the other flash block for the duration of the cycle. If the DMA engine is set up to write a block of data to flash, an interrupt can be set up to abort the current write; however, the DMA engine starts the next write immediately. The interrupt causing the abort stays asserted so that there is a number of aborted write cycles in this case before the processor gains access to flash. When an abort is triggered by an interrupt, all commands are repeatedly aborted until the appropriate FEEAENx bit is cleared or the interrupt source is cleared. CPU Execution Speed The basic execution speed of the ADuCM320i/ADuCM322/ADuCM322i is one CPU cycle per clock cycle. The default clock speed is 80 MHz. This speed is achieved when running from cache; however, it is slightly less when running directly from flash. An average execution speed of over 70 MHz is typically achieved for typical C code. For more details, and how to achieve full speed operation for critical code, see the AN-1322 Application Note, ADuCM320 Code Execution Speed. Rev. A | Page 72 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Memory Cache A memory cache is provided on-chip to speed up program execution. The instruction cache is configured and set up by default. If the user writes code to the flash, the user must perform a chip reset to ensure that the old cached data is cleared and that the new code can be executed. If a chip reset is not possible, the following code can be used to clear the cache. The instruction cache must be 0x10001 or (CACHESETUP_IINIT_EN|CACHESETUP_DINIT_EN) to clear both the instruction and data cache. int FeeCacheClr(int iCache) { unsigned int ui1; ui1 = pADI_FEE->CACHESETUP; pADI_FEE->CACHEKEY = 0xf123f456; pADI_FEE->CACHESETUP = ui1|(iCache&(CACHESETUP_IINIT_EN|CACHESETUP_DINIT_EN)); while(pADI_FEE->CACHESTAT&(iCache&(CACHESETUP_IINIT_EN|CACHESETUP_DINIT_EN))); pADI_FEE->CACHEKEY = 0xf123f456; pADI_FEE->CACHESETUP = ui1; return 1; } Most programming tools clear the cache before programming code to a device. Rev. A | Page 73 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Flash DMA Support DMA can support flash controller operations. This feature is software configurable. The two flash blocks are independent; the user can continue executing from one block while programming another block. The DMA is useful for this because the core only needs to initiate the write to flash and then the DMA finishes executing the code in the background, triggering an interrupt when the operation is complete. Use the following code for writing to flash when using the DMA: void FLASHDMAINIT(void) { pADI_DMA->DMACFG = 0x1; // Enable DMA mode in DMA controller Dma_Init(); NVIC_EnableIRQ(DMA_FLASH_IRQn); // Enable Flash DMA IRQ FLASHDMAWRITE(uxFlashData, 64); pADI_DMA->DMAENSET = 0x2000; pADI_FEE->FEEFLADR = uiAdr; pADI_FEE->FEEKEY = 0xF123F456; pADI_FEE->FEECON1 |= (FEECON1_KHDMA_EN); // Enable Flash DMA mode } void FLASHDMAWRITE (unsigned char * pucTX_DMA, unsigned int iNumVals) { DmaDesc Desc; // Common configuration of all the descriptors used here Desc.ctrlCfg.Bits.cycle_ctrl = DMA_BASIC; desc.ctrlcfg.bits.next_useburst = 0x0; desc.ctrlcfg.bits.r_power = 1; desc.ctrlcfg.bits.src_prot_ctrl = 0x0; Desc.ctrlCfg.Bits.dst_prot_ctrl = 0x0; Desc.ctrlCfg.Bits.src_size = DMA_SIZE_WORD; Desc.ctrlCfg.Bits.dst_size = DMA_SIZE_WORD; // TX Primary Descriptor Desc.srcEndPtr = (unsigned int)(pucTX_DMA+ 4*(iNumVals - 0x1) ); Desc.destEndPtr = (unsigned int)&(pADI_FEE->FEEFLDATA1); Desc.ctrlCfg.Bits.n_minus_1 = iNumVals - 0x1; Desc.ctrlCfg.Bits.src_inc = DMA_SRCINC_WORD; Desc.ctrlCfg.Bits.dst_inc = DMA_DSTINC_NO; *Dma_GetDescriptor(Flash_C) = Desc; } void DMA_Flsh_Int_Handler() { pADI_FEE->FEEKEY = 0xF123F456; pADI_FEE->FEECON1 &= (~FEECON1_KHDMA_EN); // Disable Flash DMA mode dma_done = 1; } Rev. A | Page 74 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Flash Controller Performance and Command Duration All flash functions are slower than the CPU execution speed. The CPU Execution Speed section details the slight penalty of slower flash reads. All other flash operations are significantly slower, as detailed in Table 93. Table 93. Typical Flash Execution Times Operation Write 64-Bit Location Mass Erase One Flash Block Page Erase One Page Sign Flash 0/Flash 1 Information Space Sign Flash 0/Flash 1 User Space Time (Typical) 75 µs 18 ms 18 ms 33 µs 2.1 ms Comments 512 cycles, 2 kB 32k cycles, 128 kB In general, use these timings as a guideline only; software must use the flash status information or the interrupt system to detect when flash operations are complete. If one of the operations in Table 93 executes in the same block as the block from which the CPU fetches instructions, the CPU stalls until the operation is complete. REGISTER SUMMARY: FLASH CONTROLLER Table 94. Flash Controller Register Summary Address 0x40018000 0x40018004 0x40018008 0x4001800C 0x40018010 0x40018014 0x40018018 0x4001801C 0x40018020 0x40018028 0x4001802C 0x40018034 0x40018038 0x40018040 0x40018048 0x4001804C 0x40018064 0x40018074 0x40018078 0x400180C0 0x400180C4 0x400180C8 Name FEESTA FEECON0 FEECMD FEEFLADR FEEFLDATA0 FEEFLDATA1 FEEADR0 FEEADR1 FEEKEY FEEPRO0 FEEPRO1 FEESIG FEECON1 FEEWRADDRA FEEAEN0 FEEAEN1 FEEECCCONFIG FEEECCADDR0 FEEECCADDR1 CACHESTAT CACHESETUP CACHEKEY Description Status register Command control register: interrupt enable register Command register Flash address keyhole register Flash data register, keyhole interface lower 32 bits Flash data register, keyhole interface upper 32 bits Lower page address register Upper page address register Key register Write protection register for Flash 0 Write protection register for Flash 1 Upper halfword of signature User setup register Write abort address register Interrupt abort enable register, Interrupt 31 to Interrupt 0 Interrupt abort enable register, Interrupt 54 to Interrupt 32 ECC enable/disable, error response Flash 0 ECC error address Flash 1 ECC error address Cache status register Cache setup register Cache key register Rev. A | Page 75 of 190 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0xFFFFFFFF 0x0000000X 0x0000001X 0x0000000X 0x00000000 0x000000 0x00000000 0x00000000 0x00000000 0x2 0x2 0x0 RW R RW RW RW RW RW RW RW W RW RW R RW R RW RW RW R R R RW W UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER DETAILS: FLASH CONTROLLER Status Register Address: 0x40018000, Reset: 0x00000000, Name: FEESTA Table 95. Bit Descriptions for FEESTA Bits [31:29] [28:27] Bit Name RESERVED ECCREADERRIBUS [26:25] ECCREADERRDBUS [24:22] ECCCOUNTFLASH1 [21:20] [19:17] RESERVED ECCCOUNTFLASH 0 [16:14] ECCERRSIGN 13 SIGNERR [12:11] ECCREADERRFLSH1 Description Reserved Instruction bus ECC error during a read of flash if a system exception is enabled. Bits Name Description 00 NOERR No error. Successful read from Flash 1. 01 ERRDETECTED 2-bit error detected in one or more flash locations during a read from Flash 1. The errors are not corrected. 10 ERRCORRECTED 1-bit error detected for one flash location while during read from Flash 1. The error is corrected. 11 ERR1BIT_2BIT During the read, 1-bit error and 2-bit errors are detected in Flash 1. Data bus ECC error during a read of flash if a system exception is enabled, Bits Name Description 00 NOERR No error. Successful read from Flash 1. 01 ERRDETECTED 2-bit error detected in one or more flash locations during a read from Flash 1. The errors are not corrected. 10 ERRCORRECTED 1-bit error detected for one flash location while during read from Flash 1. The error is corrected. 11 ERR1BIT_2Bit During the read, 1-bit error and 2-bit errors are detected in Flash 1. This is a 3-bit counter that reflects the number of 1-bit ECC read errors in Flash 1 after FEESTA[12:11] = 0x2 and before FEESTA is read. This counter does not count on ECC 2-bit errors. The counter is cleared when FEESTA is read by the user. Reserved. This is a 3-bit counter that reflects the number of 1-bit ECC read errors in Flash 0 after FEESTA[10:9] = 0x2 and before FEESTA is read. This counter does not count on ECC 2-bit errors. The counter is cleared when FEESTA is read by the user. ECC error during initial signature check. Bits Name Description 00 NOERR No error. Successful flash read operation during initial signature check or page signature check. 01 ERRDETECTED During initial signature check, 2-bit errors are detected and not corrected for at least one flash location. 10 ERRCORRECTED 1-bit error is corrected for one flash location during a signature command. 11 ERR1BIT_2Bit During the initial signature command, 1-bit errors and 2-bit errors are detected on one or more flash locations. Information space signature check on reset error. After a reset, the flash controller automatically checks the information space signature. If the signature check fails, this bit is asserted. The user can check if this bit is set via serial wire only. User code does not execute if this bit is set. The bit is cleared if the correct signature is programmed to the most significant long word in the information space. ECC errors during a read of Flash 1 if interrupt is enabled. Bits Name Description 00 NOERR No error. Successful read from Flash 1. 01 ERRDETECTED 2-bit error detected in one or more flash locations during a read from Flash 1. The errors are not corrected. 10 ERRCORRECTED 1-bit error detected for one flash location while during read from Flash 1. The error is corrected. 11 ERR1BIT_2Bit During the read, 1-bit error and 2-bit errors are detected in Flash 1. Rev. A | Page 76 of 190 Reset 0x0 0x0 Access R RC 0x0 RC 0x0 R 0x0 0x0 R RC 0x0 R 0x0 R 0x0 RC ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bits [10:9] Bit Name ECCREADERRFLSH0 [8:7] ECCERRCMD 6 [5:4] RESERVED CMDRES 3 WRALMOSTDONE 2 CMDDONE 1 WRCLOSE 0 CMDBUSY Description ECC errors during read of Flash 0 if interrupt is enabled. Bits Name Description 00 NOERR No error. Successful read from Flash 0. 01 ERRDETECTED 2-bit error detected in one or more flash locations during a read from Flash 0. The errors are not corrected. 10 ERRCORRECTED 1-bit error detected for one flash location while during read from Flash 0. The error is corrected. 11 ERR1BIT_2Bit During the read, 1-bit error and 2-bit errors are detected in Flash 0. ECC errors during signature commands. Bits Name Description 00 NOERR No error. Successful flash read operation during the signature check. 01 ERRDETECTED 2-bit error detected in one or more flash locations during the signature command. The errors are not corrected. 10 ERRCORRECTED 1-bit error detected for one flash location while doing a signature check. The error is corrected. 11 ERR1BIT_2Bit During the signature command, 1-bit error and 2-bit errors are detected on one or more flash locations. Reserved. These two bits indicate the status of a command on completion or the status of a write. If multiple commands are executed or there are multiple writes without a read of the status register, the first error encountered is stored. Cleared to 0 when read. 00: successful completion of a command or a write. 01: attempted signcheck, write, or erase of a protected location. 10: read verify error. After an erase, the controller reads the corresponding word(s) to verify that the transaction completed successfully. If data read is not all Fs, this is the resulting status. If the sign command is executed and the resulting signature does not match the data in the upper 4 bytes of the upper page in a block, this is the resulting status. 11: indicates that a command or a write was aborted by an abort command or a system interrupt has caused an abort. Write almost complete, keyhole registers open for access. This bit flags the earliest point at which the flash controller data and address may be updated for the next command without affecting an active flash command operation. 0: cleared to 0 when read. 1: set to 1 when a write completes. This bit asserts when a command completes. If there are multiple commands, this status bit asserts after the first command completes and stays asserted until read. 0: cleared to 0 when read. 1: set to 1 when a command completes. This bit is asserted when the user has written all keyhole registers for flash write, and the controller has started the write. If this bit is high, all keyhole registers (FEEFLADR, FEEFLDATA0, FEEFLDATA1), except the command register (FEECMD), are closed for write. Command busy. This bit is asserted when the flash block is executing any command entered via the command register. Rev. A | Page 77 of 190 UG-868 Reset 0x0 Access RC 0x0 RC 0x0 0x0 R RC 0x0 RC 0x0 RC 0x0 R 0x0 R UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Command Control Register: Interrupt Enable Register Address: 0x40018004, Reset: 0x00000000, Name: FEECON0 Table 96. Bit Descriptions for FEECON0 Bit(s) [31:3] 2 Bit Name RESERVED IENERR 1 IWRALCOMP 0 IENCMD Description Returns 0 when read. Command fail interrupt enable. If this bit is set, an interrupt is generated when a command or flash write completes with an error status. 0: disable. 1: enable. Write almost complete interrupt enable. Returns 0 when read. 0: disable. 1: enable. Command complete interrupt enable. When set, an interrupt is generated when a command or flash write completes. 0: disable. 1: enable. Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access RW RW Command Register Address: 0x40018008, Reset: 0x00000000, Name: FEECMD Table 97. Bit Descriptions for FEECMD Bit(s) [31:5] [4:0] Bit Name RESERVED CMD Description Returns 0x0. Always returns 0 when read. 00000: IDLE. No command executed. 00001: PAGEERASE. Write the address of the page to be erased to the FEEADR0 register, then write this code to the FEECMD register, and the flash erases the page. When the erase has completed, the flash reads every location in the page to verify all words in the page are erased. If there is a read verify error, this error is indicated in the status register. To erase multiple pages, wait until a previous page erase has completed, check the status, then issue a command to start the next page erase. Before entering this command, 0xF123F456 must be written to the FEEKEY register. 00010: SIGN. Use this command to generate a signature for a block of data. The signature is generated on a page by page basis. To generate a signature, the address of the first page of the block is entered in the FEEADR0 register, the address of the last page is written to the FEEADR1 register, and then this code is written to the FEECMD register. When the command has completed the signature is available for reading in the sign register. The last four bytes of the last page in a block is reserved for storing the signature. Before entering this command, 0xF123F456 must be written to the FEEKEY register. 00100: WRITE. Use this command to write to the flash locations. This command needs a user key for writing into the write protection location and the user flash failure analysis key (USERFAAKEY) location. No key is required for other flash locations. This command takes the address and data from the FEEADR and FEEFLDATA keyhole registers. 00101: MASSERASE0. Erase all of Flash 0 user space. To enable this operation, 0xF123F456 must be written to the FEEKEY register (this is to prevent accidental erases). When the mass erase has completed, the controller reads every location to verify that all locations are 0xFFFFFFFFFFFFFFFF. If there is a read verify error, it is indicated in the status register. 00110: MASSERASE1. Erase all of Flash 1 user space. To enable this operation, 0xF123F456 must be written to the FEEKEY register (this is to prevent accidental erases). When the mass erase has completed, the controller reads every location to verify that all locations are 0xFFFFFFFFFFFFFFFF. If there is a read verify error, it is indicated in the status register. 01000: ABORT. If this command is issued, any command currently in progress is stopped. The status indicates command completed with an error status (FEESTA[5:4] = 0x3). Note that this is the only command that can be issued while another command is already in progress. This command can also be used to stop a write that may be in progress. If a write or erase is aborted, the flash timing is violated, and it is not possible to determine if the write or erase completed successfully. To enable this operation, 0xF123F456 must be written to the FEEKEY register (this is to prevent accidental aborts). All other combinations are reserved. Rev. A | Page 78 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Flash Address Keyhole Register Address: 0x4001800C, Reset: 0x00000000, Name: FEEFLADR Table 98. Bit Descriptions for FEEFLADR Bit(s) [31:19] [18:3] Bit Name RESERVED FLADDR [2:0] RESERVED Description Returns 0x0 if read. Memory mapped address for the flash location. Used to specify flash address for write command. The 3 LSBs always reads zero. Returns 0x0 if read. Reset 0x0 0x0 Access R RW 0x0 R Reset 0x0 Access RW Flash Data Register—Keyhole Interface Lower 32 Bits Address: 0x40018010, Reset: 0x00000000, Name: FEEFLDATA0 Table 99. Bit Descriptions for FEEFLDATA0 Bit(s) [31:0] Bit Name FLDATA0 Description FLDATA0 forms the lower 32 bits of the 64-bit data to be written to flash. Flash Data Register—Keyhole Interface Upper 32 Bits Address: 0x40018014, Reset: 0x00000000, Name: FEEFLDATA1 Table 100. Bit Descriptions for FEEFLDATA1 Bit(s) [31:0] Bit Name FLDATA1 Description FLDATA1 forms the upper 32 bits of the 64-bit data to be written to flash. Reset 0x0 Access RW Reset 0x0 0x0 Access RW RW 0x0 R Reset 0x0 0x0 Access RW RW 0x0 R Reset 0x0 Access W Lower Page Address Register Address: 0x40018018, Reset: 0x00000000, Name: FEEADR0 Table 101. Bit Descriptions for FEEADR0 Bit(s) [31:19] [18:11] Bit Name RESERVED PAGEADDR0 [10:0] RESERVED Description Return 0 when read. Used by SIGN and PAGEERASE commands for specifying page address. See the description of these commands in FEECMD (see Table 97). Reserved. Upper Page Address Register Address: 0x4001801C, Reset: 0x00000000, Name: FEEADR1 Table 102. Bit Descriptions for FEEADR1 Bit(s) [31:19] [18:11] Bit Name RESERVED PAGEADDR1 [10:0] RESERVED Description Return 0 when read. Used by SIGN command for specifying the endpage address. See the description of this command in FEECMD (see Table 97). Reserved. Key Register Address: 0x40018020, Reset: 0x00000000, Name: FEEKEY Table 103. Bit Descriptions for FEEKEY Bit(s) [31:0] Bit Name KEY Description Enter 0xF123F456 to allow key protected operations. Returns 0x00 if read. Rev. A | Page 79 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Write Protection Register for Flash 0 Address: 0x40018028, Reset: 0xFFFFFFFF, Name: FEEPRO0 Table 104. Bit Descriptions for FEEPRO0 Bit(s) [31:0] Bit Name WRPROT0 Description Write protection for Flash 0, 32 bits. Each bit corresponds to a 4 kB flash section. Writing 0 to a bit protects the corresponding section of flash. This register is read only if the write protection in flash has been programmed. Reset 0xFFFFFFFF Access RW Reset 0xFFFFFFFF Access RW Reset 0x0 0xx Access R R Write Protection Register for Flash 1 Address: 0x4001802C, Reset: 0xFFFFFFFF, Name: FEEPRO1 Table 105. Bit Descriptions for FEEPRO1 Bit(s) [31:0] Bit Name WRPROT1 Description Write protection for Flash 1, 32 bits. Each bit corresponds to a 4 kB flash section. Writing 0 to a bit protects the corresponding section of flash. This register is read only if the write protection in flash has been programmed. Upper Halfword of Signature Register Address: 0x40018034, Reset: 0x0000000X, Name: FEESIG Table 106. Bit Descriptions for FEESIG Bit(s) [31:24] [23:0] Bit Name RESERVED SIGN Description Returns 0x0 if read 24-bit signature User Setup Register Address: 0x40018038, Reset: 0x0000001X, Name: FEECON1 This register is key protected; therefore, the key (0xF123F456) must be entered in FEEKEY. After writing to FEECON1, a value other than 0xF123F456 must be written again to FEEKEY to reassert the key protection. Table 107. Bit Descriptions for FEECON1 Bit(s) [31:5] 4 3 Bit Name RESERVED MDIO SWAP 2 INCR 1 KHDMA 0 DBG Description Returns 0 when read. MDIO mode. This bit is for read only purpose. If this bit is set, MDIO address swapping can be enabled. Swap program code for MDIO mode. 0: disable address swap for User Space Flash 0 and User Space Flash 1. 1: enable address swap for User Space Flash 0 and User Space Flash 1. Auto-increment FEEFLAADR for non-DMA operation. 0: disable auto address increment. 1: enable auto address increment. Keyhole DMA enable. 0: disable DMA mode. 1: enable DMA mode. JTAG debug enable. If this bit is 1, access via the serial wire debug interface is enabled. If this bit is 0, access via the serial wire debug interface is disabled. The kernel set this bit to 1 when it has finished executing, thus enabling debug access to a user. 0: disable JTAG access. 1: enable JTAG access. Rev. A | Page 80 of 190 Reset 0x0 0x1 0xX Access R R RW 0x0 RW 0x0 RW 0xX RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Write Abort Address Register Address: 0x40018040, Reset: 0x0000000X, Name: FEEWRADDRA Table 108. Bit Descriptions for FEEWRADDRA Bit(s) [31:0] Bit Name WRABORTADDR Description If a write is aborted, this register contains the address of the location being written when the write was aborted. This register has the appropriate value if the command abort happened, which has to be read after the command is aborted, and before any other command is given. After reset, the value is random. Reset 0xx Access R Interrupt Abort Enable Register—Interrupt 31 to Interrupt 0 Address: 0x40018048, Reset: 0x00000000, Name: FEEAEN0 Table 109. Bit Descriptions for FEEAEN0 Bit(s) [31:0] Bit Name SYSIRQABORTEN Description Lower 32 bits of system interrupt abort enable. To allow a system interrupt to abort a command (write, erase, sign or mass verify), write a 1 to the appropriate bit in this register. Each bit corresponds to 1 interrupt listed in the interrupt vector table. Reset 0x0 Access RW Reset 0x0 Access RW Interrupt Abort Enable Register—Interrupt 54 to Interrupt 32 Address: 0x4001804C, Reset: 0x000000, Name: FEEAEN1 Table 110. Bit Descriptions for FEEAEN1 Bit(s) [22:0] Bit Name SYSIRQABORTEN Description Upper 23 bits of system interrupt abort enable. To allow a system interrupt to abort a command (write, erase, sign or mass verify), write a 1 to the appropriate bit in this register. Each bit corresponds to 1 interrupt listed in the interrupt vector table. ECC Enable/Disable, Error Response Register Address: 0x40018064, Reset: 0x00000000, Name: FEEECCCONFIG This register is key protected, so the key (0x5ECCACCE) must be entered in FEEKEY. After writing to FEECCCONFIG, the key is cleared. Table 111. Bit Descriptions for FEEECCCONFIG Bits [31:5] [4:3] Bit Name RESERVED ECCCMDINTEN [2:1] ECCCMDAHBEN 0 ECCDISABLE Description Reserved. Interrupt enabled (flash Interrupt) when an ECC error happens during a read. Bits Description 00 Interrupt is not generated if an ECC error occurs while reading from flash. 01 Interrupt enabled only if a 2-bit error is detected during a read from Flash 0 or Flash 1. 10 Interrupt enabled only if a 1-bit error is detected during a read from Flash 0 or Flash 1. 11 Interrupt enabled if either a 2-bit error or 1-bit error is detected during a read from Flash 0 or Flash 1. Generates a system exception (bus fault) when an ECC error happens during a read. Bits Description 00 Exception is not generated if an ECC error occurs while reading from flash. 01 Exception enabled only if a 2-bit error is detected during a read from Flash 0 or Flash 1. 10 Exception enabled only if a 1-bit error is detected during a read from Flash 0 or Flash 1. 11 Exception enabled if either a 2-bit error or 1-bit error is detected during a read from Flash 0 or Flash 1. Setting this bit to 1 disables ECC. When ECC is disabled, the ECC module is bypassed. When a read to a flash location is carried out, corresponding to the requested address, LSB 32-bit or MSB 32-bit raw data is returned to the bus. Rev. A | Page 81 of 190 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Flash 0 ECC Error Address Register Address: 0x40018074, Reset: 0x00000000, Name: FEEECCADDR0 Table 112. Bit Descriptions for FEEECCADDR0 Bits [31:19] [18:0] Bit Name RESERVED VALUE Description Reserved. This register has the address of Flash 0 for which the ECC error is detected. Reset 0x0 0x0 Access R R Reset 0x0 0x0 Access R R Flash 1 ECC Error Address Register Address: 0x40018078, Reset: 0x00000000, Name: FEEECCADDR1 Table 113. Bit Descriptions for FEEECCADDR1 Bits [31:19] [18:0] Bit Name RESERVED VALUE Description Reserved. This register has the address of Flash 0 for which the ECC error is detected. Cache Status Register Address: 0x400180C0, Reset: 0x00000002, Name: CACHESTAT Table 114. Bit Descriptions for CACHESTAT Bit(s) [31:20] 18 17 Bit Name RESERVED DLOCK DEN 16 DINIT [15:4] 2 RESERVED ILOCK 1 IEN 0 IINIT Description Reserved. This bit is set when the data cache is locked and cleared when the data cache is unlocked. If this bit is set, the data cache is enabled. When this bit is cleared, the data cache is disabled. This bit is also cleared when CACHESTAT[16] is set. It is set when the data cache memory initialization starts and clears when initialization is done. The data cache is disabled when this bit is set. Reserved. This bit is set when the instruction cache is locked. This bit is cleared when the instruction cache is unlocked. If this bit is set, the instruction cache is enabled. When this bit is cleared, the instruction cache is disabled, which is also cleared when CACHESTAT[0] is set. It is set when the instruction cache memory initialization starts and clears when the initialization is done. When this bit is set, the instruction cache is disabled. Reset 0x0 0x0 0x0 Access R R R 0x0 R 0x0 0x0 R R 0x1 R 0x0 R Reset 0x0 0x0 0x0 Access RW RW RW 0x0 RW 0x0 RW 0x0 0x0 0x0 0x0 RW RW RW RW Cache Setup Register Address: 0x400180C4, Reset: 0x00000002, Name: CACHESETUP This register is key protected; therefore, the key (0xF123F456) must be entered in CACHEKEY. Table 115. Bit Descriptions for CACHESETUP Bit(s) [31:20] 19 18 Bit Name RESERVED DWRBUF DLOCK 17 DEN 16 DINIT [15:5] 4 3 2 RESERVED IRDBUF IWRBUF ILOCK Description Reserved. If this bit is set, for every AHB access, hit from write buffer is not checked. If this bit is set, the data cache contents are locked. Any new misses are not replaced in the data cache. This bit is cleared when CACHESETUP[16] is set. If this bit set, the data cache is enabled for AHB accesses. If 0, the data cache is disabled, and all AHB accesses are via flash memory. This bit is cleared when CACHESETUP[16] is set. If this bit is set, the data cache contents are initialized to all zeros. This bit is cleared when the initialization starts. Reserved. If this bit is set, for every AHB access, hit from read buffer is not checked. If this bit is set, for every AHB access, hit from write buffer is not checked. If this bit is set, the instruction cache contents are locked. Any new misses are not replaced in the instruction cache. This bit is cleared when CACHESETUP[0] is set. Rev. A | Page 82 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 1 Bit Name IEN 0 IINIT Description If this bit set, the instruction cache is enabled for AHB accesses. If 0, the instruction cache is disabled, and all AHB accesses are via flash memory. This bit is cleared when CACHESETUP[0] is set. If this bit is set, the instruction cache contents are initialized to all zeros. This bit is cleared when the initialization starts. UG-868 Reset 0x1 Access RW 0x0 RW Reset 0x0 Access W Cache Key Register Address: 0x400180C8, Reset: 0x00000000, Name: CACHEKEY Table 116. Bit Descriptions for CACHEKEY Bit(s) [31:0] Bit Name KEY Description Cache key register. Enter 0xF123F456 to allow key protected operations. Returns 0x0 if read. The key is cleared automatically after writing to the setup register. Rev. A | Page 83 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual SILICON IDENTIFICATION The ADuCM320i/ADuCM322/ADuCM322i have two silicon die, and each die has a register that identifies the silicon. The CHIPID register contains the digital die silicon version in Bits[3:0] and the device identification in Bits[15:4]. The LVID register contains the low voltage die silicon version. SILICON IDENTIFICATION MEMORY MAPPED REGISTERS Table 117. Silicon ID Register Summary Address 0x40002024 0x40082C30 Name CHIPID LVID Description Digital die ID Low voltage die ID Reset 0x0562 0x0073 RW R R Reset 0x56 0x21 Access R R Reset 0x7 0x31 Access R DIGITAL DIE ID REGISTER Address: 0x40002024, Reset: 0x0561, Name: CHIPID Table 118. Bit Descriptions for CHIPID Bit(s) [15:4] [3:0] 1 Bit Name PARTID REV Description Digital die device identifier Digital die silicon revision number These values are based on initial released silicon. Previous/future revisions of silicon have a different reset value. LOW VOLTAGE DIE ID REGISTER Address: 0x40082C30, Reset: 0x0073, Name: LVID Table 119. Bit Descriptions for LVID Bit(s) [15:4] [3:0] 1 Bit Name LVID LVREV Description Low voltage die device identifier Low voltage die silicon revision number These values are based on initial released silicon. Previous/future revisions of silicon have a different reset value. Rev. A | Page 84 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DIGITAL INPUTS/OUTPUTS DIGITAL INPUTS/OUTPUTS FEATURES The ADuCM320i/ADuCM322/ADuCM322i feature multiple bidirectional general-purpose digital input/output (GPIO) pins. Most of the GPIO pins have multiple functions, configurable by user code. At power up, all but one of these pins are configured as GPIOs; one pin reflects the state of the POR. This pin can also be configured by user code to be used as a GPIO. On power-up, these pins are configured as inputs with their corresponding pull-up or pull-down disabled. There are five 8-bit wide ports; however, not all bits on some ports are accessible. Inaccessible bits must be ignored. DIGITAL INPUTS/OUTPUTS BLOCK DIAGRAM IOVDD OUTPUT ENABLE GPxOE OUTPUT DATA GPxOUT, GPxSET, GPxCLR, GPxTGL PULL-UP ENABLE GPxPUL GPIO INPUT ENABLE GPxIE 13437-430 INPUT DATA GPxIN Figure 17. GPIO Structure for Port 0 to Port 3 The pin circuit of Port 0 to Port 3 is shown in Figure 17. Port 4 and Port 5 are essentially the same; however, instead of the pull-ups, Port 4 and Port 5 have pull-downs to IOGND. DIGITAL INPUTS/OUTPUTS OVERVIEW The GPIOs are grouped into six ports: Port 0 to Port 5. Each GPIO can be configured as an input, output, or fully open circuit. In input mode, the internal pull-up/pull-down can be enabled by software. All input/output pins except P3.0 to P3.6 in MDIO mode are functional over the full supply range (IOVDD = 3.1 V to 3.6 V (maximum)), and the logic input voltages are specified as percentages of the supply as follows: VINL = 0.25 × IOVDD max VINH = 0.58 × IOVDD min The absolute maximum input voltage is IOVDD + 0.3 V. The typical leakage current of the GPIOs configured as input or open circuit is 50 nA per GPIO. When the ADuCM320i/ADuCM322/ADuCM322i enters a power saving mode, the GPIO pins retain their states. Note that in power saving mode, a driving peripheral cannot drive the pin, that is, if the UART is driving the pin upon entry to deep sleep, it is isolated from the pin and power is gated. Its state and control are restored upon wake-up. Inaccessible Bits Some of the bits of P2, P3, and P4 are not brought out of the package. The pin definitions in Table 120 indicate which are accessible. The inaccessible bits are still implemented. Therefore, the pull-ups/pull-downs for these bits must be disabled using the GPxPUL MMRs so that they do not waste power. Unused outputs must also be disabled using the GPxOE MMRs. These settings are the default at power up. P5.4 to P5.7 are not implemented at all. DIGITAL INPUTS/OUTPUTS OPERATION Each digital input/output is configured, read, and written independent of the other bits. General-Purpose Input Data (GPxIN) GPxIN contains the pin input levels if enabled as inputs by GPxIE. General-Purpose Output Data (GPxOUT) The values of GPxOUT are output on the GPIO pins when configured as outputs by GPxOE. Rev. A | Page 85 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Input/Output Data Out Enable (GPxOE) GPxOE enables the values of GPxOUT to be output on the GPIO pins. Input/Output Pull-Up Enable (GPxPUL) In input mode, GPxPUL enables/disables internal pull-ups/pull-downs. All Port 0 to Port 3 pins have internal pull-ups, and the Port 4 and Port 5 pins have pull-downs. The pull-ups/pull-downs are implemented as MOSFET transistors, with typical performance shown in Figure 18 and Figure 19. If a pin is configured as an output, the internal pull-up/pull-down is disabled even in open-drain mode. IPULL-UP CURRENT (µA) 80 60 40 20 0 ROUT RESISTANCE (mΩ) 50 40 30 20 0.5 1.0 1.5 2.0 2.5 3.0 3.5 13437-116 0 3.5 13437-117 10 VOUT (V) Figure 18. Typical P0 to P3 Pull-Up Characteristics CURRENT (µA) 0 IPULL-DOWN –20 –40 –60 –80 RESISTANCE (mΩ) 50 ROUT 40 30 20 10 0 0.5 1.0 1.5 2.0 2.5 3.0 VOUT (V) Figure 19. Typical P4 to P5 Pull-Down Characteristics Rev. A | Page 86 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Input/Output Data In Enable (GPxIE) GPxIE enables the GPIO pin input levels to be available in GPxIN. Open-Drain Enable (GPxODE) GPxODE configures pins in output mode to open-drain mode. For Port 0 to Port 3 in this mode, the outputs can sink current if the corresponding bit in GPxOUT[y] is low. If the bit in GPxOUT[y] is high, the pin is high impedance. For Port 4 and Port 5 in this mode, the outputs can source current if the corresponding bit in GPxOUT[y] is high. If the bit in GPxOUT[y] is low, the pin is high impedance. To enable a pin as an open-drain output, set the appropriate bits in GPxOEN and GPxODE. If a pin is configured as an output, the internal pull-up is disabled even in open-drain mode, regardless of GPxPUL[y]. If internal pull-ups are required in open drain mode, it is possible to configure the GPIOs in pseudo open-drain mode, by setting the corresponding bits of GPxOUT and GPxODE to 0b0 and the corresponding bit of GPxPUL to 0b1. To change between a low output and open drain high with a pull-up, the corresponding bit GPxOE can be changed from 0b1 to 0b0. Bit Set Bit set mode sets one or more GPIO data outputs without affecting other outputs within a port. Only the GPIO corresponding with the write data bit equal to 1 is set; the remaining GPIOs are unaffected. Bit Clear Bit clear mode clears one or more GPIO data outputs without affecting other outputs within a port. Only the GPIO corresponding with the write data bit equal to 1 is cleared; the remaining GPIOs are unaffected. Bit Toggle Bit toggle mode toggles one or more GPIO data outputs without affecting other outputs within a port. Only the GPIO corresponding to the write data bit equal to 1 is toggled; the remaining GPIOs are unaffected. Rev. A | Page 87 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DIGITAL PORT MULTIPLEX This block provides control over the GPIO functionality of specified pins because some of the pins offer the choice to work as a GPIO or to have other specific functions. Table 120. GPIO Multiplex Table GPIO GP0—GP0CON Controls These Bits P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 GP1—GP1CON Controls These Bits P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 GP2—GP2CON Controls These Bits P2.0 P2.11 P2.2 P2.3 P2.4 P2.51 P2.6 P2.7 Configuration Modes 10 00 01 GPIO (GP0CON[1:0] = 0x0) GPIO (GP0CON[3:2] = 0x0) GPIO (GP0CON[5:4] = 0x0) GPIO/IRQ0 (GP0CON[7:6] = 0x0) GPIO (GP0CON[9:8] = 0x0) GPIO (GP0CON[11:10] = 0x0) GPIO (GP0CON[13:12] = 0x0) GPIO (GP0CON[15:14] = 0x0) SPI0 SCLK (GP0CON[1:0] = 0x1) SPI0 MISO (GP0CON[3:2] = 0x1) SPI0 MOSI (GP0CON[5:4] = 0x1) SPI0 CS (GP0CON[7:6] = 0x1) I2C0 SCL (GP0CON[9:8] = 0x1) I2C0 SDA (GP0CON[11:10] = 0x1) I2C1 SCL (GP0CON[13:12] = 0x1) I2C1 SDA (GP0CON[15:14] = 0x1) GPIO (GP1CON[1:0] = 0x0) GPI0 (GP1CON[3:2] = 0x0) GPIO (GP1CON[5:4] = 0x0) GPIO (GP1CON[7:6] = 0x0) GPIO (GP1CON[9:8] = 0x0) GPIO (GP1CON[11:10] = 0x0) GPIO (GP1CON[13:12] = 0x0) GPIO/IRQ1 (GP1CON[15:14] = 0x0) UART SIN (GP1CON[1:0] = 0x1) UART SOUT (GP1CON[3:2] = 0x1) PWM0 (GP1CON[5:4] = 0x1) PWM1 (GP1CON[7:6] = 0x1) PWM2 (GP1CON[9:8] = 0x1) PWM3 (GP1CON[11:10] = 0x1) PWM4 (GP1CON[13:12] = 0x1) PWM5 (GP1CON[15:14] = 0x1) SPI1 SCLK (GP1CON[9:8] = 0x2) SPI1 MISO (GP1CON[11:10] = 0x2) SPI1 MOSI (GP1CON[13:12] = 0x2) SPI1 CS (GP1CON[15:14] = 0x2) PLAI[4] (GP1CON[1:0] = 0x3) PLAI[5] (GP1CON[3:2] = 0x3) PLAI[6] (GP1CON[5:4] = 0x3) PLAI[7] (GP1CON[7:6] = 0x3) PLAO[10] (GP1CON[9:8] = 0x3) PLAO[11] (GP1CON[11:10] = 0x3) PLAO[12] (GP1CON[13:12] = 0x3) PLAO[13] (GP1CON[15:14] = 0x3) GPIO/IRQ2 (GP2CON[1:0] = 0x0) PWMTRIP (GP2CON[1:0] = 0x1) PLACLK2 (GP2CON[1:0] = 0x2) PLAI[8] (GP2CON[1:0] = 0x3) CLKOUT (GP2CON[5:4] = 0x2) PLAI[10] (GP2CON[5:4] = 0x3) PWM6 (GP2CON[9:8] = 0x2) PLAO[18] GP2CON[9:8] = 0x3) GPIO/IRQ4 (GP2CON[5:4] = 0x0) GPIO/BM (GP2CON[7:6] = 0x0) GPIO/IRQ5 (GP2CON[9:8] = 0x0) ADCCONV (GP2CON[9:8] = 0x1) GPIO/IRQ7 (GP2CON[13:12] = 0x0) GPIO/IRQ8 (GP2CON[15:14] = 0x0) PLACLK0 (GP0CON[7:6] = 0x2) ECLKIN (GP1CON[1:0] = 0x2) PLACLK1 (GP1CON[3:2] = 0x2) 11 PLAI[0] (GP0CON[1:0] = 0x3) PLAI[1] (GP0CON[3:2] = 0x3) PLAI[2] (GP0CON[5:4] = 0x3) PLAI[3] (GP0CON[7:6] = 0x3) PLAO[2] (GP0CON[9:8] = 0x3) PLAO[3] (GP0CON[11:10] = 0x1) PLAO[4] (GP0CON[13:12] = 0x3) PLAO[5] (GP0CON[15:14] = 0x3) PLAO[20] (GP2CON[13:12] = 0x3) PLAO[21] (GP2CON[15:14] = 0x3) Rev. A | Page 88 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual GPIO GP3—GP3CON Controls These Bits P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 01 GPIO (GP3CON[1:0] = 0x0) GPIO (GP3CON[3:2] = 0x0) GPIO (GP3CON[5:4] = 0x0) GPIO (GP3CON[7:6] = 0x0) GPIO (GP3CON[9:8] = 0x0) GPIO (GP3CON[11:10] = 0x0) GPIO (GP3CON[15:14] = 0x0) PRTADDR0 (GP3CON[1:0] = 0x1) PRTADDR1 (GP3CON[3:2] = 0x1) PRTADDR2 (GP3CON[5:4] = 0x1) PRTADDR3 (GP3CON[7:6] = 0x1) PRTADDR4 (GP3CON[9:8] = 0x1) MCLK (GP3CON[11:10] = 0x1) MDIO (GP3CON[13:12] = 0x1) VDAC2 (GP3CON[15:14] = 0x1) GPIO (GP4CON[5:4] = 0x0) GPIO (GP4CON[7:6] = 0x0) GPIO (GP4CON[9:8] = 0x0) GPIO (GP4CON[11:10] = 0x0) GPIO (GP4CON[13:12] = 0x0) GPIO (GP4CON[15:14] = 0x0) AIN8 (GP4CON[5:4] = 0x1) AIN9 (GP4CON[7:6] = 0x1) AIN12 (GP4CON[9:8] = 0x1) AIN13 (GP4CON[11:10] = 0x1) AIN14 (GP4CON[13:12] = 0x1) AIN15 (GP4CON[15:14] = 0x1) GPIO (GP5CON[1:0] = 0x0) GPIO (GP5CON[3:2] = 0x0) GPIO (GP5CON[5:4] = 0x0) GPIO (GP5CON[7:6] = 0x0) VDAC3 (GP5CON[1:0] = 0x1) VDAC6 (GP5CON[3:2] = 0x1) VDAC7 (GP5CON[5:4] = 0x1) VDAC0 (GP5CON[7:6] = 0x1) P3.6 P3.72 GP4—GP4CON Controls These Bits P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 GP5—GP5CON Controls These Bits P5.02 P5.12 P5.22 P5.32 1 2 Configuration Modes 10 00 Not available as an external pin. Internal PLA elements connected to these pins can be used. Never configure this pin as an output if the associated VDAC output is enabled. Rev. A | Page 89 of 190 UG-868 11 PLAI[12] (GP3CON[1:0] = 0x3) PLAI[13] (GP3CON[3:2] = 0x3) PLAI[14] (GP3CON[5:4] = 0x3) PLAI[15] (GP3CON[7:6] = 0x3) PLAO[26] (GP3CON[9:8] = 0x3) PLAO[27] (GP3CON[11:10] = 0x3) PLAO[29] (GP3CON[15:14] = 0x3) UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: DIGITAL INPUT/OUTPUT Table 121. GPIO Register Summary Address 0x40020000 0x40020004 0x40020008 0x4002000C 0x40020010 0x40020014 0x40020018 0x4002001C 0x40020020 0x40020024 0x40020040 0x40020044 0x40020048 0x4002004C 0x40020050 0x40020054 0x40020058 0x4002005C 0x40020060 0x40020064 0x40020080 0x40020084 0x40020088 0x4002008C 0x40020090 0x40020094 0x40020098 0x4002009C 0x400200A0 0x400200A4 0x400200C0 0x400200C4 0x400200C8 0x400200CC 0x400200D0 0x400200D4 0x400200D8 0x400200DC 0x400200E0 0x400200E4 0x40020100 0x40020104 0x40020108 0x4002010C 0x40020110 0x40020114 0x40020118 0x4002011C 0x40020120 0x40020124 Name GP0CON GP0OE GP0PUL GP0IE GP0IN GP0OUT GP0SET GP0CLR GP0TGL GP0ODE GP1CON GP1OE GP1PUL GP1IE GP1IN GP1OUT GP1SET GP1CLR GP1TGL GP1ODE GP2CON GP2OE GP2PUL GP2IE GP2IN GP2OUT GP2SET GP2CLR GP2TGL GP2ODE GP3CON GP3OE GP3PUL GP3IE GP3IN GP3OUT GP3SET GP3CLR GP3TGL GP3ODE GP4CON GP4OE GP4PUL GP4IE GP4IN GP4OUT GP4SET GP4CLR GP4TGL GP4ODE Description GPIO Port 0 configuration GPIO Port 0 output enable GPIO Port 0 pull-up enable GPIO Port 0 input path enable GPIO Port 0 registered data input GPIO Port 0 data output GPIO Port 0 data out set GPIO Port 0 data out clear GPIO Port 0 pin toggle GPIO Port 0 open drain enable GPIO Port 1 configuration GPIO Port 1 output enable GPIO Port 1 pull-up enable GPIO Port 1 input path enable GPIO Port 1 registered data input GPIO Port 1 data output GPIO Port 1 data out set GPIO Port 1 data out clear GPIO Port 1 pin toggle GPIO Port 1 open drain enable GPIO Port 2 configuration GPIO Port 2 output enable GPIO Port 2 pull-up enable GPIO Port 2 input path enable GPIO Port 2 registered data input GPIO Port 2 data output GPIO Port 2 data out set GPIO Port 2 data out clear GPIO Port 2 pin toggle GPIO Port 2 open drain enable GPIO Port 3 configuration GPIO Port 3 output enable GPIO Port 3 pull-up enable GPIO Port 3 input path enable GPIO Port 3 registered data input GPIO Port 3 data output GPIO Port 3 data out set GPIO Port 3 data out clear GPIO Port 3 pin toggle GPIO Port 3 open drain enable GPIO Port 4 configuration GPIO Port 4 output enable GPIO Port 4 pull-down enable GPIO Port 4 input path enable GPIO Port 4 registered data input GPIO Port 4 data output GPIO Port 4 data out set GPIO Port 4 data out clear GPIO Port 4 pin toggle GPIO Port 4 open drain enable Rev. A | Page 90 of 190 Reset 0x0000 0x00 0x00 0xFF 0xXX 0x00 0x00 0x00 0x00 0x00 0x0000 0x00 0x00 0xFF 0xXX 0x00 0x00 0x00 0x00 0x00 0x0000 0x00 0x08 0xFF 0xXX 0x00 0x00 0x00 0x00 0x00 0x0000 0x00 0x00 0xFF 0xXX 0x00 0x00 0x00 0x00 0x00 0x0000 0x00 0x00 0xFF 0xXX 0x00 0x00 0x00 0x00 0x00 RW RW RW RW RW R RW W W W RW RW RW RW RW R RW W W W RW RW RW RW RW R RW W W W RW RW RW RW RW R RW W W W RW RW RW RW RW R RW W W W RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual Address 0x40020240 0x40020244 0x40020248 0x4002024C 0x40020250 0x40020254 0x40020258 0x4002025C 0x40020260 0x40020264 Name GP5CON GP5OE GP5PUL GP5IE GP5IN GP5OUT GP5SET GP5CLR GP5TGL GP5ODE Description GPIO Port 5 configuration GPIO Port 5 output enable GPIO Port 5 pull-down enable GPIO Port 5 input path enable GPIO Port 5 registered data input GPIO Port 5 data output GPIO Port 5 data out set GPIO Port 5 data out clear GPIO Port 5 pin toggle GPIO Port 5 open drain enable UG-868 Reset 0x00 0x00 0x0 0xF 0xXX 0x0 0x0 0x0 0x0 0x0 RW RW RW RW RW R RW W W W RW REGISTER DETAILS: DIGITAL INPUT/OUTPUT Note that not all bits are accessible to the user on some port. Inaccessible bits are reserved and must be ignored. See Table 120 for more details on the accessible bits. GPIO Port Configuration Register Address: 0x40020000, Reset: See Table 121, Name: GP0CON Address: 0x40020040, Reset: See Table 121, Name: GP1CON Address: 0x40020080, Reset: See Table 121, Name: GP2CON Address: 0x400200C0, Reset: See Table 121, Name: GP3CON Address: 0x40020100, Reset: See Table 121, Name: GP4CON Address: 0x40020240, Reset: See Table 121, Name: GP5CON Table 122. Bit Descriptions for GP0CON, GP1CON, GP2CON, GP3CON, GP4CON, and GP5CON Bit(s) [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 1 Bit Name CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0 Description Configuration bits for Port x.7. See Table 120.1 Configuration bits for Port x.6. See Table 120. Configuration bits for Port x.5. See Table 120. Configuration bits for Port x.4. See Table 120. Configuration bits for Port x.3. See Table 120. Configuration bits for Port x.2. See Table 120. Configuration bits for Port x.1. See Table 120. Configuration bits for Port x.0. See Table 120. Access RW RW RW RW RW RW RW RW Where x is 0 for Port 0, 1 for Port 1, 2 for Port 2, and 3 for Port 3. GPIO Port Output Enable Register Address: 0x40020004, Reset: See Table 121, Name: GP0OE Address: 0x40020044, Reset: See Table 121, Name: GP1OE Address: 0x40020084, Reset: See Table 121, Name: GP2OE Address: 0x400200C4, Reset: See Table 121, Name: GP3OE Address: 0x40020104, Reset: See Table 121, Name: GP4OE Address: 0x40020244, Reset: See Table 121, Name: GP5OE Table 123. Bit Descriptions for GP0OE, GP1OE, GP2OE, GP3OE, GP4OE, and GP5OE Bit(s) [7:0] Bit Name OE Description Pin output drive enable 0: disable the output on the corresponding GPIO. 1: enable the output on the corresponding GPIO. Rev. A | Page 91 of 190 Access RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual GPIO Port Pull-Up Enable Register Address: 0x40020008, Reset: See Table 121, Name: GP0PUL Address: 0x40020048, Reset: See Table 121, Name: GP1PUL Address: 0x40020088, Reset: See Table 121, Name: GP2PUL Address: 0x400200C8, Reset: See Table 121, Name: GP3PUL Table 124. Bit Descriptions for GP0PUL, GP1PUL, GP2PUL, and GP3PUL Bit(s) [7:0] Bit Name PUL Description Pin pull-up enable in input mode. 0: disable the pull up on the corresponding GPIO. 1: enable the pull up on the corresponding GPIO. Access RW GPIO Port Pull-Down Enable Register Address: 0x40020108, Reset: See Table 121, Name: GP4PUL Address: 0x40020248, Reset: See Table 121, Name: GP5PUL Table 125. Bit Descriptions for GP4PUL and GP5PUL Bit(s) [7:0] Bit Name PUL Description Pin pull-down enable in input mode. 0: disable the pull down on the corresponding GPIO. 1: enable the pull down on the corresponding GPIO. Access RW GPIO Port Input Path Enable Register Address: 0x4002000C, Reset: See Table 121, Name: GP0IE Address: 0x4002004C, Reset: See Table 121, Name: GP1IE Address: 0x4002008C, Reset: See Table 121, Name: GP2IE Address: 0x400200CC, Reset: See Table 121, Name: GP3IE Address: 0x4002010C, Reset: See Table 121, Name: GP4IE Address: 0x4002024C, Reset: See Table 121, Name: GP5IE Table 126. Bit Descriptions for GP0IE, GP1IE, GP2IE, GP3IE, GP4IE, and GP5IE Bit(s) [7:0] Bit Name IEN Description Input path enable. Must be set for external interrupts and to read the pin value. 0: disable the input path on the corresponding GPIO. 1: enable the input path on the corresponding GPIO. Access RW GPIO Port Registered Data Input Address: 0x40020010, Reset: See Table 121, Name: GP0IN Address: 0x40020050, Reset: See Table 121, Name: GP1IN Address: 0x40020090, Reset: See Table 121, Name: GP2IN Address: 0x400200D0, Reset: See Table 121, Name: GP3IN Address: 0x40020110, Reset: See Table 121, Name: GP4IN Address: 0x40020250, Reset: See Table 121, Name: GP5IN Table 127. Bit Descriptions for GP0IN, GP1IN, GP2IN, GP3IN, GP4IN, and GP5IN Bit(s) [7:0] Bit Name IN Description Registered data input. Each bit reflects the state of the GPIO pin. Rev. A | Page 92 of 190 Access R ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 GPIO Port Data Output Register Address: 0x40020014, Reset: See Table 121, Name: GP0OUT Address: 0x40020054, Reset: See Table 121, Name: GP1OUT Address: 0x40020094, Reset: See Table 121, Name: GP2OUT Address: 0x400200D4, Reset: See Table 121, Name: GP3OUT Address: 0x40020114, Reset: See Table 121, Name: GP4OUT Address: 0x40020254, Reset: See Table 121, Name: GP5OUT Table 128. Bit Descriptions for GP0OUT, GP1OUT, GP2OUT, GP3OUT, GP4OUT, and GP5OUT Bit(s) [7:0] Bit Name OUT Description Data out. Do not use the bit-band alias addresses for this register. 0: cleared by user to drive the corresponding GPIO low. 1: set by user code to drive the corresponding GPIO high. Access RW GPIO Port Data Out Set Register Address: 0x40020018, Reset: See Table 121, Name: GP0SET Address: 0x40020058, Reset: See Table 121,Name: GP1SET Address: 0x40020098, Reset: See Table 121, Name: GP2SET Address: 0x400200D8, Reset: See Table 121, Name: GP3SET Address: 0x40020118, Reset: See Table 121, Name: GP4SET Address: 0x40020258, Reset: See Table 121,Name: GP5SET Table 129. Bit Descriptions for GP0SET, GP1SET, GP2SET, GP3SET, GP4SET, and GP5SET Bit(s) [7:0] Bit Name SET Description Set the output high. Do not use the bit-band alias addresses for this register. 0: clearing this bit has no effect. 1: set by user code to drive the corresponding GPIO high. Access W GPIO Port Data Out Clear Register Address: 0x4002001C, Reset: See Table 121, Name: GP0CLR Address: 0x4002005C, Reset: See Table 121, Name: GP1CLR Address: 0x4002009C, Reset: See Table 121, Name: GP2CLR Address: 0x400200DC, Reset: See Table 121, Name: GP3CLR Address: 0x4002011C, Reset: See Table 121, Name: GP4CLR Address: 0x4002021C, Reset: See Table 121, Name: GP5CLR Table 130. Bit Descriptions for GP0CLR, GP1CLR, GP2CLR, GP3CLR, GP4CLR, and GP5CLR Bit(s) [7:0] Bit Name CLR Description Set the output low. Do not use the bit-band alias addresses for this register. 0: clearing this bit has no effect. 1: each bit is set to drive the corresponding GPIO pin low. Rev. A | Page 93 of 190 Access W UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual GPIO Port Pin Toggle Register Address: 0x40020020, Reset: See Table 121, Name: GP0TGL Address: 0x40020060, Reset: See Table 121, Name: GP1TGL Address: 0x400200A0, Reset: See Table 121, Name: GP2TGL Address: 0x400200E0, Reset: See Table 121, Name: GP3TGL Address: 0x40020120, Reset: See Table 121, Name: GP4TGL Address: 0x40020260, Reset: See Table 121, Name: GP5TGL Table 131. Bit Descriptions for GP0TGL, GP1TGL, GP2TGL, GP3TGL, GP4TGL, and GP5TGL Bit(s) [7:0] Bit Name TGL Description Toggle the output of the port pin. Do not use the bit-band alias addresses for this register. 0: clearing this bit has no effect. 1: set by user code to invert the corresponding GPIO pin. Access W GPIO Port Open Drain Enable Register Address: 0x40020024, Reset: See Table 121, Name: GP0ODE Address: 0x40020064, Reset: See Table 121, Name: GP1ODE Address: 0x400200A4, Reset: See Table 121, Name: GP2ODE Address: 0x400200E4, Reset: See Table 121, Name: GP3ODE Address: 0x40020124, Reset: See Table 121, Name: GP4ODE Address: 0x40020264, Reset: See Table 121, Name: GP5ODE Table 132. Bit Descriptions for GP0ODE, GP1ODE, GP2ODE, GP3ODE, GP4ODE, and GP5ODE Bit(s) [7:0] Bit Name ODE Description Open drain enable. 0: set output mode to push-pull for corresponding GPIO pin. 1: set output mode to open drain for corresponding GPIO pin. Rev. A | Page 94 of 190 Access RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 I2C SERIAL INTERFACE I2C FEATURES The I2C interface features master or slave mode with 2-byte transmit and receive FIFOs. The I2C interface supports 7-bit and 10-bit addressing modes; four 7-bit device addresses, or one 10-bit address and two 7-bit addresses in the slave; and repeated starts in master and slave modes. Clock stretching can be enabled by other devices on the bus without causing any issues with the ADuCM320i/ADuCM322/ADuCM322i. Master arbitration, continuous read mode for the master or up to 512 bytes fixed read, and internal and external loopback are also available. Support for DMA in master and slave modes is provided, as well as software control on the slave of the no acknowledge signal. I2C OVERVIEW The I2C data transfer uses a serial clock pin (SCL) and a serial data pin (SDA). The pins are configured in a wired-AND’ed format that allows arbitration in a multimaster system. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer during the initial address transfer. If the master does not lose arbitration and the slave acknowledges the initial address transfer, the data transfer is initiated, which continues until the master issues a stop condition, and the bus becomes idle. Figure 20 shows a typical I2C transfer. A master device can be configured to generate the serial clock. The frequency is programmed by the user in the serial clock divisor register, I2CxDIV (where x is 0 for I2C0 and 1 for I2C1). The master channel can be set to operate in fast mode (400 kHz) or standard mode (100 kHz). MSB LSB LSB R/W SLAVE ADDRESS SCL MSB DATA 3 TO 6 1 2 2 TO 7 7 START BIT 8 9 1 ACK BIT 8 9 ACK BIT STOP BIT 13437-022 SDA Figure 20. Typical I2C Transfer Sequence The user programs the I2C bus peripheral address in the I2C bus system. This ID can be modified anytime a transfer is not in progress. The user can set up to four slave addresses that are recognized by the peripheral. The peripheral is implemented with a 2-byte FIFO for each transmit and receive shift register. The IRQ and status bits in the control registers are available to signal to the processor core when the FIFOs need to be serviced. I2C OPERATION I2C Startup The following steps are required to run the I2C peripheral: 1. 2. 3. 4. Configure the I2C clock in CLKCON1[10:8], CLKCON5[4] for I2C1, and CLKCON5[3] for I2C0. Configure digital pins (P0.4/P0.5, P0.6/P0.7) for I2C operation via the GP0CON register. Configure I2C registers as required for slave or master operation. Enable the I2C slave or master interrupt source as required. Note that, when using I2C, the user must disable the internal pull-up resistors on the I2C pins via the GP0PUL register. Table 133. GPIO Multiplex GPIO P0.4, P0.6 P0.5, P0.7 Configuration Mode (01) SCL SDA Rev. A | Page 95 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Addressing Modes 7-Bit Addressing The I2CxID0, I2CxID1, I2CxID2, and I2CxID3 registers contain the slave device IDs. The device compares the four I2CxIDx registers to the address byte. To be correctly addressed, the seven MSBs of either ID register must be identical to that of the seven MSBs of the first received address byte. The LSB of the ID registers (the transfer direction bit) is ignored in the process of address recognition. The master addresses a device using the I2CxADR0 register. 10-Bit Addressing This feature is enabled by setting I2CxSCON[1] for master and slave mode. The 10-bit address of the slave is stored in the I2CxID0 and I2CxID1 registers, where the I2CxID0 register contains the first byte of the address, and the R/W bit and the upper five bits must be programmed to 11110, as shown in Figure 21. The I2CxID1 register contains the remaining eight bits of the 10-bit address. The I2CxID2 and I2CxID3 registers can still be programmed with 7-bit addresses. The master communicates to a 10-bit address slave using the I2CxADR0 and I2CxADR1 registers. The format is described in Figure 21. To perform a read from a slave with a 10-bit address, the master must first send a 10-bit address with the read/write bit cleared, and then it must generate a repeated start and send only the first byte of the address with the read/write bit set. A repeated start is generated by writing to the I2CxADR0 register while the master is still busy. I2CxADR1 AND I2CxID1 7 6 5 4 3 2 1 1 1 1 1 0 2 MSB 0 7 5 6 R/W 4 3 2 1 0 13437-023 I2CxADR0 AND I2CxID0 8 LSB Figure 21. 10-Bit Address Format A repeated start condition occurs when a second start condition is sent to a slave without a stop condition being sent in between. This sequence allows the master to reverse the direction of the transfer by changing the R/W bit without having to give up control of the bus. An example of a transfer sequence is shown in Figure 22. This sequence is generally used in cases where the first data sent to the devices sets up the register address to be read from. 1 START BIT 2 3 TO 6 LSB R/W SLAVE ADDRESS SCL MSB 7 8 DATA 9 ACK BIT 1 2 TO 7 LSB MSB 9 ACK BIT 1 2 3 TO 6 START BIT LSB R/W SLAVE ADDRESS 8 MSB 7 8 DATA 9 ACK BIT 1 2 TO 7 8 9 ACK STOP BIT BIT 13437-024 LSB MSB SDA Figure 22. I2C Repeated Start Sequence On the slave side, an interrupt is generated (if enabled in the I2CxSCON register) when a repeated start and a slave address are received. This sequence can be differentiated from receiving a start and slave address by using the START and REPSTART status bits in the I2CxSSTA MMR. On the master side, the master generates a repeated start if the I2CxADR0 register is written while the master is still busy with a transaction. After the state machine has started to transmit the device address, it is safe to write to the I2CxADR0 register. For example, if a transaction involving a write, a repeated start, and then a read/write is required, write to the I2CxADR0 register either after the state machine starts to transmit the device address or after the first MTXREQ interrupt is received. When the transmit FIFO empties, a repeated start is generated. Similarly, if a transaction involving a read, a repeated start, and then a read/write is required, write to the first master address byte register, I2CxADR1, either after the state machine starts to transmit the device address or after the first MRXREQ interrupt is received. When the requested receive count is reached, a repeated start is generated. Rev. A | Page 96 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 I2C Clock Control A gated 20 MHz system clock (PCLK) clocks the I2C peripherals. The CLKCON5[3] bit must be cleared to enable the clock to the I2C0 block. Similarly, the CLKCON5[4] bit must be cleared to enable the clock to the I2C1 block. The CLKCON1[10:8] bits allow the I2C block to be clocked with a slower clock by allowing the 20 MHz clock to be divided, which helps to reduce power. The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CxDIV MMR as follows: fSCL = fI2CCLK/(LOW + HIGH + 3) where: fSCL is the I2C baud rate. fI2CCLK = fPCLK/I2CCD. fPCLK is the peripheral clock, 20 MHz. I2CCD is the clock divide value and is set by the CLKCON1[10:8] bits. HIGH is the high period of the clock, I2CxDIV[15:8] = (REQD_HIGH_TIME/PCLK_PERIOD) − 2. LOW is the low period of the clock, I2CxDIV[7:0] = (REQD_LOW_TIME/PCLK_PERIOD) − 1. For 100 kHz SCL operation with a low time of 5 µs, a high time of 5 µs, and a PCLK frequency of 20 MHz, HIGH = (5 µs/(1/20,000,000)) − 2 = 98 = 0x62 LOW = (5 µs/(1/20,000,000)) − 1 = 99 = 0x63 fSCL = 20,000,000/(98 + 99 + 3) = 100 kHz Resetting the I2C Block Three steps are needed to reset the I2C block. In master mode, 1. 2. 3. Clear I2CxMCON[0] to 0 and disable the I2C master. Set I2CxSHCON[0] to 1, which is a write only register. Writing to this bit resets the start/stop detection circuits of the I2C block and clears the LINEBUSY status bit (I2CxMSTA[10]). Set I2CxMCON[0]= 1 to reenable the I2C master. In slave mode, 1. 2. 3. Clear I2CxSCON[0] to 0 and disable the I2C slave. Set I2CxSHCON[0] to 1, which is a write only register. Writing to this bit resets the start/stop detection circuits of the I2C block. Set I2CxSCON[0] to 1 to reenable the I2C slave Do not reset the I2C peripheral on two consecutive communication sequences. I2C OPERATING MODES Master Transfer Initiation If the master enable bit (I2CxMCON[0], MASEN) is set, a master transfer sequence is initiated by writing a value to the I2CxADRx register. If there is valid data in the I2CxMTX register, it is the first byte transferred in the sequence after the address byte during a write sequence. Slave Transfer Initiation If the slave enable bit (I2CxSCON[0], SLVEN) is set, a slave transfer sequence is monitored for the device address in Register I2CxID0, Register I2CxID1, Register I2CxID2, or Register I2CxID3. If the device address is recognized, the device participates in the slave transfer sequence. Note that a slave operation always starts with the assertion of one of three interrupt sources, read request (MRXREQ/SRXREQ ), write request (MTXREQ, STXREQ), or general call (GCINT) interrupt, and the software must always look for a stop interrupt to ensure that the transaction has completed correctly and to deassert the stop interrupt status bit. Rev. A | Page 97 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Rx/Tx Data FIFOs STOP ACK ACK ACK DEVICE ADDRESS READ The transmit data path consists of a master and slave Tx FIFO, each two bytes deep, the I2CxMTX and I2CxSTX registers, and a transmit shifter. The transmit status bits in I2CxMSTA[1:0] and I2CxSSTA[0] denote whether there is valid data in the Tx FIFO. Data from the Tx FIFO is loaded into the Tx shifter when a serial byte begins transmission. If the Tx FIFO is not full during an active transfer sequence, the transmit request bit (I2CxMSTA[2] or I2CxSSTA[2]) asserts. Figure 23 shows the effect of not having the slave Tx FIFO full at the start of a read request from a master. An extra transmit interrupt may be generated after the read bit. This extra transmit interrupt occurs if the Tx FIFO is not full. DATA (n) TRANSMIT INTERRUPT DATA (n + 1) TRANSMIT INTERRUPT DATA (n + 2) TRANSMIT INTERRUPT DATA (n + x) NO ACK R/W ACK SDA LINE TRANSMIT INTERRUPT TRANSMIT INTERRUPT 13437-021 EXTRA TRANSMIT INTERRUPT POSSIBLE IF FIFO LOADED IN PREVIOUS INTERRUPT Figure 23. I2C Slave Tx Interrupt Details In the slave, if there is no valid data to transmit when the Tx shifter is loaded, the transmit underflow status bit asserts (I2CxMSTA[12], ISCxSSTA[1]). In slave mode, the Tx FIFO must be loaded with a byte before the falling edge of SCL before the acknowledge/no acknowledge is asserted. If the Tx FIFO is empty on the falling edge of SCL for a R/W bit, the slave returns a no acknowledge because the slave in this case controls the acknowledge/no acknowledge. If the first byte is transmitted correctly in a slave Tx sequence, but the Tx FIFO is empty for any subsequent bytes in the same transfer, the slave returns the previous transmitted byte. This operation is due to the master having control of the acknowledge/no acknowledge during a slave transfer sequence. The master generates a stop condition if there is no data in the transmit FIFO and the master is writing data. The receive data path consists of a master and slave Rx FIFO, each two bytes deep, I2CxMRX and I2CxSRX. The receive request interrupt bit (I2CxMSTA[3] or I2CxSSTA[3]) indicates whether there is valid data in the Rx FIFO. Data is loaded into the Rx FIFO after each byte is received. If valid data in the Rx FIFO is overwritten by the Rx shifter, the receive overflow status bit is asserted (I2CxMSTA[9] or I2CxSSTA[4]). Automatic Clock Stretching It is recommended that automatic clock stretching is enabled, especially in slave mode. A timeout feature is added to ensure that the I2C block never erroneously holds the SCL pin low indefinitely. A separate status bit for master and slave mode indicates if stretch timeout occurred. The I2CxASSCL register controls automatic clock stretching. If automatic clock stretching is enabled, the I2C hardware holds the SCL pin low after the falling edge of SCL before an acknowledge/no acknowledge during the following conditions: • • • The Tx FIFO is empty when a valid read request is active for the master or slave. If the Tx FIFO is still empty at the end of the timeout period, the following occurs: • If the Tx FIFO is empty on the falling edge of SCL for a R/W bit, the slave returns a no acknowledge after the timeout period. • If the first byte is transmitted correctly in a slave Tx sequence, but the TX FIFO is empty for any subsequent bytes in the same transfer with clock stretch enabled, the slave returns the previous transmitted byte at the end of the timeout period. The Rx FIFO is full when another byte is about to be received. If the RX FIFO has still not been read at the end of the timeout period, a no acknowledge is returned, and the master ends the sequence with a stop condition. It is not recommended to use the I2CxSCON[6] clock stretching method when using automatic clock stretching. Master NACK When receiving data, the master responds with a no acknowledge if its FIFO is full and an attempt is made to write another byte to the FIFO. This last byte received is not written to the FIFO and is lost. Rev. A | Page 98 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 No Acknowledge from the Slave If the slave does not want to acknowledge a read access, not writing data into the slave transmit FIFO results in a no acknowledge. If the slave does not want to acknowledge a master write, assert the no acknowledge bit in the slave control register, I2CxSCON[7]. Normally, the slave acknowledges all bytes written into the receive FIFO. If the receive FIFO fills up, the slave cannot write further bytes to it, and the slave does not acknowledge subsequent bytes not written to the FIFO. The master must then stop the transaction. The slave does not acknowledge a matching device address if the read/write bit is set and the transmit FIFO is empty. Therefore, there is very little time for the microcontroller to respond to a slave transmit request and the assertion of an acknowledge. It is recommended that EARLYTXR (I2CxSCON[5]) be asserted for this reason. General Call An I2C general call is for addressing every device on the I2C bus. A general call address is 0x00 or 0x01. The first byte, the address byte, is followed by a command byte. If the address byte is 0x00, Byte 2 (the command byte) can be one of the following: • • 0x6: the I2C interface (master and slave) is reset. The general call interrupt status asserts, and the general call ID bits, GCID (I2CxSSTA[9:8]), are 0x1. User code must take corrective action to reset the entire system or simply reenable the I2C interface. 0x4: the general call interrupt status bit is asserted, and the general call ID bits (GCID) are 0x2. If the address byte is 0x01, a hardware general call is issued. Byte 2 in this case is the hardware master address. The general call interrupt status bit is set on any general call after the second byte is received, and user code must take corrective action to reprogram the device address. If GCEN is asserted, the slave always acknowledges the first byte of a general call. It acknowledges the second byte of a general call if the second byte is 0x04 or 0x06, or if the second byte is a hardware general call and HGCEN (I2CxSCON[3]) is asserted. The I2CxALT register contains the alternate device ID for a hardware general call sequence. If the hardware general call enable bit (HGCEN), the general call enable bit (GCEN), and the slave enable bit (SLVEN) are all set, the device recognizes a hardware general call. When a general call sequence is issued and the second byte of the sequence is identical to ALT, the hardware call sequence is recognized for the device. I2C Reset Mode The slave state machine is reset when SLVEN is written to 0. The master state machine is reset when MASEN is written to 0. I2C Test Modes The device can be placed in an internal loopback mode by setting the LOOPBACK bit (I2CxMCON[2]). There are four FIFOs (master Tx and Rx, and slave Tx and Rx); therefore the I2C peripheral can, in effect, be set up to talk to itself. External loopback can be performed if the master is set up to address the slave address. I2C Low Power Mode If the master and slave are both disabled (MASEN = SLVEN = 0), the I2C section is off. To fully power down the I2C block, the clock to the I2C section of the chip should be disabled by setting CLKCON5[4:3] = 0x3. DMA Requests Four DMA channels are provided to service the I2C master and slave. DMA enable bits are provided in the slave control register and in the master control register. Rev. A | Page 99 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: I2C0 Table 134. I2C0 Register Summary Address 0x40003000 0x40003004 0x40003008 0x4000300C 0x40003010 0x40003014 0x40003018 0x4000301C 0x40003024 0x40003028 0x4000302C 0x40003030 0x40003034 0x40003038 0x4000303C 0x40003040 0x40003044 0x40003048 0x4000304C 0x40003050 0x40003058 Name I2C0MCON I2C0MSTA I2C0MRX I2C0MTX I2C0MRXCNT I2C0MCRXCNT I2C0ADR0 I2C0ADR1 I2C0DIV I2C0SCON I2C0SSTA I2C0SRX I2C0STX I2C0ALT I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0FSTA I2C0SHCON I2C0ASSCL Description Master control register Master status register Master receive data register Master transmit data register Master receive data count register Master current receive data count register First master address byte register Second master address byte register Serial clock period divisor register Slave control register Slave I2C0 status/error/IRQ register Slave receive register Slave transmit register Hardware general call ID register First slave address device ID register Second slave address device ID register Thirds slave address device ID register Fourth slave address device ID register Master and slave FIFO status register Master and slave shared control register Automatic stretch control register for master and slave mode Reset 0x0000 0x6000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x1F1F 0x0000 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 RW RW R R RW RW R RW RW RW RW R R RW RW RW RW RW RW RW W RW Reset 0x0 0x0 Access R W 0x0 W 0x0 0x0 RW RW 0x0 RW 0x0 RW 0x0 RW REGISTER DETAILS: I2C0 Master Control Register Address: 0x40003000, Reset: 0x0000, Name: I2C0MCON Table 135. Bit Descriptions for I2C0MCON Bit(s) [15:12] 11 Bit Name RESERVED MTXDMA 10 MRXDMA 9 8 RESERVED IENCMP 7 IENACK 6 IENALOST 5 IENMTX Description Reserved. Enable master Tx DMA request. 0: disable DMA mode. 1: enable I2C0 master DMA Tx requests. Enable master Rx DMA request. 0: disable DMA mode. 1: enable I2C0 master DMA Rx requests. Reserved. Transaction completed (or stop detected) interrupt enable. 0: an interrupt is not generated when a stop is detected. 1: an interrupt is generated when a stop is detected. Acknowledge not received interrupt enable. 0: acknowledge not received interrupt disable. 1: acknowledge not received interrupt enable. Arbitration lost interrupt enable. 0: arbitration lost interrupt disable. 1: arbitration lost interrupt enable. Transmit request interrupt enable. 0: transmit request interrupt disable. 1: transmit request interrupt enable. Rev. A | Page 100 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 4 Bit Name IENMRX 3 2 RESERVED LOOPBACK 1 COMPETE 0 MASEN Description Receive request interrupt enable. 0: receive request interrupt disable. 1: receive request interrupt enable. Reserved. A value of 0 must be written to this bit. Internal loopback enable. Note that it is also possible for the master to loop back a transfer to the slave as long as the device address corresponds, that is, external loopback. 0: SCL and SDA out of the device are not muxed onto their corresponding inputs. 1: SCL and SDA out of the device are muxed onto their corresponding inputs. Start back-off disable. Setting this bit enables the device to compete for ownership even if another device is currently driving a start condition. Master enable. The master must be disabled when not in use because this gates the clock to the master and saves power. This bit must not be cleared until a transaction has completed (see the TCOMP bit in the master status register). 0: master is disabled. 1: master is enabled. UG-868 Reset 0x0 Access RW 0x0 0x0 RW RW 0x0 RW 0x0 RW Reset 0x0 0x1 Access R R 0x1 R 0x0 RC 0x0 RC 0x0 R 0x0 RC 0x0 RC 0x0 RC 0x0 R 0x0 RC 0x0 RC Master Status Register Address: 0x40003004, Reset: 0x6000, Name: I2C0MSTA Table 136. Bit Descriptions for I2C0MSTA Bit(s) 15 14 Bit Name RESERVED SCL_FILTERED 13 SDA_FILTERED 12 MTXUFLOW 11 MSTOP 10 LINEBUSY 9 MRXOF 8 TCOMP 7 NACKDATA 6 MBUSY 5 ALOST 4 NACKADDR Description Reserved. State of SCL line. This bit is the output of the glitch filter on SCL. SCL is always pulled high when undriven. State of SDA line. This bit is the output of the glitch filter on SDA. SDA is always pulled high when undriven. Master transmit underflow. Asserts when the I2C0 master ends the transaction due to Tx FIFO empty condition. This bit is asserted only when the IENMTX bit is set. Stop driven by this I2C0 master. Asserts when this I2C0 master drives a stop condition on the I2C0 bus. This bit, when asserted, can indicate a transaction completion, Tx underflow, Rx overflow, or a no acknowledge by the slave. This bit is different from the TCOMP because this bit is not asserted when the stop condition occurs due to any other I2C0 master. No interrupt is generated for the assertion of this bit. However, if IENCMP is 1, every stop condition generates an interrupt and this bit can be read. When this bit is read, it clears status. Line is busy. Asserts when a start is detected on the I2C0 bus. Deasserts when a stop is detected on the I2C0 bus. Master receive FIFO overflow. Asserts when a byte is written to the receive FIFO when the FIFO is already full. When the bit is read, it clears status. Transaction complete or stop detected. Transaction complete. This bit asserts when a stop condition is detected on the I2C0 bus. If IENCMP is 1, an interrupt is generated when this bit asserts. This bit only asserts if the master is enabled (MASEN = 1). Use this bit to determine when it is safe to disable the master. This bit can also be used to wait for another master transaction to complete on the I2C0 bus when this master loses arbitration. When this bit is read, it clears status. This bit can drive an interrupt. Acknowledge not received in response to data write. This bit asserts when an acknowledge is not received in response to a data write transfer. If IENACK is 1, an interrupt is generated when this bit asserts. This bit can drive an interrupt. This bit is cleared on a read of the I2C0MSTA register. Master busy. This bit indicates that the master state machine is servicing a transaction. It is cleared if the state machine is idle or another device has control of the I2C0 bus. Arbitration lost. This bit asserts if the master loses arbitration. If IENALOST is 1, an interrupt is generated when this bit asserts. This bit is cleared on a read of the I2C0MSTA register. This bit can drive an interrupt. Acknowledge not received in response to an address. This bit asserts if an acknowledge is not received in response to an address. If IENACK is 1, an interrupt is generated when this bit asserts. This bit is cleared on a read of the I2C0MSTA register. This bit can drive an interrupt. Rev. A | Page 101 of 190 UG-868 Bit(s) 3 Bit Name MRXREQ 2 MTXREQ [1:0] MTXFSTA ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description Master receive request. This bit asserts when there is data in the receive FIFO. If IENMRX is 1, an interrupt is generated when this bit asserts. This bit can drive an interrupt. Master transmit request. This bit asserts when the direction bit is 0 and the transmit FIFO is either empty or not full. If IENMTX is 1, an interrupt is generated when this bit asserts. This bit can drive an interrupt. Master transmit FIFO status. These two bits show the master transmit FIFO status and can be decoded as follows: 00 = FIFO empty. 10 = 1 byte in FIFO. 11 = FIFO full. Reset 0x0 Access R 0x0 R 0x0 R Master Receive Data Register Address: 0x40003008, Reset: 0x0000, Name: I2C0MRX Table 137. Bit Descriptions for I2C0MRX Bit(s) [15:8] [7:0] Bit Name RESERVED ICMRX Description Reserved. Master receive register. This register allows access to the receive data FIFO. The FIFO can hold 2 bytes. Reset 0x0 0x0 Access R R Reset 0x0 0x0 Access R RW Master Transmit Data Register Address: 0x4000300C, Reset: 0x0000, Name: I2C0MTX Table 138. Bit Descriptions for I2C0MTX Bit(s) [15:8] [7:0] Bit Name RESERVED I2C0MTX Description Reserved. Master transmit register. For test and debug purposes, when read, this register returns the byte that is currently being transmitted by the master; that is, a byte written to the transmit register can be read back later when that byte is being transmitted on the line. This register allows access to the transmit data FIFO. The FIFO can hold 2 bytes. Master Receive Data Count Register Address: 0x40003010, Reset: 0x0000, Name: I2C0MRXCNT Table 139. Bit Descriptions for I2C0MRXCNT Bit(s) [15:9] 8 Bit Name RESERVED EXTEND [7:0] COUNT Description Reserved. Extended read. Use this bit if greater than 256 bytes are required on a read. For example, to receive 412 bytes, write 0x100 (EXTEND = 1) to the I2C0MRXCNT register. Wait for the first byte to be received, then check the I2C0MCRXCNT register for every byte received thereafter. When COUNT returns to 0, 256 bytes have been received. Then write 0x09C to the I2C0MRXCNT register. Receive count. Program the number of bytes required minus 1 to this register. If just 1 byte is required, write 0 to this register. If greater than 256 bytes are required, use EXTEND. Reset 0x0 0x0 Access R RW 0x0 RW Reset 0x0 0x0 Access R R Master Current Receive Data Count Register Address: 0x40003014, Reset: 0x0000, Name: I2C0MCRXCNT Table 140. Bit Descriptions for I2C0MCRXCNT Bit(s) [15:8] [7:0] Bit Name RESERVED COUNT Description Reserved. Current receive count. This register gives the total number of bytes received so far. If 256 bytes are requested, this register reads 0 when the transaction has completed. Rev. A | Page 102 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 First Master Address Byte Register Address: 0x40003018, Reset: 0x0000, Name: I2C0ADR0 Table 141. Bit Descriptions for I2C0ADR0 Bit(s) [15:8] [7:0] Bit Name RESERVED ADR0 Description Reserved. Address Byte 0. If a 7-bit address is required, Bit 7 to Bit 1 of ADR0 are programmed with the address, and Bit 0 of ADR0 is programmed with the direction (0 = write, 1 = read ). If a 10-bit address is required, Bit 7 to Bit 3 of ADR0 are programmed with 11110, Bit 2 to Bit 1 of ADR0 are programmed with the 2 MSBs of the address, and Bit 0 of ADR0 is programmed to 0. Reset 0x0 0x0 Access R RW Second Master Address Byte Register Address: 0x4000301C, Reset: 0x0000, Name: I2C0ADR1 Table 142. Bit Descriptions for I2C0ADR1 Bit(s) [15:8] [7:0] Bit Name RESERVED ADR1 Description Reserved. Address Byte 1. This register is only required when addressing a slave with a 10-bit address. Bit 7 to Bit 0 of ADR1 are programmed with the lower 8 bits of the address. Reset 0x0 0x0 Access R RW Reset 0x1F Access RW 0x1F RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 0x0 RW RW Serial Clock Period Divisor Register Address: 0x40003024, Reset: 0x1F1F, Name: I2C0DIV Table 143. Bit Descriptions for I2C0DIV Bit(s) [15:8] Bit Name HIGH [7:0] LOW Description Serial clock high time. This register controls the clock high time. The core clock (PCLK) drives the timer. Use the following equation to derive the required high time. HIGH = (REQD_HIGH_TIME/PCLK_PERIOD) − 2 For example, to generate a 400 kHz SCL with a low time of 1300 ns and a high time of 1200 ns, with a core clock frequency of 50 MHz, LOWTIME = 1300 ns/20 ns − 1 = 0x40 (64 decimal) HIGH = 1200 ns/20 ns − 2 = 0x3A (58 decimal). This register is reset to 0x1F, which gives an SCL high time of 33 PCLK ticks. tHD:STA is also determined by the HIGH value. tHD:STA = (HIGH − 1) × PCLK_PERIOD Because tHD:STA must be 600 ns, with PCLK = 50 MHz, the minimum value for HIGH is 31. This gives an SCL high time of 660 ns. Serial clock low time. This register controls the clock low time. The core clock (PCLK) drives the timer. Use the following equation to derive the required low time. LOW = (REQD_LOW_TIME/PCLK_PERIOD) − 1 This register is reset to 0x1F, which gives an SCL low time of 32 PCLK ticks. Slave Control Register Address: 0x40003028, Reset: 0x0000, Name: I2C0SCON Table 144. Bit Descriptions for I2C0SCON Bit(s) 15 14 Bit Name RESERVED STXDMA 13 SRXDMA 12 IENREPST 11 10 RESERVED IENSTX Description Reserved. Enable slave Tx DMA request. Set to 1 by user code to enable I2C0 slave DMA Rx requests. Cleared by user code to disable DMA mode. Enable slave Rx DMA request. Set to 1 by user code to enable I2C0 slave DMA Rx requests. Cleared by user code to disable DMA mode. Repeated start interrupt enable. If 1, an interrupt is generated when the REPSTART status bit asserts. If 0, an interrupt is not generated when the REPSTART status bit asserts. Reserved. Slave transmit request interrupt enable. Rev. A | Page 103 of 190 UG-868 Bit(s) 9 8 7 Bit Name IENSRX IENSTOP NACK 6 5 RESERVED EARLYTXR 4 GCSBCLR 3 HGCEN 2 GCEN 1 ADR10EN 0 SLVEN ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description Slave receive request interrupt enable. Stop condition detected interrupt enable. No acknowledge next communication. If this bit is set, the next communication is not acknowledged. This setting can be used, for example, if during a 24xx style access an attempt was made to write to a read only or nonexistent location in system memory; that is, the indirect address in a 24xx style write pointed to an unwriteable memory location. Reserved. A value of 0 must be written to this bit. Early transmit request mode. Setting this bit enables a transmit request just after the positive edge of the direction bit SCL clock pulse. General call status bit clear. The general call status and general call ID bits are cleared when a 1 is written to this bit. The general call status and general call ID bits are not reset by anything other than a write to this bit or a full reset. Hardware general call enable. When this bit and the general call enable bit are set, the device after receiving a general call, Address 00h, and a data byte, checks the contents of the ALT register against the receive shift register. If they match, the device has received a hardware general call. This call is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a to whom it may concern call. The device that requires attention embeds its own address into the message. The LSB of the ALT register must always be written to a 1, as per the I2C0 January 2000 specification. General call enable. This bit enables the I2C0 slave to acknowledge an I2C0 general call, Address 0x00 (write). Enabled 10-bit addressing. If this bit is clear, the slave can support four slave addresses, programmed in Register I2C0ID0 to Register I2C0ID3. When this bit is set, 10-bit addressing is enabled. One 10-bit address is supported by the slave and is stored in I2C0ID0 and I2C0ID1, where I2C0ID0 contains the first byte of the address and the upper 5 bits must be programmed to 11110. I2C0ID3 and I2C0ID4 can be programmed with 7-bit addresses at the same time. Slave enable. When 1, the slave is enabled. When 0, all slave state machine flops are held in reset and the slave is disabled. Reset 0x0 0x0 0x0 Access RW RW RW 0x0 0x0 RW RW 0x0 W 0x0 RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access R R 0x0 RC 0x0 R 0x0 RC Slave I2C0 Status/Error/IRQ Register Address: 0x4000302C, Reset: 0x0001, Name: I2C0SSTA Table 145. Bit Descriptions for I2C0SSTA Bit(s) 15 14 Bit Name RESERVED START 13 REPSTART [12:11] IDMAT 10 STOP Description Reserved. Start and matching address. This bit is asserted if a start is detected on SCL/SDA and the device address matched; if a general call (address = 0000_0000) code is received and general call is enabled; if a high speed (address = 0000_1XXX) code is received; or if a start byte (0000_0001) is received. It is cleared on receipt of either a stop or start condition. Repeated start and matching address. This bit is asserted if start is already asserted and then a repeated start is detected. It is cleared when read or on receipt of a stop condition. This bit can drive an interrupt. Device ID matched. 00: received address matched ID Register 0. 01: received address matched ID Register 1. 10: received address matched ID Register 2. 11: received address matched ID Register 3. Stop after start and matching address. This bit is set by hardware if the slave device received a stop condition after a previous start condition and a matching address. Cleared by a read of the status register. If STOPINTEN in the slave control register is asserted, the slave interrupt request asserts when this bit is set. This bit can drive an interrupt. Rev. A | Page 104 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) [9:8] Bit Name GCID 7 GCINT 6 SBUSY 5 NOACK 4 SRXOF 3 SRXREQ 2 STXREQ 1 STXUR 0 STXFSEREQ Description General ID. GCID is cleared when the GCSBCLR is written to 1. These status bits are not cleared by a general call reset. 00: no general call. 01: general call reset and program address. 10: general call program address. 11: general call matching alternative ID. General call interrupt. This bit always drives an interrupt. The bit is asserted if the slave device receives a general call of any type. To clear, write 1 to the GCSBCLR in the slave control register. If it was a general call reset, all registers are at their default values. If it was a hardware general call, the Rx FIFO holds the second byte of the general call, and this can be compared with the ALT register. Slave busy. Set by hardware if the slave device receives an I2C0 start condition. Cleared by hardware when the address does not match an ID register, the slave device receives an I2C0 stop condition, or if a repeated start address does not match. Acknowledge not generated by the slave. When asserted, it indicates that the slave responded to its device address with a no acknowledge. It is asserted if there was no data to transmit and sequence was a slave read or if the NACK bit was set in the slave control register and the device was addressed. This bit is cleared on a read of the I2C0SSTA register. Slave receive FIFO overflow. Asserts when a byte is written to the slave receive FIFO when the FIFO is already full. Slave receive request. SRXREQ asserts whenever the slave receive FIFO is not empty. Read or flush the slave receive FIFO to clear this bit. This bit asserts on the falling edge of the SCL clock pulse that clocks in the last data bit of a byte. This bit can drive an interrupt. Slave transmit request. If EARLYTXR = 0, STXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit remains asserted. Initially, it is asserted on the negative edge of the SCL pulse that clocks in the direction bit (if the device address matched also). If EARLYTXR = 1, STXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit remains asserted. Initially, it is asserted after the positive edge of the SCL pulse that clocks in the direction bit (if the device address matched also). This bit is cleared on a read of the I2C0SSTA register. Slave transmit FIFO underflow. This bit is set if a master requests data from the device, and the Tx FIFO is empty for the rising edge of SCL. Slave Tx FIFO status or early request. If EARLYTXR = 0, this bit is asserted whenever the slave Tx FIFO is empty. If EARLYTXR = 1, STXFSEREQ is set when the direction bit for a transfer is received high. It asserts on the positive edge of the SCL clock pulse that clocks in the direction bit (if the device address matched also). It only asserts once for a transfer. It is cleared when read, if EARLYTXR is asserted. UG-868 Reset 0x0 Access R 0x0 R 0x0 R 0x0 RC 0x0 RC 0x0 RC 0x0 RC 0x0 RC 0x1 RW Reset 0x0 0x0 Access R R Reset 0x0 0x0 Access R RW Slave Receive Register Address: 0x40003030, Reset: 0x0000, Name: I2C0SRX Table 146. Bit Descriptions for I2C0SRX Bit(s) [15:8] [7:0] Bit Name RESERVED I2C0SRX Description Reserved Slave receive register Slave Transmit Register Address: 0x40003034, Reset: 0x0000, Name: I2C0STX Table 147. Bit Descriptions for I2C0STX Bit(s) [15:8] [7:0] Bit Name RESERVED I2C0STX Description Reserved Slave transmit register Rev. A | Page 105 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Hardware General Call ID Register Address: 0x40003038, Reset: 0x0000, Name: I2C0ALT Table 148. Bit Descriptions for I2C0ALT Bit(s) [15:8] [7:0] Bit Name RESERVED ALT Description Reserved. Slave Alt. This register is used in conjunction with I2C0SCON[3] to match a master generating a hardware general call. It is used in the case where a master device cannot be programmed with the address of a slave, and instead the slave must recognize the address of the master. Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW First Slave Address Device ID Register Address: 0x4000303C, Reset: 0x0000, Name: I2C0ID0 Table 149. Bit Descriptions for I2C0ID0 Bit(s) [15:8] [7:0] Bit Name RESERVED ID0 Description Reserved. Slave Device ID 0. I2C0ID0[7:1] is programmed with the device ID. I2C0ID0[0] is don't care. See the ADR10EN bit in the slave control register to see how this register is programmed with a 10-bit address. Second Slave Address Device ID Register Address: 0x40003040, Reset: 0x0000, Name: I2C0ID1 Table 150. Bit Descriptions for I2C0ID1 Bit(s) [15:8] [7:0] Bit Name RESERVED ID1 Description Reserved. Slave Device ID 1. I2C0ID1[7:1] is programmed with the device ID. I2C0ID1[0] is don't care. See the ADR10EN bit in the slave control register to see how this register is programmed with a 10-bit address. Third Slave Address Device ID Register Address: 0x40003044, Reset: 0x0000, Name: I2C0ID2 Table 151. Bit Descriptions for I2C0ID2 Bit(s) [15:8] [7:0] Bit Name RESERVED ID2 Description Reserved. Slave Device ID 2. I2C0ID2[7:1] is programmed with the device ID. I2C0ID2[0] is don't care. See the ADR10EN bit in the slave control register to see how this register is programmed with a 10-bit address. Fourth Slave Address Device ID Register Address: 0x40003048, Reset: 0x0000, Name: I2C0ID3 Table 152. Bit Descriptions for I2C0ID3 Bit(s) [15:8] [7:0] Bit Name RESERVED ID3 Description Reserved. Slave Device ID 3. I2C0ID3[7:1] is programmed with the device ID. I2C0ID3[0] is don't care. See the ADR10EN bit in the slave control register to see how this register is programmed with a 10-bit address. Rev. A | Page 106 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Master and Slave FIFO Status Register Address: 0x4000304C, Reset: 0x0000, Name: I2C0FSTA Table 153. Bit Descriptions for I2C0FSTA Bit(s) [15:10] 9 Bit Name RESERVED MFLUSH 8 SFLUSH [7:6] MRXFSTA [5:4] MTXFSTA [3:2] SRXFSTA [1:0] STXFSTA Description Reserved. Flush the master transmit FIFO. 0: clearing to 0 has no effect. 1: set to 1 to flush the master transmit FIFO. The master transmit FIFO must be flushed if arbitration is lost or a slave responds with a no acknowledge. Flush the slave transmit FIFO. 0: clearing to 0 has no effect. 1: set to 1 to flush the slave transmit FIFO. Master receive FIFO status. The status is a count of the number of bytes in a FIFO. 00: FIFO empty. 01: 1 byte in the FIFO. 10: 2 bytes in the FIFO. 11: reserved. Master transmit FIFO status. The status is a count of the number of bytes in a FIFO. 00: FIFO empty. 01: 1 byte in the FIFO. 10: 2 bytes in the FIFO. 11: reserved. Slave receive FIFO status. The status is a count of the number of bytes in a FIFO. 00: FIFO empty. 01: 1 bytes in the FIFO. 10: 2 bytes in the FIFO. 11: reserved. Slave transmit FIFO status. The status is a count of the number of bytes in a FIFO. 00: FIFO empty. 01: 1 byte in the FIFO. 10: 2 bytes in the FIFO. 11: reserved. Reset 0x0 0x0 Access RW W 0x0 W 0x0 R 0x0 R 0x0 R 0x0 R Reset 0x0000 0x0 Access RW W Master and Slave Shared Control Register Address: 0x40003050, Reset: 0x0000, Name: I2C0SHCON Table 154. Bit Descriptions for I2C0SHCON Bit(s) [15:1] 0 Bit Name RESERVED RESET Description Reserved. Write a 1 to this bit to reset the I2C start and stop detection circuits. Setting this bit resets the LINEBUSY status bit. Rev. A | Page 107 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Automatic Stretch Control Register Address: 0x40003058, Reset: 0x0000, Name: I2C0ASSCL Table 155. Bit Descriptions for I2C0ASSCL Bit(s) [15:10] 9 Bit Name RESERVED SSRTSTA 8 MSRTSTA [7:4] SSTRCON Description Reserved. Stretch timeout status bit for slave. Set when slave automatic stretch mode has timed out. Cleared when this bit is read. Stretch timeout status bit for master. Set when master automatic stretch mode has timed out. Cleared when this bit is read. Automatic stretch mode control for slave. These bits control automatic stretch mode for slave operation. SSTRCON allows the slave to hold the SCL line low and gain more time to service an interrupt, load a FIFO, or read a FIFO. Use the timeout feature to avoid a bus lockup condition where the slave indefinitely holds SCL low. As a slave transmitter, SCL is automatically stretched from the negative edge of SCL if the slave Tx FIFO is empty before sending acknowledge/no acknowledge for address byte, or before sending data for a data byte. Stretching stops when the slave Tx FIFO is no longer empty or a timeout occurs. As a slave receiver, SCL clock is automatically stretched from the negative edge of SCL, when the slave Rx FIFO is full, before sending acknowledge/no acknowledge. Stretching stops when the slave Rx FIFO is no longer in an overflow condition or a timeout occurs. 0000: automatic slave clock stretching disabled. 0001 to 1110: automatic slave clock stretching enabled. The timeout period is defined by I2C0DIV[15 : 8] + I2C0DIV[7 : 4] − 1 UCLK/CLKCON[10 : 8] [3:0] MSTRCON ( × 2I2C0ASSCL[7: 4] UCLK/CLKCON[10 : 8] ( × 2I2C0ASSCL[3:0] ) 1111: automatic master clock stretching enabled with indefinite timeout period. Rev. A | Page 108 of 190 Access R R 0x0 R 0x0 RW 0x0 RW ) Note that the I2C bus baud rate has no influence on the slave stretch timeout period. 1111: automatic slave clock stretching enabled with indefinite timeout period. Automatic stretch mode control for master. These bits control automatic stretch mode for master operation. MSTRCON allows the master to hold the SCL line low and gain more time to service an interrupt, load a FIFO, or read a FIFO. Use the timeout feature to avoid a bus lockup condition where the master indefinitely holds SCL low. As a master transmitter, SCL is automatically stretched from the negative edge of SCL if the master Tx FIFO is empty before sending acknowledge/no acknowledge for address byte, or before sending data for a data byte. Stretching stops when the master Tx FIFO is no longer empty or, a timeout occurs. As a master receiver, SCL clock is automatically stretched from the negative edge of SCL, when the master Rx FIFO is full, before sending acknowledge/no acknowledge. Stretching stops when the master Rx FIFO is no longer in an overflow condition or, a timeout occurs. 0000: automatic master clock stretching disabled. 0001 to 1110: automatic master clock stretching enabled. The timeout period is defined by I2C0DIV[15 : 8] + I2C0DIV[7 : 4] − 1 Reset 0x0 0x0 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER SUMMARY: I2C1 Table 156. I2C1 Register Summary Address 0x40003400 0x40003404 0x40003408 0x4000340C 0x40003410 0x40003414 0x40003418 0x4000341C 0x40003424 0x40003428 0x4000342C 0x40003430 0x40003434 0x40003438 0x4000343C 0x40003440 0x40003444 0x40003448 0x4000344C 0x40003450 0x40003458 Name I2C1MCON I2C1MSTA I2C1MRX I2C1MTX I2C1MRXCNT I2C1MCRXCNT I2C1ADR0 I2C1ADR1 I2C1DIV I2C1SCON I2C1SSTA I2C1SRX I2C1STX I2C1ALT I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1FSTA I2C1SHCON I2C1ASSCL Description Master control register Master status register Master receive data register Master transmit data register Master receive data count register Master current receive data count register First master address byte register Second master address byte register Serial clock period divisor register Slave control register Slave I2C status/error/IRQ register Slave receive register Slave transmit register Hardware general call ID register First slave address device ID register Second slave address device ID register Third slave address device ID register Fourth slave address device ID register Master and slave FIFO status register Master and slave shared control register Automatic stretch control register for master and slave mode Reset 0x0000 0x6000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x1F1F 0x0000 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 RW RW R R RW RW R RW RW RW RW R R RW RW RW RW RW RW RW W RW Reset 0x0 0x0 Access R W 0x0 W 0x0 0x0 RW RW 0x0 RW 0x0 RW 0x0 RW REGISTER DETAILS: I2C1 Master Control Register Address: 0x40003400, Reset: 0x0000, Name: I2C1MCON Table 157. Bit Descriptions for I2C1MCON Bit(s) [15:12] 11 Bit Name RESERVED MTXDMA 10 MRXDMA 9 8 RESERVED IENCMP 7 IENACK 6 IENALOST 5 IENMTX Description Reserved. Enable master Tx DMA request. 0: disable DMA mode. 1: enable I2C master DMA Tx requests. Enable master Rx DMA request. 0: disable DMA mode. 1: enable I2C master DMA Rx requests. Reserved. Transaction completed (or stop detected) interrupt enable. 0: an interrupt is not generated when a STOP is detected. 1: an interrupt is generated when a STOP is detected. Acknowledge not received interrupt enable. 0: acknowledge not received interrupt disable. 1: acknowledge not received interrupt enable. Arbitration lost interrupt enable. 0: arbitration lost interrupt disable. 1: arbitration lost interrupt enable. Transmit request interrupt enable. 0: transmit request interrupt disable. 1: transmit request interrupt enable. Rev. A | Page 109 of 190 UG-868 Bit(s) 4 Bit Name IENMRX 3 2 RESERVED LOOPBACK 1 COMPETE 0 MASEN ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description Receive request interrupt enable. 0: receive request interrupt disable. 1: receive request interrupt enable. Reserved. A value of 0 must be written to this bit. Internal loopback enable. Note that is also possible for the master to loop back a transfer to the slave as long as the device address corresponds, that is, external loopback. 0: SCL and SDA out of the device are not muxed onto their corresponding inputs. 1: SCL and SDA out of the device are muxed onto their corresponding inputs. Start back-off disable. Setting this bit enables the device to compete for ownership even if another device is currently driving a START condition. Master enable. The master must be disabled when not in use as this gates the clock to the master and saves power. This bit must not be cleared until a transaction has completed; see the TCOMP bit in the master status register. 0: master is disabled. 1: master is enabled. Reset 0x0 Access RW 0x0 0x0 RW RW 0x0 RW 0x0 RW Reset 0x0 0x1 Access R R 0x1 R 0x0 RC 0x0 RC 0x0 R 0x0 RC 0x0 RC 0x0 RC 0x0 R 0x0 RC 0x0 RC Master Status Register Address: 0x40003404, Reset: 0x6000, Name: I2C1MSTA Table 158. Bit Descriptions for I2C1MSTA Bit(s) 15 14 Bit Name RESERVED SCL_FILTERED 13 SDA_FILTERED 12 MTXUFLOW 11 MSTOP 10 LINEBUSY 9 MRXOF 8 TCOMP 7 NACKDATA 6 MBUSY 5 ALOST 4 NACKADDR Description Reserved. State of SCL line. This bit is the output of the glitch filter on SCL. SCL is always pulled high when undriven. State of SDA line. This bit is the output of the glitch filter on SDA. SDA is always pulled high when undriven. Master transmit underflow. Asserts when the I2C master ends the transaction due to Tx FIFO empty condition. This bit is asserted only when the IENMTX bit is set. Stop driven by this I2C master. Asserts when this I2C master drives a stop condition on the I2C bus. This bit, when asserted, can indicate a transaction completion, Tx underflow, Rx overflow, or a no acknowledge by the slave. This bit is different from TCOMP as this bit is not asserted when the stop condition occurs due to any other I2C master. No interrupt is generated for the assertion of this bit. However, if IENCMP is 1, every stop condition generates an interrupt and this bit can be read. When this bit is read, it clears status. Line is busy. Asserts when a START is detected on the I2C bus. Deasserts when a stop is detected on the I2C bus. Master receive FIFO overflow. Asserts when a byte is written to the receive FIFO when the FIFO is already full. When the bit is read, it clears status. Transaction complete or stop detected. Transaction complete. This bit asserts when a stop condition is detected on the I2C bus. If IENCMP is 1, an interrupt is generated when this bit asserts. This bit only asserts if the master is enabled (MASEN = 1). Use this bit to determine when it is safe to disable the master. This bit can also be used to wait for another master transaction to complete on the I2C bus when this master loses arbitration. When this bit is read, it clears status. This bit can drive an interrupt. Acknowledge not received in response to data write. This bit asserts when an acknowledge is not received in response to a data write transfer. If IENACK is 1, an interrupt is generated when this bit asserts. This bit can drive an interrupt. This bit is cleared on a read of the I2C1MSTA register. Master busy. This bit indicates that the master state machine is servicing a transaction. It is clear if the state machine is idle or another device has control of the I2C bus. Arbitration lost. This bit asserts if the master loses arbitration. If IENALOST is 1, an interrupt is generated when this bit asserts. This bit is cleared on a read of the I2C1MSTA register. This bit can drive an interrupt. Acknowledge not received in response to an address. This bit asserts if an acknowledge is not received in response to an address. If IENACK is 1, an interrupt is generated when this bit asserts. This bit is cleared on a read of the I2CMSTA register. This bit can drive an interrupt. Rev. A | Page 110 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 3 Bit Name MRXREQ 2 MTXREQ [1:0] MTXFSTA Description Master receive request. This bit asserts when there is data in the receive FIFO. If IENMRX is 1, an interrupt is generated when this bit asserts. This bit can drive an interrupt. Master transmit request. This bit asserts when the direction bit is 0 and the transmit FIFO is either empty or not full. If IENMTX is 1, an interrupt is generated when this bit asserts. This bit can drive an interrupt. Master transmit FIFO status. These two bits show the master transmit FIFO status and can be decoded as follows: 00 = FIFO empty. 10 = 1 byte in FIFO. 11 = FIFO full. UG-868 Reset 0x0 Access R 0x0 R 0x0 R Master Receive Data Register Address: 0x40003408, Reset: 0x0000, Name: I2C1MRX Table 159. Bit Descriptions for I2C1MRX Bit(s) [15:8] [7:0] Bit Name RESERVED ICMRX Description Reserved. Master receive register. This register allows access to the receive data FIFO. The FIFO can hold 2 bytes. Reset 0x0 0x0 Access R R Master Transmit Data Register Address: 0x4000340C, Reset: 0x0000, Name: I2C1MTX Table 160. Bit Descriptions for I2C1MTX Bit(s) [15:8] [7:0] Bit Name RESERVED I2CMTX Description Reserved. Master transmit register. For test and debug purposes, when read, this register returns the byte that is currently being transmitted by the master. That is, a byte written to the transmit register can be read back later when that byte is being transmitted on the line. This register allows access to the transmit data FIFO. The FIFO can hold 2 bytes. Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW 0x0 RW Reset 0x0 0x0 Access R R Master Receive Data Count Register Address: 0x40003410, Reset: 0x0000, Name: I2C1MRXCNT Table 161. Bit Descriptions for I2C1MRXCNT Bit(s) [15:9] 8 Bit Name RESERVED EXTEND [7:0] COUNT Description Reserved. Extended read. Use this bit if greater than 256 bytes are required on a read. For example, to receive 412 bytes, write 0x100 (EXTEND = 1) to the I2CMRXCNT register. Wait for the first byte to be received, then check the I2CMCRXCNT register for every byte received thereafter. When COUNT returns to 0, 256 bytes have been received. Then, write 0x09C to the I2CMRXCNT register. Receive count. Program the number of bytes required minus one to this register. If just 1 byte is required, write 0 to this register. If greater than 256 bytes are required, use EXTEND. Master Current Receive Data Count Register Address: 0x40003414, Reset: 0x0000, Name: I2C1MCRXCNT Table 162. Bit Descriptions for I2C1MCRXCNT Bit(s) [15:8] [7:0] Bit Name RESERVED COUNT Description Reserved. Current receive count. This register gives the total number of bytes received so far. If 256 bytes are requested, this register reads 0 when the transaction has completed. Rev. A | Page 111 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual First Master Address Byte Register Address: 0x40003418, Reset: 0x0000, Name: I2C1ADR0 Table 163. Bit Descriptions for I2C1ADR0 Bit(s) [15:8] [7:0] Bit Name RESERVED ADR0 Description Reserved. Address byte 0. If a 7-bit address is required, Bit 7 to Bit 1 of ADR0 are programmed with the address and Bit 0 of ADR0 is programmed with the direction ( 0 = write, 1 = read ). If a 10-bit address is required, Bit 7 to Bit 3 of ADR0 are programmed with 11110, Bit 2 to Bit 1 of ADR0 are programmed with the 2 MSBs of the address, and Bit 0 of ADR0 is programmed to 0. Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW Reset 0x1F Access RW 0x1F RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 0x0 RW RW Second Master Address Byte Register Address: 0x4000341C, Reset: 0x0000, Name: I2C1ADR1 Table 164. Bit Descriptions for I2C1ADR1 Bit(s) [15:8] [7:0] Bit Name RESERVED ADR1 Description Reserved. Address byte 1. This register is only required when addressing a slave with a 10-bit address. Bit 7 to Bit 0 of ADR1 are programmed with the lower 8 bits of the address. Serial Clock Period Divisor Register Address: 0x40003424, Reset: 0x1F1F, Name: I2C1DIV Table 165. Bit Descriptions for I2C1DIV Bit(s) [15:8] Bit Name HIGH [7:0] LOW Description Serial clock high time. This register controls the clock high time. The core clock (PCLK) drives the timer. Use the following equation to derive the required high time. HIGH = (REQD_HIGH_TIME/PCLK_PERIOD) − 2 For example, to generate a 400 kHz SCL with a low time of 1300 ns and a high time of 1200 ns, with a core clock frequency of 50 MHz, LOWTIME = 1300 ns/20 ns − 1 = 0x40 (64 decimal) HIGH = 1200 ns/20 ns − 2 = 0x3A (58 decimal). This register is reset to 0x1F, which gives an SCL high time of 33 PCLK ticks. tHD:STA is also determined by the HIGH value. tHD:STA = (HIGH − 1) × PCLK_PERIOD Because tHD:STA must be 600 ns, with PCLK = 50 MHz, the minimum value for HIGH is 31. This gives an SCL high time of 660 ns. Serial clock low time. This register controls the clock low time. The core clock (PCLK) drives the timer. Use the following equation to derive the required low time. LOW = (REQD_LOW_TIME/PCLK_PERIOD) − 1 This register is reset to 0x1F, which gives an SCL low time of 32 PCLK ticks. Slave Control Register Address: 0x40003428, Reset: 0x0000, Name: I2C1SCON Table 166. Bit Descriptions for I2C1SCON Bit(s) 15 14 Bit Name RESERVED STXDMA 13 SRXDMA 12 IENREPST 11 10 RESERVED IENSTX Description Reserved. Enable slave Tx DMA request. Set to 1 by user code to enable I2C slave DMA Rx requests. Cleared by user code to disable DMA mode. Enable slave Rx DMA request. Set to 1 by user code to enable I2C slave DMA Rx requests. Cleared by user code to disable DMA mode. Repeated start interrupt enable. If 1, an interrupt is generated when the REPSTART status bit asserts. If 0, an interrupt is not generated when the REPSTART status bit asserts. Reserved. Slave transmit request interrupt enable. Rev. A | Page 112 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 9 8 7 Bit Name IENSRX IENSTOP NACK 6 5 RESERVED EARLYTXR 4 GCSBCLR 3 HGCEN 2 GCEN 1 ADR10EN 0 SLVEN Description Slave receive request interrupt enable. Stop condition detected interrupt enable. No acknowledge next communication. If this bit is set, the next communication is not acknowledged. This NACK can be used, for example, if during a 24xx style access an attempt was made to write to a read only or nonexistent location in system memory; that is, the indirect address in a 24xx style write pointed to an unwriteable memory location. Reserved. A value of 0 must be written to this bit. Early transmit request mode. Setting this bit enables a transmit request just after the positive edge of the direction bit SCL clock pulse. General call status bit clear. The general call status and general call ID bits are cleared when a 1 is written to this bit. The general call status and general call ID bits are not reset by anything other than a write to this bit or a full reset. Hardware general call enable. When this bit and the general call enable bit are set the device after receiving a general call, Address 00h, and a data byte checks the contents of the ALT against the receive shift register. If they match, the device has received a hardware general call. This call is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a to whom it may concern call. The device that requires attention embeds its own address into the message. The LSB of the ALT register must always be written to a 1, as per I2C January 2000 specification. General call enable. This bit enables the I2C slave to acknowledge an I2C general call, Address 0x00 (write). Enabled 10-bit addressing. If this bit is clear, the slave can support four slave addresses, programmed in Register I2CID0 to Register I2CID3. When this bit is set, 10-bit addressing is enabled. One 10-bit address is supported by the slave and is stored in I2CID0 and I2CID1, where I2CID0 contains the first byte of the address, and the upper 5 bits must be programmed to 11110. I2CID3 and I2CID4 can be programmed with bit addresses at the same time. Slave enable. When 1, the slave is enabled. When 0, all slave state machine flops are held in reset and the slave is disabled. UG-868 Reset 0x0 0x0 0x0 Access RW RW RW 0x0 0x0 RW RW 0x0 W 0x0 RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access R R 0x0 RC 0x0 R 0x0 RC 0x0 R Slave I2C Status/Error/IRQ Register Address: 0x4000342C, Reset: 0x0001, Name: I2C1SSTA Table 167. Bit Descriptions for I2C1SSTA Bit(s) 15 14 Bit Name RESERVED START 13 REPSTART [12:11] IDMAT 10 STOP [9:8] GCID Description Reserved. Start and matching address. This bit is asserted if a start is detected on SCL/SDA and the device address matched; if a general call (address = 0000_0000) code is received and general call is enabled; if a high speed (address = 0000_1XXX) code is received; or if a start byte (0000_0001) is received. It is cleared on receipt of either a stop or start condition. Repeated start and matching address. This bit is asserted if start is already asserted and then a repeated start is detected. It is cleared when read or on receipt of a stop condition. This bit can drive an interrupt. Device ID matched. 00: received address matched ID Register 0. 01: received address matched ID Register 1. 10: received address matched ID Register 2. 11: received address matched ID Register 3. Stop after start and matching address. It gets set by hardware if the slave device received a stop condition after a previous start condition and a matching address. Cleared by a read of the status register. If STOPINTEN in the slave control register is asserted, the slave interrupt request asserts when this bit is set. This bit can drive an interrupt. General ID. GCID is cleared when the GCSBCLR is written to 1. These status bits are not cleared by a general call reset. 00: no general call. 01: general call reset and program address. 10: general call program address. 11: general call matching alternative ID. Rev. A | Page 113 of 190 UG-868 Bit(s) 7 Bit Name GCINT 6 SBUSY 5 NOACK 4 SRXOF 3 SRXREQ 2 STXREQ 1 STXUR 0 STXFSEREQ ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description General call interrupt. This bit always drives an interrupt. The bit is asserted if the slave device receives a general call of any type. To clear, write 1 to the GCSBCLR in the slave control register. If it was a general call reset, all registers are at their default values. If it was a hardware general call, the Rx FIFO holds the second byte of the general call, and this can be compared with the ALT register. Slave busy. Set by hardware if the slave device receives an I2C start condition. Cleared by hardware when the address does not match an ID register, the slave device receives an I2C stop condition, or if a repeated start address does not match. Acknowledge not generated by the slave. When asserted, it indicates that the slave responded to its device address with a no acknowledge. It is asserted if there was no data to transmit and sequence was a slave read or if the NACK bit was set in the slave control register and the device was addressed. This bit is cleared on a read of the I2CSSTA register. Slave receive FIFO overflow. Asserts when a byte is written to the slave receive FIFO when the FIFO is already full. Slave receive request. SRXREQ asserts whenever the slave receive FIFO is not empty. Read or flush the slave receive FIFO to clear this bit. This bit asserts on the falling edge of the SCL clock pulse that clocks in the last data bit of a byte. This bit can drive an interrupt. Slave transmit request. If EARLYTXR = 0, STXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit remains asserted. Initially, it is asserted on the negative edge of the SCL pulse that clocks in the direction bit (if the device address matched also). If EARLYTXR = 1, STXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full this bit remains asserted. Initially, it is asserted after the positive edge of the SCL pulse that clocks in the direction bit (if the device address matched also). This bit is cleared on a read of the I2CSSTA register. Slave transmit FIFO underflow. Is set if a master requests data from the device, and the Tx FIFO is empty for the rising edge of SCL. Slave Tx FIFO status or early request. If EARLYTXR = 0, this bit is asserted whenever the slave Tx FIFO is empty. If EARLYTXR = 1, STXFSEREQ is set when the direction bit for a transfer is received high. It asserts on the positive edge of the SCL clock pulse that clocks in the direction bit (if the device address matched also). It only asserts once for a transfer. It is cleared when read if EARLYTXR is asserted. Reset 0x0 Access R 0x0 R 0x0 RC 0x0 RC 0x0 RC 0x0 RC 0x0 RC 0x1 RW Reset 0x0 0x0 Access R R Reset 0x0 0x0 Access R RW Slave Receive Register Address: 0x40003430, Reset: 0x0000, Name: I2C1SRX Table 168. Bit Descriptions for I2C1SRX Bit(s) [15:8] [7:0] Bit Name RESERVED I2CSRX Description Reserved Slave receive register Slave Transmit Register Address: 0x40003434, Reset: 0x0000, Name: I2C1STX Table 169. Bit Descriptions for I2C1STX Bit(s) [15:8] [7:0] Bit Name RESERVED I2CSTX Description Reserved Slave transmit register Rev. A | Page 114 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Hardware General Call ID Register Address: 0x40003438, Reset: 0x0000, Name: I2C1ALT Table 170. Bit Descriptions for I2C1ALT Bit(s) [15:8] [7:0] Bit Name RESERVED ALT Description Reserved. Slave Alt. This register is used in conjunction with I2CSCON[3] to match a master generating a hardware general call. It is used in the case where a master device cannot be programmed with the address of a slave and instead the slave must recognize the address of the master. Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW Reset 0x0 0x0 Access R RW First Slave Address Device ID Register Address: 0x4000343C, Reset: 0x0000, Name: I2C1ID0 Table 171. Bit Descriptions for I2C1ID0 Bit(s) [15:8] [7:0] Bit Name RESERVED ID0 Description Reserved. Slave Device ID 0. I2CID0[7:1] is programmed with the device ID. I2CID0[0] is don't care. See the ADR10EN bit in the slave control register to see how this register is programmed with a 10-bit address. Second Slave Address Device ID Register Address: 0x40003440, Reset: 0x0000, Name: I2C1ID1 Table 172. Bit Descriptions for I2C1ID1 Bit(s) [15:8] [7:0] Bit Name RESERVED ID1 Description Reserved. Slave Device ID 1. I2CID1[7:1] is programmed with the device ID. I2CID1[0] is don't care. See the ADR10EN bit in the slave control register to see how this register is programmed with a 10-bit address. Third Slave Address Device ID Register Address: 0x40003444, Reset: 0x0000, Name: I2C1ID2 Table 173. Bit Descriptions for I2C1ID2 Bit(s) [15:8] [7:0] Bit Name RESERVED ID2 Description Reserved. Slave Device ID 2. I2CID2[7:1] is programmed with the device ID. I2CID2[0] is don't care. See the ADR10EN bit in the slave control register to see how this register is programmed with a 10-bit address. Fourth Slave Address Device ID Register Address: 0x40003448, Reset: 0x0000, Name: I2C1ID3 Table 174. Bit Descriptions for I2C1ID3 Bit(s) [15:8] [7:0] Bit Name RESERVED ID3 Description Reserved. Slave Device ID 3. I2CID3[7:1] is programmed with the device ID. I2CID3[0] is don't care. See the ADR10EN bit in the slave control register to see how this register is programmed with a 10-bit address. Rev. A | Page 115 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Master and Slave FIFO Status Register Address: 0x4000344C, Reset: 0x0000, Name: I2C1FSTA Table 175. Bit Descriptions for I2C1FSTA Bit(s) [15:10] 9 Bit Name RESERVED MFLUSH 8 SFLUSH [7:6] MRXFSTA [5:4] MTXFSTA [3:2] SRXFSTA [1:0] STXFSTA Description Reserved. Flush the master transmit FIFO. 0: clearing to 0 has no effect. 1: set to 1 to flush the master transmit FIFO. The master transmit FIFO must be flushed if arbitration is lost or a slave responds with a no acknowledge. Flush the slave transmit FIFO. 0: clearing to 0 has no effect. 1: set to 1 to flush the slave transmit FIFO. Master receive FIFO status. The status is a count of the number of bytes in a FIFO. 00: FIFO empty. 01: 1 byte in the FIFO. 10: 2 bytes in the FIFO. 11: reserved. Master transmit FIFO status. The status is a count of the number of bytes in a FIFO. 00: FIFO empty. 01: 1 byte in the FIFO. 10: 2 bytes in the FIFO. 11: reserved. Slave receive FIFO status. The status is a count of the number of bytes in a FIFO. 00: FIFO empty. 01: 1 byte in the FIFO. 10: 2 bytes in the FIFO. 11: reserved. Slave transmit FIFO status. The status is a count of the number of bytes in a FIFO. 00: FIFO empty. 01: 1 byte in the FIFO. 10: 2 bytes in the FIFO. 11: reserved. Reset 0x0 0x0 Access RW W 0x0 W 0x0 R 0x0 R 0x0 R 0x0 R Reset 0x0000 0x0 Access RW W Master and Slave Shared Control Register Address: 0x40003450, Reset: 0x0000, Name: I2C1SHCON Table 176. Bit Descriptions for I2C1SHCON Bit(s) [15:1] 0 Bit Name RESERVED RESET Description Reserved. Write a 1 to this bit to reset the I2C start and stop detection circuits. Setting this bit resets the LINEBUSY status bit. Rev. A | Page 116 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Automatic Stretch Control Register Address: 0x40003458, Reset: 0x0000, Name: I2C1ASSCL Table 177. Bit Descriptions for I2C1ASSCL Bit(s) [15:10] 9 Bit Name RESERVED SSRTSTA 8 MSRTSTA [7:4] SSTRCON Description Reserved. Stretch timeout status bit for slave. Set when slave automatic stretch mode has timed out. Cleared when this bit is read. Stretch timeout status bit for master. Set when master automatic stretch mode has timed out. Cleared when this bit is read. Automatic stretch mode control for slave. These bits control automatic stretch mode for slave operation. SSTRCON allows the slave to hold the SCL line low and gain more time to service an interrupt, load a FIFO, or read a FIFO. Use the timeout feature to avoid a bus lockup condition where the slave indefinitely holds SCL low. As a slave transmitter, SCL is automatically stretched from the negative edge of SCL if the slave Tx FIFO is empty before sending acknowledge/no acknowledge for address byte, or before sending data for a data byte. Stretching stops when the slave Tx FIFO is no longer empty or a timeout occurs. As a slave receiver, SCL clock is automatically stretched from the negative edge of SCL, when the slave Rx FIFO is full, before sending acknowledge/no acknowledge. Stretching stops when the slave Rx FIFO is no longer in an overflow condition or a timeout occurs. 0000: automatic slave clock stretching disabled. 0001 to 1110: automatic slave clock stretching enabled. The timeout period is defined by I2C0DIV[15 : 8] + I2C0DIV[7 : 4] − 1 UCLK/CLKCON[10 : 8] [3:0] MSTRCON ( × 2I2C0ASSCL[7: 4] UCLK/CLKCON[10 : 8] ( × 2I2C0ASSCL[3:0] ) 1111: automatic master clock stretching enabled with indefinite timeout period. Rev. A | Page 117 of 190 Access R R 0x0 R 0x0 RW 0x0 RW ) Note that the I2C bus baud rate has no influence on the slave stretch timeout period. 1111: automatic slave clock stretching enabled with indefinite timeout period. Automatic stretch mode control for master. These bits control automatic stretch mode for master operation. MSTRCON allows the master to hold the SCL line low and gain more time to service an interrupt, load a FIFO, or read a FIFO. Use the timeout feature to avoid a bus lockup condition where the master indefinitely holds SCL low. As a master transmitter, SCL is automatically stretched from the negative edge of SCL if the master Tx FIFO is empty before sending acknowledge/no acknowledge for address byte, or before sending data for a data byte. Stretching stops when the master Tx FIFO is no longer empty or, a timeout occurs. As a master receiver, SCL clock is automatically stretched from the negative edge of SCL, when master Rx FIFO is full, before sending acknowledge/no acknowledge. Stretching stops when master Rx FIFO is no longer in an overflow condition or, a timeout occurs. 0000: automatic master clock stretching disabled. 0001 to 1110: automatic master clock stretching enabled. The timeout period is defined by I2C0DIV[15 : 8] + I2C0DIV[7 : 4] − 1 Reset 0x0 0x0 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual SERIAL PERIPHERAL INTERFACES SPI FEATURES The ADuCM320i/ADuCM322/ADuCM322i integrate two complete hardware serial peripheral interfaces (SPI) with the following standard SPI features: • • • • • • • • • • • Serial clock phase mode and serial clock polarity mode LSB first transfer option Loopback mode Master or slave mode Transfer and interrupt mode Continuous transfer mode Tx/Rx FIFO Interrupt mode, interrupt after one, two, three, or four bytes Rx overflow mode and Tx underrun mode Open-circuit data output mode Full duplex communications supported (simultaneous transmit/receive) SPI OVERVIEW The ADuCM320i/ADuCM322/ADuCM322i integrates two complete hardware serial peripheral interfaces. SPI is an industry-standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex. The two SPIs implemented on the ADuCM320i/ADuCM322/ADuCM322i can operate to a maximum bit rate of 20 Mbps in both master and slave modes. The SPI blocks have an additional DMA feature. Each SPI block has two DMA channels that interface with a µDMA controller of the ARM Cortex-M3 processor. One DMA channel is used for transmitting data, and the other is used for receiving data. SPI OPERATION The SPI port can be configured for master or slave operation and consists of four pins: MISO, MOSI, SCLK, and CS0/CS1. Note that the GPIOs used for SPI communication must be configured in SPI mode before enabling the SPI peripheral, and that the internal pull-up resistors on the SPI pins must be disabled via the GPxPUL registers when using the SPI. Master In, Slave Out (MISO) Pin The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) must be connected to the MISO line in the slave device (data out). The data is transferred as byte-wide (8-bit) serial data, MSB first. Master Out, Slave In (MOSI) Pin The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) must be connected to the MOSI line in the slave device (data in). The data is transferred as byte-wide (8-bit) serial data, MSB first. Serial Clock Input/Output (SCLK) Pin The master serial clock (SCLK) synchronizes the data being transmitted and received through the MOSI SCLK period. Therefore, a byte is transmitted/received after eight SCLK periods. SCLK is configured as an output in master mode and as an input in slave mode. In master mode, the SPIxCON register controls the polarity and phase of the clock, and the bit rate is defined in the SPIxDIV register as follows: f SERIALCLOCK = SPICLK 2 × (1 + SPIxDIV[5 : 0]) where SPICLK is the 80 MHz system clock divided by the factor set in the CLKCON1[2:0] bits. It is possible to disable the clocks to SPI0 and SPI1 separately: • • CLKCON5[0] = 1 disables the clock to SPI0. CLKCON5[1] = 1 disables the clock to SPI1. By reducing the clock rate to the SPI blocks, it is possible to reduce the power consumption of the SPI block. The maximum data rate is 20 Mbps. Rev. A | Page 118 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 In slave mode, the SPIxCON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 20 Mbps. In both master and slave mode, data is transmitted on one edge of the SCLK signal and sampled on the other. Therefore, it is important that the polarity and phase be configured the same for the master and slave devices. Chip Select (CS0/CS1) Input Pin In SPI slave mode, a transfer is initiated by the assertion of CS0/CS1, which is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by deassertion of CS0/CS1. In slave mode, CS0/CS1 is always an input. In SPI master mode, CS0/CS1 is an active low output signal. It asserts itself automatically at the beginning of a transfer and deasserts itself upon completion. CS0/CS1 must always be configured as an SPI pin in GPxCON when the SPI is used. If an ADuCM320i/ADuCM322/ADuCM322i master wants to communicate with multiple SPI slaves, CS0/CS1 must be left floating, and the GPIOs can be connected to the CS0/CS1 lines of the slaves. The CSRSG and CSFLG bits (SPIxSTA[14] and SPIxSTA[13], respectively) can be used to determine when to pull the GPIOs low or high. SPI TRANSFER INITIATION In master mode, the transfer and interrupt mode bit, TIM (SPIxCON[6]), determines the manner in which an SPI serial transfer is initiated. If the TIM bit is set, a serial transfer is initiated after a write to the Tx FIFO. If the TIM bit is cleared, a serial transfer is initiated after a read of the Rx FIFO; the read must be done while the SPI interface is idle. A read done during an active transfer does not initiate another transfer. For any setting of SPIxCON[1] and SPIxCON[6], the SPI simultaneously receives and transmits data. Therefore, during data transmission, the SPI is also receiving data and filling up the Rx FIFO. If the data is not read from the Rx FIFO, the overflow interrupt occurs when the FIFO starts to overflow. If the user does not want to read the Rx data or receive overflow interrupts, SPIxCON[12] can be set and the receive data is not saved to the Rx FIFO. Similarly, when the user wants to only receive data and does not want to write data to the Tx FIFO, SPIxCON[13] can be set to avoid receiving underrun interrupts from the Tx FIFO. Tx Initiated Transfer For transfers initiated by a write to the Tx FIFO, the SPI starts transmitting as soon as the first byte is written to the FIFO, irrespective of the configuration in SPIxCON[15:14]. The first byte is immediately read from the FIFO, written to the Tx shift register, and the transfer commences. If the continuous transfer enable bit, SPIxCON[11], is set, the transfer continues until no valid data is available in the Tx FIFO. There is no stall period between transfers where CS0/CS1 is deasserted; CS0/CS1 is asserted and remains asserted for the duration of the transfer until the Tx FIFO is empty. Determining when the transfer stops does not depend on SPIxCON[15:14]; the transfer stops when there is no valid data left in the FIFO. Conversely, the transfer continues while there is valid data in the FIFO. If the continuous transfer enable bit, SPIxCON[11], is cleared, each transfer consists of a single 8-bit serial transfer. If valid data exists in the Tx FIFO, a new transfer is initiated after a stall period where CS0/CS1 is deasserted. Rx Initiated Transfer Transfers initiated by a read of the Rx FIFO depend on the number of bytes received in the FIFO. If SPIxCON[15:14] = 11 and a read to the Rx FIFO occurs, the SPI initiates a 4-byte transfer. If continuous mode is set, the four bytes occur continuously with no deassertion of CS0/CS1 between bytes. If continuous mode is not set, the four bytes occur with stall periods between transfers where CS0/CS1 is deasserted. A read of the Rx FIFO while the SPI is receiving data does not initiate another transfer after the present transfer is complete. In slave mode, a transfer is initiated by the assertion of CS0/CS1 (CS0/CS1 = 0). The device as a slave transmits and receives 8-bit data until the transfer is concluded by the deassertion of CS0/CS1 (CS0/CS1 = 1). The SPI transfer protocol diagrams (see Figure 24 and Figure 25) illustrate the data transfer protocol for the SPI and the effects of the CPHA and CPOL bits in the control register (SPIxCON) on that protocol. Rev. A | Page 119 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual CLOCK CYCLE NUMBER 1 2 3 4 5 6 7 8 SPI CLOCK (CPOL = 0) SPI CLOCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) XX XX MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB XX LSB XX t1 t2 t3 13437-025 CS0/CS1 Figure 24. SPI Transfer Protocol, CPHA = 0 CLOCK CYCLE NUMBER 1 2 3 4 5 6 7 8 SPI CLOCK (CPOL = 0) SPI CLOCK (CPOL = 1) MISO (FROM SLAVE) XX XX MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB XX XX CS0/CS1 t1 t2 t3 13437-026 MOSI (FROM MASTER) Figure 25. SPI Transfer Protocol, CPHA = 1 SPI Data Underrun and Overflow If the transmit zeros enable bit, ZEN (SPIxCON[7]), is cleared, the last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. If the ZEN bit is set to 1, 0s are transmitted when a transfer is initiated with no valid data in the FIFO. If the Rx overflow overwrite enable bit, RXOF (SPIxCON[8]), is set, the valid data in the Rx FIFO is overwritten by the new serial byte received if there is no space left in the FIFO. If the RXOF bit is cleared, the new serial byte received is discarded if there is no space left in the FIFO. When the RXOF bit is set, the contents of the SPI Rx FIFO are undefined, and its contents must be discarded by user code. Full Duplex Operation Simultaneous reads/writes are supported on the SPI. When implementing full duplex transfers in master mode, use the following procedure: 1. 2. 3. 4. Initiate a transfer sequence via a transmit on the MOSI pin. Set SPIxCON[6] = 1. If interrupts are enabled, interrupts are triggered when a transmit interrupt occurs but not when a byte is received. If using interrupts, the SPI Tx interrupt indicated by SPIxSTA[5] or the Tx FIFO underrun interrupt (SPIxSTA[4]) is asserted approximately 3 SPICLK to 4 SPICLK periods into the transfer of the first byte. Reload a byte into the Tx FIFO, if necessary, by writing to SPIxTX. The first byte received via the MISO pin does not update the Rx FIFO status bits (SPIxSTA[10:8]) until 12 SPICLK periods after CS0/CS1 goes low. Therefore, two transmit interrupts may occur before the first receive byte is ready to be handled. After the last transmit interrupt occurs, it may be necessary to read two more bytes. It is recommended that SPIxSTA[10:8] be polled outside of the SPI interrupt handler after the last transmit interrupt is handled. Rev. A | Page 120 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 SPI INTERRUPTS There is one interrupt line per SPI and four sources of interrupts. SPIxSTA[0] reflects the state of the interrupt line, and SPIxSTA[7:4] reflects the state of the four sources. The SPI generates either TIRQ or RIRQ. Both interrupts cannot be enabled at the same time. The appropriate interrupt is enabled using the TIM bit, SPIxCON[6]. If TIM = 1, TIRQ is enabled. If TIM = 0, RIRQ is enabled. In addition, note that the SPI0 and SPI1 interrupt source must be enabled in the NVIC register as follows: ISER0[19] = SPI0, ISER0[20] = SPI1. Tx Interrupt If TIM (SPIxCON[6]) is set, the Tx FIFO status causes the interrupt. The SPIxCON[15:14] bits control when the interrupt occurs, as shown in Table 178. Table 178. SPIxCON[15:14] IRQ Mode Bits SPIxCON[15:14] 00 01 10 11 Interrupt Condition An interrupt is generated after each byte that is transmitted. The interrupt occurs when the byte is read from the FIFO and written to the shift register. An interrupt is generated after every two bytes that are transmitted. An interrupt occurs after every third byte that is transmitted. An interrupt occurs after every fourth byte that is transmitted. The interrupts are generated depending on the number of bytes transmitted and not on the number of bytes in the FIFO, which is unlike the Rx interrupt that depends on the number of bytes in the Rx FIFO and not on the number of bytes received. The transmit interrupt is cleared by a read to the status register. The status of this interrupt can be read by reading SPIxSTA[5]. The interrupt is disabled if SPIxCON[13] is left high. A write to the control register, SPIxCON, resets the transmitted byte counter back to 0. For example, in a case where SPIxCON[15:14] is set to 0x3 and SPIxCON is written to after three bytes are transmitted, the Tx interrupt does not occur until another four bytes are transmitted. Rx Interrupt If the TIM bit (SPIxCON[6]) is cleared, the Rx FIFO status causes the interrupt. The SPIxCON[15:14] bits control when the interrupt occurs. The interrupt is cleared by a read of the SPIxSTA register. The status of this interrupt can be read by reading SPIxSTA[6]. Interrupts are only generated when data is written to the FIFO. For example, if the SPIxCON[15:14] bits are set to 0x00, an interrupt is generated after the first byte is received. When the status register is read, the interrupt is deactivated. If the byte is not read from the FIFO, the interrupt is not regenerated. Another interrupt is not generated until another byte is received in the FIFO. The interrupt depends on the number of valid bytes in FIFO and not on the number of bytes received. For example, when the SPIxCON[15:14] bits are set to 0x1, an interrupt is generated after a byte is received if there are two or more bytes in the FIFO. The interrupt is not generated after every two bytes received. The interrupt is disabled if SPIxCON[12] is left high. Underrun/Overflow Interrupts SPIxSTA[7] and SPIxSTA[4] generate SPI interrupts. When a transfer starts with no data in the Tx FIFO, SPIxSTA[4] is set to indicate an underrun condition, which causes an interrupt. The interrupt and status bit are cleared upon a read of the status register. This interrupt occurs irrespective of SPIxCON[15:14]. This interrupt is disabled if SPIxCON[13] is set. When data is received and the Rx FIFO is already full, SPIxSTA[7] is set to 1, indicating an overflow condition, which causes an interrupt. The interrupt and status bit are cleared upon a read of the status register. This interrupt occurs irrespective of SPIxCON[15:14]. This interrupt is disabled if SPIxCON[12] is set. When the SPI Rx overflow bit (SPIxSTA[7]) is set to 1, the contents of the SPI Rx FIFO are undetermined and must not be used. The user must flush the Rx FIFO upon detecting this error condition. All interrupts are cleared either by a read of the status register or when SPIxCON[0] is deasserted. The Rx and Tx interrupts are also cleared if the relevant flush bits are asserted. Otherwise, the interrupts remain active even if the SPI is reconfigured. Rev. A | Page 121 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual SPI WIRE-OR’ED MODE (WOM) To prevent contention when the SPI is used in a multimaster or multislave system, the data output pins, MOSI and MISO, can be configured to behave as open-circuit drivers. An external pull-up resistor is required when this feature is selected. The WOM bit (SPIxCON[4]) controls the pad enable outputs for the data lines. SPI CSERR CONDITION The CSERR bit (SPIxSTA[12]) indicates if an erroneous deassertion of the CS0/CS1 signal has been detected before the completion of all 8 SCLK cycles. This bit generates an interrupt and is available in all modes of operation: slave, master, and during DMA transfers. If an interrupt generated by the CSERR bit (SPIxSTA[12]) occurs, the SPI ENABLE bit (SPIxCON[0]) must be disabled and restarted to enable a clean recovery to ensure that subsequent transfers are error free. The BCRST bit (SPIxDIV[7]) must be set at all times in both slave mode and master mode except when a midbyte stall in SPI communication is required. In this case, the CSERR flag is set but can be ignored. TRANSMIT DATA 8 BITS 5 BITS 3 BITS DATA 0 DATA 1 DATA 1 8 BITS DATA 2 SPIxDIV[7] BCRST = 0 IGNORE CSERR (SPIxSTA[12]) 13437-027 CS0/CS1 Figure 26. SPI Communication: Midbyte Stall Note that the SPI must only be reenabled when the CS0/CS1 signal is high. SPI DMA DMA operation is provided on both SPI channels. Two DMA channels are dedicated to transmit and receive. The SPI DMA channels must be configured in the µDMA controller of the ARM Cortex-M3 processor. It is possible to enable a DMA request on one or two channels at the same time by setting the DMA request bits for receive or transmit in the SPIxDMA register. If only the DMA transmit request (SPIxDMA[1]) is enabled, the Rx FIFO overflows during an SPI transfer, unless the received data is read by user code, and an overflow interrupt is generated. To avoid generating overflow interrupts, the Rx FIFO flush bit must be set or the SPI interrupt should be disabled in the NVIC. If only the DMA receive request (SPIxDMA[2]) is enabled, the Tx FIFO is underrun. To avoid an underrun interrupt, the SPI interrupt must be disabled. The SPI Tx (SPIxSTA[5]) and SPI Rx (SPIxSTA[6]) interrupts are not generated when using DMA. The SPI TXUR (SPIxSTA[4]) and RXOF (SPIxSTA[7]) interrupts are generated when using DMA. The SPIxCON[15:14] bits are not used in transmit mode and must be set to 0x00 in receive mode. The enable bit (SPIxDMA[0]) controls the start of a DMA transfer. DMA requests are only generated when enable = 1. At the end of a DMA transfer, that is, when receiving a DMA SPI transfer interrupt, this bit must be cleared to prevent extra DMA requests to the µDMA controller. The data still present in the Tx FIFO is transmitted if in Tx mode. DMA Master Transmit Configuration The DMA SPI Tx channel must be configured. The NVIC should be configured to enable DMA Tx master interrupt (for example, enable DMA Tx master interrupt SPI0 Tx using ISER0[26]). When all data present in the DMA buffer are transmitted, the DMA generates an interrupt. User code should disable the DMA request. Data is still in the Tx FIFO because the DMA request is generated each time there is free space in the Tx FIFO to always keep the FIFO full. User code can check how many bytes are still present in the FIFO in the FIFO status register. DMA Master Receive Configuration The SPIxCNT register is available in DMA receive master mode only. It sets the number of receive bytes required by the SPI master or the number of clocks that the master needs to generate. When the required number of bytes are received, no more transfers are initiated. To initiate a DMA master receive transfer, complete a dummy read by user code. Add this dummy read to the SPIxCNT number. The counter counting the bytes as they are received is reset either when SPI is disabled in SPIxCON[0] or if the SPIxCNT register is modified by user code. Rev. A | Page 122 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Performing SPIx DMA Master Receive The DMA SPI Rx channel must be configured. The NVIC must be configured to enable DMA Rx master interrupt (for example, enable DMA Rx master interrupt SPI1 Rx using ISER0[29]). The DMA transfer stops when the number of bytes have been transferred. Note that the DMA buffer must be of the same size as SPI1CNT to generate a DMA interrupt when the transfer is complete. SPI AND POWER-DOWN MODES In master mode, before entering power-down mode, it is recommended to disable the SPI block in SPIxCON[0]. In slave mode in either mode of operation, interrupt driven or DMA, the CS0/CS1 line level must be checked via the GPIO registers to ensure that the SPI is not communicating and that the SPI block is disabled while the CS0/CS1 line is high. At power-up, the SPI block can be reenabled. Rev. A | Page 123 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: SPI0 Table 179. SPI0 Register Summary Address 0x4002C000 0x4002C004 0x4002C008 0x4002C00C 0x4002C010 0x4002C014 0x4002C018 Name SPI0STA SPI0RX SPI0TX SPI0DIV SPI0CON SPI0DMA SPI0CNT Description Status register Receive register Transmit register Baud rate selection register SPI configuration register SPI DMA enable register Transfer byte count register Reset 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 RW R R W RW RW RW RW REGISTER DETAILS: SPI0 Status Register Address: 0x4002C000, Reset: 0x0000, Name: SPI0STA Table 180. Bit Descriptions for SPI0STA Bit(s) 15 14 Bit Name RESERVED CSRSG 13 CSFLG 12 CSERR 11 RXS [10:8] RXFSTA 7 RXOF 6 RX 5 TX Description Reserved. Detected a rising edge on CS in CONT mode. This bit causes an interrupt, which can be used to identify the end of an SPI data frame. 0: cleared to 0 when the status register is read. 1: set to 1 when there was a rising edge in CS line, when the device was in master mode, continuous transfer, high frequency mode and CSIRQ_EN was asserted. Detected a falling edge on CS in CONT mode. This bit causes an interrupt, which can be used to identify the start of an SPI data frame. 0: cleared to 0 when the status register is read. 1: set to 1 when there was a falling edge in CS line, when the device was in master mode, continuous transfer, high frequency mode and CSIRQ_EN was asserted. Detected a CS error condition. 0: cleared to 0 when the status register is read. 1: set to 1 when the CS line was deasserted abruptly, even before the full byte of data was transmitted completely. This bit causes an interrupt. SPI Rx FIFO excess bytes present. 0: this bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. 1: this bit is set when there are more bytes in the Rx FIFO than indicated in the MOD bits in SPI0CON. SPI Rx FIFO status. 000: Rx FIFO empty. 001: 1 valid byte in FIFO. 010: 2 valid bytes in the FIFO. 011: 3 valid bytes in the FIFO. 100: 4 valid bytes in the FIFO. SPI Rx FIFO overflow. 0: cleared when the SPISTA register is read. 1: set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set in SPI0CON. SPI Rx IRQ. Not available in DMA mode. 0: cleared when the SPI0STA register is read. 1: set when a receive interrupt occurs. This bit is set when TIM in SPI0CON is cleared and the required number of bytes have been received. SPI Tx IRQ. Status bit. This bit is not available in DMA mode. 0: CLR. Cleared to 0 when the SPI0STA register is read. 1: SET. Set to 1 when a transmit interrupt occurs. This bit is set when TIM in SPI0CON is set and the required number of bytes have been transmitted. Rev. A | Page 124 of 190 Reset 0x0 0x0 Access R RC 0x0 RC 0x0 RC 0x0 R 0x0 R 0x0 RC 0x0 RC 0x0 RC ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 4 Bit Name TXUR [3:1] TXFSTA 0 IRQ Description SPI Tx FIFO underflow. 0: cleared to 0 when the SPI0STA register is read. 1: set to 1 when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI0CON. SPI Tx FIFO status. 000: Tx FIFO empty. 001: 1 valid byte in FIFO. 010: 2 valid bytes in FIFO. 011: 3 valid bytes in FIFO. 100: 4 valid bytes in FIFO. SPI interrupt status. 0: cleared to 0 after reading SPI0STA. 1: set to 1 when an SPI based interrupt occurs. UG-868 Reset 0x0 Access RC 0x0 R 0x0 RC Reset 0x0 Access R 0x0 R Reset 0x0 Access W 0x0 W Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW Receive Register Address: 0x4002C004, Reset: 0x0000, Name: SPI0RX Table 181. Bit Descriptions for SPI0RX Bit(s) [15:8] Bit Name DMA_DATA_BYTE_2 [7:0] DATA_BYTE_1 Description 8-bit receive buffer. These 8 bits are used only in DMA mode, where all FIFO accesses happen as half-word access. They return zeros if DMA is disabled. 8-bit receive buffer. Transmit Register Address: 0x4002C008, Reset: 0x0000, Name: SPI0TX Table 182. Bit Descriptions for SPI0TX Bit(s) [15:8] Bit Name DMA_DATA_BYTE_2 [7:0] DATA_BYTE_1 Description 8-bit transmit buffer. These 8 bits are used only in DMA mode, where all FIFO accesses happen as half-word access. They return zeros if DMA is disabled. 8-bit transmit buffer. Baud Rate Selection Register Address: 0x4002C00C, Reset: 0x0000, Name: SPI0DIV Table 183. Bit Descriptions for SPI0DIV Bit(s) [15:9] 8 Bit Name RESERVED CSIRQ_EN 7 BCRST 6 HFM [5:0] DIV Description Reserved. Enable interrupt on every CS edge in CONT mode. If this bit is set and the SPI module is in continuous mode, any edge on CS generates an interrupt, and the corresponding status bits (CSRSG, CSFLG) are asserted. If this bit is clear, no interrupt is generated. This bit has no effect if the SPI is not in continuous mode. Reset mode for CSERR. If this bit is set, the bit counter is reset after a CS error condition and the Cortex is expected to clear the SPI enable bit. If this bit is clear, the bit counter continues from where it stopped. SPI can receive the remaining bits when CS gets asserted, and Cortex has to ignore the CSERR interrupt. However, it is strongly recommended to set this bit for a graceful recovery after a CS error. High frequency mode. This bit is used for applications using high frequency where the pad introduces a significant delay on the SCL, which can cause a significant enough difference between the serial clock and the data being received on the Rx shift register. In this mode, the Rx shift register is clocked by SCL instead of UCLK. SPI clock divider. DIV is the factor used to divide UCLK to generate the serial clock. Rev. A | Page 125 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual SPI Configuration Register Address: 0x4002C010, Reset: 0x0000, Name: SPI0CON Table 184. Bit Descriptions for SPI0CON Bit(s) [15:14] Bit Name MOD 13 TFLUSH 12 RFLUSH 11 CON 10 LOOPBACK 9 OEN 8 RXOF 7 ZEN 6 TIM 5 LSB 4 WOM Description SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. For DMA Rx transfer, these bits must be 00. 00: Tx interrupt occurs when 1 byte has been transferred. Rx interrupt occurs when 1 or more bytes have been received into the FIFO. 01: Tx interrupt occurs when 2 bytes has been transferred. Rx interrupt occurs when 2 or more bytes have been received into the FIFO. 10: Tx interrupt occurs when 3 bytes has been transferred. Rx interrupt occurs when 3 or more bytes have been received into the FIFO. 11: Tx interrupt occurs when 4 bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or 4 bytes present. SPI Tx FIFO flush enable. 0: clear this bit to disable Tx FIFO flushing. 1: set this bit to flush the Tx FIFO. This bit does not clear itself and must be toggled if a single flush is required. If this bit is left high, either the last transmitted value or 0x00 is transmitted depending on the ZEN bit. Any writes to the Tx FIFO are ignored while this bit is set. SPI Rx FIFO flush enable. 0: clear this bit to disable Rx FIFO flushing. 1: set this bit to flush the Rx FIFO. This bit does not clear itself and must be toggled if a single flush is required. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0, a read of the Rx FIFO initiates a transfer. Continuous transfer enable. 0: DIS. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPI0TX register, a new transfer is initiated after a stall period of 1 serial clock cycle. 1: EN. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. Loopback enable. 0: cleared by user to be in normal mode. 1: set by user to connect MISO to MOSI and test software. Slave MISO output enable. 0: clear this bit to disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. 1: set this bit for MISO to operate as normal. SPIRX overflow overwrite enable. 0: cleared by user, the new serial byte received is discarded. 1: set by user, the valid data in the Rx register is overwritten by the new serial byte received. Transmit zeros enable. 0: clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO. 1: set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. SPI transfer and interrupt mode. 0: cleared by user to initiate transfer with a read of the SPI0RX register. Interrupt only occurs when Rx is full. 1: set by user to initiate transfer with a write to the SPI0TX register. Interrupt only occurs when Tx is empty. LSB first transfer enable. 0: MSB transmitted first. 1: LSB transmitted first. SPI wired OR mode. 1: enables open circuit data output enable. External pull-ups required on data out pins. 0: normal output levels. Rev. A | Page 126 of 190 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 3 Bit Name CPOL 2 CPHA 1 MASEN 0 ENABLE Description Serial clock polarity. 0: serial clock idles low. 1: serial clock idles high. Serial clock phase mode. 1: serial clock pulses at the beginning of each serial bit transfer. 0: serial clock pulses at the end of each serial bit transfer. Master mode enable. 0: enable slave mode. 1: enable master mode. SPI enable. 0: disable the SPI. 1: enable the SPI. UG-868 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access R RW SPI DMA Enable Register Address: 0x4002C014, Reset: 0x0000, Name: SPI0DMA Table 185. Bit Descriptions for SPI0DMA Bit(s) [15:3] 2 Bit Name RESERVED IENRXDMA 1 IENTXDMA 0 ENABLE Description Reserved. Enable receive DMA request. 0: disable Rx DMA interrupt. 1: enable Rx DMA interrupt. Enable transmit DMA request. 0: disable Tx DMA interrupt. 1: enable Tx DMA interrupt. Enable DMA for data transfer. Set by user code to start a DMA transfer. Cleared by user code at the end of DMA transfer. This bit must be cleared to prevent extra DMA request to the µDMA controller. Transfer Byte Count Register Address: 0x4002C018, Reset: 0x0000, Name: SPI0CNT Table 186. Bit Descriptions for SPI0CNT Bit(s) [15:8] [7:0] Bit Name RESERVED COUNT Description Reserved. Transfer byte count. COUNT indicates the number of bytes to be transferred. Count is used in both receive and transmit transfer types. The COUNT value ensures that a master mode transfer terminates at the proper time and that 16-bit DMA transfers are byte padded or discarded as required to match odd transfer counts. Reset by clearing SPI0CON[0] or if SPI0CNT is updated. Rev. A | Page 127 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: SPI1 Table 187. SPI1 Register Summary Address 0x40030000 0x40030004 0x40030008 0x4003000C 0x40030010 0x40030014 0x40030018 Name SPI1STA SPI1RX SPI1TX SPI1DIV SPI1CON SPI1DMA SPI1CNT Description Status register Receive register Transmit register Baud rate selection register SPI configuration register SPI DMA enable register Transfer byte count register Reset 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 RW R R W RW RW RW RW REGISTER DETAILS: SPI1 Status Register Address: 0x40030000, Reset: 0x0000, Name: SPI1STA Table 188. Bit Descriptions for SPI1STA Bit(s) 15 14 Bit Name RESERVED CSRSG 13 CSFLG 12 CSERR 11 RXS [10:8] RXFSTA 7 RXOF 6 RX 5 TX Description Reserved. Detected a rising edge on CS in CONT mode. This bit causes an interrupt, which can be used to identify the end of an SPI data frame. 0: cleared to 0 when the status register is read. 1: set to 1 when there was a rising edge in CS line, when the device was in master mode, continuous transfer, high frequency mode, and CSIRQ_EN was asserted. Detected a falling edge on CS in CONT mode. This bit causes an interrupt, which can be used to identify the start of an SPI data frame. 0: cleared to 0 when the status register is read. 1: set to 1 when there was a falling edge in CS line, when the device was in master mode, continuous transfer, high frequency mode, and CSIRQ_EN was asserted. Detected a CS error condition. 0: cleared to 0 when the status register is read. 1: set to 1 when the CS line was deasserted abruptly, even before the full byte of data was transmitted completely. This bit causes an interrupt. SPI Rx FIFO excess bytes present. 0: cleared to 0 when the number of bytes in the FIFO is equal or less than the number in SPI1CON[15:14]. 1: set to 1 when there are more bytes in the Rx FIFO than indicated in the MOD bits in SPI1CON. SPI Rx FIFO status. 000: Rx FIFO empty. 001: 1 valid byte in FIFO. 010: 2 valid bytes in the FIFO. 011: 3 valid bytes in the FIFO. 100: 4 valid bytes in the FIFO. SPI Rx FIFO overflow. 0: cleared to 0 when the SPI1STA register is read. 1: set to 1 when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set in SPI1CON. SPI Rx IRQ. Not available in DMA mode. Set when a receive interrupt occurs. 0: cleared to 0 when the SPI1STA register is read. 1: set to 1 when TIM in SPI1CON is cleared and the required number of bytes have been received. SPI Tx IRQ. Status bit. Not available in DMA mode. 0: CLR. Cleared to 0 when the SPI1STA register is read. 1: SET. Set to 1 when a transmit interrupt occurs. This bit is set when TIM in SPI1CON is set, and the required number of bytes have been transmitted. Rev. A | Page 128 of 190 Reset 0x0 0x0 Access R RC 0x0 RC 0x0 RC 0x0 R 0x0 R 0x0 RC 0x0 RC 0x0 RC ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 4 Bit Name TXUR [3:1] TXFSTA 0 IRQ Description SPI Tx FIFO underflow. 0: cleared to 0 when the SPI1STA register is read. 1: set to 1 when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI1CON. SPI Tx FIFO status. 000: Tx FIFO empty. 001: 1 valid byte in FIFO. 010: 2 valid bytes in FIFO. 011: 3 valid bytes in FIFO. 100: 4 valid bytes in FIFO. SPI interrupt status. 0: cleared to 0 after reading SPI1STA. 1: set to 1 when an SPI based interrupt occurs. UG-868 Reset 0x0 Access RC 0x0 R 0x0 RC Reset 0x0 Access R 0x0 R Reset 0x0 Access W 0x0 W Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW Receive Register Address: 0x40030004, Reset: 0x0000, Name: SPI1RX Table 189. Bit Descriptions for SPI1RX Bit(s) [15:8] Bit Name DMA_DATA_BYTE_2 [7:0] DATA_BYTE_1 Description 8-bit receive buffer. These 8 bits are used only in the DMA mode, where all FIFO accesses happen as half-word access. They return zeros if DMA is disabled. 8-bit receive buffer. Transmit Register Address: 0x40030008, Reset: 0x0000, Name: SPI1TX Table 190. Bit Descriptions for SPI1TX Bit(s) [15:8] Bit Name DMA_DATA_BYTE_2 [7:0] DATA_BYTE_1 Description 8-bit transmit buffer. These 8 bits are used only in the DMA mode, where all FIFO accesses happen as half-word access. They return zeros if DMA is disabled. 8-bit transmit buffer. Baud Rate Selection Register Address: 0x4003000C, Reset: 0x0000, Name: SPI1DIV Table 191. Bit Descriptions for SPI1DIV Bit(s) [15:9] 8 Bit Name RESERVED CSIRQ_EN 7 BCRST 6 HFM [5:0] DIV Description Reserved. Enable interrupt on every CS edge in CONT mode. If this bit is set and the SPI module is in continuous mode, any edge on CS generates an interrupt and the corresponding status bits (CSRSG, CSFLG) is asserted. If this bit is clear, no interrupt is generated. This bit has no effect if the SPI is not in continuous mode. Reset mode for CSERR. If this bit is set, the bit counter is reset after a CS error condition, and the Cortex is expected to clear the SPI enable bit. If this bit is clear, the bit counter continues from where it stopped. SPI can receive the remaining bits when CS is asserted and the Cortex has to ignore the CSERR interrupt. However, it is strongly recommended to set this bit for a graceful recovery after a CS error. High frequency mode. This bit is used for applications using high frequency where the pad introduces a significant delay on the SCL, which can cause a significant enough difference between the serial clock and the data being received on the Rx shift register. In this mode, the Rx shift register is clocked by SCL instead of UCLK. SPI clock divider. DIV is the factor used to divide UCLK to generate the serial clock. Rev. A | Page 129 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual SPI Configuration Register Address: 0x40030010, Reset: 0x0000, Name: SPI1CON Table 192. Bit Descriptions for SPI1CON Bit(s) [15:14] Bit Name MOD 13 TFLUSH 12 RFLUSH 11 CON 10 LOOPBACK 9 OEN 8 RXOF 7 ZEN 6 TIM 5 LSB 4 WOM Description SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. For DMA Rx transfer, these bits must be 00. 00: Tx interrupt occurs when 1 byte has been transferred. Rx interrupt occurs when 1 or more bytes have been received into the FIFO. 01: Tx interrupt occurs when 2 bytes has been transferred. Rx interrupt occurs when 2 or more bytes have been received into the FIFO. 10: Tx interrupt occurs when 3 bytes has been transferred. Rx interrupt occurs when 3 or more bytes have been received into the FIFO. 11: Tx interrupt occurs when 4 bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or 4 bytes present. SPI Tx FIFO flush enable. 0: clear this bit to disable Tx FIFO flushing. 1: set this bit to flush the Tx FIFO. This bit does not clear itself and must be toggled if a single flush is required. If this bit is left high, either the last transmitted value or 0x00 is transmitted depending on the ZEN bit. Any writes to the Tx FIFO are ignored while this bit is set. SPI Rx FIFO flush enable. 0: clear this bit to disable Rx FIFO flushing. 1: set this bit to flush the Rx FIFO. This bit does not clear itself and must be toggled if a single flush is required. If this bit is set, all incoming data is ignored, and no interrupts are generated. If set and TIM = 0, a read of the Rx FIFO initiates a transfer. Continuous transfer enable. 0: DIS. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPI1TX register, a new transfer is initiated after a stall period of 1 serial clock cycle. 1: EN. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. Loopback enable. 0: cleared by user to be in normal mode. 1: set by user to connect MISO to MOSI and test software. Slave MISO output enable. 0: clear this bit to disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. 1: set this bit for MISO to operate as normal. SPIRX overflow overwrite enable. 0: cleared by user, the new serial byte received is discarded. 1: set by user, the valid data in the Rx register is overwritten by the new serial byte received. Transmit zeros enable. 0: clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO. 1: set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. SPI transfer and interrupt mode. 0: cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full. 1: set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty. LSB first transfer enable. 0: MSB transmitted first. 1: LSB transmitted first. SPI wired OR mode. 0: normal output levels. 1: enables open circuit data output enable. External pull-ups required on data out pins. Rev. A | Page 130 of 190 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 3 Bit Name CPOL 2 CPHA 1 MASEN 0 ENABLE Description Serial clock polarity. 0: serial clock idles low. 1: serial clock idles high. Serial clock phase mode. 0: serial clock pulses at the end of each serial bit transfer. 1: serial clock pulses at the beginning of each serial bit transfer. Master mode enable. 0: enable slave mode. 1: enable master mode. SPI enable. 0: disable the SPI. 1: enable the SPI. UG-868 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access R RW SPI DMA Enable Register Address: 0x40030014, Reset: 0x0000, Name: SPI1DMA Table 193. Bit Descriptions for SPI1DMA Bit(s) [15:3] 2 Bit Name RESERVED IENRXDMA 1 IENTXDMA 0 ENABLE Description Reserved. Enable receive DMA request. 0: disable Rx DMA interrupt. 1: enable Rx DMA interrupt. Enable transmit DMA request. 0: disable Tx DMA interrupt. 1: enable Tx DMA interrupt. Enable DMA for data transfer. Set by user code to start a DMA transfer. Cleared by user code at the end of DMA transfer. This bit must be cleared to prevent extra DMA request to the µDMA controller. Transfer Byte Count Register Address: 0x40030018, Reset: 0x0000, Name: SPI1CNT Table 194. Bit Descriptions for SPI1CNT Bit(s) [15:8] [7:0] Bit Name RESERVED COUNT Description Reserved. Transfer byte count. COUNT indicates the number of bytes to be transferred. Count is used in both receive and transmit transfer types. The COUNT value ensures that a master mode transfer terminates at the proper time and that 16-bit DMA transfers are byte padded or discarded as required to match odd transfer counts. Reset by clearing SPI1CON[0] or if SPI1CNT is updated. Rev. A | Page 131 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UART SERIAL INTERFACE UART FEATURES The ADuCM320i/ADuCM322/ADuCM322i feature an industry-standard 16,450 universal asynchronous receiver/transmitter (UART) peripheral with support for DMA. UART OVERVIEW The UART peripheral is a full duplex UART, compatible with the industry-standard 16,450. The UART is responsible for converting data between serial and parallel formats. The serial communication follows an asynchronous protocol, supporting various word lengths, stop bits, and parity generation options. This UART also contains interrupt handling hardware. The UART features a fractional divider that facilitates high accuracy baud rate generation. Interrupts can be generated from several unique events, such as full/empty data buffer, transfer error detection, and break detection. UART OPERATION Serial Communications An asynchronous serial communication protocol is followed with these options: • • • • 5 data bits to 8 data bits 1, 2, or 1½ stop bits None, even, or odd parity The baud rate is as follows: Baud Rate = UCLK/CDPCLK ÷ (2 × 16 × COMDIV) ÷ (M + N ÷ 2048) where: UCLK/CDPCLK is the divided 80 MHz clock as configured via CLKCON1[10:8]. COMDIV = 1 to 65,536. M = 1 to 3. N = 0 to 2047. All data-words require a start bit and at least one stop bit, which creates a range from 7 bits to 12 bits for each word. Transmit operation is initiated by writing to the transmit holding register (COMTX). After a synchronization delay, the data is moved to the internal transmit shift register (TSR), where it is shifted out at a baud (bit) rate equal to the following with start, stop, and parity bits appended as required: UCLK/CDPCLK ÷ (2 × 16 × COMDIV) ÷ (M + N ÷ 2048) All data-words begin with a low going start bit. The transfer of COMTX to the TSR causes the transmit register empty status flag to be set. The receive operation uses the same data format as the transmit configuration except for the number of stop bits, which is always one. After detection of the start bit, the received word is shifted into the internal receive shift register (RSR). After the appropriate number of bits (including stop bits) are received, the data and any status are updated, and the RSR is transferred to the receive buffer register (COMRX). The receive buffer register full status flag is updated upon the transfer of the received word to this buffer and the appropriate synchronization delay. A sampling clock equal to 16 times the baud rate is used to sample the data as close to the midpoint of the bit as possible. A receive filter is also present that removes spurious pulses of less than two times the sampling clock period. Note that data is transmitted and received least significant bit first, which is often not the assumed case by the user. However, it is standard for the protocol. For power saving purposes, it is possible to disable the system clock to the UART via the CLKCON5[5] register. By default, the clock to the UART is disabled (CLKCON5[5] = 1). Rev. A | Page 132 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Programmed Input/Output Mode In programmed input/output mode, the software is responsible for moving data to and from the UART. This movement is typically accomplished by interrupt service routines that respond to the transmit and receive interrupts by either reading or writing data as appropriate. This mode puts certain constraints on the software itself in that the software must respond within a certain time to prevent overflow errors from occurring in the receive channel. Polling the status flag is processor intensive and not typically used unless the system can tolerate the overhead. Interrupts can be disabled using the COMIEN register. Writing COMTX when it is not empty or reading COMRX when it is not full produces incorrect results and should not be done. In the former case, COMTX is overwritten by the new word, and the previous word is never transmitted. In the latter case, the previously received word is read again. Both of these errors must be avoided in the software by correctly using either interrupts or status register polling. These errors are not detected in hardware. Enable/Disable Bit Before the ADuCM320i/ADuCM322/ADuCM322i enter power-down mode, it is recommended to disable the serial interfaces. A bit is provided in the UART control register to disable the UART serial peripheral. This bit disables the clock to the peripheral. When setting this bit, care must be taken in the software that no data is being transmitted or received. If this bit is set during communication, the data transfer does not complete; the receive or transmit register will contain only part of the data. Interrupts The UART peripheral has one interrupt output to the interrupt controller for both Rx and Tx interrupts. The COMIIR register must be read by the software to determine the cause of the interrupt. Note that in DMA mode, the break interrupt is not available. When receiving in input/output mode, the interrupt is generated for the following cases: • • • • • • COMRX full Receive overflow error Receive parity error Receive framing error Break interrupt (UART RxD held low) COMTX empty Buffer Requirements This UART is double buffered (holding register and shift register). DMA Mode In DMA mode, user code does not move data to and from the UART. DMA request signals going to the external DMA block indicate that the UART is ready to transmit or receive data. These DMA request signals can be disabled in the COMIEN register. Rev. A | Page 133 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Example Code to Set Up UART Receive DMA Channel void UARTRXDMAINIT(void) { NVIC_EnableIRQ(DMA_UART_RX_IRQn); // UArt Tx DMA interrupt enable pADI_UART->COMLCR = COMLCR_WLS_EIGHTBITS | COMLCR_STOP; // 8 data bits + 1 stop bit pADI_UART->COMDIV = 0x41; // Set UART baud rate pADI_UART->COMFBR = COMFBR_FBEN_EN | 0x803; // DIVM = 1, DIVN = 3 pADI_GP1->GPCON = 0x5; // Configure P1.0/P1.1 for UART Dma_Init(); pADI_DMA->DMACFG = 0x1; UARTDMAREAD(uxUARTRXData, 4); // Enable DMA mode in DMA controller pADI_DMA->DMAENSET = 0x20; // Enable UART_RX_DMA Channel pADI_UART->COMIEN = 0x20; // Enable DMA Rx transfers } void UARTDMAREAD(unsigned char *pucRX_DMA, unsigned int iNumVals) { DmaDesc Desc; // Common configuration of all the descriptors used here Desc.ctrlCfg.bits.cycle_ctrl = DMA_BASIC; desc.ctrlcfg.bits.next_useburst = 0x0; desc.ctrlcfg.bits.r_power = 0; Desc.ctrlCfg.Bits.src_prot_ctrl = 0x0; Desc.ctrlCfg.Bits.dst_prot_ctrl = 0x0; Desc.ctrlCfg.Bits.src_size = DMA_SIZE_BYTE; Desc.ctrlCfg.Bits.dst_size = DMA_SIZE_BYTE; // Rx primary descriptor Desc.srcEndPtr = (unsigned int)(&pADI_UART->COMRX); Desc.destEndPtr = (unsigned int)(pucTX_DMA + (iNumVals - 0x1) ); Desc.ctrlCfg.Bits.n_minus_1 = iNumRX - 0x1; Desc.ctrlCfg.Bits.src_inc = DMA_SRCINC_NO; Desc.ctrlCfg.Bits.dst_inc = DMA_DSTINC_BYTE; *Dma_GetDescriptor(UARTRX_C) = Desc; } // UART DMA Rx IRQ handler void DMA_UART_RX_Int_Handler() { NVIC_DisableIRQ(DMA_UART_RX_IRQn); // Clear interrupt source } Rev. A | Page 134 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Example Code to Set Up UART Transmit DMA Channel void UARTTXDMAINIT(void) { NVIC_EnableIRQ(DMA_UART_TX_IRQn); // UART Tx DMA interrupt sources pADI_UART->COMLCR = COMLCR_WLS_8BITS + COMLCR_STOP; // 8 data bits + 1 stop bit pADI_UART->COMDIV = 0x41; // Set UART baud rate pADI_UART->COMFBR = COMFBR_FBEN_EN | 0x803; // DIVM = 1, DIVN = 3 pADI_GP1->GPCON = 0x5; // Configure P1.0/P1.1 for UART Dma_Init(); pADI_DMA->DMACFG = 0x1; // Enable DMA mode in DMA controller UARTDMAWRITE(uxUARTTXData, 16); pADI_DMA->DMAENSET = 0x10; // Enable UART_TX_DMA channel pADI_UART->COMIEN = 0x10; // Enable DMA Tx transfers } void UARTDMAWRITE(unsigned char *pucTX_DMA, unsigned int iNumVals) { DmaDesc Desc; // Common configuration of all the descriptors used here Desc.ctrlCfg.Bits.cycle_ctrl = DMA_BASIC; Desc.ctrlCfg.Bits.next_useburst = 0x0; Desc.ctrlCfg.Bits.r_power = 0; Desc.ctrlCfg.Bits.src_prot_ctrl = 0x0; Desc.ctrlCfg.Bits.dst_prot_ctrl = 0x0; Desc.ctrlCfg.Bits.src_size = DMA_SIZE_BYTE; Desc.ctrlCfg.Bits.dst_size = DMA_SIZE_BYTE; // Tx primary descriptor Desc.srcEndPtr = (unsigned int)(pucTX_DMA + (iNumVals - 0x1) ); Desc.destEndPtr = (unsigned int)(&pADI_UART->COMTX); Desc.ctrlCfg.Bits.n_minus_1 = iNumRX - 0x1; Desc.ctrlCfg.Bits.src_inc = DMA_SRCINC_BYTE; Desc.ctrlCfg.Bits.dst_inc = DMA_DSTINC_NO; *Dma_GetDescriptor(UARTTX_C) = Desc; } // UART DMA Tx IRQ handler void DMA_UART_TX_Int_Handler() { NVIC_DisableIRQ(DMA_UART_TX_IRQn); // Clear interrupt source } Rev. A | Page 135 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: UART Table 195. UART Register Summary Address 0x40005000 0x40005000 0x40005004 0x40005008 0x4000500C 0x40005010 0x40005014 0x40005018 0x4000501C 0x40005024 0x40005028 Name COMTX COMRX COMIEN COMIIR COMLCR COMMCR COMLSR COMMSR COMSCR COMFBR COMDIV Description Transmit holding register Receive buffer register Interrupt enable register Interrupt identification register Line control register Modem control register Line status register Modem status register Scratch buffer register Fractional baud rate register Baud rate divider register Reset 0x0000 0x0000 0x0000 0x0001 0x0000 0x0000 0x0060 0x0000 0x0000 0x0000 0x0001 RW W R RW RC RW RW RC RC RW RW RW REGISTER DETAILS: UART Transmit Holding Register Address: 0x40005000, Reset: 0x0000, Name: COMTX COMRX and COMTX share the same address while they are implemented as different registers. If these registers are written to, the user accesses the transmit holding register (COMTX). If these registers are read from, the user accesses the receive buffer register (COMRX). Table 196. Bit Descriptions for COMTX Bit(s) [15:8] [7:0] Bit Name RESERVED THR Description Reserved. Transmit holding register. This is an 8-bit register to which the user can write the data to be sent. If the ETBEI bit is set in the COMIEN register, an interrupt generates when COMTX is empty. If user code sets ETBEI while COMTX is already empty, an interrupt generates immediately. Reset 0x0 0x0 Access R W Reset 0x0 0x0 Access R R Receive Buffer Register Address: 0x40005000, Reset: 0x0000, Name: COMRX Table 197. Bit Descriptions for COMRX Bit(s) [15:8] [7:0] Bit Name RESERVED RBR Description Reserved. Receive buffer register. This is an 8-bit register from which the user can read received data. If the ERBFI bit is set in the COMIEN register, an interrupt generates when this register is fully loaded with the received data via the serial input port. If user code sets the ERBFI bit while COMRX is already full, an interrupt generates immediately. Rev. A | Page 136 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Interrupt Enable Register Address: 0x40005004, Reset: 0x0000, Name: COMIEN COMIEN is the interrupt enable register that configures which interrupt source generates the interrupt. Only the lowest four bits in this register enable interrupts. Bit 4 and Bit 5 enable UART DMA signals. The UART DMA channel and interrupt must be configured in the DMA block. Table 198. Bit Descriptions for COMIEN Bit(s) [15:6] 5 Bit Name RESERVED EDMAR 4 EDMAT 3 EDSSI 2 ELSI 1 ETBEI 0 ERBFI Description Reserved. DMA requests in receive mode. 0: DMA requests disabled. 1: DMA requests enabled. DMA requests in transmit mode. 0: DMA requests are disabled. 1: DMA requests are enabled. Modem status interrupt. Interrupt is generated when any of COMMSR[3:0] are set. 0: interrupt disabled. 1: interrupt enabled. Rx status interrupt. 0: interrupt disabled. 1: interrupt enabled. Transmit buffer empty interrupt. 0: interrupt disabled. 1: interrupt enabled. Receive buffer full interrupt. 0: interrupt disabled. 1: interrupt enabled. Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access R RC 0x1 RC Interrupt Identification Register Address: 0x40005008, Reset: 0x0001, Name: COMIIR Table 199. Bit Descriptions for COMIIR Bit(s) [15:3] [2:1] Bit Name RESERVED STA 0 NIRQ Description Reserved. Interrupt status. When NIRQ is low (active low), this indicates an interrupt, and the STA bit decoding is as follows. 00: modem status interrupt (read COMMSR to clear). 01: transmit buffer empty interrupt (write to COMTX or read COMIIR to clear). 10: receive buffer full interrupt (read COMRX to clear). 11: receive line status interrupt (read COMLSR to clear). Interrupt flag. 0: interrupt occurred. Source of interrupt indicated in the STA bits. 1: no interrupt occurred. Rev. A | Page 137 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Line Control Register Address: 0x4000500C, Reset: 0x0000, Name: COMLCR Table 200. Bit Descriptions for COMLCR Bit(s) [15:7] 6 Bit Name RESERVED BRK 5 SP 4 EPS 3 PEN 2 STOP [1:0] WLS Description Reserved. Set break. 0: force TxD to 0. 1: normal TxD operation. Stick parity. Used to force parity to defined values. When set, the parity is based on the following bit settings: When EPS = 1 and PEN = 1, the parity is forced to 0. When EPS = 0 and PEN = 1, the parity is forced to 1. When EPS = X and PEN = 0, no parity is transmitted. 0: parity is not forced based on EPS and PEN. 1: parity forced based on EPS and PEN. Parity select. This bit only has meaning if parity is enabled (PEN set). 0: odd parity is transmitted and checked. 1: even parity is transmitted and checked. Parity enable. Used to control of the parity bit transmitted and checked. The value transmitted and the value checked are based on the settings of EPS and SP. 0: parity is not transmitted or checked. 1: parity is transmitted and checked. Stop bit. Used to control the number of stop bits transmitted. In all cases, only the first stop bit is evaluated on data received. 0: send 1 stop bit regardless of the word length (WLS). 1: send a number of stop bits based on the word length. Transmit 1.5 stop bits if the word length is 5 bits (WLS = 00), or 2 stop bits if the word length is 6 (WLS = 01), 7 (WLS = 10), or 8 bits (WLS = 11). Word length select. Selects the number of bits per transmission. 00: 5 bits. 01: 6 bits. 10: 7 bits. 11: 8 bits. Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Modem Control Register Address: 0x40005010, Reset: 0x0000, Name: COMMCR Table 201. Bit Descriptions for COMMCR Bit(s) [15:5] 4 Bit Name RESERVED LOOPBACK 3 OUT2 2 OUT1 1 RTS 0 DTR Description Reserved. Loop back mode. In loop back mode, the SOUT is forced high. The modem signals are also directly connected to the status inputs (RTS to CTS, DTR to DSR, OUT1 to RI, and OUT2 to DCD). 0: normal operation, loop back disabled. 1: loop back enabled. Output 2. 0: force OUT2 to a Logic 1. 1: force OUT2 to a Logic 0. Output 1. 0: force OUT1 to a Logic 1. 1: force OUT1 to a Logic 0. Request to send. 0: force RTS to a Logic 1. 1: force RTS to a Logic 0. Data terminal ready. 0: force DTR to a Logic 1. 1: force DTR to a Logic 0. Rev. A | Page 138 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Line Status Register Address: 0x40005014, Reset: 0x0060, Name: COMLSR Table 202. Bit Descriptions for COMLSR Bit(s) [15:7] 6 Bit Name RESERVED TEMT 5 THRE 4 BI 3 FE 2 PE 1 OE 0 DR Description Reserved. COMTX and shift register empty status. 0: COMTX has been written to and contains data to be transmitted. Take care not to overwrite its value. 1: COMTX and the transmit shift register are empty and it is safe to write new data to COMTX. Data has been transmitted. COMTX empty. THRE is cleared when COMRX is read. 0: COMTX has been written to and contains data to be transmitted. Take care not to overwrite its value. 1: COMTX is empty and it is safe to write new data to COMTX. The previous data may not have been transmitted yet and can still be present in the shift register. Break indicator. If set, this bit self clears after COMLSR is read. 0: SIN was not detected to be longer than the maximum word length. 1: SIN was held low for more than the maximum word length. Framing error. If set, this bit self clears after COMLSR is read. 0: no invalid stop bit was detected. 1: an invalid stop bit was detected on a received word. Parity error. If set, this bit self clears after COMLSR is read. 0: no parity error was detected. 1: a parity error occurred on a received word. Overrun error. If set, this bit self clears after COMLSR is read. 0: receive data has not been overwritten. 1: receive data was overwritten by new data before COMRX was read. Data ready. This bit is cleared only by reading COMRX. If set, this bit does not self clear. 0: COMRX does not contain new receive data. 1: COMRX contains receive data that should be read. Reset 0x0 0x1 Access R R 0x1 R 0x0 RC 0x0 RC 0x0 RC 0x0 RC 0x0 RC Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R Modem Status Register Address: 0x40005018, Reset: 0x0000, Name: COMMSR Table 203. Bit Descriptions for COMMSR Bit(s) [15:8] 7 Bit Name RESERVED DCD 6 RI 5 DSR 4 CTS 3 DDCD Description Reserved. Data carrier detect. This bit reflects the direct status complement of the DCD pin. 0: DCD is currently logic high. 1: DCD is currently logic low. Ring indicator. This bit reflects the direct status complement of the DCD pin. 0: RI is currently logic high. 1: RI is currently logic low. Data set ready. This bit reflects the direct status complement of the DCD pin. 0: DSR is currently logic high. 1: DSR is currently logic low. Clear to send. This bit reflects the direct status complement of the DCD pin. 0: CTS is currently logic high. 1: CTS is currently logic low. Delta DCD. If set, this bit self clears after COMMSR is read. 0: DCD has not changed state since COMMSR was last read. 1: DCD changed state since COMMSR last read. Rev. A | Page 139 of 190 UG-868 Bit(s) 2 Bit Name TERI 1 DDSR 0 DCTS ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description Trailing edge RI. If set, this bit self clears after COMMSR is read. 0: RI has not changed from 0 to 1 since COMMSR last read. 1: RI changed from 0 to 1 since COMMSR last read. Delta DSR. If set, this bit self clears after COMMSR is read. 0: DSR has not changed state since COMMSR was last read. 1: DSR changed state since COMMSR last read. Delta CTS. If set, this bit self clears after COMMSR is read. 0: CTS has not changed state since COMMSR was last read. 1: CTS changed state since COMMSR last read. Reset 0x0 Access R 0x0 R 0x0 R Reset 0x0 0x0 Access R RW Reset 0x0 Access RW 0x0 0x0 0x0 R RW RW Scratch Buffer Register Address: 0x4000501C, Reset: 0x0000, Name: COMSCR Table 204. Bit Descriptions for COMSCR Bit(s) [15:8] [7:0] Bit Name RESERVED SCR Description Reserved. Scratch. The scratch register is an 8-bit register used to store intermediate results. The value contained in the scratch register does not affect UART functionality or performance. Only 8 bits of this register are implemented. Bit 15 to Bit 8 are read only and always return 0x00 when read. Writable with any value from 0 to 255. A read returns the last value written. Fractional Baud Rate Register Address: 0x40005024, Reset: 0x0000, Name: COMFBR Table 205. Bit Descriptions for COMFBR Bit(s) 15 Bit Name FBEN [14:13] [12:11] [10:0] RESERVED DIVM DIVN Description Fractional baud rate generator enable. The generating of fractional baud rate can be described by the following formula, and the final baud rate of UART operation is calculated as Baud rate = ((UCLK)/(2 × (M + N/2048)) 16 × COMDIV) Reserved. Fractional baud rate M divide bits, 1 to 3. This bit must not be 0. Fractional baud rate N divide bits, 0 to 2047. Baud Rate Divider Register Address: 0x40005028, Reset: 0x0001, Name: COMDIV Table 206. Bit Descriptions for COMDIV Bit(s) [15:0] Bit Name DIV Description Baud rate divider. The COMDIV register should not be 0, which is not specified. The range of allowed DIV values is from 1 to 65,535. Rev. A | Page 140 of 190 Reset 0x1 Access RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 PROGRAMMABLE LOGIC ARRAY (PLA) PLA FEATURES The ADuCM320i/ADuCM322/ADuCM322i integrate a fully PLA that consists of four independent but interconnected PLA blocks. Each block consists of eight PLA elements: Block x Element 0 to Block x Element 7, where x is the block number. Each ADuCM320i/ADuCM322/ADuCM322i has four blocks, resulting in a total of 32 PLA elements: Element 0 to Element 31. PLA OVERVIEW Each PLA element contains a two-input lookup table that can be configured to generate any logic output function based on two inputs and a flip-flop. PLA_CLK 2 BLOCK X ELEMENT BLOCK X ELEMENT BLOCK X ELEMENT BLOCK X ELEMENT PLA_DIN0[n] 1 0 2 4 6 2 0 A PLA_ELEMn[10:9] PLA_ELEMn[6] B BLOCK X ELEMENT BLOCK X ELEMENT BLOCK X ELEMENT BLOCK X ELEMENT 1 3 5 7 LOOKUP TABLE 4 OUTPUT ELEMENT n 1 3 PLA_ELEMn[4:1] PLA_ELEMn[0] GPIO INPUT PLA_ELEMn[5] WHERE: BLOCK X IS BLOCK 0 OR BLOCK 1. PLA_ELEMn IS THE MMR CONTROLING ELEMENT n, n = 0 TO 15. NC = NO CONNECTION. 1THE FIRST SELECTION OF MUX0 IS THE FEEDBACK FROM BLOCK X ELEMENT 0, WHERE X IS THE NUMBER OF THE CURRENT BLOCK. IF THE FIRST ELEMENT IN THE BLOCK IS BEING CONFIGURED, THEN THE FEEDBACK COMES FROM ANOTHER BLOCK. SEE THE INTERBLOCK CONNECTION DIAGRAM FOR MORE DETAILS. 2BLOCK 0 AND BLOCK 1 ARE SET IN THE CORRESPONDING BIT IN THE PLA_DIN0 MMR. 13437-124 PLA_ELEMn[8:7] Figure 27. PLA Element: Block 0 and Block 1 BLOCK X ELEMENT BLOCK X ELEMENT BLOCK X ELEMENT BLOCK X ELEMENT 0 2 4 6 1 PLA_CLK 2 OUTPUT ELEMENT (n – 16) 2 0 A PLA_ELEMn[10:9] PLA_ELEMn[6] B BLOCK X ELEMENT BLOCK X ELEMENT BLOCK X ELEMENT BLOCK X ELEMENT 1 3 5 7 LOOKUP TABLE 4 OUTPUT ELEMENT n 1 3 PLA_ELEMn[4:1] PLA_ELEMn[0] NC PLA_ELEMn[5] WHERE: BLOCK X IS BLOCK 2 OR BLOCK 3. PLA_ELEMn IS THE MMR CONTROLING ELEMENT n, n = 16 TO 31. NC = NO CONNECTION. 1THE FIRST SELECTION OF MUX0 IS THE FEEDBACK FROM BLOCK X ELEMENT 0, WHERE X IS THE NUMBER OF THE CURRENT BLOCK. IF THE FIRST ELEMENT IN THE BLOCK IS BEING CONFIGURED, THEN THE FEEDBACK COMES FROM ANOTHER BLOCK. SEE THE INTERBLOCK CONNECTION DIAGRAM. 2FOR BLOCK 2 AND BLOCK 3 THE INPUT COMES FROM THE OUTPUT OF ELEMENT(n – 16), WHERE n IS THE NUMBER OF THE ELEMENT BEING CONFIGURED. FOR EXAMPLE, FOR ELEMENT 25 THE INPUT TO MUX 2 COMES FROM ELEMENT 9. THIS ALLOWS GPIO INPUTS TO BE INDIRECTLY CONNECTED TO ELEMENTS IN BLOCK 2 AND BLOCK 3. 13437-125 PLA_ELEMn[8:7] Figure 28. PLA Element: Block 2 and Block 3 In total, 28 GPIO pins are available on each ADuCM320i/ADuCM322/ADuCM322i for the PLA. These include 14 input pins and 14 output pin that must be configured in the GPxCON register as PLA pins before using the PLA. Rev. A | Page 141 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual PLA OPERATION The PLA is configured via a set of user MMRs. The output(s) of the PLA can be routed to the internal interrupt system, to the PLA_DOUTx MMRs, or to any of the 14 PLA output pins. The GPIO inputs to the PLA are always connected to their corresponding elements, regardless of the setting in the GPxCON register, which means that a pin can be used as both an output and an input to the PLA at the same time. A PLA block can have several clock sources for its output flip-flops, or the flip-flops can be individually bypassed. All output flip-flops in the same block that are not bypassed share the same clock source. The configuration of the clock sources can be found in the PLA clock select register (PLA_CLK). Each PLA element in a block can be connected to other elements in the same block by configuring the output of Mux 0 and Mux 1. The configuration of these two multiplexer can be found in the PLA_ELEMn configuration register. A complete list of the possible connections is given in Table 208 and Table 209. The four blocks can be interconnected as follows: • • • • Output of Element 7 (Block 0 Element 7) can be fed back to the Input 0 of Mux 0 of Element 8 (Block 1 Element 0). Output of Element 15 (Block 1 Element 7) can be fed back to Input 0 of Mux 0 of Element 16 (Block 2 Element 0). Output of Element 23 (Block 2 Element 7) can be fed back to the Input 0 of Mux 0 of Element 24 (Block 3 Element 0). Output of Element 31 (Block 3 Element 7) can be fed back to Input 0 of Mux 0 of Element 0 (Block 0 Element 0). See Figure 29 for more information. There are four interrupts available for the PLA. These inputs can be configured to trigger the output of any element using the PLA_IRQ0 and PLA_IRQ1 registers. The interrupts are active high; therefore, the interrupts continue to be triggered until the output of the element goes low or until the IRQ is disabled. If an active low interrupt is required, an extra element must be configured as an inverter and then the interrupt must be configured to monitor the output of this new element. If an edge triggered interrupt is required, two extra elements must be used and configured as an edge detector ((A) AND A). Rev. A | Page 142 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 BLOCK 2 BLOCK 0 OUTPUT ELEMENT (n – 16) 0 BLOCK 2 ELEMENT 0 (ELEMENT 16) 0 BLOCK 0 ELEMENT 0 (ELEMENT 0) 4 BLOCK 0 ELEMENT 7 (ELEMENT 7) 4 2 OUTPUT 2 BLOCK 2 ELEMENT 7 4 (ELEMENT 23) OUTPUT BLOCK 3 BLOCK 1 0 BLOCK 3 ELEMENT 0 (ELEMENT 24) BLOCK 1 ELEMENT 0 (ELEMENT 8) 4 BLOCK 1 ELEMENT 7 (ELEMENT 15) 4 2 2 OUTPUT BLOCK 3 ELEMENT 7 (ELEMENT 31) Figure 29. PLA Interblock Connections Rev. A | Page 143 of 190 4 OUTPUT 13437-126 0 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Table 207. Element GPIO Input/Output Element 0 1 2 3 4 5 6 7 PLA Block 0 Input P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 Output P0.4 P0.5 P0.6 P0.7 Element 8 9 10 11 12 13 14 15 PLA Block 1 Input Output P2.0 P2.2 P3.0 P3.1 P3.2 P3.3 P1.4 P1.5 P1.6 P1.7 PLA Block 2 Element Output 16 17 18 P2.4 19 20 P2.6 21 P2.7 22 23 PLA Block 3 Element Output 24 25 26 P3.4 27 P3.5 28 29 P3.7 30 31 Table 208. Mux 0 Feedback Configuration PLA_ ELEMn[10:9] 00 01 10 11 PLA_ELEM0 Element 31 Element 2 Element 4 Element 6 PLA_ELEM1 to PLA_ELEM7 Element 0 Element 2 Element 4 Element 6 PLA_ELEM8 Element 7 Element 10 Element 12 Element 14 PLA_ELEM9 to PLA_ELEM15 Element 8 Element 10 Element 12 Element 14 PLA_ELEM16 Element 15 Element 18 Element 20 Element 22 PLA_ELEM17 to PLA_ELEM23 Element 16 Element 18 Element 20 Element 22 PLA_ELEM16 Element 17 Element 19 Element 21 Element 23 PLA_ELEM17 to PLA_ELEM23 Element 17 Element 19 Element 21 Element 23 PLA_ELEM24 Element 23 Element 26 Element 28 Element 30 PLA_ELEM25 to PLA_ELEM31 Element 24 Element 26 Element 28 Element 30 PLA_ELEM24 Element 25 Element 27 Element 29 Element 31 PLA_ELEM25 to PLA_ELEM31 Element 25 Element 27 Element 29 Element 31 Table 209. Mux 1 Feedback Configuration PLA_ ELEMn[8:7] 00 01 10 11 PLA_ELEM0 Element 1 Element 3 Element 5 Element 7 PLA_ELEM1 to PLA_ELEM7 Element 1 Element 3 Element 5 Element 7 PLA_ELEM8 Element 9 Element 11 Element 13 Element 15 PLA_ELEM9 to PLA_ELEM15 Element 9 Element 11 Element 13 Element 15 Table 210. Lookup Table Configuration PLA_ELEMn[4:1] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Function 0 A NOR B A AND B A A AND B B A XOR B A NAND B A AND B A EXNOR B B A OR B A A OR B A OR B 1 Rev. A | Page 144 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER SUMMARY: PLA Table 211. PLA Register Summary Address 0x40005800 to 0x4000587C 0x40005880 0x40005884 0x40005888 0x4000588C 0x40005890 0x40005898 0x4000589C 0x400058A0 Name PLA_ELEMn Description ELEMx configuration register Reset 0x0000 RW RW PLA_CLK PLA_IRQ0 PLA_IRQ1 PLA_ADC PLA_DIN0 PLA_DOUT0 PLA_DOUT1 PLA_LCK PLA clock select Interrupt register for Block 0 and Block 1 Interrupt register for Block 2 and Block 3 ADC configuration register Data input for Block 0 and Block 1 Data output for Block 0 and Block 1 Data output for Block 2 and Block 3 Write lock register, can only be set once every reset 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 RW RW RW RW RW R R RW1S Reset 0x00 0x0 Access Reserved RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW REGISTER DETAILS: PLA ELEMx Configuration Register Address: 0x40005800 to 0x4000587C (Increments of 0x4), Reset: 0x0000, Name: PLA_ELEMn Table 212. Bit Descriptions for PLA_ELEMn Bit(s) [15:11] [10:9] Bit Name RESERVED MUX0 [8:7] MUX1 6 MUX2 5 MUX3 [4:1] TBL Description Not used. Even element feedback selection (in respective block). 00: feedback from Element 0 (all except Element 0)/input from other block (Element 0 only). 01: feedback from Element 2. 10: feedback from Element 4. 11: feedback from Element 6. Odd element feedback selection (in respective block). 00: feedback from Element 1. 01: feedback from Element 3. 10: feedback from Element 5. 11: feedback from Element 7. Select between corresponding bit from PLA_DINx register or even feedback mux. 0: PLA_DINx input. 1: even feedback mux. Select between GPIO Bus input and odd feedback input (for Element 16 to Element 31, odd feedback is always selected). 0: odd feedback mux. 1: GPIO input. Bit 4, Bit 3, Bit 2, and Bit 1 configures output for {mux2_out, mux3_out} = 11, 10, 01, 00, respectively. 0000: 0. 0001: NOR. 0010: B and not A. 0011: NOT A. 0100: A and not B. 0101: Not B. 0110: EXOR. 0111: NAND. 1000: AND. 1001: EXNOR. 1010: B. 1011: B or not A. 1100: A. 1101: A or not B. 1110: OR. 1111: 1. Rev. A | Page 145 of 190 UG-868 Bit(s) 0 Bit Name MUX4 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description Select or bypass flip-flop output. 0: FF output. 1: bypass output. Reset 0x0 Access RW Reset 0x0 0x0 Access Reserved RW 0x0 0x0 Reserved RW 0x0 0x0 Reserved RW 0x0 0x0 Reserved RW PLA Clock Select Register Address: 0x40005880, Reset: 0x0000, Name: PLA_CLK Table 213. Bit Descriptions for PLA_CLK Bit(s) 15 [14:12] Bit Name RESERVED BLOCK3 11 [10:8] RESERVED BLOCK2 7 [6:4] RESERVED BLOCK1 3 [2:0] RESERVED BLOCK0 Description Not used. Clock select for Block 3. 000: GPIO clock on P0.3. 001: GPIO clock on P1.1. 010: GPIO clock on P2.0. 011: HCLK. 100: MOSC (16 MHz). 101: Timer 0. 110: Timer 2. 111: KOSC (32 kHz). Not used. Clock select for Block 2. 000: GPIO clock on P0.3. 001: GPIO clock on P1.1. 010: GPIO clock on P2.0. 011: HCLK. 100: MOSC (16 MHz). 101: Timer 0. 110: Timer 2. 111: KOSC (32 kHz). Not used. Clock select for Block 1. 000: GPIO clock on P0.3. 001: GPIO clock on P1.1. 010: GPIO clock on P2.0. 011: HCLK. 100: MOSC (16 MHz). 101: Timer 0. 110: Timer 2. 111: KOSC (32 kHz). Not used. Clock select for Block 0. 000: GPIO clock on P0.3. 001: GPIO clock on P1.1. 010: GPIO clock on P2.0. 011: HCLK. 100: MOSC (16 MHz). 101: Timer 0. 110: Timer 2. 111: KOSC (32 kHz). Rev. A | Page 146 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Interrupt Register for Block 0 and Block 1 Address: 0x40005884, Reset: 0x0000, Name: PLA_IRQ0 Table 214. Bit Descriptions for PLA_IRQ0 Bit(s) [15:13] 12 Bit Name RESERVED IRQ1_EN [11:8] IRQ1_SRC [7:5] 4 RESERVED IRQ0_EN [3:0] IRQ0_SRC Description Not used. IRQ1 enable. 0: disable IRQ1 interrupt. 1: enable IRQ1 interrupt. IRQ1 source select (Element 0 to Element 15). The 4-bit value corresponds to the element number (for example, 1011 selects Element 11). Not used. IRQ0 enable. 0: disable IRQ0 interrupt. 1: enable IRQ0 interrupt. IRQ0 source select (Element 0 to Element 15). The 4-bit value corresponds to the element number (for example, 1011 selects Element 11). Reset 0x0 0x0 Access Reserved RW 0x0 RW 0x0 0x0 Reserved RW 0x0 RW Reset 0x0 0x0 Access Reserved RW 0x0 RW 0x0 0x0 Reserved RW 0x0 RW Reset 0x000 0x0 Access Reserved RW 0x00 RW Interrupt Register for Block 2 and Block 3 Address: 0x40005888, Reset: 0x0000, Name: PLA_IRQ1 Table 215. Bit Descriptions for PLA_IRQ1 Bit(s) [15:13] 12 Bit Name RESERVED IRQ3_EN [11:8] IRQ3_SRC [7:5] 4 RESERVED IRQ2_EN [3:0] IRQ2_SRC Description Not used. IRQ3 enable. 0: disable IRQ3 interrupt. 1: enable IRQ3 interrupt. IRQ3 source select (Element 16 to Element 31). The element number corresponds to the 4-bit value + 16 (for example, 1011 selects Element 27). Not used. IRQ2 enable. 0: disable IRQ2 interrupt. 1: enable IRQ2 interrupt. IRQ2 source select (Element 16 to Element 31). The element number corresponds to the 4-bit value + 16 (for example, 1011 selects Element 27). ADC Configuration Register Address: 0x4000588C, Reset: 0x0000, Name: PLA_ADC Table 216. Bit Descriptions for PLA_ADC Bit(s) [15:6] 5 Bit Name RESERVED CONVST_EN [4:0] CONVST_SRC Description Not used. Bit to enable ADC start convert from PLA. 0: disable. 1: enable. Element for ADC start convert source. The binary value corresponds to the element number. For example, Element 23 is 10111. Rev. A | Page 147 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Data Input for Block 0 and Block 1 Register Address: 0x40005890, Reset: 0x0000, Name: PLA_DIN0 Table 217. Bit Descriptions for PLA_DIN0 Bit(s) [15:0] Bit Name DIN Description Input bit to Element 15 to Element 0 Reset 0x0 Access RW Reset 0x0 Access R Reset 0x0 Access R Data Output for Block 0 and Block 1 Register Address: 0x40005898, Reset: 0x0000, Name: PLA_DOUT0 Table 218. Bit Descriptions for PLA_DOUT0 Bit(s) [15:0] Bit Name DOUT Description Output bit from Element 15 to Element 0 Data Output for Block 2 and Block 3 Register Address: 0x4000589C, Reset: 0x0000, Name: PLA_DOUT1 Table 219. Bit Descriptions for PLA_DOUT1 Bit(s) [15:0] Bit Name DOUT Description Output bit from Element 31 to Element 16 Write Lock Register Address: 0x400058A0, Reset: 0x0000, Name: PLA_LCK This register can only be set once every reset. Table 220. Bit Descriptions for PLA_LCK Bit(s) [15:1] 0 Bit Name RESERVED LOCK Description Not used. Set to disable writing to registers. 0: writing to registers allowed. 1: writing to registers disabled. Rev. A | Page 148 of 190 Reset 0x0000 0x0 Access Reserved RW1S ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 GENERAL-PURPOSE TIMERS GENERAL-PURPOSE TIMERS FEATURES The ADuCM320i/ADuCM322/ADuCM322i integrate three identical general-purpose, 16-bit count-up/count-down timers: Timer 0, Timer 1, and Timer 2. The timers can be clocked from the following five different clock sources: • Peripheral clock (PCLK) • 80 MHz system clock (HCLK) • 32 kHz internal oscillator (LFOSC) • 16 MHz external crystal (HFXTAL) or internal 16 MHz oscillator (HFOSC), depending on the value in CLKCON0[11] Clock sources can be scaled down using a prescaler 1, 4, 16256, or 32768. Additionally, two of the clocks can be scaled down using a prescaler of 4, and the other two clock sources can be used directly (prescaler of 1). Two modes are available: free running and periodic. The timers have a capture events feature, with the capability to capture 15 different events on each timer. GENERAL-PURPOSE TIMERS BLOCK DIAGRAM 16-BIT LOAD CLOCK SOURCES PCLK PRESCALER 1, 4, 16256, OR 32768 HCLK LFOSC 16-BIT UP/DOWN COUNTER TIMER INTERRUPT HFXTAL/HFOSC TIMER VALUE CAPTURE NOTES 1. 16MHz EXTERNAL CRYSTAL (HFXTAL) OR INTERNAL 16MHz OSCILLATOR (HFOSC), DEPENDING ON THE VALUE IN CLKCON0[11]. 13437-029 EVENT SELECT Figure 30. General-Purpose Timers Block Diagram GENERAL-PURPOSE TIMERS OVERVIEW Timer 0, Timer 1, and Timer 2 are three identical general-purpose, 16-bit count-up/count-down timers. They can be clocked from the following five different clock sources: • • • • PCLK HCLK 32 kHz internal oscillator (LFOSC) 16 MHz external crystal (HFXTAL) or internal 16 MHz oscillator (HFOSC), depending on the value in CLKCON0[11]. The clock sources can be scaled down using a prescaler of 1, 4, 16256, or 32768. The timers can be either free running or periodic. In free running mode, the counter decrements from full scale to zero scale or increments from zero scale to full scale and then restarts. In periodic mode, the counter decrements or increments from the value in the load register (TxLD MMR, where x is 0 for Timer 0, 1 for Timer 1, and 2 for Timer 2) until zero scale or full scale is reached and then restarts at the value stored in the load register. The value of a counter can be read at any time by accessing its value register (TxVAL). The TxCON register selects the timer mode, configures the clock source, selects count-up/count-down, starts the counter, and controls the event capture function. An interrupt signal is generated each time the value of the counter reaches 0 when counting down, or each time the counter value reaches the maximum value when counting up. An IRQ can be cleared by writing 1 to the time clear interrupt register of that particular timer (TxCLRI). In addition, Timer 0, Timer 1, and Timer 2 have a capture register (TxCAP) that is triggered by a selected IRQ source initial assertion. When triggered, the current timer value is copied to TxCAP, and the timer continues to run. This feature can determine the assertion of an event with increased accuracy. Rev. A | Page 149 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual GENERAL-PURPOSE TIMER OPERATIONS Free Running Mode In free running mode, the timer is started by setting the enable bit (TxCON[4]) to 1 and the MOD bit (TxCON[3]) to 0. The timer increments from zero scale/full scale to full scale/zero scale if counting up/down. Full scale is 216 − 1 or 0xFFFF in binary format. Upon reaching full scale (or zero scale), a timeout interrupt occurs and TxSTA[0] is set. To clear the timer interrupt, user code must write 1 to TxCLRI[0]. If TxCON[7] is set, the timer keeps counting and reloads when the TxCLRI register is written. Periodic Mode In periodic mode, the initial TxLD value must be loaded before starting the timer by setting the enable bit (TxCON[4]) to 1. The timer value either increments from the value in TxLD to full scale or decrements from the value in TxLD to zero scale, depending on the TxCON[2] settings (count up/down). Upon reaching full scale or zero scale, the timer generates an interrupt. The TxLD is reloaded into TxVAL, and the timer continues counting up or down. The timer must be disabled prior to changing the TxCON or TxLD register. If the TxLD register is changed while the timer is being loaded, undefined results may occur. By default, the counter is reloaded automatically when generating the interrupt signal. If TxCON[7] is set to 1, the counter is also reloaded when user code writes TxCLRI, which allows user changes to the TxLD to take effect immediately instead of waiting until the next timeout. The timer interval is calculated as follows: If the timer is set to count down, Interval = (TxLD × Prescaler)/Source Clock For example, if TxLD = 0x100, prescaler = 4, and clock source = UCLK, the interval is 12.8 µs (where UCLK = 80 MHz). If the timer is set to count up, Interval = ((Full Scale − TxLD) × Prescaler)/Source Clock Asynchronous Clock Source Timers are started by setting the enable bit (TxCON[4]) to 1 in the control register of the corresponding timer. However, when the timer clock source is HFXTAL or LFOSC, some precautions must be taken: • • Do not write to the control register (TxCON) if TxSTA[6] is set. Therefore, TxSTA must be read prior to configuring the control register (TxCON). When TxSTA[6] is cleared, the register can be modified, ensuring that synchronizing the timer control between the processor and the timer clock domains is complete. TxSTA[6] is the timer busy status bit. After clearing the interrupt in TxCLRI, ensure that the register write has completed before returning from the interrupt handler. Use the data synchronization barrier (DSB) instruction if necessary and check that TxSTA[7] = 0. __asm void asmDSB() { nop DSB BX LR } • The value of a counter can be read at any time by accessing its value register (TxVAL). In an asynchronous configuration, TxVAL must always be read twice. If the two readings are different, it must be read a third time to determine the correct value. TxSTA must be read prior to writing to any timer register after setting or clearing the enable bit. When TxSTA[7] is cleared, registers can be modified, which ensures that the timer has completed synchronization between the processor and the timer clock domains. The typical synchronization time is two timer clock periods. The TxCON register enables the counter, selects the mode, selects the prescale value, and controls the event capture function. Rev. A | Page 150 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Capture Event Function The general-purpose timers can capture several interrupt events. These events are shown in Table 221. Any one of the events associated with a general-purpose timer can cause a capture of the 16-bit TxVAL register into the 16-bit TxCAP register. TxCON has a 4-bit field that can select which event to capture. When the selected interrupt event occurs, the TxVAL register is copied into the TxCAP register. When TxSTA[1] is set, it indicates that a capture event is pending. The bit is cleared by writing 1 to TxCLRI[1]. The TxCAP register also holds its value and cannot be overwritten until a 1 is written to TxCLRI[1]. Table 221. Capture Event Function Event Select Bits (EVENT) TxCON[11:8] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Timer 0 Capture Source Wake-up timer External Interrupt 0 External Interrupt 1 External Interrupt 2 Reserved External Interrupt 4 External Interrupt 5 Reserved External Interrupt 7 External Interrupt 8 Watchdog timer Reserved Reserved Low Voltage Analog Die Interrupt 0 MDIO General-Purpose Timer 1 Timer 1 Capture Source External Interrupt 4 External Interrupt 5 Reserved Flash controller UART SPI0 PLA 0 PLA 1 DMA error DMA done (any) Reserved Reserved Reserved I2C1 slave I2C1 master General-Purpose Timer 2 Rev. A | Page 151 of 190 Timer 2 Capture Source External Interrupt 7 External Interrupt 8 SPI1 I2C0 slave I2C0 master PLA 2 PLA 3 PWM trip PWM0 PWM1 PWM2 PWM3 Low Voltage Analog Die Interrupt 1 External Interrupt 0 External Interrupt 1 General-Purpose Timer 1 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: GENERAL-PURPOSE TIMER 0 Table 222. Timer 0 Register Summary Address 0x40000000 0x40000004 0x40000008 0x4000000C 0x40000010 0x4000001C Name T0LD T0VAL T0CON T0CLRI T0CAP T0STA Description 16-bit load value register 16-bit timer value register Control register Clear interrupt register Capture register Status register Reset 0x0000 0x0000 0x000A 0x0000 0x0000 0x0000 RW RW R RW W R R REGISTER DETAILS: GENERAL-PURPOSE TIMER 0 16-Bit Load Value Register Address: 0x40000000, Reset: 0x0000, Name: T0LD Table 223. Bit Descriptions for T0LD Bit(s) [15:0] Bit Name LOAD Description Load value. The up/down counter is periodically loaded with this value if periodic mode is selected (T0CON[3] = 1). LOAD writes during up/down counter timeout events are delayed until the event passes. Reset 0x0 Access RW Reset 0x0 Access R Reset 0x0 0x0 Access R RW 0x0 0x0 RW RW 0x0 RW 0x0 RW 0x1 RW 16-Bit Timer Value Register Address: 0x40000004, Reset: 0x0000, Name: T0VAL Table 224. Bit Descriptions for T0VAL Bit(s) [15:0] Bit Name VAL Description Current count. Reflects the current up/down counter value. Value delayed by two PCLK cycles due to clock synchronizers. Control Register Address: 0x40000008, Reset: 0x000A, Name: T0CON Table 225. Bit Descriptions for T0CON Bit(s) [15:13] 12 Bit Name RESERVED EVENTEN [11:8] 7 EVENT RLD [6:5] CLK 4 ENABLE 3 MOD Description Reserved. Event select. Used to enable and to disable the capture of events. This bit is used in conjunction with the EVENT select range. When a selected event occurs, the current value of the up/down counter is captured in T0CAP. 0: events are not captured. 1: events are captured. Event select range. Timer event select range (0 to 15). Reload control. RLD is only used for periodic mode. This bit allows the user to select whether the up/down counter should be reset only on a timeout event or also when T0CLRI[0] is set. 1: resets the up/down counter when T0CLRI[0] is set. 0: up/down counter is only reset on a timeout event. Clock select. Used to select a timer clock from the four available clock sources. 00: PCLK. 01: HCLK. 10: LFOSC. 32 kHz OSC. 11: HFXTAL. 16 MHz OSC or XTAL, dependent on the value in CLKCON0[11]. Timer enable. Used to enable and to disable the timer. Clearing this bit resets the timer, including the T0VAL register. 0: DIS. Timer is disabled (default). 1: EN. Timer is enabled. Timer mode. This bit controls whether the timer runs in periodic or free running mode. In periodic mode, the up/down counter starts at the defined LOAD value (T0LD). In free running mode, the up/down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down. 0: FREERUN. Timer runs in free running mode. 1: PERIODIC. Timer runs in periodic mode (default). Rev. A | Page 152 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 2 Bit Name UP [1:0] PRE Description Count up. Used to control whether the timer increments (counts up) or decrements (counts down) the up/down counter. 0: DIS. Timer is set to count down (default). 1: EN. Timer is set to count up. Prescaler. Controls the prescaler division factor applied to the timer's selected clock. If CLK Source 0 (PCLK) or CLK Source 1 (HCLK) is selected, Prescaler Value 0 means divide by 4, or else, it means divide by 1. 00: source clock/[1 or 4]. 01: source clock/16. 10: source clock/256. 11: source clock/32,768. UG-868 Reset 0x0 Access RW 0x2 RW Reset 0x0 0x0 Access R W1C 0x0 W1C Reset 0x0 Access R Reset 0x0 0x0 Access R R 0x0 R 0x0 0x0 R R 0x0 R Clear Interrupt Register Address: 0x4000000C, Reset: 0x0000, Name: T0CLRI Table 226. Bit Descriptions for T0CLRI Bit(s) [15:2] 1 Bit Name RESERVED CAP 0 TMOUT Description Reserved. Clear captured event interrupt. This bit is used to clear a capture event interrupt. 0: no effect. 1: clear the capture event interrupt. Clear timeout interrupt. This bit is used to clear a timeout interrupt. 0: no effect. 1: clears the timeout interrupt. Capture Register Address: 0x40000010, Reset: 0x0000, Name: T0CAP Table 227. Bit Descriptions for T0CAP Bit(s) [15:0] Bit Name CAP Description 16-bit captured value. T0CAP holds its value until T0CLRI[1] is set by user code. T0CAP is not overwritten even if another event occurs without writing to the T0CLRI[1]. Status Register Address: 0x4000001C, Reset: 0x0000, Name: T0STA Table 228. Bit Descriptions for T0STA Bit(s) [15:8] 7 Bit Name RESERVED PDOK 6 BUSY [5:2] 1 RESERVED CAP 0 TMOUT Description Reserved. T0CLRI synchronization. This bit is set automatically when the user sets T0CLRI[0] = 1. It is cleared automatically when the clear interrupt request has crossed clock domains and taken effect in the timer clock domain. 0: CLR. The interrupt is cleared in the timer clock domain. 1: SET. T0CLRI[0] is being updated in the timer clock domain. Timer busy. This bit informs the user that a write to T0CON is still crossing into the timer clock domain. Check this bit after writing T0CON and suppress further writes until this bit is cleared. 0: CLR. Timer ready to receive commands to T0CON. 1: SET. Timer not ready to receive commands to T0CON. Reserved. Capture event pending. 0: CLR. No capture event is pending. 1: SET. A capture event is pending. Timeout event occurred. This bit set automatically when the value of the counter reaches zero while counting down or reaches full scale when counting up. This bit is cleared when T0CLRI[0] is set by the user. 0: CLR. No timeout event has occurred. 1: SET. A timeout event has occurred. Rev. A | Page 153 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: GENERAL-PURPOSE TIMER 1 Table 229. Timer 1 Register Summary Address 0x40000400 0x40000404 0x40000408 0x4000040C 0x40000410 0x4000041C Name T1LD T1VAL T1CON T1CLRI T1CAP T1STA Description 16-bit load value register 16-bit timer value register Control register Clear interrupt register Capture register Status register Reset 0x0000 0x0000 0x000A 0x0000 0x0000 0x0000 RW RW R RW W R R REGISTER DETAILS: GENERAL-PURPOSE TIMER 1 16-Bit Load Value Register Address: 0x40000400, Reset: 0x0000, Name: T1LD Table 230. Bit Descriptions for T1LD Bit(s) [15:0] Bit Name LOAD Description Load value. The up/down counter is periodically loaded with this value if periodic mode is selected (T1CON[3] = 1). LOAD writes during up/down counter timeout events are delayed until the event passes. Reset 0x0 Access RW Reset 0x0 Access R Reset 0x0 0x0 Access R RW 0x0 0x0 RW RW 0x0 RW 0x0 RW 0x1 RW 16-Bit Timer Value Register Address: 0x40000404, Reset: 0x0000, Name: T1VAL Table 231. Bit Descriptions for T1VAL Bit(s) [15:0] Bit Name VAL Description Current count. Reflects the current up/down counter value. Value delayed two PCLK cycles due to clock synchronizers. Control Register Address: 0x40000408, Reset: 0x000A, Name: T1CON Table 232. Bit Descriptions for T1CON Bit(s) [15:13] 12 Bit Name RESERVED EVENTEN [11:8] 7 EVENT RLD [6:5] CLK 4 ENABLE 3 MOD Description Reserved. Event select. Used to enable and to disable the capture of events. This bit is used in conjunction with the EVENT select range. When a selected event occurs, the current value of the up/down counter is captured in T1CAP. 0: events are not captured. 1: events are captured. Event select range. Timer event select range (0 to 15). Reload control. RLD is only used for periodic mode. This bit allows the user to select whether the up/down counter should be reset only on a timeout event or also when T1CLRI[0] is set. 1: resets the up/down counter when T1CLRI[0] is set. 0: up/down counter is only reset on a timeout event. Clock select. Used to select a timer clock from the four available clock sources. 00: PCLK. 01: HCLK. 10: LFOSC. 32 KHz OSC 11: HFXTAL. 16 MHz OSC or XTAL, Dependent on the value in CLKCON0[11]. Timer enable. Used to enable and disable the timer. Clearing this bit resets the timer, including the T1VAL register. 0: DIS. Timer is disabled (default). 1: EN. Timer is enabled. Timer mode. This bit controls whether the timer runs in periodic or free running mode. In periodic mode, the up/down counter starts at the defined LOAD value (T1LD). In free running mode, the up/down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down. 0: FREERUN. Timer runs in free running mode. 1: PERIODIC. Timer runs in periodic mode (default). Rev. A | Page 154 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 2 Bit Name UP [1:0] PRE Description Count up. Used to control whether the timer increments (counts up) or decrements (counts down) the up/down counter. 0: DIS. Timer is set to count down (default). 1: EN. Timer is set to count up. Prescaler. Controls the prescaler division factor applied to the selected clock of the timer. If CLK Source 0 (PCLK) or CLK Source 1 (HCLK) is selected, then Prescaler Value 0 means divide by 4, else it means divide by 1. 00: source clock/[1 or 4]. 01: source clock/16. 10: source clock/256. 11: source clock/32,768. UG-868 Reset 0x0 Access RW 0x2 RW Reset 0x0 0x0 Access R W1C 0x0 W1C Reset 0x0 Access R Reset 0x0 0x0 Access R R 0x0 R 0x0 0x0 R R 0x0 R Clear Interrupt Register Address: 0x4000040C, Reset: 0x0000, Name: T1CLRI Table 233. Bit Descriptions for T1CLRI Bit(s) [15:2] 1 Bit Name RESERVED CAP 0 TMOUT Description Reserved. Clear captured event interrupt. This bit is used to clear a capture event interrupt. 0: no effect. 1: clear the capture event interrupt. Clear timeout interrupt. This bit is used to clear a timeout interrupt. 0: no effect. 1: clears the timeout interrupt. Capture Register Address: 0x40000410, Reset: 0x0000, Name: T1CAP Table 234. Bit Descriptions for T1CAP Bit(s) [15:0] Bit Name CAP Description 16-bit captured value. T1CAP holds its value until T1CLRI[1] is set by user code. T1CAP is not overwritten even if another event occurs without writing to the T1CLRI[1]. Status Register Address: 0x4000041C, Reset: 0x0000, Name: T1STA Table 235. Bit Descriptions for T1STA Bit(s) [15:8] 7 Bit Name RESERVED PDOK 6 BUSY [5:2] 1 RESERVED CAP 0 TMOUT Description Reserved. T1CLRI synchronization. This bit is set automatically when the user sets T1CLRI[0] = 1. It is cleared automatically when the clear interrupt request has crossed clock domains and taken effect in the timer clock domain. 0: CLR. The interrupt is cleared in the timer clock domain. 1: SET. T1CLRI[0] is being updated in the timer clock domain. Timer busy. This bit informs the user that a write to T1CON is still crossing into the timer clock domain. Check this bit after writing T1CON and suppress further writes until this bit is cleared. 0: CLR. Timer ready to receive commands to T1CON. 1: SET. Timer not ready to receive commands to T1CON. Reserved. Capture event pending. 0: CLR. No capture event is pending. 1: SET. A capture event is pending. Timeout event occurred. This bit set automatically when the value of the counter reaches zero while counting down or reaches full scale when counting up. This bit is cleared when T1CLRI[0] is set by the user. 0: CLR. No timeout event has occurred. 1: SET. A timeout event has occurred. Rev. A | Page 155 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: GENERAL-PURPOSE TIMER 2 Table 236. Timer 2 Register Summary Address 0x40000800 0x40000804 0x40000808 0x4000080C 0x40000810 0x4000081C Name T2LD T2VAL T2CON T2CLRI T2CAP T2STA Description 16-bit load value register 16-bit timer value register Control register Clear interrupt register Capture register Status register Reset 0x0000 0x0000 0x000A 0x0000 0x0000 0x0000 RW RW R RW W R R REGISTER DETAILS: GENERAL-PURPOSE TIMER 2 16-Bit Load Value Register Address: 0x40000800, Reset: 0x0000, Name: T2LD Table 237. Bit Descriptions for T2LD Bit(s) [15:0] Bit Name LOAD Description Load value. The up/down counter is periodically loaded with this value if periodic mode is selected (T2CON[3 ] =1). LOAD writes during up/down counter timeout events are delayed until the event passes. Reset 0x0 Access RW Reset 0x0 Access R Reset 0x0 0x0 Access R RW 0x0 0x0 RW RW 0x0 RW 0x0 RW 0x1 RW 16-Bit Timer Value Register Address: 0x40000804, Reset: 0x0000, Name: T2VAL Table 238. Bit Descriptions for T2VAL Bit(s) [15:0] Bit Name VAL Description Current count. Reflects the current up/down counter value. Value delayed two PCLK cycles due to clock synchronizers. Control Register Address: 0x40000808, Reset: 0x000A, Name: T2CON Table 239. Bit Descriptions for T2CON Bit(s) [15:13] 12 Bit Name RESERVED EVENTEN [11:8] 7 EVENT RLD [6:5] CLK 4 ENABLE 3 MOD Description Reserved. Event select. Used to enable and to disable the capture of events. This bit is used in conjunction with the EVENT select range. When a selected event occurs, the current value of the up/down counter is captured in T2CAP. 0: events are not captured. 1: events are captured. Event select range. Timer event select range (0 to 15). Reload control. RLD is only used for periodic mode. This bit allows the user to select whether the up/down counter should be reset only on a timeout event or also when T2CLRI[0] is set. 1: resets the up/down counter when T2CLRI[0] is set. 0: up/down counter is only reset on a timeout event. Clock select. Used to select a timer clock from the four available clock sources. 00: PCLK. 01: HCLK. 10: LFOSC. 32 KHz OSC. 11: HFXTAL. 16 MHz OSC or XTAL, dependent on the value in CLKCON0[11]. Timer enable. Used to enable and to disable the timer. Clearing this bit resets the timer, including the T2VAL register. 0: DIS. Timer is disabled (default). 1: EN. Timer is enabled. Timer mode. This bit controls whether the timer runs in periodic or free running mode. In periodic mode, the up/down counter starts at the defined LOAD value (T2LD). In free running mode, the up/down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down. 0: FREERUN. Timer runs in free running mode. 1: PERIODIC. Timer runs in periodic mode (default). Rev. A | Page 156 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 2 Bit Name UP [1:0] PRE Description Count up. Used to control whether the timer increments (counts up) or decrements (counts down) the up/down counter. 0: DIS. Timer is set to count down (default). 1: EN. Timer is set to count up. Prescaler. Controls the prescaler division factor applied to the selected clock of the timer. If CLK Source 0 (PCLK) or CLK Source 1 (HCLK) is selected, then Prescaler Value 0 means divide by 4, else it means divide by 1. 00: source clock/[1 or 4]. 01: source clock/16. 10: source clock/256. 11: source clock/32,768. UG-868 Reset 0x0 Access RW 0x2 RW Clear Interrupt Register Address: 0x4000080C, Reset: 0x0000, Name: T2CLRI Table 240. Bit Descriptions for T2CLRI Bit(s) [15:2] 1 Bit Name RESERVED CAP 0 TMOUT Description Reserved. Clear captured event interrupt. This bit is used to clear a capture event interrupt. 0: no effect. 1: clear the capture event interrupt. Clear timeout interrupt. This bit is used to clear a timeout interrupt. 0: no effect. 1: clears the timeout interrupt. Reset 0x0 0x0 Access R W1C 0x0 W1C Capture Register Address: 0x40000810, Reset: 0x0000, Name: T2CAP Table 241. Bit Descriptions for T2CAP Bit(s) [15:0] Bit Name CAP Description 16-bit captured value. T2CAP holds its value until T2CLRI[1] is set by user code. T2CAP is not overwritten even if another event occurs without writing to the T2CLRI[1]. Reset 0x0 Access R Reset 0x0 0x0 Access R R 0x0 R 0x0 0x0 R R 0x0 R Status Register Address: 0x4000081C, Reset: 0x0000, Name: T2STA Table 242. Bit Descriptions for T2STA Bit(s) [15:8] 7 Bit Name RESERVED PDOK 6 BUSY [5:2] 1 RESERVED CAP 0 TMOUT Description Reserved. T2CLRI synchronization. This bit is set automatically when the user sets T2CLRI[0] = 1. It is cleared automatically when the clear interrupt request has crossed clock domains and taken effect in the timer clock domain. 0: CLR. The interrupt is cleared in the timer clock domain. 1: SET. T2CLRI[0] is being updated in the timer clock domain. Timer Busy. This bit informs the user that a write to T2CON is still crossing into the timer clock domain. Check this bit after writing T2CON and suppress further writes until this bit is cleared. 0: CLR. Timer ready to receive commands to T2CON. 1: SET. Timer not ready to receive commands to T2CON. Reserved. Capture event pending. 0: CLR. No capture event is pending. 1: SET. A capture event is pending. Timeout event occurred. This bit set automatically when the value of the counter reaches zero while counting down or reaches full scale when counting up. This bit is cleared when T2CLRI[0] is set by the user. 0: CLR. No timeout event has occurred. 1: SET. A timeout event has occurred. Rev. A | Page 157 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual WATCHDOG TIMER WATCHDOG TIMER FEATURES The watchdog timer is a 16-bit count down timer that can recover from an invalid software state. The 32 kHz internal oscillator (LFOSC) clocks the timer with a programmable prescaler (1, 16256, or 4096). WATCHDOG TIMER BLOCK DIAGRAM 16-BIT LOAD PRESCALER 1, 16256, OR 4096 WATCHDOG TIMER RESET 1616-BIT BIT UP/DOWN DOWN COUNTER COUNTER WATCHDOG TIMER INTERRUPT TIMER 3 VALUE 13437-032 LFOSC Figure 31. Watchdog Timer Block Diagram WATCHDOG TIMER OVERVIEW The watchdog timer (Timer 3) can recover from an invalid software state. When enabled, this timer requires periodic servicing to prevent it from forcing a reset of the device. For debug purposes, the timer can generate an interrupt instead of a reset. The internal 32.768 kHz oscillator, LFOSC clocks the watchdog timer. It is clocked at all times except during a reset. The watchdog timer is a 16-bit count down timer with a programmable prescalar. The prescalar is selectable and can divide LFOSC by a factor of 1, 16256, or 4096. WATCHDOG TIMER OPERATION The watchdog timer is enabled by default after a reset. When debugging, the user code should disable the watchdog timer at the start of the user code, or if the watchdog timer is not required. T3CON = 0x00; // Disable watchdog timer Enabling the watchdog timer (set T3CON[5] = 1) also write protects the T3CON and T3LD registers. After kernel execution, the user code can disable the timer and then reconfigure it with T3CON[5] = 1 only once. Then, the T3CON and T3LD registers are write protected. T3STA[4] indicates if the timer configuration has been locked. Only a reset clears T3CON[5], unlocking the T3CON and T3LD registers, and allows reconfiguration of the timer. If the T3CON register is not modified, the user code can change the T3LD register at any time. If T3CON[5] is cleared to 0, the timer is disabled. Settings can be modified and the timer can be reenabled. When the watchdog timer is used in interrupt mode (T3STA[0]), the watchdog timer interrupt bit is set to 1 for a very short period (2 × PCLK); therefore, do not use T3STA[0] for polling purposes. Rev. A | Page 158 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER SUMMARY: WATCHDOG TIMER Table 243. Watchdog Timer Register Summary Address 0x40002580 0x40002584 0x40002588 0x4000258C 0x40002598 Name T3LD T3VAL T3CON T3CLRI T3STA Description Load value register Current count value register Control register Clear interrupt register Status register Reset 0x1000 0x1000 0x00E9 0x0000 0x0000 RW RW R RW W R Reset 0x1000 Access RW Reset 0x1000 Access R Reset 0x1 0x1 Access R RW 0x1 RW 0x0 0x2 R RW 0x0 RW 0x1 RW REGISTER DETAILS: WATCHDOG TIMER Load Value Register Address: 0x40002580, Reset: 0x1000, Name: T3LD Table 244. Bit Descriptions for T3LD Bit(s) [15:0] Bit Name LOAD Description Load value Current Count Value Register Address: 0x40002584, Reset: 0x1000, Name: T3VAL Table 245. Bit Descriptions for T3VAL Bit(s) [15:0] Bit Name CCOUNT Description Current count value Control Register Address: 0x40002588, Reset: 0x00E9, Name: T3CON Table 246. Bit Descriptions for T3CON Bit(s) [15:7] 6 Bit Name RESERVED MOD 5 ENABLE 4 [3:2] RESERVED PRE 1 IRQ 0 PMD Description Reserved. Timer mode. Note that, in free running mode, it wraps around at 0x1000. 0: FREERUN. Cleared by user to operate in free running mode. 1: PERIODIC. Set by user to operate in periodic mode (default). Timer enable. 0: DIS. Cleared by user to disable the timer. 1: EN. Set by user to enable the timer (default). Reserved. Prescaler. 00: DIV1. Source clock/1. 01: DIV16. Source clock/16. 10: DIV256. Source clock/256 (default). 11: DIV4096. Source clock/4096. Timer interrupt. 0: DIS. Cleared by user to generate a reset on a time out (default). 1: EN. Set by user to generate an interrupt when the timer times out. This feature is provided for debug purposes and is only available in active mode. Power Mode Disable. PMD controls the behavior of the watchdog when in hibernate mode. If the application requires prolonged time periods spent in hibernate mode, and it is not desirable to periodically wake up to service the watchdog timer, the counter within the watchdog timer can be suspended when entering hibernate power mode. Regardless of how the PMD bit is set, it is recommended that the watchdog timer be cleared before entering hibernate mode. 0: DIS. The watchdog timer continues its countdown while in hibernate mode. 1: EN. When hibernate mode is entered, the watchdog counter suspends its countdown. When hibernate mode is exited, the countdown resumes from its current count value (the count is not reset). Rev. A | Page 159 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Clear Interrupt Register Address: 0x4000258C, Reset: 0x0000, Name: T3CLRI Table 247. Bit Descriptions for T3CLRI Bit(s) [15:0] Bit Name CLRWDG Description Clear watchdog. User writes 0xCCCC to reset/reload/restart Timer 3 or clear IRQ. A write of any other value causes a watchdog reset. Write only, reads 0. Do not write to this register if using the timer in IRQ mode. Reset 0x0 Access W Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R Status Register Address: 0x40002598, Reset: 0x0000, Name: T3STA Table 248. Bit Descriptions for T3STA Bit(s) [15:5] 4 Bit Name RESERVED LOCK 3 CON 2 LD 1 CLRI 0 IRQ Description Reserved. Lock status bit. Set automatically in hardware if T3CON[5] has been set by user code. Cleared by default and until user code sets T3CON[5]. T3CON write sync in progress. 0: internal bus and Timer 3 clock domains T3CON configuration values match. 1: internal bus T3CON register values are being synchronized to Timer 3 clock domain. T3LD write sync in progress. 0: internal bus and Timer 3 clock domains T3LD values match. 1: internal bus T3LD value is being synchronized to Timer 3 clock domain. T3CLRI write sync in progress. 0: internal bus T3CLRI write sync not done. 1: internal bus T3CLRI write is being synced to Timer 3 clock domain. Timer 3 is restarted (if 0xCCCC was written) when sync is complete. Watchdog timer interrupt. 0: Timer 3 interrupt not pending. 1: Timer 3 interrupt pending. Rev. A | Page 160 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 WAKE-UP TIMER WAKE-UP TIMER FEATURES The wake-up timer features for the ADuCM320i/ADuCM322/ADuCM322i include the following: • • • 32-bit counter (count down or count up) Three clock sources with programmable prescaler (1, 16256, or 32768) • Peripheral clock (PCLK) • 32 kHz internal oscillator (LFOSC) • External clock applied on Pin P1.0 (ECLKIN) Four compare points, one automatic increment WAKE-UP TIMER BLOCK DIAGRAM 32-BIT COMPARE A 32-BIT COMPARE B 32-BIT COMPARE C 32-BIT COMPARE D 12-BIT INTERVAL A CLOCK SOURCES PCLK PRESCALER 1, 16256, OR 32768 TIMER 4 INTERRUPT 32-BIT UP/DOWN COUNTER MCU WAKE-UP ECLKIN TIMER 4 VALUE 13437-030 LFOSC Figure 32. Wake-Up Timer Block Diagram WAKE-UP TIMER OVERVIEW The wake-up timer (Timer 4) block consists of a 32-bit counter clocked from one of three different sources: the system clock (PCLK), the internal oscillator (LFOSC), or an external clock applied on Pin P1.0 (ECLKIN). The selected clock source can be scaled down using a prescaler of 1, 16256, or 32768. The wake-up timer continues to run independent of the clock source used when the PCLK clock is disabled. The timer can be used in free running or periodic mode. In free running mode, the timer counts from 0x00000000 to 0xFFFFFFFF and then restarts at 0x00000000. In periodic mode, the timer counts from 0x00000000 to T4WUFD (T4WUFD0 and T4WUFD1). In addition, the wake-up timer has four specific time fields to compare with the wake-up counter: T4WUFA, T4WUFB, T4WUFC, and T4WUFD. All four wake-up compare points can generate interrupts or wake-up signals. When the timer is in free running mode, T4WUFA, T4WUFB, T4WUFC, andT4WUFD must be reconfigured in the software to generate a periodic interrupt. WAKE-UP TIMER OPERATION The wake-up timer comparator registers must be configured before starting the timer. The timer is started by writing to the control enable bit (T4CON[7]). The timer increments until the value reaches full scale in free running mode or when T4WUFD matches the wake-up value (T4VAL). The wake-up timer is a 32-bit timer. Its current value is stored in two 16-bit registers: T4VAL1 stores the upper 16 bits, and T4VAL0 stores the lower 16 bits. When T4VAL0 is read, T4VAL1 is frozen at its current value until it is subsequently read. The freeze control bit (T4CON[3]) must be set to freeze the T4VAL value between the lower and upper reads. Clock Selection Clock selection is made by setting T4CON[10:9]. If PCLK is selected (T4CON[10:9] = 00), configuring T4CON[1:0] = 00 results in a prescaler of 4. Synchronization to the LFOSC clock domain is done automatically by hardware, and precautions concerning asynchronous clocks as described in Timer 0, Timer 1, and Timer 2 do not apply. Rev. A | Page 161 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Compare Field Registers Hardware Updated Field T4INC is a 12-bit interval register that updates the compare value in T4WUFAx by using the hardware. When a new value is written in T4INC, Bits[16:5] of the internal 32-bit compare register (T4WUFAx) are loaded with the new T4INC value. If the new compare value is less than the T4WUFD value in periodic mode or less than 0xFFFFFFFF in free running mode, this 32-bit compare register is automatically incremented with the contents of T4INC (shifted by five) each time the wake-up counter reaches the value in this compare register. If the new compare value is greater than these limits, it is recalculated as follows. In free running mode, the new value is T4WUFA = Old T4WUFA + (32 × T4INC) − 0xFFFFFFFF. In periodic mode, the new value is T4WUFA = Old T4WUFA + (32 × T4INC) − T4WUFD. The maximum programmable interval is just above 4 seconds. T4INC is compared with Bits[16:5] of the timer value. Because it is shifted left by five bits, its value must be multiplied by 32 to obtain the compare value. With the default value of 0xC8 (where for calculation purposes 0xC8 = 200 in decimal), a prescaler = 1, and a 32 kHz clock selected, Interval = ((200 × 32) + 1) × 1/32,768 = 195.3155 ms To modify the interval value, the timer must be stopped so that the interval register can be loaded in the compare register if T4CON[11] = 0. To modify the interval value, set STOPINC (T4CON[11] = 1) while the timer is running. The new T4INC value takes effect after the next Wake-Up Field A interrupt. If the user is writing to this register while the timer is enabled, the STOPINC bit must be set before writing to it, and then STOPINC must be cleared after the update. Software Updated Field T4WUFB, T4WUFC, and T4WUFD are 32-bit values programmed by the user in the T4WUFx0 and T4WUFx1 registers (x = B, C, or D). T4WUFD contains the load value when the wake-up timer is configured in periodic mode. The T4WUFBx and T4WUFCx registers can be written to at any time; however, the corresponding interrupt enable (T4IEN[1] or T4IEN[2]) must be disabled. After the register is updated, the interrupt can be reenabled. In periodic mode, the T4WUFDx registers can be written to only when the timer is disabled. In free running mode, the T4WUFDx registers can be written to while the timer is running. Before doing so, the corresponding interrupt enable (T4IEN[3]) must be disabled. After the register is updated, the interrupt can be reenabled. In free running mode, T4WUFB, T4WUFC, and T4WUFD can be written to at any time, but the corresponding interrupt enable in the T4IEN register must be disabled. After the register is updated, the interrupt can be reenabled. In periodic mode, this is only applicable to T4WUFB and T4WUFC. FREE RUNNING: 0xFFFFFFFF PERIODIC: T4WUFD = T4VAL T4WUFD TIMER VALUE T4INC T4INC T4INC T4INC T4INC T4WUFC T4WUFB INTERUPTS T4WUFA (T4INC, T4WUFB, T4WUFC, AND T4WUFD VALUES ARE SET BY USER) T4WUFA T4WUFA T4WUFA T4WUFA Figure 33. Wake-Up Timer Fields Action Rev. A | Page 162 of 190 T4WUFA 13437-031 0x00000000 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Interrupts/Wake-Up Signals An interrupt is generated when the counter value corresponds to any of the compare points or full scale in free running mode. The timer continues counting or is reset to 0. The wake-up timer generates five maskable interrupts. They are enabled in the T4IEN register. Interrupts can be cleared by setting the corresponding bit in the T4CLRI register. Note that it takes two 32 kHz clock cycles for the interrupt clear to take effect when the 32 kHz internal oscillator is used. Ensure that the register write has fully completed before returning from the interrupt handler. Use the data synchronization barrier (DSB) instruction if necessary. The following is a code example showing how to implement the DSB ARM Cortex-M3 instruction in a C program. void Ext_Int4_Handler () { EiClr(EXTINT4); __DSB(); } During that time, do not place the device in any of the power-down modes. IRQCRY (T4STA[6]) indicates when the device can be placed in power-down mode. The timer is stopped and reset when clearing the timer enable bit in the T4CON register (T4CON[7]). Rev. A | Page 163 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: WAKE-UP TIMER Table 249. Wake-Up Timer Register Summary Address 0x40002500 0x40002504 0x40002508 0x4000250C 0x40002510 0x40002514 0x40002518 0x4000251C 0x40002520 0x40002524 0x40002528 0x4000252C 0x40002530 0x4000253C 0x40002540 Name T4VAL0 T4VAL1 T4CON T4INC T4WUFB0 T4WUFB1 T4WUFC0 T4WUFC1 T4WUFD0 T4WUFD1 T4IEN T4STA T4CLRI T4WUFA0 T4WUFA1 Description Current count value, least significant 16 bits Current count value, most significant 16 bits Control register 12-bit interval for Wake-Up Field A Wake-Up Field B, least significant 16 bits Wake-Up Field B, most significant 16 bits Wake-Up Field C, least significant 16 bits Wake-Up Field C, most significant 16 bits Wake-Up Field D, least significant 16 bits Wake-Up Field D, most significant 16 bits Interrupt enable register Status register Clear interrupt register Wake-Up Field A, least significant 16 bits Wake-Up Field A, most significant 16 bits Reset 0x0000 0x0000 0x0040 0x00C8 0x1FFF 0x0000 0x2FFF 0x0000 0x3FFF 0x0000 0x0000 0x0000 0x0000 0x1900 0x0000 RW R R RW RW RW RW RW RW RW RW RW R W R R REGISTER DETAILS: WAKE-UP TIMER Current Count Value, Least Significant 16 Bits Register Address: 0x40002500, Reset: 0x0000, Name: T4VAL0 Table 250. Bit Descriptions for T4VAL0 Bit(s) [15:0] Bit Name T4VALL Description Current count low. Least significant 16 bits of current count value. Reset 0x0 Access R Reset 0x0 Access R Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW Current Count Value, Most Significant 16 Bits Register Address: 0x40002504, Reset: 0x0000, Name: T4VAL1 Table 251. Bit Descriptions for T4VAL1 Bit(s) [15:0] Bit Name T4VALH Description Current count high. Most significant 16 bits of current count value. Control Register Address: 0x40002508, Reset: 0x0040, Name: T4CON Table 252. Bit Descriptions for T4CON Bit(s) [15:12] 11 Bit Name RESERVED STOP_WUFA [10:9] CLK 8 WUEN 7 ENABLE Description Reserved. Disables updating Field A register T4WUFA. This bit when set stops the Wake-Up Field A register, T4WUFA, from being updated with the interval register I2INC value. This allows the user to update the interval T4INC or T4WUFA registers safely. Clock select. 00: PCLK, PCLK (default). 01: LFOSC, 32 kHz internal oscillator. 10: LFOSC, 32 kHz internal oscillator. 11: ECLKIN, external clock from P1.0. Wake-up enable. 0: DIS, cleared by user to disable the wake up timer when the core clock is off. 1: EN, set by user to enable the wake up timer even when the core clock is off. Timer enable. 0: DIS, disable the timer (default). 1: EN, enable the timer. Rev. A | Page 164 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 6 Bit Name MOD [5:4] 3 RESERVED FREEZE 2 [1:0] RESERVED PRE Description Timer mode. 0: PERIODIC, cleared by user to operate in periodic mode. In this mode, the timer counts up to T4WUFD. 1: FREERUN, set by user to operate in free running mode (default). Reserved. These bits should be written 0. Freeze enable. 0: DIS, cleared by user to disable this feature (default). 1: EN, set by user to enable the freeze of the high 16-bits after the lower bits have been read from T4VAL0. This ensures that the software reads an atomic shot of the timer. T4VAL1 unfreezes after it has been read. Reserved. Prescaler. 00: PREDIV1, source clock/1 (default). If the selected clock source is PCLK, this setting results in a prescaler of 4. 01: PREDIV16, source clock/16. 10: PREDIV256, source clock/256. 11: PREDIV32768, source clock/32,768. UG-868 Reset 0x1 Access RW 0x0 0x0 RW RW 0x0 0x0 RW RW Reset 0x0 0x0C8 Access R RW Reset 0x1FFF Access RW Reset 0x0 Access RW Reset 0x2FFF Access RW Reset 0x0 Access RW 12-Bit Interval for Wake-Up Field A Register Address: 0x4000250C, Reset: 0x00C8, Name: T4INC Table 253. Bit Descriptions for T4INC Bit(s) [15:12] [11:0] Bit Name RESERVED INTERVAL Description Reserved Interval for Wake-Up Field A Wake-Up Field B, Least Significant 16 Bits Register Address: 0x40002510, Reset: 0x1FFF, Name: T4WUFB0 Table 254. Bit Descriptions for T4WUFB0 Bit(s) [15:0] Bit Name T4WUFBL Description Wake-Up Field B low. Least significant 16 bits of Wake-Up Field B. Wake-Up Field B, Most Significant 16 Bits Register Address: 0x40002514, Reset: 0x0000, Name: T4WUFB1 Table 255. Bit Descriptions for T4WUFB1 Bit(s) [15:0] Bit Name T4WUFBH Description Wake-Up Field B High. Most significant 16 bits of Wake-Up Field B. Wake-Up Field C, Least Significant 16 Bits Register Address: 0x40002518, Reset: 0x2FFF, Name: T4WUFC0 Table 256. Bit Descriptions for T4WUFC0 Bit(s) [15:0] Bit Name T4WUFCL Description Wake-Up Field C Low. Least significant 16 bits of Wake-Up Field C. Wake-Up Field C, Most Significant 16 Bits Register Address: 0x4000251C, Reset: 0x0000, Name: T4WUFC1 Table 257. Bit Descriptions for T4WUFC1 Bit(s) [15:0] Bit Name T4WUFCH Description Wake-Up Field C High. Most significant 16 bits of Wake-Up Field C. Rev. A | Page 165 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Wake-Up Field D, Least Significant 16 Bits Register Address: 0x40002520, Reset: 0x3FFF, Name: T4WUFD0 Table 258. Bit Descriptions for T4WUFD0 Bit(s) [15:0] Bit Name T4WUFD0 Description Wake-Up Field D Low. Least significant 16 bits of Wake-Up Field C. Reset 0x3FFF Access RW Reset 0x0 Access RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 R Wake-Up Field D, Most Significant 16 Bits Register Address: 0x40002524, Reset: 0x0000, Name: T4WUFD1 Table 259. Bit Descriptions for T4WUFD1 Bit(s) [15:0] Bit Name T4WUFDH Description Wake-Up Field D high. Most significant 16 bits of Wake-Up Field D. Interrupt Enable Register Address: 0x40002528, Reset: 0x0000, Name: T4IEN Table 260. Bit Descriptions for T4IEN Bit(s) [15:5] 4 Bit Name RESERVED ROLL 3 WUFD 2 WUFC 1 WUFB 0 WUFA Description Reserved. Rollover interrupt enable. Used only in free running mode. Set by user to generate an interrupt when Timer2 rolls over. Cleared by user to disable the roll over interrupt (default). T4WUFD interrupt enable. Set by user code to generate an interrupt when T4VAL reaches T4WUFD. Cleared by user code to disable T4WUFD interrupt (default). T4WUFC interrupt enable. Set by user code to generate an interrupt when T4VAL reaches T4WUFC. Cleared by user code to disable T4WUFC interrupt (default). T4WUFB interrupt enable. Set by user code to generate an interrupt when T4VAL reaches T4WUFB. Cleared by user code to disable T4WUFB interrupt (default). T4WUFA interrupt enable. Set by user code to generate an interrupt when T4VAL reaches T4WUFA. Cleared by user code to disable T4WUFA interrupt (default). Status Register Address: 0x4000252C, Reset: 0x0000, Name: T4STA Table 261. Bit Descriptions for T4STA Bit(s) [15:9] 8 Bit Name RESERVED PDOK 7 FREEZE 6 IRQCRY 5 4 RESERVED ROLL 3 WUFD 2 WUFC 1 WUFB 0 WUFA Description Reserved. Enable bit synchronized. Indicates when a change in the enable bit is synchronized to the 32 kHz clock domain. It is set high when the enable bit (Bit 5) in the control register is set or cleared. It returns low when the change in the enable bit has been synchronized to the 32 kHz clock domain. Timer value freeze. Set automatically to indicate that the value in T4VAL1 is frozen. Cleared by automatically when T4VAL1 is read. Wake-up status to power-down. Set automatically when any of the interrupts are still set in the external crystal clock domain. Cleared automatically when the interrupts are cleared, allowing powerdown mode. User code should wait for this bit to be cleared before entering power-down mode. Reserved. Roll over interrupt flag. Used only in free running mode. Set automatically to indicate a roll over interrupt has occurred. Cleared automatically after a write to T4CLRI. T4WUFD interrupt flag. Set automatically to indicate a comparator interrupt has occurred. Cleared automatically after a write to the corresponding bit in T4CLRI. T4WUFC interrupt flag. Set automatically to indicate a comparator interrupt has occurred. Cleared automatically after a write to the corresponding bit in T4CLRI. T4WUFB interrupt flag. Set automatically to indicate a comparator interrupt has occurred. Cleared automatically after a write to the corresponding bit in T4CLRI. T4WUFA interrupt flag. Set automatically to indicate a comparator interrupt has occurred. Cleared automatically after a write to the corresponding bit in T4CLRI. Rev. A | Page 166 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Clear Interrupt Register Address: 0x40002530, Reset: 0x0000, Name: T4CLRI Table 262. Bit Descriptions for T4CLRI Bit(s) [15:5] 4 Bit Name RESERVED ROLL 3 2 WUFD WUFC 1 WUFB 0 WUFA Description Reserved. Rollover interrupt clear. Used only in free running mode. Set by user code to clear a roll over interrupt flag. Cleared automatically after synchronization. T4WUFD interrupt clear. T4WUFC interrupt clear. Set by user code to clear a T4WUFC interrupt flag. Cleared automatically after synchronization. T4WUFB interrupt clear. Set by user code to clear a T4WUFB interrupt flag. Cleared automatically after synchronization. T4WUFA interrupt clear. Set by user code to clear a T4WUFA interrupt flag. Cleared automatically after synchronization. Reset 0x0 0x0 Access R RW 0x0 0x0 RW RW 0x0 RW 0x0 RW Reset 0x1900 Access RW Reset 0x0 Access RW Wake-Up Field A, Least Significant 16 Bits Register Address: 0x4000253C, Reset: 0x1900, Name: T4WUFA0 Table 263. Bit Descriptions for T4WUFA0 Bit(s) [15:0] Bit Name T4WUFAL Description Wake-Up Field A low. Least significant 16 bits of Wake-Up Field A. Wake-Up Field A, Most Significant 16 Bits Register Address: 0x40002540, Reset: 0x0000, Name: T4WUFA1 Table 264. Bit Descriptions for T4WUFA1 Bit(s) [15:0] Bit Name T4WUFAH Description Wake-Up Field A high. Most significant 16 bits of Wake-Up Field A. Rev. A | Page 167 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual PULSE WIDTH MODULATOR (PWM) PWM FEATURES The PWM features an 8-channel PWM interface, and H-bridge mode supported on two pairs. PWM OVERVIEW The ADuCM320i/ADuCM322/ADuCM322i integrate an 8-channel PWM interface. Eight channels are grouped as three pairs (0 to 3). The first two pairs of PWM outputs (PWM0, PWM1, PWM2, and PWM3) can be configured in standard mode or to drive an H-bridge. Pair 2 and Pair 3 can only be configured in standard mode. The PWM pairs and modes are summarized in Table 265. Table 265. PWM Channel Grouping Port Name PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 Description High-side PWM output for Pair 0 Low-side PWM output for Pair 0 High-side PWM output for Pair 1 Low-side PWM output for Pair 1 High-side PWM output for Pair 2 Low-side PWM output for Pair 2 High-side PWM output for Pair 3 Low-side PWM output for Pair 3 PWM Mode Available H-bridge and standard H-bridge and standard H-bridge and standard H-bridge and standard Standard Standard Standard Standard On power-up, the PWM outputs default to H-bridge mode for Pair 0 and Pair 1. In the standard mode, users have control over the period of each pair of outputs and over the duty cycle of each individual output. In the event of external fault conditions, a falling edge on the PWMTRIP signal provides an instantaneous shutdown of the PWM controller. All PWM outputs are placed in an off state, that is, in low state for the low side and high state for the high side, and a PWMTRIP interrupt can be generated. PWM OPERATION The PWM clock is selectable via the PWMCON0 register with one of the following values: HCLK divided by 2, 4, 8, 16, 32, 64, 128, or 256. In all modes, the PWMxCOMx MMRs control the point at which the PWM output changes state. An example is shown in Figure 34. Each pair has an associated counter. The PWMxLEN register defines the length of the PWM period. The count value of the 16-bit timer and the compare register contents set the PWM waveforms. An example for PWM Pair 0 (Port PWM0 and Port PWM1) is as follows: • • The low-side waveform (PWM1) goes high when the timer count reaches the value held in the PWM0LEN register, and it goes low when the timer count reaches the value held in the PWM0COM2 register or when the high-side waveform PWM0 goes low. The high-side waveform (PWM0) goes high when the timer count reaches the value held in the PWM0COM0 register, and it goes low when the timer count reaches the value held in the PWM0COM1 register. Rev. A | Page 168 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 PAIR 0 TIMER 0xFFFF PWM0LEN PWM0COM0 PWM0COM1 PWM0COM2 0x0000 PWM0COM2 PWM0COM1 PWM0COM0 PWM0LEN PAIR 0 OUTPUTS PWM0 HIGH SIDE NOTES 1. NOTE THAT THE HIGH-SIDE PWM OUTPUT FOR EACH CHANNEL MUST HAVE A HIGH DURATION PERIOD GREATER THAN OR EQUAL TO THE HIGH PERIOD DURATION OF THE LOW-SIDE OUTPUT. FOR EXAMPLE, THE HIGH PERIOD FOR PWM0 MUST BE GREATER THAN OR EQUAL TO THE HIGH PERIOD OF PWM1. 13437-033 PWM1 LOW SIDE Figure 34. Waveform of PWM Channel Pair in Standard Mode Table 266 lists equations for the period and duration for both the outputs of a PWM channel. Table 266. PWM Equations PWM Low Side (PWM1) Period tUCLK/DIV × (PWM0LEN + 1) × NPRESCALE High Side (PWM0) tUCLK/DIV × (PWM0LEN + 1) × NPRESCALE Duration For the high duration, if PWMCOM2 < PWMCOM1, then tUCLK/DIV × (PWM0LEN − PWM0COM2) × NPRESCALE. Otherwise, tUCLK × (PWM0LEN − PWM0COM1) × NPRESCALE. For low duration, tUCLK/DIV × (PWM0COM0 − PWM0COM1) × NPRESCALE. Note that tUCLK/DIV is the PWM clock frequency selected by CLKCON1[2:0], and that NPRESCALE is the prescaler value as determined by PWMCON0[8:6]. Rev. A | Page 169 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Standard Mode In standard mode, each pair is controlled individually by a selection of registers, as shown in Table 267. Table 267. Compare Register Descriptions in Standard Mode (Base Address: 0x40024000) 1 2 3 Name PWM0COM0 PWM0COM1 PWM0COM2 PWM0LEN PWM1COM0 PWM1COM1 PWM1COM2 PWM1LEN PWM2COM0 PWM2COM1 PWM2COM2 PWM2LEN PWM3COM0 PWM3COM1 PWM3COM2 PWM3LEN Description PWM0 output goes high when the PWM timer reaches the count value stored in this register. PWM0 output goes low when the PWM timer reaches the count value stored in this register. PWM1 output goes low when the PWM timer reaches the count value stored in this register. PWM1 output goes high when the PWM timer reaches the count value stored in this register. PWM2 output goes high when the PWM timer reaches the count value stored in this register. PWM2 output goes low when the PWM timer reaches the count value stored in this register. PWM3 output goes low when the PWM timer reaches the count value stored in this register. PWM3 output goes high when the PWM timer reaches the count value stored in this register. PWM4 output goes high when the PWM timer reaches the count value stored in this register. PWM4 output goes low when the PWM timer reaches the count value stored in this register. PWM5 output goes low when the PWM timer reaches the count value stored in this register. PWM5 output goes high when the PWM timer reaches the count value stored in this register. PWM6 output goes high when the PWM timer reaches the count value stored in this register. PWM6 output goes low when the PWM timer reaches the count value stored in this register. PWM7 output goes low when the PWM timer reaches the count value stored in this register. PWM7 output goes high when the PWM timer reaches the count value stored in this register. 1 2 13437-034 Pair 0 Figure 35. PWM Output on PWM0 and PWM1 (PWM0 Channel 2) Rev. A | Page 170 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 H-Bridge Mode In H-bridge mode, the period and duty cycle of the four outputs are controlled using the Pair 0 registers: PWM0COM0, PWM0COM1, PWM0COM2, and PWM0LEN. In addition, the PWMCON0 register, Bit 9, Bit 5, Bit 4, and Bit 2, controls the state of the output as summarized in Table 268. An example of the H-bridge configuration is shown in Figure 36. Note that only PWM0 to PWM3 participate in H-bridge mode; other outputs (PWM4 to PWM7) do not and continue to generate standard mode output. P CHANNEL PWM0 G S PWM2 D +M– PWM3 13437-135 PWM1 N CHANNEL Figure 36. Example H-Bridge Configuration Table 268. PWM Output in H-Bridge Mode ENA, PWMCON0[9] 0 X 1 PWM Control Bit(s)1 POINV, HOFF, PWMCON0[5] PWMCON0[4] X 0 X 1 0 0 DIR, PWMCON0[2] X X 0 PWM0 1 (Disable) 1 (Disable) 0 (Enable) PWM1 1 (Enable) 0 (Disable) 0 (Disable) PWM2 1 (Disable) 1 (Disable) HS PWM3 1 (Enable) 0 (Disable) LS 1 0 0 1 HS LS 0 (Enable) 0 (Disable) 1 1 0 0 LS HS 1 (Disable) 1 (Enable) 1 1 0 1 1 (Disable) 1 (Enable) LS HS 1 2 PWM Outputs2 State of Motor Brake Free run Move controlled by LS on PWM3 Move controlled by LS on PWM1 Move controlled by LS on PWM0 Move controlled by LS on PWM2 X is don’t care. HS is high side, LS is low side, HS is inverse of high side, and LS is inverse of low side, as programmed in the PWM0 registers. PWM INTERRUPT GENERATION PWM Trip Function Interrupt When the PWM trip function is enabled (TRIPEN, PWMCON1[6]) and the PWM trip input signal goes low (falling edge), the PWM peripheral disables itself (PWMCON0[0] = 0). It also generates the PWM trip interrupt. The interrupt is cleared by setting PWMCLRI[4]. When using the PWM trip interrupt, clear the PWM interrupt before exiting the ISR to prevent the generation of multiple interrupts. PWM Output Pairs Interrupts In standard mode, each PWM pair has a dedicated interrupt: IRQPWM0, IRQPWM1, IRQPWM2, or IRQPWM3. When the interrupt generation is enabled (PWMCON0[10]) and the counter value for Pair 0 changes from PWM0LEN to 0, it also generates the IRQPWM0 interrupt. The interrupt is cleared by setting PWMCLRI[0]. When the interrupt generation is enabled (PWMCON0[10]) and the counter value for Pair 1 changes from PWM1LEN to 0, it also generates the IRQPWM1 interrupt. The interrupt is cleared by setting PWMCLRI[1]. When the interrupt generation is enabled (PWMCON0[10]) and the counter value for Pair 2 changes from PWM2LEN to 0, it also generates the IRQPWM2 interrupt. The interrupt is cleared by setting PWMCLRI[2]. When the interrupt generation is enabled (PWMCON0[10]) and the counter value for Pair 3 changes from PWM3LEN to 0, it also generates the IRQPWM3 interrupt. The interrupt is cleared by setting PWMCLRI[3]. In H-bridge mode, Pair 0 and Pair 1 are used in the bridge configuration and generate one interrupt only, IRQPWM0. While Pair 0 and Pair 1 are in H-bridge mode, Pair 2 and Pair 3 can be used in standard mode, and they can generate the IRQPWM2 and IRQPWM3 interrupts. Rev. A | Page 171 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: PWM Table 269. PWM Register Summary Address 0x40024000 0x40024004 0x40024008 0x40024010 0x40024014 0x40024018 0x4002401C 0x40024020 0x40024024 0x40024028 0x4002402C 0x40024030 0x40024034 0x40024038 0x4002403C 0x40024040 0x40024044 0x40024048 0x4002404C Name PWMCON0 PWMCON1 PWMICLR PWM0COM0 PWM0COM1 PWM0COM2 PWM0LEN PWM1COM0 PWM1COM1 PWM1COM2 PWM1LEN PWM2COM0 PWM2COM1 PWM2COM2 PWM2LEN PWM3COM0 PWM3COM1 PWM3COM2 PWM3LEN Description PWM control register ADC conversion start and trip control register Hardware trip configuration register Compare Register 0 for PWM0 and PWM1 Compare Register 1 for PWM0 and PWM1 Compare Register 2 for PWM0 and PWM1 Period value register for PWM0 and PWM1 Compare Register 0 for PWM2 and PWM3 Compare Register 1 for PWM2 and PWM3 Compare Register 2 for PWM2 and PWM3 Period value register for PWM2 and PWM3 Compare Register 0 for PWM4 and PWM5 Compare Register 1 for PWM4 and PWM5 Compare Register 2 for PWM4 and PWM5 Period value register for PWM4 and PWM5 Compare Register 0 for PWM6 and PWM7 Compare Register 1 for PWM6 and PWM7 Compare Register 2 for PWM6 and PWM7 Period value register for PWM6 and PWM7 Reset 0x0012 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 RW RW RW RW1C RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW REGISTER DETAILS: PWM PWM Control Register Address: 0x40024000, Reset: 0x0012, Name: PWMCON0 Table 270. Bit Descriptions for PWMCON0 Bit(s) 15 Bit Name SYNC 14 13 12 11 10 9 PWM7INV PWM5INV PWM3INV PWM1INV PWMIEN ENA [8:6] PWMCMP 5 4 POINV HOFF Description Set to enable PWM synchronization from the SYNC pin of the PWM. 0: ignore transition from the SYNC pin. 1: all PWM counters are reset on the next clock cycle after detection of a falling edge from the SYNC pin. Set to invert PWM7 output. Set to invert PWM5 output. Set to invert PWM3 output. Set to invert PWM1 output. Set to enable interrupts for PWM. When HOFF = 0 and HMODE = 1, this serves as enable for Pair 0 and Pair 1. 0: disable Pair 0 and Pair 1. 1: enable Pair 0 and Pair 1. PWM clock prescaler. Sets HCLK divider. 000: HCLK/2. 001: HCLK/4. 010: HCLK/8. 011: HCLK/16. 100: HCLK/32. 101: HCLK/64. 110: HCLK/128. 111: HCLK/256. Set to invert PWM outputs for Pair 0 and Pair 1 when PWM is in H-bridge mode. Set to turn off the high-side for Pair 0 and Pair 1 when PWM is in H-bridge mode. Rev. A | Page 172 of 190 Reset 0x0 Access RW 0x0 0x0 0x0 0x0 0x0 0x0 RW RW RW RW RW RW 0x0 RW 0x0 0x1 RW RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 3 Bit Name LCOMP 2 DIR 1 0 HMODE PWMEN Description Signal to load a new set of compare register values. In standard mode, this bit is cleared when the new values are loaded in the compare registers for all the channels. In H-bridge mode, this bit is not cleared; however, the user must write a value of 1 to this bit for the compare registers to be loaded. 0: use the values previously store in the compare and length registers. 1: load the internal compare registers with values stored in the PWMxCOMx and PWMxLEN registers. Direction control when PWM is in H-bridge mode. 0: PWM2 and PWM3 act as output signals while PWM0 and PWM1 are held low. 1: PWM0 and PWM1 act as output signals while PWM2 and PWM3 are held low. Set to enable H-bridge mode. Master enable for PWM. 0: disable all PWM outputs. 1: enable all PWM outputs. UG-868 Reset 0x0 Access RW 0x0 RW 0x1 0x0 RW RW Reset 0x00 0x0 0x0 Access Reserved RW Reserved Reset 0x000 0x0 0x0 0x0 0x0 0x0 Access Reserved RW1C RW1C RW1C RW1C RW1C Reset 0x0 Access RW ADC Conversion Start And Trip Control Register Address: 0x40024004, Reset: 0x0000, Name: PWMCON1 Table 271. Bit Descriptions for PWMCON1 Bit(s) [15:7] 6 [5:0] Bit Name RESERVED TRIP_EN RESERVED Description Reserved. Return 0 on reads. Set to enable PWM trip functionality. Reserved. Hardware Trip Configuration Register Address: 0x40024008, Reset: 0x0000, Name: PWMICLR Table 272. Bit Descriptions for PWMICLR Bit(s) [15:5] 4 3 2 1 0 Bit Name RESERVED TRIP PWM3 PWM2 PWM1 PWM0 Description Reserved. Return 0 on reads. Write a 1 to clear latched IRQ PWM trip interrupt. Returns 0 on reads. Write a 1 to clear latched IRQPWM3 interrupt. Returns 0 on reads. Write a 1 to clear latched IRQPWM2 interrupt. Returns 0 on reads. Write a 1 to clear latched IRQPWM1 interrupt. Returns 0 on reads. Write a 1 to clear latched IRQPWM0 interrupt. Returns 0 on reads. Compare Register 0 for PWM0 and PWM1 Address: 0x40024010, Reset: 0x0000, Name: PWM0COM0 Table 273. Bit Descriptions for PWM0COM0 Bit(s) [15:0] Bit Name COM0 Description Compare Register 0 data Compare Register 1 for PWM0 and PWM1 Address: 0x40024014, Reset: 0x0000, Name: PWM0COM1 Table 274. Bit Descriptions for PWM0COM1 Bit(s) [15:0] Bit Name COM1 Description Compare Register 1 data Reset 0x0 Rev. A | Page 173 of 190 Access RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Compare Register 2 for PWM0 and PWM1 Address: 0x40024018, Reset: 0x0000, Name: PWM0COM2 Table 275. Bit Descriptions for PWM0COM2 Bit(s) [15:0] Bit Name COM2 Description Compare Register 2 data Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Period Value Register for PWM0 and PWM1 Address: 0x4002401C, Reset: 0x0000, Name: PWM0LEN Table 276. Bit Descriptions for PWM0LEN Bit(s) [15:0] Bit Name LEN Description Period value Compare Register 0 for PWM2 and PWM3 Address: 0x40024020, Reset: 0x0000, Name: PWM1COM0 Table 277. Bit Descriptions for PWM1COM0 Bit(s) [15:0] Bit Name COM0 Description Compare Register 0 data Compare Register 1 for PWM2 and PWM3 Address: 0x40024024, Reset: 0x0000, Name: PWM1COM1 Table 278. Bit Descriptions for PWM1COM1 Bit(s) [15:0] Bit Name COM1 Description Compare Register 1 data Compare Register 2 for PWM2 and PWM3 Address: 0x40024028, Reset: 0x0000, Name: PWM1COM2 Table 279. Bit Descriptions for PWM1COM2 Bit(s) [15:0] Bit Name COM2 Description Compare Register 2 data Period Value Register for PWM2 and PWM3 Address: 0x4002402C, Reset: 0x0000, Name: PWM1LEN Table 280. Bit Descriptions for PWM1LEN Bit(s) [15:0] Bit Name LEN Description Period value Compare Register 0 for PWM4 and PWM5 Address: 0x40024030, Reset: 0x0000, Name: PWM2COM0 Table 281. Bit Descriptions for PWM2COM0 Bit(s) [15:0] Bit Name COM0 Description Compare Register 0 data Rev. A | Page 174 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Compare Register 1 for PWM4 and PWM5 Address: 0x40024034, Reset: 0x0000, Name: PWM2COM1 Table 282. Bit Descriptions for PWM2COM1 Bit(s) [15:0] Bit Name COM1 Description Compare Register 1 data Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 Access RW Compare Register 2 for PWM4 and PWM5 Address: 0x40024038, Reset: 0x0000, Name: PWM2COM2 Table 283. Bit Descriptions for PWM2COM2 Bit(s) [15:0] Bit Name COM2 Description Compare Register 2 data Period Value Register for PWM4 and PWM5 Address: 0x4002403C, Reset: 0x0000, Name: PWM2LEN Table 284. Bit Descriptions for PWM2LEN Bit(s) [15:0] Bit Name LEN Description Period value Compare Register 0 for PWM6 and PWM7 Address: 0x40024040, Reset: 0x0000, Name: PWM3COM0 Table 285. Bit Descriptions for PWM3COM0 Bit(s) [15:0] Bit Name COM0 Description Compare Register 0 data Compare Register 1 for PWM6 and PWM7 Address: 0x40024044, Reset: 0x0000, Name: PWM3COM1 Table 286. Bit Descriptions for PWM3COM1 Bit(s) [15:0] Bit Name COM1 Description Compare Register 1 data Compare Register 2 for PWM6 and PWM7 Address: 0x40024048, Reset: 0x0000, Name: PWM3COM2 Table 287. Bit Descriptions for PWM3COM2 Bit(s) [15:0] Bit Name COM2 Description Compare Register 2 data Period Value Register for PWM6 and PWM7 Address: 0x4002404C, Reset: 0x0000, Name: PWM3LEN Table 288. Bit Descriptions for PWM3LEN Bit(s) [15:0] Bit Name LEN Description Period value Rev. A | Page 175 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual MANAGEMENT DATA INPUT/OUTPUT (MDIO) MDIO FEATURES The MDIO interface hardware can receive complete MDIO frames without software intervention. The MDIO interface hardware can also transmit complete MDIO frames without software intervention as long as the data to be sent is provided before receiving the turnaround bits (TA) of the read or post read increment address frame. To assist in using and supplying the relevant data, interrupts generate at the end of every complete frame. If the physical address (PHYADR) or device address (DEVADD) received does not match the expected values, the frame is not acted upon. Interrupts can also be generated after every valid PHYADR and DEVADD to permit more sophisticated control within frames. MDIO OVERVIEW This MDIO interface is designed for compliance with CFP management interface architecture (as per Draft CFP MSA Management Interface Specification, Version 2.0 r07, June 30, 2011), as shown in Figure 37. This architecture includes an MDIO hardware interface to handle the serial communications. The transfer of data between this CFP MDIO interface and the MDIO defined memory blocks is done via the software. 0x0000 CFP MODULE (MMD) 0x7FFF MDIO BUS 2 HOST MDIO INTERFACE (STA) INTERNAL BUS REGISTERS FOR IEEE 802.3 NONVOLATILE MEMORY (NVM) 0x8000 CFP REGISTER SET CFP MDIO INTERFACE 3 OR 5 DIGITAL DIAGNOSTIC MONITORING (DDM) 0xFFFF PORT ADD BUS 13437-134 CPU/CONTROL LOGIC Figure 37. CFP Management Interface Architecture MDIO OPERATION MDIO Frame Structure The MDIO interface uses the communication data frame structure defined in the IEEE 802.3, Clause 45. The frame structure is shown in Figure 38. Each frame can be either an address frame or a data frame. The total bit length of each frame is 64, consisting of 32 bits of preamble, and the frame command body. The command body consists of six portions, as illustrated in Figure 38. More information about the various frame types is provided in Table 289. All values are transmitted MSB first. 32-BIT PREAMBLE ST OP PHYADR DEVADD TA 16-BIT ADDRESS/DATA 00 ACCESS TYPE ADDRESS WRITE READ POST READ INCREMENT ADDRESS DEVADD 00000 00001 00010 00011 00100 00101 DEVICE TYPE RESERVED PMA/PMD WIS PCS PHY XS DTE XS NOTES 1. ST = START BITS (2 BITS) 2. OP = OPERATION CODE (2 BITS) 3. PHYADR = PHYSICAL PORT ADDRESS (5 BITS) 4. DEVADD = MDIO DEVICE ADDRESS (OR CALLED DEVICE TYPE, 5 BITS) 5. TA = TURNAROUND BITS (2 BITS) 6. 16-BIT ADDRESS/DATA IS THE PAYLOAD Figure 38. MDIO Frame Structure Rev. A | Page 176 of 190 ACCESS TYPE ADDRESS WRITE READ READ INCREMENT CONTENT REG ADDRESS WRITE DATA READ DATA READ DATA 13437-035 OP 00 01 11 10 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Table 289. Frame Details for Different Frame Types1 Frame Write Address Write Data Read Data Post Read Increment Address Frame 1 Idle Z Z Z Z PRE 1…1 1…1 1…1 1…1 ST 00 00 00 00 OP 00 01 11 10 Management Frame Fields PHYADR DEVADD TA aaaaa aaaaa 10 aaaaa aaaaa 10 aaaaa aaaaa z0 aaaaa aaaaa z0 Address/Data aaaaaaaaaaaaaaaa dddddddddddddddd dddddddddddddddd dddddddddddddddd Idle Z Z Z Z During the idle condition, the MDIO clock (MDC) and MDIO are not actively driven. During the second bit of TA and during the 16-bit data of the read and post read increment address add frames, MDIO is driven by the MDIO manageable device (slave). At all other times, the STA bits drive the ADC and the MDIO. Idle Condition (Idle) The idle condition for the MDIO is a high impedance state. Preamble (PRE) At the beginning of each transaction, the station management entity (host) sends a sequence of at least 32 contiguous bits sent one bit at a time to the MDIO, with 32 corresponding clock cycles on the MDIO clock (MDC), to establish the start of a frame. Start of Frame (ST) After PRE, the ST (consisting of two zero bits) indicates the start of the frame information. Operation Code (OP) The OP specifies the action to take, as described in Table 290. Table 290. Operation Code OP 00 01 11 10 Descriptions Set the address for a subsequent write or read frame. Write to the previously set address. Read from the previously set address. Read from the previously set address, and then increment the address. User code must increment the address in the MDADR register. Physical Address (PHYADR) The physical address is five bits, allowing 32 unique addresses. PHYADR is set either by five pins or by the software. Device Address (DEVAD) DEVAD is five bits and selects the device type. In the CFP standard, only MDIO Device Address 1 is supported. Turnaround (TA) The TA time changes STA to be driven by the MDIO manageable device (slave), as per Figure 38. Address/Data The address/data field is 16 bits. Typical Usage Sequence Most of the MDIO interface is implemented in the hardware, requiring minimal software effort. The following is the typical usage sequence: 1. 2. 3. 4. 5. Enable the MDIO onto the physical pins by writing 0x0555 to the GP3CON register. Set the frame parameters using the MDPHY, MDCON, and MDPIN registers. Set the interrupts with the MDIEN register and the required system interrupt settings. At this stage, the address and write frames can be received in the MDRXD and MDADR registers, respectively. Data must be placed in the MDTXD register in advance of the read or post read increment address frame so that the data can be automatically inserted for the frame. No software intervention is required during any of the transmissions; however, frame progress can be monitored with the MDFRM register during or upon completion of each frame. Do not use the MDSTA register to check frame progress because this MMR is automatically cleared, and bits can be lost if read at an inappropriate time. To monitor frame progress, select the appropriate time to read the MDSTA register based on interrupts or by polling the MDIO bit in INTSETP0 in the interrupt system. Read the MDSTA register only once per frame. MDIO must have the highest interrupt priority of all peripherals; otherwise, MDIO events will be likely lost. Rev. A | Page 177 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual MDIO Interrupt Power Up Register Write Sequence To avoid false MDIO interrupts on start up, the order of register writes is important. The following is a code example showing how to correctly configure the MDIO interrupt on start up. pADI_MDIO->MDCON = 0x0006; pADI_MDIO->MDPHY = 0x0700; sta = pADI_MDIO->MDSTA; //read the MDSTA register to clear any interrupts pADI_MDIO->MDIEN = 0x000F; NVIC_ClearPendingIRQ(MDIO_IRQn); //clear any pending interrupts in the Cortex REGISTER SUMMARY: MDIO INTERFACE (MDIO) Names and short descriptions of bits refer to the active state represented by a high (1) level, unless explicitly enumerated. Table 291. MDIO Register Summary Address 0x40005C00 0x40005C04 0x40005C08 0x40005C0C 0x40005C10 0x40005C14 0x40005C18 0x40005C1C 0x40005C20 Name MDCON MDFRM MDRXD MDADR MDTXD MDPHY MDSTA MDIEN MDPIN Description MDIO block control MDIO received frame control information MDIO received data MDIO received address MDIO data for transmission MDIO PHYADDR software values and selection and DEVADD MDIO progress signaling through frame MDIO interrupt enables MDIO read PHYADDR pins Reset 0x0000 0x0000 0x000X 0x000X 0x0000 0x0400 0x0000 0x0000 0x0000 Access RW R R R RW RW RW RW RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 W REGISTER DETAILS: MDIO MDIO Block Control Register Address: 0x40005C00, Reset: 0x0000, Name: MDCON Control for MDIO block. Table 292. Bit Descriptions for MDCON Bits [15:3] 2 Bit Name RESERVED MD_DRV 1 MD_PHY 0 MD_RST Description Reserved. 0: MDIO drive open-drain. 1: MDIO drive push-pull. 0: MDIO PHY uses 5 bits. 1: MDIO PHY uses 3 bits. Unused PHY bits are ignored. Write 1 to reset MDIO block. Hardware immediately clears MD_RST again. Rev. A | Page 178 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 MDIO Received Frame Control Information Register Address: 0x40005C04, Reset: 0x0000, Name: MDFRM Contains control information of last frame received. Table 293. Bit Descriptions for MDFRM Bits [15:12] [11:7] [6:2] [1:0] Bit Name RESERVED MD_DEV MD_PHY MD_OP Description Reserved Received DEVADD Received PHYADR Received OP 00: address frame 01: write frame 10: post read increment address frame 11: read frame Reset 0x0 0x0 0x0 0x0 Access R R R R Reset 0xx Access R MDIO Received Data Register Address: 0x40005C08, Reset: 0x000X, Name: MDRXD Data received from last write frame. Table 294. Bit Descriptions for MDRXD Bits [15:0] Bit Name MD_RXD Description Received data MDIO Received Address Register Address: 0x40005C0C, Reset: 0x000X, Name: MDADR Data received from last address frame. Table 295. Bit Descriptions for MDADR Bits [15:0] Bit Name MD_ADR Description Received address Reset 0xx Access R MDIO Data for Transmission Register Address: 0x40005C10, Reset: 0x0000, Name: MDTXD Data to be transmitted by next data frame. Table 296. Bit Descriptions for MDTXD Bits [15:0] Bit Name MD_TXD Description Data that is transmitted by the next read or post read increment address frame. Before a read frame, the master sends an address frame to specify which data is to be read. After this address frame, the user software must place this requested data into MD_TXD before it is required by the read frame. The time available is at least 45 MDIO clock cycles being a minimum of the read frame preamble and up to 3 cycles before TA, which is equivalent to 900 CPU clock cycles. Reset 0x0000 Access RW Reset 0x0 0x1 0x0 Access R RW RW 0x0 RW MDIO PHYADDR Software Values and Selection and DEVADD Register Address: 0x40005C14, Reset: 0x0400, Name: MDPHY Sets expected values for control part of frame. Table 297. Bit Descriptions for MDPHY Bits 15 [14:10] [9:5] Bit Name RESERVED MD_DEVADD MD_PHYSEL [4:0] MD_PHYSW Description Reserved. Expected DEVADD. Normally 01. Selects expected PHYADR bits. For each of the 5 bits: 0: sets expected PHYADR.x = PRTADRx pin. 1: sets expected PHYADR.x = MD_PHYSW.x. Software provided PHYADR bits. Chosen according to corresponding MD_PHYSEL bits. Rev. A | Page 179 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual MDIO Progress Signaling Through Frame Register Address: 0x40005C18, Reset: 0x0000, Name: MDSTA Indicates progress through frame. Table 298. Bit Descriptions for MDSTA Bits [15:8] 7 6 5 4 3 2 Bit Name RESERVED MD_PHYN MD_PHYM MD_DEVN MD_DEVM MD_RDF MD_INCF 1 0 MD_ADRF MD_WRF Description Reserved. Set at end of PHYADR if PHYADR nonmatching. Cleared by reading the MDSTA register. Set at end of PHYADR if PHYADR matching. Cleared by reading the MDSTA register. Set at end of DEVADD if DEVADD nonmatching. Cleared by reading the MDSTA register. Set at end of DEVADD if DEVADD matching. Cleared by reading the MDSTA register. Set at end of read frame if DEVADD and PHYADR are matching. Cleared by reading the MDSTA register. Set at end of post read increment address frame if DEVADD and PHYADR are matching. Cleared by reading MDSTA. Set at end of address frame if DEVADD and PHYADR are matching. Cleared by reading the MDSTA register. Set at end of write frame if DEVADD and PHYADR are matching. Cleared by reading the MDSTA register. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R RC RC RC RC RC RC 0x0 0x0 RC RC MDIO Interrupt Enables Register Address: 0x40005C1C, Reset: 0x0000, Name: MDIEN Enables interrupts on specified events. Table 299. Bit Descriptions for MDIEN Bits [15:8] 7 6 5 4 3 2 1 0 Bit Name RESERVED MD_PHYNI MD_PHYMI MD_DEVNI MD_DEVMI MD_RDFI MD_INCFI MD_ADRFI MD_WRFI Description Reserved. If set, interrupt is requested when MD_PHYN becomes active. If set, interrupt is requested when MD_PHYM becomes active. If set, interrupt is requested when MD_DEVN becomes active. If set, interrupt is requested when MD_DEVM becomes active. If set, interrupt is requested when MD_RDF becomes active. If set, interrupt is requested when MD_INCF becomes active. If set, interrupt is requested when MD_ADRF becomes active. If set, interrupt is requested when MD_WRF becomes active. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R RW RW RW RW RW RW RW RW Reset 0x0 0x0 Access R R MDIO Read PHYADDR Pins Register Address: 0x40005C20, Reset: 0x0000, Name: MDPIN Reads the MDIO address pins. Table 300. Bit Descriptions for MDPIN Bits [15:5] [4:0] Bit Name RESERVED MD_PIN Description Reserved Reads PRTADRx pins Rev. A | Page 180 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DOWNLOADER The ADuCM320i and the ADuCM322i allow users to download code to the microcontroller via an I2C interface, while the ADuCM322 allows users to download code to the microcontroller via the MDIO interface. I2C DOWNLOADER (ADUCM320i/ADUCM322i ONLY) The ADuCM320i and ADuCM322i contain firmware that is inaccessible to the user but runs after every reset to set up the device and to allow programming of the device via the I2C interface on the P0.4 and P0.5 pins. The mechanism to enter the downloader and the protocol used are described in the AN-806 Application Note, Flash Programming via I2C—Protocol Type 5. MDIO DOWNLOADER (ADUCM322 ONLY) For MDIO applications, the system memory is separated into two flash blocks, as shown in Figure 39. FLASH BLOCK 0 ACTIVE (FEECON1[3] = 0) FLASH BLOCK 1 ACTIVE (FEECON1[3] = 1) 0x3FFFF 0x1FFFF RESERVED1 RESERVED1 0x3FFE8 0x3FFFF FLASH 1 ACTIVE NVR DATA 8kB (IMAGE A) 0x3E000 FLASH 1 NOT USED KEY2' (K2B1) 0x20000 NOT USED KEY1' (K1B1) 0x1FFE8 0x1FFFF 0x3DFE8 0x3DFE0 0x0 INACTIVE PROGRAM 120kB (IMAGE B) INACTIVE NVR DATA 8kB (IMAGE A) KEY2 (K2B1) 0x1DFE8 NOT USED KEY1 (K1B1) 0x1DFE0 ACTIVE PROGRAM 120kB (IMAGE B) 0x20000 0x0 0x1FFFF 0x3FFFF RESERVED1 RESERVED1 0x1FFE8 0x1FFFF FLASH 0 INACTIVE NVR DATA 8kB (IMAGE B) NOT USED KEY1 (K1B0) 0x0 0x3FFE8 0x3FFFF 0x1E000 FLASH 0 NOT USED KEY2 (K2B0) ACTIVE NVR DATA 8kB (IMAGE B) 0x3E000 NOT USED 0x1DFE8 KEY2' (K2B0) 0x3DFE8 0x1DFE0 NOT USED KEY1' (K1B0) 0x3DFE0 0x20000 ACTIVE PROGRAM 120kB (IMAGE B) ACTIVE PROGRAM 120kB (IMAGE A) 0x0 0x20000 THE FLASH CONTROLLER SECTION FOR MORE INFORMATION ABOUT RESERVED LOCATIONS. 13437-136 1SEE 0x1E000 NOT USED NOTES 1. ADuCM322 ONLY. Figure 39. Memory Maps for MDIO Block Switching (ADuCM322 Only) Rev. A | Page 181 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Flash Block Partitioning In the MDIO dual program image configuration, Program Image A in Flash 0 and the NVR Data Block A in Flash 1 should be used together or, alternatively, Program Image B in Flash 1 and the NVR Data Block B in Flash 0 should be used together. Because the data and code are in different flash blocks, the code can continue executing in the active program image while flash operations are performed on the associated nonvolatile RAM (NVR) data flash block. Only one combination can be used at a time, which is known as the active combination. The other combination can be updated with new code if required, and by means of the block switching described, code can be made to execute from the new code. In unswitched mode, Flash Block 0 is mapped from 0 to 0x1FFFF, and Flash Block 1 is mapped from 0x20000 to 0x3FFFF. In switched mode, Flash Block 1 is mapped from 0 to 0x1FFFF, and Flash Block 0 is mapped from 0x20000 to 0x3FFFF. Build code to run in the 0 to 0x1FFFF address range and only run code in this range. A mechanism is provided in the kernel to run from the appropriate flash block after any reset, which is described in the subsequent subsections of the Management Data Input/Output (MDIO) section. For additional information, see Figure 40, Table 301, and Table 302. Program Image The choice of which blocks are used is determined by the kernel and based on keys placed at the top of the two 120 kB program image blocks. The six modes of operation follow: • • • • • • Debug mode Downloader mode (no valid code) Normal running from Program Image A (Flash 0) Trial run from Program Image A (Flash 0) Normal running from Program Image B (Flash 1) Trial run from Program Image B (Flash 1) Each of these modes can only be entered via a reset. Every reset causes the kernel to run, and the kernel chooses the appropriate mode according to keys in the program images. Each program image contains two keys. For the active program image, Key1 at Address 0x1DFE0 has a numeric value that indicates the update number. The higher the Key1 value, the more recent the update. Key2 at Address 0x1DFE8 manages the trial runs. A value of 0xFFFFFFFF (erased) indicates a new download. When a trial run has passed, this must be indicated by changing the value to 0. Key1’ of the other program image is at 0x3DFE0, and Key2’ of the other program image is at 0x3DFE8. The user program space CRCs can be stored at 0x1DFFC for Flash 0 and at 0x3DFFC for Flash 1. The CRC is not required as part of the block selection mechanism but to increased robustness it is recommended to included it. The user code can check this CRC periodically. Note that the keys are placed just below the 120 kB boundary, which is assumed to be the top of the program space. There is no technical reason why some code cannot be placed above this boundary or why some data cannot be placed below this boundary. Debug Mode If after a reset the kernel determines that the download pin (P2.3) is high, the kernel enters user code regardless of the keys. This mode is intended for debugging only Choosing the Active Block After any reset, the kernel chooses the active program image. Figure 40 is the flowchart for choosing the active program image. Initially, the kernel assumes that the program image with the larger Key1 is made active. If the associated Key2 is not 0, this code has not passed the trial run and should not yet be used. Instead, the kernel investigates using the other program image. If the Key2’ of the other program image is 0, that program image is chosen. Based on these decisions, the kernel then sets the active program image and exits to the user code. If neither program image has a valid Key2, the kernel enters its own download mode. Rev. A | Page 182 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Trial Run Mode After the user code is entered, the code checks whether a trial run or a normal run should be performed. A trial run is indicated if the active Key1 is less than the Key1’. In a trial run, the old code first checks that the new program image is functioning correctly. The trial run starts in the old program image and performs initial checks, such as CRCs and other checks that the user deems necessary, on the new program image. The trial run can then continue by switching to the new image using Bit 3 (SWAP) of the FEECON1 register. It is recommended that the code that performs the switching be at a fixed location in Flash Page0 and be the same in all revisions. The code following the switching point should include sufficient identical code so that the CPU pipeline plus the flash look ahead buffers contain the expected code after switching. The user must also clear the memory cache to prevent old code from executing after the switch. The trial run should copy all necessary data from the old NVR to the new NVR. After the new flash blocks are correct, the user code must write 0 to Key2’ of the new flash block to mark the block as good. The user code can then initiate normal operation. Alternatively, a software reset can be issued, and the device then enters normal mode in the new program image. A reset may occur during a trial run, for instance, due to power loss or during a watchdog event due to program hanging or a deliberate software reset. In this case, a trial run restarts in the old code, and the trial run code then decides how to proceed. Normal Mode The user code must check whether a trial run or a normal run should be performed. A normal run is indicated if the active Key1 is larger than the other Key1. During normal operation, the MDIO master can send download information to the active user code so that new code is written to the other program image. Such a download must also write the new Key1’ with a value of one more than the active Key1. The new Key2’ must be left erased as 0xFFs. After the download, the device must be reset to allow a trial run to occur. Typical Sequence A typical sequence is shown in Table 301, and a definition of the keys is in Table 302. On a new device, the initial code can be downloaded via serial wire (SW) JTAG if P2.3 is held high during a reset; otherwise, the kernel enters its own downloader because there is no valid key. At the end of the download to Flash 0, Key1 is set to 1, and Key2 is set to 0. After a reset, normal code is run from Flash 0 because its Key1 is greater than Key1’ (0xFFs = −1) and its Key2 is 0. User code can receive MDIO frames instructing it to download code to Flash 1, which results in the new Key2’ being erased and 2 being written to the new Key1’. After a reset, the kernel activates Flash 0 for a trial run on the new code because Key2’ of Flash 1 is 0xFFs. If the trial run passes, the user code sets Key2 to 0 and issues a software reset. After a reset, the kernel selects Flash 1 because its Key1 is still larger than Key1’ and the active Key2 is 0. User code can receive MDIO frames instructing it to download code, including copying the NVR data block to Flash 0, which results in Key2 being erased and 3 being written to Key1. Changeover back to Flash 0 is then similar to the change to Flash 1. Table 301. Example Block Switching Sequence No. of Software Download Not applicable 1 Key2 of Flash 0 0xFFFFFFFF 0 Key1 of Flash 0 0xFFFFFFFF 1 Key2 of Flash 1 0xFFFFFFFF 0xFFFFFFFF Key1 of Flash 1 0xFFFFFFFF 0xFFFFFFFF 1 0 1 0xFFFFFFFF 0xFFFFFFFF 2 0 1 0xFFFFFFFF 2 2 0 1 0xFFFFFFFF 2 2 2 0 0 1 1 0 0 2 2 3 0xFFFFFFFF 3 0 2 3 0xFFFFFFFF 3 0 2 3 3 0 0 3 3 0 0 2 2 Rev. A | Page 183 of 190 Status Initial startup Kernel has downloaded Code1 to Flash 0 Code1 normal execution in Flash 0 Code1 has downloaded Code2 to Flash 1 Code1 starts a trial run on Code2 in Flash 1 Code2 trial run complete Code 2 normal execution in Flash 1 Code2 has downloaded Code3 to Flash 0 Code2 starts trial run on Code3 in Flash 0 Code3 trial mode complete Code3 normal execution in Flash 0 Reset Required? Yes No Yes No Yes No Yes No Yes No UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual No. of Software Download 4 Key2 of Flash 0 0 Key1 of Flash 0 3 Key2 of Flash 1 0xFFFFFFFF Key1 of Flash 1 4 4 0 3 0xFFFFFFFF 4 4 4 0 0 3 3 0 0 4 4 … … … Table 302. Definition of Keys Key1, 2 K1B0 K1B1 K2B0 K2B1 Key1 Key2 Key1’ Key2’ 0xFFs 1 2 Description Key1 in Flash Block 0 at 0x1DFE0 Key1 in Flash Block 1 at 0x3DFE0 Key2 in Flash Block 0 at 0x1DFE8 Key2 in Flash Block 1 at 0x3DFE8 Key used to identify latest revision in active flash block at 0x1DFE0 Key used for trial runs in active flash block at 0x1DFE8 Key1 for the other flash block at 0x3DFE0 Key2 for the other flash block at 0x3DFE8 0xFFFFFFFFFFFFFFFF Key1, Key2, Key1’, and Key2’ refer to the keys as seen by the user. K1B0, K1B1, K2B0, and K2B1 refer to the keys as seen by the kernel before block switching occurs. Rev. A | Page 184 of 190 Status Code3 has downloaded Code4 to Flash 1 Code3 starts a trial run on Code4 in Flash 1 Code 4 trial mode complete Code4 normal execution in Flash 1 … Reset Required? Yes No Yes No ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 RESET SWITCH TO FLASH 1 HARDWARE KERNEL CODE Y N P2.3 = HIGH N K1B0 < K1B1 Y Y K2B0 = 0 N Y K2B1 = 0 N K2B1 = 0 N N RUN DOWNLOADER Y K2B0 = 0 Y SWITCH TO FLASH 1 CHANGE TO USER CODE USER CODE Y N KEY1’ > KEY1 TRIAL RUN Y KEY2 = 0 N TRIAL OK N Y ERROR NORMAL RUN WRITE KEY2’ = 0 11176-137 FLASH OTHER BLOCK (KEY2’ = 0xFFs, K1’ = K1+1) NOTES 1. ADuCM322 ONLY. Figure 40. Flowchart for MDIO Memory Block Switching (ADuCM322 Only) Rev. A | Page 185 of 190 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual HARDWARE DESIGN CONSIDERATIONS TYPICAL SYSTEM CONFIGURATION Figure 41 shows a typical ADuCM320i configuration, Figure 42 shows a typical ADuCM322 configuration, and Figure 43 shows a typical ADuCM320i configuration. Figure 41, Figure 42, and Figure 43 illustrate some of the hardware considerations. Place the four 0.47 µF capacitors on DVDD_1V8, DVDD_2V5, AVDD_REG1, and AVDD_REG2 as close as possible to the pins. VDD1 must either have a separate power supply or be filtered from the other digital supply using an inductor bead and a resistor. The same applies to the AVDD supply. Decoupling capacitors are required between each power and associated ground, as indicated in the ADuCM320i, the ADuCM322, the ADuCM322i data sheets. Place these capacitors as close as possible to the pins and in such a way that the current paths do not interfere with one another. All GNDs must be connected together in as close to a star connection as the layout allows. Rev. A | Page 186 of 190 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DVDD UG-868 VDD1 0.47µF 0.47µF B1 D11 J1 K6 L2 K2 L1 D10 C1 E11 K1 IOVDD1 IOVDD2 IOVDD3 VDD1 DVDD_1V8 DVDD_2V5 DGND1 DGND2 IOGND1 IOGND2 IOGND3 VDD1 RESET 10kΩ B2 RESET J2 XTALI H2 XTALO 12pF DGND VDD1 10kΩ PVDD PVDD2 A8 PVDD3 B4 CDAMP0 B8 CDAMP1 B5 CDAMP2 B7 CDAMP3 P1.1/SOUT/PLACLK1/PLAI[5] B10 AVDD_REG1 AGND1 AGND2 AGND3 AGND4 SWDIO E10 AVDD_REG0 PGND PGND SWCLK E9 ADC_REFN A6 B6 P1.0/SIN/ECLKIN/PLAI[4] B9 ADuCM320i ADC_REFP 10nF PVDD1 A4 IREF 10nF A9 VREF_1V2 10nF PVDD0 AVDD4 10nF P2.3/BM C3 A3 AVDD3 12pF L6 G11 F11 A11 K11 L11 F9 F10 J5 K7 L7 H11 AVDD RESET 0.47µF 0.47µF AGND RESET GND SWDIO DGND TX SWCLK RX NC DVDD VDD1 1.6Ω 10µF VIN 0.1µF 10µF 0.1µF 10kΩ 10µF 0.1µF AGND1 AVDD 1.6Ω VOUT SENSE EN 10µF 0.1µF DGND PG AGND AGND GND ADP1741ACPZ +2.5V DGND DGND1 DVDD ADP7102ARDZ-3.3 VIN 0.1µF PVDD VIN VOUT 30kΩ 10µF EN 10kΩ EP GND PGND 10µF ADJ SS PGND PGND 10µF Figure 41. Typical System Configuration for the ADuCM320i Rev. A | Page 187 of 190 13437-138 INTERFACE BOARD CONNECTOR 0.47µF 3.16kΩ 4.7µF UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual VDD1 DVDD 0.47µF 0.47µF D11 J1 K6 L2 K2 L1 D10 C1 E11 K1 IOVDD2 IOVDD3 VDD1 DVDD_1V8 DVDD_2V5 DGND1 DGND2 IOGND1 IOGND2 IOGND3 10kΩ B1 IOVDD1 VDD1 RESET B2 RESET 12pF DGND J2 XTALI H2 XTALO A3 RESERVED A9 RESERVED A4 RESERVED A8 RESERVED NC B4 RESERVED NC B8 RESERVED NC B5 RESERVED NC B7 RESERVED VDD1 12pF P1.1/SOUT/PLACLK1/PLA1[5] B10 K11 L11 AGND4 A11 AGND3 F11 AGND2 ADC_REFN G11 AGND1 ADC_REFP L6 AVDD_REG1 IREF SWDIO E10 VREF_1V2 DGND SWCLK E9 AVDD4 DGND B6 P1.0/SIN/ECLKIN/PLAI[4] B9 AVDD3 A6 P2.3/BM C3 ADuCM322 F10 J5 K7 L7 H11 AVDD_REG0 AVDD_REG1 10kΩ F9 AVDD 3.3kΩ 4.7µF 0.47µF 0.47µF AGND RESET RESET GND SWDIO TX DGND SWCLK RX NC VDD1 DVDD 1.6Ω 10µF VIN ADP7102ARDZ-3.3 VIN 0.1µF 10µF EN DGND DGND1 DVDD 1.6Ω VOUT SENSE 10kΩ 0.1µF 10µF 0.1µF 10µF DGND Figure 42. Typical System Configuration for the ADuCM322 Rev. A | Page 188 of 190 AGND1 AVDD 0.1µF PG GND 0.1µF AGND AGND 13437-042 INTERFACE BOARD CONNECTOR 0.47µF ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 VDD1 DVDD 0.47µF 0.47µF D11 J1 K6 L2 K2 L1 D10 C1 E11 K1 IOVDD2 IOVDD3 VDD1 DVDD_1V8 DVDD_2V5 DGND1 DGND2 IOGND1 IOGND2 IOGND3 10kΩ B1 IOVDD1 VDD1 RESET B2 RESET 12pF DGND J2 XTALI H2 XTALO A3 RESERVED A9 RESERVED A4 RESERVED A8 RESERVED NC B4 RESERVED NC B8 RESERVED NC B5 RESERVED NC B7 RESERVED VDD1 12pF P1.1/SOUT/PLACLK1/PLA1[5] B10 K11 L11 AGND4 A11 AGND3 F11 AGND2 ADC_REFN G11 AGND1 ADC_REFP L6 AVDD_REG1 IREF SWDIO E10 VREF_1V2 DGND SWCLK E9 AVDD4 DGND B6 P1.0/SIN/ECLKIN/PLAI[4] B9 AVDD3 A6 P2.3/BM C3 ADuCM322i F10 J5 K7 L7 H11 AVDD_REG0 AVDD_REG1 10kΩ F9 AVDD 3.3kΩ 4.7µF 0.47µF 0.47µF AGND RESET RESET GND SWDIO TX DGND SWCLK RX NC VDD1 DVDD 1.6Ω 10µF VIN ADP7102ARDZ-3.3 VIN 0.1µF 10µF EN DGND DGND1 DVDD 1.6Ω VOUT SENSE 10kΩ 0.1µF 10µF 0.1µF 10µF DGND Figure 43. Typical System Configuration for the ADuCM322i Rev. A | Page 189 of 190 AGND1 AVDD 0.1µF PG GND 0.1µF AGND AGND 13437-043 INTERFACE BOARD CONNECTOR 0.47µF UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual SERIAL WIRE DEBUG INTERFACE VCC 1 2 VCC (OPTIONAL) NYU 3 4 GND NYU 5 6 GND SWDIO 7 8 GND SWCLK 9 10 GND NYU 11 12 GND SWO 13 14 GND RESET 15 16 GND NYU 17 18 GND NYU 19 20 GND 13437-038 The serial wire debug (SWD) interface provides a debug port for pin limited packages. The SWD replaces the 5-pin JTAG port with a clock (SWCLK) and a single bidirectional data pin (SWDIO), providing all the normal JTAG debug and test functionality. SWDIO and SWCLK are overlaid on the TMS and TCK pins on the ARM 20-pin JTAG interface. Figure 44. SWD 20-Pin Connector Pinout Table 303. SWD Connections Signal SWDIO SWO SWCLK VCC GND RESET Connect To Data input/output pin. Use a 100 kΩ pull-up resistor to VCC from SWDIO. No connect. Clock pin. Use a 100 kΩ pull-up resistor to VCC from SWCLK. Positive supply voltage; power supply for JTAG interface drivers. Digital ground. No connect. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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