Dual Pseudo Differential 16-Bit, 1 MSPS PulSAR ADC 12.0 mW in QSOP AD7902 Data Sheet FEATURES GENERAL DESCRIPTION 16-bit resolution with no missing codes Throughput: 1 MSPS Low power dissipation 7.0 mW at 1 MSPS (VDD1 and VDD2 only) 12.0 mW at 1 MSPS (total) 140 µW at 10 kSPS INL: ±1.0 LSB typical, ±2.5 LSB maximum SINAD: 91 dB at 1 kHz THD: −105 dB at 1 kHz Pseudo differential analog input range 0 V to VREF with VREF between 2.4 V to 5.1 V Allows use of any input range Easy to drive with the ADA4841-1/ADA4841-2 No pipeline delay Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial port interface (SPI) QSPI/MICROWIRE/DSP compatible 20-lead QSOP package Wide operating temperature range: −40°C to +125°C The AD7902 is a dual 16-bit, successive approximation, analogto-digital converter (ADC) that operates from a single power supply, VDDx, per ADC. It contains two low power, high speed, 16-bit sampling ADCs and a versatile serial port interface (SPI). On the CNVx rising edge, the AD7902 samples an analog input, IN+, in the range of 0 V to VREF with respect to a ground sense, IN−. The externally applied reference voltage of the REFx pins (VREF) can be set independently from the supply voltage pins, VDDx. The power of the device scales linearly with throughput. Using the SDIx inputs, the SPI-compatible serial interface can also daisy-chain multiple ADCs on a single 3-wire bus and provide an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIOx supplies. The AD7902 is available in a 20-lead QSOP package with operation specified from −40°C to +125°C. Table 1. MSOP 14-/16-/18-Bit PulSAR® ADCs APPLICATIONS Battery-powered equipment Communications Automated test equipment (ATE) Data acquisition Medical instrumentation Redundant measurement Simultaneous sampling Bits 18 100 kSPS 250 kSPS AD76911 400 kSPS to 500 kSPS AD76901 16 AD7680 AD7683 AD7684 AD7940 AD76851 AD76871 AD7694 AD79421 AD76861 AD76881 AD76931 AD79461 14 1 1000 kSPS AD79821 AD79801 AD7903 AD7902 ADC Driver ADA4941-1 ADA4841-1 ADA4841-2 ADA4941-1 ADA4841-1 ADA4841-2 Pin-for-pin compatible. FUNCTIONAL BLOCK DIAGRAM REF = 2.5V TO 5V 2.5V VDD1 VDD2 0V TO VREF IN1+ ADC1 IN1– 0V TO VREF VIO1/VIO2 SDI1 SDI1/SDI2 SCK1 SCK1/SCK2 CNV1 CNV1/CNV2 SDO1 SDO1 VIO2 IN2+ SDI2 ADC2 SCK2 CNV2 IN2– GND VIO1 SDO2 AD7902 3-WIRE OR 4-WIRE INTERFACE (SPI, CS, AND CHAIN MODES) SDO2 11756-001 REF1 REF2 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7902 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ................................................... 15 Applications ....................................................................................... 1 Analog Inputs ............................................................................. 15 General Description ......................................................................... 1 Driver Amplifier Choice ........................................................... 16 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 16 Revision History ............................................................................... 2 Power Supply............................................................................... 17 Specifications..................................................................................... 3 Digital Interface .......................................................................... 17 Timing Specifications .................................................................. 5 CS Mode ...................................................................................... 18 Absolute Maximum Ratings............................................................ 6 Chain Mode ................................................................................ 22 ESD Caution .................................................................................. 6 Applications Information .............................................................. 24 Pin Configuration and Function Descriptions ............................. 7 Simultaneous Sampling ............................................................. 24 Typical Performance Characteristics ............................................. 8 Functional Saftey Considerations ............................................ 25 Terminology .................................................................................... 13 Layout............................................................................................... 26 Theory of Operation ...................................................................... 14 Evaluating Performance of the AD7902.................................. 26 Circuit Information .................................................................... 14 Outline Dimensions ....................................................................... 27 Converter Operation .................................................................. 14 Ordering Guide .......................................................................... 27 REVISION HISTORY 8/15—Rev. A to Rev. B Changed ADA4841-x to ADA4841-1/ADA4841-2 .. Throughout Change to Absolute Input Voltage Parameter, Table 2 ................ 3 Changes to Voltage Reference Input Section .............................. 16 Updated Outline Dimensions ....................................................... 27 7/14—Rev. 0 to Rev. A Changed Standby Current Unit from nA to μA ........................... 4 Changes to Power Supply Section ................................................ 17 2/14—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet AD7902 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = −40°C to +125°C, unless otherwise noted.1 Table 2. Parameter RESOLUTION ANALOG INPUT2 Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25°C ACCURACY No Missing Codes Differential Nonlinearity Error3 Integral Nonlinearity Error3 Transition Noise3 Gain Error4 Gain Error Temperature Drift Gain Error Match4 Zero Error4 Zero Temperature Drift Zero Error Match4 Power Supply Sensitivity3 THROUGHPUT Conversion Rate Transient Response AC ACCURACY5 Dynamic Range Oversampled Dynamic Range Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion Ratio (SINAD) Channel-to-Channel Isolation Test Conditions/Comments Min 16 INx+ − INx− INx+ INx− fIN = 450 kHz Acquisition phase 0 −0.1 −0.1 16 −1.0 VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V TMIN to TMAX −2.5 −0.08 TMIN to TMAX TMIN to TMAX −1.25 TMIN to TMAX VDD = 2.5 V ± 5% VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V above 85°C, up to 125°C Full-scale step VREF = 5 V VREF = 2.5 V fOUT = 10 kSPS fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V fIN = 10 kHz 1 Typ 0 67 200 ±0.5 ±0.8 ±1.0 ±0.9 0.75 1.2 ±0.012 0.3 0.016 ±0.25 0.19 0.2 ±0.1 0 89.5 84.5 89 84 92 87 111 91.5 86.5 −105 −105 91 86 −112 Max Unit Bits VREF VREF + 0.1 +0.1 V V V dB nA +1.0 +2.5 +0.08 0.08 +1.25 1.0 Bits LSB LSB LSB LSB LSB LSB % FS ppm/°C % FS mV ppm/°C mV LSB 1 MSPS 290 ns dB dB dB dB dB dB dB dB dB dB The voltages for the VDDx, VIOx, and REFx pins are indicated by VDD, VIO, and VREF, respectively. For information regarding input impedance, see the Analog Inputs section. For the 5 V input range, 1 LSB = 76.3 µV. For the 2.5 V input range, 1 LSB = 38.2 µV. 4 See the Terminology section. These specifications include full temperature range variation, but they do not include the error contribution from the external reference. 5 All specifications in decibels (dB) are referred to a full-scale input FSR. Although these parameters are referred to full scale, they are tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 2 3 Rev. B | Page 3 of 28 AD7902 Data Sheet VDD = 2.5 V, VIO = 2.3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted.1 Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay Aperture Delay Match DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDDx VIOx VIOx Range IVDDx IVIOx Standby Current2, 3 Power Dissipation VDDx Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE4 Specified Performance Test Conditions/Comments Min Typ 2.4 Max Unit 5.1 1 MSPS, VREF = 5 V, each ADC 330 V µA VDD = 2.5 V VDD = 2.5 V 10 2.0 2.0 MHz ns ns VIO > 3 V VIO ≤ 3 V VIO > 3 V VIO ≤ 3 V −0.3 −0.3 0.7 × VIO 0.9 × VIO −1 −1 +0.3 × VIO +0.1 × VVIO VIO + 0.3 VIO + 0.3 +1 +1 V V V V µA µA 0 Bits Samples Straight binary No delay, conversion results available immediately after conversion is complete ISINK = 500 µA ISOURCE = −500 µA Specified performance Full range Each ADC Each ADC VDD and VIO = 2.5 V, 25°C 10 kSPS throughput 1 MSPS throughput 1 MSPS throughput TMIN to TMAX 0.4 V V 2.625 5.5 5.5 1.6 0.45 V V V mA mA µA µW mW mW mW mW nJ/sample VIO − 0.3 2.375 2.3 1.8 2.5 1.4 0.2 0.35 140 12.0 7.0 3.3 1.7 7.0 −40 1 In this data sheet, the voltages for the VDDx, VIOx, and REFx pins are indicated by VDD, VIO, and VREF, respectively. With all digital inputs forced to VIOx or to ground, as required. 3 During the acquisition phase. 4 Contact Analog Devices, Inc., for the extended temperature range. 2 Rev. B | Page 4 of 28 16 +125 °C Data Sheet AD7902 TIMING SPECIFICATIONS −40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions. See Figure 39, Figure 41, Figure 43, Figure 45, Figure 47, Figure 49, and Figure 51 for timing diagrams. Table 4. Parameter Conversion Time (CNVx Rising Edge to Data Available) Acquisition Time Time Between Conversions VIOx Above 2.3 V CNVx Pulse Width (CS Mode) SCKx Period (CS Mode) VIOx Above 4.5 V VIOx Above 3 V VIOx Above 2.7 V VIOx Above 2.3 V SCKx Period (Chain mode) VIOx Above 4.5 V VIOx Above 3 V VIOx Above 2.7 V VIOx Above 2.3 V SCKx Low Time SCKx High Time SCKx Falling Edge to Data Remains Valid SCKx Falling Edge to Data Valid Delay VIOx Above 4.5 V VIOx Above 3 V VIOx Above 2.7 V VIOx Above 2.3 V CNVx or SDIx Low to SDOx, D15 (MSB) Valid (CS Mode) VIOx Above 3 V VIOx Above 2.3 V CNVx or SDIx High or Last SCKx Falling Edge to SDOx High Impedance (CS Mode) SDIx Valid Setup Time from CNVx Rising Edge(CS Mode) SDIx Valid Hold Time from CNVx Rising Edge (CS Mode) SCKx Valid Setup Time from CNVx Rising Edge (Chain Mode) SCKx Valid Hold Time from CNVx Rising Edge (Chain Mode) SDIx Valid Setup Time from SCKx Falling Edge (Chain Mode) SDIx Valid Hold Time from SCKx Falling Edge (Chain Mode) SDIx High to SDOx High (Chain Mode with Busy Indicator) tCNVH tSCK Unit ns ns 1000 10 ns ns 10.5 12 13 15 ns ns ns ns 11.5 13 14 16 4.5 4.5 3 ns ns ns ns ns ns ns tSCKL tSCKH tHSDO tDSDO 9.5 11 12 14 ns ns ns ns 10 15 20 ns ns ns ns ns ns ns ns ns ns tEN tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 5 2 5 5 2 3 15 X% VIOx1 tDELAY VIH2 VIL2 1.4V 11756-002 CL 20pF IOH Max 710 tSCK tDELAY 500µA Typ Y% VIOx1 IOL TO SDOx Min 500 290 VIH2 VIL2 1 FOR VIOx ≤ 3.0V, X = 90 AND Y = 10; FOR VIOx > 3.0V, X = 70 AND Y = 30. VIH AND MAXIMUM VIL USED. SEE SPECIFICATIONS FOR DIGITAL INPUTS PARAMETER IN TABLE 3. 2 MINIMUM Figure 3. Voltage Levels for Timing Figure 2. Load Circuit for Digital Interface Timing Rev. B | Page 5 of 28 11756-003 500µA Symbol tCONV tACQ tCYC AD7902 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs INx+, INx− to GND1 Supply Voltage REFx, VIOx to GND VDDx to GND VDDx to VIOx Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±10 mA −0.3 V to +6.0 V −0.3 V to +3.0 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 255°C 260°C See the Analog Inputs section for an explanation of INx+ and INx−. Rev. B | Page 6 of 28 Data Sheet AD7902 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF1 1 20 VIO1 VDD1 2 19 SDI1 IN1+ 3 GND 5 18 SCK1 AD7902 TOP VIEW (Not to Scale) 17 SDO1 16 CNV1 REF2 6 15 VIO2 VDD2 7 14 SDI2 IN2+ 8 13 SCK2 IN2– 9 12 SDO2 GND 10 11 CNV2 11756-004 IN1– 4 Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 6 Mnemonic REF1, REF2 Type1 AI 2, 7 VDD1, VDD2 IN1+, IN2+ IN1−, IN2− GND CNV2, CNV1 P 3, 8 4, 9 5, 10 11, 16 12, 17 AI AI P DI DO 13, 18 14, 19 SDO2, SDO1 SCK2, SCK1 SDI2, SDI1 15, 20 VIO2, VIO1 P 1 DI DI Description Reference Input Voltage. The REFx range is 2.4 V to 5.1 V. These pins are referred to the GND pin, and decouple each pin closely to the GND pin with a 10 µF capacitor. Power Supplies. Pseudo Differential Positive Analog Inputs. Pseudo Differential Negative Analog Inputs. Power Supply Ground. Conversion Inputs. These inputs have multiple functions. On the leading edge, they initiate conversions and select the interface mode of the device: chain mode or active low chip select mode (CS mode). In CS mode, the SDOx pins are enabled when the CNVx pins are low. In chain mode, the data must be read when the CNVx pins are high. Serial Data Outputs. The conversion result is output on these pins. The conversion result is synchronized to SCKx. Serial Data Clock Inputs. When the device is selected, the conversion results are shifted out by these clocks. Serial Data Inputs. These inputs provide multiple functions. They select the interface mode of the ADC, as follows: CS mode is selected if the SDIx pins are high during the CNVx rising edge. In this mode, either SDIx or CNVx can enable the serial output signals when low. If SDIx or CNVx is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (2.5 V or 3 .3 V). AI is analog input, DI is digital input, DO is digital output, and P is power. Rev. B | Page 7 of 28 AD7902 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, TA = 25°C, fSAMPLE = 1 MSPS, fIN = 10 kHz, unless otherwise noted. 0.6 0.4 0.4 0.2 0.2 DNL (LSB) 0.6 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 16384 32768 49152 65536 CODE –1.0 11756-405 –1.0 0 POSITIVE DNL: +0.38 LSB NEGATIVE DNL: –0.42 LSB 0.8 0 1.0 0.6 0.4 0.4 0.2 0.2 DNL (LSB) 0.6 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 49152 65536 CODE –1.0 0 32768 49152 65536 Figure 9. Differential Nonlinearity vs. Code, VREF = 2.5 V 0 0 fSAMPLE = 1MSPS fIN = 10kHz –20 fSAMPLE = 1MSPS fIN = 10kHz –20 SNR = 91.37dB THD = –103.7dB SFDR = 104.5dB SINAD = 91.15dB –40 SNR = 85.85dB THD = –103.0dB SFDR = 105.2dB SINAD = 85.76dB –40 –60 –80 –100 –80 –100 –120 –120 –140 –140 –160 –160 0 100 200 300 FREQUENCY (kHz) 400 500 Figure 7. FFT Plot, VREF = 5 V –180 0 100 200 300 FREQUENCY (kHz) Figure 10. FFT Plot, VREF = 2.5 V Rev. B | Page 8 of 28 400 500 11756-410 SNR (dB) –60 11756-407 SNR (dB) 16384 CODE Figure 6. Integral Nonlinearity vs. Code, VREF = 2.5 V –180 65536 POSITIVE DNL: +0.60 LSB NEGATIVE DNL: –0.58 LSB 0.8 11756-406 INL (LSB) POSITIVE INL: +0.60 LSB 0.8 NEGATIVE INL: –0.60 LSB 32768 49152 Figure 8. Differential Nonlinearity vs. Code, VREF = 5 V 1.0 16384 32768 CODE Figure 5. Integral Nonlinearity vs. Code, VREF = 5 V 0 16384 11756-408 0.8 INL (LSB) 1.0 POSITIVE INL: +0.35 LSB NEGATIVE INL: –0.90 LSB 11756-409 1.0 Data Sheet AD7902 50000 50000 46115 45000 45000 35000 30000 25000 20000 15000 11317 12406 10000 5000 40000 35000 30000 25000 20000 15000 12174 10000 3524 5000 249 210 FA6C FA6D FA6E FA6F FA70 FA71 FA72 FA73 FA74 FA75 FA76 CODES IN HEX 0 11756-411 0 2991 521 33 135 38 4 11756-414 40000 NUMBER OF OCCURRENCES NUMBER OF OCCURRENCES 41352 FABA FABB FABC FABD FABE FABF FAC0 FAC1 FAC2 FAC3 FAC4 FAC5 FAC6 CODES IN HEX Figure 11. Histogram of a DC Input at the Code Center, VREF = 5 V Figure 14. Histogram of a DC Input at the Code Center, VREF = 2.5 V 94 50000 93 40000 35000 92 31890 28056 SNR (dB) 30000 25000 20000 91 90 15000 10000 89 3393 5000 19 0 F87C F87D F87E F87F F880 F881 F882 F883 F884 F885 CODES IN HEX 88 –10 –9 –4 –3 –2 –1 –0.1 –95 114 15.5 –100 96 112 15.0 THD 14.0 88 13.5 THD (dB) 90 ENOB (Bits) –105 14.5 92 110 108 –110 106 SFDR (dB) 94 –115 86 104 SFDR 13.0 84 –120 102 12.5 82 80 12.0 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 REFERENCE VOLTAGE (V) 11756-413 SNR, SINAD (dB) –5 –125 2.25 Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage 2.75 3.25 3.75 4.25 4.75 REFERENCE VOLTAGE (V) Figure 16. THD and SFDR vs. Reference Voltage Rev. B | Page 9 of 28 100 5.25 11756-416 98 –6 Figure 15. SNR vs. Input Level 16.0 SNR SINAD ENOB –7 INPUT LEVEL (dB) Figure 12. Histogram of a DC Input at the Code Transition, VREF = 5 V 100 –8 11756-415 2177 11756-412 NUMBER OF OCCURRENCES 45000 AD7902 Data Sheet 91 –90 90 –92 89 –94 88 –96 THD (dB) 86 85 84 –98 –100 –102 –104 83 82 –106 81 –108 10k 100k 1M INPUT FREQUENCY (Hz) –110 1k 11756-417 80 1k 10k 100k 1M INPUT FREQUENCY (Hz) Figure 17. SINAD vs. Input Frequency 11756-420 SINAD (dB) 87 Figure 20. THD vs. Input Frequency 92.5 –100 92.0 –105 THD (dB) SNR (dB) 91.5 91.0 –110 90.5 –35 –15 5 25 45 85 65 105 125 TEMPERATURE (°C) –115 –55 11756-418 89.5 –55 –35 –15 5 45 25 85 65 105 125 TEMPERATURE (°C) Figure 18. SNR vs. Temperature 11756-421 90.0 Figure 21. THD vs. Temperature 1.6 1.4 TA = 25°C IVDD 1.4 1.2 1.2 CURRENT (mA) 0.8 0.6 IREF 0.4 1.0 0.8 IVDD 0.6 0.4 IVIO 0 2.375 0.2 2.425 2.475 2.525 SUPPLY VOLTAGE (V) 2.575 2.625 0 10 IVIO 100 1000 SAMPLE RATE (kSPS) Figure 22. Operating Currents for Each ADC vs. Throughput Figure 19. Operating Currents for Each ADC vs. Supply Voltage Rev. B | Page 10 of 28 11756-422 0.2 11756-050 CURRENT (mA) 1.0 Data Sheet AD7902 8 1.4 IVDD 7 1.2 6 CURRENT (µA) CURRENT (mA) 1.0 0.8 0.6 IREF 0.4 5 4 3 IVDD + IVIO 2 IVIO 0.2 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 0 –55 Figure 23. Operating Currents for Each ADC vs. Temperature 0.3 0.3 ZERO ERROR MATCH (mV) 0.4 0.1 0 –0.1 –0.2 85 105 125 0.2 0.1 0 –0.1 –0.2 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) –0.4 –55 11756-424 –35 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 24. Zero Error vs. Temperature 11756-427 –0.3 –0.3 Figure 27. Zero Error Match vs. Temperature 0.05 0.010 GAIN ERROR MATCH (% FS) 0.03 0.01 –0.01 –0.03 –35 –15 5 25 45 65 85 TEMPERATURE (°C) 105 125 11756-425 GAIN ERROR (% FS) 5 25 45 65 TEMPERATURE (°C) Figure 25. Gain Error vs. Temperature 0.005 0 –0.005 –0.010 –55 –35 –15 5 25 45 65 85 TEMPERATURE (°C) Figure 28. Gain Error Match vs. Temperature Rev. B | Page 11 of 28 105 125 11756-428 ZERO ERROR (mV) 0.2 –0.05 –55 –15 Figure 26. Power-Down Current for Each ADC vs. Temperature 0.4 –0.4 –55 –35 11756-054 –35 11756-053 0 –55 1 AD7902 Data Sheet –100 –100 –104 –106 –108 –110 –112 –114 –116 –118 –120 –55 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) 125 Figure 29. Channel-to-Channel Isolation vs. Temperature –102 –104 –106 –108 –110 –112 –114 –116 –118 –120 1k 10k 100k 1M INPUT FREQUENCY (Hz) Figure 30. Channel-to-Channel Isolation vs. Input Frequency Rev. B | Page 12 of 28 11756-430 CHANNEL-TO-CHANNEL ISOLATION (dB) –102 11756-429 CHANNEL-TO-CHANNEL ISOLATION (dB) fIN = 20kHz Data Sheet AD7902 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 32). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error The first transition should occur at a level ½ LSB above analog ground (38.1 µV for the 0 V to 5 V range). The zero error is the deviation of the actual transition from that point. Zero Error Match It is the difference in offsets, expressed in millivolts between the channels of a multichannel converter. It is computed with the following equation: Zero Matching = VZEROMAX − VZEROMIN where: VZEROMAX is the most positive zero error. VZEROMIN is the most negative zero error. Zero error matching is usually expressed in millivolts with the full-scale input range stated in the product data sheet. Gain Error The last transition (from 111 … 10 to 111 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Gain Error Match It is the ratio of the maximum full scale to the minimum full scale of a multichannel ADC. It is expressed as a percentage of full scale using the following equation: FSRMAX − FSRMIN Gain Matching = 2N × 100% where: FSRMAX is the most positive gain error of the ADC. FSRMIN is the most negative gain error. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: ENOB = (SINADdB − 1.76)/6.02 ENOB is expressed in bits. Noise Free Code Resolution Noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as follows: Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise) Noise free code resolution is expressed in bits. Effective Resolution Effective resolution is calculated as follows: Effective Resolution = log2(2N/RMS Input Noise) Effective resolution is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels (dB). Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels (dB). It is measured with a signal at −60 dBFS to include all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels (dB). Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels (dB). Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNVx input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. B | Page 13 of 28 AD7902 Data Sheet THEORY OF OPERATION INx+ MSB LSB 32,768C 16,384C 4C 2C C SWITCHES CONTROL SWx+ C BUSY REFx COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C LSB MSB SWx– 11756-011 CNVx INx– Figure 31. ADC Simplified Schematic The AD7902 is a fast, low power, precise, dual 16-bit ADC using a successive approximation architecture. The AD7902 is capable of simultaneously converting 1,000,000 samples per second (1 MSPS) and powers down between conversions. When operating at 10 kSPS, for example, it typically consumes 70 µW per ADC, making it ideal for battery-powered applications. The AD7902 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multichannel multiplexed applications. binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the device returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7902 has an on-board conversion clock, the serial clock, SCKx, is not required for the conversion process. Transfer Functions The ideal transfer characteristic for the AD7902 is shown in Figure 32 and Table 7. The AD7902 can be interfaced to any 1.8 V to 5 V digital logic family. It is available in a 20-lead QSOP that allows for flexible configurations. The device is pin-for-pin compatible with the differential, 16-bit AD7903. ADC CODE (STRAIGHT BINARY) 111 ... 111 CONVERTER OPERATION The AD7902 is a dual successive approximation ADC based on a charge redistribution DAC. Figure 31 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase of each ADC, terminals of the array tied to the input of the comparator are connected to GND via the switches, SWx+ and SWx−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− inputs. When the acquisition phase is complete and the CNVx input goes high, a conversion phase is initiated. When the conversion phase begins, SWx+ and SWx− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the INx+ and INx− inputs, captured at the end of the acquisition phase, is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REFx, the comparator input varies by 111 ... 110 111 ... 101 000 ... 010 000 ... 001 000 ... 000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT 11756-012 CIRCUIT INFORMATION Figure 32. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 1 Analog Input, VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 µV 0V Digital Output Code (Hex) FFFF1 8001 8000 7FFF 0001 00002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). This is also the code for an underranged analog input (VIN+ − VIN− below VGND). Rev. B | Page 14 of 28 2 Data Sheet AD7902 TYPICAL CONNECTION DIAGRAM 90 85 ANALOG INPUTS 80 CMRR (dB) Figure 35 shows an example of the recommended connection diagram for the AD7902 when multiple supplies are available. Figure 33 shows an equivalent circuit of the input structure of the AD7902. The two diodes, D1 and D2, provide ESD protection for the analog inputs, INx+ and INx−. The analog input signal must not exceed the reference input voltage (VREF) by more than 0.3 V. If the analog input signal exceeds this level, the diodes become forward-biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4841-1 in Figure 35) are different from those of the VREF, the analog input signal may eventually exceed the supply rails by more than 0.3 V. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the device. 70 60 1k D2 Figure 33. Equivalent Analog Input Circuit The analog input structure allows for the sampling of the differential signal between INx+ and INx−. By using these differential inputs, signals common to both inputs, and within the allowable common-mode input range, are rejected. V+ REF1 When the source impedance of the driving circuit is low, the AD7902 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. 2.5V CREF 10µF2 100nF V+ 1.8V TO 5V 100nF 20Ω 0V TO VREF 10M During the sampling phase, where the switches are closed, the input impedance is limited to CPIN. RIN and CIN make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. 11756-114 CPIN 1M During the acquisition phase, the impedance of the analog inputs (INx+ or INx−) can be modeled as a parallel combination of the CPIN capacitor and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. INx+ OR INx– GND 100k FREQUENCY (Hz) Figure 34. Analog Input CMRR vs. Frequency CIN RIN 10k ADA4841-1 3 REFx 2.7nF VDDx VIOx SDIx INx+ V– 4 SCKx AD7902 ADCx INx– GND SDOx 3-WIRE INTERFACE CNVx 1 SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). SEE RECOMMENDED LAYOUT IN FIGURE 53. 3 SEE THE DRIVER AMPLIFIER CHOICE SECTION. 4 OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION. REF Figure 35. Typical Application Diagram with Multiple Supplies Rev. B | Page 15 of 28 11756-013 2C 11756-040 65 REFx D1 75 AD7902 Data Sheet DRIVER AMPLIFIER CHOICE Table 8. Recommended Driver Amplifiers Although the AD7902 is easy to drive, the driver amplifier must meet the following requirements: Amplifier ADA4841-1/ ADA4841-2 AD8021 AD8022 OP184 AD8655 AD8605, AD8615 The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7902. The noise from the driver is filtered by the one-pole, low-pass filter of the AD7902 analog input circuit, made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7902 is 56 μV rms, the SNR degradation due to the amplifier is SNRLOSS 47.3 20 log π 2 47.3 f 3dB ( Ne N ) 2 2 Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single supply, low noise 5 V single supply, low power VOLTAGE REFERENCE INPUT The AD7902 voltage reference input, REF, has a dynamic input impedance and must therefore be driven by a low impedance source with efficient decoupling between the REFx and GND pins, as explained in the Layout section. where: f−3dB is the input bandwidth, in megahertz, of the AD7902 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, gain = 1 in buffer configuration; see Figure 35). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. Typical Application Very low noise, small, and low power For ac applications, the driver must have a THD performance that is commensurate with the AD7902. For multichannel, multiplexed applications, the driver amplifier and the AD7902 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). In the amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 16-bit level. Be sure to verify the settling time prior to driver selection. When REF is driven by a very low impedance source (for example, a reference buffer using the AD8031 or the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR430, ADR431, ADR433, ADR434, or ADR435 reference. If desired, a reference decoupling capacitor with values as small as 2.2 μF can be used with a minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REFx and GND pins. Rev. B | Page 16 of 28 Data Sheet AD7902 POWER SUPPLY DIGITAL INTERFACE The AD7902 uses two power supply pins per ADC: a core supply (VDDx) and a digital input/output interface supply (VIOx). VIOx allows direct interface with any logic between 1.8 V and 5.5 V. To reduce the number of supplies needed, VIOx and VDDx can be tied together. The AD7902 is independent of power supply sequencing between VIOx and VDDx. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 36. Although the AD7902 has a reduced number of pins, it offers flexibility in its serial interface modes. 95 90 PSRR (dB) 85 When in CS mode, the AD7902 is compatible with SPI, QSPI, digital hosts, and DSPs. In this mode, the AD7902 can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNVx, SCKx, and SDOx signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDIx, CNVx, SCKx, and SDOx signals allows CNVx, which initiates the conversions, to be independent of the readback timing (SDIx). This is useful in low jitter sampling or simultaneous sampling applications. When in chain mode, the AD7902 provides a daisy-chain feature using the SDIx input for cascading multiple ADCs on a single data line similar to a shift register. With the AD7902 housing two ADCs in one package, chain mode can be utilized to acquire data from both ADCs while using only one set of 4-wire user interface signals. 80 75 70 The mode in which the device operates depends on the SDIx level when the CNVx rising edge occurs. CS mode is selected if SDIx is high, and chain mode is selected if SDIx is low. The SDIx hold time is such that when SDIx and CNVx are connected together, chain mode is always selected. 60 1k 10k 100k FREQUENCY (Hz) 1M 11756-139 65 Figure 36. PSRR vs. Frequency The AD7902 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. This makes the device ideal for low sampling rates (of even a few hertz) and low battery-powered applications. 10 In either mode, the AD7902 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. • 1 • IVDD IREF 0.1 IVIO 0.01 0.001 10000 100000 SAMPLING RATE (SPS) 1000000 11756-137 OPERATING CURRENTS (mA) The busy indicator feature is enabled as follows: Figure 37. Operating Currents per ADC vs. Sampling Rate Rev. B | Page 17 of 28 In CS mode when CNVx or SDIx is low when the ADC conversion ends (see Figure 41 and Figure 45). In chain mode when SCKx is high during the CNVx rising edge (see Figure 49). AD7902 Data Sheet CS MODE However, to avoid generation of the busy signal indicator, CNVx must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time. When the conversion is complete, the AD7902 enters the acquisition phase and powers down. When CNVx goes low, the MSB is automatically output onto SDOx. The remaining data bits are clocked by subsequent SCKx falling edges. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the falling edge of SCKx allows a faster reading rate, provided that it has an acceptable hold time. After the 16th SCKx falling edge or when CNVx goes high (whichever occurs first), SDOx returns to high impedance. CS Mode, 3-Wire Interface Without Busy Indicator CS mode, using a 3-wire interface without a busy indicator, is usually used when a single AD7902 is connected to a SPIcompatible digital host. The connection diagram is shown in Figure 38, and the corresponding timing diagram is shown in Figure 39. With SDIx tied to VIOx, a rising edge on CNVx initiates a conversion, selects CS mode, and forces SDOx to high impedance. When a conversion is initiated, it continues until completion, regardless of the state of CNVx. This can be useful, for instance, to bring CNVx low to select other SPI devices, such as analog multiplexers. CONVERT DIGITAL HOST CNVx VIOx SDIx AD7902 DATA IN SDOx 11756-116 SCKx CLK Figure 38. CS Mode, 3-Wire Interface Without a Busy Indicator Connection Diagram (SDIx High) SDIx = 1 tCYC tCNVH CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 2 3 14 tHSDO 16 tSCKH tEN SDOx 15 tDSDO D15 D14 D13 tDIS D1 D0 Figure 39. CS Mode, 3-Wire Interface Without a Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 18 of 28 11756-216 1 SCKx Data Sheet AD7902 When the conversion is complete, SDOx goes from high impedance to low impedance. With a pull-up on the SDOx line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7902 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCKx falling edges. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the optional 17th SCKx falling edge or when CNVx goes high (whichever occurs first), SDOx returns to high impedance. CS Mode, 3-Wire Interface with Busy Indicator CS mode, using a 3-wire interface with a busy indicator, is usually used when a single AD7902 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 40, and the corresponding timing is shown in Figure 41. With SDIx tied to VIOx, a rising edge on CNVx initiates a conversion, selects CS mode, and forces SDOx to high impedance. SDOx is maintained in high impedance until the completion of the conversion, regardless of the state of CNVx. Prior to the minimum conversion time, CNVx can be used to select other SPI devices, such as analog multiplexers, but CNVx must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. If multiple ADCs are selected at the same time, the SDOx output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation. CONVERT VIOx CNVx AD7902 DATA IN SDOx IRQ SCKx 11756-118 SDIx DIGITAL HOST 47kΩ VIOx CLK Figure 40. CS Mode, 3-Wire Interface with a Busy Indicator Connection Diagram (SDIx High) SDIx = 1 tCYC tCNVH CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 15 tHSDO 16 17 tSCKH tDIS tDSDO SDOx D15 D14 D1 D0 Figure 41. CS Mode, 3-Wire Interface with a Busy Indicator Serial Interface Timing (SDIx High) Rev. B | Page 19 of 28 11756-218 SCKx AD7902 Data Sheet minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7902 enters the acquisition phase and powers down. Each ADC result can be read by bringing its respective SDIx input low, which consequently outputs the MSB onto SDOx. The remaining data bits are then clocked by subsequent SCKx falling edges. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCKx falling edge or when SDIx goes high (whichever occurs first), SDOx returns to high impedance, and another ADC result can be read. CS Mode, 4-Wire Interface Without Busy Indicator CS mode, using a 4-wire interface without a busy indicator, is usually used when both ADCs within the AD7902 are connected to a SPI-compatible digital host. See Figure 42 for an AD7902 connection diagram example. The corresponding timing diagram is shown in Figure 43. With SDIx high, a rising edge on CNVx initiates a conversion, selects CS mode, and forces SDOx to high impedance. In this mode, CNVx must be held high during the conversion phase and the subsequent data readback. (If SDIx and CNVx are low, SDOx is driven low.) Prior to the minimum conversion time, SDIx can be used to select other SPI devices, such as analog multiplexers, but SDIx must be returned high before the CS2 CS1 CONVERT CNV1 AD7902 SDO1 SDI2 AD7902 ADC1 ADC2 SCK1 SCK2 DIGITAL HOST SDO2 11756-120 SDI1 CNV2 DATA IN CLK Figure 42. CS Mode, 4-Wire Interface Without a Busy Indicator Connection Diagram tCYC CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI1 (CS1) tHSDICNV SDI2 (CS2) tSCK tSCKL 1 2 3 14 tHSDO 16 17 18 D11 D10 D215 D214 30 31 32 D21 D20 tSCKH tEN SDOx 15 tDIS tDSDO D115 D114 D113 Figure 43. CS Mode, 4-Wire Interface Without a Busy Indicator Serial Interface Timing Rev. B | Page 20 of 28 11756-220 SCKx Data Sheet AD7902 SDIx can be used to select other SPI devices, such as analog multiplexers, but SDIx must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDOx goes from high impedance to low impedance. With a pull-up on the SDOx line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7902 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCKx falling edges. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the optional 17th SCKx falling edge or SDIx going high (whichever occurs first), SDOx returns to high impedance. CS Mode, 4-Wire Interface with Busy Indicator CS mode, 4-wire with busy indicator, is usually used when an AD7902 is connected to a SPI-compatible digital host with an interrupt input. This CS mode is also used when it is desirable to keep CNVx, which is used to sample the analog input, independent of the signal that is used to select the data reading. This independence is particularly important in applications where low jitter on CNVx is desired. The connection diagram is shown in Figure 44, and the corresponding timing is given in Figure 45. With SDIx high, a rising edge on CNVx initiates a conversion, selects CS mode, and forces SDOx to high impedance. In this mode, CNVx must be held high during the conversion phase and the subsequent data readback. (If SDIx and CNVx are low, SDOx is driven low.) Prior to the minimum conversion time, CS1 CONVERT VIOx CNVx AD7902 DATA IN SDOx IRQ SCKx 11756-122 SDIx DIGITAL HOST 47kΩ CLK Figure 44. CS Mode, 4-Wire Interface with a Busy Indicator Connection Diagram tCYC CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDIx tSCK tHSDICNV tSCKL 2 3 15 tHSDO 16 17 tSCKH tDIS tDSDO tEN SDOx D15 D14 D1 Figure 45. CS Mode, 4-Wire Interface with a Busy Indicator Serial Interface Timing Rev. B | Page 21 of 28 D0 11756-222 1 SCKx AD7902 Data Sheet CHAIN MODE held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDOx and the AD7902 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCKx falling edges. For each ADC, SDIx feeds the input of the internal shift register and is clocked by the SCKx falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to read back the N ADCs. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate and, consequently, more AD7902 devices in the chain, provided that the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. Chain Mode Without Busy Indicator Chain mode without a busy indicator can be used to daisychain both ADCs within an AD7902 on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. See Figure 46 for a connection diagram example using both ADCs in an AD7902. The corresponding timing is shown in Figure 47. When SDIx and CNVx are low, SDOx is driven low. With SCKx low, a rising edge on CNVx initiates a conversion, selects chain mode, and disables the busy indicator. In this mode, CNVx is CONVERT CNV2 AD7902 ADC1 SDO1 SDI2 SCK1 DIGITAL HOST ADC2 SDO2 DATA IN SCK2 11756-124 SDI1 CNV1 AD7902 CLK Figure 46. Chain Mode Without a Busy Indicator Connection Diagram SDI1 = 0 tCYC CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSDICNV SCKx 1 2 3 15 16 17 18 30 31 32 D 11 D 10 tSCKH tHSDISCK tEN SDO1 = SDI2 14 tSSDISCK tHSDICNV D115 D114 D113 D11 D10 D 21 D20 tHSDO SDO2 D215 D214 D213 D115 D114 Figure 47. Chain Mode Without a Busy Indicator Serial Interface Timing Rev. B | Page 22 of 28 11756-224 tDSDO Data Sheet AD7902 Chain Mode with Busy Indicator conversions, the SDOx pin of the ADC closest to the digital host (see the ADC labeled ADCx in the AD7902 B box in Figure 48) is driven high. This transition on SDOx can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7902 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCKx falling edges. For each ADC, SDIx feeds the input of the internal shift register and is clocked by the SCKx falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to read back the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate and, consequently, more ADCs in the chain, provided that the digital host has an acceptable hold time. Chain mode with a busy indicator can also be used to daisychain both ADCs within an AD7902 on a 3-wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with limited interfacing capacity. Data readback is analogous to clocking a shift register. See Figure 48 for a connection diagram example using three AD7902 ADCs. The corresponding timing is shown in Figure 49. When SDIx and CNVx are low, SDOx is driven low. With SCKx high, a rising edge on CNVx initiates a conversion, selects chain mode, and enables the busy indicator feature. In this mode, CNVx is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their CONVERT SDI1A CNVx CNVx CNVx AD7902 AD7902 AD7902 ADC1 SDO1A SDI2A ADC2 SDO2A SDIxB SCKx SCKx DIGITAL HOST ADCx SDOxB DATA IN SCKx IRQ CLK AD7902 A AD7902 B 11756-126 NOTES 1. DASHED LINE DENOTED ADCs ARE WITHIN A GIVEN PACKAGE. 2. SDI1A AND SDO1A REFER TO THE SDI1 AND SDO1 PINS IN ADC1 IN THE FIRST AD7902 OF THE CHAIN (AD7902 A). SDI2A AND SDO2A REFER TO THE SDI2 AND SDO2 PINS IN ADC2 OF AD7902 A. LIKEWISE, SDIxB AND SDOxB REFER TO THE SDIx AND SDOx PINS IN BOTH ADC1 AND ADC2 OF THE SECOND AD7902 IN THE CHAIN (AD7902 B). Figure 48. Chain Mode with a Busy Indicator Connection Diagram tCYC CNVx = SDI1A tCONV tACQ ACQUISITION CONVERSION ACQUISITION tSCK tSCKH SCKx 1 2 4 3 15 16 tSSDISCK tHSCKCNV 17 18 19 31 32 33 34 35 tSCKL DA115 SDO1A = SDI2A DA114 DA113 DA11 tDSDOSDI tDSDO tDSDOSDI DA215 DA214 DA213 DA21 DA20 DA115 DA114 DA11 DA10 DBx15 DBx14 DBx13 DBx1 DBx0 DA215 DA214 DA21 DA20 tDSDOSDI SDOxB 49 DA10 tHSDO SDO2A = SDIxB 48 tDSDOSDI tHSDISCK tEN 47 tDSDODSI Figure 49. Chain Mode with a Busy Indicator Serial Interface Timing Rev. B | Page 23 of 28 DA115 DA114 DA11 DA10 11756-226 tSSCKCNV AD7902 Data Sheet APPLICATIONS INFORMATION SIMULTANEOUS SAMPLING Alternatively, for applications where simultaneous sampling is required but pins on the digital host are limited, the two user interfaces on the AD7902 can be connected in one of the daisychain configurations shown in Figure 46 and Figure 48. This daisy chaining allows the user to implement simultaneous sampling functionality while requiring only one digital host input pin. This scenario requires 31 or 32 SCKx falling edges (depending on the status of the busy indicator) to acquire data from the ADC. By having two unique user interfaces, the AD7902 provides maximum flexibility with respect to how conversion results are accessed from the device. The AD7902 provides an option for the two user interfaces to share the convert start (CNVx) signal from the digital host, creating a 2-channel, simultaneous sampling device. In applications such as control applications, where latency between the sampling instant and the availability of results in the digital host is critical, it is recommended that the AD7902 be configured as shown in Figure 50. This configuration allows simultaneous data read, in addition to simultaneous sampling. However, this configuration also requires an additional data input pin on the digital host. This scenario allows for the fastest throughput because it requires only 15 or 16 SCKx falling edges (depending on the status of the busy indicator) to acquire data from the ADC. Figure 50 shows an example of a simultaneous sampling system using two data inputs for the digital host. The corresponding timing diagram in Figure 51 shows a CS mode, 3-wire simultaneous sampling serial interface without busy indicator. However, any of the 3-wire or 4-wire serial interface timing options can be used. CONVERT CNV1 SDI1 ADC1 CNV2 VIO2 AD7902 SDO1 DIGITAL HOST AD7902 SDI2 ADC2 SDO2 DATA IN 2 DATA IN 1 SCK2 SCK1 11756-324 VIO1 CLK Figure 50. Potential Simultaneous Sampling Connection Diagram SDIx = 1 tCYC tCNVH CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 2 3 14 tHSDO 15 16 tSCKH tEN tDSDO tDIS SDO1 D15 D14 D13 D1 D0 SDO2 D15 D14 D13 D1 D0 Figure 51. Potential Simultaneous Sampling Serial Interface Timing Rev. B | Page 24 of 28 11756-316 1 SCKx Data Sheet AD7902 FUNCTIONAL SAFTEY CONSIDERATIONS The AD7902 contains two physically isolated ADCs, making it ideally suited for functional safety applications. Because of this isolation, each ADC features an independent user interface, an independent reference input, an independent analog input, and independent supplies. Physical isolation renders the device suitable for taking verification/backup measurements while separating the verification ADC from the system under control. Although the Simultaneous Sampling section describes how to operate the device in a simultaneous nature, the circuit is actually composed of two individual signal chains. This separation makes the AD7902 ideal for handling redundant measurement applications. Implementing a signal chain with redundant ADC measurement can contribute to a no single error system. Figure 52 shows a typical functional safety application circuit consisting of a redundant measurement with the employment of monitoring the inverted signal. The inversion is applied to detect common cause failures where it is expected that the circuit output moves in the same direction during a fault condition, instead of moving in the opposite direction as expected. In addition, the QSOP package that houses the device provides access to the leads for inspection. REF = 2.5V TO 5V 2.5V 0V TO VREF ADA4841-1 REF1 REF2 IN1+ ADC1 PHYSICALLY ISOLATED ADCs VREF IN1– VDD1 VDD2 VIO1 VIO1 SDI1 SDI1 SCK1 SCK1 CNV1 CNV1 SDO1 SDO1 VIO2 VIO2 SDI2 SDI2 SCK2 SCK2 CNV2 CNV2 SDO2 SDO2 R IN2+ ADC2 R R IN2– GND AD7902 Figure 52. Typical Functional Safety Block Diagram Rev. B | Page 25 of 28 11756-146 ADA4841-1 R AD7902 Data Sheet LAYOUT ceramic capacitor in close proximity to (ideally, right up against) the REFx and GND pins and then connecting them with wide, low impedance traces. Design the printed circuit board (PCB) of the AD7902 such that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7902, with its analog signals on the left side and its digital signals on the right side, eases this task. Finally, decouple the power supplies, VDDx and VIOx, with ceramic capacitors, typically 100 nF. Place them in close proximity to the AD7902 and connect them using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7902 is used as a shield. Do not run fast switching signals, such as CNVx or clocks, near analog signal paths. Avoid crossover of digital and analog signals. To avoid signal fidelity issues, take care to ensure monotonicity of digital edges in the PCB layout. See Figure 53 for an example of layout following these rules. EVALUATING PERFORMANCE OF THE AD7902 Other recommended layouts for the AD7902 are outlined in the EVAL-AD7902SDZ User Guide. The package for the evaluation board (EVAL-AD7902SDZ) includes a fully assembled and tested evaluation board, user guide, and software for controlling the board from a PC via the EVAL-SDP-CB1Z. Use at least one ground plane. It can be shared between or split between the digital and analog sections. In the latter case, join the planes underneath the AD7902. The AD7902 voltage reference inputs, REF1 and REF2, have a dynamic input impedance. Decouple these reference inputs with minimal parasitic inductances by placing the reference decoupling GND REF VDD VIO GND GND REF REF1 VIO1 VDD1 SDI1 IN1+ SCK1 IN1– GND REF REF2 SDO1 CNV1 GND VIO2 VDD2 SDI2 IN2+ SCK2 IN2– SDO2 GND CNV2 VIO VDD GND Figure 53. Example Layout of the AD7902 (Top Layer) Rev. B | Page 26 of 28 11756-147 GND Data Sheet AD7902 OUTLINE DIMENSIONS 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 20 11 10 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8° 0° 0.020 (0.51) 0.010 (0.25) 0.050 (1.27) 0.016 (0.41) COMPLIANT TO JEDEC STANDARDS MO-137-AD CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.041 (1.04) REF 09-12-2014-A 1 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) Figure 54. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 AD7902BRQZ AD7902BRQZ-RL7 EVAL-AD7902SDZ EVAL-SDP-CB1Z 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 20-Lead Shrink Small Outline Package [QSOP], Tube 20-Lead Shrink Small Outline Package [QSOP], Reel Evaluation Board Controller Board Z = RoHS Compliant Part. Rev. B | Page 27 of 28 Package Option RQ-20 RQ-20 Ordering Quantity 56 1,000 AD7902 Data Sheet NOTES ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11756-0-8/15(B) Rev. B | Page 28 of 28