UT699LEON3FTBrochure

A passion for performance.
UT699 LEON 3FT
from Aeroflex
Colorado Springs
Designed for operation
in harsh environments
Fault Tolerant architecture
Guaranteed radiation
performance
Real-time operating
system support
LEON 3FT V8 SPARC™
Microprocessor
I t ’s a f a c t
Definitions
LEON µprocessor
LEON is a 32-bit CPU microprocessor core, based on the
SPARC™ V8 RISC architecture
and instruction set. The core
is highly configurable, and suitable particularly for system-on-
W E O F F E R D E V E LO P M E N T TO O L S
A N D R E A L -T I M E O P E R AT I N G
S Y S T E M S U P P O R T. . .
An advantage to working with Aeroflex’s UT699 is the
extensive library of development tools. Since the UT699
is SPARC™ V8 compliant, compilers and kernels for SPARC
V8 are based on industry standard development tools.
chip (SOC) designs. LEON 3FT
is a Fault-Tolerant (FT) version,
Aeroflex offers a full software development suite including
designed for operation in
a C/C++ cross-compiler system based on GCC and the
harsh, radiation-prone environ-
Newlib embedded C-library. The BCC compiler system
ments, and includes function-
allows cross-compilation of C and C++ applications for
ality to detect and correct
the LEON 3FT family.
single bit upset errors in all
on-chip RAM memories.
For multi-threaded applications, SPARC-compliant ports
are available for the following operating systems: eCos,
Definitions
RTEMS, Linux, VxWorks, Nucleus, ThreadX and LynxOS.
SPARC architecture
™
To support the software development process, a simulator
SPARC (Scalable Processor
and a debugger are available. TSIM is a high-performance
Architecture) is a RISC
SPARC-architecture instruction simulator capable of
(Reduced Instruction Set
emulating the UT699 LEON 3FT. GRMON is a debug
Computing) architecture
developed by Sun Microsystems. SPARC is a registered
trademark of SPARC Inter-
monitor for the UT699 processor. It communicates with
the UT699 debug support unit (DSU) and allows nonintrusive debugging of the complete target system.
...P LU S P R OVE N I P
national, Inc., an organization
established to create a larger
The Aeroflex Gaisler GRLIB IP Library is an integrated
ecosystem for the design by
set of reusable IP cores, designed for system-on-chip
promoting, licensing, and
(SOC) development. The IP cores are centered around
providing conformance testing.
the common on-chip bus and use a coherent method
As a result, the SPARC
for simulation and synthesis. The library is vendor
architecture is fully open and
independent, with support for different CAD tools and
non-proprietary.
target technologies. A unique plug-and-play method is
used to configure and connect the IP cores without the
need to modify any global resources.
w w w. a e r o f l e x . c o m / L e o n
800-645-8862
Aeroflex offers the best software suppor
UT699 Software Development Tools (Debug)
G R M O N
CODE MANAGEMENT
• Trace buffer, breakpoint,
watch point, memory,
peripheral registers
• GNU debugger (GDB) support
• Built-in disassembler
• Error
injection
T S I M 2
GENERAL
• Custom module support
• Supports future
LEON roadmap
I/O
OPERATIONS
• Supports UT699: GPIO,
timers, SpW (RMAP,
common), CAN,
UART, cPCI
• Loadable userdefined I/O device
• 64-bit time simulation
• EDAC and MMU
emulation
• Simulation performance >45 MIPS
INTERFACES
DEBUGGING
• In-system flash programming interface
• Flexible debug
interfaces: UART,
JTAG, cPCI, SpaceWire
PLATFORM
PLATFORM
• Eclipse IDE support
• OS: Linux/Windows
• Eclipse IDE support
• OS: Linux/Windows
H A R D
W A R E
GR-CPCI-UT699
U ART or
J TA G
connection
SYSTEM HARDWARE
• 6U cPCI
• SRAM/SDRAM
Flash PROM
• Line transceivers
• RASTA
• ALExIS
• Custom
Ta r g e t h a r d w a r e /
UT699
evaluation board
PC running GRMON
on Windows or Linux
UT699 Operating Systems Options (RTOS)
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Nucleus
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LynxOS
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ThreadX
VxWorks
Snapgear Linux
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Free
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COST
License
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> 150kB
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70-150kB
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FOOTPRINT
< 70kB
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Linux
Timer
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IRQ
PCI
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eCos
UART
CAN
■
Ethernet
SpW
RTEMS
Windows
PLATFORM
OS
SUPPLIED DRIVERS
R E A L-T I M E
O P E R AT I N G
SYSTE M S
• Instruction/stack trace
buffer
• Non-intrusive execution
time profiling
• Check-pointing capability
• Code coverage monitoring
• GNU debugger (GDB) support
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rt in the industry
LEON I DE featuring
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Eclipse-based C/C++ integrated development environment
■
Code entry, build system, and debugging provided
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Support for debugging on real hardware through GRMON
or on a simulator through TSIM
■
Support for different toolchains, templates for RTEMS/RCC,
BCC, Nucleus, ThreadX, and eCos
■
Source-level debugging and disassembly view
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Variables, memory, and register view
■
Support for Linux and Windows host platforms
LEON Integrated Development Environment (I DE)
Build System
Code entry
Debugger
Toolchain support
GDB
BCC
RTEMS/
RCC
eCos
Mkprom2
BCC = Bare-C Cross Compiler
RCC = RTEMS Cross Compiler
GDB = GNU debugger
Mkprom2 = Make prom utility
Nucleus
ThreadX
GRMON
TSIM2
Hardware
Loadable
Modules
PROM image
UT699 is dedicated to HiRel
UT699 FEATURES
UT699 CORES
■
Implemented on a 0.25µm CMOS technology
AMBA bus interconnects a peripheral rich environment:
■
Flexible static design allows up to 66MHz clock rate
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10/100 Base-T Ethernet port
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89DMIPS throughput via 66MHz base clock frequency
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Integrated PCI 2.2 compatible core
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On-board programmable timers, interrupt controllers
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Four integrated multi-protocol SpaceWire nodes with
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High-performance dual-precision IEEE-754 FPU
■
Power-saving 2.5V core power supply; 3.3V I/O
■
Two CAN 2.0 compliant bus interfaces
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Hardened-by-design flip-flops and memory cells
■
Multifunctional memory controller with EDAC
two supporting the RMAP target protocol in hardware
UT699 GUARANTEED RADIATION PERFORMANCE / OPERATIONAL ENVIRONMENT
PA R A M E T E R
LI M IT
U N ITS
Total Ionizing Dose (TID)
3E5
rads(Si)
Single Event Latchup (SEL)
>108
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
UT699 BLOCK DIAGRAM
IEEE754
FPU
UT699 LEON 3FT
Debug support unit
4x SpaceWire
CAN 2.0
MUL/DIV
2X4K
D-cache
2X4K
I-cache
Serial/JTAG debug link
MMU
PCI bridge
AHB interface
AMBA AHB
AHB
arbiter
Memory
controller
8/32-bit memory bus
512MB
non-volatile
AMBA APB
AHB/APB
bridge
512MB
I/O
Up to 1GB
SRAM
UART
Timers
Ethernet
MAC
IrqCtrl
I/O port
UP to 1GB
SDRAM
NOTIONAL SINGLE BOARD COMPUTER
Port 2
UT699 LEON 3FT
Port 3
Port 4
8MB
EDAC
SRAM
4MB
EDAC
non-volatile
memory
Ethernet PHY
Dedicated SpW Links
Port 1
RS-422
LE O N UT699 3F T S PAR C™ V8
M I C R O P R O C E S S O R EVALUATI O N B OAR D
The GR-CPCI-UT699 development board is capable of running at a
system clock speed of 66MHz. The board is a 6U cPCI form factor and
can also be used in a standalone bench-top configuration. The board
supports 32-bit/33MHz PCI, 10/100 Base-T Ethernet, four SpaceWire
ports capable of running up to 200Mbits/s, two CAN ports, on-board
FLASH, SRAM, and SDRAM. A socket for a PROM device and a USB
debug port are also on-board.
ALExI S
ALExIS (Aeroflex LEON Experimenter’s Interface System) is a ready-to-run
development platform for customer applications with flexible architecture
supporting quick path-to-flight after development. Flight and non-flight
versions of the UT699-based single board computer of the ALExIS are
available. The ALExIS platform provides two cPCI slots for future card
expansion, and pre-loaded operating systems and applications drivers.
R ASTA
The Aeroflex Gaisler implementation of the RASTA (Reference Avionics
System Testbed Activity) aims to provide a standardized hardware and software infrastructure for development, prototyping and validation of on-board
systems. It allows quick and easy integration of complete systems in a lab
environment, using standardized interfaces and connectors. It also provides
access to LEON3 technology (through FPGA, ASIC, or products like UT699).
Aeroflex Colorado Springs
WEB SITE
www.aeroflex.com/leon
www.aeroflex.com/gaisler
TELEPHONE
Our passion for performance is defined by three
attributes represented by these three icons:
solution-minded, performance-driven and customer-focused.
800-645-8862
Part No. LB | 1 | 05 | 2011