UT700 (** key updates are pending)

Standard Products
UT700 LEON
3FT/SPARC™ V8 MicroProcessor
Functional Manual
January 2016
www.aeroflex.com/LEON
0
Introduction .........................................................................1
1.1
Scope ................................................................................................................. 1
1.2
Differences between UT699 and UT700 .......................................................... 1
1.3
Architecture....................................................................................................... 2
1.4
Memory map ..................................................................................................... 4
1.5
Interrupts ........................................................................................................... 5
1.6
Signals ............................................................................................................... 6
1.7
Clocking .......................................................................................................... 10
1.7.1
Clock Inputs.................................................................................................................10
LEON 3FT SPARC V8 32-bit Microprocessor ................11
2.1
Overview ......................................................................................................... 11
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.2
Integer unit................................................................................................................... 11
Cache sub-system ........................................................................................................ 11
Floating-point unit .......................................................................................................12
Memory Management unit...........................................................................................12
On-chip debug support.................................................................................................12
Interrupt Port................................................................................................................12
AMBA interface ..........................................................................................................12
Power-down mode .......................................................................................................12
LEON 3FT integer unit ................................................................................... 12
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
2.2.11
2.2.12
2.2.13
2.2.14
2.2.15
Overview......................................................................................................................12
Instruction pipeline ......................................................................................................13
SPARC implementor’s ID............................................................................................15
Divide instructions.......................................................................................................15
Multiply instructions....................................................................................................15
Branch Prediction ........................................................................................................15
Hardware breakpoints ..................................................................................................15
Instruction trace buffer.................................................................................................16
Processor configuration register ..................................................................................16
Exceptions....................................................................................................................18
Single vector trapping (SVT).......................................................................................19
Address space identifiers (ASI) ...................................................................................19
Power-down .................................................................................................................20
Processor reset operation .............................................................................................20
Integer unit SEU protection .........................................................................................21
2.3
Floating-point unit........................................................................................... 21
2.4
Cache sub-system............................................................................................ 21
2.4.1
2.4.2
Overview......................................................................................................................21
Instruction cache ..........................................................................................................22
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
2.4.10
2.4.11
2.4.12
2.5
Memory management unit ...............................................................................29
2.5.1
2.5.2
2.5.3
2.5.4
2.6
Data cache ................................................................................................................... 22
Write buffer ................................................................................................................. 22
Instruction and data cache tags.................................................................................... 22
Cache flushing............................................................................................................. 24
Data Cache snooping................................................................................................... 24
Diagnostic cache access .............................................................................................. 24
Cache control register.................................................................................................. 25
Error protection ........................................................................................................... 27
Cache configuration registers...................................................................................... 27
Software consideration................................................................................................ 28
MMU ASI usage ......................................................................................................... 29
Cache operation........................................................................................................... 29
MMU registers ............................................................................................................ 29
Translation Look-Aside Buffer (TLB) ........................................................................ 33
LEON3FT Storage Allocation .........................................................................33
2.6.1
2.6.2
2.6.3
Integer unit register file ............................................................................................... 33
Floating Point Unit (FPU) register file........................................................................ 33
Cache memories .......................................................................................................... 33
Memory Controller with EDAC .......................................35
3.1
Overview..........................................................................................................35
3.2
PROM access...................................................................................................36
3.3
Memory mapped I/O........................................................................................36
3.4
3.4 SRAM access.............................................................................................36
3.5
8-bit and 16-bit PROM and SRAM access......................................................36
3.6
8-bit I/O access and 16-bit I/O access .............................................................38
3.7
Burst cycles......................................................................................................38
3.8
SDRAM access ................................................................................................38
3.8.1
3.8.2
3.8.3
3.8.4
3.9
General ........................................................................................................................ 38
Address mapping......................................................................................................... 39
Initialization ................................................................................................................ 39
Configurable SDRAM timing parameters................................................................... 39
Refresh .............................................................................................................39
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
SDRAM commands .................................................................................................... 40
Read cycles.................................................................................................................. 40
Write cycles................................................................................................................. 40
Address bus ................................................................................................................. 40
Data bus....................................................................................................................... 40
Clocking ...................................................................................................................... 40
Initialization ................................................................................................................ 40
3.10
Memory EDAC ............................................................................................... 40
3.10.1 BCH EDAC .................................................................................................................40
3.10.2 Reed-Solomon EDAC..................................................................................................41
3.10.3 EDAC Error reporting .................................................................................................42
3.11
Using BRDY ................................................................................................... 42
3.12
Access errors ................................................................................................... 42
3.13
Attaching an external DRAM controller......................................................... 43
3.14
Registers.......................................................................................................... 43
3.14.1
3.14.2
3.14.3
3.14.4
Memory configuration register 1 (MCFG1) ................................................................43
Memory configuration register 2 (MCFG2) ................................................................45
Memory configuration register 3 .................................................................................47
Memory Configuration Register 4...............................................................................48
3.15
Boot strap configuration.................................................................................. 49
3.16
PROM, SRAM, and memory mapped I/O timing diagrams........................... 49
3.17
SDRAM timing diagrams ............................................................................... 57
AHB Status Registers .......................................................59
4.1
Overview ......................................................................................................... 59
4.2
Operation......................................................................................................... 59
4.3
Correctable errors............................................................................................ 59
4.4
Interrupts ......................................................................................................... 59
4.5
Registers.......................................................................................................... 59
Interrupt Controller ...........................................................61
5.1
Overview ......................................................................................................... 61
5.2
Operation......................................................................................................... 61
5.2.1
5.2.2
5.3
Interrupt prioritization..................................................................................................61
Interrupt allocation.......................................................................................................62
Registers.......................................................................................................... 62
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Interrupt level register .................................................................................................63
Interrupt pending register ............................................................................................63
Interrupt force register .................................................................................................63
Interrupt clear register..................................................................................................64
Status register...............................................................................................................64
UART with APB interface ................................................66
6.1
Overview..........................................................................................................66
6.2
6.2 Operation ...................................................................................................66
6.2.1
6.2.2
6.3
Baud-rate generation........................................................................................68
6.3.1
6.3.2
6.4
Transmitter operation .................................................................................................. 66
Receiver operation....................................................................................................... 67
Loop back mode .......................................................................................................... 68
Interrupt generation ..................................................................................................... 68
UART registers ................................................................................................68
6.4.1
6.4.2
6.4.3
6.4.4
UART data register...................................................................................................... 68
UART status register ................................................................................................... 69
UART control register................................................................................................. 70
UART scaler register................................................................................................... 71
Timer Unit .........................................................................72
7.1
Overview..........................................................................................................72
7.2
Operation .........................................................................................................72
7.3
Registers...........................................................................................................73
General Purpose I/O Port ..................................................77
8.1
Overview..........................................................................................................77
8.2
Operation .........................................................................................................77
8.3
Registers...........................................................................................................77
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
GPIO port data value register...................................................................................... 78
GPIO port data output register .................................................................................... 78
GPIO port data direction register ................................................................................ 79
GPIO interrupt mask register ...................................................................................... 79
GPIO interrupt polarity register .................................................................................. 79
GPIO interrupt edge register ....................................................................................... 80
PCI Target / Master Unit ..................................................81
9.1
Overview..........................................................................................................81
9.2
Operation .........................................................................................................81
9.2.1
9.2.2
9.2.3
9.2.4
9.3
PCI target unit ............................................................................................................. 81
PCI master unit............................................................................................................ 81
Burst transactions ........................................................................................................ 82
Byte Twisting .............................................................................................................. 82
PCI target interface ..........................................................................................82
9.4
PCI target configuration space header registers.............................................. 83
9.5
PCI target map registers .................................................................................. 88
9.5.1
9.5.2
9.6
PAGE0 register ............................................................................................................88
9.5.2 PAGE1 register ...................................................................................................89
PCI master interface........................................................................................ 90
9.6.1
9.6.2
9.6.3
PCI configuration cycles..............................................................................................90
9.6.2 I/O cycles ............................................................................................................90
PCI memory cycles......................................................................................................90
9.7
PCI host operation........................................................................................... 91
9.8
Interrupt Support ............................................................................................. 91
9.9
Registers.......................................................................................................... 92
DMA Controller for the GRPCI Interface ........................98
10.1
Introduction ..................................................................................................... 98
10.2
Operation......................................................................................................... 98
10.3
Registers.......................................................................................................... 99
PCIARB - PCI Arbiter ....................................................102
11.1
Overview ....................................................................................................... 102
11.2
Operation....................................................................................................... 102
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
Scheduling algorithm.................................................................................................102
Time-out.....................................................................................................................102
Turn-around ...............................................................................................................102
11.2.4 Bus parking .....................................................................................................102
Lock ...........................................................................................................................102
Latency.......................................................................................................................102
SpaceWire Interface with
RMAP support (GRSPW2) .............................................103
12.1
Overview ....................................................................................................... 103
12.2
12.2 Operation............................................................................................... 103
12.2.1 Overview....................................................................................................................103
12.2.2 Protocol support.........................................................................................................104
12.3
Link interface ................................................................................................ 104
12.3.1 Link interface FSM....................................................................................................104
12.3.2 Transmitter ............................................................................................................... 105
12.3.3 Receiver..................................................................................................................... 105
12.3.4 Time interface............................................................................................................ 106
12.4
Receiver DMA channels................................................................................106
12.4.1 Address comparison and channel selection............................................................... 106
12.4.2 Basic link functionality of a channel..........................................................................110
12.4.3 Setting up the GRSPW2 for reception .......................................................................110
12.4.4 Setting up the descriptor.............................................................................................110
12.4.5 Enabling descriptors...................................................................................................110
12.4.6 Setting up the DMA control register ..........................................................................112
12.4.7 The effect to the control bits during reception ...........................................................112
12.4.8 Status bits ...................................................................................................................112
12.4.9 Error handling ............................................................................................................113
12.4.10 Promiscuous mode .....................................................................................................113
12.5
Transmitter DMA channels............................................................................113
12.5.1
12.5.2
12.5.3
12.5.4
12.5.5
12.5.6
12.5.7
12.6
RMAP ............................................................................................................117
12.6.1
12.6.2
12.6.3
12.6.4
12.6.5
12.6.6
12.7
Basic functionality of a channel .................................................................................113
Setting up the GRSPW2 for transmission ..................................................................113
Enabling descriptors...................................................................................................114
Starting transmissions ................................................................................................114
The transmission process ...........................................................................................116
The descriptor register................................................................................................116
Error handling ............................................................................................................116
Fundamentals of the protocol.....................................................................................117
Implementation ..........................................................................................................117
Write commands.........................................................................................................119
Read commands ........................................................................................................ 120
RMW commands ...................................................................................................... 120
Control....................................................................................................................... 120
AMBA interface ............................................................................................123
12.7.1 APB slave interface................................................................................................... 123
12.7.2 AHB master interface................................................................................................ 123
12.8
SpaceWire clock generation ..........................................................................124
12.9
Registers.........................................................................................................124
CAN-2.0 Interface ..........................................................135
13.1
Overview........................................................................................................135
13.2
AHB interface ................................................................................................135
13.3
13.3 BasicCAN mode ....................................................................................136
13.3.1 BasicCAN register map (Address 0xFFF20000 and 0xFFF20100).......................... 136
13.3.2 Control register.......................................................................................................... 137
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.4
Command register......................................................................................................137
Status register.............................................................................................................138
Interrupt register ........................................................................................................139
Transmit buffer .......................................................................................................... 139
Receive buffer............................................................................................................140
Acceptance filter ........................................................................................................140
PeliCAN mode .............................................................................................. 141
13.4.1 PeliCAN register map (Address 0xFFF20000 and 0xFFF20100) .............................141
13.4.2 Mode Register............................................................................................................ 142
13.4.3 Command register......................................................................................................143
13.4.4 Status register.............................................................................................................143
13.4.5 Interrupt register ........................................................................................................144
13.4.6 Interrupt enable register .............................................................................................144
13.4.7 Arbitration lost capture register .................................................................................145
13.4.8 Error code capture register.........................................................................................145
13.4.9 Error warning limit register .......................................................................................146
13.4.10 RX error counter register (address 14) ......................................................................146
13.4.11 TX error counter register (address 15).......................................................................146
13.4.12 Transmit buffer ..........................................................................................................147
13.4.13 Receive buffer............................................................................................................149
13.4.14 Acceptance filter ........................................................................................................151
13.4.15 RX Message Counter .................................................................................................153
13.5
Common registers ......................................................................................... 153
13.5.1 Clock Divider Register ..............................................................................................153
13.5.2 Bus timing 0...............................................................................................................153
13.5.3 Bus timing 1...............................................................................................................154
13.6
CAN-OC VS SJA1000.................................................................................. 154
Ethernet Media Access Controller (MAC)
with EDCL Support ........................................................155
14.1
Overview ....................................................................................................... 155
14.2
Operation....................................................................................................... 155
14.2.1 System overview........................................................................................................155
14.2.2 Protocol support.........................................................................................................156
14.2.3 Hardware requirements..............................................................................................156
14.2.4 Transmitter DMA interface........................................................................................156
14.2.5 Setting up a descriptor ...............................................................................................156
14.2.6 Starting transmissions ................................................................................................157
14.2.7 Descriptor handling after transmission ......................................................................158
14.2.8 Setting up the data for transmission...........................................................................158
14.2.9 Receiver DMA interface ............................................................................................158
14.2.10 Setting up descriptors.................................................................................................158
14.2.11 Starting reception .......................................................................................................160
14.2.12 Descriptor handling after reception........................................................................... 160
14.2.13 Reception with AHB errors....................................................................................... 160
14.2.14 MDIO interface ......................................................................................................... 160
14.2.15 Ethernet Debug Communication Link (EDCL) ........................................................ 161
14.2.16 Media independent interfaces.................................................................................... 162
14.2.17 Software drivers ........................................................................................................ 162
14.3
Registers.........................................................................................................162
Hardware Debug Support ...............................................169
15.1
Introduction....................................................................................................169
15.2
Operation .......................................................................................................169
15.3
AHB Trace Buffer..........................................................................................170
15.4
Instruction trace buffer...................................................................................171
15.5
DSU memory map .........................................................................................171
15.6
DSU registers.................................................................................................173
15.6.1
15.6.2
15.6.3
15.6.4
15.6.5
15.6.6
15.6.7
15.6.8
15.6.9
DSU control register.................................................................................................. 173
DSU break and single-step register........................................................................... 174
DSU trap register....................................................................................................... 175
DSU trace buffer time tag counter register ............................................................... 175
DSU ASI diagnostic access register.......................................................................... 176
AHB trace buffer control register.............................................................................. 176
AHB trace buffer index register ................................................................................ 177
AHB trace buffer breakpoint registers ...................................................................... 177
Instruction trace control register ............................................................................... 178
Serial Debug Link ...........................................................179
16.1
Overview........................................................................................................179
16.2
Operation .......................................................................................................180
16.2.1 Transmission protocol ............................................................................................... 180
16.2.2 Baud rate generation.................................................................................................. 180
16.3
Registers.........................................................................................................181
JTAG Debug Link ..........................................................183
17.1
Overview........................................................................................................183
17.2
Operation .......................................................................................................183
17.2.1 Transmission protocol ............................................................................................... 183
17.3
Registers.........................................................................................................184
17.4
Boundary Scan .............................................................................................. 184
CLKGATE Clock Gating Unit .......................................185
18.1
Overview ....................................................................................................... 185
18.2
Operation....................................................................................................... 185
18.3
Registers........................................................................................................ 186
SPI Controller .................................................................187
19.1
Overview ....................................................................................................... 187
19.2
Operation....................................................................................................... 187
19.2.1
19.2.2
19.2.3
19.2.4
19.3
SPI transmission protocol ..........................................................................................187
Receive and transmit queues......................................................................................188
Clock generation ........................................................................................................188
Operation (master-only).............................................................................................189
Registers........................................................................................................ 189
Dual Redundant MIL-STD-1553B
Interface (GR1553B) ......................................................197
20.1
Overview ....................................................................................................... 197
20.2
Electrical interface ........................................................................................ 197
20.3
Operation....................................................................................................... 198
20.3.1
20.3.2
20.3.3
20.3.4
20.4
Bus Controller Operation .............................................................................. 198
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.4.6
20.5
Operating modes ........................................................................................................198
Register interface .......................................................................................................198
Interrupting ................................................................................................................198
MIL-STD-1553 Codec...............................................................................................198
Overview....................................................................................................................198
Timing control ........................................................................................................... 198
Bus selection ..............................................................................................................199
Secondary transfer list ...............................................................................................199
Interrupt generation....................................................................................................199
Transfer list format ....................................................................................................200
Remote Terminal Operation.......................................................................... 205
20.5.1
20.5.2
20.5.3
20.5.4
Overview....................................................................................................................205
Data transfer handling................................................................................................205
Mode Codes ............................................................................................................... 206
Event Log...................................................................................................................206
20.5.5 Subaddress table format ............................................................................................ 207
20.6
Bus Monitor Operation ..................................................................................210
20.6.1 Overview ................................................................................................................... 210
20.6.2 No-response handling................................................................................................ 210
20.6.3 Log entry format........................................................................................................ 210
20.7
Clocking and reset .........................................................................................211
20.8
Registers.........................................................................................................212
Appendix A: Errata ........................................................232
UT700 MIL-STD-1553 NOISE REJECTION LIMITATIONS ................................232
Overview/Problem Statement ........................................................................232
Technical Background ...................................................................................232
Specific Description of the Problem..............................................................232
Implications ...................................................................................................232
Workarounds ..................................................................................................233
Chapter 1: Introduction
Section 1.1: Scope
Chapter 1: Introduction
1.1
Scope
The following document describes the UT700 LEON 3FT microprocessor; a pipelined, monolithic, high-performance, faulttolerant SPARC™ V8 compliant processor, designed using a combination of hardened flip-flops and TMR schemes to ensure
reliable operations in a typical HiRel environment. The UT700 provides a 32-bit/33MHz PCI (Revision 2.1 compatible) master/target interface with DMA and arbitration capabilities. An AMBA (Rev. 2.0) bus interface integrates the LEON 3FT CPU,
SpaceWire, Ethernet MAC, memory controller, PCI, Mil-Std-1553, SPI, CAN bus, UART, and programmable general purpose
input/output cores.
Industry standard SPARC V8 compilers and kernels support the UT700 software development environment. A full software
development suite, includes a C/C++ cross-compiler based on the Gnu Compiler Collection(GCC), and POSIX-compliant
Newlib embedded C-library. Contact Aeroflex Gaisler for C/C++ cross-compiler and C-library support. The Bare C Compiler
(BCC), based upon GCC, produces a small run-time kernel with interrupt support and Pthreads library. Software development suite runs on either Windows or Linux operating systems. SPARC compliant ports of the eCos real-time kernel,
RTEMS, and VxWorks RTOS support multi-thread applications.
The UT700 LEON 3FT microprocessor is based on IP cores from Aeroflex Gaisler AB’s GRLIB Intellectual Property (IP) library
and uses a plug-and-play system on a chip design approach.
1.2
Differences between UT699 and UT700
The table below outlines the main differences between UT699 and UT700.
Table 1.1 UT699 versus UT700 Differences
94-00-00-000
Ver. 1.1.0
Parameter
UT699
UT700
1553 BC, RT, BM
None
Yes
AHB trace buffer
128 lines
256 lines
Clocking
Processor and AHB in same clock
domain
AHB can be clocked at 1/2 processor clock
Data cache misses
Single words can be cached
Cache misses always result in cache line fill
Ethernet debug link
None
Yes
LEON3 cache size
2 x 4 Kbyte icache, 2 x 4 Kbyte
dcache
4 x 4 Kbyte icache, 4 x 4 Kbyte dcache
LEON3 load delay
Pipeline load delays is 2
Pipeline load delay is 1
LEON3 dcache fetch
Data cache fetches only missed
word
Data cache fetches whole line (16 bytes)
LEON3 MMU
8 + 8 I/D TLB entries
2 clocks stall on write hit
16 + 16 I/D TLB entries
No stall on write hit
LEON3 FPU
GRFPU
GRFPU with instruction FIFO and correction of bugs
LEON3 register file
Protected against SEU using 7-bit
BCH (SEC/DED)
Protected against SEU using TMR
-1-
Aeroflex Microelectronic Solutions - HiRel
Chapter 1: Introduction
Section 1.3: Architecture
Table 1.1 UT699 versus UT700 Differences
1.3
Parameter
UT699
UT700
LEON3 Multiplier
16-bit multiplier requiring 5 clocks
per MUL instruction
32-bit multiplier requiring 1 clock per MUL
instruction
LEON3 instruction trace
128 lines
256 lines
LEON3 cache freeze
Cache freeze is available for data
and instruction cache
Only instruction cache freeze is available
LEON3 IU
Pipeline restart on correction
Correction without pipeline restart
Memory controller
BCH EDAC only
BCH and Reed-Solomon protection of
SDRAM
PCI
Parity checking errata
Correction of parity checking errata
Processor and bus clock
domain
Shared clock domain
Processor operates on a separate clock
domain from the AMBA and memory bus
SpaceWire write synchronization error bit
Supported
No longer required
SpaceWire
GRSPW (with 2 RMAP)
GRSPW2 (with 4 RMAP)
SpaceWire RMAP error code
No support for RMAP invalid desttination address error code
RMAP invalid destination address error
code is supported
SpaceWire timer and disconnect register
Supported
No longer required or supported
SpaceWire CLK to system clock
relationship
SPW_CLK ≤ 4 x SYS_CLK
SPW_CLK ≤ 8 x SYS_CLK
SpaceWire receive clock to system clock relationship
RxCLK ≤ 2 x SYS_CLK
No longer tied to SYS_CLK, relationship is
now related to the SPW_CLK
SPW_CLK ≥ 3/4 receive data rate (max)
SpaceWire Loopback
Not Supported
Supports internal loopback
SPI
None
Yes
Interrupt Controller status register with extended interrupts
and CPU power-down status
Not Supported
Supported
Architecture
The UT700 consists of the following components:
•
•
•
•
•
•
•
94-00-00-000
Ver. 1.1.0
LEON3FT processor core
8/16/32-bit memory controller
Four Spacewire links
Two CAN-2.0 interfaces
UART
A timer unit with 4 timings
One Extended Interrupt Controller
-2-
Aeroflex Microelectronic Solutions - HiRel
Chapter 1: Introduction
Section 1.3: Architecture
• A 16-bit I/O port
• Serial/JTAG debug links
• 10/100 ethernet MAC
• MIL-STD-1553B (BC, RT, BM)
• An SPI interface.
The following image is a block diagram of the UT700 architecture.
RS232
JTAG
1553 A/B
IEEE754
GRFPU
LEON3FT
1553
BC,RT,BM
MUL/DIV
Serial/JTAG
Debug Link
LVTTL
PCI
2xCAN
4x SpW
PCI
Bridge
CAN-2.0
4x4K Icache 4x4K Dcache
SRMMU
32-bit AHB interface
32-bit AMBA AHB
AHB Ctrl
Memory
Controller
AMBA APB
AHB/APB
Bridge
UART
Timers
RS232
WDOGN
IrqCtrl
I/O port
SPI
16-bit I/O
1xSPI
Ethernet
MAC
8/32-bits memory bus
PROM
I/O
SRAM
SDRAM
10/100 PHY
Figure 1.1 UT700 Functional Block Diagram
The design is based on the following IP cores from the GRLIB IP library:
Table 1.2 GRLIB IP cores used in the UT700
CORE
FUNCTION
VENDOR ID
DEVICE ID
REV
LEON 3FT
SPARC V8 32-bit processor
0x01
0x053
0x0
DSU3
Debug support unit
0x01
0x004
0x1
IRQMP
Interrupt controller
0x01
0x00D
0x3
APBCTRL
AHB/APB Bridge
0x01
0x006
0x0
FTMCTRL
8/32-bit memory controller with EDAC
0x01
0x054
0x1
AHBSTAT
AHB failing address register
0x01
0x052
0x0
AHBUART
Serial/AHB debug interface
0x01
0x007
0x0
AHBJTAG
JTAG/AHB debug interface
0x01
0x01C
0x1
GRSPW2
SpaceWire link with RMAP
0x01
0x029
0x0
GRPCI
32-bit PCI bridge
0x01
0x014
0x0
PCIDMA
DMA controller for PCI bridge
0x01
0x016
0x0
94-00-00-000
Ver. 1.1.0
-3-
Aeroflex Microelectronic Solutions - HiRel
Chapter 1: Introduction
Section 1.4: Memory map
Table 1.2 GRLIB IP cores used in the UT700
1.4
CORE
FUNCTION
VENDOR ID
DEVICE ID
REV
CANMC
Dual CAN-2.0 interface
0x01
0x019
0x1
GRETH
10/100 Ethernet MAC with EDCL
0x01
0x01D
0x0
APBUART
8-bit UART with FIFO
0x01
0x00C
0x1
GPTIMER
Modular timer unit
0x01
0x011
0x0
GPIO
General purpose I/O port
0x01
0x01A
0x1
CLKGATE
Clock gating module
0x01
0x02C
0x0
PCIARB
PCI Arbiter
0x04
0x10
0x0
GR1553B
Advanced MIL-STD-1553B BC, RT, BM
0x01
0x04D
0x0
SPICTRL
SPI controller (master)
0x01
0x02D
0x5
GRGPREG
General purpose register
0x01
0x087
0x0
Memory map
The following table is a memory map of the internal AHB/APB buses.
Table 1.3 Internal Memory Map
CORE
BUS
FTMCTRL
0x00000000 - 0x1FFFFFFF : PROM area
0x20000000 - 0x2FFFFFFF : I/O area
0x40000000 - 0x7FFFFFFF : SRAM/SDRAM area
AHB
APBCTRL1
0x80000000 - 0x800FFFFF : APB bridge
AHB
FTMCTRL
0x80000000 - 0x800000FF : Registers
APB
APBUART
0x80000100 - 0x800001FF : Registers
APB
IRQMP
0x80000200 - 0x800002FF : Registers
APB
GPTIMER
0x80000300 - 0x800003FF : Registers
APB
0x80000400 - 0x800004FF : PCI DMA control registers
APB
PCI DMA CTRL
0x80000500 - 0x800005FF : Registers
APB
CLKGATE
0x80000600 - 0x800006FF : Registers
APB
AHBUART
0x80000700 - 0x800007FF : Registers
APB
PCIARB
0x80000800 - 0x800008FF : Registers
APB
GPIO
0x80000900 - 0x800009AA : Registers
APB
SPW1
0x80000A00 - 0x80000AFF : Registers
APB
SPW2
0x80000B00 - 0x80000BFF : Registers
APB
PCI
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Aeroflex Microelectronic Solutions - HiRel
Chapter 1: Introduction
Section 1.5: Interrupts
Table 1.3 Internal Memory Map
CORE
ADDRESS RANGE
BUS
SPW3
0x80000C00 - 0x80000CFF : Registers
APB
SPW4
0x80000D00 - 0x80000DFF : Registers
APB
ETH
0x80000E00 - 0x80000EFF : Registers
APB
AHBSTAT
0x80000F00 - 0x80000FFF : Registers
APB
Reserved
0x80001000 - 0x800FEFFF : Unused
APB
0x800FF000 - 0x800FFFFF : Plug-and-play configuration
APB
0x80100000 - 0x801FFFFF : APB bridge
AHB
1553B
0x80100000 - 0x801000FF : Registers
APB
SPICTRL
0x80100100 - 0x801001FF : Registers
APB
GPREG
0x80100200 - 0x801002FF : Registers
APB
0x801FF000 - 0x801FFFFF: Plug&play configuration
APB
Reserved
0x80200000 - 0x8FFFFFFF : Unused
APB
DSU3
0x90000000 - 0x9FFFFFFF : Registers
AHB
Reserved
0xA0000000 - 0xBFFFFFFF : Unused
APB
0xC0000000 - 0xFFEFFFFF : PCI Bus
0xFFF00000 - 0xFFF1FFFF : PCI I/O space
AHB
CANOC1
0xFFF20000 - 0xFFF200FF : Registers
AHB
CANOC2
0xFFF20100 - 0xFFF201FF : Registers
AHB
Reserved
0xFFF20200 - 0xFFFFEFFF : Unused
AHB
0xFFFFF000 - 0xFFFFFFFF : Plug-and-play configuration
AHB
APB plug-and-play
APBCTRL2
APB plug&play
PCI
AHB plug-and-play
Access to addresses outside the ranges described above will return an AHB error response.
1.5
Interrupts
The interrupts are routed to the IRQMP interrupt controller and forwarded to the LEON 3FT processor. The following table
indicates the interrupt assignments:
Table 1.4 Interrupt Assignment
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CORE
INTERRUPT #
FUNCTION
AHBSTAT
1
AHB bus error
APBUART
2
UART RX/RX interrupt
PCI
3
PCI DMA interrupt
CAN1
4
CAN1 interrupt
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Chapter 1: Introduction
Section 1.6: Signals
Table 1.4 Interrupt Assignment
1.6
CORE
INTERRUPT #
FUNCTION
CAN2
5
CAN2 interrupt
GPTIMER
6, 7, 8, 9
Timer underflow interrupts
IRQMP
9
Extended interrupt vector
SPW1
10
SpaceWire1 interrupt
SPW2
11
SpaceWire2 interrupt
SPW3
12
SpaceWire3 interrupt
SPW4
13
SpaceWire4 interrupt
ETH
14
Ethernet interrupt
1553B
17
MIL-STD-1553 BC, RT, BM interrupt
SPICTRL
18
SPI controller interrupt
GPIO
1 - 15
External I/O interrupt
Signals
The device has the following external signals. The reset value for any signal is undefined if not otherwise indicated.
Table 1.5 Signals
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PIN NAME
FUNCTION
RESET
VALUE
SYSCLK
I
--
Main system clock
NODIV
I
--
Clock divider input. Set to ‘1’ for 1x memory clock, ‘0’
for 1/2x memory clock, relative to SYSCLK
RESET
IS
--
System reset
ERROR1
OD
--
Processor error mode indicator. This is an active low
output.
WDOG1
OD
--
Watchdog indicator. This is an active low output.
ADDR[27:0]
O
[000...0]
Address bus
DATA[31:0]2
I/O
High-z
Data bus
CB[15:0]
I/O
High-z
EDAC checkbits
WRITE
O
1
Write strobe for PROM and I/O
OEN
O
1
Output enable for PROM and I/O
IOS
O
1
I/O area chip select
ROMS[1:0]
O
1
PROM chip select
RWE[3:0]
O
1
SRAM write enable strobe
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DESCRIPTION
Aeroflex Microelectronic Solutions - HiRel
Chapter 1: Introduction
Section 1.6: Signals
Table 1.5 Signals
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PIN NAME
FUNCTION
RESET
VALUE
RAMOE[4:0]
O
1
SRAM output enable
RAMS[4:0]
O
1
SRAM chip select
READ
O
1
SRAM, PROM, and I/O read indicator
BEXC
I
--
Bus exception
BRDY
I
--
Bus ready
SDCLK
O
1
SDRAM clock
SDRAS
O
1
SDRAM row address strobe
SDCAS
O
1
SDRAM column address strobe
SDWEN
O
1
SDRAM write enable
SDCS[1:0]
O
1
SDRAM chip select
SDDQM[3:0]
O
1
SDRAM data mask
CAN_RXD[1:0]
I
--
CAN receive data
CAN_TXD[1:0]
O
1
CAN transmit data
DSUACT
O
0
DSU mode indicator
DSUBRE
I
--
DSU break
DSUEN
I
--
DSU enable
DSURX
I
--
DSU UART receive data
DSUTX
O
1
DSU UART transmit data
TRST
I
--
JTAG reset
TMS
I
--
JTAG test mode select
TCK
I
--
JTAG clock
TDI
I
--
JTAG test data input
TDO
O
--
JTAG test data output
EMDC
O
0
Ethernet media interface clock
ERX_CLK
I
--
Ethernet RX clock
EMDIO
I/O
High-z
ERX_COL
I
--
Ethernet collision error
ERX_CRS
I
--
Ethernet carrier sense detect
ERX_DV
I
--
Ethernet receiver data valid
ERX_ER
I
--
Ethernet reception error
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DESCRIPTION
Ethernet media interface data
Aeroflex Microelectronic Solutions - HiRel
Chapter 1: Introduction
Section 1.6: Signals
Table 1.5 Signals
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PIN NAME
FUNCTION
RESET
VALUE
DESCRIPTION
ERXD[3:0]
I
--
Ethernet receive data
ETXD[3:0]
O
[1010]
Ethernet transmit data
ETX_CLK
I
--
Ethernet TX clock
ETX_EN
O
0
Ethernet transmit enable
ETX_ER
O
0
Ethernet transmit error
EMDINT
I
--
Ethernet management interface data interrupt
EDCLDIS
I
--
Ethernet debug link disable
GPIO[15:0]
I/O
High-z
SPW_CLK
I
--
SpaceWire clock
SPW_RXS[3:0]
I
--
SpaceWire receive strobe
SPW_RXD[3:0]
I
--
SpaceWire receive data
SPW_TXS[3:0]
O
0
SpaceWire transmit strobe
SPW_TXD[3:0]
O
0
SpaceWire transmit data
SPW_RXD[3:0]
I
--
SpaceWire receive data
RXD
I
--
UART receive data
TXD
O
1
UART transmit data
PCI_AD[31:0]
PCI-I/O
High-z
PCI_RST
PCI-I
--
PCI reset input
PCI_CLK
PCI-I
--
PCI clock input
PCI_CBE[3:0]
PCI-I/O
High-z
PCI bus command and byte enable
PCI_PAR
PCI-I/O
High-z
PCI parity checkbit
PCI_FRAME1
PCI-3
High-z
PCI cycle frame indicator
PCI_IRDY1
PCI-3
High-z
PCI initiator ready indicator
PCI_TDRY1
PCI-3
High-z
PCI target ready indicator
PCI_STOP1
PCI-3
High-z
PCI target stop request
PCI_DEVSEL1
PCI-3
High-z
PCI device select
PCI_IDSEL
PCI-I
--
PCI_REQ
PCI-O
High-z
General Purpose I/O
Bit 0 of PCI address and data bus
PCI initializer device select
-8-
PCI request to arbiter in point to point configuration
Aeroflex Microelectronic Solutions - HiRel
Chapter 1: Introduction
Section 1.6: Signals
Table 1.5 Signals
PIN NAME
FUNCTION
RESET
VALUE
DESCRIPTION
PCI_GNT
PCI-I
--
PCI bus access indicator in point to point configuration
PCI_HOST
PCI-I
--
PCI host enable input
PCI_ARB_REQ[7:0]
PCI-I
--
PCI arbiter bus request
PCI_ARB_GNT[7:0]
PCI-O
High-z
PCI arbiter bus grant
PCI_PERR1
PCI-3
High-z
PCI parity error indicator
1553CLK
I
--
1553TXINA
O
High-z
MIL-STD-1553B Transmit Inhibit A
1553RXA
I
--
MIL-STD-1553B Receive Positive A
1553RXA
I
--
MIL-STD-1553B Receive Negative A
1553TXA
O
High-z
MIL-STD-1553B Transmit Positive A
1553TXA
O
High-z
MIL-STD-1553B Transmit Negative A
1553RXENA
O
High-z
MIL-STD-1553B Receive Enable A
1553TXINB
O
High-z
MIL-STD-1553B Transmit Inhibit B
1553RXB
I
--
MIL-STD-1553B Receive Positive B
1553RXB
I
--
MIL-STD-1553B Receive Negative B
1553TXB
O
High-z
MIL-STD-1553B Transmit Positive B
1553TXB
O
High-z
MIL-STD-1553B Transmit Negative B
1553RXENB
O
High-z
MIL-STD-1553B Receive Enable B
SPI_SCK
O
--
SPI Clock
SPIMOSI
O
--
SPI Master Out Slave In
SPIMISO
I
--
SPI Master In Slave Out
SPISLVSEL
O
--
SPI Select
MIL-STD-1553B Clock
Notes:
1. This pin requires a pull-up resistor tied to VDD. Specified resistor values are based on design requirements or as specified in the PCI Local Bus Specification Revision
2.1, Section 4.3.3.
2. CB[15:8] are reset to a high logic level.
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Chapter 1: Introduction
Section 1.7: Clocking
1.7
Clocking
1.7.1
Clock Inputs
The following table shows the clock inputs to the UT700.
Table 1.6 Clock Inputs
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SIGNAL
DESCRIPTION
SYSCLK
Main system clock. The processor and AHB bus is clocked directly by CLK.
PCI_CLK
0-33 MHz PCI clock. Drives the PCI clock domain in the PCI interface.
SPW_CLK
10-200 MHz SpaceWire clock. Provides a clock to all four SpaceWire links.
ETX_CLK
Ethernet transmitter clock. 2.5 or 25 MHz generated by external PHY.
ERX_CLK
Ethernet receiver clock. 2.5 or 25 MHz generated by external PHY.
1553CLK
MIL-STD-1553B BC, RT, BM 20 MHz clock.
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Aeroflex Microelectronic Solutions - HiRel
Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
Section 2.1: Overview
Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
2.1
Overview
The LEON 3FT is a 32-bit processor core conforming to the IEEE-1754 (SPARC V8) architecture. It is designed for embedded
applications while combining high performance with low complexity and low power consumption. The processor core
storage elements and on-chip memory are hardened against SEU errors utilizing various fault-tolerance techniques.
The LEON 3FT has the following main features: 7-stage pipeline with Harvard architecture, separate instruction and data
caches, memory management unit, hardware multiplier and divider, on-chip debug support and a floating point unit.
A block diagram of the LEON 3FT core follows:
3-Port Register File
Trace Buffer
FPU
Multiplier
7-Stage
Integer Pipeline
Divider
I-Cache
Debug port
Debug support unit
Interrupt port
Interrupt controller
D-Cache
SRMMU
AHB I/F
AMBA AHB Master (32-bit)
Figure 2.1 LEON 3FT Microprocessor Core Block Diagram
2.1.1
Integer unit
The LEON 3FT integer unit supports the full SPARC V8 instruction set, including hardware multiply and divide instructions.
The integer unit has eight register windows consiting of a total of one hundred and thirty six(136) 32-bit general-purpose
registers (r registers). These registers conform to the SPARC model for the general purpose operand registers accessible
through instructions, and implemented with RAM blocks. The instruction pipeline uses a Harvard architecture consisting
of seven stages interfaced to a separate instruction and data cache.
2.1.2
Cache sub-system
The processor is configured with 16 Kbyte instruction and 16 Kbyte data caches. The instruction cache is configured as
four-way set-associative with 4 Kbyte per way and 32 bytes per line, while the data cache has four ways of 4 Kbyte with 16
bytes per line. Sub-blocking is implemented with one valid bit per 32-bit word for the instruction cache and one valid bit
per line for data cache. The instruction cache uses streaming during line-refill to minimize refill latency. The data cache
uses write-through policy and implements a double-word write-buffer. The data cache can perform bus-snooping on the
AHB bus, if enabled. Bus-snooping on the AHB bus is used to maintain cache coherency for the data cache.
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Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
Section 2.2: LEON 3FT integer unit
2.1.3
Floating-point unit
The LEON 3FT processor is configured with the Aeroflex Gaisler floating-point unit (GRFPU). The GRFPU executes in parallel
with the integer unit, and does not block the processor operation unless a data or resource dependency exists.
2.1.4
Memory Management unit
The LEON 3FT processor is configured with the SPARC V8 Reference Memory Management Unit (SRMMU). The SPARC V8
compliant SRMMU provides mapping between multiple 32-bit virtual address spaces and physical memory. A three-level
hardware table-walk is implemented, and the MMU has 16 Translation Look-Aside Buffer (TLB) entries for instructions and
16 TLB entries for data.
2.1.5
On-chip debug support
The LEON 3FT pipeline provides support for non-intrusive debugging. Full access to all processor registers and cache
memory is provided through the debug support unit (DSU). To aid software debugging, two hardware watchpoint registers are implemented. Each register can cause a breakpoint trap on an arbitrary instruction or data address range. When
the DSU is enabled, the watchpoints can be used to enter debug mode. The DSU also allows single stepping, instruction
tracing and hardware breakpoint/watchpoint control. An internal trace buffer monitors and stores executed instructions
which can later be read out over the debug interface.
2.1.6
Interrupt Port
LEON 3FT supports the SPARC V8 trap model that supports 15 asynchronous interrupts. The interrupts to the interrupt
port are triggered through the Interrupt Controller.
2.1.7
AMBA interface
The cache system implements an AMBA AHB master to load and store data to/from the caches. The interface is compliant
with the AMBA-2.0 standard. During line refill, incremental bursts are generated to optimize the data transfer.
2.1.8
Power-down mode
The LEON 3FT processor core implements a power-down mode, which halts the pipeline and caches until the next interrupt. This is an efficient way to minimize power-consumption when the application is idle. The processor supports clock
gating during the power down period that provides the means to check for wake-up conditions and maintain cache
coherency.
2.2
LEON 3FT integer unit
2.2.1
Overview
The LEON 3FT integer unit implements the integer part of the SPARC V8 instruction set. The implementation is focused on
high performance and low complexity. The LEON 3FT integer unit has the following main features:
•
•
•
•
•
•
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7-stage instruction pipeline
Separate instruction and data cache interface
Eight register windows to access the 136 r registers
Hardware multiplier with 2 clocks latency
Radix-2 divider (non-restoring)
Single-vector trapping for reduced code size
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Aeroflex Microelectronic Solutions - HiRel
Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
Section 2.2: LEON 3FT integer unit
• Static branch prediction
call/branch address
I-cache
data address
+1
Add
‘0’ jmpa tbr
f_pc
Fetch
d_inst
d_pc
r_inst
r_pc
Decode
r_imm
rd
register file
rs1
imm
rs2
Register Access
y, tbr, wim, psr
e_inst
e_pc
rs1
Execute
operand2
alu/shift
m_inst
mul/div
y
e pc
m_pc
result
30
jmpl address
32
32
address/dataout
datain
m_y
Memory
x_inst
x_pc
xres
x_y
w_inst
w_pc
wres
Y
D-cache
Exception
Write back
30
tbr, wim, psr
Figure 2.2 LEON 3FT Integer Unit Datapath Diagram
2.2.2
Instruction pipeline
The LEON 3FT integer unit uses a single instruction issue pipeline with seven stages:
1. FE (Instruction Fetch): If the instruction cache is enabled and a cache hit occurs, the instruction is fetched from the
instruction cache. Otherwise, the fetch is forwarded to the memory controller. The instruction is valid at the end of
this stage and is latched inside the IU.
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Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
Section 2.2: LEON 3FT integer unit
2. DE (Decode): The instruction is decoded and the CALL or branch target address is generated.
3. RA (Register Access): Operands are read from the register file or from internal data bypasses.
4. EX (Execute): ALU, logical, and shift operations are performed. For memory operations (e.g. LD/ST) and JMPL/RETT
instructions, the address is generated.
5. ME (Memory): Data cache is accessed. If a data cache miss occurs, data is accessed from system memory and the
cache is updated. Store data read out in the execution stage is written to the data cache at this time.
6. XC (Exception) Traps and interrupts are resolved. For cache reads, the data is aligned as appropriate.
7. WR (Write): The result of any ALU, logical, shift, or cache operations are written back to the register file.
Table 2.1 lists the cycles per instruction (assuming cache hit, and no integer condition codes or load interlock exist):
Table 2.1 Instruction Timing
INSTRUCTION
CYCLES
JMPL
31
JMPL, RETT pair
4
Double load
2
Single store
23
Double store
33
SMUL/UMUL
12
SDIV/UDIV
35
Taken Trap
53
Atomic load/store
3
All other instructions
1
Note:
1. Assuming instruction in JMPL delay slot takes one cycle. Additional cycles spent in the delay slot reduces the effective time of the JMPL to 2 or 1.
2. Multiplication cycle count is 1 clock (1 clock issue rate, 2 clock data latency) for the 32x32 multiplier.
3. Cycles can incrrease by 2 cycles during a MMU slow-write.
A number of conditions can extend an instruction’s duration in the pipeline:
Branch interlock: When a conditional branch or trap is performed 1-2 cycles after an instruction which modifies the condition codes, 1-2 cycles of delay is added to allow the condition to be computed. The extra delay is incurred only if the
branch is not taken
Load delay: When using data resulting on a load shortly after the load, the instruction delays to satisfy the pipeline’s load
delay. The processor pipeline can be configured for one or two cycles load delay. One cycle load delay improves performance at a fixed speed, but may degrade maximum clock frequency due to added forwarding paths in the pipeline.
Mul latency: For pipelined multiplier implementations there is 1 cycle extra data latency, accessing the result immediately
after a MUL or MAC adds one cycle pipeline delay.
Hold cycles: During cache miss processing or when blocking on the store buffer, the pipeline holds still until the data is
ready, effectively extending the execution time of the instruction causing the miss by the corresponding number of cycles.
Note: Since the whole pipeline is held still, hold cycles will not mask load delay or interlock delays. On a load cache miss
followed by a data-dependent instruction, both hold cycles and load delay will be incurred.
FPU: The floating-point unit may need to hold the pipeline or extend a specific instruction.
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Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
Section 2.2: LEON 3FT integer unit
2.2.3
SPARC implementor’s ID
Aeroflex Gaisler is assigned number 15 (0x0F) as SPARC implementor’s identification. This value is hard-coded into bits
31:28 in the processor state register (%PSR:impl). The version number for LEON 3FT is 3, which is hard-coded in to bits
27:24 of the PSR (%PSR:ver).
2.2.4
Divide instructions
Full support for SPARC V8 divide instructions is provided via instruction SDIV, UDIV, SDIVCC and UDIVCC. The divide
instructions perform a 64-by-32 bit divide and produce a 32-bit result. Rounding and overflow detection is performed as
defined in the SPARC V8 standard.
2.2.5
Multiply instructions
The LEON 3FT processor supports the SPARC integer multiply instructions UMUL, SMUL UMULCC and SMULCC. These
instructions perform 32x32-bit integer multiplication producing a 64-bit result. SMUL and SMULCC perform signed multiplication while UMUL and UMULCC perform unsigned multiplication. UMULCC and SMULCC also set the condition codes
of the PSR to reflect the result of the operation. The multiply instructions are performed using a 16x16 signed hardware
multiplier, which is iterated four times. To improve timing, the 16x16 multiplier is implemented with a pipeline register
stage.
2.2.6
Branch Prediction
Static branch prediction reduces the penalty for branches preceded by an instruction that modifies the integer condition
codes (see section 2.2.2). The predictor uses a branch-always strategy, and starts fetching instruction from the branch
address. On a prediction hit, 1 or 2 clock cycles are saved, and there is no extra penalty incurred for misprediction as long
as the branch target can be fetched from cache. Branch prediction improves the performance up to 10 - 20% on most control-type applications.
2.2.7
Hardware breakpoints
The integer unit is configured with two hardware breakpoints. Each breakpoint consists of a pair of Ancillary State Registers (%asr24/25 and%asr26/27); one with the break address and one with a mask.
WPR1, WPR2
%asr24,%asr26
31
2
WADDR[31:2]
1
0
--
IF
Figure 2.3 Watchpoint Address Registers
Table 2.2 Description of Watchpoint Address Registers
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BIT NUMBER(S)
BIT NAME
31-2
WADDR[31:2]
1
Reserved
0
IF
RESET
STATE
DESCRIPTION
Watch Address
Defines the range of watch addresses used to
generate a breakpoint.
Instruction Fetch Break Enable
0: Break on instruction fetch disabled.
1: Break on instruction fetch enabled.
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Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
Section 2.2: LEON 3FT integer unit
WPMR1, WPMR2
%asr25, %asr27
31
2
1
WMASK[31:2]
0
DL DS
Figure 2.4 Watchpoint Mask Registers
Table 2.3 Description of Watchpoint Mask Registers
BIT NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-2
WMASK[31:2]
1
DL
Data Load Break Enable
0: Break on data load disabled
1: Break on data load
0
DS
Data Store Break Enable
0: Break on data store disabled
1: Break on data store
Watch Mask
These bits mask or unmask the corresponding
bits in the WADDR.
0: Address bit not used by the WADDR.
1: Address bit used by the WADDR.
Any binary aligned address range can be watched. The range is defined by the WADDR field and masked by the WMASK
field (WMASK[n] = 1 enables comparison). On a breakpoint hit, trap 0x0B is generated. By setting the IF, DL and DS bits, a
hit can be generated on instruction fetch, data load or data store. Clearing these three bits will effectively disable the
breakpoint function.
2.2.8
Instruction trace buffer
The instruction trace buffer consists of a circular buffer that stores executed instructions. The trace buffer operation is controlled through the debug support interface and does not affect processor operation. The size of the trace buffer is 256
lines deep and 128 bits wide. The buffer stores the following information:
• Instruction address and opcode
• Instruction result
• Load/store data and address
• Trap information
• 30-bit time tag
The operation and control of the trace buffer is further described in Chapter 15.0, Hardware Debug Support.
2.2.9
Processor configuration register
The application specific register 17 (%asr17) provides information on configuration of the LEON3FT core. This can be used
to enhance the performance of software. The register can be accessed through the RDASR instruction and has the following layout:
PCR
%asr17
31
28 27
PI
24 23
RFT
15 14 13 12 11 10
RESERVED
DW SV LD
FPU
9
8
M
V8
7
5
NWP
4
0
NWIN
Figure 2.5 Processor Configuration Register
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Table 2.4 Description of Processor Configuration Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-28
PI
0
27-24
RFT
0000
23-15
Reserved
14
DW
0
Disable Write Error Trap
0: Write error trap (tt=0x2b) ignored.
1: Write error trap (tt=0x2b) allowed.
13
SV
0
Single-Vector Trapping Enable
0: Single-vector trapping disabled.
1: Single-vector trapping enabled.
12
LD
0
Load Delay
0: One-cycle load delay is used.
1: Two-cycle load delay is used.
Read=0; Write=don’t care.
11-10
FPU
01
Floating Point Implementation
00: No FPU
01: GRFPU
10: Meiko FPU
11: GRFPU-Lite
Read=01; Write=don’t care.
9
M
0
MAC Implementation
0: Optional multiply-accumulate (MAC) instruction not
available.
1: Optional multiply-accumulate (MAC) instruction is available.
Read=0; Write=don’t care.
8
V8
1
Multiply and Divide Implementation
0: SPARC V8 multiply and divide instructions not available.
1: SPARC V8 multiply and divide instructions are available.
Read=1; Write=don’t care.
7-5
NWP
010
4-0
NWIN
00111
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Processor Index
In multi-processor systems, each LEON 3FT core gets a
unique index to support enumeration. Read=0;
Write=don’t care.
Register File RAM Timing Adjust
Read=0000b; Must write 0000b.
Watchpoint Implementation
Number of implemented watchpoints.
Read=010b; Write=don’t care.
Register Window Implementation
Number of implemented registers windows corresponds to
NWIN+1.
Read=00111b; Write=don’t care.
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Section 2.2: LEON 3FT integer unit
2.2.10 Exceptions
LEON 3FT adheres to the general SPARC trap model. The table below shows the implemented traps and their individual
priority. When Processor Status Register (PSR) bit ET=0, two consecutive exception traps cause the processor to halt execution and enter error mode. The external processor error signal will be asserted (Active Low).
Table 2.5 Trap Allocation and Priority
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TRAP
TT
PRI
DESCRIPTION
Class
reset
0x00
1
Power-on reset
Interrupting
write error
0x2B
2
Write buffer error
Interrupting
instruction_access_error
0x01
3
Error during instruction fetch
Precise
illegal_instruction
0x02
5
UNIMP or other un-implemented instruction
Precise
privileged_instruction
0x03
4
Execution of privileged
instruction in user mode
Precise
fp_disabled
0x04
6
FP instruction while FPU disabled
Precise
cp_disabled
0x24
6
CP instruction while Co-processor disabled
Precise
watchpoint_detected
0x0B
7
Hardware breakpoint match
Precise
window_overflow
0x05
8
SAVE into invalid window
Precise
window_underflow
0x06
8
RESTORE into invalid window
Precise
register_hardware_error
0x20
9
Uncorrectable register file SEU
error
Interrupting
mem_address_not_aligned
0x07
10
Memory access to un-aligned
address
Precise
fp_exception
0x08
11
FPU exception
Deferred
cp_exception
0x28
11
Co-processor exception
Deferred
data_access_exception
0x09
13
Access error during load or
store instruction
Precise
tag_overflow
0x0A
14
Tagged arithmetic overflow
Precise
divide_exception
0x2A
15
Divide by zero
Precise
trap_instruction
0x80 0xFF
16
Software trap instruction (TA)
Precise
interrupt_level_15
0x1F
17
GPIO 15
Interrupting
interrupt_level_14
0x1E
18
GPIO 14 / ETH
Interrupting
interrupt_level_13
0x1D
19
GPIO 13 / SPW4
Interrupting
interrupt_level_12
0x1C
20
GPIO 12 / SPW3
Interrupting
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Table 2.5 Trap Allocation and Priority
TRAP
TT
PRI
DESCRIPTION
Class
interrupt_level_11
0x1B
21
GPIO 11 / SPW2
Interrupting
interrupt_level_10
0x1A
22
GPIO 10 / SPW1
Interrupting
interrupt_level_9
0x19
23
GPIO 9 / GPTIMER 4 / GR1553B
/ SPI
Interrupting
interrupt_level_8
0x18
24
GPIO 8 / GPTIMER 3
Interrupting
interrupt_level_7
0x17
25
GPIO 7 / GPTIMER 2
Interrupting
interrupt_level_6
0x16
26
GPIO 6 / GPTIMER 1
Interrupting
interrupt_level_5
0x15
27
GPIO 5 / CAN2
Interrupting
interrupt_level_4
0x14
28
GPIO 4 / CAN1
Interrupting
interrupt_level_3
0x13
29
GPIO 3
Interrupting
interrupt_level_2
0x12
30
GPIO 2 / APBUART
Interrupting
interrupt_level_1
0x11
31
GPIO 1 / AHBSTAT
Interrupting
2.2.11 Single vector trapping (SVT)
The LEON3FT supports Single-Vector Trapping (SVT) to reduce code size for embedded applications. When enabled, any
taken trap always jumps to the reset trap handler whose address is defined by Trap Base Address Register(TBR) bits
TBR.tba, or TBR[31:19], with the lower 12 bits don’t care. The trap type will be indicated in TBR.tt, or TBR[11:4], and must be
decoded by the shared trap handler. SVT is enabled by setting bit 13 in the PCR (%asr17).
2.2.12 Address space identifiers (ASI)
In addition to the address, the SPARC processor also generates an 8-bit Address Space Identifier (ASI) providing up to 256
separate, 32-bit address spaces. During normal operation, the LEON 3FT processor accesses instructions and data using
ASI 0x08 - 0x0B as defined in the SPARC standard. The LDA/STA instructions are used to access the alternative address
spaces. Table 12 shows the ASI usage for LEON 3FT
Table 2.6 ASI Usage
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ASI
USAGE
0x01
Forced cache miss
0x02
System (cache control) registers
0x08
User instruction
0x09
Supervisor instruction
0x0A
User data
0x0B
Supervisor data
0x0C
Instruction cache tags
0x0D
Instruction cache data
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Section 2.2: LEON 3FT integer unit
Table 2.6 ASI Usage
ASI
USAGE
0x0E
Data cache tags
0x0F
Data cache data
0x10
Flush entire instruction cache
0x11
Flush entire data cache
0x13
MMU flush inst and data context
0x14
MMU diagnostic dcache context access
0x1E
Separate snoop tags
0x15
MMU diagnostic icache context access (requires that the instruction cache is disabled)
0x18
Flush TLB and instruction and data cache
0x19
MMU registers
0x1C
MMU bypass
0x1D
MMU diagnostic access
0x1E
MMU snoop tags diagnostic access
2.2.13 Power-down
The processor supports a power-down feature to minimize power consumption during idle periods. The power-down
mode is entered by performing a WRASR instruction to %asr19:
wr
%g0,%asr19
! write 0x0 to%asr19
During power-down, the pipeline is halted until the next interrupt occurs; therefore, this instruction should not be executed with interrupts disabled or the processor never wake up. Signals inside the processor pipeline and caches are then
static, reducing power consumption from dynamic switching.
2.2.14 Processor reset operation
The processor is reset by asserting the RESET input for at least four clock cycles. The following table indicates the reset values of the registers that are affected by the reset. All other registers either maintain their value or are undefined.
Table 2.7 Processor Reset Values
REGISTER
RESET VALUE
PC (Program Counter)
0x00000000
nPC (Next Program Counter)
0x00000004
PSR (Processor Status Register)
ET=0, S=1
TBR (Trap Base Register)
0x---------
Code execution starts at address 0 following a reset.
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2.2.15 Integer unit SEU protection
The SEU protection for the integer unit register file (RF) is implemented with a triple modular redundancy (TMR) scheme.
When a data word in the register file is corrected, the corrected value is used during the execution of the current instruction, but not automatically written back to the register file. There is generally no need to perform data scrubbing (readwrite operation) on the IU register file. During normal operation, the active part of the IU register file will be flushed to
memory on each task switch. This causes all saved registers to be checked and corrected if necessary. Since most real-time
operating systems performs several task switches per second, the data in the register file is frequently refreshed.
2.3
Floating-point unit
The UT700 SPARC V8 architecture is configured with the GRFPU from Aeroflex Gaisler.
The high-performance GRFPU operates on single- and double-precision operands, and implements all SPARC V8 FPU
instructions except quad precision instructions. The FPU is interfaced to the LEON 3FT pipeline using a LEON3-specific FPU
controller (GRFPC) that allows FPU instructions to be executed simultaneously with integer instructions. Only in case of a
data or resource dependency is the integer pipline held. The GRFPU is fully pipelined and allows the start of one instruction each clock cycle, with the exception of FDIV and FSQRT, which can only be executed one at a time. The FDIV and
FSQRT instructions are executed in a separate divide unit and do not block the GRFPU from performing other operations
in parallel.
All instructions except FDIV and FSQRT have a latency of four clock cycles at instruction level. The table below shows the
GRFPU instruction timing when used together with GRFPC.
Table 2.8 GRFPU Worst-Case Instruction Timing with GRFPC
INSTRUCTION
THROUGHPUT
LATENCY
FADDS, FADDD, FSUBS, FSUBD,FMULS, FMULD, FSMULD,
FITOS, FITOD, FSTOI, FDTOI, FSTOD, FDTOS, FCMPS, FCMPD,
FCMPES, FCMPED
1
4
FDIVS
14
16
FDIVD
15
17
FSQRTS
22
24
FSQRTD
23
25
The GRFPU controller uses the SPARC deferred traps and the GRFPU deferred trap queue (FQ) can contain up to seven
queued instructions when an GRFPU exception is taken. The register file for the GRFPU consists of thirty-two, 32-bit registers. In the UT700, the register file has been implemented with SEU-hardened flip-flops and does not need SEU errordetection or correction.
2.4
Cache sub-system
2.4.1
Overview
The LEON3 processor pipeline implements a Harvard architecture with separate instruction and data buses, connected to
two independent cache controllers. The instruction and data cache controllers each provide a four-way set associative
cache. The way size is 4 Kbyte, divided into cache lines of 16 bytes of data. A cache line can be locked in the instruction or
data cache to prevent it from being replaced by the replacement algorithm. The cache sub-system uses least recently used
CLRD replace policy.
Cachability for both caches is controlled through the AHB plug-and-play address information. The memory mapping for
each AHB slave indicates whether the area is cachable, and this information is used to statically determine which access
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will be treated as cachable. This approach means that the cachability mapping is always coherent with the current AHB
configuration.
The detailed operation of the instruction and data caches is described in the following sections.
2.4.2
Instruction cache
The instruction cache is implemented as a four-way set-associative cache with LRU replacement. Each way is 4 KB large
and divided into cache lines of 32 bytes. Each line has a cache tag associated with it, consisting of a tag field and valid bit
for each 4-byte sub-block. On an instruction cache miss to a cachable location, the instruction is fetched and the corresponding tag and data line are updated.
If instruction burst fetch is enabled in the cache control register (CCR), the cache line is filled from main memory starting at
the missed address and until the end of the line. At the same time, the instructions are forwarded to the IU. If the IU cannot
accept the streamed instructions due to internal dependencies or multi-cycle instruction, the IU is halted until the line fill
is completed. If the IU executes a control transfer instruction (branch/CALL/JMPL/RETT/TRAP) during the line fill, the line
fill will be terminated on the next fetch. If instruction burst fetch is enabled, instruction streaming is enabled even when
the cache is disabled. In this case, the fetched instructions are only forwarded to the IU and the cache is not updated. During cache line refill, incremental bursts are generated on the AHB bus.
If a memory access error occurs during a line fill with the IU halted, the corresponding valid bit in the cache tag will not be
set. If the IU later fetches an instruction from the failed address, a cache miss occurs, triggering a new access to the failed
address. If the error remains, an instruction access error trap (tt=0x01) will be generated.
2.4.3
Data cache
The data cache is configured with four-ways of 4 KB 16 bytes/line and LRU replacement. On a data cache read-miss to a
cachable location, 16 bytes (one line) of data are loaded into the cache from main memory. The write policy for stores is
write-through with no-allocate on a write miss. If a memory access error occurs during a data load, the corresponding
valid bit in the cache tag will not be set and a data access error trap (tt=0x09) will be generated.
2.4.4
Write buffer
The write buffer (WRB) is capable of holding any single 8, 16, 32, or 64 bit data to be written to the destination device. For
half-word or byte stores, the stored data is replicated into proper byte alignment for writing to a word-addressed device
before being loaded into one of the WRB registers. The WRB is emptied prior to a load-miss cache-fill sequence to avoid
any stale data from being written into the data cache.
Since the processor executes in parallel with the write buffer, a write error will not cause an exception to the store instruction. Depending on memory and cache activity, the write cycle may not occur until several clock cycles after the store
instruction has completed. If a write error occurs, the currently executing instruction will take trap 0x2B.
Note: The 0x2B trap handler should flush the data cache, since a write hit would update the cache while the memory
would keep the old value due the write error.
2.4.5
Instruction and data cache tags
The instruction and data cache tags and shown in Figure 2.6 and Figure 2.8.
31
12 11
ITAG
8
7
00000
0
IVAL
Figure 2.6 Instruction Cache Tag Layout for 4 KB per Way with 32 Bytes/Line
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Table 2.9 Description of Instruction Cache Tag Layout for 4 KB per Way with 32 Bytes/Line
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-13
ITAG
[000...0]
Instruction Cache Address Tag
Contains the tag address of the cache line.
12-8
Reserved
[000...0]
Read=00000b; Write=don’t care.
7-0
IVAL
[000...0]
Instruction Tag Valid
When set, the corresponding sub-block of the cache line contains
valid data. These bits are set when a sub-block is filled due to a
cache miss; a cache fill which results in a memory error will leave
the valid bit unset. A FLUSH instruction will clear all valid bits.
IVAL[0]: corresponds to address 0 in the I-cache line
IVAL[1]: corresponds to address 1 in the I-cache line
IVAL[4]: corresponds to address 2 in the I-cache line
IVAL[3]: corresponds to address 3 in the I-cache line
IVAL[4]: corresponds to address 4 in the I-cache line
IVAL[5]: corresponds to address 5 in the I-cache line
IVAL[6]: corresponds to address 6 in the I-cache line
IVAL[7]: corresponds to address 7 in the I-cache line
31
12 11
DTAG
4
00000000
3
0
DVAL
Figure 2.7 Data Cache Tag Layout for 4 KB per Way with 16 Bytes / Line
Table 2.10 Description of Data Cache Tag Layout with 16 Bytes / Line
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-12
DTAG
[000...0]
Data Cache Address Tag
Contains the tag address of the cache line.
11-4
Reserved
[000...0]
Read=00000000b; Write=don’t care.
3-0
DVAL
[000...0]
Data Tag Valid
When set, the corresponding sub-block of the cache line contains
valid data. These bits are set when a sub-block is filled due to a
cache miss; a cache fill which results in a memory error will leave
the valid bit unset. A FLUSH instruction will clear all valid bits.
DVAL[0]: corresponds to address 0 in the D-cache line
DVAL[1]: corresponds to address 1 in the D-cache line
DVAL[4]: corresponds to address 2 in the D-cache line
DVAL[3]: corresponds to address 3 in the D-cache line
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Section 2.4: Cache sub-system
2.4.6
Cache flushing
Both instruction and data caches are flushed by executing the FLUSH instruction. The entire instruction cache is also
flushed by setting the FI bit in the cache control register (CCR) or by writing to any location with ASI=0x10. The entire data
cache is also flushed by setting the FD bit in the CCR or by writing to any location with ASI=0x11. Cache flushing takes one
cycle per cache line, during which, the IU will not be halted and the caches are disabled. When the flush operation is completed, the cache resumes the state (disabled, enabled or frozen) indicated in the cache control register. Diagnostic access
to the cache is not possible during a FLUSH operation and will cause a data exception (tt=0x09), if attempted.
2.4.7
Data Cache snooping
To keep the data cache synchronized with external memory, cache snooping can be enabled in the cache control register.
When enabled, the data cache monitors write accesses on the AHB bus to cacheable locations. If any other AHB master
writes to a cacheable location which is currently cached in the data cache, the corresponding cache line is marked as
invalid, and causes a cache miss when accessed by the processor. This updates the data cache with the latest data from
external memory.
2.4.8
Diagnostic cache access
Tags and data in the instruction and data cache can be accessed through ASI address space 0x0C, 0x0D, 0x0E and 0x0F by
executing LDA and STA instructions. The ITAG and DTAG fields of the cache tag define the upper 20 bits of the address,
while the twelve (12) least significant bits of the address correspond to the index of the cache set.
2.4.8.1 Diagnostic reads of instruction and data cache
Cache tags are read by executing an LDA instruction with ASI=0x0C for instruction cache tags and ASI=0x0E for data cache
tags. A cache line and set are indexed by the address bits making up the cache offset and the least significant bits of the
address bits making up the address tag. Similarly, the data sub-blocks may be read by executing an LDA instruction with
ASI=0x0D for instruction cache data and ASI=0x0F for data cache data. The sub-block to be read in the indexed cache line
and set is selected 64, the regaddr field of the LDA or STA instruction.
2.4.8.2 2.4.8.2 Diagnostic writes to instruction and data cache
Cache tags can be directly written to by executing a STA instruction with ASI=0xC for the instruction cache tags and
ASI=0x0E for the data cache tags. The cache line and set are indexed by the address bits making up the cache offset and
the least significant bits of the address bits making up the address tag. D[31:10] is written into the ATAG filed and the valid
bits are written with D[7:0] of the write data for instruction cache and D[3:0] for data cache. Bit D[9] is written into the LRR
bit (disabled) and D[8] is written into the lock bit (disabled). The data sub-blocks can be directly written by executing a STA
instruction with ASI=0xD for the instruction cache data and ASI=0xF for the data cache data. The sub-block to be read in
the indexed cache line and set is selected by A[4:2].
In four-way caches, the address of the tags and data of the ways are concatenated. The address of a tag or data is thus:
ADDRESS = WAY & LINE & DATA & “00”
Examples: the tag for line 2 in way 1 of a 4x4 Kbyte cache with 16 byte line would be:
A[13:12]
=1
(WAY)
A[11:5]
=2
(TAG)
=> TAG ADDRESS = 0x1040
The data of this line would be at addresses 0x1040 - 0x104C.
The context and parity bits for data and instruction caches can be read out via ASI 0xC - 0xF when the PS bit in the cache
control register is set. The data will be organized as shown below.
ASI = 0xC
ASI = 0xE
31
23
16 15
MMU CTX [7:0]
ASI = 0xD
ASI = 0xF
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0
TAG PAR[3:0]
DATA PAR[3:0]
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Figure 2.8 Data Cache Tag Diagnostic Access when CCR.PS = “1”
2.4.9
Cache control register
The operation of the instruction and data caches is controlled through a common Cache Control Register (CCR) is shown in
Figure 2.9. The instruction cache can operate in the disabled, enabled, or frozen mode as configured by the Instruction
Code State (ICS) field. The data cache can operate in the disabled or enabled modes, as configured in the Data Cache State
(DCS) field. If disabled, no cache operation is performed and load and store requests are passed directly to the memory
controller. If enabled, the cache operates as described above. In the frozen state, the cache is accessed and kept synchronized to the main memory as if it were enabled, but no new lines are allocated on read misses.
Table 2.11 ASI 0x02 (System Registers) Address Map
REGISTER
ADDRESS
Cache control register
0x00
Instruction cache configuration register
0x08
Data cache configuration register
0x0C
ASI 0x02
OFFSET 0x00
CCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RES
PS
TB
DS FD
FI
FT
RES ST
IB
IP
DP
ITE
IDE
9
8
DTE
7
6
DDE
5
4
DF
IF
3
2
DCS
1
0
ICS
Figure 2.9 Cache Control Register
Table 2.12 Description of Cache Control Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-29
Reserved
000
28
PS
0
27-24
TB
0000
23
DS
1
Data Cache Snoop
1: Enable data cache snoop
2: Disable data cache snoop
22
FD
0
Flush Data Cache
0: No effect.
1: Flush the data cache.
Read=0.
Parity Select
0: Diagnostic read will return tag or data word.
1: Diagnostic read will return the check bits in the bits 3:0.
Test Bits
0: No effect.
1: Check bits will be XORed with test bits TB during diagnostic.
write.
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Table 2.12 Description of Cache Control Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
21
FI
0
Flush Instruction Cache
0: No effect.
1: Flush the instruction cache.
Read=0.
20-19
FT
00
Fault Tolerant Mode
00: No fault-tolerance
01: 4-bit parity checking
10: Unused
11: Unused
18
Reserved
0
17
ST
1
Separate Snoop Tags
1: Separate snoop tags for instruction and data
Read = 1; Write = don’t care
16
IB
1
Instruction Burst Fetch
0: Disable burst fill during instruction fetch.
1: Enable burst fill during instruction fetch.
15
IP
0
Instruction Cache Flush Pending
0: Instruction cache flush operation not in progress.
1: Instruction cache flush operation is in progress.
14
DP
0
Data Cache Flush Pending
0: Data cache flush operation is not in progress.
1: Data cache flush operation is in progress.
13-12
ITE
00
Instruction Cache Tag Errors
Number of detected parity errors in the instruction tag cache.
11-10
IDE
00
Instruction Cache Data Errors
Number of parity errors in the instruction data cache.
9-8
DTE
00
Data Cache Tag Errors
Number of detected parity errors in the data tag cache.
7-6
DDE
00
Data Cache Data Errors
Number of detected parity errors in the data cache.
5
DF
0
Data Cache Freeze on Interrupt
Data cache response to asynchronous interrupt:
0: Normal operation.
Read = 0, Write = don’t care
4
IF
0
Instruction Cache Freeze on Interrupt
Instruction cache response to asynchronous interrupt:
0: Normal operation.
1: Instruction cache automatically frozen.
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Table 2.12 Description of Cache Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
3-2
DCS
11
Data Cache State
Indicates the current data cache state:
00: Disabled
x1: Enabled
x=don’t care.
1-0
ICS
11
Instruction Cache State
Indicates the current instruction cache state:
x0: Disabled
01: Frozen
11: Enabled
If the DF or IF bit is set, the corresponding cache will be frozen when an asynchronous interrupt is taken. This can be beneficial in a real-time system to allow a more accurate calculation of worst-case execution time for a code segment. The execution of the interrupt handler will not evict any cache lines. When control is returned to the interrupted task, the cache
state is identical to what it was before the interrupt. If a cache has been frozen by an interrupt, it can only be re-enabled by
setting the DCS or ICS fields to the enabled state. This is typically done at the end of the interrupt handler before control is
returned to the interrupted task.
2.4.10 Error protection
Each word in the cache tag or cache data is protected by four parity bits. An error during a cache access causes a cache line
flush and a re-execution of the failing instruction. This ensures the complete cache line (tags and data) is refilled from
external memory. For every detected error, the corresponding counter in the cache control register is incremented. The
counters saturate at their maximum value of three and should be reset by software after reading the fields. The cache
memory check bits can be diagnostically read by setting the PS bit in the cache control register and then performing a
normal tag or data diagnostic read.
2.4.11 Cache configuration registers
The configuration of the two caches is defined in two registers: the instruction and data configuration registers. These registers are read-only and indicate the size and configuration of the caches.
ASI 0x02
Offset 0x08, 0x0C
ICCR, DCCR
31 30 29 28 27 26 25 24 23
CL
--
CP
SN
WAYS
20 19 18
WSIZE
LR
16 15
LSIZE
12 11
LRSZ
4
LRSA
3
MMU
0
RES
Figure 2.10 Cache Configuration Registers
Table 2.13 Description of Cache Configuration Registers
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
CL
0
30
Reserved
DESCRIPTION
Cache Locking
0: Cache locking is not implemented.
Read=0; Write=don’t care.
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Section 2.4: Cache sub-system
Table 2.13 Description of Cache Configuration Registers
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
29-28
CP
01
27
SN
0:(I)
1:(D)
Cache Snooping
0: Snoop disabled
1: Snoop enabled
26-24
WAYS
011
Cache Associativity
011: four-way set associative
Read=011b; Write=don’t care.
23-20
WSIZE
0010
Set Way Size
Indicates the size in KB of each cache way. Size = 2WSIZE
Read=0010b; Write=don’t care.
19
LR
0
18-16
LSIZE
011 (I)
010 (D)
15-12
LRSZ
0
Local Ram Size
Read=0; Write=don’t care.
11-4
LRSA
0
Local Ram Start Address
Read=0; Write=don’t care.
3
MMU
1
MMU Present
0: MMU not present.
1: MMU present.
Read=1; Write=don’t care.
2-0
Reserved
000
Cache Replacement Policy
01: Least recently used (LRU).
Read=01; Write=don’t care.
Local Ram Present
Read=0; Write=don’t care.
Line Size
Indicated the size (words) of each cache line. Line size = 2LSZ
Read=011b for I-cache and 010b for D-cache; Write=don’t care.
All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 0x02.
The table below shows the register addresses. The following assembly instruction shows how to read any of the cache system registers.
lda
%g1, [rr] 2
! load register%g1 with the contents of the
! corresponding cache register
where rr is 0x00, 0x08, or 0x0C. Following this instruction, the contents of the cache register whose address is rr will be
loaded into global register%g1.
2.4.12 Software consideration
After reset, the caches are disabled and the value of cache control register (CCR) is 0. Before the caches may be enabled, a
flush operation must be performed to initialized (clear) the tags and valid bits. A suitable assembly sequence could be:
flush
set
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0x81000F,%g1
! load global register %g1 with 0x0081000F
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Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
Section 2.5: Memory management unit
sta
2.5
%g1, [%g0] 2
! store the contents of %g1 to the CCR
Memory management unit
A memory management unit (MMU) compatible with the SPARC V8 reference MMU can optionally be configured to operate in-line with the cache subsystem. For details on operation, see the SPARC V8 manual.
2.5.1
MMU ASI usage
When the MMU is enabled, the following ASI mappings are added.
Table 2.14 MMU ASI Usage
2.5.2
Address
Register
0x13
MMU flush instruction and data context
0x14
MMU diagnostic dcache context access
0x1E
Separate snoop tags
0x15
MMU diagnostic icache context access (requires that the
instruction cache is disabled)
0x18
Flush TLB and instruction and data cache
0x19
MMU registers
0x1C
MMU bypass
0x1D
MMU diagnostic access
0x1E
MMU snoop tags diagnostic access
Cache operation
When the MMU is disabled, the caches operate normally with physical address mapping. When the MMU is enabled, the
cache tags contain the virtual address and include an 8-bit context field. Because the cache is virtually tagged, no extra
clock cycles are needed in the case of a cache load hit. In the case of a cache miss or store hit (write-through cache) at least
two extra clock cycles are used if there is a translation look-aside buffer (TLB) hit. If there is a TLB miss, the page table must
be traversed, resulting in up to four AMBA read accesses and one possible write-back operation.
2.5.3
MMU registers
The following MMU registers are implemented.
Table 2.15 MMU Registers (ASI = 0x19)
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ADDRESS
REGISTER
0x000
MMU control register
0x100
Context pointer register
0x200
Context register
0x300
Fault status register
0x400
Fault address register
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Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
Section 2.5: Memory management unit
2.5.3.1 MMU Control Register
The MMU control register is located in ASI 0x19 offset 0, and the layout can be seen in Figure 2.11 and Table 2.16.
Offset 0x000
31
30
29
28
27
26
IMPL
15
14
TD
ST
13
25
24
23
VER
12
11
10
22
21
20
ITLB
9
8
7
6
19
18
17
DTLB
5
4
3
16
PSZ
2
RESERVED
1
0
NF
E
Figure 2.11 MMU Control Register
Table 2.16 MMU Control Register
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BIT
NUMBER(S)
BIT
NAME
RESET
STATE
DESCRIPTION
31-28
IMPL
0000
MMU Implementation ID
27-24
VER
0001
MMU Version ID
23-21
ITLB
100
Number of ITLB entries. The number of ITLB entries is
calculated as 2ITLB. If the TLB is shared between instructions and data, this field indicates the total number of
TLBs.
20-18
DTLB
100
Number of DTLB entries. The number of DTLB entries is
calculated as 2DTLB. If the TLB is shared between
instructions and data, this field is zero.
17-16
PSZ
00
Page size. The size of the smallest MMU page. 0 = 4 KB;
1 = 8 KB; 2 = 16 KB; 3 = 32 KB. If the page size is programmable, this field is writable, otherwise it is readonly.
15
TD
0
TLB disable. When set to 1, the TLB will be disabled and
each data access will generate an MMU page table
walk.
14
ST
1
Separate TLB. This bit is set to 1 if separate instruction
and data TLBs are implemented.
13-2
RES
[000...00]
1
NF
0
No Fault. When NF= 0, any fault detected by the MMU
causes FSR and FAR to be updated and causes a fault to
be generated to the processor. When NF= 1, a fault on
an access to ASI 9 is handled as when NF= 0; a fault on
an access to any other ASI causes FSR and FAR to be
updated but no fault is generated to the processor.
0
E
0
Enable MMU. 0 = MMU disabled, 1 = MMU enabled
Reserved for future implementations
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Section 2.5: Memory management unit
2.5.3.2 Context Pointer Register
The MMU context pointer register is located in ASI 0x19 offset 0x100 and the MMU context register is located in ASI 0x19
offset 0x200. They together determine the location of the root page table descriptor for the current context. Their definition follows the SRMMU specification in the SPARC V8 manual.
Offset 0x100
31
2
1
CTP
Figure 2.12 Context Pointer Register
Table 2.17 Control Pointer Register
BIT
NUMBER(S)
BIT
NAME
RESET
STATE
DESCRIPTION
31-2
CTP
[000...00]
1-0
RES
00
Context table pointer, physical address bits 35-6. Note: address is
shifted 4 bits
Reserved, always 0
Offset 0x200
31
8
7
RESERVED
0
31
8
CID
RESERVED
7
0
CID
Figure 2.13 Context ID Register
Table 2.18 Context ID Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-8
RES
[000...00]
Reserved
7-0
CIB
[000...00]
Current context ID
In the LEON3, the context bits are OR:ed with the lower MMU context pointer bits when calculating the address, so one
can use less context bits to reduce the size/alignment requirements for the context table. MMU fault status register.
2.5.3.3 Fault Status Register
The MMU fault status register is located in ASI 0x19 offset 0x300, and the definition follows the SRMMU specification in the
SPARC V8 manual. The SPARC V8 specifies that the fault status register should be cleared on read, on the LEON3 only the
FAV bit is cleared on read. The FAV bit is always set on error in the LEON3 implementation, so it can be used as a valid bit for
the other fields.
RegisterName
Offset 0x300
31
18
RESERVED
17
16
EBE
Figure 2.14 Fault Status Register
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Section 2.5: Memory management unit
15
10
9
EBE
8
7
L
5
4
AT
2
FT
1
0
FAV
OW
Figure 2.14 Fault Status Register
Table 2.19 Fault Status Register
BIT
NUMBER(S)
BIT NAME
RESET STATE
DESCRIPTION
31-8
RES
[000...00]
Reserved
17-10
EBE
[000...00]
External bus error (EBE). Never set on the LEON3.
9-8
L
00
Level (L) - Level of page table entry causing the fault
7-5
AT
000
Access type (AT) - See V8 standard
4-2
FT
000
Fault type (FT) - See table Figure 2.20
1
FAV
0
Fault address valid (FAV) - cleared on read, always written to 1 on
fault
0
W
0
Overview (W) - multiple faults of the same priority encountered
Table 2.20 Fault Type
FT
Fault Type
0
None
1
Invalid Address Error
2
Protection Error
3
Priviledge Violation Error
4
Translation Error
5
Access Bus Error
6
Internal Error
7
Reserved
2.5.3.4 Fault Address Register
The MMU context pointer register is located in ASI 0x19 offset 0x100, and the definition follows the SRMMU specification
in the SPARC V8 manual.
Offset 0x400
31
12 11
FA
0
Reserved
Figure 2.15 Fault Address Register
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Chapter 2: LEON 3FT SPARC V8 32-bit Microprocessor
Section 2.6: LEON3FT Storage Allocation
Table 2.21 Fault Address Register
2.5.4
BIT
NUMBER(S)
BIT NAME
RESET STATE
DESCRIPTION
31-12
FA
[000...00]
Top bits of virtual address causing translation fault
11-0
RES
[000...00]
Reserved, always 0
Translation Look-Aside Buffer (TLB)
The MMU is configured to use a separate TLB for instructions and data. The number of entries are eight for instructions and
eight for data. The organization of the TLB and number of entries is not visible to the software and does not require any
modification to the operating system.
2.6
LEON3FT Storage Allocation
2.6.1
Integer unit register file
The integer Unit register file has one write port and two read ports, all 32 bit wide. The register file is protected with RAM
flip-flop blocks in a TMR configuration.
2.6.2
Floating Point Unit (FPU) register file
The FPU register file is protected with SEU hardened flip-flops.
2.6.3
Cache memories
The following sections detail how cache information is stored in physical memory.
2.6.3.1 Instruction cache tags
The instruction tags are made up by 8 valid bits, 20 tag address bits, eight MMU context bits and four parity bits. A total of
40 bits are dedicated to each Instruction Cache line. There are a total of 128 instruction tags. Instruction cache tags have
the following allocation.
Table 2.22 Instruction Cache Tags
BITS
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USAGE
47-39
Unused and tied to ground
38-35
Parity
Bit 38: XOR [35:20]
Bit 37: XOR [19:12]
Bit 36: XOR [11:8]
Bit 35: XOR [7:0]
34-27
MMU context
26-8
Tag address
7-0
Valid
0: Word not valid
1: Word valid
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Section 2.6: LEON3FT Storage Allocation
2.6.3.2 Data cache tags
The data tags are made of one valid bit, 20 tag address bits, eight MMU context bits and four parity bits. A total of 33 bits
are dedicated for each Data Cache line. There are a total of 256 data tags. Data cache tags have the following allocation.
Table 2.23 Data Cache Tags
BITS
USAGE
35-33
Unused and tied to ground
32-29
Parity
Bit 39: XOR [28:13]
Bit 38: XOR [12:5]
Bit 30: XOR [4:1]
Bit 29: XOR [0]
28-21
MMU context
20-1
Tag address
0
Valid
0: Word not vaid
1: Word valid
2.6.3.3 Data snoop tags
The data snoop tags are made up by 20 tag address bits and one parity bit. A total of 21 bits are dedicated for each data
snoop line. The bits are located as follows: tag address [19:0], parity [20].
2.6.3.4 Instruction and data cache data memory
The data part of the instruction and data caches consist of 32-data bits and four parity bits. The bits are allocated as follows:
Table 2.24 Instruction and Data Cache Memory
BITS
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USAGE
39-36
Unused and tied to ground
35-32
Parity
Bit 35: XOR [31:24]
Bit 34: XOR [23:16]
Bit 33: XOR [15:8]
Bit 32: XOR [7:0]
31-0
Data
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Chapter 3: Memory Controller with EDAC
Section 3.1: Overview
Chapter 3: Memory Controller with EDAC
3.1
Overview
The memory controller provides a bridge between external memory and the AHB bus. The memory controller handles
four types of devices: PROM, Asynchronous Static Ram (SRAM), Synchronous Dynamic Ram (SDRAM) and memory
mapped Input/Output (I/O) devices. The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39,7) BCH code.
The EDAC provides single-error correction and double-error detection for each 32-bit memory word.
The SDRAM area can optionally also be protected using Reed-Solomon coding. In this case, a 16-bit checksum is used for
each 32-bit word and any two adjacent 4-bit (nibble) errors can be corrected.
The memory controller is configured through three configuration registers accessible via an APB bus interface. The external data bus can be configured in 8, 16, or 32-bit mode depending on application requirements. The controller decodes
three address spaces on the AHB bus (PROM, I/O, and SRAM/SDRAM).
External chip-selects are provided for two PROM banks, one I/O bank, five SRAM banks and two SDRAM banks. In Figure
3.1 below shows the notional connection to the different device types is made.
APB
A
AHB
APB
ROMS[1:0]
OE
WRITE
Read
CS
OE
WE
Read
IOS
CS
OE
WE
Read
FTMCTRL
BRDY
AHB
PROM
I/O
D
CB
A
D
CB
A
D
EXT. CONT. LOGIC
RAMS[4:0]
RAMOE[4:0]
RWE[3:0]
CS
OE
WE
Read
SDCS[1:0]
SDRAS
SDCAS
SDWE
SDDQM[3:0]
CSN
RAS
CAS
WE
DQM
SRAM
SDRAM
A
D
CB
A
D
CB
ADDR[27:0]
DATA[31:0]
CB[15:0]
Figure 3.1 FTMCTRL Connected to Different Types of Memory Devices
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Section 3.2: PROM access
3.2
PROM access
Two PROM chip-select signals are provided for the PROM area: ROMS[1:0]. ROMS[0] is asserted when the lower half of the
PROM area are addressed while ROMS [1] is asserted for the upper half. The size of the banks can be set in binary steps
from 16 KB to 256 MB.
A read access to PROM consists of two data cycles and between 0 and 30 waitstates. The read data (and optional EDAC
check-bits CB[15:0]) are latched on the rising edge of the clock on the last data cycle. On non-consecutive accesses, a leadout cycle is added after a read cycle to prevent bus contention due to slow turn-off time of PROM devices. See Section 3.16
for timing diagram examples of PROM accesses.
3.3
Memory mapped I/O
Accesses to I/O have similar timing to the PROM accesses. The I/O select (IOS) and output enable (OE) signals are delayed
one clock to allow for a stable address before it is asserted. See Section 3.16 for timing diagram examples of I/O accesses.
3.4
3.4 SRAM access
The SRAM area is divided on up to five RAM banks. The size of banks 1-4 (RAMS[3:0]) is programmed in the RAM bank-size
field (MCFG2[12:9]) and can be set in binary steps from 8 Kbyte to 256 Mbyte. The fifth bank (RAMS[4]) decodes the upper
512 Mbyte. A read access to SRAM consists of two data cycles and between zero and three waitstates. The read data (and
optional EDAC check-bits CB[15:0]) are latched on the rising edge of the clock on the last data cycle. Accesses to RAMS[4]
can further be stretched by de-asserting BRDY until the data is available. On non-consecutive accesses, a lead-out cycle is
added after a read cycle to prevent bus contention due to slow turn-off time of memories. See Section 3.16 for timing diagram examples of SRAM accesses.
For read accesses to RAMS[4:0], a separate output enable signal (RAMOE[n]) is provided for each RAM bank and only
asserted when that bank is selected. A write access is similar to the read access, but takes a minimum of three cycles.
Each byte lane has an individual write strobe to allow efficient byte and half-word writes. If the memory uses a common
write strobe for the full 16 or 32-bit data, the read-modify-write bit MCFG2 should be set to enable read-modify-write
cycles for sub-word writes. See Section 3.16 for timing diagram examples of SRAM accesses.
3.5
8-bit and 16-bit PROM and SRAM access
To support applications with low memory and performance requirements efficiently, the SRAM and PROM areas can be
individually configured for 8-bit or 16-bit operation by programming the ROM and RAM size fields in the memory configuration registers. Since read access to memory is always done on 32-bit word basis, read access to 8-bit memory is transformed in a burst of four read cycles while access to 16-bit memory generates a burst of two 16-bits reads. During writes,
only the necessary bytes will be writen. The following figures show interface examples with 8-bit, 16-bit, and 32-bit PROM
and SRAM. 3.3
The RMW bit in MCFG2 must not be set if RAM EDAC is disabled when RAM width is set to 8-bit.
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Section 3.5: 8-bit and 16-bit PROM and SRAM access
8-bit PROM
ROMS[0]
OE
WRITE
CS
OE
WE
MEMORY
CONTROLLER
RAMS[0]
RAMOE[0]
RWE[0]
A
PROM
D
A
D
A[25:0]
D[31:24]
8-bit RAM
CS
OE
WE
A
SRAM
D
A[25:0]
D[31:24]
ADDR[27:0]
DATA[31:24]
Figure 3.2 8-bit Memory Interface Example
16-bit PROM
ROMS[0]
OE
WRITE
CS
OE
WE
MEMORY
CONTROLLER
RAMS[0]
RAMOE[0]
RWE[1:0]
PROM
A
D
A
D
A[26:1]
D[31:16]
16-bit RAM
CS
OE
WE
SRAM
A
D
A[26:1]
D[31:16]
ADDR[27:0]
DATA[31:16]
Figure 3.3 16-bit Memory Interface Example
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Section 3.6: 8-bit I/O access and 16-bit I/O access
32-bit PROM
ROMS[0]
OE
WRITE
CS
OE
WE
MEMORY
CONTROLLER
PROM
A
D
A[27:2]
A
D
D[31:0]
CB[9:0]
32-bit RAM
CS
OE
WE
RAMS[4:0]
RAMOE[4:0]
RWE[3:0]
A
SRAM
D
A[27:2]
D[31:0]
CB[7:0]
ADDR[27:0]
DATA[31:0]
Figure 3.4 32-bit Memory Interface Example
In 8-bit mode, the PROM/SRAM devices should be connected to the data bus DATA[31:24]. The LSB address bus should be
used for addressing (ADDR[25:0]). In 16-bit mode, DATA[31:16] should be used as data bus and ADDR[26:1] as address bus.
EDAC protection is not available in 16-bit mode.
3.6
8-bit I/O access and 16-bit I/O access
Similar to the PROM/SRAM areas, the I/O area can also be configured to 8-bit or 16-bit mode. However, the I/O device will
not be accessed by multiple 8/16 bit accesses as the memory areas, but only with one single access just as in 32-bit mode.
To access an I/O device on an 8-bit bus, LDUB/STB instructions should be used. To access an I/O device on a 16-bit bus,
LDUH/STH instructions should be used.
3.7
Burst cycles
To improve the bandwidth of the memory bus, accesses to consecutive addresses can be performed in burst mode. Burst
transfers will be generated when the memory controller is accessed using an AHB burst request. These include instruction
cache-line fills, double loads and double stores. The timing of a burst cycle is identical to the programmed basic cycle with
the exception that during read cycles, the lead-out cycle will only occur after the last transfer. Burst cycles will not be generated to the I/O area.
3.8
SDRAM access
3.8.1
General
Synchronous Dynamic RAM (SDRAM) access is supported to two banks of PC100/PC133 compatible devices. The SDRAM
controller supports 64 MB, 256 MB and 512MB devices with 8-12 column-address bits and up to 13 row-address bits. The
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Chapter 3: Memory Controller with EDAC
Section 3.9: Refresh
size of the two banks can be programmed in binary steps between 4 Mbyte and 512 Mbyte. The SDRAM controller operation is controlled through MCFG2 and MCFG3. A 32-bit data bus width is supported that can interface a 64-bit DIMM modules. The memory controller can be configured to use either a shared or separate bus connecting the controller and
SDRAM devices. See Section 3.17 for timing diagram examples of SDRAM accesses.
3.8.2
Address mapping
Two SDRAM chip-select signals are used for address decoding. SDRAM is memory mapped into the upper half of the RAM
area (0x60000000+) by setting the DE bit to 1 and SI bit to 0 in memory configuration Register 2 (MCFG2). SDRAM is memory mapped into the lower half of the RAM area (0x40000000+) by setting the DE bit to 1 and SI bit to 1 in the MCFG2 register.
3.8.3
Initialization
When the SDRAM controller is enabled, it automatically performs the SDRAM initialization sequence of one PRECHARGE
command, eight AUTO-REFRESH command and LOAD-MODE-REG command on both banks simultaneously. The controller programs the SDRAM to use page burst on read and single location access on write.
3.8.4
Configurable SDRAM timing parameters
To provide optimum access cycles for different SDRAM devices (and at different frequencies), three SDRAM parameters can
be programmed via MCGF2: TCAS, TRP and TRFC. The value of these field affects the SDRAM timing as described in Table
3.1.
Table 3.1 SDRAM Programmable Minimum Timing Parameters
SDRAM TIMING PARAMETER
MINIMUM TIMING CLOCKS
CAS latency, RAS/CAS delay (tCAS, tRCD)
TCAS + 2
Precharge to activate (tRP)
TRP + 2
Auto-refresh command period (tRFC)
TRFC + 3
Activate to precharge (tRAS)
TRFC + 1
Activate to Activate (tRC)
TRP + TRFC + 4
If the TCAS, TRP and TRFC are programmed such that the PC100/133 specifications are fulfilled, the remaining SDRAM timing parameters will also be met. The table below shows typical settings for 100 and 133 MHz operation and the resulting
SDRAM timing (in ns).
Table 3.2 SDRAM Example Programming
3.9
SDRAM SETTINGS
tCAS
tRC
tRP
tRFC
tRAS
100 MHz, CL=2; TRP=0, TCAS=0, TRFC=4
20
80
20
70
50
100 MHz, CL=3; TRP=0, TCAS=1, TRFC=4
30
80
20
70
50
133 MHz, CL=2; TRP=1, TCAS=0, TRFC=6
15
82
22
67
52
133 MHz, CL=3; TRP=1, TCAS=1, TRFC=6
22
82
22
67
52
Refresh
The SDRAM controller contains a refresh function that periodically issues an AUTO-REFRESH command to both SDRAM
banks. The period between the commands (in clock periods) is programmed in the refresh counter reload field in the
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Section 3.10: Memory EDAC
MCFG3 register. Depending on SDRAM type, the required period is typically 7.8 or 15.6 ms (corresponding to 780 or 1560
clocks at 100 MHz). The generated refresh period is calculated as ((reload value)+1)/sysclk. The refresh function is enabled
by setting bit 31 in MCFG2.
3.9.1
SDRAM commands
The controller can issue three SDRAM commands by writing to the SDRAM command field in MCFG2: PRE-CHARGE, AUTOREFRESH and LOAD-MODE-REG (LMR). If the LMR command is issued, the CAS delay as programmed in MCFG2 will be used
and remaining fields are fixed: page read burst, single location write, sequential burst. The command field clears after a
command has been executed. When changing the value of the CAS delay, a LOAD-MODE-REGISTER command should be
generated at the same time. Note: When issuing SDRAM commands, the SDRAM refresh must be disabled.
3.9.2
Read cycles
A read cycle is started by performing an ACTIVATE command to the desired bank and row, followed by a READ command
after the programmed CAS delay. A read burst is performed if a burst access has been requested on the AHB bus. The read
cycle is terminated with a PRE-CHARGE command, no banks are left open between two accesses.
3.9.3
Write cycles
Write cycles are performed similarly to read cycles, but WRITE commands are issued after activation. A write burst on the
AHB bus generates a burst of write commands without idle cycles in-between.
3.9.4
Address bus
The memory controller uses a common address bus for Prom, I/O, SRAM and SDRAM. SDRAM connected to the address
bus should use ADDR[14:2] for the row select and ADDR[16:15] for the bank select.
3.9.5
Data bus
The memory controller uses a common address bus for Prom, I/O, SRAM and SDRAM. The SDRAM uses a 32-bit data bus
and can access a 64-bit SDRAM at half the data capacity.
3.9.6
Clocking
The SDRAM memory is clocked by the SDCLK output. This output is in phase with the internal system clock and provides
the maximum margin for setup and hold on the external signals. The SDCLK output will be available as long as the system
clock is operating.
3.9.7
Initialization
Each time the SDRAM is enabled (by setting bit 14 in MCFG2), an SDRAM initialization sequence will be sent to both
SDRAM banks. The sequence consists of one PRECHARGE command, eight AUTO-REFRESH command and one LOAD-COMMAND-REGISTER command.
3.10 Memory EDAC
3.10.1 BCH EDAC
The FTMCTRL is provided with an error detected and correction (EDAC) controller that can correct one error and detect
two errors in a 32-bit word. For each word, a 7-bit checksum is generated according to the equations below. A correctable
error will be handled transparently by the memory controller, but will add one waitstate to the access. If an un-correctable
error (double-error) is detected, the current AHB cycle will end with an error response. The EDAC can be used during
access to PROM, SRAM and SDRAM areas by setting the corresponding EDAC enable bits in the MCFG3 register. The equations below show how the EDAC checkbits are generated:
CB0 = D0 ^ D4 ^ D6 ^ D7 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31
CB1 = D0 ^ D1 ^ D2 ^ D4 ^ D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28
CB2 = D0 ^ D3 ^ D4 ^ D7 ^ D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31
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Chapter 3: Memory Controller with EDAC
Section 3.10: Memory EDAC
CB3 = D0 ^ D1 ^ D5 ^ D6 ^ D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29
CB4 = D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31
CB5 = D8 ^ D9 ^ D10 ^ D11 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
CB6 = D0 ^ D1 ^ D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
If the memory is configured in 8-bit mode, the EDAC checkbit bus (CB[7:0]) is not used, but it is still possible to use EDAC
protection. This is done by allocating the top 20% of the memory bank to the EDAC checksums. If the EDAC is enabled, a
read access reads the data bytes from the nominal address and the EDAC checksum from the top part of the bank. A write
cycle is performed the same way. In this way, 80% of the bank memory is available as program or data memory while the
top 20% is used for check bits. The size of the memory bank is determined from the settings in MCFG1 and MCFG2. The
EDAC cannot be used on memory areas configured in 16-bit mode.
The operation of the EDAC can be tested trough the MCFG3 register. If the WB (write bypass) bit is set, the value in the TCB
field replaces the normal checkbits during memory write cycles. If the RB (read bypass) is set, the memory checkbits of the
loaded data will be stored in the TCB field during memory read cycles.
Note: When the EDAC is enabled, the RMW bit in memory configuration register 2 must be set.
3.10.2 Reed-Solomon EDAC
The Reed-Solomon EDAC provides block error correction and is capable of correcting up to two 4-bit nibble errors in a 32bit data word or 16-bit checksum. The Reed-Solomon EDAC can be enabled for the SDRAM area only and uses a 16-bit
checksum. Operation and timing is identical to the BCH EDAC with the pipeline option enabled. The Reed-Solomon EDAC
is enabled by setting the RSE and RE bits in MCFG3 and the RMW bit in MCFG2.
The Reed-Solomon data symbols are 4-bit wide, represented as GF(2^4). The basic Reed-Solomon code is a shortened
RS(15, 13, 2) code, represented as RS(6, 4, 2). It has the capability to detect and correct a single symbol error anywhere in
the codeword. The EDAC implements an interleaved RS(6, 4, 2) code where the overall data is represented as 32 bits and
the overall checksum is represented as 16 bits. The codewords are interleaved nibble-wise. The interleaved code can correct two 4-bit errors when each error is located in a nibble and not in the same original RS(6, 4, 2) codeword.
The Reed-Solomon RS(15, 13, 2) code has the following definition:
•
•
•
•
•
there are 4 bits per symbol;
there are 15 symbols per codeword;
the code is systematic;
the code can correct one symbol error per codeword;
the field polynomial is
4
f(x) = x + x + 1
• the code generator polynomial is
g( x) =
1
2
i
∏ (x + α )
i=0
=
 gj ⋅ x
j
j=0
for which the highest power of x is stored first;
• a codeword is defined as 15 symbols:
• c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14
• where c0 to c12 represent information symbols and c13 to c14 represent check symbols.
The shortened and interleaved RS(6, 4, 2) code has the following definition:
• the codeword length is shortened to 4 information symbols and 2 check symbols and as follows:
c0 = c1 = c2 = c3 = c4 = c5 = c6 = c7 = c8 = 0
where the above information symbols are suppressed or virtually filled with zeros;
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Section 3.11: Using BRDY
• two codewords are interleaved (i.e. interleaved depth I=2) with the following mapping to the 32-bit data and 16-bit
checksum, were ci,j is a symbol with codeword index i and symbol index j:
c0,9 = DATA[31:28]
c1,9 = DATA[27:24]
c0,10 = DATA[23:20]
c1,10 = DATA[19:16]
c0,11 = DATA[15:12]
c1,11 = DATA[11:8]
c0,12 = DATA[7:4]
c1,12 = DATA[3:0]
c0,13 = CB[15:12]
c1,13 = CB[11:8]
c0,14 = CB[7:4]
c1,14 = CB[3:0]
Note: The Reed-Solomon EDAC is not supported for 64-bit wide SDRAM buses.
3.10.3 EDAC Error reporting
An un-correctable EDAC error results in an AHB error response. The initiating AHB master will be notified of the error and
take corresponding action. If the master was the LEON3FT processor, an instruction or data error strap will be taken (see
section 2). The AHB error response will also be registered in the AHB status register. Correctable EDAC errors are handled
transparently and are not visible on the AHB bus. They are registered in the AHB status register through the use of a sideband signal. This can be used for providing an external scrubbing mechanism and/or error statistics. The correctable error
signal is connected to the AHB status register which monitors the correctable error signal and error responses on the bus.
Please see the AHB status register section for more information.
3.11 Using BRDY
The BRDY signal can be used to stretch access cycles to the PROM and I/O areas and the SRAM area decoded by RAMS[4].
The accesses will always have at least the pre-programmed number of waitstates as defined in registers MCFG1 and
MCFG2, but will be further stretched until BRDY is asserted. BRDY should be asserted in the cycle preceding the last one. If
bit 29 in MCFG1 is set, BRDY can be asserted asynchronously with the system clock. In this case, the read data must be kept
stable until the de-assertion of OE/RAMOE. BRDY must be asserted for at least 1.5 clock cycles. The use of BRDY can be
enabled separately for the PROM, I/O and RAMS[4] areas. It is recommended that BRDYN remain asserted until the corresponding chip select signal is de-asserted to ensure that the access has been properly completed and to avoid a datapath
stall. See Section 3.16 for timing diagram examples with BRDY.
3.12 Access errors
An access error can be signaled by asserting the BEXC signal which is sampled together with the data. If the usage of BEXC
is enabled in register MCFG1, an error response will be generated on the internal AHB bus. BEXC can be enabled or disabled through register MCFG1 and is active for all areas (PROM, I/O an RAM). For writes, it is sampled on the last rising edge
before chip select is de-asserted which is controlled by means of waitstates or bus ready signaling. BEXC is only sampled in
the last access for 8-bit mode for RAM and PROM. When four bytes are written for a word access to 8-bit wide memory
BEXC is only sampled in the last access with the same timing as a single access in 32-bit mode. See Section 3.16 for timing
diagram examples using BEXC.
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Chapter 3: Memory Controller with EDAC
Section 3.13: Attaching an external DRAM controller
3.13 Attaching an external DRAM controller
To attach an external DRAM controller, RAMS[4] should be used since it allows the cycle time to vary through the use of
BRDY. In this way, delays can be inserted as required for opening of banks and refresh.
3.14 Registers
The core is programmed through registers mapped into APB address space.
Table 3.3 FTMCTRL Memory Controller Registers
REGISTER
APB ADDRESS
Memory configuration register 1 (MCFG1)
0x80000000
Memory configuration register 2 (MCFG2)
0x80000004
Memory configuration register 3 (MCFG3)
0x80000008
Memory configuration register 4 (MCFG4)
0x8000000C
3.14.1 Memory configuration register 1 (MCFG1)
Memory configuration register 1 is used to program the timing of ROM and I/O accesses.
MCFG1
Address = 0x80000000
31 30 29 28 27 26 25 24 23
- -
PB AB
IW
IB
BE
--
20 19 18 17
IW
IE
--
14 13 12 11 10
PZ
---
PE
--
9
8
PD
7
4
3
PW
0
PR
Figure 3.5 Memory Configuration Register 1
Table 3.4 Description of Memory Configuration Register 1
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
Reserved
0
30
PB
0
PROM area bus enable
0: BRDY disabled for PROM area.
1: BRDY enabled for PROM area.
29
AB
0
Asynchronous bus ready
0: BRDY is synchronous relative to system clock.
1: BRDY input can be asserted without relation to the system
clock.
28-27
IW
_
I/O data bus width
00: 8 bits
01: 16 bits
10: 32 bits
11: Not used
26
IB
0
I/O area bus ready enable
0: BRDY disabled for I/O area.
1: BRDY enabled for I/O area.
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Section 3.14: Registers
Table 3.4 Description of Memory Configuration Register 1
BIT
NUMBER(S)
BIT NAME
RESET
STATE
25
BE
0
24
Reserved
0
23-20
IW
0000
19
IE
0
18
Reserved
0
17-14
PZ
0000
13-12
Reserved
00
11
PE
0
10
Reserved
9-8
PD
GPIO
[1:0]
Data width of the PROM area
PWIDTH is set to the value GPIO[1:0] following a reset.
00: 8 bits
01: 16 bits
10: 32 bits
11: Not used
7-4
PW
1111
Number of waitstates during PROM write cycles
PWS is set to the maximum value of 15 which equals 30 waitstates following a reset.
0000: 0
0001: 2
0010: 4
...
1111: 30
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Bus error enable
0: BEXC disabled
1: BEXC enabled
Number of waitstates during I/O accesses
0000: 0 waitstates
0001: 1 waitstates
0010: 2 waitstates
...
1111: 15 waitstates
I/O enable
0: Access to memory mapped I/O space is disabled
1: Access to memory mapped I/O space is enabled
PROM size is fixed at 256MB
PROM write enable
0: PROM write cycles disabled
1: PROM write cycles enabled
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Chapter 3: Memory Controller with EDAC
Section 3.14: Registers
Table 3.4 Description of Memory Configuration Register 1
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
3-0
PR
1111
Number of waitstates during PROM read cycles
PRS is set to the maximum value of 15 which equals 30 waitstates
following a reset.
0000: 0
0001: 2
0010: 4
...
1111: 30
3.14.2 Memory configuration register 2 (MCFG2)
Memory configuration register 2 is used to control the timing of the SRAM and SDRAM.
MCFG2
Address = 0x80000004
31 30 29
DR DP
27 26 25
DF
DC
23 22 21 20 19
DZ
DS
DD
18 17 16 15 14 13 12
BW PB
--
DE
SI
9
SZ
8
--
7
6
5
SB RM
4
SD
3
2
SW
1
0
SR
Figure 3.6 Memory Configuration Register 2
Table 3.5 Description of Memory Configuration Register 2
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
DR
0
SDRAM refresh
0: SDRAM refresh disable
1: SDRAM refresh enabled
30
DP
1
SDRAM TRP parameter
0: tRP = 2 system clocks
1: tRP = 3 system clocks
29-27
DF
111
26
DC
1
25-23
DZ
000
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SDRAM TRFC parameter
tRFC = 3 + DF system clocks
SDRAM CAS parameter
When changed, a LOAD-COMMAND-REGISTER command must be
issued at the same time and also sets RAS/CAS delay (tRCD).
0: CAS = 2 cycle delay
1: CAS = 3 cycle delay
Bank size for SDRAM chip selects defined as 4MB*2DZ
000: 4MB
001: 8MB
010: 16MB
...
111: 512MB
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Section 3.14: Registers
Table 3.5 Description of Memory Configuration Register 2
BIT
NUMBER(S)
BIT NAME
RESET
STATE
22-21
DS
10
SDRAM column size is 2048 when bits [25:23] = 111
Otherwise, the column size is defined as:
00: 256
01: 512
10: 1024
11: 4096
20-19
DD
00
SDRAM command
Writing a non-zero value generates an SDRAM command. The
field is reset to 00b after command has been executed.
01: PRECHARGE
10: AUTO-REFRESH
11: LOAD-COMMAND-REGISTER
18
BW
0
Memory controller data bus width.
0: 32-bit
1: 64-bit
Read=0; Write=don’t care.
17
PB
0
SDRAM Page Burst
0: Line burst of length 8 bytes for read operations
1: Page burst is used for read operations
16-15
Reserved
00
14
DE
0
SDRAM enable
0: SDRAM controller disabled
1: SDRAM controller enabled
13
SI
0
SRAM disable
If set together with bit 14 the SRAM will be disabled.
DE=0
x: SRAM enabled
DE=1
0: SRAM enabled
1: SRAM disabled
x=don’t care
12-9
SZ
----
8
Reserved
0
7
SB
0
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Size of each SRAM bank as 8*2SZ KB
0000: 8KB
0001: 16KB
0010: 32KB
...
1111: 256MB
SRAM area bus ready enable
0: BRDY disabled for SRAM area
1: BRDY enabled for SRAM area
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Section 3.14: Registers
Table 3.5 Description of Memory Configuration Register 2
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
6
RM
-
Enable read-modify-write cycles on sub-word writes to 16- and
32-bit areas with common write strobe (no byte write strobe).
0: Disabled
1: Enabled
5-4
SD
--
Data width of the SRAM area
00: 8
01: 16
1x: 32
x=don’t care
3-2
SW
00
Number of waitstates during SRAM write cycles
00: 0
01: 1
10: 2
11: 3
1-0
SR
00
Number of waitstates during SRAM read cycles
00: 0
01: 1
10: 2
11: 3
3.14.3 Memory configuration register 3
MCFG3 is contains the reload value for the SDRAM refresh counter and to control and monitor the memory EDAC. It also
contains the configuration of the register file EDAC.
MCFG3
Address = 0x80000008
31 30 29
28
Reserved
RSE
27 26
11
ME
RLDVAL
10 9
8
WB RB SE PE
7
TCB [7:0]
Figure 3.7 Memory Configuration Register 3
Table 3.6 Description of Memory Configuration Register 3
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-29
Reserved
000
28
RSE
0
Reed-Solomon EDAC
0: BCH EDAC available for SDRAM
1: Reed-Solomon EDAC available for SDRAM
27
ME
1
Memory EDAC
Indicates if memory EDAC is present
Read = 1; Write = Don’t care
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Chapter 3: Memory Controller with EDAC
Section 3.14: Registers
Table 3.6 Description of Memory Configuration Register 3
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
26-12
RLDVAL
[- -...-]
SDRAM refresh counter reload value
The period between each AUTO-REFRESH command is calculated
as follows:
tREFRESH = (RLDVAL + 1) / SYS_CLK
11
WB
0
EDAC diagnostic write bypass
0: Normal operation
1: EDAC write bypassed
10
RB
0
EDAC diagnostic read bypass
0: Normal operation
1: EDAC read bypassed
9
SE
-
Enable EDAC checking of the SDRAM or SRAM area
0: EDAC checking of the RAM area disabled
1: EDAC checking of the RAM area enabled
8
PE
GPIO
[2]
Enable EDAC checking of the PROM area
At reset, this bit is initialized with the value GPIO[2].
0: EDAC checking of the PROM area disabled
1: EDAC checking of the PROM area enabled
7-0
TCB[7:0]
[- -...-]
Test checkbits
This field replaces the normal checkbits during store cycles when
WB (bit 11) is set. TCB is also loaded with the memory checkbits
during load cycles when RB (bit 10) is set.
3.14.4 Memory Configuration Register 4
MCFG4 provides the means to insert Reed-Soloman EDAC errors into memory for diagnostic purposes.
MCFG4
Address = 8000000C
31
17 16 31
RESERVED
WB
15
0
17 16
RESERVED
15
WB
0
ACTB[15:0]
ACTB[15:0]
Figure 3.8 Memory Configuration Register 4
Table 3.7 Description of Memory Configuration Register 4
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NUMBER(S)
BIT NAME
RESET
STATE
31-17
Reserved
0
DESCRIPTION
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Chapter 3: Memory Controller with EDAC
Section 3.15: Boot strap configuration
Table 3.7 Description of Memory Configuration Register 4
BIT
NUMBER(S)
16
15-0
BIT NAME
RESET
STATE
WB
0
RTCB[15:0]
[- -...-]
DESCRIPTION
Reed Soloman EDAC diagnostics write bypass
0: Normal
1: EDAC write bypasses
Reed Soloman test checkbits
This field replaces the normal check bits during write
cycles when WB is set.
3.15 Boot strap configuration
Upon power up or external RESET, GPIO[2] is configured as an input and a high logic level seen on this pin when RESET
goes high configures the PROM to operate with EDAC enable. Upon power up or external RESET, GPIO[1:0] are configured
as an inputs and the following logic level combinations on each pin when RESET goes high configures the PROM data
width:
Table 3.8 Logic Leevel Combinations
GPIO[1:0]
PROM Data width
00
8-bit
01
16-bit
10
32-bit
3.16 PROM, SRAM, and memory mapped I/O timing diagrams
This section shows typical timing diagrams for PROM, SRAM and I/O accesses. These timing diagrams are functional, and
are intended to show the relationship between control signals and SDCLK. The actual values of the timing parameters can
be found in Chapter 4 of the UT700 datasheet.
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Chapter 3: Memory Controller with EDAC
Section 3.16: PROM, SRAM, and memory mapped I/O timing diagrams
Data1
Data2
Lead-Out
Lead-Out
SDCLK
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
ROMS[1:0]
RAMS[4:0]
OE
RAMOE[4:0]
READ
WRITE
RWE[3:0]
ADDR[27:2]
t6
t6
t5
t5
DATA[31:0]
t6
t6
t5
t5
CB[7:0]
t6
t5
BEXC
Figure 3.9 PROM and SRAM 32-bit Read
Data1
Data2
Lead-Out
SDCLK
t1
t1
t1
t1
ROMS[1:0]
RAMS[4:0]
OE
RAMOE[4:0]
t1
READ
WRITE
RWE[3:0]
t1
t1
ADDR[27:2]
t6
t6
t5
t5
DATA[31:0]
t6
t6
t5
t5
CB[7:0]
Figure 3.10 PROM and SRAM 32-bit Read Cycle Consecutive
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Section 3.16: PROM, SRAM, and memory mapped I/O timing diagrams
Data
nWS
BRDY
Lead-Out
SDCLK
t1
t1
t1
t1
ROMS[1:0]
RAMS[4:0]
OE
RAMOE[4:0]
t1
READ
WRITE
RWE[3:0]
t1
t1
ADDR[27:2]
t6
t5
BRDY
t6
t5
DATA[31:0]
t6
t5
CB[7:0]
Figure 3.11 PROM and SRAM 32-bit Read Cycle with Wait States and BRDY
Data
nWS
BRDY
Lead-Out
SDCLK
t1
t1
t1
t1
ROMS[1:0]
RAMS[4:0]
OE
RAMOE[4:0]
t1
READ
WRITE
RWE[3:0]
t1
t1
ADDR[27:2]
t7
BRDY
t6
t5
DATA[31:0]
t6
t5
CB[7:0]
Figure 3.12 PROM and SRAM 32-bit Read Cycle Wait States and Asynchronous BRDY
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Section 3.16: PROM, SRAM, and memory mapped I/O timing diagrams
Data1
Data2
Lead-Out
Lead-Out
SDCLK
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
ROMS[1:0]
RAMS[4:0]
OE
RAMOE[4:0]
READ
WRITE
RWE[3:0]
ADDR[27:1]
t6
t6
t5
t5
DATA[31:16]
t6
t6
t5
t5
CB[7:0]
Figure 3.13 PROM and SRAM 16-bit Read Cycle
Data1
Data2
Data3
Lead-Out
Data4
Lead-Out
Lead-Out
Lead-Out
SDCLK
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
ROMS[1:0]
RAMS[4:0]
OE
RAMOE[4:0]
READ
WRITE
RWE[3:0]
ADDR[27:0]
t6
t5
t6
t5
t6
t6
t5
t5
DATA[31:24]
Figure 3.14 PROM and SRAM 16-bit Read Cycle
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Section 3.16: PROM, SRAM, and memory mapped I/O timing diagrams
Data
Lead-In
Lead-Out
t1
t1
SDCLK
ROMS[1:0]
RAMS[4:0]
OE
RAMOE[4:0]
t1
t1
READ
t1
t1
WRITE
RWE[3:0]
t1
t1
ADDR[27:2]
t2
t3
t2
t3
DATA[31:0]
CB[7:0]
Figure 3.15 PROM and SRAM 32-bit Write Cycle on a 32-bit Bus
Data
Data
Lead-In
Lead-Out
Lead-In
Lead-Out
t1
t1
t1
t1
SDCLK
ROMS[1:0]
RAMS[4:0]
OE
RAMOE[4:0]
t1
t1
t1
t1
READ
t1
t1
t1
t1
WRITE
RWE[1:0]
t1
t1
t1
t1
*
ADDR[27:1]
t2
t3
t2
t3
t2
t3
t2
t3
*
DATA[31:16]
CB[7:0]
Figure 3.16 PROM and SRAM 16-bit Write Cycle on a 16-bit Bus
* ADDR[27:0] and DATA[31:24] and RWE[0] are used for 8-bit bus architecture.
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Chapter 3: Memory Controller with EDAC
Section 3.16: PROM, SRAM, and memory mapped I/O timing diagrams
Data
Lead-In
Lead-Out
SDCLK
t1
t1
t1
t1
IOS
OE
t1
READ
WRITE
t1
t1
ADDR[27:2]
t6
t5
DATA[31:0]
t6
t5
BEXC
Figure 3.17 Memory Mapped I/O 32-bit Read Cycle
Data
Lead-In
Lead-Out
SDCLK
t1
t1
t1
t1
IOS
OE
t1
READ
WRITE
t1
t1
ADDR[27:1]
t6
t5
DATA[31:16]
t6
t5
BEXC
Figure 3.18 Memory Mapped I/O 16-bit Read Cycle
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Chapter 3: Memory Controller with EDAC
Section 3.16: PROM, SRAM, and memory mapped I/O timing diagrams
Data
Lead-In
Lead-Out
SDCLK
t1
t1
t1
t1
IOS
OE
t1
READ
WRITE
t1
t1
ADDR[27:0]
t6
t5
DATA[31:24]
t6
t5
BEXC
Figure 3.19 Memory Mapped I/O 8-bit Read Cycle
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Chapter 3: Memory Controller with EDAC
Section 3.16: PROM, SRAM, and memory mapped I/O timing diagrams
Data
Lead-In
Lead-Out
SDCLK
t1
t1
IOS
OE
t1
t1
READ
t1
t1
WRITE
t1
t1
*
ADDR[27:2]
t2
t3
DATA[31:0]*
Figure 3.20 Memory Mapped I/O 32-bit Write Cycle
* ADDR[27:0] and Data[31:24] are used for 16-bit I/O bus configurations. ADDR[27:0] and DATA[31:24] for 8-bit I/O bus configurations.
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Chapter 3: Memory Controller with EDAC
Section 3.17: SDRAM timing diagrams
3.17 SDRAM timing diagrams
This section shows typical timing diagrams for SDRAM accesses. These timing diagrams are functional, and are intended to
show the relationship between control signals and the SDCLK. The actual values of the timing parameters can be found in
Chapter 4 of the UT700 datasheet.
tRC
tRAS
tCAS
tRCD
tRP
SDCLK
t1b
t1b
t1c
t1c
t1b
t1b
t1b
t1b
t1b
t1b
t1c
t1c
t1c
t1c
t1c
t1c
SDCS[1:0]
SDRAS
t1c
t1c
SDCAS
SDWE
t1a
t1a
t1a
t1a
t1a
t1a
t1a
t1a
t1a
t1a
t1a
t1a
t1d
t1d
ADDR[14:2]
ADDR[16:15]
SDDQM[3:0]
t6a
t5a
DATA[31:0]
t6a
t5a
CB[7:0]
Figure 3.21 SDRAM Read Cycle
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Chapter 3: Memory Controller with EDAC
Section 3.17: SDRAM timing diagrams
tRC
tRAS
tCAS
tRCD
tRP
SDCLK
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
SDCS[1:0]
SDRAS
t1
t1
t1
t1
SDCAS
SDWE
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
t1
ADDR[14:2]
ADDR[16:15]
SDDQM[3:0]
t2
t3
t2
t3
DATA[31:0]
CB[15:0]
Figure 3.22 SDRAM Write Cycle
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Chapter 4: AHB Status Registers
Section 4.1: Overview
Chapter 4: AHB Status Registers
4.1
Overview
The AHB status registers store information about AHB accesses triggering an error response. There is a status register (AHBSTAT) and a failing address register (AHBADDR). Both are contained in a module accessed from the APB bus.
4.2
Operation
The AHB status module monitors AHB bus transactions and stores the current HADDR, HWRITE, HMASTER and HSIZE internally. It is automatically enabled after power-on reset and monitors the AHB bus until an error response (HRESP = “01”) is
detected. When the error is detected, the status and address register content is frozen and the New Error (NE) bit is set to
one. At the same time, interrupt 1 is generated. To start monitoring the bus again, the NE bit must be cleared by software.
The status registers are also frozen when the memory controller signals a correctable error even though HRESP is “00” in
this case. The software can then scrub the corrected address in order to prevent error build-up and un-correctable multiple errors.
4.3
Correctable errors
Error responses on the AHB bus can be detected, the FT memory controller has a correctable error signal which is asserted
each time a correctable error is detected. When such an error is detected, the effect will be the same as for an AHB error
response. The only difference is that the Correctable Error (CE) bit in the status register is set to one when a correctable
error is detected.
When the CE bit is set the interrupt routine can acquire the address containing the correctable error from the failing
address register and correct it. Clearing the NE bit resets the CE bit and the monitoring becomes active again. Interrupt
handling is described in detail in the following section.
4.4
Interrupts
The interrupt is connected to the interrupt controller to inform the processor of the error condition. The normal procedure
is that an interrupt routine handles the error with the aid of the information in the status registers. When it is finished it
resets the NE bit and the monitoring becomes active again. Interrupts are generated for both AMBA error responses and
correctable errors as described above.
4.5
Registers
Figure 4.1 and Figure 4.2 shows the status register and failing address register. The registers are accessed from the APB bus.
AHBSTAT
Address = 0x80000F00
31
10
RESERVED
9
8
7
CE NE HW
6
3
HM
2
0
HS
31
RES
Figure 4.1 AHB Status Register
Table 4.1 Description of AHB Status Register
BIT NUMBER(S)
BIT NAME
RESET
STATE
31-10
Reserved
--
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Reserved
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Chapter 4: AHB Status Registers
Section 4.5: Registers
Table 4.1 Description of AHB Status Register
BIT NUMBER(S)
BIT NAME
RESET
STATE
9
CE
0
Correctable error. Set if the memory controller signaled a correctable error.
8
NE
0
New error. Deasserted at start-up and after reset. Asserted when
an error is detected. Reset by writing a zero to it.
7
HW
0
The HWRITE signal of the AHB transaction that caused the error.
6-3
HM
0000
The HMASTER signal of the AHB transaction that caused the error.
2-0
HS
000
The HSIZE signal of the AHB transaction that caused the error.
DESCRIPTION
AHBADDR
Address=0x80000F04
31
0
HADDR
Figure 4.2 AHB Failing Address Register
Table 4.2 Description of AHB Failing Address Register
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BIT NUMBER(S)
BIT NAME
RESET
STATE
31-0
HADDR
[000...0]
DESCRIPTION
The failing address of the AHB transaction that
caused the error.
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Chapter 5: Interrupt Controller
Section 5.1: Overview
Chapter 5: Interrupt Controller
5.1
Overview
The interrupts generated by on-chip units are all forwarded to the interrupt controller. The controller core then propagates
the interrupt with highest priority to the LEON 3FT processor.
5.2
Operation
5.2.1
Interrupt prioritization
The interrupt controller receives all on-chip interrupts. Each interrupt can be assigned to one of two levels (0 or 1) as programmed in the interrupt level register. Level 1 has higher priority than level 0. The interrupts are prioritized within each
level with interrupt 15 having the highest priority and interrupt 1 the lowest. The highest interrupt from level 1 forwardesto the processor. If no unmasked pending interrupt exists on level 1, then the highest unmasked interrupt from
level 0 forwards.
Interrupts are prioritized at system level while masking and forwarding of interrupts is done for each processor separately.
Each processor in a multi-processor system has separate interrupt mask and force registers. When an interrupt is signalled
on the AMBA bus, the interrupt controller prioritizes interrupts, perform interrupt masking for each processor according to
the mask in the corresponding mask register, and forward the interrupts to the processors.
IRQ Level
Select
IRQ
Pending
Priority
Encoder
Incoming IRQ
4
15
IRQ
Clear
IRQ
Force
LEON 3FT Interrupt
Control Logic [3:0]
IRQ
Mask
Figure 5.1 Interrupt Controller Block Diagram
When the processor acknowledges the interrupt, the corresponding pending bit automatically clears. Interrupt can also
be forced by setting a bit in the interrupt force register. In this case, the processor acknowledgement clears the force bit
rather than the pending bit. After reset, the interrupt mask register is set to all zeros while the remaining control registers
are undefined.
Note: Interrupt 15 cannot be masked by the LEON 3FT processor and should be used with care as most operating systems
do not safely handle this interrupt.
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Chapter 5: Interrupt Controller
Section 5.3: Registers
5.2.2
Interrupt allocation
The following table indicates the interrupt assignment in the UT700.
Table 5.1 Interrupt Assignment
5.3
CORE
INTERRUPT #
FUNCTION
AHBSTAT
1
AHB bus error
APBUART
2
UART1 RX/TX interrupt
GRPCI
3
PCI DMA Interrupts
CAN1
4
CAN1 interrupt
CAN2
5
CAN2 interrupt
GPTIMER
6, 7, 8, 9
Timer underflow interrupts
IRQMP
9
Extended interrupt vector
SPW1
10
SpaceWire1data interrupt
SPW2
11
SpaceWire2 data interrupt
SPW3
12
SpaceWire3 data interrupt
SPW4
13
SpaceWire4data interrupt
ETH
14
Ethernet interrupt
1553B
17
MIL-STD-1553 BC, RT, BM interrupt
SPICTRL
18
SPI controller interrupt
GPIO
1 - 15
External I/O interrupt
Registers
Table 5.2 shows the Interrupt Controller registers. The base address of the registers is 0x80000200.
Table 5.2 IRQ Controller Register
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REGISTER
APB Address
Interrupt level register (ILR)
0x80000200
Interrupt pending register (IPR)
0x80000204
Interrupt force register (IFR)
0x80000208
Interrupt clear register (ICR)
0x8000020C
Interrupt status register (ISR)
0x80000210
Interrupt mask register (IMR)
0x80000240
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Chapter 5: Interrupt Controller
Section 5.3: Registers
5.3.1
Interrupt level register
ILR
Address = 0x80000200
31
16 15
1
RESERVED
IL[15:1]
0
R
Figure 5.2 Interrupt Level Register
Table 5.3 Description of Interrupt Level Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...00]
15-1
IL[15:1]
[000...00]
DESCRIPTION
Interrupt level for interrupt IL[n]
0: Interrupt level 0
1: Interrupt level 1
0
5.3.2
Reserved
0
Interrupt pending register
IPR
Address = 0x80000204
31
16 15
1
RESERVED
IP[15:1]
0
R
Figure 5.3 Interrupt Pending Register
Table 5.4 Description of Interrupt Pending Register
BIT
NUMBER(S)
RESET
STATE
31-16
Reserved
[000...00]
15-1
IP[15:1]
[000...00]
0
5.3.3
BIT NAME
Reserved
DESCRIPTION
Interrupt pending for interrupt IP[n]
0: Interrupt not pending
1: Interrupt pending
0
Interrupt force register
IFR
Address = 0x80000208
31
16 15
1
RESERVED
IF[15:1]
0
R
Figure 5.4 Interrupt Force Register
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Chapter 5: Interrupt Controller
Section 5.3: Registers
Table 5.5 Description of Interrupt Force Register
BIT
NUMBER(S)
RESET
STATE
31-16
Reserved
[000...00]
15-1
IF[15:1]
[000...00]
0
5.3.4
BIT NAME
Reserved
DESCRIPTION
Force interrupt IF[n]
0: Normal operation
1: Force interrupt
0
Interrupt clear register
ICR
Address = 0x8000020C
31
16 15
1
RESERVED
IC[15:1]
0
--
Figure 5.5 Interrupt Clear Register
Table 5.6 Description of Interrupt Clear Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
15-1
IC[15:1]
[000...0]
DESCRIPTION
Clear interrupt IC[n]
0: Normal operation
1: Clear interrupt
0
5.3.5
Reserved
0
Status register
ISR
Address = 0x80000210
31
28 27 26
NCPU
BA
20 19
Reserved
16 15
0
EIRQ
STATUS[15:0]
Figure 5.6 Interrupt Status Register
Table 5.7 Description of Interrupt Status Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-28
NCPU
[000...0]
27
BA
0
26-20
Reserved
[000...0]
DESCRIPTION
Number of CPUs in the system -1
Broadcast Available - set to 1 if NCPU > 0
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Chapter 5: Interrupt Controller
Section 5.3: Registers
Table 5.7 Description of Interrupt Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
19-16
EIRQ
1001
15-0
STATUS[15:0]
[000...0]
DESCRIPTION
Extended Interrupts 1-15
Power-down status of CPU[n] (STATUS[n]) 1 - power-down, 0 - running
Write STATUS[n] with a ‘1’ to start processor n
IMR
Address = 0x80000810
31
16 15
0
Reserved
IM[15:1]
Figure 5.7
Table 5.8 Description of Interrupt Mask Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
15-1
IM[15:1]
[00...0]
DESCRIPTION
Interrupt mask for IM[n]
0: Interrupt is masked
1: Interrupt is enabled
0
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Chapter 6: UART with APB interface
Section 6.1: Overview
Chapter 6: UART with APB interface
6.1
Overview
A UART is provided for serial communications. The UART supports data frames with eight data bits, one optional parity bit,
and one stop bit. To generate the bit-rate, the UART has a programmable 12-bit clock divider. Two 8-byte FIFOs are used for
the data transfers between the bus and UART. Figure 6.1 shows a block diagram of the UART.
Baud-rate
8*bitclk
generator
RXD
Serial port
Controller
Receiver shift register
Transmitter shift register
Receiver FIFO
Transmitter FIFO
TXD
APB
Figure 6.1 APB UART Block Diagram
6.2
6.2 Operation
6.2.1
Transmitter operation
The transmitter is enabled through the TE bit in the UART control register UARTCTR. Data that is to be transferred is stored
in the transmitter FIFO by writing to the data register UARTDTR [7:0]. When ready to transmit, data is transferred from the
transmitter FIFO to the transmitter shift register and converted to a serial stream on the transmitter serial output pin (TXD).
It automatically sends a start bit followed by eight data bits, an optional parity bit, and one stop bit (Figure 6.2). The least
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Chapter 6: UART with APB interface
Section 6.2: 6.2 Operation
significant bit of the data is sent first.
Data frame, no parity:
Start D0
D1
D2
D3
D4
D5
D6
D7 Stop
Data frame with parity:
Start D0
D1
D2
D3
D4
D5
D6
D7 Parity Stop
Figure 6.2 UART Data Frames
Following the transmission of the stop bit, if a new character is not available in the transmitter FIFO, the transmitter serial
data output remains high and the transmitter shift register empty bit (TS) is set in the UART status register. Transmission
resumes and the TS is cleared when a new character is loaded into the transmitter FIFO. When the FIFO is empty the TE bit
is set in the status register UARTSTR. If the transmitter is disabled, it immediately stops any active transmissions including
the character currently being shifted out from the transmitter shift register. The transmitter holding register may not be
loaded when the transmitter is disabled or when the transmitter FIFO is full. If this is done, data might be overwritten and
one or more frames lost.
The TF status bit (not to be confused with the TF control bit) is set if the transmitter FIFO is currently full and the TH bit is
set as long as the FIFO is less than half-full, i.e. less than half of entries in the FIFO contain data. The TF control bit in the control register UARTCTR enables FIFO interrupts when set. The status register also contains a counter (TCNT) showing the
current number of data entries in the transmitter FIFO.
6.2.2
Receiver operation
The receiver is enabled for data reception through the receiver enable (RE) bit in the UART control register. The receiver
looks for a high to low transition of a start bit on the receiver serial data input pin. If a transition is detected, the state of the
serial input is sampled a half bit clock later. If the serial input is sampled high, the start bit is invalid and the search for a
valid start bit continues. If the serial input is still low, a valid start bit is assumed and the receiver continues to sample the
serial input at one bit time intervals (at the theoretical center of the bit) until the proper number of data bits and the parity
bit have been assembled and one stop bit has been detected. The serial input is shifted through an 8-bit shift register
where all bits need the same value before the new value is taken into account, effectively forming a low-pass filter with a
cut-off frequency of 1/8 system clock.
The receiver also has a 8-byte receiver FIFO identical to the transmitter. FIFO data from the receiver FIFO is removed by
reading the data register UARTDTR [7:0].
During reception, the least significant bit is received first. The data is then transferred to the receiver FIFO and the data
ready (DR) bit is set in the UART status register as soon as the FIFO contains at least one data frame. The parity, framing and
overrun error bits are set at the received byte boundary at the same time as the receiver ready bit is set. The data frame is
not stored in the FIFO if an error is detected. Also, the new error status bits are OR’d with the old values before they are
stored into the status register. Thus, they are not cleared until written to with zeros from the APB bus. If both the receiver
FIFO and shift registers are full when a new start bit is detected, then the character held in the receiver shift register is lost
and the overrun bit is set in the UART status register.
The RF status bit (not to be confused with the RF control bit) is set when the receiver FIFO is full. The RH status bit is set
when the receiver FIFO is half-full (at least half of the entries in the FIFO contain data frames). The RF control bit in the control register UARTCTR enables receiver FIFO interrupts when set. A RCNT field is also available showing the current number
of data frames in the FIFO.
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Chapter 6: UART with APB interface
Section 6.3: Baud-rate generation
6.3
Baud-rate generation
Each UART contains a 12-bit down-counting scaler to generate the desired baud-rate. The scaler is clocked by the system
clock and generates a UART tick each time it underflows. It is reloaded with the value of the UART scaler reload register
after each underflow. The resulting UART tick frequency should be eight times the desired baud-rate.
SCALER_RELOAD_VALUE = SYS_CLK/(BAUD_RATE*8)
6.3.1
Loop back mode
If the LB bit in the UART control register is set, the UART is in loop back mode. In this mode, the transmitter output is internally connected to the receiver input. It is then possible to perform loop back tests to verify operation of receiver, transmitter and associated software routines. In this mode, the outputs remain in the inactive state, in order to avoid sending out
data.
6.3.2
Interrupt generation
Two different kinds of interrupts are available: normal interrupts and FIFO interrupts. For the transmitter, normal interrupts
are generated when transmitter interrupts are enabled (TI), the transmitter is enabled and the transmitter FIFO goes from
containing data to being empty. FIFO interrupts are generated when the FIFO interrupts are enabled (TF), transmissions
are enabled (TE) and the UART is less than half-full, i.e. whenever the TH status bit is set. This is a level interrupt and the
interrupt signal is continuously driven high as long as the condition prevails. The receiver interrupts work in the same way.
Normal interrupts are generated in the same manner as for the holding register. FIFO interrupts are generated when
receiver FIFO interrupts are enabled, the receiver is enabled and the FIFO is half-full. The interrupt signal is continuously
driven high as long as the receiver FIFO is half-full (at least half of the entries contain data frames).
6.4
UART registers
The APB UART is controlled through four registers mapped into APB address space. UART registers are mapped as follows:
Table 6.1 APB UART Registers
6.4.1
REGISTER
APB ADDRESS
UART Data Register (UARTDTR)
0x80000100
UART Status Register (UARTSTR)
0x80000104
UART Control Register (UARTCTR)
0x80000108
UART Scaler Register (UARTSCR)
0x8000010C
UART data register
The UART data register provides access to the receiver and transmit FIFO register. The transmitter FIFO is accessed by writing to the data register. The receiver FIFO is accessed by reading the data register.
UARTDTR
Address=0x80000100
31
8
RESERVED
7
0
DATA[7:0]
Figure 6.3 UART Data Register
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Chapter 6: UART with APB interface
Section 6.4: UART registers
Table 6.2 Description of UART Data Register
6.4.2
BIT
NUMBER
BIT NAME
RESET
STATE
DESCRIPTION
31-8
Reserved
[000...00]
7-0
Receiver FIFO
[000...00]
Reading the data register accesses the
receiver FIFO.
7-0
Transmitter FIFO
[000...00]
Writing to the data register access the
transmitter FIFO.
UART status register
The UART Status Register provides information about the state of the FIFO’s and error conditions.
UARTSTR
Address=0x80000104
31
26 25
RCNT
20 19
11 10
TCNT
RESERVED
RF
9
8
7
6
TF RH TH FE
5
4
3
2
1
0
PE OV BR TE TS DR
Figure 6.4 UART Status Register
Table 6.3 Description of UART Status Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-26
RCNT
[000...00]
Receiver FIFO Count
Shows the number of data frames in the
Receiver FIFO.
25-20
TCNT
[000...00]
Transmitter FIFO Count
Shows the number of data frames in the
Transmitter FIFO.
19-11
Reserved
[000...00]
10
RF
0
Receiver FIFO Full
Indicates that the Receiver FIFO is full.
9
TF
0
Transmitter FIFO Full
Indicates that the Transmitter FIFO is full.
8
RH
0
Receiver FIFO Half Full
Indicates that at least half of the FIFO is
holding data.
7
TH
0
Transmitter FIFO Half Full
Indicates that the FIFO is less than halffull.
6
FE
0
Framing Error
Indicates that a framing error was
detected.
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Chapter 6: UART with APB interface
Section 6.4: UART registers
Table 6.3 Description of UART Status Register
6.4.3
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
5
PE
0
Parity Error
Indicates that a parity error was
detected.
4
OV
0
Overrun
Indicates that one or more characters
have been lost due to overrun.
3
BR
0
Break Received
Indicates that a BREAK has been
received.
2
TE
0
Transmitter FIFO Empty
Indicates that the transmitter FIFO is
empty.
1
TS
0
Transmitter Shift Register Empty
Indicates that the transmitter shift register is empty.
0
DR
0
Data Ready
Indicates that new data is available in
the receiver holding register.
UART control register
The UART Control Register is used to enable the transmitter and receiver and control how interrupts are generated.
UARTCTR
Address=0x80000108
31
11 10
9
8
7
6
RF
TF
--
LB
--
RESERVED
5
4
PE PS
3
2
TI
RI
1
0
TE RE
Figure 6.5 UART Control Register
Table 6.4 Description of UART Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-11
Reserved
[000...00]
10
RF
0
Receiver FIFO Interrupt Enable
0: Receiver FIFO level interrupts disabled
1: Receiver FIFO level interrupts enabled
9
TF
0
Transmitter FIFO Interrupt Enable
0: Transmitter FIFO level interrupts disabled
1: Transmitter FIFO level interrupts enabled
8
Reserved
0
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Chapter 6: UART with APB interface
Section 6.4: UART registers
Table 6.4 Description of UART Control Register
6.4.4
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
7
LB
0
6
Reserved
0
5
PE
0
Parity Enable
0: Parity generation and checking disabled
1: Parity generation and checking enabled
4
PS
0
Parity Select
0: Even parity
1: Odd parity
3
TI
0
Transmitter Interrupt Enable
0: No frame interrupts
1: Interrupts generated when a frame is transmitted
2
RI
0
Receiver Interrupt Enable
0: No frame interrupts
1: Interrupts generated when a frame is received
1
TE
0
Transmitter Enable
0: Transmitter disabled
1: Transmitter enabled
0
RE
0
Receiver Enable
0: Receiver disabled
1: Receiver enabled
Loopback Mode
0: Disabled
1: Enabled
UART scaler register
UARTSCR
Address=0x800010C
31
12 11
RESERVED
0
SCALER RELOAD VALUE
Figure 6.6
Table 6.5 Description of UART Scaler Reload Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-12
Reserved
[000...00]
11-0
SRV
0
94-00-00-000
Ver. 1.1.0
DESCRIPTION
Scaler Reload Value
SRV=SYS_CLK / (BAUD_RATE*8)
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Chapter 7: Timer Unit
Section 7.1: Overview
Chapter 7: Timer Unit
7.1
Overview
The Timer Unit implements one 12-bit prescaler and four 32-bit decrementing timers. The timer unit registers are accessed
through the APB bus. The unit is capable of asserting an interrupt when a timer underflows. A separate interrupt is available for each timer.
timer 1 reload
timer 2 reload
timer 3 reload
timer 4 reload
prescaler reload
prescaler value
tick
-1
timer 1 value
irq 6
timer 2 value
irq 7
timer 3 value
irq 8
timer 4 value
irq 9
-1
Figure 7.1 Timer Unit Block Diagram
7.2
Operation
The prescaler is clocked by the system clock and decremented on each clock cycle. When the prescaler underflows, it is
reloaded from the prescaler reload register and a timer tick is generated. Timers share the decrementer to save area. On
the next timer tick, timer n+1 next timer is decremented giving an effective division rate equal to
SCALER_RELOAD_VALUE+1.
The operation of each timer is controlled through its control register. A timer is enabled by setting the enable bit (EN) in
the control register. The timer value is then decremented on each prescaler tick. When a timer underflows, it will automatically be reloaded with the value of the corresponding timer reload register, if the restart bit (RS) in the control register is
set, otherwise it stops at -1 and reset the enable bit.
Each timer signals its interrupt when the timer underflows (if the interrupt enable bit (IE) for the current timer is set). The
interrupt pending bit (IP) in the control register of the underflown timer sets and remains set until cleared by writing ‘0’.
Timer 1 generates interrupt 6, timer 2 generates interrupt 7, timer 3 generates interrupt 8, and timer 4 generates interrupt
9.
To minimize complexity, timers share the same decrementer. This means that the minimum allowed prescaler division factor is 5 (SCALER_RELOAD_VALUE=4).
By setting the chain bit (CH) in the control register timer n can be chained with preceding timer n-1. Decrementing timer n
will start when timer n-1 underflows.
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Chapter 7: Timer Unit
Section 7.3: Registers
Each timer can be reloaded with the value in its reload register at any time by writing a ‘1’ to the load bit (LD) in the control
register. Timer 4 also operates as a watchdog, driving the watchdog output signal (WDOG) low when the count underflows Timer 4 counter value register.
7.3
Registers
Table 7.1 shows the timer unit registers.
Table 7.1 General Purpose Timer Unit Registers
REGISTER
APB ADDRESS
Scaler Value
0x80000300
Scaler Reload Value
0x80000304
Configuration Register
0x80000308
Timer 1 Counter Value Register
0x80000310
Timer 1 Reload Value Register
0x80000314
Timer 1 Control Register
0x80000318
Timer 2 Counter Value Register
0x80000320
Timer 2 Reload Value Register
0x80000324
Timer 2 Control Register
0x80000328
Timer 3 Counter Value Register
0x80000330
Timer 3 Reload Value Register
0x80000334
Timer 3 Control Register
0x80000338
Timer 4 Counter Value Register
0x80000340
Timer 4 Reload Value Register
0x80000344
Timer 4 Control Register
0x80000348
Figure 7.4 and Figure 7.5 show the layout of the timer unit registers.
TIMSVR
Address=0x80000300
31
12 11
0
SCALER_VALUE
RESERVED
Figure 7.2 Scaler Value Register
TIMRVR
Address=0x80000304
31
12 11
RESERVED
0
SCALER_RELOAD_VALUE
Figure 7.3 Scaler Reload Value Register
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Chapter 7: Timer Unit
Section 7.3: Registers
Table 7.2 Description of Timer Configuration Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-10
Reserved
[000...0]
9
DF
0
Disable Timer Freeze
0: Timer unit can be frozen during debug mod
1: Timer unit cannot be frozen during debug mode
8
SI
1
Separate Interrupts
0: Single interrupt for timers
1: Each timer generates a separate interrupt
Read=1; Write=Don’t car
7-3
IRQ
00110
2-0
TIMERS
100
APB Interrupt
If configured for common interrupt, all timers will drive APB
interrupt nr IRQ, otherwise timer n will drive APB Interrupt 4 +
n.
Number of Implemented Timers
Read=100b; Write=Don’t care
TIMCVR1
TIMCVR2
TIMCVR3
TIMCVR4
Address=0x80000310
Address=0x80000320
Address=0x80000330
Address=0x80000340
31
0
TIMER_COUNTER_VALUE
Figure 7.4 Timer Counter Value Registers
Table 7.3 Description of Timer Counter Value Registers
BIT
NUMBER(S)
BIT NAME
RESET
STATE1
DESCRIPTION
31-0
Timer
Counter
Value
[- - -...-]
Decremented by 1 for each tick, or when timer n1 underflows if in chain mode.
TIMRVR1
TIMRVR2
TIMRVR3
TIMRVR4
Address=0x80000314
Address=0x80000324
Address=0x80000334
Address=0x80000344
31
0
TIMER_RELOAD_VALUE
Figure 7.5 Timer Reload Value Registers
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Chapter 7: Timer Unit
Section 7.3: Registers
Table 7.4 Description of Timer Reload Value Registers
BIT
NUMBER(S)
BIT NAME
RESET
STATE1
DESCRIPTION
31-0
Timer
Reload
Value
[- - -...-]
This value is loaded into the timer counter value register when ‘1’
is written to bit LD in the timers control register, or when the RS
bit is set in the control register and the timer underflows.
Note1: Timer resets to value 0X000FFFF
TIMCTR1
TIMCTR2
TIMCTR3
TIMCTR4
Address=0x80000318
Address=0x80000328
Address=0x80000338
Address=0x80000348
31
7
RESERVED
6
5
DH CH
4
3
IP
IE
2
1
0
LD RS EN
Figure 7.6 Timer Control Registers
Table 7.5 Description of Timer Control Registers
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-7
Reserved
[000...0]
6
DH
1
Debug Halt
State of timer when DF=0. Read only
0: Active
1: Frozen
5
CH
1
Chain with preceding timer
0: Timer functions independently
1: Decrementing timer n begins when timer (n-1) underflows.
4
IP
0
Interrupt Pending
0: Interrupt not pending
1: Interrupt pending. Remains ‘1’ until cleared by writing ‘1’ to
this bit
3
IE
0
Interrupt Enable
0: Interrupts disabled
1: Timer underflow signals interrupt
2
LD
0
Load Timer
Writing a ‘1’ to this bit loads the value from the timer reload register to the timer counter value register.
1
RS
0
Restart
Writing a ‘1’ to this bit reloads the timer counter value register
with the value of the reload register when the timer underflows.
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DESCRIPTION
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Chapter 7: Timer Unit
Section 7.3: Registers
Table 7.5 Description of Timer Control Registers
BIT
NUMBER(S)
BIT NAME
RESET
STATE
0
EN
0
94-00-00-000
Ver. 1.1.0
DESCRIPTION
Timer Enable
0: Disable
1: Enable
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Chapter 8: General Purpose I/O Port
Section 8.1: Overview
Chapter 8: General Purpose I/O Port
8.1
Overview
A general purpose I/O port is provided using the GRGPIO core from GRLIB. The unit implements a 16-bit I/O port with
interrupt support. Each bit in the port is individually set as an input or output and can optionally generate an interrupt. For
interrupt generation, the input can be filtered for polarity and level/edge detection. The figure below shows a diagram for
one I/O line.
Input
Value
Direction
D
Q
Output
Value
D
Q
Input D
Q
Value
Q
D
PAD
Figure 8.1 General Purpose I/O Port Diagram
8.2
Operation
The I/O ports are implemented as bi-directional buffers with programmable output enable. The input from each buffer is
synchronized by two flip-flops in series to remove potential meta-stability. The synchronized values can be read out from
the I/O port data register. The output enable is controlled by the I/O port direction register. A ‘1’ in a bit position enables
the output buffer for the corresponding I/O line. The output value driven is taken from the I/O port output register.
I/O ports 1-15 drive a separate interrupt line on the APB interrupt bus. The interrupt number is equal to the I/O line index
(PIO[1] = interrupt 1, etc.). The interrupt generation is controlled by three registers: interrupt mask, polarity and edge registers. To enable an interrupt, the corresponding bit in the interrupt mask register must be set. If the edge register is ‘0’, the
interrupt is treated as level sensitive. If the polarity register is ‘0’, the interrupt is active low. If the polarity register is ‘1’, the
interrupt is active high. If the edge register is ‘1’, the interrupt is edge-triggered. The polarity register then selects between
rising edge (‘1’) or falling edge (‘0’).
8.3
Registers
Table 8.1 shows the I/O port register addresses.
Table 8.1 I/O Port Registers
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REGISTER
APB ADDRESS
GPIO Port Data Register (GPIODVR)
0x80000900
GPIO Port Output Register (GPIODOR)
0x80000904
GPIO Port Direction Register (GPIODDR)
0x80000908
Interrupt Mask Register (GPIOIMR)
0x8000090C
Interrupt Polarity Register (GPIOIPR)
0x80000910
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Chapter 8: General Purpose I/O Port
Section 8.3: Registers
Table 8.1 I/O Port Registers
8.3.1
REGISTER
APB ADDRESS
Interrupt Edge Register (GPIOIER)
0x80000914
GPIO port data value register
GPIODVR
Address=0x80000900
31
16 15
0
RESERVED
I/O Port Value
Figure 8.2 GPIO Port Data Value Register
Table 8.2 Description of GPIO Port Data Value Register
8.3.2
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
15-0
PORTVAL[15:0]
[000...0]
DESCRIPTION
GPIO Port Value
This read-only register indicates the
state of port pin n.
0: Data=‘0’
1: Data=‘1’
GPIO port data output register
GPIODOR
Address=0x80000904
31
16 15
RESERVED
0
I/O Port Output Register
Figure 8.3 GPIO Port Data Output Register
Table 8.3 Description of GPIO Port Data Output Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
15-0
PORTOUT[15:0]
[000...0]
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DESCRIPTION
GPIO Port Output
The port output register sets the state of port pin n
when configured as an output.
0: Data=‘0’
1: Data=‘1’
Aeroflex Microelectronic Solutions - HiRel
Chapter 8: General Purpose I/O Port
Section 8.3: Registers
8.3.3
GPIO port data direction register
GPIODDR
Address=0x80000908
31
16 15
RESERVED
0
I/O Port Direction Register
Figure 8.4 GPIO Port Data Direction Register
Table 8.4 Description of GPIO Port Data Direction Register
8.3.4
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
15-0
PORTDDR[15:0]
[000...0]
DESCRIPTION
GPIO Data Direction
0: Port pin n configured as input
1: Port pin n configured as output
GPIO interrupt mask register
GPIOIMR
Address=0x8000090C
31
16 15
RESERVED
0
Interrupt Mask Register
Figure 8.5 GPIO Interrupt Mask Register
Table 8.5 Description of GPIO Interrupt Mask Register
8.3.5
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
15-0
GPIOIMR[15:0]
[000...0]
DESCRIPTION
GPIO Mask Register
0: Interrupt n disabled
1: Interrupt n enabled
GPIO interrupt polarity register
Address=0x80000910
GPIOIPR
31
16 15
RESERVED
0
Interrupt Polarity Register
Figure 8.6 GPIO Interrupt Polarity Register
Table 8.6 Description of GPIO Interrupt Polarity Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
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Chapter 8: General Purpose I/O Port
Section 8.3: Registers
Table 8.6 Description of GPIO Interrupt Polarity Register
8.3.6
BIT
NUMBER(S)
BIT NAME
RESET
STATE
15-0
GPIOIPR[15:0]
[---...-]
DESCRIPTION
GPIO Polarity Register
This register configures the polarity of interrupt n.
GPIOIER[n]=0
0: Active low
1: Active high
GPIOIER[n]=1
0: Falling edge
1: Rising edge
GPIO interrupt edge register
GPIOIER
Address=0x80000914
31
16 15
RESERVED
0
Interrupt Edge Register
Figure 8.7 GPIO Interrupt Edge Register
Table 8.7 Description of GPIO Interrupt Edge Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
15-0
GPIOIER[15:0]
[---...-]
DESCRIPTION
GPIO Interrupt Edge Register
This register configures how an interrupt on port
pin n is triggered.
0: Level triggered
1: Edge triggered
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Chapter 9: PCI Target / Master Unit
Section 9.1: Overview
Chapter 9: PCI Target / Master Unit
9.1
Overview
The PCI Target/Master Unit is a bridge between the PCI bus and the AMBA AHB bus. The unit is connected to the PCI bus
through the PCI Target interface and PCI Master interface. The AHB Slave and AHB Master interfaces connect the PCI core
to the AHB bus. The PCI Configuration & Status register is accessed via the APB bus.
The PCI and AMBA interfaces belong to two different clock domains. Synchronization is performed inside the core through
FIFOs.
AMBA bus
PCI Bridge
Cfg/Stat
AHB Slave
MTx FIFO
MRx FIFO
AHB Master
TTx FIFO
PCI Master
TRx FIFO
PCI Target
PCI Off-chip bus
Figure 9.1 Figure 69. PCI Master/Target Unit
9.2
Operation
9.2.1
PCI target unit
The PCI target interface and AHB master provide a connection between the PCI bus and the AHB bus. The PCI target is
capable of handling configuration and single or burst memory cycles on the PCI bus. Configuration cycles are used to
access the Configuration Space Header of the target, while the memory cycles are translated to AHB accesses. The PCI target interface can be programmed to occupy two areas in the PCI address space via registers BAR0 and BAR1 (Section 9.4).
Mapping to the AHB address space is defined by map registers PAGE0 and PAGE1, which are accessible from PCI and AHB
address space, respectively.
9.2.2
PCI master unit
The PCI master interface occupies one 1GB AHB memory bank and one 128 KB AHB I/O bank. Accesses to the memory area
are translated to PCI memory cycles and accesses to the I/O area generate I/O or configuration cycles. Generation of PCI
cycles and mapping to the PCI address spaces is controlled through the Configuration/Status Register and the I/O Map
Register (Section 9.9).
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Chapter 9: PCI Target / Master Unit
Section 9.3: PCI target interface
9.2.3
Burst transactions
Both target and master interfaces are capable of burst transactions. Data is buffered internally in FIFO.
9.2.4
Byte Twisting
As PCI is little endian and the AHB controller is big endian, byte twisting is performed on all accesses to preserve the byte
ordering as shown in Figure 9.2. Byte twisting can be enabled or disabled in the PAGE0 register (Section 9.5).
Because of byte twisting, byte accesses work correctly. However, 16- and 32-bit PCI accesses need to be byte twisted
before being sent to the PCI core.
Note: Accesses between the AHB bus and PCI bus are twisted. Accesses to the configuration space are not byte twisted.
AMBA bus
31-24
23-16
15-8
Address 0
7-0
Address 3
GRPCI
Address 3
PCI Off-chip bus
Address 0
31-24
23-16
15-8
7-0
Figure 9.2 GRPCI Byte Twisting
9.3
PCI target interface
The PCI target interface occupies two memory areas in the PCI address space as defined by the BAR0 and BAR1 registers in
the Configuration Space Header. Register BAR0 maps to a PCI space of 1MB; register BAR1 maps to a PCI space of 64MB.
The PCI Target interface handles the following PCI commands:
• Configuration Read/Write: Single access to the Configuration Space Header. No AHB access is performed
• Memory Read: If prefetching is enabled, the AHB master interface fetches a cache line. Otherwise, a single AHB
access is performed
• Memory Read Line: The unit prefetches data according to the value of the Cache Line Size register
• Memory Read Multiple: The unit performs maximum prefetching
• Memory Write
• Memory Write and Invalidate
The target interface supports incremental bursts for PCI memory cycles. The target interface can finish a PCI transaction
with one of the following abnormal responses:
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Chapter 9: PCI Target / Master Unit
Section 9.4: PCI target configuration space header registers
• Retry: This response indicates that the master should perform the same request later, as the target is temporarily
busy. This response is always given at least one time for read accesses, but can also occur for write accesses.
• Disconnect with data: Indicates that the target can accept one more data transaction, but no more. This occurs if the
master tries to read more data than the target has prefetched.
• Disconnect without data: Indicates that the target is unable to accept more data. This occurs if the master tries to
write more data than the target can buffer.
• Target-Abort: Indicates that the current access caused an internal error and that the target will not be able to complete the access.
The AHB master interface of the target is capable of burst transactions. Burst transactions are performed on the AHB when
supported by the destination unit (AHB slave); otherwise, multiple single access is performed. A PCI burst crossing a 1 KB
address boundary will be performed as multiple AHB bursts by the AHB master interface. The AHB master interface inserts
an idle-cycle before requesting a new AHB burst to allow for re-arbitration of the AHB. AHB transactions with a ‘retry’
response are repeated by the AHB master until an ‘okay’ or ‘error’ response is received. The ‘error’ response on AHB bus
results in a Target-Abort response for the PCI memory read cycle. In the case of a PCI memory write cycle, the AHB access
will not finish with an error response since write data is posted to the destination unit. Instead, the WE bit will be set in the
Configuration/Status register (APB address 0x80000400).
9.4
PCI target configuration space header registers
The registers implemented in the PCI Configuration Space Header are listed in the following table and described in this
section.
Table 9.1 Configuration Space Header Registers
REGISTER
CONFIGURATION SPACE HEADER
ADDRESS OFFSET
Device ID & Vendor ID
0x00
Status & Command
0x04
Class Code & Revision ID
0x08
BIST, Header Type, Latency Timer, Cache Line Size
0x0C
BAR0
0x10
BAR1
0x14
Max_Lat, Min_GNT, Interrupt
0x3C
Device/Vendor
Offset 0x00
31
16 15
0
DEVICE_ID
VENDOR_ID
Figure 9.3 Device ID & Vendor ID Register
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Chapter 9: PCI Target / Master Unit
Section 9.4: PCI target configuration space header registers
Table 9.2 Description of Device ID & Vendor ID Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-16
DEVICE_ID
0x699
Returns the value of Device ID.
Read=0x0699; Write=don’t care
15-0
VENDOR_ID
0x1AD0
Returns the value of Vendor ID.
Read=0x1AD0; Write=don’t care
PCISTAT
Offset 0x04
31 30 29 28 27 26 25 24 23
DPE -- RMA RTA STA
DST
5
DPD
RESERVED
4
3
MIE --
2
1
0
BM MS
--
Figure 9.4 Status & Command Register
Table 9.3 Description of Status & Command Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31
DPE
0
30
Reserved
0
29
RMA
0
Received Master Abort
Set by the PCI master interface when its transaction is terminated
with Master-Abort.
0: PCI master transaction terminated with no Master-Abort
1: PCI master transaction terminated with Master-Abort
28
RTA
0
Received Target Abort
Set by the PCI master interface when its transaction is terminated
with Target-Abort.
0: PCI master transaction terminated with no Target-Abort
1: PCI master transaction terminated with Target-Abort
27
STA
0
Signalled Target Abort
Set by the PCI target interface when the target terminates transaction with Target-Abort.
0: PCI target terminated with no Target-Abort
1: PCI target terminated with Target-Abort
26-25
DST
10
Device Select Timing
Read=10b; Write=don’t care.
24
DPD
0
Data Parity Error Detected
0: No data parity error detected
1: Data parity error detected
Detected Parity Error
0: No parity error detected
1: Parity error detected
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Chapter 9: PCI Target / Master Unit
Section 9.4: PCI target configuration space header registers
Table 9.3 Description of Status & Command Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
23-5
Reserved
0
4
MIE
0
3
Reserved
0
2
BM
0
Bus Master
Enbales the Master Interface to generate PCI cycles.
0: Disabled
1: Enabled
1
MS
0
Memory Space
Allows the unit to respond to memory space accesses.
0: Disabled
1: Enabled
0
Reserved
0
Memory Write and Invalidate Enable
Enables the PCI Master interface to generate Memory Write and
Invalidate command.
0: Disabled
1: Enabled
PCICLASS
Offset 0x08
31
8
7
CLASS_CODE
0
REVISION_ID
Figure 9.5
Table 9.4 Description of Class Code & Revision ID
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
CLASS_CODE
0xB4000
7-0
REVISION_ID
0x00
DESCRIPTION
Returns the value of Class Code.
Read=0x0B4000; Write=don’t care
Returns the value of Revision ID.
Read=0x00; Write=don’t care
PCIBHLC
Offset 0x0C
31
24 23
BIST
16 15
HEADER
8
7
LTM
0
CLS
Figure 9.6 BIST, Header Type, Latency Timer and Cache Line Size Register
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Chapter 9: PCI Target / Master Unit
Section 9.4: PCI target configuration space header registers
Table 9.5 Description of BIST, Header Type, Latency Timer and Cache Line Size Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-24
BIST
[000...0]
Built-in Self Test
Not supported. Read=0x00; Write=don’t care
23-16
HEADER
[000...0]
Header Type
Read=0x00; Write=don’t care
15-8
LTIM
[000...0]
Latency Timer
Maximum number of PCI clock cycles that the PCI bus
master can own the bus.
7-0
CLS
[000...0]
System Cache Line Size
Defines the prefetch length for Memory Read and Memory Read Line commands.
PCIBAR0
Offset 0x10
31
21 20
4
BASE_ADDRESS_0
“00...0”
3
PR
2
1
TP
0
MS
Figure 9.7 BAR0 Register
Table 9.6 Description of BAR0 Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-21
BASE_ADDRESS_0
[000...0]
PCI Target Interface Base Address 0
A memory area of 2MB is defined at memory location
BASE_ADDRESS_0. PCI memory accesses to the lower half of
this area are translated to AHB accesses using PAGE0 map register (Section 9.5).
20-4
Reserved
[000...0]
This field can be used to determine the memory requirement of
the target by writing all ‘1s’ to the BAR0 register and reading
back the value. The device returns ‘0s’ in unimplemented bits
positions effectively defining the requested memory area.
Read=00...0b; Write=don’t care
3
PR
0
Prefetchable
Read=0; Write=don’t care
2-1
TP
00
Type
Read=0; Write=don’t care
0
MS
0
Memory Space Indicator
Read=0; Write=don’t care
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Chapter 9: PCI Target / Master Unit
Section 9.4: PCI target configuration space header registers
PAGE0 register is mapped into upper half of the PCI address space defined by BAR0 register.
PCIBAR1
Offset 0x14
31
26 25
4
BASE ADDRESS
‘00..0’
3
2
PR
1
TP
0
MS
Figure 9.8 BAR1 Register
Table 9.7 Description of BAR1 Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-26
BASE_ADDRESS_1
[000...0]
PCI Target Interface Base Address 1. A memory area of 64MB is
defined at memory location BASE_ADDRESS_1. PCI memory
accesses to this memory space are translated to AHB accesses
using PAGE1 map register (Section 9.5).
25-4
Reserved
[000...0]
This field can be used to determine the memory requirement of
the target by writing all ‘1s’ to the BAR1 register and reading back
the value. The device returns ‘0s’ in unimplemented bits positions
effectively defining the requested memory area.
Read=00...0b; write=don’t care.
3
PR
0
Prefetchable
Read=0; Write=don’t care.
2-1
TP
00
Type
Read=0; Write=don’t care.
0
MS
0
Memory Space Indicator
Read=0; Write=don’t care.
PCIMM
Offset=0x3C
31
24 23
Max_LAT
16 15
Min_GNT
8
7
Interrupt Pin
0
Interrupt Line
Figure 9.9 Max_lat, min_gnt and interrupt settings register
Table 9.8 Description of max_lat, min_gnt and interrupt settings register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-24
Max_LAT
[00...0]
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DESCRIPTION
Maximum Latency
Read only
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Chapter 9: PCI Target / Master Unit
Section 9.5: PCI target map registers
Table 9.8 Description of max_lat, min_gnt and interrupt settings register
9.5
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
23-16
Min_GNT
0x01
Minimum Grant
Read=0x01; Write=don’t care.
15-8
Interrupt Pin
0x01
Interrupt Pin
Read=0x01; Write=don’t care.
7-0
Interrupt Line
[---...-]
Interrrupt Line
Write able register used by the operating system to store
information about interrupt routing.
PCI target map registers
PAGE0 and PAGE1 registers map PCI accesses to AHB address space. PAGE0 is accessed from PCI accesses. PAGE1 can be
accessed from the APB.
Table 9.9 PCI Target Map Registers
9.5.1
REGISTER
ADDRESS
PAGE0
First address in the upper half of PCI address space defined by BAR0 register (BAR0 + 0x100000). Accessible only from the PCI address space.
PAGE1
APB address 0x80000410
PAGE0 register
Register PAGE0 provides a memory mapping between the PCI address space defined by register BAR0 and the AHB
address space. PAGE0 is only accessible from a PCI memory access and its location in PCI address space depends upon the
value of BAR0. BAR0 provides a mapping of 2MB between the PCI address space and the PCI target. Only the lower half of
the BAR0 space is used. The upper half is unused except for the lowest word, which is the location of the PAGE0 register.
This means that the effective address space of BAR0 is 1MB. Any PCI access to the lower half of the BAR0 address space will
map to the AHB address space as defined by PAGE0. The following code example shows how to determine the location of
PAGE0 using a PCI memory access, and how to configure PAGE0 to provide a mapping between the PCI address space and
the APB address space.
/* Read the address of BAR0 */
pci_read_config_dword(bus, slot, function, 0x10, &tmp);
/* Determine the PCI address of PAGE0 */
addr_page0 = tmp + 0x100000;
/* Set PAGE0 to point to start of the APB memory space */
*addr_page0 = (unsigned int *) 0x80000000;
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Section 9.5: PCI target map registers
In this example, if the address of BAR0 is 0xC0000000, then the address of PAGE0 will be 0xC0100000. A write to PCI
address 0xC0000000 will translate to an AHB memory access at address 0x80000000.
PCIPAGE0
Address = 0x80000408
31
20
19
1
PAGE0_MAP
Reserved
0
BTEN
Figure 9.10 PAGE0 Register
Table 9.10 Description of PAGE0 Register
9.5.2
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-20
PAGE0_MAP
[000...0]
Maps PCI accesses to the PCI BAR0 address space to the AHB
address space. The AHB address is formed by concatenating
PAGE0_MAP with PCI address AD[19:0].
19-1
Reserved
[000...0]
Read=0x0; write=don’t care
0
BTEN
1
Byte Twisting Enable
May be altered only when bus mastering is disabled.
0: Disabled
1: Enabled
9.5.2 PAGE1 register
Register PAGE1 provides a memory mapping between the PCI address space defined by register BAR1 and the AHB
address space. PAGE1 is accessible directly from the APB bus (APB address 0x80000410), or indirectly from a PCI memory
access if PAGE0 is used to map PCI accesses to the APB memory space. BAR1 provides a mapping of 64MB between the PCI
address space and the PCI target. PAGE1 can therefore be used to map 64MB of the PCI address space to an equivalent size
in the AHB memory space.
PCIPAGE1
Address = 0x80000410
31
26 25
0
PAGE1_MAP
Reserved
Figure 9.11 PAGE1 Register
Table 9.11 Description of PAGE1 Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-26
PAGE1_MAP
[000...0]
Maps PCI accesses to the PCI BAR1 address space
to the AHB address space. The AHB address is
formed by concatenating PAGE1_MAP with PCI
address AD[25:0].
25-0
Reserved
[000...0]
Read=0x0; write=don’t care
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Chapter 9: PCI Target / Master Unit
Section 9.6: PCI master interface
9.6
PCI master interface
The PCI master interface occupies 1GB of AHB memory address space and 128 KB of AHB I/O address space. The PCI master
interface handles AHB accesses to its back-end AHB Slave interface and translates them to one of the following PCI cycles:
PCI configuration cycle, PCI memory cycle, or PCI I/O cycle.
Mapping of the PCI master’s AHB address space is configurable through the Configuration/Status Register and I/O Map
Register (Section 9.7).
9.6.1
PCI configuration cycles
Single PCI Configuration cycles are performed by accessing the upper 64 KB of AHB I/O address space allocated by the PCI
master’s AHB slave starting at address 0xFFF0FFFF. Type 0 configuration cycles are supported. The following figure shows
the configuration access format.
RegisterName
Address
31
16 15
ACM
11 10
IDSEL
8
7
FUNC
2
REGISTER
1
0
TP
Figure 9.12 Mapping of AHB I/O Addresses to PCI Address for PCI Configuration Cycles
Table 9.12 Description of Mapping of AHB I/O Addresses to PCI Address for PCI Configuration Cycles
9.6.2
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-16
ACM
[000...0]
AHB Configuration Register Mapping
These bits must always be set to 0xFFF1
15-11
IDSEL
[000...0]
This field is decoded to drive the PCI IDSEL lines
during configuration cycles.
10-8
FUNC
000
This field selects the function on a multi-function
device.
7-2
REGISTER
[000...0]
This field selects the DWORD register in the configuration space.
1-0
TP
00
Must be driven to ‘00’ to generate a Type 0 configuration cycle.
9.6.2 I/O cycles
PCI I/O cycles are performed by accessing the lower 64 KB of the AHB I/O address space occupied by the master’s AHB
slave interface are translated into PCI I/O cycles starting at address 0xFFF00000. Mapping is determined by the IOMAP field
of I/O Map Register. The IOMAP field of the I/O Map Register maps memory accesses between the PCI master (AHB memory space) and the PCI memory space when performing PCI I/O cycles. The PCI address is formed by concatenating IOMAP
with AHB address 15:0. IOMAP provides the 16 most-significant bits of the PCI I/O cycle address.
9.6.3
PCI memory cycles
PCI memory cycles are performed by accessing the 1GB AHB address space occupied by the master’s AHB slave starting at
address 0xC0000000. Mapping and PCI command generation are configured by programming the Configuration/Status
Register (APB address 0x80000400). Burst operation is supported for PCI memory cycles.The MMAP field of the Configuration/Status Register maps memory accesses between the PCI master (AHB memory space) and the PCI address space
when performing PCI memory cycles. The PCI address is formed by concatenating MMAP with AHB address 29:0. MMAP
provides the two most-significant bits of the PCI memory cycle address. PCI commands generated by the master are
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Chapter 9: PCI Target / Master Unit
Section 9.7: PCI host operation
directly dependent upon the AMBA transfer type and the value of Configuration/Status Register. The Configuration/Status
Register can be programmed to issue the following PCI commands: Memory Read, Memory Read Line, Memory Read Multiple, Memory Write, and Memory Write and Invalidate. If an AHB burst access is made to the PCI master’s AHB memory
space, it is translated to burst PCI memory cycle. When the PCI master interface is busy performing the transaction on the
PCI bus, its AHB slave interface will not be able to accept new requests. A ‘Retry’ response will be given to all accesses to its
AHB slave interface. The requesting AHB master repeats its request until an ‘OK’ or ‘Error’ response is given by the PCI master’s AHB slave interface.
Note: ‘RETRY’ responses on the PCI bus are not transparent and automatically be retried by the master PCI interface until
the transfer is either finished or aborted.For burst accesses, only linear-incremental mode is supported and is directly
translated from AMBA commands. Byte enables on the PCI bus are translated from the HSIZE control AHB signal and the
AHB address according to the table below.
Note: only WORD, HALF-WORD and BYTE values of HSIZE are valid.
Table 9.13 Byte Enable Generation
9.7
HSIZE
PCI_AD[1:0]
PCI_C/BE[3:0]
00 (8 bit)
00
1110
00 (8 bit)
01
1101
00 (8 bit)
10
1011
00 (8 bit)
11
0111
01 (16 bit)
00
1100
01 (16 bit)
10
0011
10 (32 bit)
00
0000
PCI host operation
The PCI core provides a host input signal that must be asserted (active low) for PCI host operation. If this signal is asserted,
the bus master interface is automatically enabled and the Bus Master (BM) bit is set in the Status and Command Register.
An asserted PCI host signal also enables the PCI target to respond to configuration cycles when the IDSEL signals
AD[31:11] are not asserted. This is done in order for the master to be able to configure its own target. For designs intended
to operate only as a host or peripheral, this signal can be tied low or high in the design. For multi-purpose designs it should
be connected to the appropriate PCI connector pin. The PCI Industrial Computers Manufacturers Group (PICMG) cPCI
specification specifies pin C2 on connector P2 for this purpose. The pin should have pull-up resistors as peripheral slots
leave it unconnected. PCI interrupts are supported as inputs for PCI hosts.
Note: PCI arbiter is NOT affected by the PCI_HOST input.
9.8
Interrupt Support
When acting as a PCI host, the GRPCI core can take the four PCI interrupt lines as inputs and use them to forward an interrupt to the interrupt controller.
There is no built-in support in the PCI core to generate PCI interrupts. These should be generated by the respective IP core
and drive an open-drain pad connected to the correct PCI interrupt line. Note: All single function PCI devices should drive
PCI Interrupt A.
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Chapter 9: PCI Target / Master Unit
Section 9.9: Registers
9.9
Registers
The core is programmed through registers mapped into APB address space.
Table 9.14 AMBA Registers
REGISTER
APB ADDRESS
NOTE
Configuration/Status Register
0x80000400
Read/write access from the APB bus.
BAR0 Register
0x80000404
Read-only access from the APB bus. Read/
write access from the PCI bus.
PAGE0 Register
0x80000408
Read-only access from the APB bus. Read/
write access from the PCI bus.
BAR1 Register
0x8000040C
Read-only access from the APB bus. Read/
write access from the PCI bus.
PAGE1 Register
0x80000410
Read/write access from the APB bus.
IO Map Register
0x80000414
Read/write access from the APB bus.
Status & Command Register
0x80000418
Read-only access from the APB bus. Read/
write access from the PCI bus.
APBCONF
Address=0x80000400
31 30 29
MMAP
23 22
15 14 13 12 11 10
RESERVED
LTIMER
9
8
7
WE SH BM MS WB RB CTO
0
CLS
Figure 9.13 Configuration/Status Register
Table 9.15 Description of Configuration/Status Register (Read Only)
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-30
MMAP
00
29-23
Reserved
[00...0]
22-15
LTIMER
[00...0]
14
WE
0
DESCRIPTION
Memory Space Map
Maps memory accesses between the PCI master (AHB memory
space) and PCI address space when performing PCI memory
cycles. The PCI address is formed by concatenating MMAP with
AHB address 29:0.
Latency Timer (read only)
Value of Latency Timer in the Configuration Space Header.
Target Write Error (read only)
0: No error
1: Write access to target interface resulted in error
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Chapter 9: PCI Target / Master Unit
Section 9.9: Registers
Table 9.15 Description of Configuration/Status Register (Read Only)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
13
SH
0
System Host (read only)
0: Unit is not system host
1: Unit is system host
12
BM
0
Bus Master (read only)
Value of the Bus Master field in the Command register of the
Configuration Space Header
11
MS
0
Memory Space (read only)
Value of Memory Space field in the Command register of the
Configuration Space Header
10
WB
0
Write Burst Command
Defines the PCI command used for PCI write bursts.
0: Memory Write
1: Memory Write and Invalidate
9
RB
0
Read Burst Command
Defines the PCI command used for PCI read bursts.
0: Memory Read Multiple
1: Memory Read Line
8
CTO
0
Configuration Timeout (read only)
0: No timeout occurred during configuration cycle
1: Timeout occurred during configuration cycle
7-0
CLS
[00...0]
Cache Line Size (read only)
Value of Cache Line Size register in Configuration Space Header.
APBBAR0
Address = 0x80000404
31
21 20
4
BASE_ADDRESS_0
Reserved
3
PR
2
1
TP
0
MS
Figure 9.14 BAR0 Register
Table 9.16 Description of BAR0 Register (Read Only)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-21
BASE_ADDRESS_0
[000...0]
PCI Target Interface Base Address 0
A memory area of 2MB is defined at memory location
BASE_ADDRESS_0. PCI memory accesses to the lower half of this
area are translated to AHB accesses using PAGE0 map register
(Section 9.5).
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Chapter 9: PCI Target / Master Unit
Section 9.9: Registers
Table 9.16 Description of BAR0 Register (Read Only)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
20-4
Reserved
[000...0]
This field can be used to determine the memory requirement of
the target by writing all ‘1s’ to the BAR0 register and reading
back the value. The device returns ‘0s’ in unimplemented bits
positions effectively defining the requested memory area.
Read=00...0b; write=don’t care
3
PR
0
Prefetchable
Read=0; Write=don’t care
2-1
TP
0
Type
Read=0; Write=don’t care
0
MS
00
Memory Space Indicator
Read=0; Write=don’t care
APBPAGE0
Address = 0x80000408
31
20
19
1
PAGE0_MAP
Reserved
0
BTEN
Figure 9.15 PAGE0 Register
Table 9.17 Description of PAGE0 Register (Read Only)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-20
PAGE0_MAP
[000...0]
Maps PCI accesses to the PCI BAR0 address space to the AHB
address space. The AHB address is formed by concatenating
PAGE0_MAP with PCI address AD[19:0].
19-1
Reserved
[000...0]
Read=00...0b; write=don’t care
0
BTEN
1
Byte Twisting Enable
May be altered only when bus mastering is disabled.
0: Disabled
1: Enabled
APBBAR1
Address = 0x8000040C
31
26 25
4
BASE ADDRESS
Reserved
3
PR
2
1
TP
0
MS
Figure 9.16 BAR1 Register
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Chapter 9: PCI Target / Master Unit
Section 9.9: Registers
Table 9.18 Description of BAR1 Register (Read Only)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-26
BASE_ADDRESS_1
[000...0]
PCI Target Interface Base Address 1. A memory area of 64MB is
defined at memory location BASE_ADDRESS_1. PCI memory
accesses to this memory space are translated to AHB accesses
using PAGE1 map register (Section 9.5).
25-4
Reserved
[000...0]
This field can be used to determine the memory requirement of
the target by writing all ‘1s’ to the BAR1 register and reading back
the value. The device returns ‘0s’ in unimplemented bits positions
effectively defining the requested memory area.
Read=00...0b; write=don’t care.
3
PR
0
Prefetchable
Read=0; Write=don’t care.
2-1
TP
0
Type
Read=0; Write=don’t care.
0
MS
0
Memory Space Indicator
Read=0; Write=don’t care.
APBPAGE1
Address = 0x80000410
31
26 25
0
PAGE1_MAP
Reserved
Figure 9.17 PAGE1 Register
Table 9.19 Description of PAGE1 Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-26
PAGE1_MAP
[000...0]
Maps PCI accesses to the PCI BAR1 address space to the AHB
address space. The AHB address is formed by concatenating
PAGE1_MAP with PCI address AD[25:0].
25-0
Reserved
[000...0]
Read=00...0b; write=don’t care
APBIOM
31
Address = 0x80000414
16 15
0
Figure 9.18 I/O Map Register
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Chapter 9: PCI Target / Master Unit
Section 9.9: Registers
IOMAP
RESERVED
Figure 9.18 I/O Map Register
Table 9.20 Description of I/O Map Register (Read Only)
BIT
NUMBER(S)
BIT
NAME
RESET
STATE
DESCRIPTION
31-16
IOMAP
[00...0]
Maps memory accesses between the PCI master (AHB memory
space) and the PCI memory space when performing PCI I/O cycles.
The PCI address is formed by concatenating MMAP with AHB
address 15:0.
15-0
Reserved
[00...0]
APBSTAT
Address = 0x80000418
31
16 15
0
IOMAP
RESERVED
Figure 9.19 I/O Map Register
Table 9.21 Description of Status & Command Register (Read Only)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
DPE
0
30
Reserved
0
29
RMA
0
Received Master Abort
Set by the PCI master interface when its transaction is terminated with Master-Abort.
0: PCI master transaction terminated with no Master-Abort
1: PCI master transaction terminated with Master-Abort
28
RTA
0
Received Target Abort
Set by the PCI master interface when its transaction is terminated with Target-Abort.
0: PCI master transaction terminated with no Target-Abort
1: PCI master transaction terminated with Target-Abort
Clear by writing a "1" to this bit, otherwise this bit is read only.
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DESCRIPTION
Detected Parity Error
0: No parity error detected
1: Parity error detected
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Chapter 9: PCI Target / Master Unit
Section 9.9: Registers
Table 9.21 Description of Status & Command Register (Read Only)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
27
STA
0
Signalled Target Abort
Set by the PCI target interface when the target terminates transaction with
Target-Abort.
0: PCI target terminated with no Target-Abort
1: PCI target terminated with Target-Abort
Clear by writing a "1" to this bit, otherwise this bit is read only.
26-25
DST
10
Device Select Timing
Read=10b; Write=don’t care.
24
DPD
0
Data Parity Error Detected
0: No data parity error detected
1: Data parity error detected
Clear by writing a "1" to this bit, otherwise this bit is read only.
23-5
Reserved
0
4
MIE
0
3
Reserved
0
2
BM
0
Bus Master
Enbales the Master Interface to generate PCI cycles.
0: Disabled
1: Enabled
1
MS
0
Memory Space
Allows the unit to respond to memory space accesses.
0: Disabled
1: Enabled
0
Reserved
0
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DESCRIPTION
Memory Write and Invalidate Enable
Enables the PCI Master interface to generate Memory Write and Invalidate
command.
0: Disabled
1: Enabled
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Chapter 10: DMA Controller for the GRPCI Interface
Section 10.1: Introduction
Chapter 10: DMA Controller for the GRPCI Interface
10.1 Introduction
The DMA controller is an add-on interface to the GRPCI interface. This controller performs bursts to or from the PCI bus
using the master interface of the PCI Target/Master unit.
Figure 10.1 illustrates how the DMA controller is attached between the AHB bus and the PCI master interface.
AMBA bus
AHB
Master
Buffer
Ctrl
DMA Controller
PCI Bridge
Cfg/Stat
AHB Slave
MTx FIFO
AHB Master
MRx FIFO
TTx FIFO
PCI Master
TRx FIFO
PCI Target
PCI Target/Master
PCI off-chip bus
Figure 10.1 DMA Controller Unit
10.2 Operation
The DMA controller is set up by defining the location of memory areas between which the DMA interfaces to both PCI and
AHB address spaces, as well as the direction, length, and type of transfer. Only 32-bit word transfers are supported.
The DMA transfer is automatically aborted when any kind of error is detected during a transfer. In the event of an error, the
ERR bit of the Status and Command Register is set. The DMA controller does not detect deadlocks in its communication
channels. If the system concludes that a deadlock has occurred, it manually aborts the DMA transfer. The DMA controller
may perform bursts over a 1 KB boundary of the AHB bus, which is the maximum data burst that may occur over the bus
per AMBA specification. When the size of the data burst exceeds the 1 KB boundary, AHB idle cycles are automatically
inserted to break up the burst over the boundary.
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Chapter 10: DMA Controller for the GRPCI Interface
Section 10.3: Registers
When the DMA is not active, the AHB slave interface of PCI Target/Master unit directly connects to AMBA AHB bus.
10.3 Registers
The core is programmed through registers mapped into APB address space.
Table 10.1 APB Address Register
Register
APB Address
Command and Status Register (DMASCR)
0x80000500
AMBA Target Address Register (DMAATA)
0x80000504
PCI Target Address Register (DMAPTA)
0x80000508
Burst Length Register (DMALNR)
0x8000050C
DMASCR
Address = 0x80000500
31
8
7
RESERVED
4
TTYPE
3
2
1
0
ERR RDY TD ST
Figure 10.2 Status and Command Register
Table 10.2 Description of Status and Command Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-8
Reserved
[000....00]
7-4
TTYPE
0000
3
ERR
0
Error
Last transfer was abnormally terminated. If set by the
DMA controller, this bit remains one until cleared by writing ‘1’ to it.
2
RDY
0
Ready
Current transfer is completed. When set by the DMA
Controller this bit remains one until cleared by writing ‘1’
to it.
1
TD
0
Transfer Direction
0: Read from PCI
1: Write to PCI
Transfer Type
Perform either PCI memory or I/O cycles
0100b: Perform I/O cycles
1000b: Perform memory cycles
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Chapter 10: DMA Controller for the GRPCI Interface
Section 10.3: Registers
Table 10.2 Description of Status and Command Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
0
ST
0
Start DMA Transfer
Writing ‘1’ starts the DMA transfer. All other registers
must be configured before setting this bit. Set by the PCI
Master interface when its transaction is terminated with
Target-Abort.
DMAATA
Address = 0x80000504
31
0
ATA
Figure 10.3 AMBA Target Address Register
Table 10.3 Description of AMBA Target Address Register
BIT
NUMBER(S)
BIT
NAME
RESET
STATE
DESCRIPTION
31-0
ATA
0x77FF9324
AMBA Target Address
AHB start address for the data on the AMBA bus. In case of error, it
indicates the failing address.
DMAPTA
Address = 0x80000508
31
0
PTA
Figure 10.4 PCI Target Address Register
Table 10.4 Description of PCI Target Address Register
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BIT
NUMBER(S)
BIT
NAME
RESET
STATE
DESCRIPTION
31-0
PTA
[000...00]
PCI Target Address
PCI start address on the PCI bus. This is a complete 32-bit
PCI address and is not further mapped by the PCI Target/
Master unit. In case of error, it indicates the failing
address.
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Chapter 10: DMA Controller for the GRPCI Interface
Section 10.3: Registers
DMALNR
Address = 0x8000050C
31
12 11
RESERVED
0
LEN
Figure 10.5 Burst Length Register
Table 10.5 Description of Burst Length Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-12
Reserved
[000...00]
11-0
LEN
0x933
DESCRIPTION
Burst Length
Number of 32-bit words to be transferred.
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Chapter 11: PCIARB - PCI Arbiter
Section 11.1: Overview
Chapter 11: PCIARB - PCI Arbiter
11.1 Overview
PCIARB is an arbiter for the PCI bus according to the PCI specification version 2.1. It provides 8 REQ/GNT pairs for PCI masters. The arbiter uses nested round-robin policy in two priority levels. The priority assignment is programmable through an
APB interface.
11.2 Operation
11.2.1 Scheduling algorithm
The arbiter uses the algorithm described in the implementation note of section 3.4 of the PCI standard. The bus is granted
by two nested round-robin loops, where an agent number and a priority level is assigned to each agent. The agent number determines which pair of REQ/GNT lines are used. Agents are counted from 0 to 7. All agents in one level have equal
access to the bus through a round-robin policy. All agents of level 1 as a group have access equal to each agent of level 0.
Re-arbitration occurs, when FRAMEN is asserted, as soon as any other master as requested the bus, but only once per
transaction.
The priority level of all agents except 7 is programmable via the priority register at address 0x80000880. Each bit indicates
if the corresponding REQ/GNT pair is assigned to level 1 or 0. The reset value in registers is ‘1’. The arbiter is always enabled.
ARBPRI
Address=0x80000880
31
7
1
6
0
PRI[6:0]
Figure 11.1 Priority Register
11.2.2 Time-out
The “broken master” time-out is another reason for re-arbitration (section 3.4.1 of the PCI standard). Grant is removed from
an agent which has not started a cycle within 16 cycles after request (and grant). Reporting of such a ‘broken’ master is not
implemented.
11.2.3 Turn-around
A turn-around cycle is required by the standard, when re-arbitration occurs during idle state of the bus. The “idle state” is
assumed when FRAMEN is high for more than 1 cycle.
11.2.4 11.2.4 Bus parking
The bus is parked to agent 0 after reset, it remains granted to the last owner if no other agent requests the bus.When
another request is asserted, re-arbitration occurs after one turn-around cycle.
11.2.5 Lock
Lock is defined as a resource lock by the PCI standard. The optional bus lock mentioned in the standard is not considered
here and there are no special conditions to handle when LOCKN is active during an arbitration.
11.2.6 Latency
Latency control in PCI is via the latency counters of each agent. The arbiter does not perform any latency check and a once
granted agent continues its transaction until its grant is removed AND its own latency counter has expired. Even though a
bus re-arbitration occurs during a transaction, the hand-over only becomes effective when the current owner deasserts
PCI_FRAME.
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Section 12.1: Overview
Chapter 12: SpaceWire Interface with RMAP support
(GRSPW2)
12.1 Overview
The SpaceWire core provides an interface between the AHB bus and a SpaceWire network. It implements the SpaceWire
standard (ECSS-E-ST-50-12C) with the protocol identification extension (ECSS-E-ST-50-51C). The Remote Memory Access
Protocol (RMAP) target implements the ECSS standard (ECSS-E-ST-50-52F).
The SpaceWire interface is configured through 11 hardware registers accessed through the APB interface. Data is transferred through DMA channels using an AHB master interface.
There are two clock domains for the four SpaceWire ports: (1) the system clock is utilized for the AHB interface, (2) the
transmitter clock (TxClk) and the receive sample clock comes from the external SPW_CLK pin. For proper operation, the
receiver data rate must be no more than eight times as fast as the system clock and the transmitter clock frequency must
be no more than eight times the system clock. The link frequency must be 10+1 MHz.
TXCLK
D(1:0)
TRANSMITTER
S(1:0)
LINKINTERFACE
FSM
SEND
FSM
TRANSMITTER
FSM
RMAP
TRANSMITTER
TRANSMITTER
DMA ENGINE
AHB
MASTER INTERFACE
RECEIVER
DMA ENGINE
D0
D
PHY
S0
RECEIVER0
RMAP
RECEIVER
RECEIVER
AHB FIFO
RECEIVER1
N-CHAR
FIFO
RECEIVER DATA
PARALLELIZATION
DV
REGISTERS
APB
INTERFACE
D
D1
PHY
S1
DV
Figure 12.1 Block Diagram
12.2 12.2 Operation
12.2.1 Overview
The main sub-blocks of the GRSPW2 are the link interface, the RMAP target and the AMBA interface. A block diagram of the
internal structure can be found in Figure 12.1. The link interface consists of the receiver, transmitter and the link interface
FSM. They handle communication on the SpaceWire network. The AMBA interface consists of the DMA engines, the AHB
master interface and the APB interface. The link interface provides FIFO interfaces to the DMA engines. These FIFOs are
used to transfer N-Chars between the AMBA and SpaceWire domains during reception and transmission.
The RMAP target handles incoming packets which are determined to be RMAP commands instead of the receiver DMA
engine. The RMAP command is decoded and if it is valid, the operation is performed on the AHB bus. If a reply was
requested it is automatically transmitted back to the source by the RMAP transmitter. The GRSPW2 is controlled by writing
to a set of user registers through the APB interface. The link interface, RXDMA engine, TXDMA engine, RMAP target and
AMBA interface are described in section, 12.3, 12.4, 12.5, 12.6 and 12.7 respectively.
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12.2.2 Protocol support
The GRSPW2 only accepts packets with a valid destination address in the first received byte. Packets with address mismatch will be silently discarded (except in promiscuous mode which is covered in section 12.4.10).
The second byte is sometimes interpreted as a protocol ID as described hereafter. The RMAP protocol (ID=0x1) is the only
protocol handled separately in hardware while other packets are stored to a DMA channel. The RMAP target will process,
execute and reply to all RMAP commands automatically controlled by hardware. Otherwise RMAP commands are stored to
a DMA channel in the same way as other packets. RMAP replies are always stored to a DMA channel.
More information on the RMAP protocol support is found in Section 12.6. RMAP is only utilized when the RMAP protocol ID
is included in a packet.
All packets arriving with the extended protocol ID (0x00) are stored to a DMA channel. This means that the hardware RMAP
target will not work if the incoming RMAP packets use the extended protocol ID. Note: Packets with the reserved
extended protocol identifier (ID = 0x000000) are not ignored by the GRSPW2. It is up to the client receiving the packets to
ignore them.When transmitting packets, the address and protocol-ID fields must be included in the buffers from where
data is fetched. They are not automatically added by the GRSPW2.
Figure 12.2 shows the packet types accepted by the GRSPW2. The GRSPW2 also allows reception and transmission with
extended protocol identifiers, but without support for RMAP CRC calculations and the RMAP target.
Addr ProtID D0
D1
D2
D3
.
Dn-2 Dn-1 EOP
D0
D2
D3
D4
.
Dm-2 Dm-1 EOP
Addr
D1
Figure 12.2 The SpaceWire Packet Types Supported by the Core
12.3 Link interface
The link interface handles the communication on the SpaceWire network and consists of a transmitter, receiver, a FSM and
FIFO interfaces. An overview of the architecture is found in Figure 12.1.
12.3.1 Link interface FSM
The FSM controls the link interface (a more detailed description is found in the SpaceWire standard). The low-level protocol handling (the signal and character level of the SpaceWire standard) is handled by the transmitter and receiver while
the exchange level is handled by the FSM.
The link interface FSM is controlled through the control register. The link can be disabled through the link disable bit,
which depending on the current state, either prevents the link interface from reaching the started state or forces it to the
error-reset state. When the link is not disabled, the link interface FSM is allowed to enter the started state when either the
link start bit is set or when a NULL character has been received and the autostart bit is set.
The current state of the link interface determines which type of characters are allowed to be transmitted which together
with the requests made from the host interfaces determine the character sent.Time-codes are sent when the FSM is in the
run-state and a request is made through the time-interface (described in section 12.3.4).
When the link interface is in the connecting- or run-state, it is allowed to send FCTs. FCTs are sent automatically by the link
interface when possible. This is done based on the maximum value of 56 for the outstanding credit counter and the currently free space in the receiver N-Char FIFO. FCTs are sent as long as the outstanding counter is less than or equal to 48
and there are at least 8 more empty FIFO entries than the counter value. N-Chars are sent in the run-state when they are
available from the transmitter FIFO and there are credits available. NULLs are sent when no other character transmission is
requested or the FSM is in a state where no other transmissions are allowed.
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The credit counter (incoming credits) is automatically increased when FCTs are received and decreased when N-Chars are
transmitted. Received N-Chars are stored to the receiver N-Char FIFO for further handling by the DMA interface. Received
Time-codes are handled by the time-interface.
12.3.2 Transmitter
The state of the FSM, credit counters, requests from the time-interface and requests from the DMA-interface are used to
decide the next character to be transmitted. The type of character and the character itself (for N-Chars and Time-codes) to
be transmitted are presented to the low-level transmitter which is located in a separate clock-domain.
This is done to run the SpaceWire link on a different frequency than the host system clock. The GRSPW2 has a separate
clock input which is used to generate the transmitter clock. Since the transmitter often runs on high frequency clocks (up
to 200 MHz), as much logic as possible has been placed in the system clock domain to minimize power consumption and
timing issues.
The transmitter logic in the host clock domain decides what character to send next and sets the proper control signal and
presents any needed character to the low-level transmitter as shown in Figure 12.3. The transmitter sends the requested
characters and generates parity and control bits as needed. If no requests are made from the host domain, NULLs are sent
as long as the transmitter is enabled. Most of the signal and character levels of the SpaceWire standard is handled in the
transmitter. External LVDS drivers are needed for the data and strobe signals.
D
S
Transmitter
Transmitter Clock Domain
Send Time-code
Send FCT
Send NChar
Time-code[7:0]
NChar[8:0]
Host Clock Domain
Figure 12.3 Schematic of the Link Interface Transmitter
A transmission FSM reads N-Chars for transmission from the transmitter FIFO. It is given packet lengths from the DMA
interface and appends EOPs/EEPs and RMAP CRC values, if required. When it is finished with a packet the DMA interface is
12.3.3 Receiver
The receiver data is reconstructed by sampling the data and strobe signals at a sampling rate of 2 times the SPW_CLK frequency. The sampling frequency determines the maximum receive data rate. The maximum receive data rate can be calculated, limited by the maximum SPW_CLK frequency, using the following equation:
SPW_CLK > 3/4 Receive Data Rate(max)
The receiver detects connections from other nodes and receives characters as a bit stream recovered from the data and
strobe signals. The receiver operates in a separate clock domain which runs on a clock translated from the data and strobe
signals. The receiver is activated as soon as the link interface leaves the error reset state. Then after a NULL is received, it
starts receiving any characters. It detects parity, escape and credit errors which causes the link interface to enter the error
reset state. Disconnections are handled in the link interface part in the tx clock domain because no receiver clock is available when disconnected.
Received Characters are flagged to the host domain and the data is presented in parallel form. The interface to the host
domain is shown in Figure 12.4. L-Chars are the handled automatically by the host domain link interface while all N-Chars
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are stored in the receiver FIFO for further handling. If two or more consecutive EOPs/EEPs are received, all but the first are
discarded.
D
Got Time-code
Got FCT
Got EOP
Got EEP
Got NChar
Time-code[7:0]
NChar[7:0]
Receiver
DV
Receiver Clock Domain
Host Clock Domain
Figure 12.4 Schematic of the Link Interface Receiver
12.3.4 Time interface
The time interface is used for sending Time-codes over the SpaceWire network and consists of a time-counter register,
time-ctrl register, tick-in signal, tick-out signal, tick-in register field and a tick-out register field. There are also two control
register bits which enable the time receiver and transmitter respectively.
Each Time-code sent from the GRSPW2 is a concatenation of the time-ctrl and the time-counter register. There is a
timetxen bit which is used to enable Time-code transmissions. It is not possible to send time-codes if this bit is zero.
Received Time-codes are stored to the same time-ctrl and time-counter registers which are used for transmission. The
timerxen bit in the control register is used for enabling time-code reception. No time-codes will be received if this bit is
zero.
The two enable bits are used for ensuring that a node will not (accidentally) both transmit and receive time-codes which
violates the SpaceWire standard. It also ensures that the master sending time-codes on a network will not have its timecounter overwritten if another (faulty) node starts sending time-codes.
The time-counter register is set to 0 after reset and is incremented each time the tick-in signal is asserted for one clockperiod and the timetxen bit is set. This also causes the link interface to send the new value on the network. Tick-in can be
generated either by writing a one to the register field or by asserting the tick-in signal. A Tick-in should not be generated
too often since if the time-code after the previous Tick-in has not been sent, the register will not be incremented and no
new value is sent. The tick-in field is automatically cleared when the value has been sent. Thus, no new ticks should be
generated until this field is zero. If the tick-in signal is used there should be at least 4 system-clock and 25 transmit-clock
cycles between each assertion.
A tick-out is generated each time a valid time-code is received and the timerxen bit is set. When the tick-out is generated,
the tick-out signal asserts one clock-cycle and the tick-out register field is asserted until it is cleared by writing a one to it.
The current time counter value can be read from the time register. It is updated each time a Time-code is received and the
timerxen bit is set. The same register is used for transmissions and can also be written directly from the APB interface.
The control bits of the Time-code are stored to the time-ctrl register when a Time-code is received whose time-count is
one more than the nodes current time-counter register. The time-ctrl register can be read through the APB interface. The
same register is used during time-code transmissions.
It is possible to have both the time-transmission and reception functions enabled at the same time.
12.4 Receiver DMA channels
The receiver DMA engine handles reception of data from the SpaceWire network to different DMA channels.
12.4.1 Address comparison and channel selection
Packets are accepted by different channels based on the address and whether a channel is enabled or not. When the
receiver N-Char FIFO contains one or more characters, N-Chars are read by the receiver DMA engine. The first character is
interpreted as the logical address and is compared with the addresses of each channel starting from 0. The packet is stored
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to the first channel with a matching address. The complete packet including address and protocol ID, but excluding EOP/
EEP, is stored to the memory address pointed to by the descriptors (explained later in this section) of the channel.
Each SpaceWire address register has a corresponding mask register. Only bits at an index containing a zero in the corresponding mask register are compared. This way a DMA channel can accept a range of addresses. There is a default address
register which is used for address checking for RMAP commands in the RMAP target.
If an RMAP command is received, it is only handled by the target if the default address register (including mask) matches
the received address. Otherwise, the packet is stored to a DMA channel if one or more of them has a matching address. If
the address does not match the default address or one of the DMA channels’ separate register, the packet is still handled
by the RMAP target if enabled since it has to return the invalid address error code. The packet is only discarded (up to and
including the next EOP/EEP) if an address match cannot be found and the RMAP target is disabled.
Packets, other than RMAP commands, that do not match the default address register will be discarded. Figure 12.5 shows a
flowchart of packet reception. At least 2 non EOP/EEP N-Chars needs to be received for a packet to be stored to the DMA
channel unless the promiscuous mode is enabled, in which case 1 N-Char is enough. If it is an RMAP packet with hardware
RMAP enabled, 3 N-Chars are needed since the command byte determines where the packet is processed. Packets smaller
than these sizes are discarded.
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Start Reception
Receive
2 bytes
rmap enabled
and
pid =1 and
defaddr*!defmask =
rxaddr*!defmask
No
Yes
Receive
1 byte
No
Set DMA channel
number to 0
RMAP command
Increment
channel number
Yes
No
Yes
No
Channel enabled
Last DMA channel
Yes
No
Separate addressing
RMAP enabled
No
Yes
No
dma(n).addr*
!dma(n).mask=
rxaddr*!dma(n).mask
defaddr*!defmask =
rxaddr*!defmask
No
Yes
Yes
Process RMAP
command
Store packet to
DMA channel
Discard packet
Figure 12.5 Flow Chart of Packet Reception
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12.4.2 Basic link functionality of a channel
Reception is based on descriptors located in a consecutive area in memory that hold pointers to buffers where packets
should be stored. When a packet arrives at the GRSPW2, the channel which should receive it is first determined as
described in the previous section. A descriptor is then read from the channels’ descriptor area and the packet is stored to
the memory area pointed to by the descriptor. Lastly, status is stored to the same descriptor and increments the descriptor
pointer to the next one. The following sections will describe DMA channel reception in more detail.
12.4.3 Setting up the GRSPW2 for reception
A few registers need to be initialized before reception to a channel can take place. First, the link interface needs to be put
in the run state before any data can be sent. The DMA channel has a maximum length register which sets the maximum
packet size in bytes that can be received to this channel. Larger packets are truncated and the unused portion is discarded.
If this happens, an indication will be given in the status field of the descriptor. The minimum value for the receiver maximum length field is 4 and the value can only be incremented in steps of four bytes up to the maximum value 33554428. If
the maximum length is set to zero, the receiver will not function correctly.
Either the default address register or the channel specific address register (the accompanying mask register must also be
set) needs to be set to hold the address used by the channel. A control bit in the DMA channel control register determines
whether the channel should use default address and mask registers for address comparison or the channel’s own registers.
Using the default register, the same address range is accepted as for other channels with default addressing and the RMAP
target, while the separate address provides the channel its own range. If all channels use the default registers they will
accept the same address range and the enabled channel with the lowest number receives the packet.
Finally, the descriptor table and control register must be initialized. This is described in the two following sections.
12.4.4 Setting up the descriptor
The GRSPW2 reads descriptors from an area in memory pointed to by the receiver descriptor register. The register consists
of a base address and a descriptor selector. The base address points to the beginning of the area and must start on a 1024
bytes aligned address. It is also limited to be 1024 bytes in size which means the maximum number of descriptors is 128
since the descriptor size is 8 bytes.
The descriptor selector points to individual descriptors and is increased by 1 when a descriptor has been used. When the
selector reaches the upper limit of the area it wraps to the beginning automatically. It can also be set to wrap at a specific
descriptor before the upper limit by setting the wrap bit in the descriptor. The idea is that the selector should be initialized
to 0 (start of the descriptor area), but it can also be written with another 8 bytes aligned value to start somewhere in the
middle of the area. It will still wrap to the beginning of the area.
If one wants to use a new descriptor table the receiver enable bit has to be cleared first. When the rxactive bit for the channel is cleared it is safe to update the descriptor table register. When this is finished and descriptors are enabled, the
receiver enable bit can be set again.
12.4.5 Enabling descriptors
As mentioned earlier, one or more descriptors must be enabled before reception can take place. Each descriptor is 8 byte
in size and the layout can be found in the tables below. The descriptors should be written to the memory area pointed to
by the receiver descriptor register. When new descriptors are added they must always be placed after the previous one
written to the area. Otherwise, they will not be noticed.
A descriptor is enabled by setting the address pointer to point at a location where data can be stored and then setting the
enable bit. The WR bit can be set to cause the selector to be set to zero when reception has finished to this descriptor. IE
should be set if an interrupt is wanted when the reception has finished. The DMA control register interrupt enable bit must
also be set for an interrupt to be generated.
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The descriptor packet address should be word aligned. All accesses on the bus are word accesses so complete words
always overwritten regardless of whether all 32-bit contain received data. Also, if the packet does not end on a word
boundary, the complete word containing the last data byte will be overwritten.
Offset=0x0
31 30 29 28 27 26 25 24
TR DC HC EP
0
IE WR EN
PACKET_LENGTH
Figure 12.6 SpaceWire Receive Descriptor Word 0
Table 12.1 Description of SpaceWire Receive Descriptor Word 0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
TR
-
Truncated
Packet was truncated due to maximum length violation.
30
DC
-
Data CRC
0: No data CRC error detected
1: Data CRC error detected
29
HC
-
Header CRC
0: No header CRC error detected
1: Header CRC error detected
28
EP
-
EEP Termination
0: Normal packet termination
1: Packet ended with an Error End of Packet character
27
IE
-
Interrupt Enable
0: No interrupt generated upon packet reception
1: An interrupt generates when a packet has been received if the
Receive Enable interrupt bit in the DMA Channel Control and Status
Register is set.
26
WR
-
Wrap
0: DESCRIPTOR_SELECTOR increases by 0x8 to use the descriptor at
the next memory location. The descriptor table is limited to 1 KB in
size and the pointer automatically wraps back to the base address
when it reaches the 1 KB boundary.
1: The next descriptor used by the GRSPW2 will be the first one in the
descriptor table at the base address.
25
EN
-
Enable Descriptor
0: Descriptor disabled
1: Descriptor enabled. This means that the descriptor contains valid
control values and the memory area pointed to by the
PACKET_ADDRESS field can be used to store a packet.
24-0
Packet
Length
[--...-]
The number of bytes received by the buffer. Only valid after EN has
been set to 0 by the GRSPW2.
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Offset=0x4
31
0
PACKET_ADDRESS
Figure 12.7 SpaceWire Receive Descriptor Word 1
Table 12.2 Description of SpaceWire Receive Descriptor Word 1
BIT
NUMBER(S)
31-0
BIT NAME
RESET
STATE
Packet
Address
DESCRIPTION
The address pointing to the buffer which will be
used to store the received packet.
12.4.6 Setting up the DMA control register
The final step to receive packets is to set the control register in the following steps: The receiver must be enabled by setting the rxen bit in the DMA control register (see section 12.9). This can be done anytime and before this bit is set nothing
will happen. The rxdescav bit in the DMA control register is then set to indicate that there are new active descriptors. This
must always be done after the descriptors have been enabled or the GRSPW2 might not notice the new descriptors. More
descriptors can be activated when reception has already started by enabling the descriptors and writing the rxdescav bit.
When these bits are set reception starts immediately when data is arriving.
12.4.7 The effect to the control bits during reception
When the receiver is disabled all packets going to the DMA-channel are discarded if the packet’s address does not fall into
the range of the DMA channel. If the receiver is enabled and the address falls into the accepted address range, the next
state is entered where the rxdescav bit is checked. This bit indicates whether there are active descriptors or not and should
be set by the external application using the DMA channel each time descriptors are enabled as mentioned above. If the
rxdescav bit is ‘0’ and the nospill bit is ‘0’, the packets are discarded. If nospill is one, the GRSPW2 waits until rxdescav is set
and the characters are kept in the N-Char fifo during this time. If the fifo becomes full, further N-char transmissions are
inhibited by stopping the transmission of FCTs.
When rxdescav is set the next descriptor is read and, if enabled, the packet is received to the buffer. If the read descriptor is
not enabled, rxdescav is set to ‘0’ and the packet spills depending on the value of nospill. The receiver can be disabled at
any time and stops packets from being received to this channel. If a packet is currently received when the receiver is disabled,
the reception still finishes. The rxdescav bit can also be cleared at any time. It will not affect any ongoing receptions, but no
more descriptors are read until it is set again. Rxdescav is also cleared by the GRSPW2 when it reads a disabled descriptor.
12.4.8 Status bits
When the reception of a packet is finished, the enable bit in the current descriptor is set to zero. When enable is zero, the
status bits are also valid and the number of received bytes is indicated in the length field. The DMA control register contains a status bit which is set each time a packet has been received. The GRSPW2 can also generate an interrupt for this
event.
The RMAP CRC calculation is always active for all received packets and all bytes except the EOP/EEP are included. The
packet is always assumed to be a RMAP packet and the length of the header is determined by checking byte 3 which
should be the command field. The calculated CRC value is then checked when the header has been received (according to
the calculated number of bytes) and if it is non-zero, the HC bit sets indicating a header CRC error.
The CRC value is not set to zero after the header has been received. Instead, the calculation continues in the same way
until the complete packet has been received. Then, if the CRC value is non-zero, the DC bit sets indicating a data CRC error.
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This means that the GRSPW2 can indicate a data CRC error even if the data field was correct when the header CRC was
incorrect. However, the data should not be used when the header is corrupt; therefore, the DC bit is unimportant in this
case. When the header is not corrupted, the CRC value always is zero when the calculation continues with the data field
and the behaviour will be as if the CRC calculation was restarted
If the received packet is not of RMAP type, the header CRC error indication bit cannot be used. It is still possible to use the
DC bit if the complete packet is covered by a CRC calculated using the RMAP CRC definition. This is because the GRSPW2
does not restart the calculation after the header has been received, but instead calculates a complete CRC over the packet.
Thus, any packet format with one CRC at the end of the packet calculated according to RMAP standard can be checked
using the DC bit. If the packet is neither of RMAP type nor of the type above, with RMAP CRC at the end, then both the HC
and DC bits should be ignored.
12.4.9 Error handling
If a packet reception needs to be aborted because of congestion on the network, the suggested solution is to set link disable to ‘1’. Unfortunately, this also causes the packet currently being transmitted to be truncated, but this is the only safe
solution since packet reception is a passive operation depending on the transmitter at the other end. A channel reset bit
could be provided, but is not a satisfactory solution since the untransmitted characters would still be in the transmitter
node. The next character (somewhere in the middle of the packet) would be interpreted as the node address which would
probably cause the packet to be discarded, but not with 100% certainty. Usually this action is performed when a reception
has stuck because of the transmitter not providing more data. The channel reset would not resolve this congestion.
If an AHB error occurs during reception, the current packet is spilled, up to and including, the next EEP/EOP and then the
currently active channel is disabled and the receiver enters the idle state. A bit in the channels control/status register is set
to indicate this condition.
12.4.10 Promiscuous mode
The GRSPW2 supports a promiscuous mode where all the data received is stored to the first DMA channel enabled regardless of the node address and possible early EOPs/EEPs. This means that all non-eop/eep N-Chars received will be stored to
the DMA channel. The rxmaxlength register is still checked and packets exceeding this size are truncated.
RMAP commands are handled by it when promiscuous mode is enabled if the rmapen bit is set. If it is cleared, RMAP commands are also be stored to a DMA channel.
12.5 Transmitter DMA channels
The transmitter DMA engine handles transmission of data from the DMA channels to the SpaceWire network. Each receive
channel has a corresponding transmit channel which means there can be up to 4 transmit channels. It is only necessary to
use a separate transmit channel for each receive channel if there are also separate entities controlling the transmissions.
The use of a single channel with multiple controlling entities would cause them to corrupt each other’s transmissions. A
single channel is more efficient and should be used when possible.
Multiple transmit channels with pending transmissions are arbitrated in a round-robin fashion.
12.5.1 Basic functionality of a channel
A transmit DMA channel reads data from the AHB bus and stores them in the transmitter FIFO for transmission on the
SpaceWire network. Transmission is based on the same type of descriptors as for the receiver and the descriptor table has
the same alignment and size restrictions. When there are new descriptors enabled, the GRSPW2 reads them and transfers
the amount data indicated.
12.5.2 Setting up the GRSPW2 for transmission
Four steps need to be performed before transmissions can be done with the GRSPW2. First, the link interface must be
enabled and started by writing the appropriate value to the ctrl register. Then, the address to the descriptor table needs to
be written to the transmitter descriptor register and one or more descriptors must also be enabled in the table. Finally, the
txen bit in the DMA control register is written with a one which triggers the transmission. These steps are covered in more
detail in the next sections.
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12.5.3 Enabling descriptors
The descriptor register works in the same way as the receivers corresponding register which was covered in Section 12.4.
The maximum size is 1024 bytes as for the receiver, but since the descriptor size is 16 bytes the number of descriptors is 64.
To transmit packets, one or more descriptors have to be initialized in memory which is done in the following way. The
number of bytes to be transmitted and a pointer to the data has to be set. There are two different length and address fields
in the transmit descriptors because there are separate pointers for header and data. If a length field is zero, the corresponding part of a packet is skipped and, if both are zero, no packet is sent. The maximum header length is 255 bytes and
the maximum data length is 16 Mbyte - 1. When the pointer and length fields have been set, the enable bit should be set
to enable the descriptor. This must always be done last. The other control bits must also be set before enabling the
descriptor.
The transmit descriptors are 16 bytes in size so the maximum number in a single table is 64. The different fields of the
descriptor, together with the memory offsets, are shown in the tables below.
The HC bit should be set if RMAP CRC should be calculated and inserted for the header field and correspondingly, the DC
bit should be set for the data field. The header CRC are calculated from the data fetched from the header pointer and the
data CRC is generated from data fetched from the data pointer. The CRCs are appended after the corresponding fields. The
NON-CRC bytes field is set to the number of bytes in the beginning of the header field that should not be included in the
CRC calculation.
The CRCs are sent even if the corresponding length is zero. When both lengths are zero no packet is sent not even an EOP.
12.5.4 Starting transmissions
When the descriptors have been initialized, the transmit enable bit in the DMA control register has to be set to tell the
GRSPW2 to start transmitting. New descriptors can be activated in the table as needed (while transmission is active). Each
time a set of descriptors is added the transmit enable register bit should be set. This has to be done because each time the
GRSPW2 encounters a disabled descriptor this register bit is set to 0.
Offset=0x0
31
17 16 15 14 13 12 11
RESERVED
CC LE
IE WR EN
8
NON_CRC_
BYTES
7
0
HEADER LENGTH
Figure 12.8 SpaceWire Transmitter Descriptor Word 0
Table 12.3 Description of SpaceWire Transmitter Descriptor Word 0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-17
Reserved
[--...-]
16
CC
-
Calculate CRC
If set, two CRC values will be generated and appended to the
packet according to the RMAP specification. The first CRC is
appended after the data pointed to by the header address field
and the second is appended after the data pointed to by the data
address field.
15
LE
-
Link Error
0: No link error occurred
1: A link error occurred during the transmission of this packet
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Table 12.3 Description of SpaceWire Transmitter Descriptor Word 0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
14
IE
-
Interrupt Enable
0: Disable interrupts
1: An interrupt generates when the packet has been transmitted
and the Transmitter Interrupt TE enable bit in the DMA control
register is set.
13
WR
-
Wrap
0: The descriptor pointer is increased with 0x10 to use the
descriptor at the next higher memory location.
1: The descriptor pointer wraps and the next descriptor read will
be the first one in the table (at the base address).
12
EN
-
Enable
0: Disable transmitter descriptor
1: Enable transmitter descriptor. When all control fields (address,
length, wrap and crc) are set, this bit should be set. While the bit
is set the descriptor should not be modified since this might corrupt the transmission in progress. The GRSPW2 clears this bit
when the transmission has finished.
11-8
NON_CRC_B
YTES
[--...-]
Sets the number of bytes in the beginning of the header which
should not be included in the CRC calculation. This is necessary
when using path addressing since one or more bytes in the
beginning of the packet might be discarded before the packet
reaches its destination.
7-0
HEADER_LE
NGTH
[--...-]
Header length in bytes. If set to zero, the header is skipped.
Offset=0x4
31
0
HEADER_ADDRESS
Figure 12.9 SpaceWire Transmitter Descriptor Word 1
Table 12.4 Description of SpaceWire Transmitter Descriptor Word 1
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-0
HEADER_ADDRESS
[--...-]
DESCRIPTION
Address from where the packet header is fetched.
Does not need to be word aligned.
Offset=0x8
Figure 12.10 SpaceWire Transmitter Descriptor Word 2
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31
24 23
0
RESERVED
DATA_LENGTH
Figure 12.10 SpaceWire Transmitter Descriptor Word 2
Table 12.5 Description of SpaceWire Transmitter Descriptor Word 2
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-24
Reserved
[00...0]
23-0
DATA_LENGTH
[00...0]
DESCRIPTION
Length of data part of the packet in bytes. If set to zero, no data
will be sent. If both data- and header-lengths are set to zero, no
packet will be sent.
Offset=0xC
31
0
DATA_ADDRESS
Figure 12.11 SpaceWire Transmitter Descriptor Word 3
Table 12.6 Description of SpaceWire Transmitter Descriptor Word 3
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-0
DATA_ADDRESS
[00...0]
Address from where data is read. Does not
need to be word aligned.
12.5.5 The transmission process
When the txen bit is set the GRSPW2, starts reading descriptors immediately. The number of bytes indicated are read and
transmitted. When a transmission has finished, status is written to the first field of the descriptor and a packet sent bit is set
in the DMA control register. If an interrupt was requested, it also generates. Then a new descriptor is read and, if enabled, a
new transmission starts; otherwise, the transmit enable bit clears and nothing happens until it is enabled again.
12.5.6 The descriptor register
The internal pointer which is used to keep the current position in the descriptor table can be read and written through the
APB interface. This pointer is set to zero during reset and is incremented each time a descriptor is used. It wraps automatically when the 1024 bytes limit for the descriptor table is reached or it can be set to wrap earlier by setting a bit in the current descriptor.
The descriptor table register can be updated with a new table anytime when no transmission is active. No transmission is
active if the transmit enable bit is zero and the complete table has been sent or if the table is aborted (explained below). If
the table is aborted, one has to wait until the transmit enable bit is zero before updating the table pointer.
12.5.7 Error handling
Abort Tx
The DMA control register contains a bit called Abort TX which if set causes the current transmission to be aborted, the
packet is truncated and an EEP is inserted. This is only useful if the packet needs to be aborted because of congestion on
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the SpaceWire network. If the congestion is on the AHB bus, this will not help. Note: This should not be a problem since
AHB slaves should have a maximum of 16 waitstates). The aborted packet has its LE bit set in the descriptor. The transmit
enable register bit is also cleared and no new transmissions are done until the transmitter is enabled again.
AHB error
When an AHB error is encountered during transmission, the currently active DMA channel is disabled and the transmitter
goes to the idle mode. A bit in the DMA channels control/status register sets to indicate this error condition and, if
enabled, an interrupt will also be generated. Further, error handling depends on what state the transmitter DMA engine
was in when the AHB error occurred. If the descriptor was being read, the packet transmission had not been started yet; no
more actions are needed.
If the AHB error occurs during packet transmission, the packet is truncated and an EEP is inserted. Lastly, if it occurs when
status is written to the descriptor, the packet has been successfully transmitted, but the descriptor is not written and continues to be enabled (this also means that no error bits are set in the descriptor for AHB errors).The client using the channel
has to correct the AHB error condition and enable the channel again. No more AHB transfers are done again from the same
unit (receiver or transmitter) which was active during the AHB error until the error state is cleared and the unit is enabled
again.
Link error
When a link error occurs during the transmission, the remaining part of the packet is discarded up to and including the
next EOP/EEP. When this is done, status is immediately written (with the LE bit set) and the descriptor pointer is incremented. The link will be disconnected when the link error occurs, but the GRSPW2 automatically tries to connect again
provided that the link-start bit is asserted and the link-disabled bit is deasserted. If the LE bit in the DMA channel’s control
register is not set the transmitter DMA engine waits for the link to enter run-state and start a new transmission immediately, when possible, if packets are pending. Otherwise, the transmitter is disabled when a link error occurs during the
transmission of the current packet and no more packets are transmitted until it is enabled again immediately, when possible, if packets are pending.
12.6 RMAP
The Remote Memory Access Protocol (RMAP) is used to implement access to resources in the node via the SpaceWire Link.
Some common operations are reading and writing to memory, registers and FIFOs. This section describes the basics of the
RMAP protocol and the target implementation.
12.6.1 Fundamentals of the protocol
RMAP is a protocol which is designed to provide remote access via a SpaceWire network to memory mapped resources on
a SpaceWire node. It has been assigned protocol ID 0x01. It provides three operations: write, read and read-modify-write.
These operations are posted operations, which means that a source does not wait for an acknowledge or reply. It also
implies that any number of operations can be outstanding at any time, and that no timeout mechanism is implemented in
the protocol. Time-outs must be implemented in the user application which sends the commands. Data payloads of up to
16 MB - 1 is supported in the protocol. A destination can be requested to send replies and to verify data before executing
an operation. A complete description of the protocol is found in the RMAP standard.
12.6.2 Implementation
The GRSPW2 includes a target for RMAP commands which processes all incoming packets with protocol ID = 0x01, type
field (bit 7 and 6 of the 3rd byte in the packet) equal to 01b and an address falling in the range set by the default address
and mask register. When such a packet is detected, it is not stored to the DMA channel, instead it is passed to the RMAP
receiver. The GRSPW2 implements all three commands defined in the standard with some restrictions. Support is only provided for 32-bit big-endian systems. This means that the first byte received is the MSB in a word. The target will not receive
RMAP packets using the extended protocol ID which are always dumped to the DMA channel.
The RMAP receiver processes commands. If they are correct and accepted, the operation is performed on the AHB bus and
a reply is formatted. If an acknowledge is requested, the RMAP transmitter automatically sends the reply. RMAP transmissions have priority over DMA channel transmissions. There is a user accessible destination key register which is compared
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to destination key field in incoming packets. If there is a mismatch and a reply has been requested, the error code in the
reply is set to 3. Replies are sent if and only if the ack field is set to ‘1’.
When a failure occurs during a bus access, the error code is set to 1 (General Error). There is predetermined order in which
error-codes are set in the case of multiple errors in the GRSPW2. It is shown in Table 12.7.
Table 12.7 SpaceWire RMAP Packet Error Codes and Detection Order (Highest Priority is 1)
APPLICABILITY
DETECTION
ORDER
ERROR
CODE
0
0
Command
executed successfully
7*
1
General error
code
7
2
3
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ERROR DESCRIPTION
WRITE
READ
RMW
X
X
X
The detected error does not fit into
the other error cases or the node
does not support further distinction
between the errors
X
X
X
Unused
RMAP Packet
Type or Command Code
The Header CRC was decoded correctly, but the packet type is reserved
or the command is not used by the
RMAP protocol.
X
X
X
3
Invalid key
The Header CRC was decoded correctly, but the device key did not
match that expected by the target
user application.
X
X
X
9
4
Invalid Data
CRC
Error in the CRC of the data field
X
8
5
Early EOP
EOP marker detected before the end
of the data.
X
X
X
12
6
Cargo Too
Large
More than the expected amount of
data in a command has been
received.
X
X
X
8
7
EEP
EEP marker detected immediately
after the header CRC or during the
transfer of data and Data CRC or
immediately thereafter indicates that
there was a communication failure of
some sort on the network.
X
X
X
NA
8
Reserved
Reserved
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Table 12.7 SpaceWire RMAP Packet Error Codes and Detection Order (Highest Priority is 1)
APPLICABILITY
DETECTION
ORDER
ERROR
CODE
4
9
Verify buffer
overrun
The verify before write bit of the
command was set so that the data
field was buffered in order to verify
the Data CRC before transferring the
data to target memory. The data field
was longer than able to fit inside the
verify buffer resulting in a buffer
overrun. Note: The command is not
executed in this case.
X
6
10
Authorization failure
The target user application did not
authorize the requested operation.
This may be because the command
requested has not been implemented.
X
5
11
RMW Data
Length error
The amount of data in a RMW command is invalid (0x01, 0x03, 0x05,
0x07 or greater than 0x08).
1
12
Invalid destination target
logical
address
The Header CRC was decoded correctly but the Target Logical Address
was not the value expected by the
target.
ERROR
ERROR DESCRIPTION
WRITE
READ
RMW
X
X
X
X
X
X
X
Note: *The AHB error is not guaranteed to be detected before Early EOP/EEP or Invalid Data CRC. For very long accesses, the
AHB error detection might be delayed causing the other two errors to appear first.
Read accesses are performed as needed. They are not stored in a temporary buffer before transmitting. This means that
the error code 1 will never be seen in a read reply since the header has already been sent when the data is read. If the AHB
error occurs the packet is truncated and ended with an EEP.
Errors up to, and including Invalid Data CRC (number 8), are checked before verified commands. The other errors do not
prevent verified operations from being performed. The details of the support for the different commands are now presented. All defined commands which are received, but have an option set which is not supported in this specific implementation, will not be executed and a possible reply is sent with error code 10.
12.6.3 Write commands
The write commands are divided into two subcategories when examining their capabilities: verified writes and non-verified writes. Verified writes have a length restriction of 4 bytes and the address must be aligned to the size. That is 1 byte
writes can be done to any address, 2 bytes must be halfword aligned, 3 bytes are not allowed and 4 bytes writes must be
word aligned. Since there will always be only an AHB operation performed for each RMAP verified write command, the
incrementing address bit can be set to any value.
Non-verified writes have no restrictions when the incrementing bit is set to 1. If it is set to 0 the number of bytes must be a
multiple of 4 and the address word aligned. There is no guarantee how many words are written when early EOP/EEP is
detected for non-verified writes.
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12.6.4 Read commands
Read commands are performed as needed when the reply is sent. Thus, if an AHB error occurs, the packet truncates and
ends with an EEP. There are no restrictions for incrementing reads, but non-incrementing reads have the same alignment
restrictions as non-verified writes. Note: The “Authorization failure” error code is sent in the reply if a violation was
detected even if the length field was zero. Also, no data is sent in the reply if an error was detected, i.e. if the status field is
non-zero.
12.6.5 RMW commands
All read-modify-write sizes are supported except 6 which would have caused 3 B being read and written on the bus. The
RMW bus accesses have the same restrictions as the verified writes. As in the verified write case, the incrementing bit can
be set to any value since only one AHB bus operation will be performed for each RMW command. Cargo too large is
detected after the bus accesses so this error will not prevent the operation from being performed. No data is sent in a reply
if an error is detected, i.e., the status field is non-zero.
12.6.6 Control
The RMAP target mostly runs in the background without any external intervention, but there are a few control possibilities.
There is an enable bit in the control register of the GRSPW2 which can be used to completely disable the RMAP target.
When it is set to ‘0’ no RMAP packets will be handled in hardware, instead they are all stored to the DMA channel. There is
a possibility that RMAP commands will not be performed in the order they arrive. This can happen if a read arrives before
one or more writes. Since the target stores replies in a buffer with more than one entry several commands can be processed even if no replies are sent. Data for read replies is read when the reply is sent and thus writes coming after the read
might have been performed already if there was congestion in the transmitter. To avoid this, the RMAP buffer disable bit
can be set to force the target to only use one buffer which prevents this situation.
The last control option for the target is the possibility to set the destination key which is found in a separate register.
Table 12.8 GRSPW2 Hardware RMAP Handling of Different Packet Type and Command Fields
PACKET TYPE
RMAP COMMAND CODES
COMMAND
ACTION
BIT 7
BIT6
BIT 5
BIT4
BIT 3
BIT 2
Reserve
d
Comman
d/
Response
Write
/Read
Verify
data
before
write
Acknow
-ledge
Increment
Address
0
0
-
-
-
-
Response
Stored to DMA-channel
0
1
0
0
0
0
Not used
Does nothing. No reply is
sent.
0
1
0
0
0
1
Not used
Does nothing. No reply is
sent.
0
1
0
0
1
0
Read single
address
Executed normally.
Address has to be word
aligned and data size a
multiple of four. Reply is
sent. If alignment restrictions are violated error
code is set to 10.
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Table 12.8 GRSPW2 Hardware RMAP Handling of Different Packet Type and Command Fields
PACKET TYPE
RMAP COMMAND CODES
COMMAND
ACTION
BIT 7
BIT6
BIT 5
BIT4
BIT 3
BIT 2
Reserve
d
Comman
d/
Response
Write
/Read
Verify
data
before
write
Acknow
-ledge
Increment
Address
0
1
0
0
1
1
Read incrementing
address.
Executed normally. No
restrictions. Reply is sent.
0
1
0
1
0
0
Not used
Does nothing. No reply is
sent.
0
1
0
1
0
1
Not used
Does nothing. No reply is
sent.
0
1
0
1
1
0
Not used
Does nothing. Reply is
sent with error code 2.
0
1
0
1
1
1
Read-ModifyWrite incrementing
address
Executed normally. If
length is not one of the
allowed RMW values nothing is done and error code
is set to 11. If the length
was correct, alignment
restrictions are checked
next. 1 byte can be RMW
to any address. 2 bytes
must be halfword aligned.
3 bytes are not allowed. 4
bytes must be word
aligned. If these restrictions are violated nothing
is done and error code is
set to 10. If an AHB error
occurs error code is set to
1. Reply is sent.
0
1
1
0
0
0
Write, singleaddress, do not
verify before
writing, no
acknowledge
Executed normally.
Address has to be word
aligned and data size a
multiple of four. If alignment is violated nothing is
done. No reply is sent.
0
1
1
0
0
1
Write, incrementing
address, do not
verify before
writing, no
acknowledge
Executed normally. No
restrictions. No reply is
sent.
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Table 12.8 GRSPW2 Hardware RMAP Handling of Different Packet Type and Command Fields
PACKET TYPE
RMAP COMMAND CODES
COMMAND
ACTION
BIT 7
BIT6
BIT 5
BIT4
BIT 3
BIT 2
Reserve
d
Comman
d/
Response
Write
/Read
Verify
data
before
write
Acknow
-ledge
Increment
Address
0
1
1
0
1
0
Write, singleaddress, do not
verify before
writing, send
acknowledge
Executed normally.
Address has to be word
aligned and data size a
multiple of four. If alignment is violated nothing is
done and error code is set
to 10. If an AHB error
occurs error code is set to
1. Reply is sent.
0
1
1
0
1
1
Write, incrementing
address, do not
verify before
writing, send
acknowledge
Executed normally. No
restrictions. If AHB error
occurs error code is set to
1. Reply is sent.
0
1
1
1
0
0
Write, single
address, verify
before writing,
no acknowledge
Executed normally.
Length must be 4 or less.
Otherwise nothing is
done. Same alignment
restrictions apply as for
RMW. No reply is sent.
0
1
1
1
0
1
Write, incrementing
address, verify
before writing,
no acknowledge
Executed normally.
Length must be 4 or less.
Otherwise nothing is
done. Same alignment
restrictions apply as for
RMW. If they are violated
nothing is done. No reply
is sent.
0
1
1
1
1
0
Write, single
address, verify
before writing,
send acknowledge
Executed normally.
Length must be 4 or less.
Otherwise nothing is
done and error code is set
to 9. Same alignment
restrictions apply as for
RMW. If they are violated
nothing is done and error
code is set to 10. If an AHB
error occurs error code is
set to 1. Reply is sent.
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Table 12.8 GRSPW2 Hardware RMAP Handling of Different Packet Type and Command Fields
PACKET TYPE
RMAP COMMAND CODES
COMMAND
ACTION
BIT 7
BIT6
BIT 5
BIT4
BIT 3
BIT 2
Reserve
d
Comman
d/
Response
Write
/Read
Verify
data
before
write
Acknow
-ledge
Increment
Address
0
1
1
1
1
1
Write, incrementing
address, verify
before writing,
send acknowledge
Executed normally.
Length must be 4 or less.
Otherwise nothing is
done and error code is set
to 9. Same alignment
restrictions apply as for
RMW. If they are violated
nothing is done and error
code is set to 10. If an AHB
error occurs error code is
set to 1. Reply is sent.
1
0
-
-
-
-
Unused
Stored to DMA-channel.
1
1
-
-
-
-
Unused
Stored to DMA-channel.
12.7 AMBA interface
The AMBA interface consists of an APB interface, an AHB master interface and DMA FIFOs. The APB interface provides
access to the user registers which are described in section 12.9. The DMA engines have 32-bit wide FIFOs to the AHB master interface which are used when reading and writing to the bus.The transmitter DMA engine reads data from the bus in
bursts which are half the FIFO size in length. A burst is always started when the FIFO is half-empty or if it can hold the last
data for the packet. The burst containing the last data might have shorter length if the packet is not an even number of
bursts in size.
The receiver DMA works in the same way except that it checks if the FIFO is half-full and then performs a burst write to the
bus which is half the fifo size in length. The last burst might be shorter. If the rmap or rxunaligned VHDL generics are set to
1, the interface also handles byte accesses. Byte accesses are used for non word-aligned buffers and/or packet lengths that
are not a multiple of four bytes. There might be 1 to 3 single byte writes when writing the beginning and end of the
received packets.
12.7.1 APB slave interface
As mentioned above, the APB interface provides access to the user registers which are 32-bits in width. The accesses to this
interface are required to be aligned word accesses. The result is undefined if this restriction is violated.
12.7.2 AHB master interface
The GRSPW2 contains a single master interface which is used by both the transmitter and receiver DMA engines. The arbitration algorithm between the channels is done so that if the current owner requests the interface again, it will always
acquire it. This will not lead to starvation problems since the DMA engines always deassert their requests between
accesses.
The AHB accesses can be of size byte, halfword and word (HSIZE = 0x000, 0x001, 0x010) otherwise. Byte and halfword
accesses are always NONSEQ.
Note: Read accesses are always word accesses (HSIZE=0x010), which can result in a destructive read.
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The burst length will be half the AHB FIFO size except for the last transfer for a packet which might be smaller. Shorter
accesses are also done during descriptor reads and status writes.
The AHB master also supports non-incrementing accesses where the address will be constant for several consecutive
accesses. HTRANS will always be NONSEQ in this case while for incrementing accesses it is set to SEQ after the first access.
This feature is included to support non-incrementing reads and writes for RMAP.
If the GRSPW2 does not need the bus after a burst has finished, there will be one wasted cycle (HTRANS = IDLE).
BUSY transfer types are never requested and the GRSPW2 provides full support for ERROR, RETRY and SPLIT responses.
12.8 SpaceWire clock generation
The clock source for SpaceWire core is the SPW_CLK input.
The SpaceWire transmit clock must be a multiple of 10 MHz in order to achieve the 10 MHz start up frequency. The division
to 10 MHz is done internally in the GRSPW2 core. During reset the clock link divider register in GRSPW2 gets its value from
GPIO[7:4], which must be pulled up/down to set the divider correctly. Thus, it is possible to use a SPW_CLK which is any
multiple of 10 between 10-150 MHz. Note: The required precision is 10 MHz +/- 1 MHz.
12.9 Registers
The UT700 has four SpaceWire nodes, each comprised of a GRSPW2 core. Each core has its own set of registers mapped
into APB memory space. The APB address mapping for each GRSPW2 core is listed in Table 97. The relative offset of each
register is shown in Table 12.9 below. All GRSPW2 cores have RMAP functionality, so any RMAP registers apply to these
cores.
Table 12.9 GRSPW2 Registers
APB ADDRESS
OFFSET
REGISTER
94-00-00-000
Ver. 1.1.0
SPW Control Register (SPWCTR)
0x0
SPW Status Register (SPWSTR)
0x4
SPW Node Address Register (SPWNDR)
0x8
SPW Clock Divisor Register (SPW_CLK)
0xC
SPW Destination Key Register (SPWKEY)
0x10
SPW Time Register (SPWTIM)
0x14
Reserved
0x18
SPW DMA Channel Control and Status Register (SPWCHN)
0x20
SPW DMA Channel Receiver Maximum Length Register (SPWRXL)
0x24
SPW DMA Transmit Descriptor Register (SPWTXD)
0x28
SPW DMA Receive Descriptor Register (SPWRXD)
0x2C
SPW DMA Receive Description Register (SPWRXD)
0x2C
DMA Channel address register
0x30
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Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
SPWCTR
Address=0x80000[A/B/C/D]00
31 30 29 28 27 26 25
RA RX RC
RES
PO
23
22
21
RESERVED LOOP
18 17 16 15
RESERVED
RD RE
12 11 10
9
8
7
TR
LI
TQ
--
RESERVED
TT
6
5
4
3
RS OPM TI
IE
2
1
31
AS LS RA
Figure 12.12 SPW Control Register
Table 12.10 Description of SPW Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
RA
1
RMAP Available
0: RMAP unavailable
1: Set to one if the RMAP command handler is available
Read=0; Write=don’t care
30
RX
0
RX Unaligned Access
0: Unaligned writes not available for the receiver
1: Unaligned writes available for the receiver
Read=0; Write=don’t care
29
RC
1
RMAP CRC Available
0: RMAP CRC not available
1: RMAP CRC available
Read=0; Write=don’t care.
28-27
Reserved
00
26
PO
0
25-23
Reserved
000
22
Loop
0
21-18
Reserved
0000
17
RD
0
RMAP Buffer Disable
0: All RMAP buffers are used
1: Only one RMAP buffer is used. This ensures that all RMAP commands are executed consecutively.
16
RE
1
RMAP Enable
0: Disable RMAP command handler
1: Enable RMAP command handler
15-12
Reserved
0000
11
TR
0
94-00-00-000
Ver. 1.1.0
DESCRIPTION
Number of available SpaceWire ports minus 1
Port loop back:
0: Loop back disable
1: Tx is internally looped to Rx
Time RX Enable
0: Disable time-code receptions
1: Enable time-code receptions
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Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
Table 12.10 Description of SPW Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
10
TT
0
Time TX Enable
0: Disable time-code transmissions
1: Enable time-code transmissions
9
LI
-
Link Error IRQ
0: No interrupt
1: Generate interrupt when a link error occurs. Not reset.
8
TQ
-
Tick-Out IRQ
0: No interrupt
1: Generate interrupt when a valid time-code is received. Not reset.
7
Reserved
0
6
RS
0
Reset
0: No action
1: Make complete reset of the SpaceWire node. Self clearing.
5
OPM
0
Open Packet Mode
0: Disable open-packet mode
1: Enable open packet mode
4
TI
0
Tick In
The host can generate a tick by writing a one to this field. This increments the timer counter and the new value is transmitted after the
current character is transferred.
3
IE
0
Interrupt Enable
0: No interrupt
1: Interrupt is generated when bits 8 or 9 is set and its corresponding event occurs.
2
AS
-
Autostart
0: No effect
1: Automatically start the link when a NULL has been received. Not
reset.
1
LS
1
Link Start
0: No effect
1: Start the link, i.e., allow a transition from ready to started state.
0
LD
0
Link Disable
0: No effect
1: Disable the SpaceWire codec.
SPWSTR
31
Address=0x80000[A/B/C/D]04
24 23
21 20
9
8
7
6
5
4
3
2
1
0
Figure 12.13
94-00-00-000
Ver. 1.1.0
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Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
RESERVED
LS
RESERVED
EE
IA
--
--
PE DE ER CE TO
Figure 12.13
Table 12.11 Description of SPW Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-24
Reserved
[000...0]
23-21
LS
20-9
Reserved
Link State
This field indicates the current state of the start-up sequence.
0: Error-reset
1: Error-wait
2: Ready
3: Started
4: Connecting
5: Run
[000...0]
8
EE
0
Early EOP/EEP
Read:
0: Packet received normally
1: Packet was received with an EOP after the first byte for a nonRMAP packet or after the second byte for a RMAP packet.
Write:
0: No effect
1: Clear bit
7
IA
0
Invalid Address
Read:
0: Packet received normally
1: Packet was received with an invalid destination address field
Write:
0: No effect
1: Clear bit
Reserved
00
PE
0
6-5
4
94-00-00-000
Ver. 1.1.0
000
DESCRIPTION
Parity Error
Read:
0: Packet received normally
1: A parity error has occurred
Write:
0: No effect
1: Clear bit
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Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
Table 12.11 Description of SPW Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
3
DE
0
Disconnect Error
Read:
0: No disconnection error
1: A disconnection error has occurred
Write:
0: No effect
1: Clear bit
2
ER
0
Escape Error
Read:
0: No escape error
1: An escape error has occurred
Write:
0: No effect
1: Clear bit
1
CE
0
Credit Error
Read:
0: No credit error
1: A credit has occurred
Write:
0: No effect
1: Clear bit
0
TO
0
Tick Out
Read:
0: No new time count
1: A new time count value was received and is stored in the time
counter field.
Write:
0: No effect
1: Clear bit
SPWNDR
Address=0x80000[A/B/C/D]08
31
16 15
RESERVED
8
7
ADDRESS_MASK
0
NODE_ ADDRESS
Figure 12.14 SPW Node Address Register
Table 12.12 Description of SPW Node Address Register
94-00-00-000
Ver. 1.1.0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[---...--]
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DESCRIPTION
Aeroflex Microelectronic Solutions - HiRel
Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
Table 12.12 Description of SPW Node Address Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
15-8
ADDRESS_MASK
[000...0]
Used for masking the address before comparison.
Both the received address and the NODE_ADDRESS
fields are logically ended with the inverse of
ADDRESS_MASK before the address check.
7-0
NODE_ADDRESS
254
8-Bit Node Address
Used for node identification on the SpaceWire network.
SPW_CLK
Address=0x80000[A/B/C/D]0C
31
16 15
RESERVED
8
7
CLOCK_DIVISOR_LINK
0
CLOCK_DIVISOR_RUN
Figure 12.15 SPW Clock Divisor Register
Table 12.13 Description of SPW Clock Divisor Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-16
Reserved
[000...0]
15-8
CLOCK_DIVISOR_LINK
0
8-Bit Clock Divisor Link State Value
Used for the clock-divider when the link interface is in the
startup-state. Actual divisor value = (CLOCK_DIVISOR_LINK
+ 1).
7-0
CLOCK_DIVISOR_RUN
0
8-Bit Clock Divisor Run State Value
Used for the clock-divider when the link interface is in the
run-state. Actual divisor value = (CLOCK_DIVISOR_RUN +
1).
SPWKEY
Address=0x80000[A/B/C/D]10
31
8
RESERVED
7
0
DESTINATION_KEY
Figure 12.16 SPW Destination Key Register
94-00-00-000
Ver. 1.1.0
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Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
Table 12.14 Description of SPW Destination Key Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...0]
7-0
DESTINATION_KEY
[000...0]
DESCRIPTION
RMAP Destination Key
SPWTIM
Address=0x80000[A/B/C/D]14
31
8
7
6
5
TIME_CT
RL
RESERVED
0
TIME_COUNTER
Figure 12.17 SPW Time Register
Table 12.15 Description of SPW Time Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-8
Reserved
[000...0]
7-6
TIME_CTRL
0
Time Control Flags
The current value of the time control flags. Sent with time-code
resulting from a tick-in. Received control flags are also stored in
this field.
5-0
TIME_COUNTER
0
Time Counter
The counter represents the system time count. The counter is
incremented each time a time code is received and decoded into
a tick-out or when the host writes to the tick-in bit.
SPWCHN
Address=0x80000[A/B/C/D]20
31
16 15 14 13 12 11 10
RESERVED
LE
9
8
7
6
5
SP SA EN NS RD RX AT RA TA PR PS
4
3
2
AI
RI
TI
1
0
RE TE
Figure 12.18 SPW DMA Channel Control and Status Register
Table 12.16 Description of SPW DMA Channel Control and Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-17
Reserved
[000...0]
16
LE
0
94-00-00-000
Ver. 1.1.0
DESCRIPTION
Link error disable
Disable transmitter when a link error occurs. No more packets are transmitted until the transmitter is enabled again.
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Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
Table 12.16 Description of SPW DMA Channel Control and Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
15
SP
0
Strip pid
Remove the pid byte (second byte) of each packet. The address byte (first
byte) is also removed when this bit is set independent of the SA bit.
14
SA
0
Strip addr
Remove the addr byte (first byte) of each packet.
13
EN
0
Enable addr
Enable separate node address for this channel.
12
NS
0
No Spill
0: If cleared, packets are discarded when a packet is arriving and there are
no active descriptors.
1: If set, the GRSPW2 waits for a descriptor to be activated
11
RD
0
RX Descriptors Available
Read:
0: Cleared by GRSPW2 when it encounters a disabled descriptor.
1: Indicates enabled descriptors in the descriptor table.
Write:
0: No active descriptors in the descriptor table.
1: Set to one to indicate to the GRSPW2 that there are enabled descriptors
in the descriptor table.
10
RX
0
RX Active
0: No DMA channel activity
1: Set if a reception to the DMA channel is currently active.
9
AT
0
Abort TX
0: No effect
1: Setting the bit aborts the currently transmitting packet and disable
transmissions. If no transmission is active, the only effect is to disable
transmissions. Self clearing.
8
RA
0
RX AHB Error
0: No error response
1: An error response was detected on the AHB bus while this receive DMA
channel was accessing the bus. Cleared when written with a one.
7
TA
0
TX AHB Error
0: No error response
1: An error response was detected on the AHB bus while this transmit DMA
channel was accessing the bus. Cleared when written with a one.
6
PR
0
Packet Received
0: No new packet
1: This bit is set each time a packet has been received. Not self clearing.
Cleared when written with a one.
94-00-00-000
Ver. 1.1.0
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Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
Table 12.16 Description of SPW DMA Channel Control and Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
5
PS
0
Packet Sent
0: No packet sent
1: This bit is set each time a packet has been sent. Not self clearing. Cleared
when written with a one.
4
AI
-
AHB Error Interrupt
0: No interrupt will be generated
1: If set, an interrupt generates each time an AHB error occurs when this
DMA channel is accessing the bus. Not reset.
3
RI
-
Receive Interrupt
0: No interrupt will be generated
1: If set, an interrupt generates each time a packet has been received. This
happens if either the packet is terminated by an EEP or EOP. Not reset.
2
TI
-
Transmit Interrupt
0: No interrupt generates
1: If set, an interrupt generates each time a packet is transmitted. The
interrupt is generated regardless of whether the transmission was successful or not. Not reset.
1
RE
0
Receiver Enable
0: Channel is not allowed to receive packets
1: Channel is allowed to receive packets
0
TE
0
Transmitter Enable
Read:
0: Cleared by GRSPW2 when it encounters a disabled descriptor.
1: Indicates enabled descriptors in the descriptor table.
Write:
0: No active descriptors in the descriptor table.
1: Set to one to indicate to the GRSPW2 that there are enabled descriptors
in the descriptor table. Writing a one will cause the GRSPW2 to read a new
descriptor and try to transmit the packet to which it points.
SPWRXL
31
Address=0x80000[A/B/C/D]24
25 24
0
RESERVED
RX_MAX_LENGTH
Figure 12.19 SPW DMA Channel Receiver Max Length
94-00-00-000
Ver. 1.1.0
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Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
Table 12.17 Description of SPW DMA Channel Receiver Max Length Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-25
Reserved
[000...0]
24-0
RX_MAX_LENGTH
[---...-]
DESCRIPTION
Receiver Packet Maximum Length
The maximum number of bytes in a packet that may be received.
Only bits 24-2 are writable. Bits 1-0 always read 0. Not reset.
SPWTXD
Address=0x80000[A/B/C/D]28
31
10
9
TX_BASE_ADDRESS
4
3
TX_DESC_SELECT
0
RES
Figure 12.20 SPW Transmitter Descriptor Register
Table 12.18 Description of SPW Transmitter Descriptor Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-10
TX_BASE_ADDRESS
[--...-]
9-4
TX_DESC_SELECT
0
3-0
Reserved
[000]
DESCRIPTION
Transmitter Descriptor Table Base Address
Sets the base address of the descriptor table. Not reset.
Transmitter Descriptor Selector
This is the relative offset into the descriptor table and indicates
which descriptor is currently used by the GRSPW2. For each
new descriptor read, TX_DESC_SELECT increases by one and
wrap to zero when the field increments to 64.
SPWRXD
Address=0x80000[A/B/C/D]2C
31
10
RX_BASE_ADDRESS
9
3
RX_DESC_SELECT
2
0
RES
Figure 12.21 SPW Receiver Descriptor Register
94-00-00-000
Ver. 1.1.0
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Chapter 12: SpaceWire Interface with RMAP support (GRSPW2)
Section 12.9: Registers
Table 12.19 Description of SPW Receiver Descriptor Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-10
RX_BASE_ADDRESS
[--...-]
9-3
RX_DESC_SELECT
0
2-0
Reserved
[00]
94-00-00-000
Ver. 1.1.0
DESCRIPTION
Receiver Descriptor Table Base Address
Sets the base address of the descriptor table. Not reset.
Receiver Descriptor Selector
This is the relative offset into the descriptor table and indicates
which descriptor is currently used by the GRSPW2. For each new
descriptor read, RX_DESC_SELECT will increase by one and
wrap to zero when the field increments to 64.
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Aeroflex Microelectronic Solutions - HiRel
Chapter 13: CAN-2.0 Interface
Section 13.1: Overview
Chapter 13: CAN-2.0 Interface
13.1 Overview
The CAN-2.0 interfaces in UT700 is based on the CAN core from Opencores with an AHB slave interface for accessing all
CAN core registers. The CAN core is a derivative of the Philips SJA1000 and has a compatible register map with a few
exceptions. Each CAN core is capable of up to 1Mb/s band rate. These exceptions are indicated in the register description
tables and in Section 13.6. The CAN core supports both BasicCAN and PeliCAN modes. In PeliCAN mode the extended features of CAN 2.0B are supported. The mode of operation is chosen through the clock divider register.
CAN Core with AHB
CAN_TXO
Buffer RAM
CAN Core
CAN_RXI
AHB slave interface
IRQ
AMBA AHB
Figure 13.1 CAN Core Block Diagram
This chapter lists the CAN core registers and their functionality. The Philips SJA1000 data sheet can be used as an additional reference, except as noted in Section 13.6.
The register map and functionality is different depending upon which mode of operation is selected. BasicCAN mode will
be described in Section 13.3, followed by PeliCAN in Section 13.4. The common registers (Clock Divisor and Bus Timing) are
described in Section 13.5. The register map also differs depending on whether the core is in operating mode or in reset
mode. After reset, the CAN core starts up in reset mode awaiting configuration. Operating mode is entered by clearing the
Reset Request (CR.0) bit in the Control Register. Set the bit to re-enter reset mode.
The UT700 implements two identical instances of the Opencores CAN core. Both operate completely independent of each
other. The AHB register mapping for each core is indicated in Table 1.3 of Section 1.4 of this manual.
13.2 AHB interface
All registers are one byte wide and the addresses specified in this document are byte addresses. Byte reads and writes
should be used when interfacing with this core. The read byte is duplicated on all byte lanes of the AHB bus. The interface
is big endian so the core expects the MSB at the lowest address.
The bit numbering in this document uses bit 7 as the MSB and bit 0 as the LSB.
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Ver. 1.1.0
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Chapter 13: CAN-2.0 Interface
Section 13.3: 13.3 BasicCAN mode
13.3 13.3 BasicCAN mode
13.3.1 BasicCAN register map (Address 0xFFF20000 and 0xFFF20100)
Table 13.1 Basic CAN Address Allocation
ADDRESS
OPERATING MODE
Read
94-00-00-000
Ver. 1.1.0
Write
RESET MODE
Read
Write
0
Control
Control
Control
Control
1
(0xFF)
Command
(0xFF)
Command
2
Status
-
Status
-
3
Interrupt
-
Interrupt
-
4
(0xFF)
-
Acceptance
Code
Acceptance
Code
5
(0xFF)
-
Acceptance
Mask
Acceptance
Mask
6
(0xFF)
-
Bus Timing 0
Bus Timing 0
7
(0xFF)
-
Bus Timing 1
Bus Timing 1
8
(0x00)
-
(0x00)
-
9
(0x00)
-
(0x00)
-
10
TX ID1
TX ID1
(0xFF)
-
11
TX ID2, rtr, dlc
TX ID2, rtr, dlc
(0xFF)
-
12
TX Data Byte 1
TX Data Byte 1
(0xFF)
-
13
TX Data Byte 2
TX Data Byte 2
(0xFF)
-
14
TX Data Byte 3
TX Data Byte 3
(0xFF)
-
15
TX Data Byte 4
TX Data Byte 4
(0xFF)
-
16
TX Data Byte 5
TX Data Byte 5
(0xFF)
-
17
TX Data Byte 6
TX Data Byte 6
(0xFF)
-
18
TX Data Byte 7
TX Data Byte 7
(0xFF)
-
19
TX Data Byte 8
TX Data Byte 8
(0xFF)
-
20
RX ID1
-
RX ID1
-
21
RX ID2, rtr, dlc
-
RX ID2, rtr, dlc
-
22
RX Data Byte 1
-
RX Data Byte 1
-
23
RX Data Byte 2
-
RX Data Byte 2
-
24
RX Data Byte 3
-
RX Data Byte 3
-
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Aeroflex Microelectronic Solutions - HiRel
Chapter 13: CAN-2.0 Interface
Section 13.3: 13.3 BasicCAN mode
Table 13.1 Basic CAN Address Allocation
ADDRESS
OPERATING MODE
Read
RESET MODE
Write
Read
Write
25
RX Data Byte 4
-
RX Data Byte 4
-
26
RX Data Byte 5
-
RX Data Byte 5
-
27
RX Data Byte 6
-
RX Data Byte 6
-
28
RX Data Byte 7
-
RX Data Byte 7
-
29
RX Data Byte 8
-
RX Data Byte 8
-
30
(0x00)
-
(0x00)
-
31
Clock Divider
Clock Divider
Clock Divider
Clock Divider
13.3.2 Control register
The Control Register contains interrupt enable bits as well as the reset request bit.
Table 13.2 Bit Interpretation of Control Register (CR) (Address 0)
BIT
NAME
DESCRIPTION
CR.7
-
Reserved
CR.6
-
Reserved
CR.5
-
Reserved
CR.4
Overrun Interrupt Enable
1 - enabled, 0 - disabled
CR.3
Error Interrupt Enable
1 - enabled, 0 - disabled
CR.2
Transmit Interrupt Enable
1 - enabled, 0 - disabled
CR.1
Receive Interrupt Enable
1 - enabled, 0 - disabled
CR.0
Reset request
Writing 1 to this bit aborts any ongoing transfer and enters
reset mode. Writing 0 returns to operating mode.
13.3.3 Command register
Writing a one to the corresponding bit in this register initiates an action supported by the core.
Table 13.3 Bit interpretation of Command Register (CMR) (Address 1)
94-00-00-000
Ver. 1.1.0
BIT
NAME
DESCRIPTION
CMR.7
-
Reserved
CMR.6
-
Reserved
CMR.5
-
Reserved
CMR.4
-
Not used (go to sleep in SJA1000 core)
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Chapter 13: CAN-2.0 Interface
Section 13.3: 13.3 BasicCAN mode
Table 13.3 Bit interpretation of Command Register (CMR) (Address 1)
BIT
NAME
DESCRIPTION
CMR.3
Clear Data Overrun
Clear the Data Overrun status bit
CMR.2
Release Receive Buffer
Free the current receive buffer for new reception
CMR.1
Abort Transmission
Aborts a transmission that has not yet started
CMR.0
Transmission Request
Starts the transfer of the message in the TX buffer
A transmission is started by writing a ‘1’ to CMR.0. It can only be aborted by writing ‘1’ to CMR.1 and only if the transfer has
not yet started. If the transmission has started it will not be aborted when setting CMR.1, but it will not be retransmitted if
an error occurs.
Release the receive buffer by setting the Release Receive Buffer bit (CMR.2) after reading the contents of the receive buffer.
If there is another message waiting in the FIFO, a new receive interrupt will be generated if enabled by setting the Receive
Interrupt bit (IR.0), and the Receive Buffer Status (SR.0) bit will be set again. Set the Clear Data Overrun bit (CMR.3) to clear
the Data overrun status bit.
13.3.4 Status register
The status register is read only and reflects the current status of the core.
Table 13.4 Bit Interpretation of Status Register (SR) (Address 2)
BIT
NAME
DESCRIPTION
SR.7
Bus Status
1 when the core is in the bus-off state and is not allowed to
have any influence on the bus
SR.6
Error Status
At least one of the error counters have reached or
exceeded the CPU warning limit (96)
SR.5
Transmit Status
1 when transmitting a message
SR.4
Receive Status
1 when receiving a message
SR.3
Transmission Complete
SR.2
Transmit Buffer Status
SR.1
Data Overrun Status
1 if a message was lost because of no space in the FIFO
SR.0
Receive Buffer Status
1 if messages are available in the receive FIFO
1 indicates the last message was successfully transferred.
1 means CPU can write into the transmit buffer
Receive buffer status is cleared when the Release Receive Buffer command (CMR.2) is given and is set if there are more
messages available in the FIFO. The Data Overrun Status (SR.1) signals that a message that was accepted could not be
placed in the receive FIFO because there was not enough space left. Note: This bit differs from the SJA1000 behavior and is
set when the FIFO has been read out. When the Transmit Buffer Status is high, the transmit buffer can be written to by the
CPU. During an on-going transmission the buffer is locked and this bit is 0. The Transmission Complete bit is cleared when
a transmission request has been issued and will not be set again until a message has successfully been transmitted.
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Section 13.3: 13.3 BasicCAN mode
13.3.5 Interrupt register
The interrupt register signals to the CPU what caused the interrupt. The interrupt bits are only set if the corresponding
interrupt enable bit is set in the control register.The interrupt assignment for both CAN cores is shown in Table 1.4 of Section 1.5.
Table 13.5 Bit Interpretation of Interrupt Register (IR) (Address 3)
BIT
NAME
DESCRIPTION
IR.7
-
Reserved
IR.6
-
Reserved
IR.5
-
Reserved
IR.4
-
IR.3
Data Overrun Interrupt
IR.2
Error Interrupt
IR.1
Transmit Interrupt
Set when Transmit Buffer is released (SR.2 transitions from 0 to 1)
IR.0
Receive Interrupt
This bit is set while there are more messages in the fifo
Not used (wake-up interrupt of SJA1000)
Set when Data Overrun Status (SR.1) transitions from 0 to 1
Set when Error Status (SR.6) or Bus Status (SR.7) change
This register is reset on read with the exception of IR.0. This core resets the Receive Interrupt bit when the Release Receive
Buffer command is given (as in PeliCAN mode).
NOTE: Bit IR.5 through IR.7 read ‘1’. Bit IR.4 reads ‘0’.
13.3.6 Transmit buffer
The table below shows the layout of the transmit buffer. In BasicCAN only standard frame messages can be transmitted
and received. Extended Frame Format (EFF) messages on the bus are ignored.
Table 13.6 Transmit Buffer Layout
ADDR
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NAME
BITS
7
6
5
4
3
2
1
0
10
ID byte 1
ID.10
ID.9
ID.8
ID.7
ID.6
ID.5
ID.4
ID.3
11
ID byte 2
ID.2
ID.1
ID.0
RTR
DLC.3
DLC.2
DLC.1
DLC.0
12
TX data 1
TX byte 1
13
TX data 2
TX byte 2
14
TX data 3
TX byte 3
15
TX data 4
TX byte 4
16
TX data 5
TX byte 5
17
TX data 6
TX byte 6
18
TX data 7
TX byte 7
19
TX data 8
TX byte 8
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Section 13.3: 13.3 BasicCAN mode
If the RTR bit is set no data bytes will be sent, but DLC is still part of the frame and must be specified according to the
requested frame. It is possible to specify a DLC larger than eight bytes, but should not be done for compatibility reasons. If
DLC is greater than 8, only 8 bytes can be sent.
13.3.7 Receive buffer
The receive buffer on address 20 through 29 is the visible part of the 64-byte RX FIFO. Its layout is identical to that of the
transmit buffer.
13.3.8 Acceptance filter
Messages can be filtered based on their identifiers using the Acceptance Code and Acceptance Mask registers. Bits ID.10
through ID.3 of the 11-bit identifier are compared with the Acceptance Code Register. Only the bits set to ‘0’ in the Acceptance Mask Register are used for comparison. If a match is detected, the message is stored to the FIFO.
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Section 13.4: PeliCAN mode
13.4 PeliCAN mode
13.4.1 PeliCAN register map (Address 0xFFF20000 and 0xFFF20100)
Table 13.7 PeliCAN Address Allocation
OPERATING MODE
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RESET MODE
#
READ
WRITE
READ
WRITE
0
Mode
Mode
Mode
Mode
1
(0x00)
Command
(0x00)
Command
2
Status
-
Status
-
3
Interrupt
-
Interrupt
-
4
Interrupt enable
Interrupt enable
Interrupt Enable
Interrupt Enable
5
reserved (0x00)
-
reserved (0x00)
-
6
Bus Timing 0
-
Bus Timing 0
Bus Timing 0
7
Bus Timing 1
-
Bus Timing 1
Bus Timing 1
8
(0x00)
-
(0x00)
-
9
(0x00)
-
(0x00)
-
10
(0x00)
-
(0x00)
-
11
Arbitration Lost Capture
-
Arbitration Lost
Capture
-
12
Error Code Capture
-
Error Code Capture
-
13
Error Warning Limit
-
Error Warning
Limit
Error Warning
Limit
14
RX Error Counter
-
RX Error Counter
RX Error Counter
15
TX Error Counter
-
TX Error Counter
TX Error Counter
16
RX FI SFF
RX FI EFF
TX FI SFF
TX FI EFF
Acceptance Code 0
Acceptance Code 0
17
RX ID 1
RX ID 1
TX ID 1
TX ID 1
Acceptance Code 1
Acceptance Code 1
18
RX ID 2
RX ID 2
TX ID 2
TX ID 2
Acceptance Code 2
Acceptance Code 2
19
RX Data 1
RX ID 3
TX Data 1
TX ID 3
Acceptance Code 3
Acceptance Code 3
20
RX Data 2
RX ID 4
TX Data 2
TX ID 4
Acceptance Mask 0
Acceptance Mask 0
21
RX Data 3
RX Data 1
TX Data 3
TX Data 1
Acceptance Mask 1
Acceptance Mask 1
22
RX Data 4
RX Data 2
TX Data 4
TX Data 2
Acceptance Mask 2
Acceptance Mask 2
23
RX Data 5
RX Data 3
TX Data 5
TX Data 3
Acceptance Mask 3
Acceptance Mask 3
24
RX Data 6
RX Data 4
TX Data 6
TX Data 4
(0x00)
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Section 13.4: PeliCAN mode
Table 13.7 PeliCAN Address Allocation
OPERATING MODE
#
READ
RESET MODE
WRITE
READ
WRITE
25
RX Data 7
RX Data 5
TX Data 7
TX Data 5
(0x00)
-
26
RX Data 8
RX Data 6
TX Data 8
TX Data 6
(0x00)
-
27
FIFO
RX Data 7
-
TX Data 7
(0x00)
-
28
FIFO
RX Data 8
-
TX Data 8
(0x00)
-
29
RX Message Counter
-
RX Msg Counter
-
30
(0x00)
-
(0x00)
-
31
Clock Divider
Clock Divider
Clock Divider
Clock Divider
The transmit and receive buffers have a different layout depending on if standard frame format (SFF) or extended frame
format (EFF) is to be transmitted or received.
13.4.2 Mode Register
Table 13.8 Bit Interpretation of Mode Register (MOD) (Address 0)
BIT
NAME
DESCRIPTION
MOD.7
-
Reserved
MOD.6
-
Reserved
MOD.5
-
Reserved
MOD.4
-
Not used (sleep mode in SJA1000)
MOD.3
Acceptance Filter Mode
1 - single filter mode, 0 - dual filter mode
MOD.2
Self-Test Mode
Set if the controller is in self-test mode
MOD.1
Listen-Only Mode
Set if the controller is in listen-only mode
MOD.0
Reset Mode
Writing 1 to this bit aborts any ongoing transfer and enters
reset mode. Writing 0 returns to operating mode
Writing to MOD.1-3 can only be done when reset mode has been previously entered. In listen-only mode, the core will not
send any acknowledgements.
When in self-test mode, the core can complete a successful transmission without getting an acknowledgement if given
the Self Reception Request command (CMR.4). The core must still be connected to a real bus as it does not do an internal
roll-back.
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Section 13.4: PeliCAN mode
13.4.3 Command register
Writing a ‘1’ to the corresponding bit in this register initiates an action supported by the core.
Table 13.9 Bit Interpretation of Command Register (CMR) (Address 1)
BIT
NAME
DESCRIPTION
CMR.7
-
Reserved
CMR.6
-
Reserved
CMR.5
-
Reserved
CMR.4
Self Reception Request
Transmits and simultaneously receives a message
CMR.3
Clear Data Overrun
Clears the data overrun status bit
CMR.2
Release Receive Buffer
Free the current receive buffer for new reception
CMR.1
Abort Transmission
Aborts a not yet started transmission.
CMR.0
Transmission Request
Starts the transfer of the message in the TX buffer
A transmission is started by setting CMR.0. It can only be aborted by setting CMR.1 and only if the transfer has not yet
started. Setting CMR.0 and CMR.1 simultaneously will result in a so-called single shot transfer, i.e. the core will not try to
retransmit the message if not successful the first time.
Giving the Release Receive Buffer command (CMR.2) should be done after reading the contents of the receive buffer in
order to release the memory. If there is another message waiting in the FIFO, a new Receive Interrupt (IR.0) will be generated (if enabled), and the Receive Buffer Status bit (SR.0) will be set again.
The Self Reception Request bit (CMR.4) together with the self-test mode makes it possible to do a self test of the core without any other cores on the bus. A message will simultaneously be transmitted and received and both receive and transmit
interrupts will be generated
13.4.4 Status register
The status register is read only and reflects the current status of the core.
Table 13.10 Bit Interpretation of Status Register (SR) (Address 2)
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BIT
NAME
DESCRIPTION
SR.7
Bus Status
1 when the core is in bus-off and not involved in bus activities
SR.6
Error Status
At least one of the error counters have reached or exceeded the
error warning limit.
SR.5
Transmit Status
1 when transmitting a message
SR.4
Receive Status
1 when receiving a message
SR.3
Transmission Complete
SR.2
Transmit Buffer Status
1 means CPU can write into the transmit buffer
SR.1
Data Overrun Status
1 if a message was lost because no space in fifo
SR.0
Receive Buffer Status
1 if messages available in the receive fifo
1 indicates the last message was successfully transferred
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Section 13.4: PeliCAN mode
Receive Buffer Status (SR.0) is cleared when there are no more messages in the receive FIFO. The Data Overrun Status (SR.1)
signals that a message that was accepted could not be placed in the FIFO because there was not enough space left.
NOTE: This bit differs from the SJA1000 behavior and is set first when the FIFO has been read out.
When the Transmit Buffer Status (SR.2) is high the transmit buffer is available to be written to by the CPU. During an ongoing transmission the buffer is locked and this bit is ‘0’.
The Transmission Complete bit (SR.3) is cleared when a Transmission Request (CMR0) or Self Reception Request (CMR.4)
has been issued and will not be set again until a message has successfully been transmitted.
13.4.5 Interrupt register
The Interrupt Register signals to CPU what caused an interrupt. The interrupt bits are only set if the corresponding interrupt enable bit is set in the Interrupt Enable Register. The interrupt assignment for both CAN cores is shown in Table 1.4 of
Section 1.5. This register is reset on read with the exception of IR.0 which is reset when the FIFO has been emptied.
Table 13.11 Bit Interpretation of Interrupt Register (IR) (Address 3)
BIT
NAME
DESCRIPTION
IR.7
Bus Error Interrupt
Set if an error on the bus has been detected
IR.6
Arbitration Lost Interrupt
Set when the core has lost arbitration
IR.5
Error Passive Interrupt
Set when the core goes between error active and error
passive
IR.4
-
Not used (wake-up interrupt of SJA1000)
IR.3
Data Overrun Interrupt
Set when Data Overrun Status bit is set
IR.2
Error Warning Interrupt
Set on every change of the error status or bus status
IR.1
Transmit Interrupt
Set when the transmit buffer is released
IR.0
Receive Interrupt
Set while the receive FIFO is not empty.
13.4.6 Interrupt enable register
Interrupts sources can be enabled or disabled in the Interrupt Enable Register. If a bit is enabled, the corresponding interrupt can be generated.
Table 13.12 Bit Interpretation of Interrupt Enable Register (IER) (Address 4)
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BIT
NAME
DESCRIPTION
IR.7
Bus Error Interrupt
1 - enabled, 0 - disabled
IR.6
Arbitration Lost Interrupt
1 - enabled, 0 - disabled
IR.5
Error Passive Interrupt
1 - enabled, 0 - disabled
IR.4
-
Not used (wake-up interrupt of SJA1000)
IR.3
Data Overrun Interrupt
1 - enabled, 0 - disabled
IR.2
Error Warning Interrupt
1 - enabled, 0 - disabled.
IR.1
Transmit Interrupt
1 - enabled, 0 - disabled
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Section 13.4: PeliCAN mode
Table 13.12 Bit Interpretation of Interrupt Enable Register (IER) (Address 4)
BIT
NAME
DESCRIPTION
IR.0
Receive Interrupt
1 - enabled, 0 - disabled
13.4.7 Arbitration lost capture register
Table 13.13 Bit Interpretation of Arbitration Lost Capture Register (ALC) (Address 11)
BIT
NAME
DESCRIPTION
ALC.7-5
-
Reserved
ALC.4-0
Bit number
Bit where arbitration was lost
When the core loses arbitration the bit position of the bit stream processor is captured into arbitration lost capture register. The register will not change content again until read out.
13.4.8 Error code capture register
Table 13.14 Bit Interpretation of Error Code Capture Register (ECC) (Address 12)
BIT
NAME
DESCRIPTION
ECC.7-6
Error code
Error code number
ECC.5
Direction
1 - Reception, 0 - transmission error
ECC.4-0
Segment
Location in frame where error occurred
When a bus error occurs, the Error Code Capture Register is set according to the type of error that occurred, i.e., if it
occurred while transmitting or receiving, and where in the frame it occurred. As with the ALC register, the ECC register will
not change value until it has been read out. The following table shows how to interpret bit ECC.7-6.
Table 13.15 Error Code Interpretation
ECC.7-6
DESCRIPTION
0
Bit error
1
Form error
2
Stuff error
3
Other
The table below indicates how to interpret ECC.4-0.
Table 13.16 Bit Interpretation of ECC.4-0
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DESCRIPTION
0x03
Start of frame
0x02
ID.28 - ID.21
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Section 13.4: PeliCAN mode
Table 13.16 Bit Interpretation of ECC.4-0
ECC.4-0
DESCRIPTION
0x06
ID.20 - ID.18
0x04
Bit SRTR
0x05
Bit IDE
0x07
ID.17 - ID.13
0x0F
ID.12 - ID.5
0x0E
ID.4 - ID.0
0x0C
Bit RTR
0x0D
Reserved bit 1
0x09
Reserved bit 0
0x0B
Data length code
0x0A
Data field
0x08
CRC sequence
0x18
CRC delimiter
0x19
Acknowledge slot
0x1B
Acknowledge delimiter
0x1A
End of frame
0x12
Intermission
0x11
Active error flag
0x16
Passive error flag
0x13
Tolerate dominant bits
0x17
Error delimiter
0x1C
Overload flag
13.4.9 Error warning limit register
This register allows for setting the CPU error warning limit. The default is 96. Note: This register is only writable in reset
mode.
13.4.10 RX error counter register (address 14)
This register shows the value of the RX error counter. It is writable in reset mode. A bus-off event resets this counter to 0.
13.4.11 TX error counter register (address 15)
This register shows the value of the TX error counter. It is writable in reset mode. If a bus-off event occurs, this register is
configured to count down the protocol-defined 128 occurrences of the bus-free signal. The status of the bus-off recovery
can be read out from this register. The CPU can force a bus-off by writing 255 to this register. Unlike the SJA1000, this core
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signals bus-off immediately, not initially when entering operating mode. The bus-off recovery sequence starts when
entering operating mode after writing 255 to this register in reset mode.
13.4.12 Transmit buffer
The transmit buffer is write-only and is mapped to address 16 to 28. Reading of this area is mapped to the same address
offset as the receive buffer described in the next section. The layout of the transmit buffer depends on whether a standard
frame (SFF) or an extended frame (EFF) is to be sent as seen below.
Table 13.17 Transmit Buffer Layout
#
WRITE (SFF)
WRITE (EFF)
16
TX Frame Information
TX Frame Information
17
TX ID 1
TX ID 1
18
TX ID 2
TX ID 2
19
TX Data1
TX ID 3
20
TX Data 2
TX ID 4
21
TX Data 3
TX Data 1
22
TX Data 4
TX Data 2
23
TX Data 5
TX Data 3
24
TX Data 6
TX Data 4
25
TX Data 7
TX Data 5
26
TX Data 8
TX Data 6
27
-
TX Data 7
28
-
TX Data 8
Table 13.18 Description of TX Frame Information, Address 16
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7
FF
-
FF selects the frame format, i.e. whether this is to be interpreted
as an extended or standard frame. 1 = EFF, 0 = SFF.
6
RTR
0
RTR should be set to 1 for a Remote Transmission Request frame.
5-4
--
00
Don’t care
3-0
DLC.0 - DLC.3
0000
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DESCRIPTION
DLC specifies the Data Length Code and should have a value
between 0 and 8. If the value is greater than 8, only 8 bytes will be
transmitted.
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Section 13.4: PeliCAN mode
Table 13.19 Description of TX Identifier 1, Address 17
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-0
ID.21 - ID.28
00000000
DESCRIPTION
The top eight bits of the identifier.
Table 13.20 Description of TX Identifier 2, Address 18
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-5
ID.18 - ID.20
000
4-0
--
00000
DESCRIPTION
Bottom three bits of an SFF identifier.
Don’t care
Table 13.21 Description of TX Identifier 2, Address 18
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-0
ID.13 - ID.20
00000000
DESCRIPTION
Bit 20:13 of 29 bit EFF identifier.
Table 13.22 Description of TX Identifier 3, Address 19
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-0
ID.5 - ID.12
0000000
DESCRIPTION
Bit 12:5 of 29 bit EFF identifier.
Table 13.23 Description of TX Identifier 4, Address 20
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-3
ID.0 - ID.4
00000
2-0
--
000
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DESCRIPTION
Bit 4:0 of 29 bit EFF identifier.
Don’t care
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Chapter 13: CAN-2.0 Interface
Section 13.4: PeliCAN mode
Data field
The data field is located at addresses 19 to 26 for SFF frames, and at address 21 to 28 for EFF frames. The data is transmitted
starting from the MSB at the lowest address.
13.4.13 Receive buffer
Table 13.24 Receive Buffer Layout
#
READ (SFF)
READ (EFF)
16
RX Frame Information
RX Frame Information
17
RX ID 1
RX ID 1
18
RX ID 2
RX ID 2
19
RX Data 1
RX ID 3
20
RX Data 2
RX ID 4
21
RX Data 3
RX Data 1
22
RX Data 4
RX Data 2
23
RX Data 5
RX Data 3
24
RX Data 6
RX Data 4
25
RX Data 7
RX Data 5
26
RX Data 8
RX Data 6
27
RX FI of next message in fifo
RX Data 7
28
RX ID1 of next message in fifo
RX Data 8
RX frame information
Table 132. Description of RX Frame Information, Address 16
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7
FF
0
Frame format of received message. 1 = EFF, 0 = SFF.
6
RTR
0
1 if RTR frame.
5-4
Reserved
00
3-0
DLC.0 - DLC.3
0000
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DESCRIPTION
DLC specifies the Data Length Code.
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Section 13.4: PeliCAN mode
RX identifier 1
Table 13.25 Description of RX Identifier 1, Address 17
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-0
ID.21 - ID.28
00000000
DESCRIPTION
The top eight bits of the identifier.
Table 13.26 Description of RX Identifier 2, Address 18
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-5
ID.18 - ID.20
000
4
RTR
0
3-0
Reserved
DESCRIPTION
Bottom three bits of an SFF identifier.
1 if RTR frame.
Table 13.27 Description of RX Identifier 2 Address 18
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-0
ID.13 - ID.20
00000000
DESCRIPTION
Bit 20:13 of 29 bit EFF identifier.
Table 13.28 Description of RX Identifier 3, Address 19
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-0
ID.5 - ID.12
00000000
DESCRIPTION
Bit 12:5 of 29 bit EFF identifier.
Table 13.29 Description of RX Identifier 4, Address 20
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
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Chapter 13: CAN-2.0 Interface
Section 13.4: PeliCAN mode
Table 13.29 Description of RX Identifier 4, Address 20
BIT
NUMBER(S)
BIT NAME
RESET
STATE
7-3
ID.0 - ID.4
00000
2
RTR
0
1-0
Reserved
00
DESCRIPTION
Bit 4:0 of 29 bit EFF identifier
1 if RTR frame
Data field
The data field is located at address 19 to 26 for SFF frames, and at addresses 21 to 28 for EFF frames.
13.4.14 Acceptance filter
The acceptance filter can be used to filter out messages not meeting certain demands. If a message is filtered out, it will
not be put into the receive FIFO and the CPU will not have to process it.
There are two different filtering modes: Single filter mode and dual filter mode. The mode is selected by the Acceptance
Filter Mode bit (MOD.3) in the Mode Register. In single filter mode, a single filter is used. In dual filter, two smaller filters are
used. If there is a match with either filter, the message is accepted. Each filter consists of an acceptance code and an acceptance mask. The Acceptance Code registers are used for specifying the pattern to match, and the Acceptance Mask registers specify which bits to use for comparison. In total, eight registers are used for the acceptance filters as shown in the
following table.
NOTE: The registers are only read/writable in reset mode.
Table 13.30 Acceptance Filter Registers
ADDRESS
DESCRIPTION
16
Acceptance Code 0 (ACR0)
17
Acceptance Code 1 (ACR1)
18
Acceptance Code 2 (ACR2)
19
Acceptance Code 3 (ACR3)
20
Acceptance Mask 0 (AMR0)
21
Acceptance Mask 1 (AMR1)
22
Acceptance Mask 2 (AMR2)
23
Acceptance Mask 3 (AMR3)
Single filter mode, standard frame
When receiving a standard frame in single filter mode the registers ACR0-3 are compared against the incoming message in
the following way:
ACR0.7-0 & ACR1.7-5 are compared to ID.28-18
ACR1.4 is compared to the RTR bit.
ACR1.3-0 are unused.
ACR2 & ACR3 are compared to data byte 1 & 2.
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The corresponding bits in the AMR registers select which bits are used for comparison. A set bit in the mask register means
don’t care.
Single filter mode, extended frame
When receiving an extended frame in single filter mode the registers ACR0-3 are compared against the incoming message
in the following way:
ACR0.7-0 & ACR1.7-0 are compared to ID.28-13
ACR2.7-0 & ACR3.7-3 are compared to ID.12-0
ACR3.2 are compared to the RTR bit
ACR3.1-0 are unused.
The corresponding bits in the AMR registers select which bits are used for comparison. A set bit in the mask register means
don’t care.
Dual filter mode, standard frame
When receiving a standard frame in dual filter mode the registers ACR0-3 are compared against the incoming message in
the following way:
Filter 1
ACR0.7-0 & ACR1.7-5 are compared to ID.28-18
ACR1.4 is compared to the RTR bit.
ACR1.3-0 are compared against upper nibble of data byte 1
ACR3.3-0 are compared against lower nibble of data byte 1
Filter 2
ACR2.7-0 & ACR3.7-5 are compared to ID.28-18
ACR3.4 is compared to the RTR bit.
The corresponding bits in the AMR registers select which bits are used for comparison. A set bit in the mask register means
don’t care.
Dual filter mode, extended frame
When receiving a standard frame in dual filter mode the registers ACR0-3 are compared against the incoming message in
the following way:
Filter 1
ACR0.7-0 & ACR1.7-0 are compared to ID.28-13
Filter 2
ACR2.7-0 & ACR3.7-0 are compared to ID.28-13
The corresponding bits in the AMR registers select which bits are used for comparison. A set bit in the mask register means
don’t care.
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Chapter 13: CAN-2.0 Interface
Section 13.5: Common registers
13.4.15 RX Message Counter
The RX message counter register at address 29 holds the number of messages currently stored in the receive FIFO. The top
three bits are always 0.
13.5 Common registers
There are three common registers that are at the same addresses and have the same functionality in both BasiCAN and
PeliCAN mode. These are the Clock Divider Register and Bit Timing Registers 0 and 1.
13.5.1 Clock Divider Register
The only function of this register in the GRLIB version of the Opencores CAN is to choose between PeliCAN and BasiCAN.
Table 13.31 Bit Interpretation of Clock Divider Register (CDR) (Address 31)
BIT
NAME
DESCRIPTION
CDR.7
CAN mode
1 - PeliCAN, 0 - BasiCAN
CDR.6
-
Unused
CDR.5
-
Unused
CDR.4
-
Reserved
CDR.3
-
Reserved
CDR.2
-
Reserved
CDR.1
-
Reserved
CDR.0
-
Reserved
13.5.2 Bus timing 0
Table 13.32 Bit Interpretation of Bus Timing 0 Register (BTR0) (Address 6)
BIT
NAME
DESCRIPTION
BTR0.7-6
SJW
Synchronization jump width
BTR0.5-0
BRP
Baud rate prescaler
The CAN core system clock is calculated as:
tscl = 2*tclk*(BRP+1)
where tclk is the system clock.
The sync jump width defines how many clock cycles (tscl) a bit period may be adjusted with by one re-synchronization.
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Section 13.6: CAN-OC VS SJA1000
13.5.3 Bus timing 1
Table 13.33 Bit Interpretation of Bus Timing 1 Register (BTR1) (Address 7)
BIT
NAME
DESCRIPTION
BTR1.7
SAM
1 - The bus is sampled three times, 0 - single sample point
BTR1.6-4
TSEG2
Time segment 2
BTR1.3-0
TSEG1
Time segment 1
The CAN bus bit period is determined by the CAN system clock and time segment 1 and 2 as shown in the equations
below:
ttseg1 = tscl * (TSEG1+1)
ttseg2 = tscl * (TSEG2+1)
tbit = ttseg1 + ttseg2 + tscl
The additional tscl term comes from the initial sync segment.
Sampling is done between TSEG1 and TSEG2 in the bit period.
13.6 CAN-OC VS SJA1000
This section lists the known differences between this CAN controller and the SJA1000 on which is it based.
• All bits related to sleep mode are unavailable
• Output control and test registers do not exist (reads 0x00)
• Clock divisor register bit 6 (CBP) and 5 (RXINTEN) are not implemented
• Data overrun IRQ and status not set until FIFO is read out
• BasicCAN specific differences:
• The receive IRQ bit is not reset on read (works like in PeliCAN mode)
• Bit CR.6 always reads 0 and is not a flip-flop with no effect as in the SJA1000
• Bit IRQ is not reset on read as in SJA1000
• Does not become error passive and active error frames are still sent.
PeliCAN specific differences:
•
•
•
•
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Writing 256 to TX error counter gives immediate bus-off when still in reset mode
Read Buffer Start Address register does not exist
Addresses above 31 are not implemented (i.e. the internal RAM/FIFO access)
The core transmits active error frames in Listen only mode
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.1: Overview
Chapter 14: Ethernet Media Access Controller (MAC) with
EDCL Support
14.1 Overview
Aeroflex Gaisler’s Ethernet Media Access Controller (GRETH) provides an interface between an AMBA AHB bus and an
Ethernet network. It supports 10/100 Mbit speed in both full- and half-duplex modes. The AMBA interface consists of an
APB interface for configuration and control and an AHB master interface that handles the dataflow. The dataflow is handled through DMA channels. There is one DMA engine for the transmitter and one for the receiver. Both share the same
AHB master interface. The Ethernet interface supports the MII interface, which should be connected to an external PHY.
The GRETH also provides access to the MII management interface which is used to configure the PHY. Hardware support
for the Ethernet Debug Communication Link (EDCL) protocol is enabled by tying the EDCLDIS pin to a logic low. This is an
UDP/IP based protocol used for remote debugging.
APB
HB
Ethernet MAC
MDIO_OE
MDIO_O
Registers
MDIO
MDIO_I
MDC
Transmitter
DMA Engine
AHB Master
Interface
FIFO
Transmitter
EDCL
Transmitter
EDCL
Receiver
Receiver
DMA Engine
Receiver
FIFO
TX_EN
TX_ER
TXD(3:0)
TX_CLK
RX_CRS
RX_COL
RX_DV
RX_ER
RXD(3:0)
RX_CLK
Figure 14.1 Block Diagram of the Internal Structure of the GRETH
14.2 Operation
14.2.1 System overview
The GRETH consists 3 functional units: The DMA channels, MDIO interface and the Ethernet Debug Communication Link
(EDCL).
The main functionality consists of the DMA channels, which are used to transfer data between an AHB bus and an Ethernet
network. There is one transmitter DMA channel and one Receiver DMA channel. The operation of the DMA channels is
controlled through registers accessible through the APB interface.
The MDIO interface is used for accessing configuration and status registers in one or more PHYs connected to the MAC.
The operation of this interface is also controlled through the APB interface.
The EDCL provides read and write access to an AHB bus through Ethernet. It uses the UDP, IP, ARP protocols together with
a custom application layer protocol to accomplish this. The EDCL contains no user accessible registers and always runs in
parallel with the DMA channels.
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.2: Operation
The Media Independent Interface (MII) is used for communicating with the PHY. There is an Ethernet transmitter which
sends all data from the AHB domain on the Ethernet using the MII interface. Correspondingly, there is an Ethernet receiver
which stores all data from the Ethernet on the AHB bus. Both of these interfaces use FIFOs when transferring the data
streams.
14.2.2 Protocol support
The GRETH is implemented according to IEEE standard 802.3-2002. There is no support for the optional control sublayer
and no multicast addresses can be assigned to the MAC. This means that packets with type 0x8808 (the only currently
defined control packets) are discarded.
14.2.3 Hardware requirements
There are three clock domains: The AHB clock, the Ethernet receiver clock and the Ethernet transmitter clock. Both fullduplex and half-duplex operating modes are supported. The system frequency requirement (SYSCLK) is 2.5 MHz for up to
10 Mbit/s operation and 25 Mhz for up to 100 Mbit/s operation.
14.2.4 Transmitter DMA interface
The transmitter DMA interface is used for transmitting data on an Ethernet network. The transmission is done using
descriptors located in memory.
14.2.5 Setting up a descriptor
A single descriptor is shown in Figure 14.2 and Figure 14.3. The number of bytes to be sent should be set in the Length
field and the Address field should point to the data. The address must be word-aligned. If the Interrupt Enable (IE) bit is set,
an interrupt will be generated when the packet has been sent (this requires that the Transmitter Interrupt (TI) bit in the
Control Register also be set). The interrupt will be generated regardless of whether the packet was transmitted successfully or not. The Wrap (WR) bit is also a control bit that should be set before transmission and it will be explained later in
this section.
Offset = 0x0
31
19 18 17 16 15 14 13 12 11 10
RESERVED
LE
--
AL UE
IE WR EN
0
LENGTH
Figure 14.2 Ethernet Transmitter Descriptor Word 0
Table 14.1 Description of Ethernet Transmitter Descriptor Word 0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-19
Reserved
[000...0]
18
LE
0
Length Error
The length/type field of the packet did not match the actual
number of received bytes.
15
AL
0
Attempt Limit Error
Set if the packet was not transmitted because the maximum
number of attempts was reached.
14
UE
0
Underrun Error
Set if the packet was incorrectly transmitted due to a FIFO underrun error.
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.2: Operation
Table 14.1 Description of Ethernet Transmitter Descriptor Word 0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
13
IE
0
Interrupt Enable
An interrupt will be generated when the packet from this descriptor has been sent provided that the Transmitter Interrupt (TI)
enable bit in the Control Register is set. The interrupt is generated
regardless if the packet was transmitted successfully or if it terminated with an error.
0: Disable interrupts
1: Enable interrupts
12
WR
0
Wrap
Set to one to make the descriptor pointer wrap to zero after this
descriptor has been used. If this bit is not set the pointer will
increment by 8. The pointer automatically wraps to zero when
the 1 KB boundary of the descriptor table is reached.
0: Wrap disabled
1: Wrap enabled
11
EN
0
Enable
Set to one to enable the descriptor. Should always be the last bit
set in the descriptor fields.
0: Descriptor disabled
1: Descriptor enabled
10-0
LENGTH
[000...0]
The number of bytes to be transmitted.
Offset = 0x4
31
2
ADDRESS
1
0
RES
Figure 14.3 Ethernet Transmitter Descriptor Word 1
Table 14.2 Description of Ethernet Transmitter Descriptor Word 1
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-2
Address
[000...0]
1-0
Reserved
[00]
DESCRIPTION
Pointer to the buffer area from where the
packet data will be loaded.
Read=00b; Write=don’t care.
To enable a descriptor the Enable (EN) bit must be set. After a descriptor is enabled, it should not be modified until the
Enable bit has been cleared.
14.2.6 Starting transmissions
Enabling a descriptor is not enough to start a transmission. A pointer to the memory area holding the descriptors must
first be set in the GRETH. This is done in the Transmitter Descriptor Pointer Register. The address must be aligned to a 1 KB
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Section 14.2: Operation
boundary. Bits 31:10 hold the base address of descriptor area, while bits 9:3 form a pointer to an individual descriptor. The
first descriptor should be located at the base address and when it has been used by the GRETH, the Descriptor Pointer field
is incremented by eight to point to the next descriptor. The pointer automatically wraps back to zero after the last 1 KB
boundary has been reached at address offset 0x3F8. The Wrap (WR) bit in the descriptors can be set to make the pointer
wrap back to zero before the 1 KB boundary.
The Descriptor Pointer field has also been made writable for maximum flexibility. However, care should be taken when
writing to the Descriptor Pointer Register. It should never be modified when a transmission is active. The final step to activate the transmission is to set the Transmit Enable (TE) bit in the control register. This tells the GRETH there are active
descriptors in the descriptor table. This bit should always be set when new descriptors are enabled, even if transmissions
are already active. The descriptors must always be enabled before the Transmit Enable bit is set.
14.2.7 Descriptor handling after transmission
When a transmission of a packet has finished, status is written to the first word in the corresponding descriptor. The Underrun Error (UE) bit is set if the FIFO became empty before the packet was completely transmitted. The Attempt Limit Error
(AL) bit is set if more collisions occurred than allowed. The packet was successfully transmitted only if both of these bits are
zero. The other bits in the first descriptor word are set to zero after transmission while the second word is left untouched.
The Enable bit should be used as the indicator when a descriptor can be used again, which is when it has been cleared by
the GRETH. There are three bits in the GRETH status register that hold transmission status. The Transmitter Error (TE) bit is
set each time a transmission ended with an error (when at least one of the two status bits in the transmitter descriptor has
been set). The Transmitter Interrupt (TI) is set each time a transmission ended successfully. The Transmitter AHB Error (TA)
bit is set when an AHB error was encountered either when reading a descriptor or when reading packet data. Any active
transmissions are aborted and the transmitter is disabled. The transmitter can be activated again by setting the Transmit
Enable bit in the Control Register.
14.2.8 Setting up the data for transmission
The data to be transmitted should be placed beginning at the address pointed by the descriptor Address field of the transmitter descriptor. The GRETH does not add the Ethernet address and type fields, so they must also be stored in the data
buffer. The 4 byte Ethernet CRC is automatically appended to the end of each packet. Each descriptor will be sent as a single Ethernet packet. If the size field in a descriptor is greater than 1514 byte, the packet will not be sent.
14.2.9 Receiver DMA interface
The receiver DMA interface is used for receiving data from an Ethernet network. The reception is done using descriptors
located in memory.
14.2.10 Setting up descriptors
A single descriptor is shown in Figure 14.4 and Figure 14.5. The address field should point to a word-aligned buffer where
the received data is to be stored. The GRETH never stores more than 1514 byte to the buffer. If the Interrupt Enable (IE) bit
is set, an interrupt will be generated when a packet has been received to this buffer (this requires that the Receiver Interrupt (RI) bit in the Control Register be set). The interrupt will be generated regardless of whether the packet was received
successfully or not. The Wrap (WR) bit is also a control bit that should be set before the descriptor is enabled and it will be
explained later in this section.
Offset = 0x0
31
18 17 16 15 14 13 12 11 10
RESERVED
OE CE FT AE
IE WR EN
0
LENGTH
Figure 14.4 Ethernet Receiver Descriptor Word 0
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Section 14.2: Operation
Table 14.3 Description of Ethernet Receiver Descriptor Word 0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-18
Reserved
[000...0]
17
OE
0
Overrun Error
Set if the frame was incorrectly received due to a FIFO overrun.
16
CE
0
CRC Error
Set if a CRC error was detected in this frame.
15
FT
0
Frame Too Long
Set if a frame larger than the maximum size was received.
The excessive part was truncated.
14
AE
0
Alignment Error
Set if an odd number of nibbles were received.
13
IE
0
Interrupt Enable
An interrupt will be generated when a packet has been
received to this descriptor provided the Receiver Interrupt
(RI) enable bit in the Control Register is set. The interrupt is
generated regardless if the packet was received successfully
or if it terminated with an error.
0: Interrupts disabled
1: Interrupts enabled
12
Wrap (WR)
0
Set to one to make the descriptor pointer wrap to zero after
this descriptor has been used. If this bit is not set, the pointer
will increment by 8. The pointer automatically wraps to zero
when the 1 KB boundary of the descriptor table is reached.
0: Wrap disabled
1: Wrap enabled
11
Enable (EN)
0
Enable
Set to one to enable the descriptor. Should always be set last
of all the descriptor fields.
0: Descriptor disabled
1: Descriptor enabled
10-0
LENGTH
[000...0]
The number of bytes received by this descriptor.
Offset = 0x4
31
2
ADDRESS
1
0
RES
Figure 14.5 Ethernet Receiver Descriptor Word 1
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Table 14.4: Description of Ethernet Receiver Descriptor Word 1
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-2
Address
[000...0]
Pointer to the buffer area from where the packet data will be
loaded.
1-0
Reserved
00
Read=00b; Write=don’t care.
14.2.11 Starting reception
Enabling a descriptor is not enough to start reception. A pointer to the memory area holding the descriptors must first be
set in the GRETH. This is done in the Receiver Descriptor Pointer Register. The address must be aligned to a 1 KB boundary.
Bits 31:10 hold the base address of the descriptor area while bits 9:3 form a pointer to an individual descriptor. The first
descriptor should be located at the base address and when it has been used by the GRETH, the pointer field is incremented
by 8 to point to the next descriptor. The pointer automatically wraps back to zero when the last 1 KB boundary has been
reached at address offset 0x3F8. The Wrap (WR) bit in the descriptors can be set to make the pointer wrap back to zero
before the 1 KB boundary.
The Descriptor Pointer field has also been made writable for maximum flexibility, but care should be taken when writing to
the descriptor pointer register. It should never be modified when reception is active.
The final step to activate reception is to set the Receiver Enable (RE) bit in the Control Register. This makes the GRETH read
the first descriptor and wait for an incoming packet.
14.2.12 Descriptor handling after reception
The GRETH indicates a completed reception by clearing the descriptor’s Enable bit. Control bits WR and IE are also cleared.
The number of received bytes is shown in the Length field. The parts of the Ethernet frame stored are the destination
address, source address, type, and data fields. Bits 17:14 in the first descriptor word are status bits indicating different
receive errors. All four bits are zero after a reception without errors.
Packets arriving that are smaller than the minimum Ethernet size of 64 bytes are not considered valid and are discarded.
The current receive descriptor will be left untouched and used for the first packet arriving with an accepted size. The Too
Small (TS) bit in the Status Register is set each time this event occurs.
If a packet is received with an address not accepted by the MAC, the Invalid Address (IA) bit in the Status Register will be
set.
Packets larger than maximum size cause the Frame Too Long (FT) bit in the receiver descriptor to be set. In this case, the
Length field is not guaranteed to hold the correct value of received bytes. The counting stops after the word containing
the last byte up to the maximum size limit has been written to memory.
The address word of the descriptor is never touched by the GRETH.
14.2.13 Reception with AHB errors
If an AHB error occurs during a descriptor read or data store, the Receiver AHB Error (RA) bit in the Status Register will be
set and the receiver is disabled. The current reception is aborted. The receiver can be enabled again by setting the Receive
Enable (RE) bit in the Control Register.
14.2.14 MDIO interface
The MDIO interface provides access to PHY configuration and status registers through a two-wire interface which is
included in the MII interface. The GRETH provides full support for the MDIO interface.
The MDIO interface can be used to access from 1 to 32 PHYs containing 1 to 32 16-bit registers. A read transfer is set up by
writing to the PHY Address and Register Address fields of the MDIO Control and Status Register and setting the Read (RD)
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.2: Operation
bit. This causes the Busy (BU) bit to be set and the operation is finished when the Busy bit is cleared. If the operation was
successful, the Link Fail (LF) bit is cleared and the data field contains the read data. An unsuccessful operation is indicated
by the Link Fail bit being set. The data field is undefined in this case.
A write operation is started by writing to the 16-bit Data field and to the PHY Address and Register field of the MDIO Control Register, and setting the Write (WR) bit. The operation is finished when the Busy (BU) bit is cleared and it was successful if the Link Fail bit is zero.
14.2.15 Ethernet Debug Communication Link (EDCL)
The EDCL provides access to an on-chip AHB bus through Ethernet. It uses the UDP, IP and ARP protocols together with a
custom application layer protocol. The application layer protocol uses an ARQ algorithm to provide reliable AHB instruction transfers. Through this link, a read or write transfer can be generated to any address on the AHB bus.
14.2.15.1 Operation
The EDCL receives packets in parallel with the MAC receive DMA channel. It uses a separate MAC address which is used for
distinguishing EDCL packets from packets destined to the MAC DMA channel. The EDCL also has a present IP address.
Since ARP packets use the Ethernet broadcast address, the IP-address must be used in this case to distinguish between
EDCL ARP packets and those that should go to the DMA-channel. Packets that are determined to be EDCL packets are not
processed by the receive DMA channel. When the packets are checked to be correct, the AHB operation is performed. The
operation is performed with the same AHB master interface that the DMA-engines use. The replies are automatically sent
by the EDCL transmitter when the operation is finished. It shares the Ethernet transmitter with the transmitter DMAengine but has higher priority.
14.2.15.2 EDCL protocols
The EDCL accepts Ethernet frames containing IP or ARP data. ARP is handled according to the protocol specification with
no exceptions. IP packets carry the actual AHB commands. The EDCL expects an Ethernet frame containing IP, UDP and the
EDCL specific application layer parts. Table 14.5 shows the IP packet required by the EDCL. The contents of the different
protocol headers can be found in TCP/IP literature.
Table 14.5 Ethernet IP Package Title Expected by the EDCL
ETHERNET
IP
UDP
2B
4B
4B
DATA 0 - 242
ETHERNET
Header
Header
Header
Offset
Control word
Address
4B Words
CRC
The following is required for successful communication with the EDCL: A correct destination MAC address as set by the
generics, an Ethernet type field containing 0x0806 (ARP) or 0x0800 (IP). The IP-address is then compared with the value
determined by the generics for a match. The IP-header checksum and identification fields are not checked. There are a few
restrictions on the IP-header fields. The version must be four and the header size must be 5 B (no options). The protocol
field must always be 0x11 indicating a UDP packet. The length and checksum are the only IP fields changed for the reply.
The EDCL only provides one service at the moment and it is therefore not required to check the UDP port number. The
reply will have the original source port number in both the source and destination fields. UDP checksum are not used and
the checksum field is set to zero in the replies.
The UDP data field contains the EDCL application protocol fields. Table 14.6 shows the application protocol fields (data
field excluded) in packets received by the EDCL. The 16-bit offset is used to align the rest of the application layer data to
word boundaries in memory and can thus be set to any value. The R/W field determines whether a read (0) or a write(1)
should be performed. The length field contains the number of bytes to be read or written. If R/W is one the data field
shown in Table 14.6 contains the data to be written. If R/W is zero the data field is empty in the received packets. Table 14.7
shows the application layer fields of the replies from the EDCL. The length field is always zero for replies to write requests.
For read requests it contains the number of bytes of data contained in the data field.
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.3: Registers
Table 14.6 EDCL Application Layer Fields in Received Frames
16-bit Offset
14-bit Sequence number
1-bit R/W
10-bit Length
7-bit Unused
Table 14.7 Application Layer Fields in Transmitted Frames
16-bit Offset
14-bit sequence number
1-bit ACK/NAK
10-bit Length
7-bit Unused
The EDCL implements a Go-Back-N algorithm providing reliable transfers. The 14-bit sequence number in received packets
are checked against an internal counter for a match. If they do not match, no operation is performed and the ACK/NAK
field is set to 1 in the reply frame. The reply frame contains the internal counter value in the sequence number field. If the
sequence number matches, the operation is performed, the internal counter value is stored in the sequence number field,
the ACK/NAK field is set to 0 in the reply and the internal counter is incremented. The length field is always set to 0 for ACK/
NAK=1 frames. The unused field is not checked and is copied to the reply. It can be set to hold for example some extra
identifier bits if needed.
14.2.15.3 EDCL IP and Ethernet address settings
The default value of the EDCL IP and MAC address is 192.168.0.64. The IP address can later be changed by software, but the
MAC address is fixed.
14.2.15.4 EDCL buffer size
The EDCL has a dedicated internal buffer memory which stores the received packets during processing. The size of this
buffer is.......
14.2.16 Media independent interfaces
There are several interfaces defined between the MAC sublayer and the physical layer. The GRETH supports the Media
Independent Interface. The MII was defined in the 802.3 standard and is most commonly supported. The Ethernet interface has been implemented according to this specification and uses 16 signals.
14.2.17 Software drivers
Drivers for the GRETH MAC is provided for the following operating systems: RTEMS, eCos, uClinux and Linux. The drivers
are freely available in full source code under the GPL license from Aeroflex Gaisler.
14.3 Registers
The core is programmed through registers mapped into APB address space.
Table 14.8 GRETH Registers
REGISTER
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Ethernet Control Register (ETHCTR)
0x80000E00
Ethernet Status and Interrupt Source Register (ETHSIS)
0x80000E04
Ethernet MAC Address MSB (MACMSB)
0x80000E08
Ethernet MAC Address LSB (MACLSB)
0x80000E0C
Ethernet MDIO Control and Status Register (ETHMDC)
0x80000E10
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.1: Overview
Chapter 14: Ethernet Media Access Controller (MAC) with
EDCL Support
14.1 Overview
Aeroflex Gaisler’s Ethernet Media Access Controller (GRETH) provides an interface between an AMBA AHB bus and an
Ethernet network. It supports 10/100 Mbit speed in both full- and half-duplex modes. The AMBA interface consists of an
APB interface for configuration and control and an AHB master interface that handles the dataflow. The dataflow is handled through DMA channels. There is one DMA engine for the transmitter and one for the receiver. Both share the same
AHB master interface. The Ethernet interface supports the MII interface, which should be connected to an external PHY.
The GRETH also provides access to the MII management interface which is used to configure the PHY. Hardware support
for the Ethernet Debug Communication Link (EDCL) protocol is enabled by tying the EDCLDIS pin to a logic low. This is an
UDP/IP based protocol used for remote debugging.
APB
HB
Ethernet MAC
MDIO_OE
MDIO_O
Registers
MDIO
MDIO_I
MDC
Transmitter
DMA Engine
AHB Master
Interface
FIFO
Transmitter
EDCL
Transmitter
EDCL
Receiver
Receiver
DMA Engine
Receiver
FIFO
TX_EN
TX_ER
TXD(3:0)
TX_CLK
RX_CRS
RX_COL
RX_DV
RX_ER
RXD(3:0)
RX_CLK
Figure 14.1 Block Diagram of the Internal Structure of the GRETH
14.2 Operation
14.2.1 System overview
The GRETH consists 3 functional units: The DMA channels, MDIO interface and the Ethernet Debug Communication Link
(EDCL).
The main functionality consists of the DMA channels, which are used to transfer data between an AHB bus and an Ethernet
network. There is one transmitter DMA channel and one Receiver DMA channel. The operation of the DMA channels is
controlled through registers accessible through the APB interface.
The MDIO interface is used for accessing configuration and status registers in one or more PHYs connected to the MAC.
The operation of this interface is also controlled through the APB interface.
The EDCL provides read and write access to an AHB bus through Ethernet. It uses the UDP, IP, ARP protocols together with
a custom application layer protocol to accomplish this. The EDCL contains no user accessible registers and always runs in
parallel with the DMA channels.
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Section 14.2: Operation
The Media Independent Interface (MII) is used for communicating with the PHY. There is an Ethernet transmitter which
sends all data from the AHB domain on the Ethernet using the MII interface. Correspondingly, there is an Ethernet receiver
which stores all data from the Ethernet on the AHB bus. Both of these interfaces use FIFOs when transferring the data
streams.
14.2.2 Protocol support
The GRETH is implemented according to IEEE standard 802.3-2002. There is no support for the optional control sublayer
and no multicast addresses can be assigned to the MAC. This means that packets with type 0x8808 (the only currently
defined control packets) are discarded.
14.2.3 Hardware requirements
There are three clock domains: The AHB clock, the Ethernet receiver clock and the Ethernet transmitter clock. Both fullduplex and half-duplex operating modes are supported. The system frequency requirement (SYSCLK) is 2.5 MHz for up to
10 Mbit/s operation and 25 Mhz for up to 100 Mbit/s operation.
14.2.4 Transmitter DMA interface
The transmitter DMA interface is used for transmitting data on an Ethernet network. The transmission is done using
descriptors located in memory.
14.2.5 Setting up a descriptor
A single descriptor is shown in Figure 14.2 and Figure 14.3. The number of bytes to be sent should be set in the Length
field and the Address field should point to the data. The address must be word-aligned. If the Interrupt Enable (IE) bit is set,
an interrupt will be generated when the packet has been sent (this requires that the Transmitter Interrupt (TI) bit in the
Control Register also be set). The interrupt will be generated regardless of whether the packet was transmitted successfully or not. The Wrap (WR) bit is also a control bit that should be set before transmission and it will be explained later in
this section.
Offset = 0x0
31
19 18 17 16 15 14 13 12 11 10
RESERVED
LE
--
AL UE
IE WR EN
0
LENGTH
Figure 14.2 Ethernet Transmitter Descriptor Word 0
Table 14.1 Description of Ethernet Transmitter Descriptor Word 0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-19
Reserved
[000...0]
18
LE
0
Length Error
The length/type field of the packet did not match the actual
number of received bytes.
15
AL
0
Attempt Limit Error
Set if the packet was not transmitted because the maximum
number of attempts was reached.
14
UE
0
Underrun Error
Set if the packet was incorrectly transmitted due to a FIFO underrun error.
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Table 14.1 Description of Ethernet Transmitter Descriptor Word 0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
13
IE
0
Interrupt Enable
An interrupt will be generated when the packet from this descriptor has been sent provided that the Transmitter Interrupt (TI)
enable bit in the Control Register is set. The interrupt is generated
regardless if the packet was transmitted successfully or if it terminated with an error.
0: Disable interrupts
1: Enable interrupts
12
WR
0
Wrap
Set to one to make the descriptor pointer wrap to zero after this
descriptor has been used. If this bit is not set the pointer will
increment by 8. The pointer automatically wraps to zero when
the 1 KB boundary of the descriptor table is reached.
0: Wrap disabled
1: Wrap enabled
11
EN
0
Enable
Set to one to enable the descriptor. Should always be the last bit
set in the descriptor fields.
0: Descriptor disabled
1: Descriptor enabled
10-0
LENGTH
[000...0]
The number of bytes to be transmitted.
Offset = 0x4
31
2
ADDRESS
1
0
RES
Figure 14.3 Ethernet Transmitter Descriptor Word 1
Table 14.2 Description of Ethernet Transmitter Descriptor Word 1
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-2
Address
[000...0]
1-0
Reserved
[00]
DESCRIPTION
Pointer to the buffer area from where the
packet data will be loaded.
Read=00b; Write=don’t care.
To enable a descriptor the Enable (EN) bit must be set. After a descriptor is enabled, it should not be modified until the
Enable bit has been cleared.
14.2.6 Starting transmissions
Enabling a descriptor is not enough to start a transmission. A pointer to the memory area holding the descriptors must
first be set in the GRETH. This is done in the Transmitter Descriptor Pointer Register. The address must be aligned to a 1 KB
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boundary. Bits 31:10 hold the base address of descriptor area, while bits 9:3 form a pointer to an individual descriptor. The
first descriptor should be located at the base address and when it has been used by the GRETH, the Descriptor Pointer field
is incremented by eight to point to the next descriptor. The pointer automatically wraps back to zero after the last 1 KB
boundary has been reached at address offset 0x3F8. The Wrap (WR) bit in the descriptors can be set to make the pointer
wrap back to zero before the 1 KB boundary.
The Descriptor Pointer field has also been made writable for maximum flexibility. However, care should be taken when
writing to the Descriptor Pointer Register. It should never be modified when a transmission is active. The final step to activate the transmission is to set the Transmit Enable (TE) bit in the control register. This tells the GRETH there are active
descriptors in the descriptor table. This bit should always be set when new descriptors are enabled, even if transmissions
are already active. The descriptors must always be enabled before the Transmit Enable bit is set.
14.2.7 Descriptor handling after transmission
When a transmission of a packet has finished, status is written to the first word in the corresponding descriptor. The Underrun Error (UE) bit is set if the FIFO became empty before the packet was completely transmitted. The Attempt Limit Error
(AL) bit is set if more collisions occurred than allowed. The packet was successfully transmitted only if both of these bits are
zero. The other bits in the first descriptor word are set to zero after transmission while the second word is left untouched.
The Enable bit should be used as the indicator when a descriptor can be used again, which is when it has been cleared by
the GRETH. There are three bits in the GRETH status register that hold transmission status. The Transmitter Error (TE) bit is
set each time a transmission ended with an error (when at least one of the two status bits in the transmitter descriptor has
been set). The Transmitter Interrupt (TI) is set each time a transmission ended successfully. The Transmitter AHB Error (TA)
bit is set when an AHB error was encountered either when reading a descriptor or when reading packet data. Any active
transmissions are aborted and the transmitter is disabled. The transmitter can be activated again by setting the Transmit
Enable bit in the Control Register.
14.2.8 Setting up the data for transmission
The data to be transmitted should be placed beginning at the address pointed by the descriptor Address field of the transmitter descriptor. The GRETH does not add the Ethernet address and type fields, so they must also be stored in the data
buffer. The 4 byte Ethernet CRC is automatically appended to the end of each packet. Each descriptor will be sent as a single Ethernet packet. If the size field in a descriptor is greater than 1514 byte, the packet will not be sent.
14.2.9 Receiver DMA interface
The receiver DMA interface is used for receiving data from an Ethernet network. The reception is done using descriptors
located in memory.
14.2.10 Setting up descriptors
A single descriptor is shown in Figure 14.4 and Figure 14.5. The address field should point to a word-aligned buffer where
the received data is to be stored. The GRETH never stores more than 1514 byte to the buffer. If the Interrupt Enable (IE) bit
is set, an interrupt will be generated when a packet has been received to this buffer (this requires that the Receiver Interrupt (RI) bit in the Control Register be set). The interrupt will be generated regardless of whether the packet was received
successfully or not. The Wrap (WR) bit is also a control bit that should be set before the descriptor is enabled and it will be
explained later in this section.
Offset = 0x0
31
18 17 16 15 14 13 12 11 10
RESERVED
OE CE FT AE
IE WR EN
0
LENGTH
Figure 14.4 Ethernet Receiver Descriptor Word 0
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Table 14.3 Description of Ethernet Receiver Descriptor Word 0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-18
Reserved
[000...0]
17
OE
0
Overrun Error
Set if the frame was incorrectly received due to a FIFO overrun.
16
CE
0
CRC Error
Set if a CRC error was detected in this frame.
15
FT
0
Frame Too Long
Set if a frame larger than the maximum size was received.
The excessive part was truncated.
14
AE
0
Alignment Error
Set if an odd number of nibbles were received.
13
IE
0
Interrupt Enable
An interrupt will be generated when a packet has been
received to this descriptor provided the Receiver Interrupt
(RI) enable bit in the Control Register is set. The interrupt is
generated regardless if the packet was received successfully
or if it terminated with an error.
0: Interrupts disabled
1: Interrupts enabled
12
Wrap (WR)
0
Set to one to make the descriptor pointer wrap to zero after
this descriptor has been used. If this bit is not set, the pointer
will increment by 8. The pointer automatically wraps to zero
when the 1 KB boundary of the descriptor table is reached.
0: Wrap disabled
1: Wrap enabled
11
Enable (EN)
0
Enable
Set to one to enable the descriptor. Should always be set last
of all the descriptor fields.
0: Descriptor disabled
1: Descriptor enabled
10-0
LENGTH
[000...0]
The number of bytes received by this descriptor.
Offset = 0x4
31
2
ADDRESS
1
0
RES
Figure 14.5 Ethernet Receiver Descriptor Word 1
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Table 14.4: Description of Ethernet Receiver Descriptor Word 1
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-2
Address
[000...0]
Pointer to the buffer area from where the packet data will be
loaded.
1-0
Reserved
00
Read=00b; Write=don’t care.
14.2.11 Starting reception
Enabling a descriptor is not enough to start reception. A pointer to the memory area holding the descriptors must first be
set in the GRETH. This is done in the Receiver Descriptor Pointer Register. The address must be aligned to a 1 KB boundary.
Bits 31:10 hold the base address of the descriptor area while bits 9:3 form a pointer to an individual descriptor. The first
descriptor should be located at the base address and when it has been used by the GRETH, the pointer field is incremented
by 8 to point to the next descriptor. The pointer automatically wraps back to zero when the last 1 KB boundary has been
reached at address offset 0x3F8. The Wrap (WR) bit in the descriptors can be set to make the pointer wrap back to zero
before the 1 KB boundary.
The Descriptor Pointer field has also been made writable for maximum flexibility, but care should be taken when writing to
the descriptor pointer register. It should never be modified when reception is active.
The final step to activate reception is to set the Receiver Enable (RE) bit in the Control Register. This makes the GRETH read
the first descriptor and wait for an incoming packet.
14.2.12 Descriptor handling after reception
The GRETH indicates a completed reception by clearing the descriptor’s Enable bit. Control bits WR and IE are also cleared.
The number of received bytes is shown in the Length field. The parts of the Ethernet frame stored are the destination
address, source address, type, and data fields. Bits 17:14 in the first descriptor word are status bits indicating different
receive errors. All four bits are zero after a reception without errors.
Packets arriving that are smaller than the minimum Ethernet size of 64 bytes are not considered valid and are discarded.
The current receive descriptor will be left untouched and used for the first packet arriving with an accepted size. The Too
Small (TS) bit in the Status Register is set each time this event occurs.
If a packet is received with an address not accepted by the MAC, the Invalid Address (IA) bit in the Status Register will be
set.
Packets larger than maximum size cause the Frame Too Long (FT) bit in the receiver descriptor to be set. In this case, the
Length field is not guaranteed to hold the correct value of received bytes. The counting stops after the word containing
the last byte up to the maximum size limit has been written to memory.
The address word of the descriptor is never touched by the GRETH.
14.2.13 Reception with AHB errors
If an AHB error occurs during a descriptor read or data store, the Receiver AHB Error (RA) bit in the Status Register will be
set and the receiver is disabled. The current reception is aborted. The receiver can be enabled again by setting the Receive
Enable (RE) bit in the Control Register.
14.2.14 MDIO interface
The MDIO interface provides access to PHY configuration and status registers through a two-wire interface which is
included in the MII interface. The GRETH provides full support for the MDIO interface.
The MDIO interface can be used to access from 1 to 32 PHYs containing 1 to 32 16-bit registers. A read transfer is set up by
writing to the PHY Address and Register Address fields of the MDIO Control and Status Register and setting the Read (RD)
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bit. This causes the Busy (BU) bit to be set and the operation is finished when the Busy bit is cleared. If the operation was
successful, the Link Fail (LF) bit is cleared and the data field contains the read data. An unsuccessful operation is indicated
by the Link Fail bit being set. The data field is undefined in this case.
A write operation is started by writing to the 16-bit Data field and to the PHY Address and Register field of the MDIO Control Register, and setting the Write (WR) bit. The operation is finished when the Busy (BU) bit is cleared and it was successful if the Link Fail bit is zero.
14.2.15 Ethernet Debug Communication Link (EDCL)
The EDCL provides access to an on-chip AHB bus through Ethernet. It uses the UDP, IP and ARP protocols together with a
custom application layer protocol. The application layer protocol uses an ARQ algorithm to provide reliable AHB instruction transfers. Through this link, a read or write transfer can be generated to any address on the AHB bus.
14.2.15.1 Operation
The EDCL receives packets in parallel with the MAC receive DMA channel. It uses a separate MAC address which is used for
distinguishing EDCL packets from packets destined to the MAC DMA channel. The EDCL also has a present IP address.
Since ARP packets use the Ethernet broadcast address, the IP-address must be used in this case to distinguish between
EDCL ARP packets and those that should go to the DMA-channel. Packets that are determined to be EDCL packets are not
processed by the receive DMA channel. When the packets are checked to be correct, the AHB operation is performed. The
operation is performed with the same AHB master interface that the DMA-engines use. The replies are automatically sent
by the EDCL transmitter when the operation is finished. It shares the Ethernet transmitter with the transmitter DMAengine but has higher priority.
14.2.15.2 EDCL protocols
The EDCL accepts Ethernet frames containing IP or ARP data. ARP is handled according to the protocol specification with
no exceptions. IP packets carry the actual AHB commands. The EDCL expects an Ethernet frame containing IP, UDP and the
EDCL specific application layer parts. Table 14.5 shows the IP packet required by the EDCL. The contents of the different
protocol headers can be found in TCP/IP literature.
Table 14.5 Ethernet IP Package Title Expected by the EDCL
ETHERNET
IP
UDP
2B
4B
4B
DATA 0 - 242
ETHERNET
Header
Header
Header
Offset
Control word
Address
4B Words
CRC
The following is required for successful communication with the EDCL: A correct destination MAC address as set by the
generics, an Ethernet type field containing 0x0806 (ARP) or 0x0800 (IP). The IP-address is then compared with the value
determined by the generics for a match. The IP-header checksum and identification fields are not checked. There are a few
restrictions on the IP-header fields. The version must be four and the header size must be 5 B (no options). The protocol
field must always be 0x11 indicating a UDP packet. The length and checksum are the only IP fields changed for the reply.
The EDCL only provides one service at the moment and it is therefore not required to check the UDP port number. The
reply will have the original source port number in both the source and destination fields. UDP checksum are not used and
the checksum field is set to zero in the replies.
The UDP data field contains the EDCL application protocol fields. Table 14.6 shows the application protocol fields (data
field excluded) in packets received by the EDCL. The 16-bit offset is used to align the rest of the application layer data to
word boundaries in memory and can thus be set to any value. The R/W field determines whether a read (0) or a write(1)
should be performed. The length field contains the number of bytes to be read or written. If R/W is one the data field
shown in Table 14.6 contains the data to be written. If R/W is zero the data field is empty in the received packets. Table 14.7
shows the application layer fields of the replies from the EDCL. The length field is always zero for replies to write requests.
For read requests it contains the number of bytes of data contained in the data field.
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Table 14.6 EDCL Application Layer Fields in Received Frames
16-bit Offset
14-bit Sequence number
1-bit R/W
10-bit Length
7-bit Unused
Table 14.7 Application Layer Fields in Transmitted Frames
16-bit Offset
14-bit sequence number
1-bit ACK/NAK
10-bit Length
7-bit Unused
The EDCL implements a Go-Back-N algorithm providing reliable transfers. The 14-bit sequence number in received packets
are checked against an internal counter for a match. If they do not match, no operation is performed and the ACK/NAK
field is set to 1 in the reply frame. The reply frame contains the internal counter value in the sequence number field. If the
sequence number matches, the operation is performed, the internal counter value is stored in the sequence number field,
the ACK/NAK field is set to 0 in the reply and the internal counter is incremented. The length field is always set to 0 for ACK/
NAK=1 frames. The unused field is not checked and is copied to the reply. It can be set to hold for example some extra
identifier bits if needed.
14.2.15.3 EDCL IP and Ethernet address settings
The default value of the EDCL IP and MAC address is 192.168.0.64. The IP address can later be changed by software, but the
MAC address is fixed.
14.2.15.4 EDCL buffer size
The EDCL has a dedicated internal buffer memory which stores the received packets during processing. The size of this
buffer is.......
14.2.16 Media independent interfaces
There are several interfaces defined between the MAC sublayer and the physical layer. The GRETH supports the Media
Independent Interface. The MII was defined in the 802.3 standard and is most commonly supported. The Ethernet interface has been implemented according to this specification and uses 16 signals.
14.2.17 Software drivers
Drivers for the GRETH MAC is provided for the following operating systems: RTEMS, eCos, uClinux and Linux. The drivers
are freely available in full source code under the GPL license from Aeroflex Gaisler.
14.3 Registers
The core is programmed through registers mapped into APB address space.
Table 14.8 GRETH Registers
REGISTER
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Ethernet Control Register (ETHCTR)
0x80000E00
Ethernet Status and Interrupt Source Register (ETHSIS)
0x80000E04
Ethernet MAC Address MSB (MACMSB)
0x80000E08
Ethernet MAC Address LSB (MACLSB)
0x80000E0C
Ethernet MDIO Control and Status Register (ETHMDC)
0x80000E10
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Table 14.8 GRETH Registers
REGISTER
APB ADDRESS
Ethernet Transmitter Descriptor Pointer Register (ETHTDP)
0x80000E14
Ethernet Receiver Descriptor Pointer Register (ETHRDP)
0x80000E18
ETHCTR
31 30
Address = 0x80000E00
28
ED
7
BS
RESERVED
6
5
4
SP RS PM FD
3
2
RI
TI
1
0
RE TE
Figure 14.6 Ethernet Control Register
Table 14.9 Description of Ethernet Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
ED
1
30-28
BS
001
27-7
Reserved
[- - -...-]
7
SP
0
Speed
Sets the current speed mode. 0 = 10 Mbit, 1 = 100 Mbit. A default
value is automatically read from the PHY after reset.
6
RS
0
Reset
Setting this bit resets the GRETH core. Self clearing.
5
PM
-
Open Packet Mode
If set, the GRETH operates in open packet mode, which means it
will receive all packets regardless of the destination address.
0: Not open-packet mode
1: Operates in open-packet mode
Not reset
4
FD
-
Full Duplex
0: GRETH operates in half-duplex mode
1: GRETH operates in full-duplex mode
Not reset
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EDCL Available
0: EDCL unavailable
1: EDCL available
Read=0; Write=don’t care.
EDCL Buffer Size
Shows the amount of memory used for EDCL buffers. 0 = 1 KB, 1 =
2 KB,...., 6 = 64 KB
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Table 14.9 Description of Ethernet Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
3
RI
0
Enable Receiver Interrupts
An interrupt will be generated each time a packet is received
when this bit is set. The interrupt is generated regardless if the
packet was received successfully or if it terminated with an error.
Not reset.
0: Receiver interrupts disabled
1: Receiver interrupts enabled
2
TI
0
Enable Transmitter Interrupts
An interrupt will be generated each time a packet is transmitted
when this bit is set. The interrupt is generated regardless if the
packet was transmitted successfully or if it terminated with an
error. Not reset.
0: Transmitter interrupts disabled
1: Transmitter interrupts enabled
1
RE
0
Receive Enable
Should be written with a one each time new descriptors are
enabled. As long as this bit is one, the GRETH reads new descriptors and as soon as it encounters a disabled descriptor it will stop
until RE is set again. This bit should be written with a one after the
new descriptors have been enabled.
0
TE
0
Transmit Enable
Should be written with a one each time new descriptors are
enabled. As long as this bit is one the GRETH reads new descriptors and as soon as it encounters a disabled descriptor it stops
until TE is set again. This bit should be written with a one after the
new descriptors have been enabled.
ETHSIS
Address = 0x80000E04
31
8
RESERVED
7
IA
6
5
4
TS TA RA
3
2
TI
RI
1
0
TE RE
Figure 14.7 GRETH Status and Interrupt Source Register
Table 14.10 Description of GRETH Status and Interrupt Source Register
BIT
NUMBER(S)
BIT NAME
31-8
Reserved
7
IA
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STATE
0
DESCRIPTION
Invalid Address
A set bit indicates a packet with an address not accepted by the
MAC was received. Cleared when written with a one.
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Table 14.10 Description of GRETH Status and Interrupt Source Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
6
TS
0
Too Small
A set bit indicates a packet smaller than the minimum size was
received. Cleared when written with a one.
5
TA
_
Transmitter AHB Error
A set bit indicates an AHB error was encountered in transmitter
DMA engine. Cleared when written with a one. Not reset.
4
RA
_
Receiver AHB Error
A set bit indicates an AHB error was encountered in receiver DMA
engine. Cleared when written with a one. Not reset.
3
TI
_
Transmitter Interrupt
A set bit indicates a packet was transmitted without errors.
Cleared when written with a one. Not reset.
2
RI
_
Receiver Interrupt
A set bit indicates a packet was received without errors. Cleared
when written with a one. Not reset.
1
TE
_
Transmitter Error
A set bit indicates a packet was transmitted which terminated
with an error. Cleared when written with a one. Not reset.
0
RE
_
Receiver Error
A set bit indicates a packet has been received which terminated
with an error. Cleared when written with a one. Not reset.
MACMSB
Address = 0x80000E08
31
16 15
0
RESERVED
MAC Address [47:32]
Figure 14.8 Ethernet MAC Address MSB
Table 14.11 Description of Ethernet MAC Address MSB
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
15-0
Address MSB
[- - -...-]
DESCRIPTION
The two most significant bytes of the MAC
address. Not reset.
MACLSB
Address = 0x80000E0C
Figure 14.9 Ethernet MAC Address LSB
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31
0
MAC Address [31:0]
Figure 14.9 Ethernet MAC Address LSB
Table 14.12 Description of Ethernet MAC Address LSB
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-0
Address LSB
[- - -...-]
DESCRIPTION
The 4 least significant bytes of the
MAC address. Not reset.
ETHMDC
Address = 0x80000E10
31
16 15
DATA
11 10
PHY ADDRESS
6
REGISTER ADDRESS
5
-
4
3
2
1
0
NV BU LF RD WR
Figure 14.10 Ethernet MDIO Control and Status Register
Table 14.13 Description of Ethernet MDIO Control and Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-16
Data
[- - ...-]
Contains data read during a read operation and data that is transmitted is taken from this field. Not Reset.
15-11
PHY Address
[- - ...-]
This field contains the address of the PHY that should be
accessed during a write or read operation. Not Reset.
10-6
Register Address
[- - ...-]
This field contains the address of the register that should be
accessed during a write or read operation. Not Reset.
5
Reserved
[- - ...-]
4
NV
_
Not Valid
When an operation is finished (BU = 0) this bit indicates whether
valid data has been received that is, the data field contains correct data. Not Reset.
0: Data field contains valid data
1: Data field contains invalid data
3
BU
0
Busy
When an operation is performed this bit is set to one. As soon as
the operation is finished and the management link is idle, this bit
is cleared.
0: Management link idle
1: Management link active
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Table 14.13 Description of Ethernet MDIO Control and Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
2
LF
_
Link Fail
When an operation completes (BU = 0), this bit is set if a functional management link was not detected. Not Reset.
0: Functional management link detected
1: Functional management link not detected
1
RD
0
Read
Set to start a read operation from the management interface.
Data is stored in the Data field.
0
WR
0
Write
Set to start a write operation to the management interface. Data
is taken from the Data field.
ETHTDP
Address = 0x80000E14
31
10
TXDTRA
9
3
RX_DESCRIPTOR_POINTER
2
0
RESERVED
Figure 14.11 Ethernet Transmitter Descriptor Pointer Register
Table 14.14 Description of Ethernet Transmitter Descriptor Pointer Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-10
TXDTRA
[- - -...-]
Base address of the Transmitter Descriptor Table
9-3
TX_Descriptor_Pointer
[- - -...-]
This field is incremented by one each
time a descriptor has been used. It is
automatically incremented by the Ethernet MAC.
2-0
Reserved
[000]
Read: 000b; Write=don’t care.
ETHRDP
Address = 0x80000E18
31
10
RXDTBA
9
3
RX_DESCRIPTOR_POINTER
2
0
RESERVED
Figure 14.12 Ethernet Receiver Descriptor Pointer Register
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.3: Registers
Table 14.15 Description of Ethernet Receiver Descriptor Pointer Register
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Ver. 1.1.0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-10
RXDTBA
[- - -...-]
Base address of the Receiver Descriptor
Table
9-3
RX_Descriptor_Pointer
[- - -...-]
This field is incremented by one each time a
descriptor has been
used. It is automatically incremented by the
Ethernet MAC.
2-0
Reserved
[000]
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DESCRIPTION
Read: 000b; Write=don’t care.
Aeroflex Microelectronic Solutions - HiRel
Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.3: Registers
Table 14.9 Description of Ethernet Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
3
RI
0
Enable Receiver Interrupts
An interrupt will be generated each time a packet is received
when this bit is set. The interrupt is generated regardless if the
packet was received successfully or if it terminated with an error.
Not reset.
0: Receiver interrupts disabled
1: Receiver interrupts enabled
2
TI
0
Enable Transmitter Interrupts
An interrupt will be generated each time a packet is transmitted
when this bit is set. The interrupt is generated regardless if the
packet was transmitted successfully or if it terminated with an
error. Not reset.
0: Transmitter interrupts disabled
1: Transmitter interrupts enabled
1
RE
0
Receive Enable
Should be written with a one each time new descriptors are
enabled. As long as this bit is one, the GRETH reads new descriptors and as soon as it encounters a disabled descriptor it will stop
until RE is set again. This bit should be written with a one after the
new descriptors have been enabled.
0
TE
0
Transmit Enable
Should be written with a one each time new descriptors are
enabled. As long as this bit is one the GRETH reads new descriptors and as soon as it encounters a disabled descriptor it stops
until TE is set again. This bit should be written with a one after the
new descriptors have been enabled.
ETHSIS
Address = 0x80000E04
31
8
RESERVED
7
IA
6
5
4
TS TA RA
3
2
TI
RI
1
0
TE RE
Figure 14.7 GRETH Status and Interrupt Source Register
Table 14.10 Description of GRETH Status and Interrupt Source Register
BIT
NUMBER(S)
BIT NAME
31-8
Reserved
7
IA
94-00-00-000
Ver. 1.1.0
RESET
STATE
0
DESCRIPTION
Invalid Address
A set bit indicates a packet with an address not accepted by the
MAC was received. Cleared when written with a one.
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.3: Registers
Table 14.10 Description of GRETH Status and Interrupt Source Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
6
TS
0
Too Small
A set bit indicates a packet smaller than the minimum size was
received. Cleared when written with a one.
5
TA
_
Transmitter AHB Error
A set bit indicates an AHB error was encountered in transmitter
DMA engine. Cleared when written with a one. Not reset.
4
RA
_
Receiver AHB Error
A set bit indicates an AHB error was encountered in receiver DMA
engine. Cleared when written with a one. Not reset.
3
TI
_
Transmitter Interrupt
A set bit indicates a packet was transmitted without errors.
Cleared when written with a one. Not reset.
2
RI
_
Receiver Interrupt
A set bit indicates a packet was received without errors. Cleared
when written with a one. Not reset.
1
TE
_
Transmitter Error
A set bit indicates a packet was transmitted which terminated
with an error. Cleared when written with a one. Not reset.
0
RE
_
Receiver Error
A set bit indicates a packet has been received which terminated
with an error. Cleared when written with a one. Not reset.
MACMSB
Address = 0x80000E08
31
16 15
0
RESERVED
MAC Address [47:32]
Figure 14.8 Ethernet MAC Address MSB
Table 14.11 Description of Ethernet MAC Address MSB
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-16
Reserved
[000...0]
15-0
Address MSB
[- - -...-]
DESCRIPTION
The two most significant bytes of the MAC
address. Not reset.
MACLSB
Address = 0x80000E0C
Figure 14.9 Ethernet MAC Address LSB
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.3: Registers
31
0
MAC Address [31:0]
Figure 14.9 Ethernet MAC Address LSB
Table 14.12 Description of Ethernet MAC Address LSB
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-0
Address LSB
[- - -...-]
DESCRIPTION
The 4 least significant bytes of the
MAC address. Not reset.
ETHMDC
Address = 0x80000E10
31
16 15
DATA
11 10
PHY ADDRESS
6
REGISTER ADDRESS
5
-
4
3
2
1
0
NV BU LF RD WR
Figure 14.10 Ethernet MDIO Control and Status Register
Table 14.13 Description of Ethernet MDIO Control and Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-16
Data
[- - ...-]
Contains data read during a read operation and data that is transmitted is taken from this field. Not Reset.
15-11
PHY Address
[- - ...-]
This field contains the address of the PHY that should be
accessed during a write or read operation. Not Reset.
10-6
Register Address
[- - ...-]
This field contains the address of the register that should be
accessed during a write or read operation. Not Reset.
5
Reserved
[- - ...-]
4
NV
_
Not Valid
When an operation is finished (BU = 0) this bit indicates whether
valid data has been received that is, the data field contains correct data. Not Reset.
0: Data field contains valid data
1: Data field contains invalid data
3
BU
0
Busy
When an operation is performed this bit is set to one. As soon as
the operation is finished and the management link is idle, this bit
is cleared.
0: Management link idle
1: Management link active
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.3: Registers
Table 14.13 Description of Ethernet MDIO Control and Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
2
LF
_
Link Fail
When an operation completes (BU = 0), this bit is set if a functional management link was not detected. Not Reset.
0: Functional management link detected
1: Functional management link not detected
1
RD
0
Read
Set to start a read operation from the management interface.
Data is stored in the Data field.
0
WR
0
Write
Set to start a write operation to the management interface. Data
is taken from the Data field.
ETHTDP
Address = 0x80000E14
31
10
TXDTRA
9
3
RX_DESCRIPTOR_POINTER
2
0
RESERVED
Figure 14.11 Ethernet Transmitter Descriptor Pointer Register
Table 14.14 Description of Ethernet Transmitter Descriptor Pointer Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-10
TXDTRA
[- - -...-]
Base address of the Transmitter Descriptor Table
9-3
TX_Descriptor_Pointer
[- - -...-]
This field is incremented by one each
time a descriptor has been used. It is
automatically incremented by the Ethernet MAC.
2-0
Reserved
[000]
Read: 000b; Write=don’t care.
ETHRDP
Address = 0x80000E18
31
10
RXDTBA
9
3
RX_DESCRIPTOR_POINTER
2
0
RESERVED
Figure 14.12 Ethernet Receiver Descriptor Pointer Register
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Chapter 14: Ethernet Media Access Controller (MAC) with EDCL Support
Section 14.3: Registers
Table 14.15 Description of Ethernet Receiver Descriptor Pointer Register
94-00-00-000
Ver. 1.1.0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-10
RXDTBA
[- - -...-]
Base address of the Receiver Descriptor
Table
9-3
RX_Descriptor_Pointer
[- - -...-]
This field is incremented by one each time a
descriptor has been
used. It is automatically incremented by the
Ethernet MAC.
2-0
Reserved
[000]
- 168 -
DESCRIPTION
Read: 000b; Write=don’t care.
Aeroflex Microelectronic Solutions - HiRel
Chapter 15: Hardware Debug Support
Section 15.1: Introduction
Chapter 15: Hardware Debug Support
15.1 Introduction
To simplify debugging on target hardware, the LEON3 processor implements a debug mode during which the pipeline is
idle and the processor is controlled through a special debug interface. The LEON3 Debug Support Unit (DSU) is used to
control the processor during debug mode. The DSU acts as an AHB slave and can be accessed by any AHB master. An
external debug host can therefore access the DSU through several different interfaces. Such an interface can be a serial
UART (RS232), JTAG, PCI, SPW, or Ethernet.
Debug I/F
LEON3
Processor(s)
Debug Support
Unit
AHB Slave I/F
AHB Master I/F
AMBA AHB BUS
RS232
PCI
Ethernet
JTAG
SPW
DEBUG HOST
Figure 15.1 LEON3/DSU Connection
15.2 Operation
Through the DSU AHB slave interface, the AHB masters listed above can access the processor registers and the contents of
the instruction trace buffer. The DSU control registers can be accessed at any time, while the processor registers, caches
and trace buffer can only be accessed when the processor has entered debug mode. In debug mode, the processor pipeline is held and the processor state can be accessed by the DSU. Entering the debug mode can occur on the following
events:
•
•
•
•
•
•
•
•
94-00-00-000
Ver. 1.1.0
Executing a breakpoint, i.e.Trap Always instruction (ta 1)
Integer unit hardware breakpoint/watchpoint hit (trap 0x0B)
Rising edge of the external break signal (DSUBRE)
Setting the Break-Now (BN) bit in the DSU Break and Single-Step Register
A trap that would cause the processor to enter error mode
Occurrence of any, or a selection of traps, as defined in the DSU Control Register
After a single-step operation
DSU breakpoint hit
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Chapter 15: Hardware Debug Support
Section 15.3: AHB Trace Buffer
Debug mode can only be entered when the debug support unit is enabled by setting the DSUEN pin high. When debug
mode is entered, the following actions are taken:
• PC and nPC are saved in temporary registers (accessible by the debug unit)
• An output signal (DSUACT) is asserted to indicate the debug state
• The timer unit is (optionally) stopped to freeze the LEON 3FT timers and watchdog
The instruction that caused the processor to enter debug mode is not executed and the processor state is kept unmodified. Execution is resumed by clearing the BN bit in the DSU Control Register or by de-asserting DSUEN. The timer unit will
be re-enabled and execution continues from the saved PC and nPC. Debug mode can also be entered after the processor
has entered error mode. For instance, when an application has terminated and halted the processor error mode can be
reset and the processor restarted at any address.
When a processor is in debug mode, accesses to the ASI diagnostic area are forwarded to the IU, which performs accesses
with the ASI equal to value in the DSU ASI Diagnostic Register and address consisting of 20 least-significant bits of the
original address.
15.3 AHB Trace Buffer
The AHB trace buffer consists of a circular buffer that stores AHB data transfers. The address, data, and various control signals of the AHB bus are stored and can be read out for later analysis. The trace buffer is 128 bits wide and 256 lines deep.
The information stored is indicated in the table below.
Table 15.1 AHB Trace Buffer Data Allocation
BITS
NAME
DEFINITION
127
AHB breakpoint hit
Set to ‘1’ if a DSU AHB breakpoint hit occurred.
126
-
Not used
125-96
Time tag
DSU time tag counter
95
-
Not used
94-80
Hirq
AHB HIRQ[15:1]
79
Hwrite
AHB HWRITE
78-77
Htrans
AHB HTRANS
76-74
Hsize
AHB HSIZE
73-71
Hburst
AHB HBURST
70-67
Hmaster
AHB HMASTER
66
Hmastlock
AHB HMASTLOCK
65-64
Hresp
AHB HRESP
63-32
Load/Store data
AHB HRDATA or HWDATA
31-0
Load/Store address
AHB HADDR
In addition to the AHB signals, the DSU time tag counter is also stored in the trace. The trace buffer is enabled by setting
the Enable (EN) bit in the AHB Trace Buffer Control Register. Each AHB transfer is then stored in the buffer in a circular manner. The address to which the next transfer is written is held in the Trace Buffer Index Register and is automatically incremented after each transfer. Tracing is stopped when the EN bit is cleared, or when an AHB breakpoint is hit. Tracing is
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Chapter 15: Hardware Debug Support
Section 15.4: Instruction trace buffer
temporarily suspended when the processor enters debug mode. Neither the trace buffer memory nor the breakpoint registers (see below) can be read/written by software when the trace buffer is enabled.
15.4 Instruction trace buffer
The instruction trace buffer consists of a circular buffer that stores executed instructions. The instruction trace buffer is
located in the processor and read out via the DSU. The trace buffer is 128 bits wide and 256 lines deep. The information
stored is indicated in the table below.
Table 15.2 Instruction Trace Buffer Data Allocation
BITS
NAME
DEFINITION
127
-
Unused
126
Multi-cycle instruction
Set to ‘1’ on the second and third instance of a multicycle instruction (LDD, ST or FPOP)
125-96
Time tag
The value of the DSU time tag counter
95-64
Load/Store parameters
Instruction result, Store address or Store data
63-34
Program counter
Program counter (2 lsb bits removed since they are
always zero)
33
Instruction trap
Set to ‘1’ if traced instruction trapped
32
Processor error mode
Set to ‘1’ if the traced instruction caused processor
error mode
31-0
Opcode
Instruction opcode
During tracing, one instruction is stored per line in the trace buffer with the exception of multi-cycle instructions. Multicycle instructions are entered two or three times in the trace buffer. For store instructions, bits 63:32 correspond to the
store address on the first entry and to the stored data on the second entry (and the third in case of an STD instruction). Bit
126 is set on the second and third entry to indicate this. A double load (LDD) instruction is entered twice in the trace buffer
with bits 63:32 containing the loaded data. Multiply and divide instructions are entered twice, but only the last entry contains the result. Bit 126 is set for the second entry. For FPU operation producing a double-precision result, the first entry
puts the most-significant 32 bits of the results in bits 63:32, while the second entry puts the least-significant 32 bits in this
field.
When the processor enters debug mode, tracing is suspended. The trace buffer and the AHB Trace Buffer Control Register
can be read and written to, while the processor is in debug mode. During instruction tracing (processor in normal mode),
the trace buffer and the AHB Trace Buffer Control Register can not be accessed
15.5 DSU memory map
The DSU memory map can be seen in Table 15.3 below. The base address is 0x90000000.
Table 15.3 DSU Memory Map
REGISTER
94-00-00-000
Ver. 1.1.0
ADDRESS
DSU Control Register
0x90000000
DSU Trace Buffer Time Tag Counter Register
0x90000008
DSU Break and Single-Step Register
0x90000020
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Chapter 15: Hardware Debug Support
Section 15.5: DSU memory map
Table 15.3 DSU Memory Map
REGISTER
ADDRESS
AHB Trace Buffer Control Register
0x90000040
AHB Trace Buffer Index Register
0x90000044
AHB Trace Buffer Breakpoint Address Register 1
0x90000050
AHB Trace Buffer Breakpoint Mask Register 1
0x90000054
AHB Trace Buffer Breakpoint Address Register 2
0x90000058
AHB Trace Buffer Breakpoint Mask Register 2
0x9000005c
Instruction Trace Buffer
0x90100000 - 0x9010FFFF
Instruction Trace Buffer Control Register
94-00-00-000
Ver. 1.1.0
0x90110000
AHB Trace Buffer
0x90200000 - 0x9021FFFF
IU Register File
0x90300000 - 0x903007FC
IU Register File Port 1(ASR16) and Port 2 (ASR16)
0x90300800 - 0X90300FFC
FPU Register File
0x90301000 - 0x9030107C
IU Special Purpose Registers
0x90400000 - 0x904FFFFC
Y Register
0x90400000
PSR Register
0x90400004
WIM Register
0x90400008
TBR Register
0x9040000C
PC Register
0x90400010
NPC Register
0x90400014
FSR Register
0x90400018
CPSR Register
0x9040001C
DSU Trap Register
0x90400020
DSU ASI Diagnostic Access Register
0x90400024
ASR16 - ASR31 (when implemented)
0x90400040 - 0x9040007C
ASI Diagnostic Access (ASI = value in DSU ASI register, address =
address[19:0])
ASI = 0x9: Local instruction RAM
ASI = 0xB: Local data RAM
ASI = 0xC: Instruction cache tags
ASI = 0xD: Instruction cache data
ASI = 0xE: Data cache tags
ASI = 0xF: Data cache data
ASI = 0x1E: Separate snoop tags
0x90700000 - 0x907FFFFC
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Chapter 15: Hardware Debug Support
Section 15.6: DSU registers
The addresses of the IU registers are calculated as follows:
•
•
•
•
•
%on: 0x90300000 + (((psr.cwp * 64) + 32 + n*4) mod 128)
%ln: 0x90300000 + (((psr.cwp * 64) + 64 + n*4) mod 128)
%in: 0x90300000 + (((psr.cwp * 64) + 96 + n*4) mod 128)
%gn: 0x90300000 + 128 + n*4
%fn: 0x90301000 + n*4
15.6 DSU registers
15.6.1 DSU control register
The DSU is controlled by the DSU control register:
DCR
Address = 0x90000000
31
12 11 10
RESERVED
9
8
7
6
5
4
3
2
1
0
PW HL PE EB EE DM BZ BX BS BW BE TE
Figure 15.2 Description of DSU Control Register
Table 15.4 Description of DSU Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-12
Reserved
[000...0]
11
PW
0
Power Down
Returns ‘1’ when processor in power-down mode.
10
HL
0
Processor Halt
Returns ‘1’ on read when processor is halted. If the processor is in
debug mode, setting this bit puts the processor in halt mode.
9
PE
0
Processor Error Mode
Returns ‘1’ on read when processor is in error mode, else ‘0’. If
written with ‘1’, it clears the error and halt mode.
8
EB
_
Value of the external DSUBRE signal (read-only).
7
EE
_
Value of the external DSUEN signal (read-only).
6
DM
0
Debug Mode
Indicates when the processor has entered debug mode (readonly).
5
BZ
0
Break on Error Traps
If set, forces the processor into debug mode on all except the following traps: priviledged_instruction, fpu_disabled,
window_overflow, window_underflow, asynchronous_interrupt,
ticc_trap.
4
BX
0
Break on Trap
If set, forces the processor into debug mode when any trap
occurs.
94-00-00-000
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DESCRIPTION
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Chapter 15: Hardware Debug Support
Section 15.6: DSU registers
Table 15.4 Description of DSU Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
3
BS
0
Break on Software Breakpoint
If set, debug mode will be forced when an breakpoint instruction
(ta 1) is executed.
2
BW
0
Break on IU Watchpoint
If set, debug mode will be forced on a IU watchpoint (trap 0xb).
1
BE
0
Break on Error
If set, forces the processor to debug mode when the processor
would have entered error condition (trap in trap).
0
TE
0
Trap Enable
Enables instruction tracing. If set the instructions will be stored in
the trace buffer. Remains set when then processor enters debug
or error mode.
DESCRIPTION
15.6.2 DSU break and single-step register
This register is used to break or single-step the processor.
DBSSR
Address = 0x90000020
31
RESERVED
17 16 15
0
SS
BN
Figure 15.3 DSU Break and Single-Step Register
Table 15.5 Description of DSU Break and Single-Step Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-17
Reserved
[000...0]
16
SS
0
15-1
Reserved
[000...0]
0
BN
0
94-00-00-000
Ver. 1.1.0
DESCRIPTION
Single-Step
If set, the processor executes one instruction and return to debug
mode. The bit remains set after the processor goes into the
debug mode.
Break Now
Force the processor into debug mode if the Break on S/W breakpoint (BS) bit in the processors DSU control register is set. If
cleared, the processor x resumes execution.
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Chapter 15: Hardware Debug Support
Section 15.6: DSU registers
15.6.3 DSU trap register
The DSU trap register is a read-only register that indicates which SPARC trap type that caused the processor to enter debug
mode. When debug mode is force by setting the BN bit in the DSU control register, the trap type will be 0xb (hardware
watchpoint trap).
DTR
Address = 0x90400020
31
13 12 11
RESERVED
EM
4
3
TRAP TYPE
0
0000
Figure 15.4 DSU Trap Register
Table 15.6 Description of DSU Trap Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-13
Reserved
[000...0]
12
EM
0
11-4
Trap Type
[000...0]
8-bit SPARC trap type.
[000...0]
Read=0000b; Write=don’t care.
3-0
DESCRIPTION
Error Mode
Set if the trap would have caused the processor to enter error
mode.
15.6.4 DSU trace buffer time tag counter register
The trace buffer time tag counter increments each clock as long as the processor is running. The counter is stopped when
the processor enters debug mode and restarted when execution is resumed. The value is used as time tag in the instruction and AHB trace buffer.
DTBTCR
Address = 0x90000008
31 30 29
0
RES
DSU_TIME_TAG_VALUE
Figure 15.5 DSU Trace Buffer Time Tag Counter Register
Table 15.7 Description of DSU Trace Buffer Time Tag Counter Register
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Ver. 1.1.0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-30
Reserved
00
29-0
DSU_TIME_TAG_VALUE
[- - -...-]
- 175 -
DESCRIPTION
Read = 00b; Write = Don’t Care
Aeroflex Microelectronic Solutions - HiRel
Chapter 15: Hardware Debug Support
Section 15.6: DSU registers
15.6.5 DSU ASI diagnostic access register
The DSU performs diagnostic accesses to different ASI areas. The value in the ASI diagnostic access register is used as ASI
while the address is supplied from the DSU.
DADAR
Address = 0x90400024
31
8
7
0
ASI
RESERVED
Figure 15.6 DSU ASI Diagnostic Access Register
Table 15.8 Description of DSU ASI Diagnostic Access Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[- - -...-]
7-0
ASI
[- - -...-]
DESCRIPTION
ASI to be used on diagnostic ASI access.
15.6.6 AHB trace buffer control register
The AHB trace buffer is controlled by the AHB Trace Buffer Control Register:
ATBCR
Address = 0x90000040
31
16 15
DCNT
8
RESERVED
7
4
RAM TIM.
3
00
2
1
0
DM EN
Figure 15.7 AHB Trace Buffer Control Register
Table 15.9 Description AHB Trace Buffer Control Register
94-00-00-000
Ver. 1.1.0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-16
DCNT
0x00F2
Trace Buffer Delay Counter
The number of bits actually implemented depends
on the size of the trace buffer.
15-8
Reserved
[000...0]
7-4
RAM TIM
[0000]
3-2
Reserved
01
Read=00b; Write=don’t care.
1
DM
0
Delay Counter Mode
Indicates that the trace buffer is in delay counter
mode.
Trace Buffer RAM Timing Registers
Used for test only, must always be written with
“0000”.
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Chapter 15: Hardware Debug Support
Section 15.6: DSU registers
Table 15.9 Description AHB Trace Buffer Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
0
EN
0
DESCRIPTION
Trace Buffer Enable
0: Disabled
1: Enabled
15.6.7 AHB trace buffer index register
The AHB trace buffer index register contains the address of the next trace line to be written.
ATBIR
Address = 0x90000044
31
4
INDEX
3
0
0000
Figure 15.8 AHB Trace Buffer Index Register
Table 15.10 Description of AHB Trace Buffer Index Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-4
INDEX
[000...0]
3-0
0000
DESCRIPTION
Trace Buffer Index Counter
Note: The number of bits used depends on the
size of the trace buffer.
Read=0000b; Write=don’t care.
15.6.8 AHB trace buffer breakpoint registers
The DSU contains two breakpoint registers for matching AHB addresses. A breakpoint hit is used to freeze the trace buffer
by automatically clearing the enable bit. Freezing can be delayed by programming the DCNT field in the trace buffer control register to a non-zero value. In this case, the DCNT value decrements for each additional trace until it reaches zero,
after which the trace buffer is frozen. A mask register is associated with each breakpoint, allowing breaking on a block of
addresses. Only address bits with the corresponding mask bit set to ‘1’ are compared during breakpoint detection. To
break on AHB load or store accesses, the LD and/or ST bits should be set.
ATBAR1, ATBAR2
Addresses = 0x90000050, 0x90000058
31
2
BADDR[31:2]
1
0
00
Figure 15.9 AHB Trace Buffer Breakpoint Address Registers 1 and 2
Table 15.11 Description of AHB Trace Buffer Breakpoint Address Registers 1 and 2
94-00-00-000
Ver. 1.1.0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-2
BADDR[31:2]
[000...0]
1-0
Reserved
00
- 177 -
DESCRIPTION
Breakpoint Address [31:2]
Read = 00b; write = don’t care
Aeroflex Microelectronic Solutions - HiRel
Chapter 15: Hardware Debug Support
Section 15.6: DSU registers
ATBBMR1, ATBBMR2
Address = 0x90000054, 0x9000005C
31
2
BMASK[31:2]
1
0
LD ST
Figure 15.10 AHB Trace Buffer Breakpoint Mask Registers 1 and 2
Table 15.12 Description of AHB Trace Buffer Breakpoint Mask Register 1 and 2
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-2
BMASK[31:2]
[000...0]
1
LD
0
Break on data load address
0
ST
0
Break on data store address
Breakpoint mask
15.6.9 Instruction trace control register
The instruction trace control register contains a pointer that indicates the next line of the instruction trace buffer to be
written.
ITCR
Address = 0x90110000
31
8
7
0
RESERVED
IT POINTER
Figure 15.11 Instruction Trace Buffer Register
Table 15.13 Description of Instruction Trace Buffer Control Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-8
Reserved
[000...00]
7-0
Instruction trace
pointer
[000...00]
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DESCRIPTION
Pointer to the next line of the instruction
trace buffer.
Aeroflex Microelectronic Solutions - HiRel
Chapter 16: Serial Debug Link
Section 16.1: Overview
Chapter 16: Serial Debug Link
16.1 Overview
The serial debug link consists of a UART connected to the AHB bus as a master as shown in the figure below. A simple communication protocol is supported to transmit access parameters and data. Through the communication link, a read or
write transfer can be generated to any address on the AHB bus.
Baud-rate
generator
RX
Serial port
Controller
8*bitclk
AMBA APB
Receiver shift register
Transmitter shift register
AHB master interface
AHB data/response
TX
AMBA AHB
Figure 16.1 Debug UART Block Diagram
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Chapter 16: Serial Debug Link
Section 16.2: Operation
16.2 Operation
16.2.1 Transmission protocol
The debug UART supports simple protocol where commands consist of a control byte, followed by a 32-bit address, followed by optional write data. A Write access does not return any response, while a read access returns only the read data.
Data is sent on 8-bit basis as shown below.
Start D0
D1
D2
D3
D4
D5
D6
D7 Stop
Figure 16.2 Debug UART Data Frame
Write Command
Send
11 Length -1
Addr[31:24]
Addr[23:16]
Addr[15:8]
Addr[7:0]
10 Length -1
Addr[31:24]
Addr[23:16]
Addr[15:8]
Addr[7:0]
Data[31:24]
Data[23:16]
Data[15:8]
Data[7:0]
Data[31:24]
Data[23:16]
Data[15:8]
Data[7:0]
Read command
Send
Receive
Figure 16.3 Debug UART Commands
Block transfers can be performed by setting the length field to n-1, where n denotes the number of transferred words. For
write accesses, the control byte and address is sent once, followed by the number of data words to be written. The address
is automatically incremented after each data word. For read accesses, the control byte and address is sent once and the
corresponding number of data words is returned.
16.2.2 Baud rate generation
The debug UART contains a 18-bit down-counting scaler to generate the desired baud-rate. The scaler is clocked by the
system clock and generates a UART tick each time it underflows. The scaler is reloaded with the value of the UART scaler
reload register after each underflow. The resulting UART tick frequency should be 8 times the desired baud-rate.
If not programmed by software, the baud rate will be automatically discovered. This is done by searching for the shortest
period between two falling edges of the received data (corresponding to two bit periods). When three identical two-bit
periods have been found, the corresponding scaler reload value is latched into the reload register, and the Baud Rate Lock
(BL) bit is set in the UART Control Register. If the BL bit is reset by software, the baud rate discovery process is restarted. The
baud rate discovery is also restarted when a ‘break’ or framing error is detected by the receiver, allowing the system to
change the baud rate from the external transmitter. For proper baud rate detection, the value 0x55 should be transmitted
to the receiver after reset or after sending a break.
The best scaler value for manually programming the baudrate can be calculated as follows:
scaler = (((system_clk*10)/(baudrate*8))-5)/10
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Chapter 16: Serial Debug Link
Section 16.3: Registers
16.3 Registers
The debug UART can be programmed through the registers mapped into APB address space.
Table 16.1 Description of Debug UART Register Addresses
REGISTER
APB ADDRESS
AHB UART Status Register (SDLSTR)
0x80000704
AHB UART Control Register (SDLCTR)
0x80000708
AHB UART Scaler Register (SDLSCL)
0x8000070C
SDLCTR
Address = 0x80000704
31
2
RESERVED
1
0
31
BL EN RES
Figure 16.4 Debug UART Control Register
Table 16.2 Description of Debug UART Control Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-2
Reserved
[- - -...-]
1
BL
0
Baud Rate Locked
This bit is automatically set when the baud rate is
locked.
0
RE
0
Receiver Enable
If set, both the transmitter and receiver are
enabled.
SDLSTR
Address = 0x80000708
31
6
RESERVED
FE
5
4
OV
3
2
1
0
TH TS DR
Figure 16.5 Debug UART Status Register
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Chapter 16: Serial Debug Link
Section 16.3: Registers
Table 16.3 Description of Debug UART Status Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-7
Reserved
6
FE
0
5
Reserved
0
4
OV
0
3
Reserved
0
2
TH
1
Transmitter Hold Register Empty
Indicates that the transmitter hold register is empty. Read only.
1
TS
1
Transmitter Shift Register Empty
Indicates that the transmitter shift register is empty.
0
DR
0
Data Ready
Indicates that new data has been received by the AHB master
interface.
Frame Error
Indicates that a frame error was detected.
Overrun
Indicates that one or more characters have been lost due to over
run.
SDLSCL
Address = 0x8000070C
31
14 13
0
RESERVED
SRV
Figure 16.6 Debug UART Scaler Reload Register
Table 16.4 Description of Debug UART Scaler Reload Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-14
Reserved
[000...0]
13-0
SRV
[000...0]
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DESCRIPTION
Scaler Reload Value
See Section 15.2.2. The optimum value is:
SCALER = ((SYSCLK*10)/baudrate*8))-5/10.
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Chapter 17: JTAG Debug Link
Section 17.1: Overview
Chapter 17: JTAG Debug Link
17.1 Overview
The JTAG debug interface provides access to the AMBA AHB bus through JTAG. The JTAG debug interface implements a
simple protocol that translates JTAG instructions to AHB transfers. Through this link, a read or write transfer can be generated to any address on the AHB bus.
TDI
JTAG TAP
Controller
TCK
TMS
JTAG Communication
Interface
TDO
AHB master interface
AMBA AHB
Figure 17.1 JTAG Debug Link Block Diagram
17.2 Operation
17.2.1 Transmission protocol
The JTAG Debug link decodes two JTAG instructions and implements two JTAG data registers: the JTAG Debug Link Command and Address Register and Data Register. A read access is initiated by setting the Write bit, and the SIZE and
AHB_ADDRESS fields of the Command and Address Register and shifting out the data over the JTAG port. The AHB read
access is performed and data is ready to be shifted out of the Data Register. Write accesses are performed by setting the
Write bit, and the SIZE and AHB_ADDRESS fields of the Command and Address Register, followed by shifting in write data
into the Data Register. Sequential transfers can be performed by shifting in command and address for the transfer start
address and setting the SEQ bit in Data Register for subsequent accesses. The SEQ bit increments the AHB address for the
subsequent access. Sequential transfers should not cross a 1 KB boundary. Sequential transfers are always word based.
JDLCAR
34 33
W
Internal Serial
32 31
0
SIZE
AHB_ADDRESS
Figure 17.2
Table 17.1 Description of JTAG Debug Link Command and Address Register
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
34
W
0
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DESCRIPTION
Write
0: Read transfer
1: Write transfer
Aeroflex Microelectronic Solutions - HiRel
Chapter 17: JTAG Debug Link
Section 17.3: Registers
Table 17.1 Description of JTAG Debug Link Command and Address Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
33-32
SIZE
00
31-0
AHB_ADDRESS
[000...0]
DESCRIPTION
AHB Transfer Size
00: Byte
01: Half word
10: Word
11: Reserved
JDLDR
32
Internal Serial
31
0
SQ
AHB_DATA
Figure 17.3 JTAG Debug Link Data Register
Table 17.2 Description of JTAG Debug Link Data Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
32
SQ
0
Sequential Transfer
0: Non-sequential transfer
1: When read data is shifted out or write data
shifted in, the subsequent transfer will be to the
word address.
31-0
AHB_DATA
[000...0]
For byte and half-word transfers, data is aligned
according to big-endian order where data with
address offset 0 data is placed in MSB bits.
17.3 Registers
The core does not implement any registers mapped in the AMBA AHB or APB address space.
17.4 Boundary Scan
The JTAG Tap controller supports boundary scan to permit board level interconnect and diagnostic through a JTAG chain.
The JTAG TAP controller supports nine instructions: SAMPLE, PRELOAD, BYPASS, EXTEST, INTEST, Highz, IDCODE,
AHBADDR, and AHBDATA. The IDCODE will be read as 0x10699649.
The boundary scan consists of 1 cell bypass, 32 cell IDCODE, 35 cell AHBADDR, 33 cell AHBDATA, and 478 cell scan chain
registers. Each register is operated based on the instruction code loaded the TAP controller. The clock frequency for operating the boundary scan is 10 MHz. A Boundary Scan Descriptive Language (BSDL) file providing details on the boundary
scan operations is available at www.aeroflex.com/LEON.
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Chapter 18: CLKGATE Clock Gating Unit
Section 18.1: Overview
Chapter 18: CLKGATE Clock Gating Unit
18.1 Overview
The CLKGATE clock gating unit provides a means to save power by disabling the clock to unutilized core blocks. The unit
can enable and disable up to 8 individual clock signals or reset the core state and registers to default.
18.2 Operation
The operation of the clock gating unit is controlled through three registers: the unlock, clock enable and core reset registers. The clock enable register defines if a clock is enabled or disabled. A ‘1’ in a bit location enables the corresponding
clock, while a ‘0’ disables the clock. The core reset register resets each core to a default state. A reset will be generated as
long as the corresponding bit is set to ‘1’. The bits in clock enable and core reset registers can only be written when the corresponding bit in the unlock register is 1. If the a bit in the unlock register is 0, the corresponding bits in the clock enable
and core reset registers cannot be written.
To gate the clock for a core, the following procedure should be applied:
1. Disable the core through software to make sure it does not initialize any AHB accesses
1. Write a 1 to the corresponding bit in the unlock register
2. Write a 0 to the corresponding bit in the clock enable register
3. Write 1 to the corresponding bit in the reset register to ensure core logic and I/O are in a known state
4. Write a 0 to the corresponding bit in the unlock register
To enable the clock for a core, the following procedure should be applied
1. Write a 1 to the corresponding bit in the unlock register
5. Write a 1 to the corresponding bit in the clock enable register
6. Write a 0 to the corresponding bit in the unlock register
7. Write a 1 to the corresponding bit in the core reset register
8. Write a 0 to the corresponding bit in the unlock register
Repeat this procedure to reset a specific core using the core reset register in place of the clock enable register.
The cores connected to the clock gating unit are defined in the table below:
Table 18.1 Clocks Controlled by CLKGATE Unit
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BIT
FUNCTIONAL MODE
0
GRSPW Spacewire link 0
1
GRSPW Spacewire link 1
2
GRSPW Spacewire link 2
3
GRSPW Spacewire link 3
4
CAN core 1 & 2
5
GRETH 10/100 Mbit Ethernet MAC (AHB Clock)
6
GRPCI 32-bit PCI Bridge (AHB Clock)
7
GR1553B controller
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Chapter 18: CLKGATE Clock Gating Unit
Section 18.3: Registers
18.3 Registers
Table 18.2 shows the clock gating unit registers. The base address for the registers is 0x80000600.
Table 18.2 Clock Unit Control Registers
APB ADDRESS
FUNCTIONAL MODULE
RESET VALUE
0x80000600
Unlock Register
00000000
0x80000604
Clock Enable Register
01111111
0x80000608
Core Reset Register
00000000
NOTE: The clock for the GR1553B is disabled after reset and must be enabled before the unit can be used.
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Chapter 19: SPI Controller
Section 19.1: Overview
Chapter 19: SPI Controller
19.1 Overview
The SPI controller provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus. The SPI core is
controlled through the APB address space, and can only work as master. The SPI bus parameters are highly configurable
via registers. The controller has configurable word length, bit ordering and clock gap insertion. To facilitate reuse of existing software drivers, the controller’s interface is compatible with the SPI controller interface in the Free-scale MPC83xx
series.
SPICTRL
A
M
B
A
Mode register
A
P
B
Transmit register
Event register
Mask register
Control
Transmit
FIFO
Master ctrl
Com. register
Receive register
Clock gen.
Receive
FIFO
S
y
n
c
r
e
g
i
s
t
e
SPICLK
SPIMISO
SPIMOSI
Figure 19.1 Block Diagram
19.2 Operation
19.2.1 SPI transmission protocol
The SPI bus is a full-duplex synchronous serial bus. Transmission starts when the clock line SPICLK transitions from its idle
state. Data is transferred from the master through the Master-Output-Slave-Input (SPIMOSI) signal and from the slave
through the Master-Input-Slave-Output (SPIMISO) signal. In a system with only one master and one slave, the Slave Select
input of the slave may be always active and the master does not need to have a slave select output.
During a transmission on the SPI bus, data is either changed or read at a transition of SPICLK. If data has been read at edge
n, data is changed at edge n+1. If data is read at the first transition of SPICLK the bus is said to have clock phase 0 and if
data is changed at the first transition of SPICLK, the bus has clock phase 1. The idle state of SPICLK may be either high or
low. If the idle state of SPICLK is low, the bus has clock polarity 0 and if the idle state is high the clock polarity is 1. The combined values of clock polarity (CPOL) and clock phase (CPHA) determine the mode of the SPI bus. Figure 19.2 shows one
byte (0x55) being transferred MSb first over the SPI bus under the four different modes. Note: The idle state of the SPIMOSI
line is ‘1’ and that CPHA = 0 means that the devices must have data ready before the first transition of SPICLK. The figure
does not include the SPIMISO signal, the behavior of this line is the same as for the SPIMOSI signal.
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Chapter 19: SPI Controller
Section 19.2: Operation
CPOL = 0
CPHA = 0
SPICLK
Mode 0
SPIMOSI
CPHA = 1
SPICLK
Mode 1
SPIMOSI
CPOL = 1
CPHA = 0
SPICLK
Mode 2
SPIMOSI
CPHA = 1
SPICLK
Mode 3
SPIMOSI
Figure 19.2 SPI Transfer of Byte 0x55 in All Modes
19.2.2 Receive and transmit queues
The core’s transmit queue consists of the transmit register and the transmit FIFO. The receive queue consists of the receive
register and the receive FIFO. The total number of words that can exist in each queue is thus the FIFO depth plus one.
When the core has one or more free slots in the transmit queue, it asserts the Not full (NF) bit in the event register. Software may only write to the transmit register when this bit is asserted. When the core has received a word, as defined by
word length (LEN) in the Mode register, it places the data in the receive queue. When the receive queue has one or more
elements stored the Event register bit Not empty (NE) will be asserted. The receive register will only contain valid data if
the Not empty bit is asserted and software should not access the receive register unless this bit is set. If the receive queue
is full and the core receives a new word, an overrun condition occurs. The received data will be discarded and the Overrun
(OV) bit in the Event register will be set.
19.2.3 Clock generation
The core only generates the clock in master mode, the generated frequency depends on the system clock frequency and
the Mode register fields DIV16, FACT, and PM. Without DIV16 the SPICLK frequency is:
SCKFrequency = -----AMBAclockfrequency
--------------------------------------------( 4 – ( 2 ⋅ FACT ) ) ⋅ ( PM + 1 )
With DIV16 enabled the frequency of SPICLK is derived through:
SCKFrequency = ---------AMBAclockfrequency
------------------------------------------------16 ⋅ ( 4 – ( 2 ⋅ FACT ) ) ⋅ ( PM + 1 )
NOTE: The fields of the Mode register, which includes DIV16, FACT and PM, should not be changed when the core is
enabled. If the FACT field is set to 1 the core’s register interface is compatible with the register interface found in MPC83xx
SoCs. If the FACT field is set to 0, the core can generate an SPICLK clock with higher frequency.
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Chapter 19: SPI Controller
Section 19.3: Registers
19.2.4 Operation (master-only)
Master operation transmits a word when there is data available in the transmit queue. When the transmit queue is empty,
the core will drive SPICLK to its idle state.
19.3 Registers
The core is programmed through registers mapped into APB address space.
Table 19.1 SPI Controller Registers
Register
APB address
Capability register
0x80100100
Mode register
0x80100120
Event register
0x80100124
Mask register
0x80100128
Command register
0x8010012C
Transmit register
0x80100130
Receive register
0x80100134
SPICPR
Address = 0x80100100
31
24
23
20
SSSZ
19
MXL
15
8
FDEPTH
7
SR
6
17
RESERVED
5
4
SFT
16
SSEN
0
REV
Figure 19.3 GR1553B BM RT Mode Code Filter Register
Table 19.2 Description of SPI Controller Capability Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-24
SSSZ
0x01
Slave select register size
If the core has been configured with slave select signals this field
contains the number of available signals. This field is only valid is
the SSEN bit 16) is ‘1
23-20
MXL
0000
Max word length
19-17
RESERVED
00
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Chapter 19: SPI Controller
Section 19.3: Registers
Table 19.2 Description of SPI Controller Capability Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
16
SSEN
1
Slave select enable
If the core has a slave select register, and corresponding slave
select lines, the value of this field is one. Otherwise the value of
this field is zero.
15-8
FDEPTH
0x10
FIFO depth
This field contains the depth of the core’s internal FIFOs. The
number of words the core can store in each queue is FDEPTH+1,
since the transmit and receive registers can contain one word
each.
7
SR
1
SYNCRAM
6-5
SFT
00
Fault tolerance
4-0
REV
00101
Core revision
SPIMD
31
Address = 0x80100120
30
29
28
27
26
RESV LOOP CPOL CPHA DIV16 REVD
15
14
RESERVED
13
12
FACT
RESV
25
24
MS
EN
11
23
20
19
16
LEN
7
CG
PM
6
3
RESERVED
2
1
IGSEL CITE
0
RESV
Figure 19.4
Table 19.3 Description of SPI Controller Mode Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
RESERVED
0
30
LOOP
0
Loop mode:
When this bit is set, and the core is enabled, the core’s transmitter
and receiver are interconnected and the core operates in loopback mode. The core still detect and will be disabled on Multiplemaster errors.
29
CPOL
0
Clock polarity:
Determines the polarity (idle state) of the SCK clock.
28
CPHA
0
Clock polarity:
Determines the polarity (idle state) of the SCK clock.
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Chapter 19: SPI Controller
Section 19.3: Registers
Table 19.3 Description of SPI Controller Mode Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
27
DIV16
0
Divide by 16:
Divide system clock by 16, see description of PM field and see
section 19.2.3 on clock generation. This bit has no significance in
slave mode.
26
REVD
0
Reverse data:
When this bit is ‘0’ data is transmitted LSB first, when this bit is ‘1’
data is transmitted MSB first. This bit affects the layout of the
transmit and receive registers.
25
MS
1
Master/Mode:
1: Operates as a master
Read = 1; Write = don’t care
24
EN
0
Enable core:
When this bit is set to ‘1’ the core is enabled. No fields in the
mode register should be changed while the core is enabled. This
bit can be set to ‘0’ by software or by the core if a multiple-master
error occurs.
23-20
LEN
0000
Word length:
The value of this field determines the length in bits of a transfer
on the SPI bus. Values are interpreted as:
0b0000 - 32-bit word length
0b0001-0b0010 - Illegal values
0b0011-0b1111 - Word length is LEN+1, allows words of length 416 bits
The value of this field must never specify a word length that is
greater than the maximum allowed word length specified by the
MAXWLEN field in the Capability register.
19-16
PM
0000
Prescale modulus:
This value is used in master mode to divide the system clock and
generate the SPI SCK clock. The value in this field depends on the
value of the FACT bit.
If bit 13 (FACT) is ‘0’:The system clock is divided by 4*(PM+1) if the
DIV16 field is ‘0’ and 16*4*(PM+1) if the DIV16 field is set to ‘1’. The
highest SCK frequency is attained when PM is set to 0b0000 and
DIV16 to ‘0’, this configuration gives a SCK frequency that is (system clock)/4. With this setting the core is compatible with the SPI
register interface found in MPC83xx SoCs.
If bit 13 (FACT) is ‘1’: The system clock is divided by 2*(PM+1) if
the DIV16 field is ‘0’ and 16*2*(PM+1) if the DIV16 field is set to ‘1’.
The highest SCK frequency is attained when PM is set to 0b0000
and DIV16 to ‘0’, this configuration gives a SCK frequency that is
(system clock)/2.
In slave mode, the value of this field defines the number of system clock cycles that the SCK input must be stable for the core to
accept the state of the signal.
15-14
RESERVED
00
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Chapter 19: SPI Controller
Section 19.3: Registers
Table 19.3 Description of SPI Controller Mode Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
13
FACT
0
PM factor:
If this bit is 1, the core’s register interface is no longer compatible
with the MPC83xx register interface. The value of this bit affects
how the PM field is utilized to scale the SPI clock. See the description of PM field.
12
RESERVED
0
11-7
CG
00000
6-3
RESERVED
0000
2
IGSEL
0
Ignore SPISEL input:
If this bit is set to ‘1’, then the core ignores the value of the SPISEL
input.
1
CITE
0
Require Clock Idle for Transfer End:
If this bit is ‘0’, the core regards the transfer of a word as completed when the last bit has been sampled. If this bit is set to ‘1’,
the core waits until it has set the SCK clock to its idle level (see CI
field) before regarding a transfer as completed. This setting only
affects the behavior of the TIP status bit and automatic slave
select toggling at the end of a transfer when the clock phase (CP
field) is ‘0’.
0
RESERVED
0
Clock gap:
The value of this field is only significant in master mode. The core
inserts CG SCK clock cycles between each consecutive word. This
only applies when the transmit queue is kept non-empty. After
the last word of the transmit queue has been sent, the core goes
into an idle state and continues to transmit data as soon as a new
word is written to the transmit register, regardless of the value in
CG. A value of 0b00000 in this field enables back-to-back transfers.
SPIER
Address = 0x80100124
31 30
15 14 13 12 11 10
TIP
RESERVED
LT RES OV
RES
9
8
NE NF
7
0
Reserved
Figure 19.5 SPI Controller Event Register
Table 19.4: Description of SPI Controller Event Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
TIP
0
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DESCRIPTION
Transfer in progress LF (Line Feed). This bit is ‘1’ when the core
has a transfer in progress. Writes have no effect.
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Chapter 19: SPI Controller
Section 19.3: Registers
Table 19.4: Description of SPI Controller Event Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
30-15
RESERVED
[000...0]
14
LT
0
Last character LF. This bit is set when a transfer completes if the
transmit queue is empty and the LST bit in the Command register
has been written. This bit is cleared by writing ‘1’, writes of ‘0’
have no effect.
13
RESERVED
0
RESERVED LF. Read as zero and should be written to zero to
ensure forward compatibility.
12
OV
0
Overrun LF. This bit gets set when the receive queue is full and
the core receives new data. The core continues communicating
over the SPI bus, but discards the new data. This bit is cleared by
writing ‘1’, writes of ‘0’ have no effect.
11-10
RESERVED
0
9
NE
0
Not empty LF. This bit is set when the receive queue contains one
or more elements. It is cleared automatically by the core; writes
have no effect.
8
NF
0
Not full LF. This bit is set when the transmit queue has room for
one or more words. It is cleared automatically by the core when
the queue is full; writes have no effect.
7-0
RESERVED
[000...0]
RESERVED
Read as zero and should be written to zero to ensure forward
compatibility.
RESERVED LF. Read as zero and should be written to zero to
ensure forward compatibility.
SPIMR
31
Address = 0x80100120
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
TIPE
RESERVED
10
9
8
LTE RES OVE UNE MMEE NEE NFE
7
0
RESERVED
Figure 19.6 SPI Controller Mask Register
Table 19.5 Description of SPI Controller Mask Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31
TIPE
0
Transfer in progress enable
When this bit is set ,the core generates an interrupt when the TIP
bit in the Event register transitions from ‘0’ to ‘1’.
30-15
RESERVED
[000...0]
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RESERVED
Read as zero and should be written to zero to ensure forward
compatibility.
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Chapter 19: SPI Controller
Section 19.3: Registers
Table 19.5 Description of SPI Controller Mask Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
14
LTE
0
Last character enable
When this bit is set, the core generates an interrupt when the LT
bit in the Event register transitions from ‘0’ to ‘1’.
13
RESERVED
0
RESERVED
Read as zero and should be written to zero to ensure forward
compatibility.
12
OVE
0
Overrun enable
When this bit is set ,the core generates an interrupt when the OV
bit in the Event register transitions from ‘0’ to ‘1’.
11
UNE
0
Underrun enable
When this bit is set, the core generates an interrupt when the UN
bit in the Event register transitions from ‘0’ to ‘1’.
10
MMEE
0
Multiple-master error enable
When this bit is set, the core generates an interrupt when the
MME bit in the Event register transitions from ‘0’ to ‘1’.
9
NEE
0
Not empty enable
When this bit is set, the core generates an interrupt when the NE
bit in the Event register transitions from ‘0’ to ‘1’.
8
NFE
0
Not full enable
When this bit is set, the core generates an interrupt when the NF
bit in the Event register transitions from ‘0’ to ‘1’.
7-0
RESERVED
0
RESERVED
Read as zero and should be written to zero to ensure forward
compatibility.
SPICCR
Address = 0x8010012C
31
23 22 21
RESERVED
0
LST
RESERVED
Figure 19.7 SPI Controller Command Register
Table 19.6 Description of SPI Controller Command Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31-23
RESERVED
0
94-00-00-000
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DESCRIPTION
RESERVED
Read as zero and should be written to zero to ensure forward
compatibility.
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Chapter 19: SPI Controller
Section 19.3: Registers
Table 19.6 Description of SPI Controller Command Register
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
22
LST
0
Last
After this bit has been written to ‘1’ the core sets the Event register bit LT when a character has been transmitted and the transmit
queue is empty. If the core is operating in 3-wire mode, the Event
register bit is set when the whole transfer has completed. This bit
is automatically cleared when the Event register bit has been set
and is always read as zero.
21-0
RESERVED
0
RESERVED
Read as zero and should be written to zero to ensure forward
compatibility.
SPITR
Address = 0x80100130
31
0
TDATA
Figure 19.8 SPI Controller Transmit Register
Table 19.7 Description of SPI Controller Transmit Register
BIT
NUMBER(S)
BIT
NAME
RESET
STATE
DESCRIPTION
31-0
TDATA
0
Transmit data (TDATA) - Writing a word into this register places
the word in the transmit queue. This register only reacts to writes
if the Not full (NF) bit in the Event register is set. The layout of this
register depends on the value of the REV field in the Mode register:
Rev = ‘0’: The word to transmit should be written with its least significant bit at bit 0.
Rev = ‘1’: The word to transmit should be written with its most
significant bit at bit 31.
SPIRR
Address = 0x80100134
31
0
TDATA
Figure 19.9 Description of SPI Controller Receive Register
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Section 19.3: Registers
Table 19.8 Description of SPI Controller Receive Register
94-00-00-000
Ver. 1.1.0
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-0
RDATA
[- - - ...-]
Receive data (RDATA) - This register contains valid receive data
when the Not empty (NE) bit of the Event register is set. The
placement of the received word depends on the Mode register fields LEN and REV:
For LEN = 0b0000 - The data is placed with its MSb in bit 31
and its LSb in bit 0.
For other lengths and REV = ‘0’ - The data is placed with its
MSB in bit 15.
For other lengths and REV = ‘1’ - The data is placed with its LSB
in bit 16.
To illustrate this, a transfer of a word with eight bits (LEN = 7)
that are all set to one have the following placement:
REV = ‘0’ - 0x0000FF00
REV = ‘1’ - 0x00FF0000
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.1: Overview
Chapter 20: Dual Redundant MIL-STD-1553B Interface
(GR1553B)
20.1 Overview
This interface core connects the AMBA AHB/APB bus to a dual redundant MIL-STD-1553B bus and can operate as a Bus
Controller, Remote Terminal or Bus Monitor.
MIL-STD-1553B is a bus standard for transferring data between up to 32 devices over a shared (typically dual-redundant)
differential wire. The bus is designed for predictable real-time behavior and fault-tolerance. The raw bus data rate is fixed
at 1 Mbit/s, giving a maximum payload data rate of around 770 kbit/s.
One of the terminals on the bus is the Bus Controller (BC) which controls all traffic on the bus. The other terminals are
Remote Terminals (RTs), which act on commands issued by the bus controller. Each RT is assigned a unique address
between 0-30. In addition, the bus may have passive Bus Monitors (BMs) connected.
There are 5 possible data transfer commands on the MIL-STD-1553 bus:
• BC-to-RT transfer (“receive”)
• RT-to-BC transfer (“transmit”)
• RT-to-RT transfer
• Broadcast BC-to-RTs
• Broadcast RT-to-RTs
Each transfer can contain 1-32 data words, each16 bits wide.
The bus controller can also send “mode codes” to the RTs to perform administrative tasks such as time synchronization,
and reading out terminal status.
20.2 Electrical interface
The core is connected to the MIL-STD-1553B bus wire through single or dual transceivers, isolation transformers and transformer or stub couplers as shown in Figure 20.1. If single-redundancy is used, the unused bus receive P/N signals should
be tied both-high or both-low. The transmit/receive enables may be inverted on some transceivers. See the standard and
the respective component’s data sheets for more information on the electrical connection.
Bus A
txinhA
txA_P
txA_N
rxA_P
rxA_N
rxenA
GR1553B
Bus B
txinhB
txB_P
txB_N
rxB_P
rxB_N
rxenB
Terminal boundary
Figure 20.1 Interface between core and MIL-STD-1553B bus (dual-redundant, transformer coupled)
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.3: Operation
20.3 Operation
20.3.1 Operating modes
The core contains three separate control units for the Bus Controller, Remote Terminal and Bus Monitor handling, with a
shared 1553 codec. The operating mode of the core is controlled by starting and stopping of these units via register writes.
At power-up, the GR1553B clock is disabled rendering the BC and RT inoperative.
The BC and RT parts of the core can not be active on the 1553 bus at the same time. While the BC is running or suspended,
only the BC (and possibly BM) has access to the 1553 bus, and the RT can only receive and respond to commands when
both the BC schedules are completely stopped (not running or even suspended).
The Bus Monitor, however, is only listening on the codec receivers and operates regardless of the enabled/disabled state of
the other two parts.
20.3.2 Register interface
The core is configured and controlled through control registers accessed over the APB bus. Each of the BC, RT, and BM
parts has a separate set of registers, plus there is a small set of shared registers.
Some of the control register fields for the RT are protected using a ‘key’, a field in the same register that has to be written
with a certain value for the write to take effect. The purpose of the keys are to give RT/BM designers a way to ensure that
the software can not interfere with the bus traffic by enabling the BC or changing the RT address. If the software is built
without knowledge of the key to a certain register, it is very unlikely that it will accidentally perform a write with the correct key to that control register.
20.3.3 Interrupting
The core has one interrupt output which can be generated from several different source events. Which events should
cause an interrupt can be controlled through the IRQ Enable Mask register.
20.3.4 MIL-STD-1553 Codec
The core’s internal codec receives and transmits data words on the 1553 bus and generates and checks sync patterns and
parity. Loop-back checking logic checks that each transmitted word is also seen on the receive inputs. If the transmitted
word is not echoed back, the transmitter stops and signals an error condition which is then reported back to the user.
20.4 Bus Controller Operation
20.4.1 Overview
When operating as Bus Controller, the core controls message transactions on the MIL-STD-1553 bus.
This mode works based on a scheduled transfer list concept. The software sets up a sequence of transfer descriptors and
branches, data buffers for send and received data and an IRQ pointer ring buffer in the available memory space. When the
schedule is started (through a BC action register write), the core processes the list, performs the transfers one after another
and writes resulting status into the transfer list and incoming data into the corresponding buffers.
20.4.2 Timing control
In each transfer descriptor in the schedule is a “slot time” field. If the scheduled transfer finishes sooner than its slot time,
the core pauses the remaining time before scheduling the next command. This allows the user to accurately control the
message timing during a communication frame.
If the transfer uses more than its slot time, the overshooting time will be subtracted from the following command’s time
slot. The following command may in turn borrow time from the following command and so on. The core can keep track of
up to one second of borrowed time, and will not insert pauses again until the balance is positive, except for inter-message
gaps and pauses that the standard requires.
If you wish to execute the schedule as fast as possible you can set all slot times in the schedule to zero. If you want to group
a number of transfers you can move all the slot time to the last transfer.
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Section 20.4: Bus Controller Operation
The schedule can be stopped or suspended by writing into the BC action register. When suspended, the schedule’s time
will still be accounted so that the schedule timing will still be correct when the schedule is resumed. When stopped, on the
other hand, the schedule’s timers will be reset.
20.4.3 Bus selection
Each transfer descriptor has a bus selection bit that allows you to control on which one of the two redundant buses (‘0’ for
bus A, ‘1’ for bus B) the transfer occurs.
Another way to control the bus usage is through the per-RT bus swap register which has one register bit for each RT
address. Writing a ‘1’ to a bit in the register inverts the meaning of the bus selection bit for all transfers to the corresponding RT, so ‘0’ now means bus ‘B’ and ‘1’ means bus ‘A’. This allows you to switch all transfers to one or a set of RTs over to the
other bus with a single register write and without having to modify any descriptors.
The hardware determines which bus to use by taking the exclusive-or of the bus swap register bit and the bus selection
bit. Normally, it only makes sense to use one of these two methods for each RT, either the bus selection bit is always zero
and the swap register is used, or the swap register bit is always zero and the bus selection bit is used.
If the bus swap register is used for bus selection, the store-bus descriptor bit can be enabled to automatically update the
register depending on transfer outcome. If the transfer succeeded on bus A, the bus swap register bit is set to ‘0’, if it succeeds on bus B, the swap register bit is set to ‘1’. If the transfer fails, the bus swap register is set to the opposite value.
20.4.4 Secondary transfer list
The core can be set up with a secondary “asynchronous” transfer list with the same format as the ordinary schedule. This
transfer list can be commanded to start at any time during the ordinary schedule. While the core is waiting for a scheduled
command’s slot time to finish, it checks if the next asynchronous transfer’s slot time is lower than the remaining sleep time.
In that case, the asynchronous command will be scheduled.
If the asynchronous command doesn’t finish in time, time will be borrowed from the next command in the ordinary schedule. In order to not disturb the ordinary schedule, the slot time for the asynchronous messages must be set to pessimistic
values.
The exclusive bit in the transfer descriptor can be set if one does not want an asynchronous command scheduled during
the sleep time following the transfer.
Asynchronous messages will not be scheduled while the schedule is waiting for a sync pulse or the schedule is suspended
and the current slot time has expired since it is not known when the next scheduled command will start.
20.4.5 Interrupt generation
Each command in the transfer schedule can be set to generate an interrupt after certain transfers have completed, with or
without error. Invalid command descriptors always generate interrupts and stop the schedule. Before a transfer-triggered
interrupt is generated, the address to the corresponding descriptor is written into the BC transfer-triggered IRQ ring buffer
and the BC Transfer-triggered IRQ Ring Position Register is incremented.
A separate error interrupt signals DMA errors. If a DMA error occurs when reading/writing descriptors, the executing
schedule will be suspended. DMA errors in data buffers will cause the corresponding transfer to fail with an error code (see
Table 20.4).
Whether any of these interrupt events actually cause an interrupt request on the AMBA bus is controlled by the IRQ Mask
Register setting.
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.4: Bus Controller Operation
20.4.6 Transfer list format
The BC’s transfer list is an array of transfer descriptors mixed with branches as shown in Table 20.3. Each entry has to be
aligned to start on a 128-bit (16-byte) boundary. The two unused words in the branch case are free to be used by software
to store arbitrary data.
Table 20.1 GR1553B Transfer Descriptor Format
Offset
Value for transfer descriptor
DMA R/
W
Value for branch
DMA R/
W
0x00
Transfer descriptor word 0 (see Table 177)
R
Condition word (see table)
R
0x04
Transfer descriptor word 1 (see Table 178)
R
Jump address, 128-bit
aligned
R
Data buffer pointer, 16-bit aligned.
R
Unused
-
W
Unused
-
0x08
For write buffers, if bit 0 is set the received
data is discarded and the pointer is ignored.
This can be used for RT-to-RT transfers
where the BC is not interested in the data
transferred.
0x0C
Result word, written by core
The transfer descriptor words are structured as shown in Table 177 and 178 below.
Offset 0x00
31
30
29
28
DID
RES
EXCL
IRQE
27
26
25
24
IRQN SUSE SUSN
23
RETMD
22
20
NRET
19
18
STBUS GAP
17
16
RESERVED
15
0
RESERVED
Figure 20.2 GR1553B BC Transfer Descriptor Word 0
Table 20.2 Description of GR1553B BC Transfer Descriptor Word 0 (Address offset 0x00)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
DID
0
Must be 0 to identify as descriptor
30
RES
0
Always write a 0 in this position
29
EXCL
0
Exclusive time slot - Do not schedule asynchronous messages
28
IRQE
0
IRQ after transfer on Error
27
IRQN
0
IRQ normally - Always interrupts after transfer
26
SUSE
0
Suspend on Error - Suspends the schedule (or stops the async
transfer list) on error
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DESCRIPTION
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.4: Bus Controller Operation
Table 20.2 Description of GR1553B BC Transfer Descriptor Word 0 (Address offset 0x00)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
25
SUSN
0
Suspend normally - Always suspends after transfer
24-23
RETMD.
00
Retry mode 00 - Retry on same bus only. 01 - Retry alternating on
both buses
10: Retry first on same bus, then on alternating bus. 11 RESERVED, do not use
22-20
NRET
00
Number of retries - Number of automatic retries per bus
The total number of tries (including the first attempt) is NRET+1
for RETMD=00, 2 x (NRET+1) for RETMD=01/10
19
STBUS
0
Store bus - If the transfer succeeds and this bit is set, store the bus
on which the transfer succeeded (0 for bus A, 1 for bus B) into the
per-RT bus swap register. If the transfer fails and this bit is set,
store the opposite bus instead.
18
GAP
0
Extended intermessage gap - If set, adds an additional amount of
gap time, corresponding to the RTTO field, after the transfer
17-16
RESERVED
0
RESERVED- Set to 0 for forward compatibility
15-0
STIME
[000...0]
Slot time - Allocated time in 4 microsecond units, remaining time
after transfer will insert delay
Offset 0x04
31
30
DUM
BUS
29
26
25
21
RTTO
15
11
RTAD1
20
16
RTAD2
10
9
TR
8
7
RTSA1
RTSA2
6
5
4
3
2
1
0
WCMC
Figure 20.3
Table 20.3 GR1553B BC Transfer Descriptor Word 1 (Address offset 0x04)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31
DUM
0
Dummy transfer
If set to ‘1’ no bus traffic is generated and transfer “succeeds”
immediately
For dummy transfers, the EXCL,IRQN,SUSN,STBUS,GAP,STIME settings are still in effect, other bits and the data buffer pointer are
ignored.
30
BUS
0
Bus selection
Bus to use for transfer, 0 - Bus A, 1 - Bus B
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.4: Bus Controller Operation
Table 20.3 GR1553B BC Transfer Descriptor Word 1 (Address offset 0x04)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
29-26
RTTO
0000
RT Timeout
Extra RT status word timeout above nominal in units of 4 us (0000
-14 us, 1111 -74 us). NOTE: This extra time is also used as extra
intermessage gap time if the GAP bit is set.
25-21
RTAD2
0000
Second RT Address for RT-to-RT transfer
See Table 175 for details on how to setup
RTAD1,RTSA1,RTAD2,RTSA2,WCMC,TR for different transfer types.
20-16
RTSA2
0000
Second RT Subaddress for RT-to-RT transfer
See Table 178 for details on how to setup
RTAD1,RTSA1,RTAD2,RTSA2,WCMC,TR for different transfer types.
15-11
RTAD1
0000
RT Address
10
TR
0
9-5
RTSA1
[000...0]
4-0
WCMC
00000
Transmit/receive
NOTE: Bits 15:0 correspond to the (first) command word on the
1553 bus
RT Subaddress
Word count/Mode code
Offset 0x0C
31
30
24
0
23
16
RESERVED
RT2ST
15
8
7
RTST
4
RETCNT
3
2
RES
0
TFRST
Figure 20.4 GR1553B Transfer Descriptor Result Word
Table 20.4 GR1553B Transfer Descriptor Result Word (Address offset 0x0C)
BIT
NUMBER(S)
BIT NAME
31
94-00-00-000
Ver. 1.1.0
RESET
STATE
0
DESCRIPTION
Always written as 0
30-24
RESERVED
[000...0]
RESERVED
23-16
RT2ST
[000...0]
RT 2 Status Bits
Status bits from receiving RT in RT-to-RT transfer, otherwise 0
Same bit pattern as for RTST below
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.4: Bus Controller Operation
Table 20.4 GR1553B Transfer Descriptor Result Word (Address offset 0x0C)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
15-8
RTST
[000...0]
RT Status Bits
Status bits from RT (transmitting RT in RT-to-RT transfer)
15 - Message error, 14 - Instrumentation bit or RESERVED bit set,
13 - Service request,
12 - Broadcast command received, 11 - Busy bit, 10 - Subsystem
flag, 9 - Dynamic bus control acceptance, 8 - Terminal flag
7-4
RETCNT
[000...0]
Retry count
Number of retries performed
3
RESERVED
0
2-0
TFRST
000
RESERVED
Transfer status
Outcome of last try:
000 - Success (or dummy bit was set)
001 - RT did not respond (transmitting RT in RT-to-RT transfer)
010 - Receiving RT of RT-to-RT transfer did not respond
011 - A responding RT:s status word had message error, busy,
instrumentation or RESERVED bit set (*)
100 - Protocol error (improperly timed data words, decoder error,
wrong number of data words)
101 - The transfer descriptor was invalid
110 - Data buffer DMA timeout or error response
111 - Transfer aborted due to loop back check failure
* Error code 011 is issued only when the number of data words match the success case, otherwise code 100 is used. Error
code 011 can be issued for a correctly executed "transmit last command" or "transmit last status word" mode code since
these commands do not reset the status word.
Table 20.5 GR1553B BC Transfer Configuration Bits for Different Transfer Types
TRANSFER
TYPE
RTAD1
(15:11)
RTSA1
(9:5)
RTAD2
(25:21)
Data, BC-to-RT
RT address
(0-30)
RT subaddr (1-30)
Don’t care
0
Word
count (0
for 32)
0
Read
(2-64 bytes)
Data, RT-to-BC
RT address
(0-30)
RT subaddr (1-30)
Don’t care
0
Word
count (0
for 32)
1
Write
(2-64 bytes)
Data, RT-to-RT
Recv-RT
addr (0-30)
Recv-RT
subad. (130)
Xmit-RT
addr (030)
Xmit-RT
subad. (130)
Word
count (0
for 32)
0
Write
(2-64 bytes)
Mode, no data
RT address
(0-30)
0 or 31 (*)
Don’t care
Don’t care
Mode
code (0-8)
1
Unused
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(20:16)
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WCMC
(4:0)
TR
(10)
DATA BUFFER
DIRECTION
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.4: Bus Controller Operation
Table 20.5 GR1553B BC Transfer Configuration Bits for Different Transfer Types
TRANSFER
TYPE
RTAD1
(15:11)
RTSA1
(9:5)
RTAD2
(25:21)
RTSA2
(20:16)
WCMC
(4:0)
TR
(10)
DATA BUFFER
DIRECTION
Mode, RT-to-BC
RT address
(0-30)
0 or 31 (*)
Don’t care
Don’t care
Mode
code (16/
18/19)
1
Write
(2 bytes)
Mode, BC-to-RT
RT address
(0-30)
0 or 31 (*)
Don’t care
Don’t care
Mode
code (17/
20/21)
0
Read
(2 bytes)
Broadcast
Data, BC-to-RTs
31
RTs subaddr (1-30)
Don’t care
0
Word
count (0
for 32)
0
Read
(2-64 bytes)
Broadcast
Data, RT-to-RTs
31
Recv-RTs
subad. (130)
Xmit-RT
addr (030)
Xmit-RT
subad. (130)
Word
count (0
for 32)
0
Write
(2-64 bytes)
Broadcast
Mode, no data
31
0 or 31 (*)
Don’t care
Don’t care
Mode
code (1, 38)
1
Unused
Broadcast
Mode, BC-to-RT
31
0 or 31 (*)
Don’t care
Don’t care
Mode
code (17/
20/21)
0
Read
(2 bytes)
(*) The standard allows using either of subaddress 0 or 31 for mode commands.
The branch condition word is formed as shown in Table 20.6.
Offset 0x00
31 30 29 28 27
1
RESERVED
26
25
24
23
IRQC ACT MODE
16 15
RT2CC
8
RTCC
7
0
STCC
Figure 20.5 GR1553B Branch Condition Word
Table 20.6 GR1553B Branch Condition Word (Address offset 0x00)
BIT
NUMBER(S)
BIT NAME
31
94-00-00-000
Ver. 1.1.0
RESET
STATE
0
DESCRIPTION
Must be 1 to identify as branch
RESERVED - Set to 0
30-27
RESERVED
0000
26
IRQC
0
Interrupt if condition met
25
ACT
0
Action
What to do if condition is met, 0 - Suspend schedule, 1 Jump
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.5: Remote Terminal Operation
Table 20.6 GR1553B Branch Condition Word (Address offset 0x00)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
24
MODE
0
23-16
RT2CC
[000....0]
RT 2 Condition Code
Mask with bits corresponding to RT2ST in result word of
last transfer
15-8
RTCC
[000....0]
RT Condition Code
Mask with bits corresponding to RTST in result word of
last transfer
7:0
STCC
[000....0]
Status Condition
Code Mask with bits corresponding to status value of
last transfer
Logic mode:
0 = Or mode (any bit set in RT2CC, RTCC is set in
RT2ST,RTST, or result is in STCC mask)
1 - And mode (all bits set in RT2CC,RTCC are set in
RT2ST,RTST and result is in STCC mask)
NOTE: You can get a constant true condition by setting MODE=0 and STCC=0xFF, and a constant false condition by setting
STCC=0x00. 0x800000FF can thus be used as an end-of-list marker.
20.5 Remote Terminal Operation
20.5.1 Overview
When operating as Remote Terminal, the core acts as a slave on the MIL-STD-1553B bus. It listens for requests to its own RT
address (or broadcast transfers), checks whether they are configured as legal and, if legal, performs the corresponding
transfer or, if illegal, sets the message error flag in the status word. Legality is controlled by the subaddress control word for
data transfers and by the mode code control register for mode codes.
To start the RT, set up the subaddress table and log ring buffer, and then write the address and RT enable bit is into the RT
Config Register.
20.5.2 Data transfer handling
The Remote Terminal mode uses a three-level structure to handle data transfer DMA. The top level is a subaddress table,
where each subaddress has a subaddress control word, and pointers to a transmit descriptor and a receive descriptor. Each
descriptor in turn contains a descriptor control/status word, pointer to a data buffer and a pointer to a next descriptor,
forming a linked list or ring of descriptors. Data buffers can reside anywhere in memory with 16-bit alignment.
When the RT receives a data transfer request, it checks in the subaddress table that the request is legal. If it is legal, the
transfer is then performed with DMA to or from the corresponding data buffer. After a data transfer, the descriptor’s control/status word is updated with success or failure status and the subaddress table pointer is changed to point to the next
descriptor.
If logging is enabled, a log entry will be written into a log ring buffer area. A transfer-triggered IRQ may also be enabled. To
identify which transfer caused the interrupt, the RT Event Log IRQ Position points to the corresponding log entry. For that
reason, logging must be enabled in order to enable interrupts.
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Section 20.5: Remote Terminal Operation
If a request is legal, but can not be fulfilled, either because there is no valid descriptor ready or because the data can not be
accessed within the required response time, the core signals a RT table access error interrupt and not respond to the
request. Optionally, the terminal flag status bit can be automatically set on these error conditions.
Descriptor ctrl/stat
SA N-1
Transmit data
Data buffer ptr.
Next pointer
SA ctrl word
SA N
Transmit descr. ptr
Descriptor ctrl/stat
Receive descr. ptr
Data buffer ptr.
Receive buffer
Next pointer
Descriptor ctrl/stat
SA N+1
Data buffer ptr.
Next pointer
Receive buffer
0x3
Subaddress table
Figure 20.6 RT Subaddress Data Structure Example Diagram
20.5.3 Mode Codes
Which of the MIL-STD-1553B mode codes that are legal and should be logged and interrupted are controlled by the RT
Mode Code Control register. As for data transfers, to enable interrupts, you must also enable logging. Inhibit mode codes
are controlled by the same fields as their non-inhibit counterpart and mode codes that can be broadcast have two separate fields to control the broadcast and non-broadcast variants. The different mode codes and the corresponding action
taken by the RT are tabulated below. Some mode coes do not have a built-in action, so they need to be implemented in
software if desired. The relation betweem each mode code to the fields in the RT Mode Code control register is shown.
20.5.4 Event Log
The event log is a ring of 32-bit entries, each entry having the format given in Table 20.7. NOTE: For data transfers, bits 230 in the event log are identical to bits 23-0 in the descriptor status word.
Address
31
IRQSR
30 29 28
TYPE
24 23
10
SAMC
TIMEL
9
8
BC
3
SZ
2
0
TRES
Figure 20.7 GR1553B RT Event Log Entry Format
Table 20.7 Description of GR1553B RT Event Log Entry Format
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BIT
NUMBER(S)
BIT NAME
RESET
STATE
31
IRQSRC
0
DESCRIPTION
IRQ Source
Set to ‘1’ if this transfer caused an interrupt
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Section 20.5: Remote Terminal Operation
Table 20.7 Description of GR1553B RT Event Log Entry Format
BIT
NUMBER(S)
BIT NAME
RESET
STATE
30-29
TYPE
00
28-24
SAMC
0000
23-10
TIMEL
[000...0]
9
BC
0
8-3
SZ
[000....0]
2-0
TRES
000
DESCRIPTION
Transfer type
00 - Transmit data, 01 - Receive data, 10 - Mode code
Subaddress / Mode code If TYPE=00/01 this is the
transfer subaddress, If TYPE=10, this is the mode code
Low 14 bits of time tag counter.
Broadcast
Set to 1 if request was to the broadcast address
Transfer size
Count in 16-bit words (0-32)
Transfer result
000 = Success
001 = Superseded (canceled because a new command
was given on the other bus)
010 = DMA error or memory timeout occurred
011 = Protocol error (improperly timed data words or
decoder error)
100 = The busy bit or message error bit was set in the
transmitted status word and no data was sent
101 = Transfer aborted due to loop back checker error
20.5.5 Subaddress table format
Table 20.8 Description of GR1553B RT Subaddress Table Entry for Subaddress Number N, 0<N<31
Offset
Value
DMA R/W
0x10*N + 0x00
Subaddress N control word (table)
R
0x10*N + 0x04
Transmit descriptor pointer, 16-byte aligned (0x3 to indicate invalid pointer)
R/W
0x10*N + 0x08
Receive descriptor pointer, 16-byte aligned (0x3 to indicate invalid pointer)
R/W
0x10*N + 0x0C
Unused
-
NOTE: The table entries for mode code subaddresses 0 and 31 are never accessed by the core.
Offset 0x00
31
19
0 (RESERVED)
18
17
16
15
14
13
WRAP IGNDV BCRXE RXEN RXLOG RXIRQ
12
8
RXSZ
7
6
5
TXEN TXLOG TXIRQ
4
0
TXSZ
Figure 20.8 GR1553B RT Subaddress Table Control Word
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Section 20.5: Remote Terminal Operation
Table 20.9 Description of GR1553B RT Subaddress Table Control Word (Address offset 0x00)
BIT
NUMBER(S)
BIT NAME
RESET
STATE
DESCRIPTION
31-19
RESERVED
[000....0]
18
WRAP
0
Auto-wraparound enable
Enables a test mode for this subaddress, where transmit transfers
send back the last received data. This is done by copying the finished transfer’s descriptor pointer to the transmit descriptor
pointer address after each successful transfer.
NOTE: If WRAP=1, you should not set TXSZ > RXSZ as this might
cause reading beyond buffer end
17
IGNDV
0
Ignore data valid bit
If this is ‘1’ then receive transfers will proceed (and overwrite the
buffer) if the receive descriptor has the data valid bit set, instead
of not responding to the request.
This can be used for descriptor rings where you don’t care if the
oldest data is overwritten.
16
BCRXEN
0
Broadcast receive enable
Allow broadcast receive transfers to this subaddress
15
RXEN
0
Receive enable
Allow receive transfers to this subaddress
14
RXLOG
0
Log receive transfers
Log all receive transfers in event log ring (only used if RXEN=1)
13
RXIRQ
0
Interrupt on receive transfers
Each receive transfer will cause an interrupt (only if also RXEN,
RXLOG=1)
12-8
RXSZ
[000....0]
7
TXEN
0
Transmit enable
Allow transmit transfers from this subaddress
6
TXLOG
0
Log transmit transfers
Log all transmit transfers in event log ring (only if also TXEN=1)
5
TXIRQ
0
Interrupt on transmit transfers
Each transmit transfer will cause an interrupt (only if
TXEN,TXLOG=1)
4-0
TXSZ
0
Maximum legal transmit size
from this subaddress - in 16-bit words, 0 means 32
Set to 0 for forward compatibility
Maximum legal receive size
to this subaddress - in16-bit words, 0 means 32
Table 193. Description of GR1553B RT Descriptor Format
Offset
0x00
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Value
Control and status word, see Figure 20.9
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Section 20.5: Remote Terminal Operation
Table 193. Description of GR1553B RT Descriptor Format
Offset
Value
DMA R/W
0x04
Data buffer pointer, 16-bit aligned
R
0x08
Pointer to next descriptor, 16-byte aligned
or 0x0000003 to indicate end of list
R
Offset 0x00
31
30
29
26 25
10
DV IRQEN RESERVED (0)
TIME
9
BC
8
3
SZ
2
0
TRES
Figure 20.9 Descriptor control/status word
Table 20.10 Description of GR1553B RT Descriptor Control/Status Word (Address offset 0x00)
BIT
RESET
NUMBER(S)
BIT
NAME
31
DV
0
Data valid
Should be set to 0 by software before and set to 1 by hardware
after transfer.
If DV=1 in the current receive descriptor before the receive transfer begins then a descriptor table error will be triggered. You can
override this by setting the IGNDV bit in the subaddress table.
30
IRQEN
0
IRQ Enable override
Log and IRQ after transfer regardless of SA control word settings
Can be used for getting an interrupt when nearing the end of a
descriptor list.
[000....0]
RESERVED - Write 0 and mask out on read for forward compatibility
29-26
94-00-00-000
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DESCRIPTION
STATE
25-10
TTIME
[000....0]
Transmission time tag Set by the core to the value of the RT timer
when the transfer finished.
9
BC
0
Broadcast Set by the core if the transfer was a broadcast transfer
8-3
SZ
[000....0]
Transfer size Count in 16-bit words (0-32)
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Section 20.6: Bus Monitor Operation
Table 20.10 Description of GR1553B RT Descriptor Control/Status Word (Address offset 0x00)
BIT
RESET
NUMBER(S)
BIT
NAME
2-0
TRES
000
DESCRIPTION
STATE
Transfer result
000 = Success
001 = Superseded (canceled because a new command was given
on the other bus)
010 = DMA error or memory timeout occurred
011 = Protocol error (improperly timed data words or decoder
error)
100 = The busy bit or message error bit was set in the transmitted
status word and no data was sent
101 = Transfer aborted due to loop back checker error
20.6 Bus Monitor Operation
20.6.1 Overview
The Bus Monitor (BM) can be enabled by itself, or in parallel to the BC or RT. The BM acts as a passive logging device, writing received data with time stamps to a ring buffer.
Transfers can be filtered per RT address and per subaddress or mode code and the filter conditions are logically AND:ed. If
all bits of the three filter registers and bits 2-3 of the control register are set to’1’, the BM core logs all words that are
received on the bus.
In order to filter on subaddress/mode code, the BM has logic to track 1553 words belonging to the same message. All 10
message types are supported. If an unexpected word appears, the filter logic will restart. Data words not appearing to
belong to any message can be logged by setting a bit in the control register.
The filter logic can be manually restarted by setting the BM enable bit low and then back to high. This feature is mainly to
improve testability of the BM itself.
20.6.2 No-response handling
Due to the nature of the MIL-STD-1553B protocol, ambiguity can arise when the subaddress or mode code filters are used,
an RT is not responding on a subaddress and the BC then commands the same RT again on subaddress 8 or mode code
indicator 0 on the same bus. This leads to the second command word being interpreted as a status word and filtered out.
The BM uses the instrumentation bit and RESERVED bits to disambiguate, which means that this case never occurs when
subaddresses 1-7, 16-30 and mode code indicator 31 are used. Also, this case does not occur if only the RT address filter is
used.
20.6.3 Log entry format
Each log entry is two 32-bit words.
Offset 0x00
31 30
1
24 23
0
RESERVED
TIME
Figure 20.10 GR1553B BM Log Word 0
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Section 20.7: Clocking and reset
Table 20.11 Description of GR1553B BM Log Entry Word 0 (Address offset 0x00)
BIT
BIT NAME
RESET
NUMBER(S)
STATE
31
1
DESCRIPTION
Always written as 1
30-24
RESERVED
[000....0]
Mask out on read for forward compatibility
23-0
TIME
[000....0]
Time tag
Offset 0x04
31 30
0
20 19 18 17 16 15
RESERVED
BUS
0
WTP
WD
Figure 20.11 GR1553B BM Log Entry Word 1
Table 20.12 Description of GR1553B BM Log Entry Word 1 (offset 0x04)
BIT
BIT NAME
RESET
NUMBER(S)
STATE
31
0
DESCRIPTION
Always written as 0
Mask out on read for forward compatibility
30-20
RESERVED
[000....0]
19
BUS
0
Receive data bus
0:A
1:B
18-17
WST
00
Word status
00=word OK
01=Manchester error
10=Parity error
16
WTP
0
Word type
0:Data
1:Command/status
15-0
WD
[000....0]
Word data
20.7 Clocking and reset
The 1553 interface requires an external 20 MHz clock fed via the M1553_CLK input. For correct operation, it also requires
the system clock frequency to be 10MHz or higher. The system clock and M1553_CLK are not required to be synchronous.
A propagation delay of up to one codec clock cycle (50 ns) can be tolerated in each clock-domain crossing signal.
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Section 20.8: Registers
20.8 Registers
The core is programmed through registers mapped into APB address 0x80100000. RESERVED register fields should be
written as zeroes and masked out on read.
Table 20.13 MIL-STD-1553B Interface Registers
Register
R/W
APB address offset
IRQ Register
RW (write ‘1’ to clear)
0x00
IRQ Enable
RW
0x04
(RESERVED)
0x08...0x0F
Hardware config register
R (constant)
0x10
(RESERVED)
0x14...0x3F
BC Register area (see Table 190)
0x40...0x7F
RT Register area (see Table 191)
0x80...0xBF
BM Register area (see Table 192)
0xC0...0xFF
Table 20.14 MIL-STD-1553B Interface BC-Specific Registers
Register
R/W
APB address offset
BC Status and Config register
RW
0x40
BC Action register
W
0x44
BC Transfer list next pointer
RW
0x48
BC Asynchronous list next pointer
RW
0x4C
BC Timer register
R
0x50
BC Timer wake-up register
RW
0x54
BC Transfer-triggered IRQ ring position
RW
0x58
BC Per-RT bus swap register
RW
0x5C
(RESERVED)
0x60...0x67
BC Transfer list current slot pointer
R(W)**
0x68
BC Asynchronous list current slot pointer
R(W)**
0x6C
(RESERVED)
0x70...0x7F
(**) Writing has the same effect as writing the next pointer register
Table 20.15 MIL-STD-1553B Interface RT-Specific Registers
Register
94-00-00-000
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R/W
APB address offset
RT Status register
R
0x80
RT Config register
RW
0x84
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Section 20.8: Registers
Table 20.15 MIL-STD-1553B Interface RT-Specific Registers
Register
R/W
APB address offset
RT Bus status bits register
RW
0x88
RT Status words register
RW
0x8C
RT Sync register
R
0x90
RT Subaddress table base address
RW
0x94
RT Mode code control register
RW
0x98
(RESERVED)
0x9C...0xA3
RT Time tag control register
RW
0xA4
(RESERVED)
0xA8
RT Event log size mask
RW
0xAC
RT Event log position
RW
0xB0
RT Event log interrupt position
R
0xB4
(RESERVED)
0xB8.. 0xBF
(***) Reset value is affected by the external RTADDR/RTPAR input signals
Table 20.16 MIL-STD-1553B Interface BM-Specific Registers
Register
R/W
APB address offset
BM Status register
R
0xC0
BM Control register
RW
0xC4
BM RT Address filter register
RW
0xC8
BM RT Subaddress filter register
RW
0xCC
BM RT Mode code filter register
RW
0xD0
BM Log buffer start
RW
0xD4
BM Log buffer end
RW
0xD8
BM Log buffer position
RW
0xDC
BM Time tag control register
RW
0xE0
(RESERVED)
0xE4...0xFF
GR1553IR
Address = 0x80100000
31
18
RESERVED
17
16
15 14 13 12 11
BMTOF BMD
RESERVED
10
9
8
RTTE RTD RTEV
7
6
5
4
RESERVED
3
2
1
0
BC
BCD BCEV
WK
Figure 20.12 GR1553B IRQ Register
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Section 20.8: Registers
Table 20.17 Description of GR1553B IRQ Register
BIT
BIT NAME
RESET
NUMBER(S)
DESCRIPTION
STATE
31-18
RESERVED
0
17
BMTOF
0
BM Timer overflow
0: No interrupt triggered
1: Interrupt triggered
Writing a ‘1’ to this field resets value to ‘0’
16
BMD
0
BM DMA Error
0: No interrupt triggered
1: Interrupt triggered
Writing a ‘1’ to this field resets value to ‘0’
15-11
RESERVED
0
10
RTTE
0
RT Table access error
0: No interrupt triggered
1: Interrupt triggered
Writing a ‘1’ to this field resets value to ‘0’
9
RTD
0
RT DMA Error
0: No interrupt triggered
1: Interrupt triggered
Writing a ‘1’ to this field resets value to ‘0’
8
RTEV
0
RT transfer-triggered event interrupt
0: No interrupt triggered
1: Interrupt triggered
Writing a ‘1’ to this field resets value to ‘0’
2
BCWK
0
BC Wake-up timer interrupt
0: No interrupt triggered
1: Interrupt triggered
Writing a ‘1’ to this field resets value to ‘0’
1
BCD
0
BC DMA Error
0: No interrupt triggered
1: Interrupt triggered
Writing a ‘1’ to this field resets value to ‘0’
0
BCEV
0
BC Transfer-triggered event interrupt
0: No interrupt triggered
1: Interrupt triggered
Writing a ‘1’ to this field resets value to ‘0’
GR1553IER
Address = 0x80100004
31
18
RESERVED
17
16
BMTOE BMDE
15
11
RESERVED
10
9
8
RTTEE RTDE RTEVE
7
3
RESERVED
2
1
0
BCWKE BCDE BCEVE
Figure 20.13 GR1553B IRQ Enable Register
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Section 20.8: Registers
Table 20.18 Description of GR1553B IRQ Enable Register
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
31-18
RESERVED
[000...0]
17
BMTOE
0
BM Timer overflow interrupt enable
16
BMDE
0
BM DMA error interrupt enable
15-11
RESERVED
00000
10
RTTEE
0
RT Table access error interrupt enable
9
RTDE
0
RT DMA error interrupt enable
8
RTEVE
0
RT Transfer-triggered event interrupt enable
7-3
RESERVED
00000
2
BCWKE
0
BC Wake up timer interrupt
1
BCDE
0
BC DMA Error Enable
0
BCEVE
0
BC Transfer-triggered event interrupt
GR1553HCR
31
Address = 0x80100010
30
12
MOD
RESERVED
11
10
9
8
7
XKEYS ENDIAN SCLK
0
CCFREQ
Figure 20.14 GR1553B Hardware Configuration Register
Table 20.19 Description of GR1553B Hardware Configuration Register
BIT
BIT NAME
NUMBER(S)
94-00-00-000
Ver. 1.1.0
RESET
DESCRIPTION
STATE
Modified
RESERVED to indicate that the core has been modified / customized in an unspecified manner
31
(MOD)
0
30-12
RESERVED
0
11
XKEYS
00
Set if safety keys are enabled for the BM Control Register and for
all RT Control Register fields.
10-9
ENDIAN
0
AHB Endianness - 00=Big-endian, 01=Little-endian, 10/
11=RESERVED
8
(SCLK)
0
Same clock
RESERVED for future versions to indicate that the core has been
modified to run with a single clock
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Section 20.8: Registers
Table 20.19 Description of GR1553B Hardware Configuration Register
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
7-0
CCFREQ
[000...0]
GR1553BCSR
31
BCSUP
Address = 0x80100040
30 29 28 27
BCFEAT
17
RESERERVED
16
15
11 10
BCCHK
ASADL
9
0
8
7
3
ASST
2
SCADL
0
SCST
Figure 20.15 GR1553B BC Status and Config Register
Table 20.20 Description of GR1553B BC Status and Config Register
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
BC Supported - Reads ‘1’ if core supports BC mode
31
BCSUP
0
30-28
BCFEAT
000
16
BCCHK
0
15-11
ASADL
[000...0]
10
RESERVED
0
9-8
ASST
00
7-3
SCADL
00000
Schedule address low bits - Bit 8-4 of currently executing (if
SCST=001) or next schedule descriptor address
2-0
SCST
000
Schedule state - 000=Stopped, 001=Executing command,
010=Waiting for time slot, 011=Suspended, 100=Waiting for
external trigger
BC Features - Bit field describing supported optional features
(‘1’=supported):
30-BC Schedule timer supported
29-BC Schedule time wake-up interrupt supported
28-BC per-RT bus swap register and STBUS descriptor bit supported
Check broadcasts - Writable bit, if set to ‘1’ enables waiting and
checking for (unexpected) responses to all broadcasts.
Asynchronous list address low bits - Bit 8-4 of currently executing
(if ASST=01) or next asynchronous command descriptor address
Asynchronous list state 00=Stopped, 01=Executing command,
10=Waiting for time slot
GR1553BCAR
Address = 0x80100044
31
10
RESERVED
9
8
7
6
5
ASSTP ASSRT RESERVED
4
3
2
1
0
CLRT SETT SCSTP SCSUS SCSRT
Figure 20.16 GR1553B BC Action Register
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Section 20.8: Registers
Table 20.21 Description of GR1553B BC Action Register
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
31-10
RESERVED
0
9
ASSTP
0
Asynchronous list stop
Write ‘1’ to stop asynchronous list (after current transfer, if executing)
8
ASSRT
0
Asynchronous list start
Write ‘1’ to start asynchronous list
4
CLRT
0
Clear external trigger
Write ‘1’ to clear trigger memory
3
SETT
0
Set external trigger
Write ‘1’ to force the trigger memory to set
2
SCSTP
0
Schedule stop
Write ‘1’ to stop schedule (after current transfer, if executing)
1
SCSUS
0
Schedule suspend
Write ‘1’ to suspend schedule (after current transfer, if executing)
0
SCSRT
0
Schedule start
Write ‘1’ to start schedule
GR1553BCTP
Address = 0x80100048
31
0
STLP
Figure 20.17 GR1553B BC Transfer List Next Pointer Register
Table 20.22 Description of GR1553B BC Transfer List Next Pointer Register
BIT
RESET
NUMBER(S)
BIT
NAME
31-0
STLP
[000...0]
DESCRIPTION
STATE
SCHEDULE TRANSFER LIST POINTER
Read: Currently executing (if SCST=001) or next transfer to be
executed in regular schedule.
Write: Change address. If running, this will cause a jump after the
current transfer has finished.
GR1553BCAP
Address = 0x8010004C
31
0
Figure 20.18 GR1553B BC Asynchronous List Next Pointer Register
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Section 20.8: Registers
ALP
Figure 20.18 GR1553B BC Asynchronous List Next Pointer Register
Table 20.23 Description of GR1553B BC Asynchronous List Next Pointer Register
BIT
RESET
NUMBER(S)
BIT
NAME
31-0
ALP
[000...0]
DESCRIPTION
STATE
AS YNCHRONOUS LIST POINTER
Read: Currently executing (if ASST=01) or next transfer to be executed in asynchronous schedule.
Write: Change address. If running, this causes a jump after the
current transfer has finished.
GR1553BCTR
Address = 0x80100050
31
24 23
0
RESERVED
SCHEDULE TIME (SCTM)
Figure 20.19 GR1553B BC Timer Register
Table 20.24 Description of GR1553B BC Timer Register
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
31-24
RESERVED
[000...0]
23-0
RESERVED
[000...0]
Elapsed “transfer list” time in microseconds (read-only)
Set to zero when schedule is stopped or on external sync.
NOTE: This register is an optional feature, see BC Status and Config Register, bit 30
GR1553BCTW
31
WKEN
Address = 0x80100054
30
24 23
0
RESERVED
WAKE-UP TIME (WKTM)
Figure 20.20 GR1553B BC Timer Register
94-00-00-000
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Table 20.25 Description of GR1553B BC Timer Wake-up Register
BIT
BIT NAME
RESET
NUMBER(S)
DESCRIPTION
STATE
31
WKEN
0
Wake-up timer enable
If set, an interrupt will be triggered when
WKTM=SCTM
30-24
RESERVED
[000...0]
23-0
WKTM
[000...0]
Wake-up time
GR1553BCTI
Address = 0x80100058
31
0
BCIRQ SOURCE POINTER RING POSITION (BISPRP)
Figure 20.21 GR1553B BC Transfer-triggered IRQ Ring Position Register
Table 20.26 Description of GR1553B BC Transfer-triggered IRQ Ring Position Register
BIT
RESET
NUMBER(S)
BIT
NAME
31-0
BISPRP
[000...0]
DESCRIPTION
STATE
BC IRQ SOURCE POINTER RING POSITION
The current write pointer into the transfer-triggered IRQ descriptor pointer ring.
Bits 1:0 are constant zero (4-byte aligned)
The ring wraps at the 64-byte boundary, so bits 31:6 are only
changed by user
GR1553BCRS
Address = 0x8010005C
31
0
BC PER-RT BUS SWAP (BRPS)
Figure 20.22 GR1553B BC per-RT Bus Swap Register
Table 20.27 Description of GR1553B BC per-RT Bus Swap Register
BIT
94-00-00-000
Ver. 1.1.0
RESET
NUMBER(S)
BIT
NAME
31-0
BRBS
[000...0]
DESCRIPTION
STATE
The bus selection value will be logically exclusive-or:ed with the
bit in this mask corresponding to the addressed RT (the receiving
RT for RT-to-RT transfers). This register gets updated by the core if
the STBUS descriptor bit is used.
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
GR1553BCTL
Address = 0x80100068
31
0
BC TRNSFER SLOT POINTER (BTSP)
Figure 20.23 GR1553B BC Transfer List Current Slot Pointer
Table 20.28 Description of GR1553B BC Transfer List Current Slot Pointer
BIT
BIT NAME
NUMBER(S)
31-0
RESET
DESCRIPTION
STATE
BTSP
[000...0]
Points to the transfer descriptor corresponding to the current
time slot (read-only, only valid while transfer list is running).
Bits 3:0 are constant zero (128-bit/16-byte aligned)
GR1553BCAL
Address = 0x8010006C
31
0
BC ASYNCHRONOUS LIST POINTER (BCAP)
Figure 20.24 GR1553B BC Asynchronous List Current Slot Pointer
Table 20.29 Description of GR1553B BC Asynchronous List Current Slot Pointer
BIT
BIT NAME
RESET
NUMBER(S)
31-0
DESCRIPTION
STATE
BCAP
[000...0]
Read: Currently executing (if ASST=01) or next transfer to be
executed in asynchronous schedule.
Write: Change address. If running, this causes a jump after the
current transfer has finished.
GR1553RTS
31
Address = 0x80100080
30
4
RTSUP
RESERVED
3
2
1
0
ACT SHDA SHDB RUN
Figure 20.25 GR1553B RT Status Register (read-only)
Table 20.30 Description of GR1553B RT Status Register (read-only)
BIT
BIT NAME
NUMBER(S)
31
94-00-00-000
Ver. 1.1.0
RESET
DESCRIPTION
STATE
RTSUP
1
RT Supported
Reads ‘1’ if core supports RT mode
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Table 20.30 Description of GR1553B RT Status Register (read-only)
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
30-4
RESERVED
[000...0]
3
ACT
0
RT Active
‘1’ if RT is currently processing a transfer
2
SHDA
0
Bus A shutdown
Reads ‘1’ if bus A has been shut down by the BC (using the transmitter shutdown mode command on bus B)
1
SHDB
0
Bus B shutdown
Reads ‘1’ if bus B has been shut down by the BC (using the transmitter shutdown mode command on bus A)
0
RUN
0
RT Running
‘1’ if the RT is listening to commands.
GR1553RTC
Address = 0x80100084
31
16 15
RTKEY
7
RESERVED
6
RTEIS
5
1
RTADDR
0
RTEN
Figure 20.26 GR1553B RT Config Register
Table 20.31 Description of GR1553B RT Configuration Register
BIT
BIT NAME
NUMBER(S)
94-00-00-000
Ver. 1.1.0
RESET
DESCRIPTION
STATE
31-16
RTKEY
[000....0]
15-7
RESERVED
[000...0]
6
RTEIS
0
5-1
RTADDR
11110
0
RTEN
0
Safety code
Must be written as 0x1553 when changing the RT address, otherwise the address field is unaffected by the write. When reading
the register, this field reads 0x0000.
If extra safety keys are enabled (see Hardware Config Register),
the lower half of the key is used to also protect the other fields in
this register.
Reads ‘1’ if current address was set through external inputs.
After setting the address from software this field is set to ‘0’
RT Address
This RT:s address (0-30)
RT Enable
Set to ‘1’ to enable listening for requests
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
GR1553RTBS
Address = 0x80100088
31
9
RESERVED
8
7
5
4
3
2
1
0
TFDE RESERVED SREQBUSY SSF DBCA TFLG
Figure 20.27 GR1553B RT Bus Status Register
Table 20.32 Description of GR1553B RT Bus Status Register
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
8
TFDE
0
Set Terminal flag automatically on DMA and descriptor table
errors
7-5
RESERVED
[000]
4
SREQ
0
Service request
Sent in the RT:s status responses over the 1553 bus
3
BUSY
0
Busy bit
NOTE: If the busy bit is set, the RT will respond with only the status word and the transfer “fails”
Sent in the RT:s status responses over the 1553 bus
2
SSF
0
Subsystem Flag
Sent in the RT:s status responses over the 1553 bus
1
DBCA
0
Dynamic Bus Control Acceptance
NOTE: This bit is only sent in response to the Dynamic Bus Control mode code
Sent in the RT:s status responses over the 1553 bus
0
TFLG
0
Terminal Flag
The BC can mask this flag using the “inhibit terminal flag” mode
command, if legal
Sent in the RT:s status responses over the 1553 bus
GR1553RTSW
Address = 0x8010008C
31
16 15
BIT WORD (BITW)
0
VECTOR WORD (VECW)
Figure 20.28 GR1553B RT Status Words Register
94-00-00-000
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Table 20.33 Description of GR1553B RT Status Words Register
BIT
RESET
NUMBER(S)
BIT
NAME
DESCRIPTION
31-16
BITW
[000...0]
BIT Word
Transmitted in response to the “Transmit BIT Word” mode command, if legal
15-0
VECW
[000...0]
Vector word
Transmitted in response to the “Transmit vector word” mode
command, if legal.
STATE
GR1553RTSY
Address = 0x80100090
31
16 15
0
SYNC TIME (SYTM)
SYNC DATA (SYD)
Figure 20.29 GR1553B RT Sync Register
Table 20.34 Description of GR1553B RT Sync Register
BIT
RESET
NUMBER(S)
BIT
NAME
DESCRIPTION
31-16
SYTM
[000...0]
The value of the RT timer at the last sync or sync with
data word mode command, if legal.
15-0
SYD
[000...0]
The data received with the last synchronize with data
word mode command, if legal.
STATE
GR1553RTST
Address = 0x80100094
31
9
8
6
SUBADDRESS TABLE BASE (SATB)
5
4
3
2
1
0
RESERVED
Figure 20.30 GR1553B BC Transfer List Current Slot Pointer
Table 20.35 Description of GR1553B RT Subaddress Table Base Address Register
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
31-9
SATB
[000...0]
8-0
Reserved
[000...0]
Base address, bits 31-9 for subaddress table
GR1553RTEL
Address = 0x801000B4
31
0
EVENT LOG IRQ POINTER (ELIP)
Figure 20.31 GR1553B RT Event Log Interrupt Position Register
94-00-00-000
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Table 20.36 Description of GR1553B RT Event Log Interrupt Position Register
BIT
RESET
NUMBER(S)
BIT
NAME
31-0
ELIP
[000...0]
DESCRIPTION
STATE
Address to event log entry corresponding to interrupt, 32-bit
aligned
The register is set for the first interrupt and not set again until
the interrupt has been acknowledged.
GR1553RTMC
31
30
RESERVED
15
14
TBW
Address = 0x80100098
29
28
27
RRTB
13
12
TVW
26
25
RRT
11
24
23
22
ITFB
10
TSB
9
ITF
8
TS
21
7
20
19
ISTB
6
5
17
IST
4
SDB
18
3
SD
16
DBC
2
SB
1
0
S
Figure 20.32 GR1553B RT Mode Code Control Register
Table 20.37 Description of GR1553B RT Mode Code Control Register
BIT
BIT NAME
NUMBER(S)
94-00-00-000
Ver. 1.1.0
RESET
DESCRIPTION
STATE
31-30
RESERVED
00
29-28
RRTB
00
Reset remote terminal broadcast
27-26
RRT
00
Reset remote terminal
25-24
ITFB
00
Inhibit & override inhibit terminal flag bit broadcast
23-22
ITF
00
Inhibit & override inhibit terminal flag
21-20
ISTB
00
Initiate self test broadcast
19-18
IST
00
Initiate self test
17-16
DBC
00
Dynamic bus control
15-14
TBW
00
Transmit BIT word
13-12
TVW
00
Transmit vector word
11-10
TSB
01
Transmitter shutdown & override transmitter shutdown broadcast
9-8
TS
01
Transmitter shutdown & override transmitter shutdown
7-6
SDB
01
Synchronize with data word broadcast
6-4
SD
01
Synchronize with data word
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Table 20.37 Description of GR1553B RT Mode Code Control Register
BIT
BIT NAME
RESET
NUMBER(S)
DESCRIPTION
STATE
3-2
SB
01
Synchronize broadcast (SB)
1-0
S
01
Synchronize (S)
For each mode code: “00” - Illegal, “01” - Legal, “10” - Legal, log enabled, “11” - Legal, log and interrupt
GR1553RTTT
Address = 0x801000A4
31
16 15
0
TIME RESOLUTION (TRES)
TIME TAG VALUE (TVAL)
Figure 20.33 GR1553B RT Time tag Control Register
Table 20.38 Description of GR1553B RT Time Tag Control Register
BIT
RESET
NUMBER(S)
BIT
NAME
DESCRIPTION
31-16
TRES
[000...0]
Time tag resolution
Time unit of RT:s time tag counter in microseconds,
minus 1
15-0
TVAL
[000...0]
Time tag value
Current value of running time tag counter
STATE
GR1553RTLS
Address = 0x801000AC
31
21 20
2
RESERVER
EVENT LOG SIZE MASK (ELSM)
1
0
RES
Figure 20.34 GR1553B RT Event Log Size Mask Register
Table 20.39 Description of GR1553B RT Event Log Size Mask Register
BIT
BIT NAME
NUMBER(S)
94-00-00-000
Ver. 1.1.0
RESET
DESCRIPTION
STATE
31-21
Reserved
00
20-2
ELSNM
ox7FFFF
1-0
Reserved
00
Always reads “0”
Mask determining size and alignment of the RT event log ring
buffer. All bits “above” the size should be set to ‘1’, all bits below
should be set to ‘0’.
Always reads ‘0’
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
GR1553RTELP
Address = 0x801000B0
31
0
EVENT LOG WRITE POINTER (ELWP)
Figure 20.35 Description of GR1553B RT Event Log Position Register
Table 20.40 Description of GR1553B RT Event Log Position Register
BIT
RESET
NUMBER(S)
BIT
NAME
31-0
ELWP
[000...0]
DESCRIPTION
STATE
Address to first un used/oldest entry of event
log buffer, 32-bit aligned.
GR1553BMS
31
30
BMSUP
KEYEN
Address
29
0
Figure 20.36 GR1553B BM Status Register
Table 20.41 Description of GR1553B BM Status Register
BIT
RESET
NUMBER(S)
BIT
NAME
DESCRIPTION
31
BMSUP
1
BM Supported
Reads ‘1’ if BM support is in the core.
30
KEYEN
0
Key Enabled
Reads ‘1’ if the BM validates the BMKEY field
when the control register is written.
29-0
RESERVE
D
[000...0]
STATE
GR1553BMC
Address = 0x801000C4
31
6
RESERVED
5
4
3
2
1
0
WRSTP EXST IMCL UDWL MANL BMEN
Figure 20.37 GR1553B BM Control Register
94-00-00-000
Ver. 1.1.0
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Table 20.42 Description of GR1553B BM Control Register
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
31-6
RESERVED
[000...0]
5
WRSTP
0
Wrap stop
If set to ‘1’, BMEN will be set to ‘0’ and stop the BM when the
BM log position wraps around from buffer end to buffer start
4
EXST
0
External sync start
If set to ‘1’,BMEN will be set to ‘1’ and the BM is started when
an external BC sync pulse is received
3
IMCL
0
Invalid mode code log
Set to ‘1’ to log invalid or RESERVED mode codes.
2
UDWL
0
Unexpected data word logging
Set to ‘1’ to log data words not seeming to be part of any
command
1
MANL
0
Manchester/parity error logging
Set to ‘1’ to log bit decoding errors
0
BMEN
0
BM Enable
Must be set to ‘1’ to enable any BM logging
GR1553BMAF
31
Address = 0x801000C8
30
1
LBTE
0
ADDRESS FILTER MASK (AFM)
Figure 20.38 GR1553B BM RT Address Filter Register
Table 20.43 Description of GR1553B BM RT Address Filter Register
BIT
RESET
NUMBER(S)
BIT
NAME
31
LBTE
1
30-0
AFM
0X7FFFFFFF
DESCRIPTION
STATE
Enables logging of broadcast transfers
Each bit position set to ‘1’ enables logging of transfers
with the corresponding RT address.
GR1553BMSF
31
LMCE31
Address = 0x801000CC
30
1
SUBADDRESS FILTER MASK (SFM)
0
LMCE0
Figure 20.39 GR1553B BM RT Subaddress Filter Register
94-00-00-000
Ver. 1.1.0
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Table 20.44 Description of GR1553B BM RT Subaddress Filter Register
BIT
RESET
NUMBER(S)
BIT
NAME
DESCRIPTION
31
LMCE31
1
30-1
SFM
0X3FFFFFFF
0
LMCE0
1
STATE
Enables logging of mode commands on subaddress 31
Each bit position set to ‘1’ enables logging of transfers with the
corresponding RT subaddress.
Enables logging of mode commands on subaddress 0
GR1553BMMC
Address = 0x801000D0
31
19
RESERVED
18
17
16
STSB
STS
TLC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TSW
RRTB
RRT
ITFB
ITF
ISTB
IST
DBC
TBW
TVW
TSB
TS
SDB
SD
SB
S
Figure 20.40 GR1553B BM RT Mode Code Filter Register
Table 20.45 Description of GR1553B BM RT Mode Code Filter Register
BIT
BIT NAME
NUMBER(S)
94-00-00-000
Ver. 1.1.0
RESET
DESCRIPTION
STATE
31-19
RESERVED
[111...1]
18
STSB
1
Selected transmitter shutdown broadcast & override selected
transmitter shutdown broadcast
17
STS
1
Selected transmitter shutdown & override selected transmitter
shutdown
16
TLC
1
Transmit last command
15
TSW
1
Transmit status word
14
RRTB
1
Reset remote terminal broadcast
13
RRT
1
Reset remote terminal
12
ITFB
1
Inhibit & override inhibit terminal flag bit broadcast
11
ITF
1
Inhibit & override inhibit terminal flag
10
ISTB
1
Initiate self test broadcast
9
IST
1
Initiate self test
8
DBC
1
Dynamic bus control
7
TBW
1
Transmit BIT word
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Table 20.45 Description of GR1553B BM RT Mode Code Filter Register
BIT
BIT NAME
NUMBER(S)
RESET
DESCRIPTION
STATE
6
TVW
1
Transmit vector word
5
TSB
1
Transmitter shutdown & override transmitter shutdown broadcast
4
TS
1
Transmitter shutdown & override transmitter shutdown
3
SDB
1
Synchronize with data word broadcast
2
SD
1
Synchronize with data word
1
SB
1
Synchronize broadcast
0
S
1
Synchronize
NOTE: Each bit set to ‘1’ enables logging of a mode code:
GR1553BMLB
Address = 0x801000D4
31
0
BM LOG BUFFER START (BLBS)
Figure 20.41 GR1553B BM Log Buffer Start
Table 20.46 Description of GR1553B BM Log Buffer Start
BIT
RESET
NUMBER(S)
BIT
NAME
31-0
BLBS
[000...0]
DESCRIPTION
STATE
Pointer to the lowest address of the BM log buffer
(8-byte aligned)
Due to alignment, bits 2:0 are always 0.
GR1553BMLE
Address = 0x801000D8
31
0
BM LOG BUFFER END (BLBE)
Figure 20.42 GR1553B BM Log Buffer End
94-00-00-000
Ver. 1.1.0
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Table 20.47 Description of GR1553B BM Log Buffer End
BIT
RESET
NUMBER(S)
BIT
NAME
DESCRIPTION
31-0
BLBE
0x00000007
STATE
Pointer to the highest address of the BM log buffer
Only bits 21:3 are settable, i.e. the buffer can not cross a 4 MB
boundary Bits 31:22 read the same as the buffer start
address.Due to alignment, bits 2:0 are always equal to 1.
Address = 0x801000E0
GR1553BMTT
31
24 23
0
TIME TAG RESOLUTION
TIME TAG VALUE (TTV
Figure 20.43 GR1553B BM Time Tag Control Register
Table 20.48 Description of GR1553B BM Time Tag Control Register
BIT
RESET
NUMBER(S)
BIT
NAME
DESCRIPTION
31-24
TTR
[000...0]
Time tag resolution
Time unit of BM:s time tag counter in microseconds, minus 1
23-0
TTV
[000...0]
Time tag value
Current value of running time tag counter
STATE
GR1553BMLBP
Address = 0x801000DC
31
0
BM LOG BUFFER POSITION (BLP)
Figure 20.44 GR1553B BM Log Buffer Position
Table 20.49 Description of GR1553B BM Log Buffer Position
BIT
94-00-00-000
Ver. 1.1.0
RESET
NUMBER(S)
BIT
NAME
31-0
BLP
[000...0]
DESCRIPTION
STATE
Pointer to the next position that will be written to in the BM log
buffer
Only bits 21:3 are settable, i.e. the buffer can not cross a 4 MB
boundary Bits 31:22 read the same as the buffer start
address.Due to alignment, bits 2:0 are always equal to 0.
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Chapter 20: Dual Redundant MIL-STD-1553B Interface (GR1553B)
Section 20.8: Registers
Revision History
Version
Release Date
1.0.0
November 2014
1.1.0
April 2015
94-00-00-000
Ver. 1.1.0
Description
Initial Release
Added Appendix A: Errata to the manual
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Section : UT700 MIL-STD-1553 NOISE REJECTION LIMITATIONS
Appendix A: Errata
UT700 MIL-STD-1553 NOISE REJECTION LIMITATIONS
Table 21.1 Cross Reference of Applicable Products
Product Name:
Manufacturer
Part Number
SMD #
Device Type
Internal PIC
Number
UT700 LEON 3FT
Microprocessor
UT700
5962-13238
All
WQ03
Overview/Problem Statement
MIL-STD-1553 paragraph 5.3 requires a terminal to pass a noise rejection test to ensure correct interoperability while
exposed to a noisy environment. The noise rejection test requires injecting a band limited, 1.0K to 4MHz, White Gaussian
noise at 140 mVrms (transformer coupled) or 200 mVrms (direct coupled) on the bus and transmitting a minimum of
40,000,000 data words without any message errors. This erratum explains why meeting the noise rejection test is a challenge for the GR1553 core contained in the UT700.
Technical Background
The GR1553 is a MIL-STD-1553 compliant protocol controller for the UT700. The GR1553 has the ability to operate as a
Remote Terminal, Bus Controller, and Bus Monitor. Certification of a MIL-STD-1553 device typically involves testing the
Remote Terminal operations. The GR1553 protocol controller is configured to operate as a Re-mote Terminal during the
certification testing. The noise rejection test results are a function of the protocol controller as well as the transceiver and
transformer. It is typical of most transceivers to pass a narrow pulse as a result of noise on the bus. Protocol controllers
designed to filter the narrow pulses are unaffected. Since each protocol controller is designed to evaluate the width and
proximity of random pulses differently, sensitivity to noise induced pulses will differ between manufactures.
Specific Description of the Problem
The MIL-STD-1553 interface used for the UT700 has a potential to fail the noise rejection test requirements specified in
MIL-STD-1553 due to two built in features of the GR1553 interface. The GR1553 has the ability to monitor for invalid sync or
parity bits. An invalid sync bit or erroneous glitch occurring within 3 μs of a valid message will cause the message to be
rejected. An invalid parity bit will also cause the message to be rejected. Rejecting a message with invalid symbols is desirable with additional checks to ensure subsequent symbols are not valid. However, the decoder circuit used for the GR1553
interface monitors for pulses greater than 150ns wide and potentially will evaluate the pulse as erroneous or invalid and
prevent processing of messages received within 3 μs of this pulse. The 3 μs window permits time for controller to reset to
an operational state. Also, there are times when the decoder may interpret the last received parity bit as too wide or too
narrow, which would inhibit a response.
Implications
Impact on the system/user when encountered:
• Remote Terminal validation testing of the UT700 determined that the product passes the MIL-STD-1553 noise
induced word error rate of 1E-7 at a noise amplitude of 100 mVrms. At noise levels >100 mVrms, the associate error
rate increased in accordance with the plot shown in figure 21.1
• MIL-STD-1553 testing has a correlation between the message rate and the word rate, since each transfer consists of a
command word and 32 data words. Because the UT700 error rate is strongly correlated to the idle time just before
the command word's sync pulse and right after the final data word's parity bit, the error rate is a function of the
message rate. Assuming a maximum word error rate of 1E-7 that requires a minimum of 303.03 k messages, the
94-00-00-000
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Section : Workarounds
maximum message error rate would be 3.3E-6. Therefore, the retry rate is expected to in-crease proportionally to
the noise level as see in the following figure:
Figure 21.1 UT700 MIL-STD-1553 Message Error Rate vs Noise Amplitude
Workarounds
Best practice for PCB layout of transceiver and transformers
Designing the PCB with the least amount of skew between receiver input lines on the bus side will help minimize susceptibility to the noise, particularly at zero crossing. Part of the noise protection in a terminal relies on the filtering capabilities
of the transformers, using high quality transformers will lower the susceptibility to system noise. Additionally, ensuring
there are no signal, ground, or power plains beneath the transformers optimizes the transformer filtering capability.
Provide an appropriate budget for noise induced retries
Planning for a reduction in performance by allowing system retries for any message where the RT did not provide a
response ensures the system meets the mission requirements.
Reduce the noise exposure to the system
Enhancing the power filtering, cable shielding, and environmental shielding can reduce the likelihood that noise will affect
the system.
Summary/Conclusion and Possible Corrective Action
The protocol controller used in the UT700 may prevent passing the noise rejection test as prescribed by MIL-STD-1553.
However, typical space vehicles don’t experience the level of noise specified in MIL-STD-1553, paragraph 5.3. The expected
performance reduction in data rate can be compensated by proper planning of bus traffic and system bandwidth. Additionally, enhanced shielding and best practices applied to the PCB and operating environment will reduce the susceptibility a system to noise.
94-00-00-000
Ver. 1.1.0
- 233 -
Aeroflex Microelectronic Solutions - HiRel
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A license from the Department of Commerce may be required prior to the export of this product from the United
States.
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1
January 2016
DATA SHEET REVISION HISTORY
Revision
Date
1.0.0
11/14
Initial Release
1.1.0
4/15
Added Appendix A: Errata to manual
1.1.0
1/16
Edited Table 2.5 interrupt_level_3. Edited Table 3.4 bit number 17-14, edited Table 14.9 bit 19, 55, 163
number 7
36-00-04-010
Version 0.4.0
Description of Change
Page(s)
REV
Author
Simms
256-257
-1-
Simms
Stratton
Cobham Semiconductor Solutions
Aeroflex.com/Logic