GR712RC Dual-Core LEON3-FT SPARC V8 Processor 2016 Data Sheet The most important thing we build is trust Features • Dual-core SPARC V8 integer unit, each with 7stage pipeline, 8 register windows, 4x4 KiB multiway instruction cache, 4x4 KiB multi-way data cache, branch prediction, hardware multiplier and divider, power-down mode, hardware watchpoints, single-vector trapping, SPARC reference memory management unit, etc. • Two high-performance double precision IEEE754 floating point units • EDAC protected (8-bit BCH and 16-bit Reed-Solomon) interface to multiple 8/32-bits • PROM/SRAM/SDRAM memory banks • Advanced on-chip debug support unit • 192 KiB EDAC protected on-chip memory • Multiple SpaceWire links with RMAP target • Redundant 1553 BC/RT/MT interfaces • Redundant CAN 2.0 interfaces • 10/100 Ethernet MAC with RMII interface • SPI, I2C, ASCS16 (STR), SLINK interfaces • CCSDS/ECSS Telemetry and Telecommand • UARTs, Timers & Watchdog, GPIO ports, • Interrupt controllers, Status registers, JTAG, etc. • Configurable I/O switch matrix Description The GR712RC is an implementation of the dual-core LEON3FT SPARC V8 processor using RadSafe technology. The fault tolerant design of the processor in combination with the radiation tolerant technology provides total immunity to radiation effects. Specification • CQFP240 package • Total Ionizing Dose (TID) up to 300 krad(Si) • Proven Single-Event Latch-Up (SEL) immunity • Proven Single-Event Upset (SEU) tolerance • 1.8V & 3.3V supply • 15 mW/MHz processor core power consumption • 100 MHz system frequency • 200 Mbps SpaceWire links • 10 Mbps CCSDS Telecommand link • 50 Mbps CCSDS Telemetry link Applications GR712RC is an advanced system-on-chip, targeting high reliability radhard space, aeronautics and military applications. It incorporates a dual-core LEON3-FT SPARC V8 processor and is implemented with Ramon Chips’ RadSafe library on TowerJazz’ 180 nm CMOS technology. GR712RC-DS, Jan 2016, Version 2.3 www.cobham.com/gaisler GR712RC Table of contents 1 Introduction.............................................................................................................................. 3 1.1 1.2 1.3 1.4 1.5 2 Electrical characteristics ........................................................................................................ 17 2.1 2.2 2.3 2.4 3 Overview ................................................................................................................................................. 3 Key features............................................................................................................................................. 3 Signal overview ....................................................................................................................................... 5 Signal description .................................................................................................................................... 6 I/O switch matrix overview ..................................................................................................................... 7 Absolute maximum ratings ................................................................................................................... 17 Recommended operating conditions ..................................................................................................... 17 DC electrical performance characteristics............................................................................................. 18 AC electrical performance characteristics............................................................................................. 20 Mechanical description .......................................................................................................... 35 3.1 3.2 3.3 Package.................................................................................................................................................. 35 Pin assignment....................................................................................................................................... 35 Mechanical package drawings............................................................................................................... 41 4 Reference documents ............................................................................................................. 43 5 Screening, qualification, and quality control ......................................................................... 44 6 Ordering information ............................................................................................................. 44 7 Change record ........................................................................................................................ 44 GR712RC-DS, Jan 2016, Version 2.3 2 www.cobham.com/gaisler GR712RC 1 Introduction 1.1 Overview GR712RC is a dual-core LEON3-FT SPARC V8 processor, with advanced interface protocols, dedicated for high reliability Rad-Hard aerospace applications. The GR712RC is fabricated at Tower Semiconductors Ltd., using standard 180 nm CMOS technology. It employs radiation-hard-by-design methods from Cobham Gaisler and the RadSafeTM technology from Ramon Chips Ltd., enabling superior radiation hardness together with excellent low-power performance. The LEON3-FT processors provide hardware support for cache coherency, processor enumeration and interrupt steering. Each processor core includes a SPARC Reference Memory Management Unit (SRMMU) and an IEEE-754 compliant double-precision FPU for floating-point operations. It can be utilized in symmetric or asymmetric multiprocessing mode. The GR712RC architecture is centered around the AMBA Advanced High-speed Bus (AHB), to which the two LEON3-FT processors and other high-bandwidth units are connected. Low-bandwidth units are connected to the AMBA Advanced Peripheral Bus (APB) which is accessed through an AHB to APB bridge. GR712RC is provided in a 240-pin, 0.5 mm pitch high-reliability ceramic quad flat package (CQFP). This document is complemented by the GR712RC Dual-Core LEON3-FT SPARC V8 Processor User's Manual from Cobham Gaisler [UM], which provides information related to software integration and development. 1.2 Key features • Technology: 180 nm standard CMOS, Tower Semiconductors Ltd. • Library: 180 nm RadSafe™, Ramon Chips Ltd. • Package: • 240 pin CQFP, 0.5 mm pitch, 32 mm ×x 32 mm, hermetically sealed, delivered with flat pins and insulating lead-frame for customer trim and form • Core voltage 1.8V +/- 0.15V, I/O voltage 3.3V +/- 0.3V • -55ºC to +125ºC temperature range • Radiation tolerance: • TID: up to 300 krad(Si) • SEL: > 118 MeV-cm2/mg • SEU: proven tolerance with hardened flip-flops and error correction on all on-chip memories • Error detection and correction on external memories • Maximum system clock frequency of 100 MHz (depending on external memory choice) • Optional 2x internal system frequency multiplication by an all-digital DLL • Optional 2x or 4x internal SpaceWire frequency multiplication by an all-digital DLL • Clock-gating for each major core • Two LEON3-FT SPARC V8 compliant 32-bit processors, each with: • SPARC reference memory management unit (SRMMU) with 32 TLB entries • High-performance double-precision IEEE-754 floating point co-processor (GRFPU) GR712RC-DS, Jan 2016, Version 2.3 3 www.cobham.com/gaisler GR712RC • 16 KiB multi-way instruction cache and 16 KiB multi-way data cache • Internal on-chip high speed AMBA (AHB) bus • Instruction trace and AMBA (AHB) trace buffers for debugging • Timer unit with four 32-bit timers including watchdog • Secondary timer unit with four 32-bit timers • Primary and secondary interrupt controller for 31 interrupts • On-chip 192 KiB memory block with EDAC • External memory support: • up to 32 MiB PROM over two 16 MiB banks • up to 32 MiB SRAM over two 16 MiB banks • up to 1 GiB SDRAM over two 512 MiB banks • Bus width: 8 bits, or 32 bit data plus 8/16 bits for EDAC checkbits, 24 bit address • 8 bit BCH EDAC for SRAM and PROM, 16 bit Reed-Solomon EDAC for SDRAM • Memory types: SRAM, SDRAM, PROM / EEPROM / NOR-FLASH and I/O address space • Programmable wait-states: • SRAM read/write cycle 2 - 5 clock cycles • PROM / EEPROM / NOR-FLASH read cycle 2 - 32 clock periods • One idle clock period between accesses to SRAM and PROM • Debug Support Unit (DSU) accessed via JTAG and SpaceWire RMAP targets • Two SpaceWire ports with RMAP targets, maximum 200 Mbps full-duplex data rate • Configurable I/O selection matrix, connecting a subset of available I/O units to 67 shared pins: • Four SpaceWire ports, maximum 200 Mbps full-duplex data rate • Redundant MIL-STD-1553B BRM (BC/RT/BM) interface • Two CAN 2.0B bus controllers • Six UART ports, with 8-byte FIFO • Ethernet MAC with RMII 10/100 Mbps port • SPI master serial port • I2C master serial port • ASCS16 (STR) serial port • SLINK 6 MHz serial port • CCSDS / ECSS Telecommand decoder (five input channels), maximum 10 Mbps input rate • CCSDS / ECSS Telemetry encoder, maximum 50 Mbps output rate • 26 input and 38 input/output general purpose ports GR712RC-DS, Jan 2016, Version 2.3 4 www.cobham.com/gaisler GR712RC 1.3 Signal overview INCLK RESETN DLLBPN Clock & Reset Error & Watchdog TESTEN SCANEN Test TCK TMS TDI DATA[31:0] CB[7:0] BRDYN BEXCN SPWCLK SPW_RXD[1:0] SPW_RXS[1:0] JTAG Memory interface SpaceWire Links I/O Matrix ERRORN WDOGN TDO ADDRESS[23:0] RAMSN[1:0] RAMOEN RAMWEN ROMSN[1:0] IOSN OEN READ WRITEN SDCLK SPW_TXD[1:0] SPW_TXS[1:0] SWMX[66:0] Figure 1. Signal overview GR712RC-DS, Jan 2016, Version 2.3 5 www.cobham.com/gaisler GR712RC 1.4 Signal description The external signals are described in table 1. Table 1. External signals Name Usage Direction Polarity INCLK Main system clock In - DLLBPN DLL bypass In Low RESETN System reset In Low SCANEN Scan enable (tie to ground) In High TESTEN Test enable (tie to ground) In High ERRORN Processor error mode Out-Tri Low WDOGN Watchdog output Out-Tri Low TCK JTAG Test Clock In - TMS JTAG Test Mode In High TDI JTAG Test Data Input In - TDO JTAG Test Data Output Out - ADDRESS[23:0] Memory address Out - DATA[31:0] Memory data bus In/Out - CB[7:0] Memory checkbits In/Out - RAMSN[1:0] SRAM chip selects Out Low RAMOEN SRAM output enable Out Low RAMWEN SRAM write enable strobe Out Low OEN PROM, I/O output enable Out Low WRITEN PROM, I/O write strobe Out Low Out High READ SRAM, PROM I/O read indicator 1) IOSN I/O area chip select Out Low ROMSN[1:0] PROM chip selects Out Low BRDYN Bus ready In Low BEXCN Bus exception In Low SDCLK SDRAM clock Out - SPWCLK SpaceWire receiver and transmitter clock In - SPW_RXD[1:0] SpaceWire Data input In High SPW_RXS[1:0] SpaceWire Strobe input In High SPW_TXD[1:0] SpaceWire Data output Out High SPW_TXS[1:0] SpaceWire Strobe output Out High SWMX[66:0] I/O switch matrix In/Out - Note 1: The READ signal may also change value during SDRAM accesses. GR712RC-DS, Jan 2016, Version 2.3 6 www.cobham.com/gaisler GR712RC 1.5 I/O switch matrix overview The I/O switch matrix provides access to several I/O units. When an interface is not activated, its pins automatically become general purpose I/O. After reset, all I/O switch matrix pins are defined as I/O until programmed otherwise. Note that some pins are input only, some are output only, and the rest are both input and output, as described in table 3. The enabling of the I/O units is described in [UM]. Figure 2 shows how the various I/O units are connected to the I/O switch matrix. Table 2 shows examples of possible configurations using the I/O switch matrix. Note that two SpaceWire interfaces are always available outside the I/O switch matrix. Table 3 shows a listing of all pins in the I/O switch matrix, indicating the priority amongst them. Table 4 shows a listing of pin utilization per I/O unit. Table 5 shows a listing of pins in the I/O switch matrix grouped per function (GPIO is not listed). Table 6 shows a complete listing of conflicts between I/O units (GPIO is not listed). TMS, TCK TDI, TDO JTAG INCLK, SPWCLK DLLBPN, RESETN ERRORN DSU LEON3FT LEON3FT 192K RAM CANMUX CLKGATE GPREG TESTEN SCANEN WDOGN IRQ STAT TIMERS AMBA TM MCTRL SDRAM 1553 TC SLINK CAN I2C ETH SPI UART UART UART UART UART UART ASCS GPIO GPIO SPW SPW SPW SPW SWMX[66:0] ADDRESS[23:0] DATA[31:0], CB[7:0] CTRL, SDCLK SPW SPW SPW_TXD/S[1:0] SPW_RXD/S[1:0] Figure 2. Architectural block diagram showing connections to the I/O switch matrix Table 2. Example of possible configurations using the I/O switch matrix. Note that other configurations are also possible. Interface type Example configuration CF0 SDRAM with or without Reed-Solomon CF1 CF2 CF3 CF4 CF5 1 1 1 1 1 6 UART 6 4 6 6 6 SpaceWire 6 4 2 2 4 3 1 1 Ethernet MIL-STD-1553B BC/RT/BM 1 I2C 1 SPI 1 1 SLINK 1 ASCS16 1 CCSDS/ECSS TC & TM GR712RC-DS, Jan 2016, Version 2.3 1 1 1 1 1 1 1 7 www.cobham.com/gaisler GR712RC Table 3. I/O switch matrix pin description, defining the order of priority for outputs and input/outputs, with the highest priority for each pin listed first. Pin no. Pin name Pin function Polarity Reset value Dir. Description 4 SWMX[0] UART_TX[0] - High Out UART Transmit 0 3 SWMX[1] UART_RX[0] - 2 SWMX[2] UART_TX[1] - 1 SWMX[3] UART_RX[1] - GPIO[0] - In GPIO 1 Register, bit 0 (input only) 240 SWMX[4] UART_TX[2] - High-Z Out UART Transmit 2 GPIO[1] - High-Z In/Out GPIO 1 Register, bit 1 MCFG3[8] - In At reset, bit 8 in MCFG3 register in the memory controller is set from this input. 239 238 233 232 231 230 229 228 227 226 225 220 219 SWMX[5] SWMX[6] SWMX[7] SWMX[8] SWMX[9] SWMX[10] SWMX[11] SWMX[12] SWMX[13] SWMX[14] SWMX[15] SWMX[16] SWMX[17] High In UART Receive 0 Out UART Transmit 1 In UART Receive 1 UART_RX[2] - In UART Receive 2 GPIO[2] - In GPIO 1 Register, bit 2 (input only) UART_TX[3] - High-Z Out UART Transmit 3 GPIO[3] - High-Z In/Out GPIO 1 Register, bit 3 MCFG1[9] - In At reset, bit 9 in MCFG1 register in the memory controller is set from this input UART_RX[3] - In UART Receive 3 GPIO[4] - In GPIO 1 Register, bit 4 (input only) UART_TX[4] - Out UART Transmit 4 High-Z TMDO - High-Z Out Telemetry Data Out GPIO[5] - High-Z In/Out GPIO 1 Register, bit 5 UART_RX[4] - In UART Receive 4 TMCLKI Rising In Telemetry Clock Input GPIO[6] - UART_TX[5] - High-Z In GPIO 1 Register, bit 6 (input only) Out UART Transmit 5 TMCLKO - High-Z Out Telemetry Clock Output GPIO[7] - High-Z In/Out GPIO 1 Register, bit 7 UART_RX[5] - In UART Receive 5 TCACT[0] High In Telecommand Active 0 In GPIO 1 Register, bit 8 (input only) Out SpaceWire Transmit Strobe 4 GPIO[8] - SPW_TXS[4] High High-Z SDCSN[0] Low High-Z Out SDRAM Select 0 GPIO[9] - High-Z In/Out GPIO 1 Register, bit 9 SPW_TXD[4] High High-Z Out SpaceWire Transmit Data 4 SDCSN[1] Low High-Z Out SDRAM Select 1 High-Z GPIO[10] - In/Out GPIO 1 Register, bit 10 SPW_RXS[4] High In SpaceWire Receive Strobe 4 TCCLK[0] Rising In Telecommand Clock 0 A16DASA - In ASCS DAS A - Slave data in GPIO[11] - In GPIO 1 Register, bit 11 (input only) SPW_RXD[4] High In SpaceWire Receive Data 4 TCD[0] - In Telecommand Data 0 A16DASB - In ASCS DAS B - Slave data in In GPIO 1 Register, bit 12 (input only) GPIO[12] - SPW_TXS[2] High High-Z Out SpaceWire Transmit Strobe 2 CANTXA - High-Z Out CAN Transmit A GPIO[13] - High-Z In/Out GPIO 1 Register, bit 13 SPW_TXD[2] High High-Z Out SpaceWire Transmit Data 2 CANTXB - High-Z Out CAN Transmit B GPIO[14] - High-Z In/Out GPIO 1 Register, bit 14 GR712RC-DS, Jan 2016, Version 2.3 8 www.cobham.com/gaisler GR712RC Table 3. I/O switch matrix pin description, defining the order of priority for outputs and input/outputs, with the highest priority for each pin listed first. Pin no. Pin name Pin function Polarity 218 SWMX[18] SPW_RXS[2] CANRXA 217 203 202 201 200 197 196 193 192 191 SWMX[19] SWMX[20] SWMX[21] SWMX[22] SWMX[23] SWMX[24] SWMX[25] SWMX[26] SWMX[27] SWMX[28] Reset value Dir. Description High In SpaceWire Receive Strobe 2 - In CAN Receive A GPIO[15] - In GPIO 1 Register, bit 15 (input only) SPW_RXD[2] High In SpaceWire Receive Data 2 CANRXB - In CAN Receive B GPIO[16] - In GPIO 1 Register, bit 16 (input only) SPW_TXS[3] High High-Z Out SpaceWire Transmit Strobe 3 SLSYNC High High-Z Out SLINK SYNC GPIO[17] - High-Z In/Out GPIO 1 Register, bit 17 SPW_TXD[3] High High-Z Out SpaceWire Transmit Data 3 A16ETR High High-Z Out ASCS ETR - Synchronization signal GPIO[18] - High-Z In/Out GPIO 1 Register, bit 18 SPW_RXS[3]] High In SpaceWire Receive Strobe 3 GPIO[19] - In GPIO 1 Register, bit 19 (input only) SPW_RXD[3] High In SpaceWire Receive Data 3 GPIO[20] - In GPIO 1 Register, bit 20 (input only) SPW_TXD[5] High High-Z Out SpaceWire Transmit Data 5 SDDQM[0] High High-Z Out SDRAM Data Mask 0, corresponds to DATA[7:0] GPIO[21] - High-Z In/Out GPIO 1 Register, bit 21 SPW_TXS[5] High High-Z Out SpaceWire Transmit Strobe 5 SDDQM[1] High High-Z Out SDRAM Data Mask 1, corresponds to DATA[15:8] High-Z GPIO[22] - In/Out GPIO 1 Register, bit 22 SPW_RXS[5] High In SpaceWire Receive Strobe 5 TCRFAVL[0] High In Telecommand RF Available 0 GPIO[23] - In GPIO 1 Register, bit 23 (input only) SPW_RXD[5] High In SpaceWire Receive Data 5 TCCLK[1] Rising In Telecommand Clock 1 GPIO[24] - In GPIO 1 Register, bit 24 (input only) 1553RXENA High High-Z Out MIL-STD-1553B Receive Enable A High-Z Out Proprietary, enabled by CAN - 190 SWMX[29] RMTXD[0] - High-Z Out Ethernet Transmit Data 0 GPIO[25] - High-Z In/Out GPIO 1 Register, bit 25 1553TXA High High-Z Out MIL-STD-1553B Transmit Positive A High-Z Out Proprietary, enabled by CAN - 189 188 185 SWMX[30] SWMX[31] SWMX[32] RMTXD[1] - High-Z Out Ethernet Transmit Data 1 GPIO[26] - High-Z In/Out GPIO 1 Register, bit 26 1553RXA High In MIL-STD-1553B Receive Positive A TCD[1] - In Telecommand Data 1 RMRXD[0] - In Ethernet Receive Data 0 GPIO[27] - In GPIO 1 Register, bit 27 (input only) 1553RXNA Low In MIL-STD-1553B Receive Negative A TCACT[1] High In Telecommand Active 1 RMRXD[1] - In Ethernet Receive Data 1 GPIO[28] - In GPIO 1 Register, bit 28 (input only) 1553TXNA Low High-Z Out MIL-STD-1553B Transmit Negative A High-Z Out Proprietary, enabled by CAN - 184 SWMX[33] RMTXEN High High-Z Out Ethernet Transmit Enable GPIO[29] - High-Z In/Out GPIO 1 Register, bit 29 1553TXINHA High High-Z Out MIL-STD-1553B Transmit Inhibit A GR712RC-DS, Jan 2016, Version 2.3 9 www.cobham.com/gaisler GR712RC Table 3. I/O switch matrix pin description, defining the order of priority for outputs and input/outputs, with the highest priority for each pin listed first. Pin no. Pin name Pin function Polarity Reset value High-Z Out Proprietary, enabled by CAN GPIO[30] - High-Z In/Out GPIO 1 Register, bit 30 1553RXB High In MIL-STD-1553B Receive Positive B TCRFAVL[1] High In Telecommand RF Available 1 - 183 182 179 178 177 SWMX[34] SWMX[35] SWMX[36] SWMX[37] SWMX[38] Dir. Description RMCRSDV High In Ethernet Carrier Sense / Data Valid GPIO[31] - In GPIO 1 Register, bit 31 (input only) 1553RXNB Low In MIL-STD-1553B Receive Negative B TCCLK[2] Rising In Telecommand Clock 2 RMINTN Low In Ethernet Management Interrupt GPIO[32] - In GPIO 2 Register, bit 0 (input only) 1553RXENB High High-Z Out MIL-STD-1553B Receive Enable B A16MCS High High-Z Out ASCS MCS - TM start/stop signal RMMDIO - High-Z In/Out Ethernet Media Interface Data GPIO[33] - High-Z In/Out GPIO 2 Register, bit 1 1553TXB High High-Z Out MIL-STD-1553B Transmit Positive B A16HS High High-Z Out ASCS HS - TM/TC serial clock RMMDC - High-Z Out Ethernet Media Interface Clock GPIO[34] - High-Z In/Out GPIO 2 Register, bit 2 SpaceWire clock divisor registers - In At reset, bits 8 and 0 in the clock divisor register of the SpaceWire interfaces are set from this input 1553CK - In MIL-STD-1553B Clock TCD[2] - In Telecommand Data 2 RMRFCLK - In Ethernet Reference Clock GPIO[35] - In GPIO 2 Register, bit 3 (input only) 176 SWMX[39] TCACT[2] High In Telecommand Active 2 GPIO[36] - 175 SWMX[40] 1553TXNB Low 174 173 172 169 166 165 SWMX[41] SWMX[42] SWMX[43] SWMX[44] SWMX[45] SWMX[46] High-Z In GPIO 2 Register, bit 4 (input only) Out MIL-STD-1553B Transmit Negative B A16DCS - High-Z Out ASCS DCS - Slave data out GPIO[37] - High-Z In/Out GPIO 2 Register, bit 5 SpaceWire clock divisor registers - In At reset, bits 9 and 1 in the clock divisor register of the SpaceWire interfaces are set from this input 1553TXINHB High High-Z Out MIL-STD-1553B Transmit Inhibit B A16MAS High High-Z Out ASCS MAS - TM start/stop signal GPIO[38] - High-Z In/Out GPIO 2 Register, bit 6 TCRFAVL[2] High In Telecommand RF Available 2 GPIO[39] - In GPIO 2 Register, bit 7 (input only) GPIO[40] - SpaceWire clock divisor registers - SPICLK High-Z Out Proprietary, enabled by CAN High-Z In/Out GPIO 2 Register, bit 8 In At reset, bits 10 and 2 in the clock divisor register of the SpaceWire interfaces are set from this input SPI Clock High-Z Out SLO - High-Z Out SLINK Data Out GPIO[41] - High-Z In/Out GPIO 2 Register, bit 9 SPIMOSI - High-Z Out SPI Master Out Slave In SLCLK High High-Z Out SLINK Clock GPIO[42] - High-Z In/Out GPIO 2 Register, bit 10 SpaceWire clock divisor registers - In At reset, bits 11 and 3 in the clock divisor register of the SpaceWire interfaces are set from this input TCCLK[3] Rising In Telecommand Clock 3 GPIO[43] - In GPIO 2 Register, bit 11 (input only) GR712RC-DS, Jan 2016, Version 2.3 10 www.cobham.com/gaisler GR712RC Table 3. I/O switch matrix pin description, defining the order of priority for outputs and input/outputs, with the highest priority for each pin listed first. Pin no. Pin name Pin function 164 SWMX[47] TCD[3] - In Telecommand Data 3 GPIO[44] - In GPIO 2 Register, bit 12 (input only) SDCASN Low High-Z Out SDRAM Column Address Strobe GPIO[45] - High-Z In/Out GPIO 2 Register, bit 13 SDRASN Low High-Z Out SDRAM Row Address Strobe GPIO[46] - High-Z In/Out GPIO 2 Register, bit 14 TCACT[3] High In Telecommand Active 3 GPIO[47] - In GPIO 2 Register, bit 15 (input only) 163 162 161 160 157 155 SWMX[48] SWMX[49] SWMX[50] SWMX[51] SWMX[52] SWMX[53] Polarity Reset value SPIMISO Dir. Description In SPI Master In Slave Out TCRFAVL[3] High In Telecommand RF Available 3 SLI - In SLINK Data In GPIO[48] - In GPIO 2 Register, bit 16 (input only) SDWEN Low High-Z Out SDRAM Write Enable GPIO[49] - High-Z In/Out GPIO 2 Register, bit 17 SDDQM[2] High High-Z Out SDRAM Data Mask 2, corresponds to DATA[23:16] GPIO[50] - High-Z In/Out GPIO 2 Register, bit 18 154 SWMX[54] SDDQM[3] High High-Z Out SDRAM Data Mask 3, corresponds to DATA[31:24] GPIO[51] - High-Z In/Out GPIO 2 Register, bit 19 153 SWMX[55] TCACT[4] High In Telecommand Active 4 GPIO[52] - In GPIO 2 Register, bit 20 (input only) TCRFAVL[4] High In Telecommand RF Available 4 GPIO[53] - In GPIO 2 Register, bit 21 (input only) High-Z In/Out I2C Serial Data High-Z In/Out GPIO 2 Register, bit 22 In Telecommand Clock 4 High-Z In/Out I2C Serial Clock High-Z In/Out GPIO 2 Register, bit 23 In Telecommand Data 4 Reed-Solomon Check Bit 8 144 143 142 140 137 136 135 132 129 128 127 SWMX[56] SWMX[57] SWMX[58] SWMX[59] SWMX[60] SWMX[61] SWMX[62] SWMX[63] SWMX[64] SWMX[65] SWMX[66] I2CSDA GPIO[54] - TCCLK[4] Rising I2CSCL GPIO[55] - TCD[4] - CB[8] - High-Z In/Out GPIO[56] - High-Z In/Out GPIO 2 Register, bit 24 CB[9] - High-Z In/Out Reed-Solomon Check Bit 9 GPIO[57] - High-Z In/Out GPIO 2 Register, bit 25 CB[10] - High-Z In/Out Reed-Solomon Check Bit 10 GPIO[58] - High-Z In/Out GPIO 2 Register, bit 26 CB[11] - High-Z In/Out Reed-Solomon Check Bit 11 GPIO[59] - High-Z In/Out GPIO 2 Register, bit 27 CB[12] - High-Z In/Out Reed-Solomon Check Bit 12 GPIO[60] - High-Z In/Out GPIO 2 Register, bit 28 CB[13] - High-Z In/Out Reed-Solomon Check Bit 13 GPIO[61] - High-Z In/Out GPIO 2 Register, bit 29 CB[14] - High-Z In/Out Reed-Solomon Check Bit 14 GPIO[62] - High-Z In/Out GPIO 2 Register, bit 30 CB[15] - High-Z In/Out Reed-Solomon Check Bit 15 GPIO[63] - High-Z In/Out GPIO 2 Register, bit 31 GR712RC-DS, Jan 2016, Version 2.3 11 www.cobham.com/gaisler GR712RC Table 4. I/O switch matrix pin utilization per interface type Interface type Pin function Direction SDRAM SDDQM[3:0], SDCASN, SDRASN, SDWEN, SDCSN[1:0] SDRAM Reed-Solomon CB[15:8] GPIO GPIO[...] 26 UART UART_TX[5:0], UART_RX[5:0] 6 6 SpaceWire SPW_RXD[5:2], SPW_RXS[5:2], SPW_TXD[5:2], SPW_TXS[5:2] 8 8 Ethernet RMTXD[1:0], RMTXEN, RMMDIO, RMMDC 5 4 CAN CANTXA, CANRXA, CANTXB, CANRXB 4 4 8 MIL-STD-1553B BC/RT/BM 1553RXA, 1553RXNA, 1553RXENA, 1553TXA, 1553TXNA, 1553TXINHA 5 8 13 In Out Total In/Out 9 9 8 8 38 64 12 16 1 10 RMRFCLK, RMRXD[0:1], RMCRSDV, RMINTN 1553RXB, 1553RXNB, 1553RXENB, 1553TXB, 1553TXNB, 1553TXINHB 1553CK I2C I2CSDA, I2CSCL SPI SPICLK, SPIMOSI, SPIMISO 1 2 2 3 SLINK SLI, SLO, SLSYNC, SLCLK 1 3 4 5 ASCS16 A16DASA, A16DASB, A16MCS, A16HS, A16DCS, A16MAS, A16ETR 2 CCSDS/ECSS TC TCACT[4:0], TCD[4:0], TCCLK[4:0], TCRFAV[4:0] 20 CCSDS/ECSS TM TMDO, TMCLKO, TMCLKI 1 GR712RC-DS, Jan 2016, Version 2.3 12 2 7 20 2 3 www.cobham.com/gaisler GR712RC Table 5. I/O switch matrix pins listed per function, including supporting signals outside the I/O switch matrix. Pin no. Pin name Pin function Polarity Reset value Dir. Description 157 SWMX[52] SDWEN Low High-Z Out SDRAM Write Enable 163 SWMX[48] SDCASN Low High-Z Out SDRAM Column Address Strobe 162 SWMX[49] SDRASN Low High-Z Out SDRAM Row Address Strobe 228 SWMX[12] SDCSN[0] Low High-Z Out SDRAM Select 0 227 SWMX[13] SDCSN[1] Low High-Z Out SDRAM Select 1 197 SWMX[24] SDDQM[0] High High-Z Out SDRAM Data Mask 0, corresponds to DATA[7:0] 196 SWMX[25] SDDQM[1] High High-Z Out SDRAM Data Mask 1, corresponds to DATA[15:8] 155 SWMX[53] SDDQM[2] High High-Z Out SDRAM Data Mask 2, corresponds to DATA[23:16] 154 SWMX[54] SDDQM[3] High High-Z Out SDRAM Data Mask 3, corresponds to DATA[31:24] 140 SWMX[59] CB[8] - High-Z In/Out Check Bit 8, Reed-Solomon 137 SWMX[60] CB[9] - High-Z In/Out Check Bit 9, Reed-Solomon 136 SWMX[61] CB[10] - High-Z In/Out Check Bit 10, Reed-Solomon 135 SWMX[62] CB[11] - High-Z In/Out Check Bit 11, Reed-Solomon 132 SWMX[63] CB[12] - High-Z In/Out Check Bit 12, Reed-Solomon 129 SWMX[64] CB[13] - High-Z In/Out Check Bit 13, Reed-Solomon 128 SWMX[65] CB[14] - High-Z In/Out Check Bit 14, Reed-Solomon 127 SWMX[66] CB[15] - High-Z In/Out Check Bit 15, Reed-Solomon ADDRESS[16:2] ADDRESS[16:2] - Low Out Memory address DATA[31:0] DATA[31:0] - High-Z In/Out Memory data bus High-Z CB[7:0] CB[7:0] - In/Out Memory checkbits 240 SWMX[4] MCFG3[8] - In At reset, bit 8 in MCFG3 register in the memory controller is set from this input. 238 SWMX[6] MCFG1[9] - In At reset, bit 9 in MCFG1 register in the memory controller is set from this input 4 SWMX[0] UART_TX[0] - High Out UART Transmit 0 3 SWMX[1] UART_RX[0] - In UART Receive 0 2 SWMX[2] UART_TX[1] - High Out UART Transmit 1 1 SWMX[3] UART_RX[1] - In UART Receive 1 240 SWMX[4] UART_TX[2] - High-Z Out UART Transmit 2 In UART Receive 2 High-Z Out UART Transmit 3 In UART Receive 3 High-Z Out UART Transmit 4 In UART Receive 4 High-Z Out UART Transmit 5 239 SWMX[5] UART_RX[2] - 238 SWMX[6] UART_TX[3] - 233 SWMX[7] UART_RX[3] - 232 SWMX[8] UART_TX[4] - 231 SWMX[9] UART_RX[4] - 230 SWMX[10] UART_TX[5] - 229 SWMX[11] UART_RX[5] - In UART Receive 5 213 SPW_RXD[0] SPW_RXD[0] High In SpaceWire Receive Data 0 214 SPW_RXS[0] SPW_RXS[0] High In SpaceWire Receive Strobe 0 215 SPW_TXD[0] SPW_TXD[0] High Low Out SpaceWire Transmit Data 0 216 SPW_TXS[0] SPW_TXS[0] High Low Out SpaceWire Transmit Strobe 0 204 SPW_RXD[1] SPW_RXD[1] High In SpaceWire Receive Data 1 205 SPW_RXS[1] SPW_RXS[1] High In SpaceWire Receive Strobe 1 206 SPW_TXD[1] SPW_TXD[1] High Low Out SpaceWire Transmit Data 1 209 SPW_TXS[1] SPW_TXS[1] High Low Out SpaceWire Transmit Strobe 1 217 SWMX[19] SPW_RXD[2] High In SpaceWire Receive Data 2 218 SWMX[18] SPW_RXS[2] High 219 SWMX[17] SPW_TXD[2] High High-Z 220 SWMX[16] SPW_TXS[2] High High-Z Out SpaceWire Transmit Strobe 2 200 SWMX[23] SPW_RXD[3] High In SpaceWire Receive Data 3 201 SWMX[22] SPW_RXS[3] High In SpaceWire Receive Strobe 3 GR712RC-DS, Jan 2016, Version 2.3 13 In SpaceWire Receive Strobe 2 Out SpaceWire Transmit Data 2 www.cobham.com/gaisler GR712RC Table 5. I/O switch matrix pins listed per function, including supporting signals outside the I/O switch matrix. Pin no. Pin name Pin function Polarity Reset value Dir. Description 202 SWMX[21] SPW_TXD[3] High High-Z Out SpaceWire Transmit Data 3 203 SWMX[20] SPW_TXS[3] High High-Z 225 SWMX[15] SPW_RXD[4] High 226 SWMX[14] SPW_RXS[4] High 227 SWMX[13] SPW_TXD[4] High High-Z 228 SWMX[12] SPW_TXS[4] High High-Z 192 SWMX[27] SPW_RXD[5] High Out SpaceWire Transmit Strobe 3 In SpaceWire Receive Data 4 In SpaceWire Receive Strobe 4 Out SpaceWire Transmit Data 4 Out SpaceWire Transmit Strobe 4 In SpaceWire Receive Data 5 193 SWMX[26] SPW_RXS[5] High In SpaceWire Receive Strobe 5 197 SWMX[24] SPW_TXD[5] High High-Z Out SpaceWire Transmit Data 5 196 SWMX[25] SPW_TXS[5] High High-Z Out SpaceWire Transmit Strobe 5 178 SWMX[37] - In At reset, bits 8 & 0 are set from this input 175 SWMX[40] - In At reset, bits 9 & 1 are set from this input 172 SWMX[43] SpaceWire clock divisor registers values at reset, all other bits are zero. - In At reset, bits 10 & 2 are set from this input 166 SWMX[45] - In At reset, bits 11 & 3 are set from this input 185 SWMX[32] RMTXEN High High-Z Out Ethernet Transmit Enable 191 SWMX[28] RMTXD[0] - High-Z Out Ethernet Transmit Data 0 190 SWMX[29] RMTXD[1] - High-Z Out Ethernet Transmit Data 1 189 SWMX[30] RMRXD[0] - In Ethernet Receive Data 0 188 SWMX[31] RMRXD[1] - In Ethernet Receive Data 1 183 SWMX[34] RMCRSDV High In Ethernet Carrier Sense / Data Valid 182 SWMX[35] RMINTN Low In Ethernet Management Interrupt 179 SWMX[36] RMMDIO - High-Z In/Out Ethernet Media Interface Data 178 SWMX[37] RMMDC - High-Z Out Ethernet Media Interface Clock In Ethernet Reference Clock High-Z Out CAN Transmit A In CAN Receive A High-Z Out CAN Transmit B 177 SWMX[38] RMRFCLK - 220 SWMX[16] CANTXA - 218 SWMX[18] CANRXA - 219 SWMX[17] CANTXB - 217 SWMX[19] CANRXB In CAN Receive B 191 SWMX[28] - High-Z Out Proprietary, enabled by CAN 190 SWMX[29] - High-Z Out Proprietary, enabled by CAN 185 SWMX[32] - High-Z Out Proprietary, enabled by CAN 184 SWMX[33] - High-Z Out Proprietary, enabled by CAN 172 SWMX[43] - High-Z Out Proprietary, enabled by CAN 177 SWMX[38] 1553CK - 184 SWMX[33] 1553TXINHA High 190 SWMX[29] 1553TXA High High-Z Out MIL-STD-1553B Transmit Positive A 185 SWMX[32] 1553TXNA Low High-Z Out MIL-STD-1553B Transmit Negative A 191 SWMX[28] 1553RXENA High High-Z Out MIL-STD-1553B Receive Enable A 189 SWMX[30] 1553RXA High In MIL-STD-1553B Receive Positive A High-Z In MIL-STD-1553B Clock Out MIL-STD-1553B Transmit Inhibit A 188 SWMX[31] 1553RXNA Low 174 SWMX[41] 1553TXINHB High 178 SWMX[37] 1553TXB High High-Z Out MIL-STD-1553B Transmit Positive B 175 SWMX[40] 1553TXNB Low High-Z Out MIL-STD-1553B Transmit Negative B 179 SWMX[36] 1553RXENB High High-Z Out MIL-STD-1553B Receive Enable B 183 SWMX[34] 1553RXB High In MIL-STD-1553B Receive Positive B 182 SWMX[35] 1553RXNB Low In MIL-STD-1553B Receive Negative B 143 SWMX[57] I2CSDA In/Out I2C Serial Data High-Z High-Z In MIL-STD-1553B Receive Negative A Out MIL-STD-1553B Transmit Inhibit B 142 SWMX[58] I2CSCL High-Z In/Out I2C Serial Clock 169 SWMX[44] SPICLK High-Z Out SPI Clock 166 SWMX[45] SPIMOSI 160 SWMX[51] SPIMISO GR712RC-DS, Jan 2016, Version 2.3 - High-Z 14 Out SPI Master Out Slave In In SPI Master In Slave Out www.cobham.com/gaisler GR712RC Table 5. I/O switch matrix pins listed per function, including supporting signals outside the I/O switch matrix. Pin no. Pin name Pin function Polarity Reset value Dir. Description 203 SWMX[20] SLSYNC High High-Z Out SLINK SYNC 166 SWMX[45] SLCLK High High-Z Out SLINK Clock 160 SWMX[51] SLI - In SLINK Data In 169 SWMX[44] SLO - 226 SWMX[14] A16DASA - High-Z Out SLINK Data Out In ASCS DAS A - Slave data in 225 SWMX[15] A16DASB - In ASCS DAS B - Slave data in 202 SWMX[21] A16ETR High High-Z Out ASCS ETR - Synchronization signal 175 SWMX[40] A16DCS - High-Z Out ASCS DCS - Slave data out 174 SWMX[41] A16MAS High High-Z Out ASCS MAS - TM start/stop signal 179 SWMX[36] A16MCS High High-Z Out ASCS MCS - TC start/stop signal 178 SWMX[37] A16HS High High-Z Out ASCS HS - TM/TC serial clock 229 SWMX[11] TCACT[0] High In Telecommand Active 0 226 SWMX[14] TCCLK[0] Rising In Telecommand Clock 0 225 SWMX[15] TCD[0] - In Telecommand Data 0 193 SWMX[26] TCRFAVL[0] High In Telecommand RF Available 0 188 SWMX[31] TCACT[1] High In Telecommand Active 1 192 SWMX[27] TCCLK[1] Rising In Telecommand Clock 1 189 SWMX[30] TCD[1] - In Telecommand Data 1 183 SWMX[34] TCRFAVL[1] High In Telecommand RF Available 1 176 SWMX[39] TCACT[2] High In Telecommand Active 2 182 SWMX[35] TCCLK[2] Rising In Telecommand Clock 2 177 SWMX[38] TCD[2] - In Telecommand Data 2 173 SWMX[42] TCRFAVL[2] High In Telecommand RF Available 2 161 SWMX[50] TCACT[3] High In Telecommand Active 3 165 SWMX[46] TCCLK[3] Rising In Telecommand Clock 3 164 SWMX[47] TCD[3] - In Telecommand Data 3 160 SWMX[51] TCRFAVL[3] High In Telecommand RF Available 3 153 SWMX[55] TCACT[4] High In Telecommand Active 4 143 SWMX[57] TCCLK[4] Rising In Telecommand Clock 4 142 SWMX[58] TCD[4] - In Telecommand Data 4 144 SWMX[56] TCRFAVL[4] High In Telecommand RF Available 4 231 SWMX[9] TMCLKI Rising In Telemetry Clock Input 230 SWMX[10] TMCLKO - High-Z Out Telemetry Clock Output 232 SWMX[8] TMDO - High-Z Out Telemetry Data Out GR712RC-DS, Jan 2016, Version 2.3 15 www.cobham.com/gaisler GR712RC Table 6. Conflicting interfaces in the I/O switch matrix are marked with an X, with duplicates shown in bold typeface. - UART 0 X X - UART 1 - UART 2 - UART 3 - UART 4 - UART 5 X - SpaceWire 0 X X - SpaceWire 1 - SpaceWire 2 - X SpaceWire 3 X - SpaceWire 5 X - X - Ethernet CAN X MIL-STD-1553B X X - X X - X X - I2C X X X X X X - SPI SLINK X ASCS X CCSDS TC 0 X X X CCSDS TC 1 X - X X - X X X CCSDS TC 2 X X X X X - X X - CCSDS TC 3 X X - 16 CCSDS TC 3 CCSDS TC 2 CCSDS TC 1 CCSDS TC 0 ASCS SLINK I2C MIL-STD-1553B CAN Ethernet SpaceWire 5 SpaceWire 4 SpaceWire 3 SpaceWire 2 - SpaceWire 1 X SpaceWire 0 UART 3 UART 2 UART 1 UART 0 SDRAM (with RS) GR712RC-DS, Jan 2016, Version 2.3 X UART 5 X CCSDS TM UART 4 CCSDS TC 4 X CCSDS TM X CCSDS TC 4 SpaceWire 4 X SPI SDRAM (with RS) www.cobham.com/gaisler GR712RC 2 Electrical characteristics 2.1 Absolute maximum ratings These values specify the stress that might apply to the device without causing it permanent damage. Table 7. Absolute maximum ratings 1) Symbol 2.2 Parameter Rating Units Min. Max. VDDIO DC Supply Voltage for I/O -0.3 4.2 V VDD DC Supply Voltage for Core -0.3 2.4 V VIN Input Voltage -0.3 VDDIO + 0.3 V Tstor Storage Temperature -65 +150 °C Tcase Operating Case Temperature -55 +125 °C Tsolder Lead Temperature (Soldering 10 sec.) +250 °C Tj Junction Temperature +150 °C JC (ceramic) Thermal Resistance, Junction to Case 4 °C/W PD Power Dissipation 6.25 W Note 1: Extended operation at the maximum levels may degrade the performance and affect the reliability of the device. Recommended operating conditions Table 8. Recommended operating conditions Symbol Parameter Rating Units Min. Typ. Max. VDDIO DC Supply Voltage for I/O 3.0 3.3 3.6 V VDD DC Supply Voltage for Core 1.65 1.8 1.95 V VIN Input Voltage 0 VDDIO V Tcase Operating Case Temperature -55 +125 °C SLIN Slew rate of all inputs 1) 0.4 Note 1: Applies only to the range 0.8V and 2.0V. GR712RC-DS, Jan 2016, Version 2.3 17 V/ns www.cobham.com/gaisler GR712RC 2.3 DC electrical performance characteristics Table 9. DC characteristics (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Symbol Parameter Condition Rating Min. VOH Output High Voltage 1) IOH = -4 mA 2) Typ. Units Max. 2.4 V IOH = -6 mA 3) VOL Output Low Voltage 0.5 IOL = 4 mA 2) V IOL = 6 mA 3) VIH Input High Voltage VIL Input Low Voltage IILEAK Input Leakage Current IOLEAK Output Leakage Current IOS Short-circuit Output Current 2.0 outputs at tri-state V 0.8 V -30 7) 30 7) uA -30 7) 30 7) uA 120 5) mA VO = VDDIO, VDDIO = 3.6V VO = 0V, VDDIO = 3.6V -120 5) IDDS Core Static Current FCLK = 0 MHz 1 250 8) mA IDD Core Supply Current FCLK = 100 MHz 0.9 2.0 5) A IDDIOS I/O Static Current 4) FCLK = 0 MHz VDDIO = 3.6V 0.2 4 9) mA IDDIO I/O Supply Current 6) CI/O I/O Pad Capacitance 5) Note 1: Except open-drain outputs ERRORN, WDOGN, I2CSCL and I2CSDA. Note 2: All outputs defined with a slow drive capability in the pin assignment table in section 3.2. Note 3: All outputs defined with a fast drive capability in the pin assignment table in section 3.2. Note 4: All inputs at 0 V or VDDIO. No resistive load. Note 5: Supplied as a design limit. Parameter not measured during production test. Note 6: The dynamic power consumption of the I/O supply can be calculated as a function of the average frequency and the capacitive load of each output i: sum of [FI/O * CLOAD](i) * (VDDIO)2 Note 7: This parameter is degrading with TID radiation. Given value at 300 krad(Si). Leakage current up to 100 krad(Si) is +/-15 uA. Note 8: This parameter is degrading with TID radiation. Given value at 300 krad(Si). Leakage current up to 100 krad(Si) is 10 mA. Note 9: This parameter is degrading with TID radiation. Given value at 300 krad(Si). Leakage current up to 100 krad(Si) is 2 mA. GR712RC-DS, Jan 2016, Version 2.3 mA 15 18 pF www.cobham.com/gaisler GR712RC Table 10. Detailed core power consumption (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Test condition Rating Units Typ. Max. 1) Static, no clocks or toggling signals 30 50 mW Standby, all cores clock gated 4 6 mW/MHz 1 processor core active at 50%, remaining IP cores clock gated 7 10 mW/MHz 1 processor core active at 100%, remaining IP cores clock gated 10 15 mW/MHz 2 processor cores active at 100%, remaining IP cores clock gated 15 24 mW/MHz 1 SpaceWire link active @ 100 Mbit/s 1 1.5 mW/MHz 2 CAN interfaces active 100% @ 1 Mbit/s 1 1.5 mW/MHz 0.5 1 mW/MHz Telemetry encoder active @ 10 Mbit/s Note 1: Supplied as a design limit. Parameter not measured during production test. GR712RC-DS, Jan 2016, Version 2.3 19 www.cobham.com/gaisler GR712RC 2.4 AC electrical performance characteristics All measured AC parameters have been tested with a 50 pF - 70 pF capacitive load on the outputs. Transition time measurements have been tested at a voltage level of 1.4 V. Equivalent load chart is provided in the product specification [PS.] 2.4.1 Clock The timing waveforms and timing parameters are shown in figure 3 and are defined in table 11. TINCLK INCLK Figure 3. Timing waveforms Table 11. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference Min Max Unit TINCLK input clock period without DLL INCLK 10 - ns FINCLK input clock frequency without DLL 2) INCLK - 100 MHz TINCLK_HIGH input clock high phase without DLL 5) INCLK 4.5 ns TINCLK_LOW input clock low phase without DLL 5) INCLK 4.5 ns TINCLK input clock period with DLL 1) INCLK 20 22 3) ns FINCLK input clock frequency with DLL 1) 2) INCLK 46 3) 50 MHz DCINCLK input frequency duty cycle with DLL INCLK 35 65 % TINCLK_HIGH input clock high phase with DLL 5) INCLK 7 ns TINCLK_LOW input clock low phase with DLL 5) INCLK 7 ns TCLK internal system clock period 4) 5) 6) - 10 - ns FCLK internal system clock frequency 2) 4) 5) 6) - - 100 MHz Note 1: For the system clock, the DLL provides a times 2 multiplication of the input frequency. Note 2: TINCLK = 1/FINCLK, TCLK = 1/FCLK Note 3: Parameter not measured during production test. Note 4: Applies to the system clock only (i.e. processor and AMBA clock) only. SpaceWire clocks are discussed in section 2.4.9. Note 5: The maximum internal system clock frequency is specified by the parameters TCLK and FCLK. The parameters TINCLK and FINCLK specify what the clock input pin and the DLL can support, and not what the internal logic can support. Note 6: The internal system clock frequency is limited by the timing of the memory interface towards external synchronous memory components. GR712RC-DS, Jan 2016, Version 2.3 20 www.cobham.com/gaisler GR712RC 2.4.2 Reset and initialization The timing waveforms and timing parameters are shown in figure 4 and are defined in table 12. INCLK RESETN tRSTGEN0 Figure 4. Timing waveforms Table 12. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tRSTGEN0 asserted period - 10 - TINCLK periods Note 1: The RESETN input is re-synchronized internally. Note 2: VDD must reach at least minimum operating voltage for tRESTGEN0 before RESETN is de-asserted. Note 3: If DLL is used, the internal reset is released 2048 TINCLK periods after RESETN is de-asserted Note 4: After power-up all flip-flops, on-chip memory and DLL are in an unknown state before reset. 2.4.3 LEON3 - High-performance SPARC V8 32-bit Processor The timing waveforms and timing parameters are shown in figure 5 and are defined in table 13. INCLK tLEON0 ERRORN tLEON1 Figure 5. Timing waveforms Table 13. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tLEON0 clock to output delay rising INCLK edge 2 1) 23 2) ns tLEON1 clock to output tri-state rising INCLK edge 50 1) ns Note 1: Parameter not measured during production test. Note 2: Parameter measured during production test without DLL enabled. Note 3: For correct operation, the signal should be pulled-up externally with 1- 10 kOhm. GR712RC does not include any internal pull-up resistors. GR712RC-DS, Jan 2016, Version 2.3 21 www.cobham.com/gaisler GR712RC 2.4.4 Fault tolerant memory controller The timing waveforms and timing parameters are shown in figure 6 and are defined in table 14. SDCLK tFTMCTRL0 ADDRESS[23:0] RAMSN[1:0] ROMSN[1:0] tFTMCTRL1 tFTMCTRL1 tFTMCTRL2 tFTMCTRL2 RAMWEN, WRITEN tFTMCTRL2 tFTMTRL2 READ tFTMCTRL3, tFTMCTRL4 DATA[31:0], CB[7:0] (output) tFTMCTRL5 SDCLK ADDRESS[23:0] RAMSN[1:0] ROMSN[1:0] tFTMCTRL6 tFTMCTRL6 RAMOEN, OEN READ tFTMCTRL7 DATA[31:0], CB[7:0] (input) tFTMCTRL8 tFTMCTRL10 tFTMCTRL9 BRDYN, BEXCN Figure 6. Timing waveforms - SRAM (0 wait state) access, PROM (0 wait state) access GR712RC-DS, Jan 2016, Version 2.3 22 www.cobham.com/gaisler GR712RC The timing waveforms and timing parameters are shown in figure 7 and are defined in table 14. SDCLK tFTMCTRL0 ADDRESS[23:0] tFTMCTRL1 IOSN tFTMCTRL1 tFTMCTRL2 tFTMCTRL2 RAMWEN, WRITEN tFTMCTRL2 tFTMCTRL2 READ tFTMCTRL3, tFTMCTRL4 DATA[31:0] (output) tFTMCTRL5 SDCLK ADDRESS[23:0] IOSN tFTMCTRL6 tFTMCTRL6 OEN READ tFTMCTRL7 DATA[31:0] (input) tFTMCTRL8 tFTMCTRL10 tFTMCTRL9 BRDYN, BEXCN Figure 7. Timing waveforms - I/O accesses GR712RC-DS, Jan 2016, Version 2.3 23 www.cobham.com/gaisler GR712RC Table 14. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge 2) Min Max Unit tFTMCTRL0 address clock to output delay 3) rising SDCLK edge 0 1) 7.5 ns tFTMCTRL1 clock to RAMSN[1:0] and ROMSN[1:0]output delay 3) rising SDCLK edge 0 1) 7.5 ns tFTMCTRL1 clock to IOSN output delay 3) rising SDCLK edge 0 1) 8.5 ns tFTMCTRL2 clock to output delay rising SDCLK edge 0 1) 8.5 ns tFTMCTRL3 clock to data output delay rising SDCLK edge 0 1) 6.5 ns tFTMCTRL4 clock to data non-tri-state delay rising SDCLK edge 0 1) 6.5 ns tFTMCTRL5 clock to data tri-state delay 4) rising SDCLK edge 0 1) 6.5 1) ns tFTMCTRL6 clock to output delay rising SDCLK edge 0 1) 8.5 ns tFTMCTRL7 data input to clock setup rising SDCLK edge 6.9 - ns tFTMCTRL8 data input from clock hold rising SDCLK edge -0.5 1) - ns tFTMCTRL9 input to clock setup rising SDCLK edge 6.9 - ns tFTMCTRL10 input from clock hold rising SDCLK edge -0.5 1) - ns Note 1: Parameter not measured during production test. Note 2: The specified timing is valid for the default programmable internal clock delay of value 0. Note 3: The ADDRESS[23:0] and RAMSN[1:0] signals change in the same clock cycle, which might not be compatible with all SRAM types. Check your SRAM documentation for compatibility. Note 4: GR712RC does not provide internal pull-up resistors on the DATA[31:0] and CB[15:0] buses. In the case of prolonged periods of idle bus activity in a board design, i.e. high impedance state, it is advised to add external pull-up resistors. GR712RC-DS, Jan 2016, Version 2.3 24 www.cobham.com/gaisler GR712RC The timing waveforms and timing parameters are shown in figure 8 and are defined in table 15. SDCLK SDCASN, SDRASN SDWEN, SDCSN[1:0] SDDQM[3:0] tFTMCTRL11 write nop read nop nop term nop nop nop tFTMCTRL11 ADDRESS[16:2] tFTMCTRL12 tFTMCTRL14 tFTMCTRL13 DATA[31:0], CB[15:0] tFTMCTRL15 Figure 8. Timing waveforms - SDRAM accesses Table 15. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge 2) tFTMCTRL11 clock to output delay rising SDCLK edge 1 tFTMCTRL12 clock to data output delay rising SDCLK edge tFTMCTRL13 data clock to data tri-state delay tFTMCTRL14 Min Max Unit 6 ns 1 1) 6.5 ns rising SDCLK edge 1 1) 6.5 1) ns data input to clock setup rising SDCLK edge 6.9 - ns tFTMCTRL15 data input from clock hold rising SDCLK edge -0.5 1) - ns Note 1: Parameter not measured during production test. Note 2: The specified timing is valid for the default programmable internal clock delay of value 0. Note 3: The maximum operating frequency of the GR712RC may be limited due to the timing performance of external SDRAM devices. 1) The timing waveforms and timing parameters are shown in figure 9 and are defined in table 16. TSDCLK0, TSDCLK51 INCLK SDCLK Figure 9. Timing waveforms Table 16. Timing parameters (VDD = 1.65V, VDDIO = 3.0V, Tcase = +125°C) 1) Name Parameter Reference TSDCLK0 clock to output delay, delay value 0 TSDCLK51 clock to output delay, delay value 51 Note 1: Production test performed at fixed voltage and temperature without DLL enabled. GR712RC-DS, Jan 2016, Version 2.3 25 Min Max Unit rising INCLK edge 7 10 ns rising INCLK edge 16 25 ns www.cobham.com/gaisler GR712RC 2.4.5 JTAG Debug Interface The timing waveforms and timing parameters are shown in figure 10 and are defined in table 17. tAHBJTAG0 tAHBJTAG1 TCK tAHBJTAG2 TDI, TMS tAHBJTAG4 tAHBJTAG3 TDO Figure 10. Timing waveforms Table 17. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tAHBJTAG0 clock period - 100 - ns tAHBJTAG1 clock low/high period - 40 - ns tAHBJTAG2 data input to clock setup rising TCK edge 10 1) - ns tAHBJTAG3 data input from clock hold rising TCK edge 10 1) - ns tAHBJTAG4 clock to data output delay falling TCK edge 0 1) 21 ns Note 1: Parameter not measured during production test. Note 2: For correct operation, all JTAG signals should be pulled-up externally with 1 - 10 kOhm. This is in line with the TAP specification where TMS and TDI implementation should be such that if an external signal fails (e.g. open circuit) then the behavior of TMS and TDI should be equivalent to a logical 1 input. GR712RC does not include any internal pull-up resistors. 2.4.6 General Purpose Timer Unit The timing waveforms and timing parameters are shown in figure 11 and are defined in table 18. INCLK tGPTIMER0 WDOGN tGPTIMER1 Figure 11. Timing waveforms Table 18. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tGPTIMER0 clock to output delay rising INCLK edge 2 1) 23 2) ns tGPTIMER1 clock to output tri-state rising INCLK edge 50 1) ns Note 1: Parameter is not measured during production test. Defined without DLL enabled. Note 2: Parameter measured during production test without DLL enabled. Note 3: For correct operation, the signal should be pulled-up externally with 1 - 10 kOhm. GR712RC does not include any internal pull-up resistors. Note 4: WDOGN output is undefined during internal reset when DLL is used to generate the internal system clock frequency. See section 2.4.2 for detailed timing information on the reset behavior. GR712RC-DS, Jan 2016, Version 2.3 26 www.cobham.com/gaisler GR712RC 2.4.7 General Purpose Input Output Port The timing waveforms and timing parameters are shown in figure 12 and are defined in table 19. INCLK GPIO[...] (output) tGRGPIO0 tGRGPIO0 tGRGPIO1 tGRGPIO2 GPIO[...] (output) GPIO[...] (input) tGRGPIO3 tGRGPIO4 Figure 12. Timing waveforms Table 19. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tGRGPIO0 clock to output delay rising INCLK edge 2 1) 21 2) ns tGRGPIO1 clock to non-tri-state delay rising INCLK edge 2 1) 21 1) ns tGRGPIO2 clock to tri-state delay rising INCLK edge 50 1) ns tGRGPIO3 input to clock hold rising INCLK edge - - ns 3) tGRGPIO4 input to clock setup rising INCLK edge - - ns 3) Note 1: Parameter is not measured during production test. Defined without DLL enabled. Note 2: Parameter measured during production test without DLL enabled. Note 3: The GPIO[...] inputs are re-synchronized to the internal system clock with a TCLK period. 2.4.8 UART Serial Interface The timing waveforms and timing parameters are shown in figure 13 and are defined in table 20. INCLK UART_TX[5:0] tAPBUART0 UART_RX[5:0] tAPBUART1 tAPBUART0 tAPBUART2 Figure 13. Timing waveforms Table 20. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge tAPBUART0 clock to output delay rising INCLK edge 2 tAPBUART1 input to clock hold rising INCLK edge - - ns 3) tAPBUART2 input to clock setup rising INCLK edge - - ns 3) Note 1: Parameter is not measured during production test. Defined without DLL enabled. Note 2: Parameter measured during production test without DLL enabled. Note 3: The UART_RX[5:0] inputs are re-synchronized to the internal system clock with a TCLK period. GR712RC-DS, Jan 2016, Version 2.3 27 Min 1) Max 21 2) Unit ns www.cobham.com/gaisler GR712RC 2.4.9 SpaceWire Interface The timing waveforms and timing parameters are shown in figure 14 and are defined in table 21. TSPWCLK SPWCLK tSPW2 tSPW2 SPW_TXD[5:0] tSPW2 SPW_TXS[5:0] tSPW3 SPW_TXD[5:0] SPW_TXS[5:0] tSPW4, tSPW6 tSPW4, tSPW6 SPW_RXD[5:0] SPW_RXS[5:0] tSPW4, tSPW6 tSPW5 SPW_RXD[5:0] SPW_RXS[5:0] Figure 14. Timing waveforms GR712RC-DS, Jan 2016, Version 2.3 28 www.cobham.com/gaisler GR712RC Table 21. Timing parameters transmitter (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit TSPWCLK input clock period without DLL 5) SPWCLK 10 4) - ns FSPWCLK input clock frequency without DLL 2) SPWCLK - 100 4) MHz DCSPWCLK input frequency duty cycle without DLL 5) SPWCLK 45 55 % TSPWCLK input clock period with DLL x2 1) 6) SPWCLK 20 22 4) ns FSPWCLK input clock frequency with DLL x2 1) 2) SPWCLK 45 4) 50 MHz TSPWCLK input clock period with DLL x4 1) 6) SPWCLK 20 22 4) ns FSPWCLK input clock frequency with DLL x4 1) 2) SPWCLK 45 4) 50 MHz DCSPWCLK input frequency duty cycle with DLL SPWCLK 35 4) 65 4) % TSPW internal transmitter clock period 6) - 5 500 4) ns FSPW internal transmitter clock frequency 2) 6) - 2 4) 200 MHz tSPW2 output data bit period - 5 4) 500 4) ns tSPW3 data & strobe output skew & jitter - - 500 4) ps tSPW4 input data bit period - 5 4) 500 4) ns tSPW5 data & strobe input skew, jitter & hold - - 800 4) ps tSPW6 data & strobe edge separation 5) - 2500 4) - ps Note 1: For the internal SpaceWire clock, the DLL provides a times 2 or 4 multiplication of the input frequency. Note 2: TSPWCLK = 1/FSPWCLK, TSPW = 1/FSPW Note 3: N/A Note 4: Parameter not measured during production test. Note 5: Minimum internal edge separation equals half the internal transmitter clock period. Minimum tSPW6 is specified at minimum TSPW with 50% duty cycle. External edge separation should not be less than the sum of tSPW5 + tSPW6. Note 6: The maximum SpaceWire clock frequency is specified by the parameters TSPW and FSPW. The parameters TSPWCLK and FSPWCLK specify what the clock input pin and the DLL can support, and not what the internal logic can support. Note 7: The parameters tSPWn are only valid between signals belonging to one SpaceWire link. GR712RC-DS, Jan 2016, Version 2.3 29 www.cobham.com/gaisler GR712RC 2.4.10 Ethernet Media Access Controller (MAC) The timing waveforms and timing parameters are shown in figure 15 and are defined in table 22. RMRFCLK RMTXD[1:0], RMTXEN tGRETH0 RMRXD[1:0] tGRETH0 tGRETH1 tGRETH2 Figure 15. Timing waveforms Table 22. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tGRETHREF Ethernet reference clock period any RMRFCLK edge 20 4) - ns tGRETH0 transmitter clock to output delay rising RMRFCLK edge 2 1) 15 ns tGRETH1 input to receiver clock hold rising RMRFCLK edge 2 - ns tGRETH2 input to receiver clock setup rising RMRFCLK edge 4 - ns Note 1: Parameter not measured during production test. Note 2: The RMINTN, RMMDIO and RMCRSDV inputs are re-synchronized internally. Note 3: The RMMDIO and RMMDC outputs are low speed signals without any timing relationship with the RMRFCLK clock. Note 4: According to Ethernet standard the reference clock RMRFCLK frequency must be 50 MHz +/- 50 ppm. 2.4.11 CAN Interface The timing waveforms and timing parameters are shown in figure 16 and are defined in table 23. INCLK tCAN_OC0 CANTX[A:B] tCAN_OC2 CANRX[A:B] tCAN_OC1 Figure 16. Timing waveforms Table 23. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit 21 2) ns tCAN_OC0 clock to data output delay rising INCLK edge 2 1) tCAN_OC1 data input to clock setup rising INCLK edge - - ns 3) tCAN_OC2 data input from clock hold rising INCLK edge - - ns 3) Note 1: Parameter is not measured during production test. Defined without DLL enabled. Note 2: Parameter measured during production test without DLL enabled. Note 3: The CANRX[A:B] input is re-synchronized to the internal system clock with a TCLK period. GR712RC-DS, Jan 2016, Version 2.3 30 www.cobham.com/gaisler GR712RC 2.4.12 Obsolete Proprietary function not supported. 2.4.13 MIL-STD-1553B BC/RT/BM The timing waveforms and timing parameters are shown in figure 17 and are defined in table 24. 1553CK t1553BRM0 1553TXA/TXAN 1553TXB/TXBN 1553TXINHA, 1553TXINHB 1553RXENA, 1553RXENB 1553RXA/RXAN 1553RXB/RXBN t1553BRM2 t1553BRM1 Figure 17. Timing waveforms Table 24. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit t1553BRM0 clock to data output delay rising 1553CK edge 2 1) 21 1) ns t1553BRM1 data input to clock setup rising 1553CK edge - - ns 2) t1553BRM2 data input from clock hold rising 1553CK edge - - ns 2) t1553BRM3 clock frequency 1553CK 16, 20, 24 MHz 3) Note 1: Parameter not measured during production test. Note 2: The 1553RXA, 1553RXAN, 1553RXB and 1553RXBN inputs are re-synchronized internally. Note 3: The core frequency must be lower than the internal system frequency: t1553BRM3 < FCLK GR712RC-DS, Jan 2016, Version 2.3 31 www.cobham.com/gaisler GR712RC 2.4.14 I2C-master The timing waveforms and timing parameters are shown in figure 18 and are defined in table 25. I2CSCL (input/output) tI2C0 I2CSDA (output) tI2C1 tI2C3 I2CSDA (input) tI2C2 Figure 18. Timing waveforms Table 25. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tI2C0 data output valid before clock rising I2CSCL edge - scaler 1) TCLK periods tI2C1 data output valid after clock falling I2CSCL edge scaler 1) - TCLK periods tI2C2 data input setup to clock rising I2CSCL edge 2 2) - TCLK periods tI2C3 data input hold from clock falling I2CSCL edge 0 2) - TCLK periods Note 1: The core’s I2C bus functional timing depends on the core’s scaler value and the internal system clock TCLK period. When the scaler is set for the core to operate in Fast- or Standard-Mode, the timing characteristics in the I2C-bus specification apply. The maximum TCLK period for proper operation is 50 ns. Note 2: The I2CSCL and I2CSDA inputs are re-synchronized to the internal system clock with a TCLK period. Note 3: I2CSCL and I2CSDA are open-drain outputs, driving a logical 0 level or tri-state. Note 4: For correct operation, the signals should be pulled-up externally with 10 kOhm. GR712RC does not include any internal pull-up resistors. 2.4.15 SPI controller The timing waveforms and timing parameters are shown in figure 19 and are defined in table 26. SPICLK SPIMOSI tSPICTRL0 SPIMISO tSPICTRL1 tSPICTRL0 tSPICTRL2 Figure 19. Timing waveforms Table 26. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge tSPICTRL0 clock to output delay driving SPICLK edge tSPICTRL1 input to clock hold sampling SPICLK edge 0 2) - ns 3) tSPICTRL2 input to clock setup sampling SPICLK edge 20 2) - ns 3) Note 1: The driving and sampling edges of the interface are programmable, and always opposite to each other. Note 2: Parameter not measured during production test. Note 3: The SPIMISO input is re-synchronized to the internal system clock with a TCLK period. GR712RC-DS, Jan 2016, Version 2.3 32 Min -15 2) Max Unit 2) ns 1) 15 www.cobham.com/gaisler GR712RC 2.4.16 SLINK Serial Bus Based Real-Time Network Master The timing waveforms and timing parameters are shown in figure 20 and are defined in table 27. SLCLK SLO, SLSYNC (output) tSLINK0 SLI (input) tSLINK1 tSLINK0 tSLINK2 Figure 20. Timing waveforms Table 27. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tSLINK0 clock to output delay rising SLCLK edge 1 - TCLK periods 1) tSLINK1 input to clock hold rising SLCLK edge 0 - TCLK periods tSLINK2 input to clock setup rising SLCLK edge 2 - TCLK periods Note 1: Output timing depends on the ODEL setting in the core’s control register. Outputs will transition (ODEL+1)*(system clock period) ns after SLCLK rising edge. 2.4.17 ASCS controller The timing waveforms and timing parameters are shown in figure 21 and are defined in table 28. tASCS1 A16MCS, A16MAS tASCS3 tASCS4 tASCS5 A16DCS tASCS2 A16HS tASCS0 tASCS6 tASCS7 A16DASA, A16DASB Figure 21. Timing waveforms Table 28. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tASCS0 clock period rising A16HS edge 2 - TCLK periods 1) tASCS1 qualifier de-asserted width - 20 - TCLK periods 1) tASCS2 qualifier asserted to clock rising A16HS edge 8 - TCLK periods 1) tASCS3 clock to qualifier de-asserted falling A16HS edge 2 - TCLK periods 1) tASCS4 output data to clock setup rising A16HS edge 1 - TCLK periods 1) tASCS5 output data after clock hold rising A16HS edge 1 - TCLK periods 1) tASCS6 input data to clock setup rising A16HS edge 2 - TCLK periods tASCS7 input data after clock hold rising A16HS edge 2 - TCLK periods Note 1: The timing of the interface is programmable and is dependable on the tASCS0 clock period. GR712RC-DS, Jan 2016, Version 2.3 33 www.cobham.com/gaisler GR712RC 2.4.18 CCSDS / ECSS Telecommand Decoder The timing waveforms and timing parameters are shown in figure 22 and are defined in table 29. TCCLK[4:0] tGRTC0 TCACT[4:0] TCD[4:0] TCRFAVL[4:0] tGRTC1 tGRTC2 tGRTC3 tGRTC4 Figure 22. Timing waveforms Table 29. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tGRTC0 bit period rising TCCLK edge 7 - TCLK periods tGRTC1 data/active input to clock hold rising TCCLK edge 3 - TCLK periods tGRTC2 data/active input to clock setup rising TCCLK edge 3 - TCLK periods tGRTC3 RF available input to clock hold rising INCLK edge - - ns 1) tGRTC4 RF available input to clock setup rising INCLK edge - - ns 1) Note 1: The TCRFAVL[4:0] inputs are re-synchronized to the internal system clock with a TCLK period. 2.4.19 CCSDS / ECSS Telemetry Encoder The timing waveforms and timing parameters are shown in figure 23 and are defined in table 30. TMCLKO TMDO tGRTM0 TCACT[4:0], TCRFAVL[4:0] tGRTM1 tGRTM0 tGRTM2 Figure 23. Timing waveforms Table 30. Timing parameters (VDD = 1.8V +/- 0.15V, VDDIO = 3.3V +/- 0.3V, Tcase = -55°C to +125°C) Name Parameter Reference edge Min Max Unit tGRTM0 clock to output delay any TMCLKO edge -15 3) 15 3) ns 1) tGRTM1 input to clock hold rising INCLK edge - - ns 2) tGRTM2 input to clock setup rising INCLK edge - - ns 2) tGRTM3 input to output delay TMCLKI to TMCLKO 0 3) 23 3) ns tGRTM4 TMCLKI clock period - 20 3) Note 1: The TMDO signal is output simultaneously with the programmable TMCLKO clock edge. The opposite clock edge should be used for sampling TMDO. Note 2: The TCACT[4:0] and TCRFAVL[4:0] inputs are re-synchronized to the TCLK period. Note 3: Parameter not measured during production test. GR712RC-DS, Jan 2016, Version 2.3 34 ns www.cobham.com/gaisler GR712RC 3 Mechanical description 3.1 Package Ceramic hermetically sealed CQFP-240L package with 0.5 mm lead pitch, with gold plated leads. See drawing in section 3.3. All devices are marked on top lid with GR712RC. For space class marking see the product specification [PS]. Lead trimming and forming are performed by customer prior to assembly on printed circuit board. 3.2 Pin assignment The pin assignment in table 31 shows the implementation characteristics of each signal, indicating how each pin has been configured in terms of drive capability, polarity and reset value. Table 31. Pin assignment Pin no. Pin name Dir. 1 SWMX[3] In 2 SWMX[2] Out Drive Polarity Reset value Slow - Note I/O Switch Matrix 3 High - I/O Switch Matrix 2 3 SWMX[1] In 4 SWMX[0] Out Slow - High I/O Switch Matrix 1 I/O Switch Matrix 0 5 CB[6] In/Out Slow - High-Z Check Bit 6 6 VDDIO I/O Supply Voltage I/O Supply Ground 7 GNDIO 8 CB[5] In/Out Slow - High-Z Check Bit 5 9 CB[4] In/Out Slow - High-Z Check Bit 4 10 CB[3] In/Out Slow - High-Z Check Bit 3 11 CB[2] In/Out Slow - High-Z Check Bit 2 12 CB[1] In/Out Slow - High-Z Check Bit 1 13 VDD 14 GND 15 CB[0] In/Out Slow - High-Z Check Bit 0 16 DATA[31] In/Out Slow - High-Z Data Bit 31 17 DATA[30] In/Out Slow - High-Z 18 VDDIO 2) Core Supply Voltage Core Supply Ground Data Bit 30 I/O Supply Voltage 19 GNDIO 20 DATA[29] In/Out Slow - High-Z I/O Supply Ground Data Bit 29 21 DATA[28] In/Out Slow - High-Z Data Bit 28 22 DATA[27] In/Out Slow - High-Z Data Bit 27 23 DATA[26] In/Out Slow - High-Z Data Bit 26 24 DATA[25] In/Out Slow - High-Z Data Bit 25 25 DATA[24] In/Out Slow - High-Z Data Bit 24 26 DATA[23] In/Out Slow - High-Z Data Bit 23 27 DATA[22] In/Out Slow - High-Z 28 VDDIO I/O Supply Voltage 29 GNDIO I/O Supply Ground 30 VDD Core Supply Voltage 31 GND 32 DATA[21] In/Out Slow - High-Z Data Bit 21 33 DATA[20] In/Out Slow - High-Z Data Bit 20 34 DATA[19] In/Out Slow - High-Z Data Bit 19 35 DATA[18] In/Out Slow - High-Z Data Bit 18 Data Bit 22 Core Supply Ground GR712RC-DS, Jan 2016, Version 2.3 35 www.cobham.com/gaisler GR712RC Table 31. Pin assignment Pin no. Pin name Dir. Drive Polarity Reset value Note 36 DATA[17] In/Out Slow - High-Z Data Bit 17 37 DATA[16] In/Out Slow - High-Z 38 VDDIO Data Bit 16 I/O Supply Voltage 39 GNDIO 40 DATA[15] In/Out Slow - High-Z I/O Supply Ground Data Bit 15 41 DATA[14] In/Out Slow - High-Z Data Bit 14 42 DATA[13] In/Out Slow - High-Z Data Bit 13 43 DATA[12] In/Out Slow - High-Z Data Bit 12 44 DATA[11] In/Out Slow - High-Z Data Bit 11 45 DATA[10] In/Out Slow - High-Z Data Bit 10 46 DATA[9] In/Out Slow - High-Z Data Bit 9 47 VDD 48 GND 49 DATA[8] 50 VDDIO Core Supply Voltage Core Supply Ground In/Out Slow - High-Z Data Bit 8 I/O Supply Voltage 51 GNDIO 52 DATA[7] In/Out Slow - High-Z Data Bit 7 53 DATA[6] In/Out Slow - High-Z Data Bit 6 54 DATA[5] In/Out Slow - High-Z Data Bit 5 55 DATA[4] In/Out Slow - High-Z Data Bit 4 56 DATA[3] In/Out Slow - High-Z Data Bit 3 57 DATA[2] In/Out Slow - High-Z Data Bit 2 58 DATA[1] In/Out Slow - High-Z Data Bit 1 59 DATA[0] In/Out Slow - High-Z 60 VDDIO 61 GNDIO 62 ADDRESS[0] I/O Supply Ground Data Bit 0 I/O Supply Voltage I/O Supply Ground Out Slow - Low Address Bit 0 63 ADDRESS[1] Out Slow - Low Address Bit 1 64 ADDRESS[2] Out Fast - Low Address Bit 2 65 ADDRESS[3] Out Fast - Low Address Bit 3 66 VDD Core Supply Voltage 67 GND 68 ADDRESS[4] 69 VDDIO I/O Supply Voltage 70 GNDIO I/O Supply Ground 71 ADDRESS[5] Out Fast - Low Address Bit 5 72 ADDRESS[6] Out Fast - Low Address Bit 6 73 ADDRESS[7] Out Fast - Low Address Bit 7 74 ADDRESS[8] Out Fast - Low Address Bit 8 75 VDDIO 76 GNDIO 77 ADDRESS[9] 78 VDD 79 GND 80 ADDRESS[10] Core Supply Ground Out Fast - Low Address Bit 4 I/O Supply Voltage I/O Supply Ground Out Fast - Low Address Bit 9 Core Supply Voltage Core Supply Ground Out Fast - Low Address Bit 10 81 ADDRESS[11] Out Fast - Low Address Bit 11 82 ADDRESS[12] Out Fast - Low Address Bit 12 83 VDDIO 84 GNDIO 85 ADDRESS[23] Out Slow - Low Address Bit 23 86 ADDRESS[13] Out Fast - Low Address Bit 13 I/O Supply Voltage I/O Supply Ground GR712RC-DS, Jan 2016, Version 2.3 36 www.cobham.com/gaisler GR712RC Table 31. Pin assignment Pin no. Pin name Dir. Drive Polarity Reset value Note 87 ADDRESS[22] Out Slow - Low Address Bit 22 88 ADDRESS[21] Out Slow - Low Address Bit 21 89 ADDRESS[14] Out Fast - Low Address Bit 14 90 VDD 91 GND 92 ADDRESS[20] 93 VDDIO Core Supply Voltage Core Supply Ground Out Slow - Low Address Bit 20 I/O Supply Voltage 94 GNDIO 95 ADDRESS[19] Out Slow - Low Address Bit 19 I/O Supply Ground 96 ADDRESS[15] Out Fast - Low Address Bit 15 97 ADDRESS[18] Out Slow - Low Address Bit 18 98 ADDRESS[16] Out Fast - Low Address Bit 16 99 ADDRESS[17] Out Slow - Low Address Bit 17 100 SCANEN In 101 ROMSN[0] Out 102 VDD Core Supply Voltage 103 GND Core Supply Ground 104 VDDIO I/O Supply Voltage 105 GNDIO I/O Supply Ground 106 ROMSN[1] Out Slow Low High PROM Select 1 107 WRITEN Out Slow Low High Write Strobe for PROM, I/O 108 IOSN Out Slow Low High I/O Select 109 RAMSN[0] Out Slow Low High SRAM Select 0 110 RAMSN[1] Out Slow Low High SRAM Select 1 111 RAMOEN Out Slow Low High SRAM Output Enable 112 RAMWEN Out Slow Low High 113 BRDYN In 114 VDD Core Supply Voltage 115 GND Core Supply Ground 116 VDDIO I/O Supply Voltage 117 GNDIO I/O Supply Ground High Slow Low Scan enable (tie to ground) High Low PROM Select 0 SRAM Write Enable Bus Ready 118 BEXCN In 119 WDOGN Out Slow Low 120 READ Out Slow 121 TDI In - Jtag Test Data In 122 TCK In - Jtag Test Clock 123 TMS In High 124 TDO Out 125 TESTEN In 126 OEN Out Slow Low High Output Enable for PROM, I/O 127 SWMX[66] In/Out Slow - High-Z I/O Switch Matrix 66 128 SWMX[65] In/Out Slow - High-Z I/O Switch Matrix 65 129 SWMX[64] In/Out Slow - High-Z I/O Switch Matrix 64 130 VDDIO 131 GNDIO 132 SWMX[63] 133 VDD Slow Bus Exception Low High-Z High High - Watchdog Indicator (output is driven active low, else it is in tri-state and therefore requires external pull-up) SRAM, PROM, I/O read indicator Jtag Test Mode Select Low High Jtag Test Data Out Test Enable (tie to ground) I/O Supply Voltage I/O Supply Ground In/Out Slow - High-Z I/O Switch Matrix 63 Core Supply Voltage 134 GND 135 SWMX[62] In/Out Slow - High-Z I/O Switch Matrix 62 Core Supply Ground 136 SWMX[61] In/Out Slow - High-Z I/O Switch Matrix 61 137 SWMX[60] In/Out Slow - High-Z I/O Switch Matrix 60 GR712RC-DS, Jan 2016, Version 2.3 37 www.cobham.com/gaisler GR712RC Table 31. Pin assignment Pin no. Pin name 138 VDDIO Dir. Drive Polarity Reset value Note 139 GNDIO 140 SWMX[59] 141 CB[7] In/Out Slow - High-Z Check Bit 7 142 SWMX[58] In/Out Slow - High-Z I/O Switch Matrix 58 143 SWMX[57] In/Out Slow - High-Z I/O Switch Matrix 57 144 SWMX[56] In 145 RESETN In 146 ERRORN Out 147 DLLBPN In Low DLL Bypass 148 INCLK In - Input Clock I/O Supply Voltage I/O Supply Ground In/Out Slow - High-Z - I/O Switch Matrix 56 Low Slow Low I/O Switch Matrix 59 System Reset High-Z Processor Error Mode (output is driven active low, else it is in tri-state and therefore requires external pull-up). See a more detailed description of LEON3 integer unit exceptions in the section named “Exceptions” in [UM] 149 VDDIO I/O Supply Voltage 150 VDD Core Supply Voltage 151 GND Core Supply Ground 152 GNDIO I/O Supply Ground 153 SWMX[55] In 154 SWMX[54] In/Out Fast - High-Z I/O Switch Matrix 55 I/O Switch Matrix 54 155 SWMX[53] In/Out Fast - High-Z I/O Switch Matrix 53 156 SDCLK Out Fast - - SDRAM Clock 157 SWMX[52] In/Out Fast - High-Z I/O Switch Matrix 52 158 VDDIO 159 GNDIO 160 SWMX[51] I/O Supply Voltage I/O Supply Ground In - I/O Switch Matrix 51 161 SWMX[50] In 162 SWMX[49] In/Out Fast - High-Z 163 SWMX[48] In/Out Fast - High-Z 164 SWMX[47] In 165 SWMX[46] In 166 SWMX[45] In/Out 167 VDD 168 GND 169 SWMX[44] 170 VDDIO 171 GNDIO 172 SWMX[43] - I/O Switch Matrix 50 - - I/O Switch Matrix 48 I/O Switch Matrix 47 Slow I/O Switch Matrix 49 I/O Switch Matrix 46 High-Z I/O Switch Matrix 45 1) Core Supply Voltage Core Supply Ground In/Out Slow - High-Z I/O Switch Matrix 44 I/O Supply Voltage I/O Supply Ground In/Out Slow - High-Z I/O Switch Matrix 43 1) 173 SWMX[42] In 174 SWMX[41] In/Out Slow - High-Z I/O Switch Matrix 41 175 SWMX[40] In/Out Slow - High-Z I/O Switch Matrix 40 1) 176 SWMX[39] In - 177 SWMX[38] In - 178 SWMX[37] In/Out Slow - High-Z I/O Switch Matrix 37 1) 179 SWMX[36] In/Out Slow - High-Z I/O Switch Matrix 36 180 VDDIO I/O Supply Voltage 181 GNDIO I/O Supply Ground 182 SWMX[35] In - 183 SWMX[34] In - 184 SWMX[33] In/Out Slow - High-Z I/O Switch Matrix 33 185 SWMX[32] In/Out Slow - High-Z I/O Switch Matrix 32 186 VDD GR712RC-DS, Jan 2016, Version 2.3 - I/O Switch Matrix 42 I/O Switch Matrix 39 I/O Switch Matrix 38 I/O Switch Matrix 35 I/O Switch Matrix 34 Core Supply Voltage 38 www.cobham.com/gaisler GR712RC Table 31. Pin assignment Pin no. Pin name 187 GND Dir. Drive Polarity Reset value Note 188 SWMX[31] In - I/O Switch Matrix 31 189 SWMX[30] In - I/O Switch Matrix 30 190 SWMX[29] In/Out Slow - High-Z I/O Switch Matrix 29 191 SWMX[28] In/Out Slow - High-Z I/O Switch Matrix 28 192 SWMX[27] In - I/O Switch Matrix 27 193 SWMX[26] In - I/O Switch Matrix 26 194 VDDIO 195 GNDIO 196 SWMX[25] In/Out Fast - High-Z I/O Switch Matrix 25 197 SWMX[24] In/Out Fast - High-Z I/O Switch Matrix 24 198 VDD 199 GND 200 SWMX[23] In - I/O Switch Matrix 23 201 SWMX[22] In - I/O Switch Matrix 22 202 SWMX[21] In/Out Fast - High-Z I/O Switch Matrix 21 203 SWMX[20] In/Out Fast - High-Z I/O Switch Matrix 20 204 SPW_RXD[1] - SpaceWire Receive Data 1 205 SPW_RXS[1] - SpaceWire Receive Strobe 1 206 SPW_TXD[1] 207 VDDIO 208 GNDIO 209 SPW_TXS[1] Core Supply Ground I/O Supply Voltage I/O Supply Ground Core Supply Voltage Core Supply Ground Out Fast - Low SpaceWire Transmit Data 1 I/O Supply Voltage I/O Supply Ground Out Fast - Low SpaceWire Transmit Strobe 1 210 VDD 211 GND Core Supply Voltage 212 SPWCLK In - SpaceWire Receiver and Transmitter Clock 213 SPW_RXD[0] In - SpaceWire Receive Data 0 Core Supply Ground 214 SPW_RXS[0] In 215 SPW_TXD[0] Out Fast - 216 SPW_TXS[0] Out 217 SWMX[19] In SpaceWire Receive Strobe 0 - Low Fast - Low Slow - SpaceWire Transmit Data 0 SpaceWire Transmit Strobe 0 I/O Switch Matrix 19 218 SWMX[18] In 219 SWMX[17] In/Out Fast - High-Z I/O Switch Matrix 17 220 SWMX[16] In/Out Fast - High-Z I/O Switch Matrix 16 221 VDDIO I/O Supply Voltage 222 VDD Core Supply Voltage GR712RC-DS, Jan 2016, Version 2.3 - 39 I/O Switch Matrix 18 www.cobham.com/gaisler GR712RC Table 31. Pin assignment Pin no. Pin name 223 GND 224 GNDIO 225 SWMX[15] Dir. Drive Polarity Reset value Note Core Supply Ground I/O Supply Ground In - I/O Switch Matrix 15 226 SWMX[14] In 227 SWMX[13] In/Out Fast - High-Z 228 SWMX[12] In/Out Fast - High-Z 229 SWMX[11] In 230 SWMX[10] In/Out 231 SWMX[9] In 232 SWMX[8] In/Out 233 SWMX[7] In 234 VDD Core Supply Voltage 235 GND Core Supply Ground 236 VDDIO I/O Supply Voltage 237 GNDIO I/O Supply Ground 238 SWMX[6] In/Out 239 SWMX[5] In 240 SWMX[4] In/Out Note 1: See tables 3 and 5 for detailed description of behavior at reset. Note 2: GNDIO is connected internally to GND. GR712RC-DS, Jan 2016, Version 2.3 - I/O Switch Matrix 14 Slow - - High-Z I/O Switch Matrix 10 High-Z I/O Switch Matrix 08 I/O Switch Matrix 09 - Slow - I/O Switch Matrix 07 High-Z Slow - 40 I/O Switch Matrix 12 I/O Switch Matrix 11 Slow I/O Switch Matrix 13 I/O Switch Matrix 06 1) I/O Switch Matrix 05 High-Z I/O Switch Matrix 04 1) www.cobham.com/gaisler GR712RC 3.3 Mechanical package drawings GND GND VDD VDD GND GND VDDIO VDDIO Figure 24. Top view Table 32. Dimensions Millimeters Min. Max. A Total height --- 3.50 A1 Body height --- 2.75 0.10 0.40 A2 b Lead width 0.15 0.25 c Lead height 0.10 0.20 D/E 74.80 75.40 D1/E1 55.44 56.56 D2/E2 31.75 32.25 D3/E3 29.50 BSC D4/E4 21.00 TYP e Lead pitch 0.50 BSC L1 16.50 TYP Note 1: The seal ring and the lid are connected to GND. Note 2: Package weight is 16 +/-1 grams, including the lead-frame. GR712RC-DS, Jan 2016, Version 2.3 41 www.cobham.com/gaisler GR712RC Figure 25. Capacitor pads on top of package (mm) GR712RC-DS, Jan 2016, Version 2.3 42 www.cobham.com/gaisler GR712RC 4 Reference documents [UM] GR712RC Dual-Core LEON3-FT SPARC V8 Processor - User's Manual, Cobham Gaisler, www.cobham.com/gaisler [PS] Product Specification GR712RC, GR712RC-PS, Cobham Gaisler [SPARC] The SPARC Architecture Manual, Version 8, Revision SAV080SI9308, SPARC International Inc. [SPW] ECSS - Space Engineering, SpaceWire - Links, Nodes, Routers and Networks, ECSS-E-ST-50-12C, 31 July 2008 [RMAPID] ECSS - Space Engineering, SpaceWire Protocol Identification, ECSS-E-ST-50-51C, February 2010 [RMAP] ECSS - Space Engineering, Remote Memory Access Protocol, ECSS-E-ST-50-52C, February 2010 [1553BRM] Core1553BRM Product Handbook, 50200040-0/11-04, November 2004, Actel Corporation Core1553BRM MIL-STD-1553 BC, RT, and MT, 51700052-4/12.05, v 5.0, December 2005, Actel Corporation Core1553BRM User's Guide, 50200023-0/06.04, June 2004, Actel Corporation Core1553BRM v2.16 Release Notes, 51300019-8/6.06, June 2006, Actel Corporation [MIL883] Test Method Standard, Microcircuits, revision H, 26 February 2010, MIL-STD-883H [MIL38535] Integrated Circuits (Microcircuits) Manufacturing, General Specification For, revision J, 28 December 2010, MIL-PRF-38535J GR712RC-DS, Jan 2016, Version 2.3 43 www.cobham.com/gaisler GR712RC 5 Screening, qualification, and quality control GR712RC is provided as a high reliability product for space, for which space level screening and qualifications tests are performed in accordance to the product specification [PS]. A Certificate of Compliance is delivered with space grade parts. A procurement specification is provided for space grade parts. GR712RC is also provided in prototype grade in military or commercial temperature range. 6 Ordering information Ordering information is provided in table 33 and a legend is provided in table 34. Table 33. Ordering information, available models Product Description GR712RC-MS-CQ240 Flight model GR712RC-MP-CQ240 Electrical qualification model GR712RC-CP-CQ240 Engineering model (prototype) Note: The -CQ240 affix was previously -CG240. There is however no change to the package. The product and qualification state is the same. Table 34. Ordering legend Designator Option Description Product GR712RC Dual-core LEON3-FT SPARC V8 Processor Temperature Range M -55°C to +125°C (Military range) C 0°C to +70°C (Commercial range) S Space grade P Prototype grade Package Type CQ Ceramic Quad Flat Pack (CQFP) 1) Lead Count 240 Number of leads Screening Level Note 1: Gold lead finish 7 Change record Change record information is provided in table 35. Table 35. Change record Issue Date Sections Note 2.3 2016 Jan None Updated text in footer. No other changes. Change bars preserved from version 2.2. 2.2 2015 Nov 1.2 Maximum size and bank size for PROM, SRAM and SDRAM 3.2 Point to ERRORN description in [UM] GR712RC-DS, Jan 2016, Version 2.3 44 www.cobham.com/gaisler GR712RC Table 35. Change record Issue Date 2.1 2014 June Sections Note 1.2 Key features: TID up to 300 krad(Si) 2.3 Updated DC electrical performance characteristics 2.4.4 Table 16 note 1 updated 2.4.6 Table 18 note 1 updated 2.4.7 Table 19 note 1 updated 2.4.8 Table 20 note 1 updated 2.4.11 Table 23 note 1 and parameter note updated 3.2 Max load changed to drive capability in Table 31 OEN pin output drive capability specified 2.0 3.3 Table 32 note 1 updated 6 Part numbering updated with new affix for the package identification 2013 February 1.2 Key features updated 1.4 Signal descriptions clarified 2.1 Absolute maximum ratings updated 2.2 Recommended operating conditions updated 2.3 DC parameters updated 2.4 AC parameter test conditions clarified 2.4.1, 2.4.3, 2.4.4, 2.4.5, 2.4.6, Updated timing 2.4.7, 2.4.8, 2.4.9, 2.4.10, 2.4.11, 2.4.13, 2.4.15, 2.4.19 1.5, 2.4.12 Obsolete proprietary function removed 3.1 Package marking clarified 3.2 GNDIO connection to GND clarified 3.3 Weight information added 4 Reference to product specification added 1.5 2012 May 1.5 The following conflicts added to table: CCSDS TC 0 vs. Proprietary CCSDS TC 0 vs. ASCS CCSDS TC 1 vs. Proprietary CCSDS TC 1 vs. Ethernet CCSDS TC 2 vs. Ethernet Proprietary vs. SpaceWire 2 1.4 2012 January 2.4.5 TCK edges in JTAG waveform & timing parameters corrected 1.3 2011 March 1.2, 2 4, 5 Table 6 Timing parameters redefined Qualification level specified Conflict between SLINK and CCSDS TC 3 clarified 1.2 2011 August 2.3 Added detailed core power consumption 1.1 2011 February Tables 3 and 5 Tables 3, 4 and 19, figure 19 Table 31 SDDQM signals marked as active high GPIO1/GPIO2 names changed to GPIO Reference added regarding behavior at reset 1.0 2011 February All New document layout All pin descriptions, reset values etc. updated GR712RC-DS, Jan 2016, Version 2.3 45 www.cobham.com/gaisler GR712RC Cobham Gaisler AB Kungsgatan 12 411 19 Göteborg Sweden www.cobham.com/gaisler [email protected] T: +46 31 7758650 F: +46 31 421407 Cobham Gaisler AB, reserves the right to make changes to any products and services described herein at any time without notice. Consult Cobham or an authorized sales representative to verify that the information in this document is current before using this product. Cobham does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Cobham; nor does the purchase, lease, or use of a product or service from Cobham convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Cobham or of third parties. All information is provided as is. There is no warranty that it is correct or suitable for any purpose, neither implicit nor explicit. Copyright © 2016 Cobham Gaisler AB GR712RC-DS, Jan 2016, Version 2.3 46 of 46 www.cobham.com/gaisler