8-Channel DAC with PLL and Differential Outputs, 192 kHz, 24 Bits AD1933 Data Sheet FEATURES GENERAL DESCRIPTION PLL generated or direct master clock Low EMI design DAC with 110 dB dynamic range and SNR −96 dB THD + N 3.3 V single supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Differential DAC output Log volume control with autoramp function SPI® controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I2S, and TDM modes Master and slave modes up to 16-channel input/output 64-lead LQFP Qualified for automotive applications The AD1933 is a high performance, single chip that provides eight digital-to-analog converters (DACs) with differential output using the Analog Devices, Inc., patented multibit sigmadelta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1933 operates from 3.3 V digital and analog supplies. The AD1933 is available in a 64-lead (differential output) LQFP. Other members of this family include a single-ended DAC output version. The AD1933 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1933 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions. APPLICATIONS Automotive audio systems Home Theater Systems Set-top boxes Digital audio effects processors FUNCTIONAL BLOCK DIAGRAM AD1933 DAC DAC DAC DIGITAL AUDIO INPUT/OUTPUT SERIAL DATA PORT CLOCKS SDATAIN TIMING MANAGEMENT AND CONTROL (CLOCK AND PULL) DIGITAL FILTER AND VOLUME CONTROL DAC DAC ANALOG AUDIO OUTPUTS DAC DAC PRECISION VOLTAGE REFERENCE DAC CONTROL PORT SPI CONTROL DATA INPUT/OUTPUT 06624-001 6.144MHz Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com AD1933 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital-to-Analog Converters (DACs) .................................... 11 Applications ....................................................................................... 1 Clock Signals ............................................................................... 11 General Description ......................................................................... 1 Reset and Power-Down ............................................................. 11 Functional Block Diagram .............................................................. 1 Serial Control Port ..................................................................... 12 Revision History ............................................................................... 2 Power Supply and Voltage Reference....................................... 13 Specifications..................................................................................... 3 Serial Data Ports—Data Format ............................................... 13 Test Conditions ............................................................................. 3 Time-Division Multiplexed (TDM) Modes ............................ 13 Analog Performance Specifications ........................................... 3 Daisy-Chain Mode ..................................................................... 15 Crystal Oscillator Specifications................................................. 4 Control Registers ............................................................................ 19 Digital Input/Output Specifications........................................... 4 Definitions ................................................................................... 19 Power Supply Specifications........................................................ 5 PLL and Clock Control Registers ............................................. 19 Digital Filters ................................................................................. 5 DAC Control Registers .............................................................. 20 Timing Specifications .................................................................. 6 Auxiliary TDM Port Control Registers ................................... 22 Absolute Maximum Ratings ............................................................ 7 Additional Modes ....................................................................... 23 Thermal Resistance ...................................................................... 7 Application Circuits ....................................................................... 24 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 25 Pin Configuration and Function Descriptions ............................. 8 Ordering Guide .......................................................................... 25 Typical Performance Characteristics ........................................... 10 Automotive Products ................................................................. 25 Theory of Operation ...................................................................... 11 REVISION HISTORY 2/13—Rev. D to Rev. E 1/11—Rev. A to Rev. B Changes to tCLH Comments, Table 7 ............................................... 6 Changes to Serial Control Port Section ....................................... 12 Changes to Features ..........................................................................1 Change to Table Summary, Table 2 and Table Summary, Table 4 ....................................................................4 Changes to Table Summary, Table 7 ...............................................6 10/11—Rev. C to Rev. D Changes to Pin 14 in Figure 2 and Table 10 .................................. 8 Changes to Ordering Guide .......................................................... 25 Added Automotive Products Section........................................... 25 7/11—Rev. B to Rev. C Deleted Reference to I2C ............................................... Throughout Changes to Table 10, DSDATAx/AUXDATA1 Pin Descriptions ...................................................................................... 8 9/09—Rev. 0 to Rev. A Change to Title ...................................................................................1 Change to Table 10 ............................................................................9 Change to Power Supply and Voltage Reference Section .......... 13 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 10/07—Revision 0: Initial Version Rev. E | Page 2 of 28 Data Sheet AD1933 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages (AVDD, DVDD) Temperature range 1 Master clock Input sample rate Measurement bandwidth Word width Load capacitance (digital output) Load current (digital output) Input voltage high Input voltage low 1 3.3 V As specified in Table 1 and Table 2 12.288 MHz (48 kHz fS, 256 × fS mode) 48 kHz 20 Hz to 20 kHz 24 bits 20 pF ±1 mA or 1.5 kΩ to ½ DVDD supply 2.0 V 0.8 V Functionally guaranteed at −40°C to +125°C case temperature. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at an ambient temperature of 25°C. Table 1. Parameter DIGITAL-TO-ANALOG CONVERTERS Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) With A-Weighted Filter (Avg) Total Harmonic Distortion + Noise Differential Version Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output REGULATOR Input Supply Voltage Regulated Supply Voltage Test Conditions/Comments Min Typ 102 105 107 110 112 Max Unit 20 Hz to 20 kHz, −60 dB input 0 dBFS Two channels running Eight channels running −96 −86 1.76 (4.96) −10 −0.2 −25 −30 −6 dB dB dB −76 +10 +0.2 +25 +30 100 0 0.375 95 ±0.6 100 dB dB V rms (V p-p) % dB mV ppm/°C dB Degrees dB dB dB Ω FILTR pin FILTR pin CM pin 1.32 1.50 1.50 1.50 1.68 V V V VSUPPLY pin VSENSE pin 4.5 3.19 5.0 3.37 5.5 3.55 V V Rev. E | Page 3 of 28 AD1933 Data Sheet Specifications measured at a case temperature of 125°C. Table 2. Parameter DIGITAL-TO-ANALOG CONVERTERS Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) With A-Weighted Filter (Average) Total Harmonic Distortion + Noise Differential Version Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output REGULATOR Input Supply Voltage Regulated Supply Voltage Test Conditions/Comments Min Typ 101 104 107 110 112 Max Unit 20 Hz to 20 kHz, −60 dB input 0 dBFS Two channels running Eight channels running −94 −86 1.76 (4.96) −10 −0.2 −25 −30 −6 dB dB dB −70 +10 +0.2 +25 +30 dB dB V rms (V p-p) % dB mV ppm/°C FILTR pin FILTR pin CM pin 1.32 1.50 1.50 1.50 1.68 V V V VSUPPLY pin VSENSE pin 4.5 3.2 5.0 3.43 5.5 3.65 V V Max Unit mmhos Max Unit V V V µA µA V V pF CRYSTAL OSCILLATOR SPECIFICATIONS Table 3. Parameter Transconductance Min Typ 3.5 DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < TC < +125°C, DVDD = 3.3 V ± 10%. Table 4. Parameter High Level Input Voltage (VIH) High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Leakage High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Input Capacitance Test Conditions/Comments MCLKI/XI pin IIH @ VIH = 2.4 V IIL @ VIL = 0.8 V IOH = 1 mA IOL = 1 mA Rev. E | Page 4 of 28 Min 2.0 2.2 Typ 0.8 10 10 DVDD − 0.60 0.4 5 Data Sheet AD1933 POWER SUPPLY SPECIFICATIONS Table 5. Parameter SUPPLIES Voltage Digital Current Normal Operation Power-Down Analog Current Normal Operation Power-Down DISSIPATION Operation All Supplies Digital Supply Analog Supply Power-Down, All Supplies POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins Test Conditions/Comments Min Typ Max Unit DVDD AVDD VSUPPLY Master clock = 256 fS fS = 48 kHz fS = 96 kHz fS = 192 kHz fS = 48 kHz to 192 kHz 3.0 3.0 4.5 3.3 3.3 5.0 3.6 3.6 5.5 V V V 56 65 95 2.0 mA mA mA mA 74 23 mA mA 429 185 244 83 mW mW mW mW 50 50 dB dB Master clock = 256 fS, 48 kHz 1 kHz, 200 mV p-p 20 kHz, 200 mV p-p DIGITAL FILTERS Table 6. Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode Factor Min 48 kHz mode, typical @ 48 kHz 96 kHz mode, typical @ 96 kHz 192 kHz mode, typical @ 192 kHz 48 kHz mode, typical @ 48 kHz 96 kHz mode, typical @ 96 kHz 192 kHz mode, typical @ 192 kHz 48 kHz mode, typical @ 48 kHz 96 kHz mode, typical @ 96 kHz 192 kHz mode, typical @ 192 kHz 48 kHz mode, typical @ 48 kHz 96 kHz mode, typical @ 96 kHz 192 kHz mode, typical @ 192 kHz 48 kHz mode, typical @ 48 kHz 96 kHz mode, typical @ 96 kHz 192 kHz mode, typical @ 192 kHz 48 kHz mode, typical @ 48 kHz 96 kHz mode, typical @ 96 kHz 192 kHz mode, typical @ 192 kHz 0.4535 fS 0.3646 fS 0.3646 fS 35 Rev. E | Page 5 of 28 Typ Max 22 70 ±0.01 ±0.05 ±0.1 0.5 fS 0.5 fS 0.5 fS 0.5465 fS 0.6354 fS 0.6354 fS 24 48 96 26 61 122 70 70 70 25/fS 11/fS 8/fS 521 115 42 Unit kHz kHz kHz dB dB dB kHz kHz kHz kHz kHz kHz dB dB dB µs µs µs AD1933 Data Sheet TIMING SPECIFICATIONS −40°C < TC < +125°C, DVDD = 3.3 V ± 10%. Table 7. Parameter INPUT MASTER CLOCK (MCLK) AND RESET tMH Condition Comments Min Max Unit MCLK duty cycle DAC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, and 768 fS DAC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) PLL mode, 256 fS reference Direct 512 fS mode 40 60 % 40 60 % 6.9 13.8 27.6 MHz MHz ns tMCLK 10 60 ms % tMH fMCLK fMCLK tPDR tPDRR PLL Lock Time 256 fS VCO Clock, Output Duty Cycle MCLKO/XO Pin SPI PORT tCCH tCCL fCCLK tCDS tCDH tCLS tCLH tCLHIGH tCOE tCOD tCOH tCOTS DAC SERIAL PORT tDBH tDBL tDLS tDLH tDLS tDDS tDDH AUXTDM SERIAL PORT tABH tABL tALS tALH tALS tDDS tDDH AUXILIARY INTERFACE tDXDD tXBH tXBL tDLS tDLH MCLK frequency RST low RST recovery Reset to active output 15 4096 MCLK and LR clock input 40 See Figure 9 CCLK high CCLK low CCLK frequency CIN setup CIN hold CLATCH setup CLATCH hold CLATCH high COUT enable COUT delay COUT hold COUT tristate 35 35 DBCLK high DBCLK low DLRCLK setup DLRCLK hold DLRCLK skew DSDATA setup DSDATA hold AUXTDMBCLK high AUXTDMBCLK low AUXTDMLRCLK setup AUXTDMLRCLK hold AUXTDMLRCLK skew DSDATA setup DSDATA hold AUXDATA delay AUXBCLK high AUXBCLK low AUXLRCLK setup AUXLRCLK hold fCCLK = 1/tCCP, only tCCP shown in Figure 9 To CCLK rising From CCLK rising To CCLK rising From CCLK rising Not shown in Figure 9 From CCLK falling From CCLK falling From CCLK falling, not shown in Figure 9 From CCLK falling See Figure 16 Slave mode Slave mode To DBCLK rising, slave mode From DBCLK rising, slave mode From DBCLK falling, master mode To DBCLK rising From DBCLK rising See Figure 17 Slave mode Slave mode To AUXTDMBCLK rising, slave mode From AUXTDMBCLK rising, slave mode From AUXTDMBCLK falling, master mode To AUXTDMBCLK, not shown in Figure 17 From AUXTDMBCLK rising, not shown in Figure 17 10 10 10 10 10 10 30 30 30 30 10 10 10 5 −8 10 5 10 10 10 5 −8 10 5 From AUXBCLK falling To AUXBCLK rising From AUXBCLK rising Rev. E | Page 6 of 28 +8 +8 18 10 10 10 5 ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet AD1933 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Analog (AVDD) Digital (DVDD) VSUPPLY Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +6.0 V ±20 mA −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −40°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA represents thermal resistance, junction-to-ambient; θJC represents thermal resistance, junction-to-case. All characteristics are for a 4-layer board. Table 9. Thermal Resistance Package Type 64-Lead LQFP ESD CAUTION Rev. E | Page 7 of 28 θJA 47 θJC 11.1 Unit °C/W AD1933 Data Sheet NC AVDD LF NC NC NC NC NC NC NC NC CM AVDD NC NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 48 AGND MCLKI/XI 2 47 FILTR MCLKO/XO 3 46 AGND AGND 4 45 AVDD AVDD 5 44 AGND OL3P 6 43 OR2N OL3N 7 AD1933 42 OR2P OR3P 8 OL2N OR3N TOP VIEW (Not to Scale) 41 9 40 OL2P OL4P 10 39 OR1N OL4N 11 38 OR1P OR4P 12 37 OL1N OR4N 13 36 OL1P DIFFERENTIAL OUTPUT 23 24 25 26 27 28 29 30 31 32 AUXTDMBCLK AUXTDMLRCLK CIN COUT DVDD NC = NO CONNECT 22 NC 21 VDRIVE 20 AUXDATA1 19 VSENSE 18 DLRCLK 17 VSUPPLY DGND DBCLK 33 DSDATA1 CCLK DGND 16 DSDATA2 CLATCH 34 DVDD 35 DSDATA3 RST 14 DSDATA4 15 06624-002 NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input/Output I I O I I O O O O O O O O I I/O Mnemonic AGND MCLKI/XI MCLKO/XO AGND AVDD OL3P OL3N OR3P OR3N OL4P OL4N OR4P OR4N RST DSDATA4 16 17 18 I I I/O DGND DVDD DSDATA3 19 20 21 22 I/O I I/O I/O DSDATA2 DSDATA1 DBCLK DLRCLK Description Analog Ground. Master Clock Input/Crystal Oscillator Input. Master Clock Output/Crystal Oscillator Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. DAC 3 Left Positive Output. DAC 3 Left Negative Output. DAC 3 Right Positive Output. DAC 3 Right Negative Output. DAC 4 Left Positive Output. DAC 4 Left Negative Output. DAC 4 Right Positive Output. DAC 4 Right Negative Output. Reset (Active Low). DACSerial Data Input 4. Input to DAC4 data in/TDM DAC2 data out (dual-line mode)/AUX DAC2 data out (to external DAC2). Digital Ground. Digital Power Supply. Connect to digital 3.3 V supply. DAC Serial Data Input 3. Data input to DAC3 in/TDM DAC2 data in (dual-line mode)/AUX not used. DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX not used. DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/AUX TDM data in. Bit Clock for DACs. Regular stereo, TDM, or daisy-chain TDM mode. LR Clock for DACs. Regular stereo, TDM, or daisy-chain TDM mode. Rev. E | Page 8 of 28 Data Sheet AD1933 Pin No. 23 24 25 26 27, 49, 50, 63, 64 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 51 52 Input/Output I I O O Mnemonic VSUPPLY VSENSE VDRIVE AUXDATA1 NC Description 5 V Input to Regulator, Emitter of Pass Transistor. 3.3 V Output of Regulator, Collector of Pass Transistor. Drive for Base of Pass Transistor. AUX DAC1 data out (to external DAC1). No Connect. I/O I/O I I/O I I I I O O O O O O O O I I I O I I O AUXTDMBCLK AUXTDMLRCLK CIN COUT DVDD DGND CCLK CLATCH OL1P OL1N OR1P OR1N OL2P OL2N OR2P OR2N AGND AVDD AGND FILTR AGND AVDD CM 53 to 60 61 62 I O I NC LF AVDD Auxiliary Mode Only DAC TDM Bit Clock. Auxiliary Mode Only DAC LR TDM Clock. Control Data Input (SPI). Control Data Output (SPI). Digital Power Supply. Connect to digital 3.3 V supply. Digital Ground. Control Clock Input (SPI). Latch Input for Control Data (SPI). DAC 1 Left Positive Output. DAC 1 Left Negative Output. DAC 1 Right Positive Output. DAC 1 Right Negative Output. DAC 2 Left Positive Output. DAC 2 Left Negative Output. DAC 2 Right Positive Output. DAC 2 Right Negative Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Analog Ground. Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Common-Mode Reference Filter Capacitor Connection. Bypass with 47 µF||100 nF to AGND. Must Be Tied to Common Mode, Pin 52. Alternately, ac-couple these pins to ground. PLL Loop Filter, Return to AVDD. Analog Power Supply. Connect to analog 3.3 V supply. Rev. E | Page 9 of 28 AD1933 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.06 0 MAGNITUDE (dB) MAGNITUDE (dB) 0.04 0.02 0 –0.02 –50 –100 0 8 16 24 FREQUENCY (kHz) 06624-003 –150 –0.06 0 24 48 72 96 FREQUENCY (kHz) 06624-006 –0.04 Figure 6. DAC Stop-Band Filter Response, 96 kHz Figure 3. DAC Pass-Band Filter Response, 48 kHz 0.5 0 0.4 0.2 MAGNITUDE (dB) MAGNITUDE (dB) 0.3 –50 –100 0.1 0 –0.1 –0.2 –0.3 12 24 36 48 FREQUENCY (kHz) –0.5 0 8 32 16 06624-007 0 06624-004 –0.4 –150 64 FREQUENCY (kHz) Figure 4. DAC Stop-Band Filter Response, 48 kHz Figure 7. DAC Pass-Band Filter Response, 192 kHz 0.10 0 MAGNITUDE (dB) –2 0 –4 –6 –0.05 –0.10 0 24 48 72 FREQUENCY (kHz) 96 Figure 5. DAC Pass-Band Filter Response, 96 kHz –10 48 64 80 FREQUENCY (kHz) Figure 8. DAC Stop-Band Filter Response, 192 kHz Rev. E | Page 10 of 28 96 06624-008 –8 06624-005 MAGNITUDE (dB) 0.05 Data Sheet AD1933 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS (DACs) The AD1933 DAC channels are arranged as differential, four stereo pairs giving eight analog outputs for minimum external components. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode). Each channel has its own independently programmable attenuator, adjustable in 255 steps in increments of 0.375 dB. Digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame clock (DLRCLK) and bit clock (DBCLK). Alternatively, one of the TDM modes can be used to access up to 16 channels on a single TDM data line. Each output pin has a nominal common-mode dc level of 1.5 V and swings ±1.27 V for a 0 dBFS digital input signal. A thirdorder, external, low-pass filter is recommended to remove high frequency noise present on the output pins. The use of op amps with low slew rates or low bandwidths can cause high frequency noise and tones to fold down into the audio band; therefore, exercise care in selecting these components. The voltage at CM, the common-mode reference pin, can be used to bias the external op amps that buffer the output signals (see the Power Supply and Voltage Reference section). CLOCK SIGNALS The on-chip, phase-locked loop (PLL) can be selected to reference the input sample rate from either of the LRCLK pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 kHz mode from the MCLKI/XI pin. The default at power-up is 256 × fS from MCLKI/XI pin. In 96 kHz mode, the master clock frequency stays at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. In 192 kHz mode, the actual multiplication rate is divided by 4. For example, if a device in the AD1933 family is programmed in 256 × fS mode, the frequency of the master clock input is 256 × 48 kHz = 12.288 MHz. If the AD1933 is then switched to 96 kHz operation (by writing to the SPI port), the frequency of the master clock should remain at 12.288 MHz, which becomes 128 × fS. In 192 kHz mode, this becomes 64 × fS. The PLL can be powered down in the PLL and Clock Control 0 register. To ensure reliable locking when changing PLL modes, or if the reference clock is unstable at power-on, power down the PLL and power it back up when the reference clock has stabilized. The internal master clock can be disabled in the PLL and Clock Control 0 register to reduce power dissipation when the AD1933 is idle. The clock should be stable before it is enabled. Unless a standalone mode is selected (see the Serial Control Port section), the clock is disabled by reset and must be enabled by writing to the SPI port for normal operation. To maintain the highest performance possible, limit the clock jitter of the internal master clock signal to less than a 300 ps rms time interval error (TIE). Even at these levels, extra noise or tones can appear in the DAC outputs if the jitter spectrum contains large spectral peaks. If the internal PLL is not used, it is highly recommended that an independent crystal oscillator generate the master clock. In addition, it is especially important that the clock signal not be passed through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD1933. In most cases, this induces clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. When the PLL is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. RESET AND POWER-DOWN The function of the RST pin sets all the control registers to their default settings. To avoid pops, reset does not power down the analog outputs. After RST is deasserted, and the PLL acquires lock condition, an initialization routine runs inside the AD1933. This initialization lasts for approximately 256 master clock cycles. The power-down bits in the PLL and Clock Control 0 and DAC Control 1 registers power down the respective sections. All other register settings are retained. To guarantee proper startup, the RST pin should be pulled low by an external resistor. The internal clock for the DACs varies by mode: 512 × fS (48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By default, the on-board PLL generates this internal master clock from an external clock. A direct 512 × fS (referenced to 48 kHz mode) master clock can be used for DACs if selected in the PLL and Clock Control 1 register. Rev. E | Page 11 of 28 AD1933 Data Sheet SERIAL CONTROL PORT The AD1933 has an SPI control port that permits programming and reading back of the internal control registers for the ADCs, DACs, and clock system. A standalone mode is also available for operation without serial control; standalone is configured at reset by connecting CIN, CCLK, and CLATCH to ground. In standalone mode, all registers are set to default, except the internal MCLK enable, which is set to 1. The ADC ABCLK and ALRCLK clock ports are set to master/slave by the connecting the COUT pin to either DVDD or ground. Standalone mode only supports stereo mode with an I2S data format and 256 fS MCLK rate. Refer to Table 11 for details. If CIN, CCLK, and CLATCH are not grounded, the AD1933 SPI port is active. It is recommended to use a weak pull-up resistor on CLATCH in applications that have a microcontroller. This pull-up resistor ensures that the AD1933 recognizes the presence of a microcontroller. The SPI control port of the AD1933 is a 4-wire serial control port. The format is similar to the Motorola SPI format except the input data-word is 24 bits wide. The serial bit clock and latch can be completely asynchronous to the sample rate of the DACs. Figure 9 shows the format of the SPI signal. The first byte is a global address with a read/write bit. For the AD1933, the address is 0x04, shifted left 1 bit due to the R/W bit. The second byte is the AD1933 register address and the third byte is the data. tCLS tCCH tCCL tCCP CLATCH tCLH tCOTS CCLK tCDS tCDH COUT D23 D22 D9 tCOE D9 D8 D0 D8 D0 06624-009 CIN tCOD Figure 9. Format of SPI Signal Rev. E | Page 12 of 28 Data Sheet AD1933 POWER SUPPLY AND VOLTAGE REFERENCE The AD1933 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 μF should also be provided on the same PCB as the DAC. For critical applications, improved performance is obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by means of a ferrite bead in series with each supply. It is important that the analog supply be as clean as possible. applications requiring more than eight DAC channels. In this mode, the AUXTDMLRCLK and AUXTDMBCLK pins are configured as TDM port clocks. In regular TDM mode, the DLRCLK and DBCLK pins are used as the TDM port clocks. The auxiliary TDM serial port format and its serial clock polarity are programmable according to the Auxiliary TDM Port Control 0 register and the Auxiliary TDM Port Control 1 register. Both DAC and auxiliary TDM serial ports are programmable to become the bus masters according to the DAC Control 1 register and auxiliary TDM Control 1 register. By default, both auxiliary TDM and DAC serial ports are in slave mode. The AD1933 includes a 3.3 V regulator driver that only requires an external pass transistor and bypass capacitors to make a 5 V to 3.3 V regulator. If the regulator driver is not used, connect VSUPPLY, VDRIVE, and VSENSE to DGND. TIME-DIVISION MULTIPLEXED (TDM) MODES The DAC internal voltage reference (VREF) is brought out on FILTR and should be bypassed as close as possible to the chip, with a parallel combination of 10 μF and 100 nF. Any external current drawn should be limited to less than 50 μA. The internal reference can be disabled in the PLL and Clock Control 1 register and FILTR can be driven from an external source. This can be used to scale the DAC output to the clipping level of a power amplifier based on its power supply voltage, DAC output gain is proportional to the FILTR voltage. The CM pin is the internal common-mode reference. It should be bypassed as close as possible to the chip, with a parallel combination of 47 μF and 100 nF. This voltage can be used to bias external op amps to the common-mode voltage of the input and output signal pins. The output current should be limited to less than 0.5 mA source and 2 mA sink. SERIAL DATA PORTS—DATA FORMAT The eight DAC channels use a common serial bit clock (DBCLK) and a common left-right framing clock (DLRCLK) in the serial data port. The clock signals are all synchronous with the sample rate. The normal stereo serial modes are shown in Figure 15. The DAC serial data modes default to I2S. The ports can also be programmed for left-justified, right-justified, and TDM modes. The word width is 24 bits by default and can be programmed for 16 or 20 bits. The DAC serial formats are programmable according to the DAC Control 0 register. The polarity of the DBCLK and DLRCLK is programmable according to the DAC Control 1 register. The auxiliary TDM port is also provided for The I/O pins of the serial ports are defined according to the serial mode selected. For a detailed description of the function of each pin in TDM and auxiliary modes, see Table 11. The AD1933 allows systems with more than eight DAC channels to be easily configured by the use of an auxiliary serial data port. The DAC TDM-AUX mode is shown in Figure 11. In this mode, the AUX channels are the last four slots of the 16-channel TDM data stream. These slots are extracted and output to the AUX serial port. One major difference between the TDM mode and an auxiliary TDM mode is the assignment of the TDM port pins, as shown in Table 11. In auxiliary TDM mode, DBCLK and DLRCLK are assigned as the auxiliary port clocks, and AUXTDMBCLK and AUXTDMLRCLK are assigned as the TDM port clocks. In regular TDM or 16-channel, daisy-chain TDM mode, the DLRCLK and DBCLK pins are set as the TDM port clocks. It should be noted that due to the high AUXTDMBCLK frequency, 16-channel auxiliary TDM mode is available only in the 48 kHz/44.1 kHz/32 kHz sample rate. LRCLK 256 BCLKs BCLK 32 BCLK DATA Rev. E | Page 13 of 28 SLOT 1 LEFT 1 SLOT 2 RIGHT 1 SLOT 3 LEFT 2 SLOT 4 RIGHT 2 SLOT 5 LEFT 3 SLOT 6 RIGHT 3 SLOT 7 LEFT 4 SLOT 8 RIGHT 4 LRCLK BCLK MSB MSB–1 MSB–2 DATA Figure 10. DAC TDM (8-Channel I2S Mode) 06624-010 All digital inputs are compatible with TTL and CMOS levels. All outputs are driven from the 3.3 V DVDD supply and are compatible with TTL and 3.3 V CMOS levels. The AD1933 serial ports have several different TDM serial data modes. The most commonly used configuration is shown in Figure 10. In Figure 10, the eight on-chip DAC data slots are packed into one TDM stream. In this mode, DBCLK is 256 fS. AD1933 Data Sheet Table 11. Pin Function Changes in TDM-AUX Mode Pin Name AUXDATA1 DSDATA1 DSDATA2 DSDATA3 DSDATA4 AUXTDMLRCLK AUXTDMBCLK DLRCLK DBCLK Stereo Modes Not Used (Float) DAC 1 Data In DAC 2 Data In DAC 3 Data In DAC 4 Data In Not Used (Ground) Not Used (Ground) DAC LRCLK In/DAC LRCLK Out DAC BCLK In/DAC BCLK Out TDM Modes Not Used (Float) DAC TDM Data In DAC TDM Data Out DAC TDM Data In 2 (Dual-Line Mode) DAC TDM Data Out 2 (Dual-Line Mode) Not Used (Ground) Not Used (Ground) DAC TDM Frame Sync In/DAC TDM Frame Sync Out DAC TDM BCLK In/DAC TDM BCLK Out AUX Modes AUX Data Out 1 (to External DAC 1) TDM Data In Not Used (Ground) Not Used (Ground) AUX Data Out 2 (to External DAC 2) TDM Frame Sync In/TDM Frame Sync Out TDM BCLK In/TDM BCLK Out AUX LRCLK In/AUX LRCLK Out AUX BCLK In/AUX BCLK Out AUXTDMLRCLK AUXTDMBCLK UNUSED SLOTS DSDATA1 (TDM_IN) EMPTY EMPTY EMPTY AUXILIARY DAC CHANNELS WILL APPEAR AT AUX DAC PORTS 8-ON-CHIP DAC CHANNELS EMPTY DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2 32 BITS MSB DLRCLK (AUX PORT) LEFT RIGHT DBCLK (AUX PORT) MSB DSDATA4 (AUX2_OUT) MSB MSB MSB Figure 11. 16-Channel DAC TDM-AUX Mode Rev. E | Page 14 of 28 06624-011 AUXDATA1 (AUX1_OUT) Data Sheet AD1933 DAISY-CHAIN MODE Again, the first four channels of each TDM input belong to the first AD1933 in the chain and the last four channels belong to the second AD1933. The AD1933 also allows a daisy-chain configuration to expand the system 16 DACs (see Figure 12). In this mode, the DBCLK frequency is 512 fS. The first eight slots of the DAC TDM data stream belong to the first AD1933 in the chain and the last eight slots belong to the second AD1933. The second AD1933 is the device attached to the DSP TDM port. The dual-line, DAC TDM mode can also be used to send data at a 192 kHz sample rate into the AD1933, as shown in Figure 14. The I/O pins of the serial ports are defined according to the serial mode selected. See Table 12 for a detailed description of the function of each pin. See Figure 18 for a typical AD1933 configuration with two external stereo DACs. Figure 15 and Figure 16 show the serial mode formats. For maximum flexibility, the polarity of LRCLK and BCLK are programmable. In these figures, all of the clocks are shown with their normal polarity. The default mode is I2S. To accommodate 16 channels at a 96 kHz sample rate, the AD1933 can be configured into a dual-line, DAC TDM mode, as shown in Figure 13. This mode allows a slower DBCLK than normally required by the one-line TDM mode. DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 (TDM_IN) OF THE SECOND AD1933 DAC L1 DAC R1 DAC L2 DSDATA2 (TDM_OUT) OF THE SECOND AD1933 THIS IS THE TDM TO THE FIRST AD1933 DAC R2 DAC L3 DAC R3 DAC L4 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 8 UNUSED SLOTS FIRST AD1933 SECOND AD1933 DSP 06624-012 32 BITS MSB Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1933 Daisy Chain) DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 (IN) DAC L1 DAC R1 DAC L2 DAC R2 DSDATA2 (OUT) DSDATA3 (IN) DAC L3 DAC R3 DSDATA4 (OUT) DAC L4 DAC R4 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4 32 BITS FIRST AD1933 SECOND AD1933 06624-013 MSB DSP Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1933 Daisy Chain; DSDATA3 and DSDATA4 Are the Daisy Chain) Rev. E | Page 15 of 28 AD1933 Data Sheet DLRCLK DBCLK DSDATA1 DAC L1 DAC R1 DAC L2 DAC R2 DSDATA2 DAC L3 DAC R3 DAC L4 DAC R4 06624-014 32 BITS MSB Figure 14. Dual-Line, DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode) LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK SDATA LSB MSB LSB MSB LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK SDATA LSB MSB LSB MSB I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK SDATA MSB LSB MSB LSB RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK MSB MSB LSB LSB DSP MODE—16 BITS TO 24 BITS PER CHANNEL 1/fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS. 3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE. Figure 15. Stereo Serial Modes Rev. E | Page 16 of 28 06624-015 SDATA Data Sheet AD1933 tDBH DBCLK tDBL tDLH tDLS DLRCLK tDDS DSDATA LEFT-JUSTIFIED MODE MSB MSB–1 tDDH tDDS DSDATA I2S-JUSTIFIED MODE MSB tDDH tDDS MSB LSB tDDH tDDH 06624-016 tDDS DSDATA RIGHT-JUSTIFIED MODE Figure 16. DAC Serial Timing tABH AUXTDMBCLK tABL tALH tALS AUXTDMLRCLK DSDATA1 I2S-JUSTIFIED MODE MSB MSB–1 MSB DSDATA1 RIGHT-JUSTIFIED MODE MSB Figure 17. AUXTDM Serial Timing Rev. E | Page 17 of 28 LSB 06624-017 DSDATA1 LEFT-JUSTIFIED MODE AD1933 Data Sheet Table 12. Pin Function Changes in TDM-AUX Mode (Replication of Table 11) Stereo Modes Not Used (Float) DAC 1 Data In DAC 2 Data In DAC 3 Data In DAC 4 Data In Not Used (Ground) Not Used (Ground) DAC LRCLK In/DAC LRCLK Out DAC BCLK In/DAC BCLK Out TDM Modes Not Used (Float) DAC TDM Data In DAC TDM Data Out DAC TDM Data In 2 (Dual-Line Mode) DAC TDM Data Out 2 (Dual-Line Mode) Not Used (Ground) Not Used (Ground) DAC TDM Frame Sync In/DAC TDM Frame Sync Out DAC TDM BCLK In/DAC TDM BCLK Out TxDATA TxCLK TFS (NC) SHARC RxCLK 12.288MHz AUX Modes AUX Data Out 1 (to External DAC 1) TDM Data In Not Used (Ground) Not Used (Ground) AUX Data Out 2 (to External DAC 2) TDM Frame Sync In/TDM Frame Sync Out TDM BCLK In/TDM BCLK Out AUX LRCLK In/AUX LRCLK Out AUX BCLK In/AUX BCLK Out SHARC IS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN) 30MHz FSYNC-TDM (RFS) LRCLK BCLK AUXTDMLRCLK AUXTDMBCLK DSDATA1 AUX DATA DAC 1 MCLK DBCLK DLRCLK AD1933 LRCLK DSDATA2 DSDATA3 TDM MASTER AUX MASTER AUXDATA1 DSDATA4 BCLK AUX DATA DAC 2 MCLK MCLKI/XI Figure 18. Example of AUX Mode Connection to SHARC® (AD1933 as TDM Master/AUX Master Shown) Rev. E | Page 18 of 28 06624-018 Pin Name AUXDATA1 DSDATA1 DSDATA2 DSDATA3 DSDATA4 AUXTDMLRCLK AUXTDMBCLK DLRCLK DBCLK Data Sheet AD1933 CONTROL REGISTERS DEFINITIONS The global address for the AD1933 is 0x04, shifted left 1 bit due to the R/W bit. All registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 13. Register Format Bit Global Address R/W Register Address Data 23:17 16 15:8 7:0 Table 14. Register Addresses and Functions Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function PLL and Clock Control 0 PLL and Clock Control 1 DAC Control 0 DAC Control 1 DAC Control 2 DAC individual channel mutes DAC L1 volume control DAC R1 volume control DAC L2 volume control DAC R2 volume control DAC L3 volume control DAC R3 volume control DAC L4 volume control DAC R4 volume control Reserved Auxiliary TDM Port Control 0 Auxiliary TDM Port Control 1 PLL AND CLOCK CONTROL REGISTERS Table 15. PLL and Clock Control 0 Bit 0 2:1 4:3 6:5 7 Value 0 1 00 01 10 11 00 01 10 11 00 01 10 11 0 1 Function Normal operation Power-down Input 256 (×44.1 kHz or 48 kHz) Input 384 (×44.1 kHz or 48 kHz) Input 512 (×44.1 kHz or 48 kHz) Input 768 (×44.1 kHz or 48 kHz) XTAL oscillator enabled 256 × fS VCO output 512 × fS VCO output Off MCLKI/XI DLRCLK AUXTDMLRCLK Reserved Disable: DAC idle Enable: DAC active Description PLL power-down MCLKI/XI pin functionality (PLL active), master clock rate setting MCLKO/XO pin, master clock rate setting PLL input Internal master clock enable Rev. E | Page 19 of 28 AD1933 Data Sheet Table 16. PLL and Clock Control 1 Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL clock MCLK PLL clock MCLK Enabled Disabled Not locked Locked Reserved Description DAC clock source select Clock source select On-chip voltage reference PLL lock indicator (read-only) DAC CONTROL REGISTERS Table 17. DAC Control 0 Bit 0 2:1 5:3 7:6 Value 0 1 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 Function Normal Power-down 32 kHz/44.1 kHz/48 kHz 64 kHz/88.2 kHz/96 kHz 128 kHz/176.4 kHz/192 kHz Reserved 1 0 8 12 16 Reserved Reserved Reserved Stereo (normal) TDM (daisy chain) DAC aux mode (DAC-, TDM-coupled) Dual-line TDM Description Power-down Sample rate SDATA delay (BCLK periods) Serial format Table 18. DAC Control 1 Bit 0 2:1 3 4 5 6 7 Value 0 1 00 01 10 11 0 1 0 1 0 1 0 1 0 1 Function Latch in midcycle (normal) Latch in at end of cycle (pipeline) 64 (2 channels) 128 (4 channels) 256 (8 channels) 512 (16 channels) Left low Left high Slave Master Slave Master DBCLK pin Internally generated Normal Inverted Description BCLK active edge (TDM in) BCLKs per frame LRCLK polarity LRCLK master/slave BCLK master/slave BCLK source BCLK polarity Rev. E | Page 20 of 28 Data Sheet AD1933 Table 19. DAC Control 2 Bit 0 2:1 4:3 5 7:6 Value 0 1 00 01 10 11 00 01 10 11 0 1 00 Function Unmute Mute Flat 48 kHz curve 44.1 kHz curve 32 kHz curve 24 20 Reserved 16 Noninverted Inverted Reserved Description Master mute De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) Word width DAC output polarity Table 20. DAC Individual Channel Mutes Bit 0 1 2 3 4 5 6 7 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Description DAC 1 left mute DAC 1 right mute DAC 2 left mute DAC 2 right mute DAC 3 left mute DAC 3 right mute DAC 4 left mute DAC 4 right mute Table 21. DAC Volume Controls Bit 7:0 Value 0 1 to 254 255 Function No attenuation −3/8 dB per step Full attenuation Description DAC volume control Rev. E | Page 21 of 28 AD1933 Data Sheet AUXILIARY TDM PORT CONTROL REGISTERS Table 22. Auxiliary TDM Control 0 Bit 1:0 4:2 6:5 7 Value 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 0 1 Function 24 20 Reserved 16 1 0 8 12 16 Reserved Reserved Reserved Reserved Reserved DAC aux mode Reserved Latch in midcycle (normal) Latch in at end of cycle (pipeline) Description Word width SDATA delay (BCLK periods) Serial format BCLK active edge (TDM in) Table 23. Auxiliary TDM Control 1 Bit 0 1 2 3 5:4 6 7 Value 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 Function 50/50 (allows 32, 24, 20, or 16 bit clocks (BCLKs) per channel) Pulse (32 BCLKs per channel) Drive out on falling edge (DEF) Drive out on rising edge Left low Left high Slave Master 64 128 256 512 Slave Master AUXTDMBCLK pin Internally generated Rev. E | Page 22 of 28 Description LRCLK format BCLK polarity LRCLK polarity LRCLK master/slave BCLKs per frame BCLK master/slave BCLK source Data Sheet AD1933 ADDITIONAL MODES The AD1933 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 19 for an example of a DAC TDM data transmission mode that does not require high speed DBCLK. This configuration is applicable when the AD1933 master clock is generated by the PLL with the DLRCLK as the PLL reference frequency. To relax the requirement for the setup time of the AD1933 in cases of high speed TDM data transmission, the AD1933 can latch in the data using the falling edge of DBCLK. This effectively dedicates the entire BCLK period to the setup time. This mode is useful in cases where the source has a large delay time in the serial data driver. Figure 20 shows this pipeline mode of data transmission. Both the BLCK-less and pipeline modes are available. DLRCLK 32 BITS INTERNAL DBCLK DSDATAx DLRCLK 06624-019 INTERNAL DBCLK TDM-DSDATAx Figure 19. Serial DAC Data Transmission in TDM Format Without DBCLK (Applicable Only If PLL Locks to DLRCLK) DLRCLK DBCLK 06624-020 DATA MUST BE VALID AT THIS BCLK EDGE MSB DSDATAx 2 Figure 20. I S Pipeline Mode in DAC Serial Data Transmission (Applicable in Stereo and TDM Useful for High Frequency TDM Transmission) Rev. E | Page 23 of 28 AD1933 Data Sheet APPLICATION CIRCUITS LRCLK + LF 39nF DAC OUTP MCLK 2.2nF 68pF NPO 3.01kΩ 2 270pF NPO 3 560pF NPO 5.62kΩ 1.50kΩ 390pF 562Ω AVDD2 – 1 OP275 + 604Ω AUDIO OUTPUT 2.2nF NPO 150pF NPO 5.62kΩ 5.6nF 3.32kΩ AVDD2 DAC OUTN 06624-021 LF 11kΩ 11kΩ 06624-022 Typical applications circuits are shown in Figure 21 through Figure 23. Figure 21 shows the recommended loop filters when using either the LR clock or the master clock as the PLL reference. Output filters for the DAC outputs are shown in Figure 22 and the regulator circuit is shown in Figure 23. Figure 22. Typical DAC Output Filter Circuit (Differential) Figure 21. Recommended Loop Filters for LRCLK or MCLK PLL Reference 100nF + 10µF VSUPPLY 5V 1kΩ E B VDRIVE FZT953 C 3.3V 100nF + 10µF 06624-023 VSENSE Figure 23. Recommended 3.3 V Regulator Circuit Rev. E | Page 24 of 28 Data Sheet AD1933 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 24. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 AD1933YSTZ AD1933YSTZ-RL AD1933WBSTZ AD1933WBSTZ-RL EVAL-AD1939AZ Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 64-Lead LQFP 64-Lead LQFP, 13” Tape and Reel 64-Lead LQFP 64-Lead LQFP, 13” Tape and Reel Evaluation Board Package Option ST-64-2 ST-64-2 ST-64-2 ST-64-2 1 Z = RoHS Compliant Part. The EVAL-AD1939AZ should be used as the evaluation board for the AD1933. The AD1933 is a DAC-only equivalent to the AD1939. 3 W = Qualified for Automotive Applications. 2 AUTOMOTIVE PRODUCTS The AD1933W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. E | Page 25 of 28 AD1933 Data Sheet NOTES Rev. E | Page 26 of 28 Data Sheet AD1933 NOTES Rev. E | Page 27 of 28 AD1933 Data Sheet NOTES ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 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