SPICE Device Model SiHF12N60E www.vishay.com Vishay Siliconix E Series Power MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the n-channel vertical DMOS. The sub-circuit model is extracted and optimized over the -55 °C to +150 °C temperature ranges under the pulsed 0 V to 15 V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. • N-Channel Vertical DMOS • Macro Model (Sub-circuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the -55 °C to +125 °C Temperature Range • Model the Gate Charge SUBCIRCUIT MODEL SCHEMATIC D M2 CGD R1 4 M2B J1 3 Gy G RG – + DBD Gx M1 ETCV CGS S Note • This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to the appropriate datasheet of the same number for guaranteed specification limits. S15-0179-Rev. A, 09-Feb-15 Document Number: 90930 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SPICE Device Model SiHF12N60E www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SIMULATED MEASURED DATA DATA UNIT SYMBOL TEST CONDITIONS VGS(th) VDS = VGS, ID = 250 μA 3 - V RDS(on) VGS = 10 V, ID = 6 A 0.32 0.32 Ω gfs VDS = 40 V, ID = 8 A 5.1 3.8 S VSD IS = 6 A, VGS = 0 V 0.9 - V 1000 937 Static Gate Threshold Voltage Drain-Source On-State Resistance Forward Transconductance a Diode Forward Voltage Dynamic a b Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd VDS = 100 V, VGS = 0 V, f = 1 MHz VDS = 480 V, VGS = 10 V, ID = 6 A 77 53 6.8 5 28 29 6 6 13 13 pF nC Notes a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. S15-0179-Rev. A, 09-Feb-15 Document Number: 90930 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SPICE Device Model SiHF12N60E www.vishay.com Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ = 25 °C, unless otherwise noted) 30 30 25 25 TJ = 150 °C VGS = 15 V, 13 V, 11 V ID - Drain Current (A) ID - Drain Current (A) TJ = 25 °C 20 VGS = 7 V 15 10 5 20 15 10 5 VGS = 5 V 0 0 0 5 10 15 20 25 30 0 5 VDS - Drain-to-Source Voltage (V) 10 20 15 25 VGS - Gate-to-Source Voltage (V) 10 000 20 VGS = 15 V, 13 V, 11 V, 9 V Ciss 1000 C - Capacitance (pF) RDS(on) - On-Resistance (Ω) 16 12 VGS = 7 V 8 100 Coss 10 4 Crss VGS = 5 V 0 1 0 5 10 15 20 25 30 0 100 ID - Drain Current (A) 24 300 400 500 600 100 ID = 6 A VDS = 120 V 20 IS - Source Current (A) VGS - Gate-to-Source Voltage (V) 200 VDS - Drain-to-Source Voltage (V) 16 VDS = 300 V 12 VDS = 480 V 8 TJ = 150 °C 10 TJ = 25 °C 1 4 0 0 10 20 30 40 Qg - Total Gate Charge (nC) 50 60 0.1 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VSD - Source-to-Drain Voltage (V) Note • Dots and squares represent measured data. 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