NCP1219PRINTGEVB NCP1219 48 W Printer Evaluation Board User's Manual Introduction http://onsemi.com The NCP1219 is the newest part in the NCP12XX family of current−mode flyback controllers. The controller features dynamic self supply (DSS), eliminating the need for external startup circuitry, contributing to a cost effective, low parts count flyback controller design. The NCP1219 also includes a user programmable skip cycle threshold, reducing power dissipation at light loads and in standby mode. An externally provided latch signal delivered to the Skip/latch pin allows the realization of protection functionality. The 48 W ac adapter evaluation board targets a printer adapter application with a 24 V output, reconfigurable to 7.25 V in standby mode selectable with an external signal. The use of DSS mode is demonstrated for low input voltages, while an auxiliary winding is used for higher input voltages to maintain standby power below 1 W. The NCP1219 evaluation board shows latched−mode protection function through the optional primary and secondary overvoltage protection circuits. The evaluation board is designed as an off−line printer adapter power supply. The adapter operates across universal inputs, 85 Vac to 265 Vac (47 Hz – 63 Hz). The adapter supplies a regulated 24 V output. It can deliver a steady state 30 W output with transient capability of 48 W, as defined in Figure 1. EVAL BOARD USER’S MANUAL bias is provided by either DSS for low input voltages, or an auxiliary winding for higher input voltages. The specifications are summarized in Table 1. Table 1. SUMMARY OF EVALUATION BOARD SPECIFICATIONS Output Current (A) Max Input Voltage Vac 85 265 Line Frequency Hz 47 63 Output Voltage Vdc 23.8 24.2 Output Current Adc − 1.25 (2.0 transient peak) Output Power − 30 (48 transient peak) havg 83.5 − Standby Voltage Vdc 7 8 Standby Power W − 1 Output Ripple Voltage mV − 200 mV − 200 1.25 A Output Voltage Under/Overshoot During Transient Load Step from 0.92 A to 2.0 A 0.92 A Design Procedure The converter design procedure is divided into several steps: • Power Component Selection • Loop Stability Analysis and Compensation • IC Supply Circuits • External Protection Circuits • Standby Reconfiguration Circuit Throughout this application note, the minimum and maximum input voltages are referred as low and high line, respectively. The evaluation board schematic is provided in Figure 2 for reference to component values throughout the design procedure. time (ms) Figure 1. Transient Output Current Specification The system has a low voltage standby mode enabled by pulling the MC node low. In standby mode the converter supplies 70 mA of standby current at 7.25 V while maintaining input power below 1 W. The system is self−contained, with the NCP1219 bias being provided by the bulk voltage through an internal startup circuit. The IC November, 2012 − Rev. 3 Min W 300 ms © Semiconductor Components Industries, LLC, 2012 Unit Average Efficiency (EPA Energy Star 2.0 Compliance) 2.0 A 700 ms Requirement 1 Publication Order Number: EVBUM2161/D AC Connector C8 R3 open C1 0.22mF/275V 10u, 1.4A open C4 4.75M 1000p C2 R2 T1 100p C5 R16 open R8 1.4M R5 1.4M D3 D4 D13 VCC 100u/400V C6 0.1/25V NCP1219AD65R2G C3 GND DRV CS FB U1 Skip/ HV latch LATCH ZD1 open JP3 JP2 1N4007 1N4007 R11 1N4007 open R1 R41 R42 1.82K 1.82K J1 J4 R13 412 R4 000 J2 U3 R54 1.69 SFH615A-3 J3 R37 10K 10 MMSD914T1G Q5 R15 1N4007RLG D10 2 1 4 3 U4 C8 open VHOUT R23 990 HS1 T2 R52 1.69 1nF/440V C9 R53 1.69 4700pF/630V C10 D6 MMSD914T1G ZD4 open D5 10 R6 22u/25V C21 open C7 R14 120K/0.5W JP1 SPA07N65C3 D2 R12 open LATCH VCC Q3 open 0 R25 R24 2.49K L1 2.2u R20 open R33 8.06k C19 0.033 20 ZD2 open Q6 2N7002L R32 2.26K R31 19.6K 330mF/35V R9 C18 open C16 VHOUT R30 open 1000uF/35V C15 VHOUT MUR420RLG R51 1.69 U2 open 2 1 6 5 C14 470pF/250V 100 D12 R18 R10 D1 4 3 4.75M 4 3 2 1 http://onsemi.com 2 Figure 2. Evaluation Board Schematic TL431B open 1 2 1N4007 1N4007 F1 JP4 2A/250V R35 10K R34 1k SGND C20 220uF/6.3V 1 2 3 J5 NCP1219PRINTGEVB NCP1219PRINTGEVB Transformer voltage supplying the controller. Using a 650 V MOSFET with a derating factor of 0.8 and a clamp voltage ratio, kc, of 1.6 yields a turns ratio of 0.303. This maintains sufficient margin for the voltage rating of the MOSFET. The power components for the flyback topology can be selected for operation in either discontinuous conduction mode (DCM) or continuous conduction mode (CCM). Measuring the tradeoffs of the two modes at the power level required for this design, the transformer is designed to make a transition between DCM and CCM at low line and a load current of 1.6 A. This ensures that the converter operates in DCM at nominal load. The critical primary inductance, LP(crit), to cause this transition is calculated using Equation 2. The turns ratio, N, is chosen to minimize the voltage stresses placed on main switch, Q5, and the secondary diode, D12. N is calculated using Equation 1, N+ NS NP + k C @ ǒV out ) V f Ǔ BV DSS @ k D * V OS * V bulk(max) (eq. 1) where NS is the number of turns on the secondary winding, NP is the number of turns on the primary winding, kc is the clamp voltage ratio, Vout is the regulated output voltage, Vf is the forward voltage drop of the secondary rectifying diode, BVDSS is the breakdown voltage of the main switch, kD is the derating factor of the main switch, Vos is the clamp voltage overshoot, and Vbulk(max) is the maximum DC bulk h @ V bulk(min) 2 @ L P(crit) + ǒ V 2 @ f OSC @ V out @ I out(crit) @ V bulk(min) ) ǒ V Ǔ Ǔ@ǒ out)V f N out)V f N L P(crit) @ f OSC @ h DI L + Ǹ 350 mH @ 65 kHz @ 85% I L(RMS) + (eq. 3) V PWM I peak V out (eq. 5) V out ) N @ V bulk(min) V bulk(min) @ D max (eq. 6) L pri @ f OSC (eq. 7) Ǹ ǒ D max @ I peak 2 * I peak @ DI L ) DI L 2 Ǔ 2 The power dissipated in the sense resistor is then calculated using Equation 8. PR sense + I L(RMS) 2 @ R sense (eq. 8) The power rating of the resistor is chosen to handle the maximum power dissipation. For this design, the worst case peak power dissipation is calculated to be 400 mW. Four 1206 surface mount resistors in parallel are chosen to dissipate the power. Note that this is the worst case power dissipation calculated assuming a continuous output current of 2 A. For normal operating conditions (Iout = 1.25 A), the power dissipation is 208 mW. + 2.23 A The NCP1219 has a current limit comparator reference voltage, VILIM, of 1 V, typical. Rsense, is calculated using Equation 4. R sense + Ǔ Finally, ΔIL is used to calculate IL(RMS) as in Equation 7. Using the specified peak output power to calculate the peak primary current: 2 @ 48 W ) h @ V bulk(min) (eq. 2) The maximum duty ratio determines the change in primary current, ΔIL, as shown in Equation 6. To calculate the value of the current current sense resistor, Rsense, the peak current of the primary winding of the transformer must first be calculated. The energy storage relationship is used to determine the peak primary current, calculated using Equation 3. Ǹ N D max + Sense Resistor I peak + out)V f The primary rms current, IL(rms) is needed in order to calculate the power dissipation in the Rsense. First, the maximum duty ratio, Dmax, is calculated using Equation 5. where fosc is the switching frequency of the controller, and Iout(crit) is the load current at which the transition between DCM and CCM occurs. By operating in the transition between DCM and CCM, the secondary RMS current is minimized, reducing the requirements on the transformer and output capacitor. For the evaluation board design, with a transition occurring at Iout = 1.6 A, the primary inductance is 350 mH. 2 @ P out V (eq. 4) This results in a value of 449 mW for Rsense (R51||R52||R53||R54). A 430 mW resistor is chosen for sufficient margin to deliver the peak output power. http://onsemi.com 3 NCP1219PRINTGEVB Primary Switch The power dissipated in the secondary diode, Pd is approximated by Equation 13, where Vf is the forward voltage of the selected diode, and Iout is the nominal output current of the converter. The main MOSFET switch, Q5, is selected to operate at a junction temperature of 120°C at an ambient temperature of 85°C. The maximum power dissipation for Q5 is calculated using Equation 9, where TMAX is the maximum junction temperature, TA is the ambient temperature, and RqJA is the thermal resistance of the MOSFET. P max + ǒT max * T AǓ R qJA P d + V f @ I out Output Capacitor The output capacitor is selected to satisfy the output voltage ripple requirements of the controller. The output capacitor must supply the entire output current during the controller on time. The capacitor value is calculated using Equation 14, (eq. 9) An isolated TO−220 with an RqJA of 80°C/W results in a maximum power dissipation of 438 mW. The RDS(on) required to satisfy the maximum power dissipation at nominal load is approximated by Equation 10. The value is taken from the datasheet curves for the desired junction temperature, provided by the MOSFET manufacturer. R DS(on) + P max I L(RMS) C out + The MOSFET is sized so that the thermal requirements are met under nominal load (30 W). Equation 3 is used to determine the peak current, in this case using 30 W for Pout, yielding a peak current of 1.7 A. The controller operates in DCM at low−line and nominal load. The equation for the primary rms current in DCM is shown in Equation 11. In this example, the primary rms current is calculated to be 0.69 A. I L(RMS) + I peak @ ǸD 3 max ESR v (eq. 14) I sec(peak) (eq. 15) I pri(peak) N (eq. 16) An ESR of 31 mW is required to meet the 200 mV output ripple requirement. The output capacitor also has a specified rms current capability that must be considered. The rms current seen by the capacitor, ICout(RMS), is calculated using Equation 17, I Cout(RMS) + ǸIsec(RMS) 2 * Iout(avg) 2 (eq. 17) where Iout(avg) is the maximum dc load current supplied by the converter and Isec(RMS) is the secondary rms current. For the maximum load current, the controller operated in CCM and Isec(RMS) is calculated using Equation 18. For this design at maximum load, ICout(RMS) is 2.44 A. An output capacitor with an ESR of 18 mW and an rms ripple current capability of 2.77 A is selected, and the resulting capacitor value is 1000 mF. The peak inverse voltage, PIV, of D12 is calculated by Equation 12. (eq. 12) 375 V @ 0.303 ) 24 V + 138 V Applying a silicon derating factor of 0.8 to PIV, the minimum breakdown voltage of D12 must be greater than 173 V. An MUR420, 200 V ultrafast rectifier is selected. Ǹ V ripple I sec(peak) + Secondary Rectifier I sec(RMS) + V ripple where Isec(peak) is proportional to the primary peak current by the turns ratio, as given by Equation 16. (eq. 11) Substituting the resulting primary rms current into Equation 10, we find an RDS(on) of less than 1.1 W is required. The Infineon SPA07N65C3 n−channel MOSFET, with RDS(on) = 600 mW is used in this design. This is a conservative approach to the selection of Q5. The RqJA used to calculate the maximum power dissipation assumes the MOSFET operates in free air, without a heat sink. This design includes an aluminum heat sink attached to the body of the TO−220, reducing the thermal resistance and increasing the maximum power capability of the MOSFET. PIV + V bulk(max) @ N ) V out I out @ t on(max) where ton(max) is the maximum on time of the controller, which can be calculated using Dmax from Equation 5. For this design, Equation 14 results in a capacitor value of 70 mF. The effective series resistance, ESR, of the capacitor also plays a significant role in the selection of the output capacitor. The secondary peak current charges the output capacitor during each cycle, and the ESR must not cause a voltage drop greater than the ripple voltage. The acceptable ESR is calculated using Equation 15, (eq. 10) 2 (eq. 13) ǒ (1 * D max) @ I sec(peak) 2 * I sec(peak) @ http://onsemi.com 4 DI L N ) DI L 2 Ǔ N2 @ 3 (eq. 18) NCP1219PRINTGEVB Auxiliary Supply Regulator The HV pin of the NCP1219 can be tied directly to the bulk storage capacitor and used to supply the IC in the absence of an auxiliary winding, for instance, during the startup of the adapter. The startup current is controlled internally and supplied to the VCC capacitor through the VCC pin. While VCC is less than the Inhibit threshold voltage, the VCC capacitor is charged with a current source of 200 mA (typical). Once the inhibit threshold is exceeded, the startup current (typically 13.5 mA) is supplied to the VCC capacitor. When VCC(on) is exceeded, the internal current source is disabled, and the VCC capacitor is discharged until VCC decreases to less than VCC(MIN), at which time the startup current source is enabled, starting the DSS cycle over again. The evaluation board contains several options for the HV pin connection and the biasing of VCC. An auxiliary winding is used to supply VCC at high line conditions in order to satisfy the low standby power requirement of 1 W. N AńN P + ǒVCC ) Vf Ǔ (eq. 19) V bulk This implies that, as the input voltage drops, the auxiliary winding can not supply the IC. When VCC reduces to VCC(MIN), the startup circuit is enabled and the IC bias is supplied to the VCC capacitor by the internal current source. Alternately, an auxiliary voltage greater than 20 V can be used by clamping VCC using a zener diode, minimizing the input voltage at which the controller enters DSS mode. This is shown in Figure 4. D12 Vout Skip/ latch Option 1 – Bulk Connection with Forward Auxiliary Winding HV FB Connecting the HV pin to the bulk voltage and using a forward auxiliary winding provides an IC bias dependant on input voltage, but independent of the output voltage. This is required in this design due to the dual output voltage design. Otherwise the converter would require additional circuitry to prevent the converter from entering DSS mode during the standby conditions. Figure 3 shows this configuration. The voltage is supplied by the auxiliary winding through a series diode. CS VCC GND DRV NCP1219 Figure 4. VCC Connection using a Forward Auxilliary Winding with Added Zener Option 2 – Full−time DSS Mode (No Auxiliary Winding) The auxiliary winding is not necessary with DSS mode, so the connection to the auxiliary winding can be removed altogether, as shown in Figure 5. D12 Vout D12 Vout Skip/ latch HV FB CS VCC Skip/ latch GND DRV HV FB NCP1219 CS VCC GND DRV Figure 3. VCC Connection Using a Forward Auxiliary Winding with DSS at Low−Line NCP1219 Figure 5. VCC Connection with Full−Time DSS Mode (No Auxiliary Winding) The voltage on the VCC pin can not exceed 20 V. Therefore the ratio between the number of turns on the auxiliary winding, NA, and the primary winding, NA/NP, is chosen to maintain VCC below 20 V at the maximum input voltage. NA/NP is calculated using Equation 19. If standby power dissipation is not an issue, this option eliminates the extra components used with the auxiliary http://onsemi.com 5 NCP1219PRINTGEVB winding. Care must be taken not to exceed the thermal capability of the IC. The power dissipated during DSS mode is approximated by Equation 20. P DSS + I CC3 @ V HV where Istart(min) is the specified minimum startup current provided to the VCC pin. Istart(min) = 5 mA and assuming Vbulk(min) = 90 V, the added series resistance should be no more than 10 kW. For the evaluation board, Rbulk is chosen as 3.6 kW so that Istart is 14.7 mA across the input voltage range. For this evaluation board, with Rbulk = 3.6 kW, Istart = 14.7 mA and a maximum ambient temperature of 85°C, the resulting maximum Vbulk is 310 V, a 53 V increase in comparison to the limit when connecting directly to the bulk voltage. The power dissipated by Rbulk during the DSS cycle is found using the rms current supplied through the startup circuit during the DSS cycle, given by Equation 25, (eq. 20) where VHV is the HV pin voltage, and ICC3 is the controller supply current during normal switching operation. ICC3 has a component that is dependant on the gate charge of Q5, as shown in Equation 21, I CC3 + I CC2 ) Q g(tot) @ f SW (eq. 21) where Qg(tot) is the total gate charge of Q5. The amount of power the controller is capable of dissipating depends on many factors, including the VCC capacitor value, airflow conditions, proximity of the controller to other heat generating components on the board, and the layout of the metal traces on the board and their heat spreading characteristics. To determine the thermal characteristics of the controller in the application, the evaluation board is placed in a controlled ambient temperature and the VHV that results in temperature shutdown is measured. RqJA of the controller is given by Eequation 22, R qJA + T SHDN * T A P DSS P Rbulk + R bulk @ ǒI start(RMS)Ǔ P DSS I CC3 ) I start @ R bulk To reduce the power dissipation of DSS mode at high input voltage, the HV pin is connected to the half−wave rectified node of the bridge rectifier in place of the bulk voltage. Figure 6 illustrates this configuration. (eq. 22) D12 Vout Skip/ latch R bulk v I start(min) HV FB CS VCC GND DRV NCP1219 Figure 6. VCC Connection with Full−time DSS Mode Supplied By the Half−Rectified Sine Wave The average voltage applied to the HV pin is reduced because, during half of the input voltage cycle, the HV voltage is a function of the input sinusoid and the other half of the cycle the input voltage is zero. The half−wave rectified waveform is illustrated in Figure 7. (eq. 23) Half-Wave Rectified Voltage where PDSS is found by rearranging Equation 22 and using the RqJA measured above. When adding the series resistors, it is recommended to maintain a minimum VHV of 40 V to ensure there is enough headroom to allow the startup circuit to supply Istart to the VCC pin. Therefore, at low line, the resistance between the bulk voltage and the HV pin can not exceed that given by Equation 24, ǒVbulk(min) * 40 VǓ (eq. 25) Option 3 – Half−Wave Rectified Connection where TA is the ambient temperature of the system and TSHDN is the junction temperature at which a thermal shutdown (TSD) fault occurs. For the evaluation board, with the HV pin tied directly to Vbulk, a VHV of 257 V results in a TSD event, and RqJA is calculated as 82.5°C/W. It is common to include a resistor, Rbulk, in series between the bulk voltage and the HV pin to spread the power dissipation between the controller and Rbulk. Rbulk often consists of at least two resistors in series for protection against shorted component testing. The same power dissipation limit is imposed on the controller as in the case where no series resistor is used. Therefore, adding Rbulk allows the maximum bulk voltage to increase by dissipating the difference in the power while the startup circuit is charging CCC. The increased bulk voltage is given by Equation 23, V bulk + 2 V peak VAVG, (half-wave) time Figure 7. Half−Wave Rectified Waveform (eq. 24) http://onsemi.com 6 NCP1219PRINTGEVB V AVG(half*wave) + V Peak p Iout The average HV pin voltage, VAVG(half−wave), is calculated using Equation 26. (eq. 26) Vout,V1 In comparison, using the example from option 2 (full−time DSS mode with the HV pin connected to Vbullk), power dissipation, PDSS, of 270 mW, and a junction temperature of 107°C is achieved. The techniques mentioned above can be explored in different combinations to optimize standby power and thermal performance of the NCP1219. Feedback Network IL,pri VFB I1,I2 The negative feedback loop that controls the output voltage senses the output voltage using a voltage divider and compares it to the internal reference voltage of a TL431 precision reference. The output current of the TL431 is then a function of the bias that is required to force the internal reference of the TL431 and the output voltage to be equal. The TL431 output drives the cathode of an optocoupler, providing isolation between the primary and secondary side of the converter. The collector of the optocoupler is connected to the FB pin of the NCP1219, closing the feedback loop, as shown in Figure 8. time Figure 9. Feedback Loop Timing Diagram Figure 8. Feedback Network Standby Reconfiguration Control VFB is compared to VCS to determine the on time. If there is an increase in load current, V1 begins to decrease with Vout. This causes I1 to decrease. The optocoupler collector current, I2, also decreases causing VFB to increase, increasing on time for the next switching cycle. The timing diagram describing the feedback loop is shown in Figure 9. The evaluation board has a dual output voltage mode. In normal operation, the converter provides a 24 V regulated output. During standby mode, the output supplies 7.25 V with a standby current of 70 mA. The output voltage level is selected by actively altering the voltage divider supplying the feedback loop. An additional resistor is connected in series with R32. A small signal MOSFET (Q6) is placed in parallel with the added resistance, as shown in Figure 10. http://onsemi.com 7 NCP1219PRINTGEVB Figure 10. Standby Mode Reconfiguration Circuit Figure 11. Screenshot of the Parameter Capture Screen from the Design Tool FLYBACK AUTO When 5 V is applied to the MC pin, Q6 turns on and R33 is bypassed. In this mode, the voltage divider is set by R31 and R32 only, providing 24 V to the output. If the MC pin is grounded or floating Q6 is off connecting R33 in series with R32. This reduces the voltage divider value and sets the output to 7.25 V. After the input and output parameters are entered, the frequency response of the power stage is calculated. The response is presented both numerically, showing the frequency of each pole and zero, along with the dc gain of the power stage and graphically through the use of a Bode plot. This is shown in the screenshot presented in Figure 12. Loop Stability The output voltage regulation is provided by the negative feedback loop described in the previous section. If the feedback loop is not stable, the converter oscillates. To ensure the stability of the converter, the closed loop frequency response phase margin should be greater than 45° at the crossover frequency. The first step in stabilizing the closed control loop is to analyze the frequency response of the power stage. Its contribution will determine the pole and zero placement. The gain and pole and zero placement of the feedback network are selected to achieve the desired crossover frequency and phase margin. ON Semiconductor provides the excel based design tool ”FLYBACK AUTO”. It provides an automated method of compensating the feedback loop of an isolated flyback converter using the TL431 and an optocoupler. The tool takes system level inputs from the user, such as bulk input voltage, output voltage, output current, and controller switching frequency. A screenshot of the parameter capture screen is shown in Figure 11. Figure 12. Screenshot of the Power Stage Frequency Response from the FLYBACK AUTO tool Next, the contribution of the optocoupler to the frequency response of the system is considered. The pole of the compensation is selected to be less than that of the optocoupler. The user enters information about the optocoupler collected from the datasheet or through frequency response characterization of the chosen optocoupler. The optocoupler chosen for the evaluation board design is a Vishay SFH615A−3. Using the test setup shown in Figure 13, the optocoupler frequency response and CTR are measured. For the frequency response measurement, the dc bias of the 2.49 kW resistor is adjusted until the collector of the optocoupler measured 2.5 V. http://onsemi.com 8 NCP1219PRINTGEVB Figure 13. Optocoupler Frequency Analysis Test Circuit From Figure 14, the crossover frequency of the SFH615A−3 is measured at 4.7 kHz. From the dc bias of the optocoupler, the current transfer ratio, CTR is measured as 41%. These values are used in the optocoupler page of the compensation tool. A bill of materials for the compensation network is provided by the tool based on the calculations of the compensation network, as shown in Figure 16. PHASE (°) MAG (dB) Figure 15. Screenshot of the Total Frequency Response Given By the Design Tool FLYBACK AUTO Figure 14. Frequency Response of Vishay’s SFH615A3 Optocoupler This data is entered into the tool and the capacitance contribution of the optocoupler is calculated. The pole and zero placement of the type 2 compensation configuration is provided by the design tool based on the desired crossover frequency and phase margin entered by the user. If the desired crossover frequency causes the pole frequency of the compensation network to exceed the pole frequency of the optocoupler, then the crossover frequency is automatically reduced. The total loop response is provided by the design tool based on the power stage response, optocoupler pole location, and the type 2 compensation design. The user can check the frequency response at various input voltages and load conditions to verify system stability over all conditions, as shown in Figure 15. Figure 16. Screenshot of the Final Feedback Network Bill of Materials The design tool provides a good starting point; a solution that allows the user to quickly set up a stable feedback network. It does not, however, release the designer from measuring the frequency response of the system and optimizing the loop stability and transient response tradeoffs. Using an AP Instruments AP200 frequency response analyzer, the frequency response of the power stage is confirmed, as shown in Figure 17. The measured gain boost required for a crossover frequency of 1 kHz is 17 dB, slightly higher than estimated by the compensation tool. http://onsemi.com 9 40 100 30 60 20 20 10 -2 0 0 -6 0 -1 0 -1 0 0 −17 dB -2 0 -1 4 0 -3 0 -1 8 0 -4 0 PHASE (°) Mag (dB) NCP1219PRINTGEVB -2 2 0 Mag (dB) Phase (°) -5 0 -2 6 0 -6 0 1 10 100 1000 Frequency (Hz) 10000 -3 0 0 100000 Figure 17. Frequency Response of the Power Stage The pole introduced by the optocoupler needs to be considered. The pole location is dependant on the biasing conditions of the optocoupler. The internal 16.7 kW pullup resistor and the output capacitance of the optocoupler set the pole at 4.7 kHz, as shown in Figure 14. The location of this pole limits the available bandwidth of the system. The evaluation board design uses the k−factor approach to pole and zero placement, and a phase margin of 65° is chosen. For the type 2 compensation network, the k−factor is found using Equation 27, * 90 ǒPM * PS ) 45Ǔ 2 k + tan The required gain boost (Gfc) needed to compensate the system and provide a crossover frequency of 1 kHz is measured as 17 dB. The gain provided by the compensation network is calculated using Equation 31. G G + 10 (eq. 31) The RLED value needed to produce this gain is calculated using Equation 32. R LED + (eq. 27) R pullup @ CTR (eq. 32) G From the measurements and the resulting gain, RLED is 990 W. The open loop response is measured by injecting an ac signal across R19 using a network analyzer and an isolation transformer as shown in Figure 18. The open loop response is the ratio of B to A. where PM is the desired phase margin, and PS is the phase brought by the power stage. For a crossover frequency, fc, of 1 kHz, the phase caused by the power stage is −88°. The resulting k value is 4.2. The pole frequency, fp, is calculated using Equation 28. fp + fC @ k fC 20 (eq. 28) The pole frequency for this design is equal to 4.2 kHz. The zero frequency, fz, is calculated using Equation 29, fz + fC (eq. 29) k The zero frequency is set to 240 Hz. The bandwidth of the optocoupler can be used to set the pole location of the compensation network. In this case, adding capacitance to satisfy the k−factor calculations limits the bandwidth of the system and causes slowing of the transient response and increased output ripple. The capacitance needed to place the zero is calculated using Equation 30. C zero + 1 2 @ p @ f z @ R upper Figure 18. Open Loop Frequency Response Measurement Setup The resulting loop response after compensation is shown in Figure 19, where the crossover frequency is 1.3 kHz, with a phase margin of 60°, measured at low−line and nominal load current. (eq. 30) For this design, a value of 33 nF is chosen for Czero. http://onsemi.com 10 NCP1219PRINTGEVB Figure 19 compares the measured results to the frequency response produced by the “FLYBACK AUTO” tool. There is good agreement for frequencies at or below the crossover frequency. There is divergence at higher frequencies due to the double pole of the output filter on the evaluation board. The frequency of the double pole (fdp) is given by Equation 33. (eq. 33) where L1 is the output inductor and C16 is the output filter capacitor, which results in a pole frequency of 7.2 kHz. The “FLYBACK AUTO” tool does not include an output filter in the compensation design. 70 200 60 160 120 50 PM = 60° 40 80 30 40 20 0 fC = 1.3 kHz 10 0 −10 −20 −30 10 PHASE (°) Mag (dB) 1 Ǹ 2 @ p @ L1 @ C16 f dp + −40 Mag (dB) −80 SimMag (dB) Phase (deg) Sim Phase (deg) −120 100 −160 −200 100000 1000 10000 FREQUENCY (Hz) Figure 19. Total Loop Response Measured at Low Line and Nominal Load Current Skip Mode for Reduced Standby Power Dissipation is adjustable by connecting an external resistor between the Skip/latch and GND pins, as shown in Figure 20. If no resistor is connected between the pins, the skip threshold is the default value, Vskip. If the voltage on the Skip/latch pin exceeds 1.3 V, then the skip threshold is clamped to Vskip(MAX), typically 1.3 V. The NCP1219 employs an adjustable skip level that reduces input power in light load and standby conditions. VFB is compared to VSkip/latch. If VFB decreases to less than VSkip/latch, the drive pulses stop until the feedback loop causes VFB to increase to greater than VSkip/latch. VSkip/latch latch-off, reset when VCC < VCC(reset) 2V Skip/latch + VSkip/latch Rskip Cskip R upper 42.0 k Vlatch + R lower 51.3 k S R Q 50 us filter VSkip - VSkip(MAX) VSkip/Latch FB + - Skip Comparator Figure 20. Adjustable Skip Level Circuit Configuration http://onsemi.com 11 To DRV latch reset NCP1219PRINTGEVB Under light load conditions, the controller enters skip mode. As seen in Figure 21, when VFB (C3) decreases to less than VSkip/latch (C1) the drive pulses stop (C4). This in turn causes VFB to increase as Vout decreases. For the evaluation board design, the NCP1219 default skip threshold is used to reduce component count. Selecting a higher skip threshold has tradeoffs. If the skip voltage is set too high, during normal operation at nominal loads the system is in skip mode. This can cause audible noise. On the other hand, when the board is operating in standby mode and the load is very low, a higher skip threshold minimizes the number of switching cycles per skip cycle. This reduces standby power. Overpower Compensation For this evaluation board, without overpower compensation, overcurrent protection occurs at a measured output power of 67.2 W at high line and 57.4 W at low line conditions. The variation in overcurrent output power with input voltage is due to the propagation delay (tdelay) of the PWM comparator. tdelay has an increased effect on the power delivered at high line than at low line as shown in Figure 22. Figure 21. Skip Mode Operation Waveforms; C1 = VSkip/latch, C2 = VCC, C3 = VFB, C4 = VDRV Peak Primary Current Higher peak current Ipeak 230 Vac 120 Vac Slope = Vbulk/Lp 0 tdelay tdelay Figure 22. Overpower Effect Due to Propagation Delay http://onsemi.com 12 time NCP1219PRINTGEVB This effect is called “Over power” because it increases the power at which the overcurrent protection disables the controller. Specifically, for a DCM flyback system, the total power delivered to the output including the propagation delay effect is: ǒ V bulk 1 P out + @ L P @ I peak ) @ t delay 2 Lp Ǔ I peak + V CS(offset) + V sense(peak1) * V sense(peak2) (eq. 37) HV For this design VCS(offset) is 70 mV. This represents the offset voltage required on the CS pin to force the controller to enter overcurrent protection at the desired output power. If the circuit in Figure 23 is chosen, the ROPP resistor is selected to ensure the power dissipation of the circuit does not exceed the desired maximum, POPP. For this design 50 mW is selected. The resistor value is calculated using Equation 38. FB CS VCC GND DRV Rcomp Rsense Figure 23. Overpower Compensation Circuit Using the Bulk Capacitor Voltage Skip/ latch Pri Aux R OPP + HV VCC I OPP + GND DRV ROPP Rcomp V bulk(max) 2 (eq. 38) P OPP ROPP creates a current that flows through Rcomp, creating the necessary offset (VCS(offset)) on the CS pin to compensate for the propagation delay. The current is calculated with Equation 39. FB CS (eq. 36) The resulting sense voltage is 1.13 V. Under high line conditions, the desired overpower output current is 2.5 A (60 W). Calculate the sense voltage associated with the desired output power using the same method. In this case, an output power of 60 W results in a sense voltage of 1.06 V. The difference between the calculated sense voltages is given by Equation 37. Vbulk ROPP (eq. 35) L p @ f OSC @ h V sense(peak) + I peak @ R sense @ f SW @ h The NCP1219 is designed with a very short tdelay (59 ns typical). This minimizes the overpower. If a tighter overpower limit is required, then overpower compensation is implemented by using the circuits shown in Figures 23 and 24. Skip/ latch 2 @ P out Using the measured output power at high line, the calculated peak current of 2.63 A causes a voltage on the sense resistor, as in Equation 36. (eq. 34) 2 Ǹ V bulk(max) * 1 V (eq. 39) V CS(offset) The ramp compensation resistor also creates an offset voltage due to the ramp compensation current supplied by the controller. The internal current ramp has a slope of 8.12 mA/ms. The controller on time is measured near the current limit in order to determine the peak voltage on the ramp compensation resistor. The total effect of the added compensation is shown in Equation 40. Rsense Figure 24. Overpower Compensation Circuit Using a Forward Auxiliary Winding The circuit in Figure 23 modifies the Ipeak setpoint proportional to the HV bulk level. The voltage divider formed by ROPP and Rcomp creates an offset that compensates for the propagation delay, but increases power dissipation. Figure 24 provides another option that results in reduced power dissipation. By altering the connection of the auxiliary winding diode, a new setpoint is created whose voltage is proportional to Vin. The power dissipation is reduced by a factor of (Npri:Naux)2. To determine the required amount of compensation, first the peak current for the overcurrent power at high line is calculated using Equation 35. R ramp + V CS(offset) 8.12 Ańs @ t on ) V *1 bulk(max) R (eq. 40) OPP ROPP is chosen to be 2.8 MW. Rramp is chosen to be 412 W to achieve an overcurrent limit at 60 W under high line conditions. The low line overcurrent limit must also be confirmed to ensure that the peak power is delivered with the overpower compensation circuit. The low line current limit for this design is measured to be 2.2 A (52.8 W). http://onsemi.com 13 NCP1219PRINTGEVB Overvoltage Protection options included on this evaluation board. For example, the latch pin may be used to implement temperature shutdown externally using an NTC element driving the base of a bipolar transistor, Q1, as shown in Figure 27. The NTC value is chosen so that the voltage divider made between it and Rbe turn on Q1 at the proper temperature. Once the controller enters a latched fault, VCC must decrease lower than VCC(reset) to reset the controller. This is typically achieved by removing power from the mains. Overvoltage protection (OVP) is implemented on this evaluation board using one of two options; primary side overvoltage protection or secondary side overvoltage protection. Primary side OVP is implemented as shown in Figure 25. With the auxiliary winding in a flyback configuration, VCC is proportional to the output voltage. A zener diode and series current limiting resistor are connected between the Skip/latch pin of the controller and VCC. If the output voltage starts to rise, VCC rises and current starts to flow through ZD1. The zener current causes the voltage on the Skip/latch pin to exceed the latch threshold and the controller enters latched fault mode. R11 D6 Rbe Q1 R15 NTC C7 Skip/ latch ZD1 Skip/ latch HV CS FB VCC GND DRV Figure 27. Temperature Shutdown Latch Circuit Any other generic latched fault can be implemented using a circuit similar to Figure 28. A fault signal is applied to the base of an npn bipolar transistor, Q2, whose cathode drives the base of a pnp bipolar transistor, Q1, bringing the Skip/latch pin high. Figure 25. Primary Overvoltage Protection Circuit A secondary side OVP latch function is implemented using the circuit shown in Figure 26. The primary and secondary sides are isolated using an optocoupler. The zener diode ZD2 starts to conduct if the output voltage exceeds the regulated voltage. The current conducted by ZD2 biases Q3 and causes current to flow from the cathode of the optocoupler. The optocoupler transistor turns on and the voltage on the Skip/latch pin increases, latching the controller. The value of R10 is chosen in order to limit the voltage applied to the Skip/latch pin during a fault condition. Q1 Latch Off Signal VCC VHOUT HV R10 Q2 Skip/ latch HV FB CS R20 VCC GND DRV FB U2 CS VCC GND DRV CS Skip/ latch HV FB ZD2 VCC Figure 28. Generic Latched Shutdown Example GND DRV SOFT−START Q3 R30 Soft−start reduces stress during power up by slowly increasing the peak current until the soft−start timer expires. The NCP1219 implements soft−start by comparing the CS pin voltage to the lesser of the internal divided by three FB voltage or the internal soft−start ramp. The soft−start management block of the NCP1219 controller enables the soft−start voltage ramp to rise in 4.8 ms. Figure 29 shows the current sense waveform taken differentially across the sense resistor, as the current ramps up during the first 4.8 ms of the startup time. C18 Figure 26. Secondary Overvoltage Protection Circuit Latch Protection The latching fault protection offered by the NCP1219 can also be used to implement other convenient board level protection functions besides the overvoltage protection http://onsemi.com 14 NCP1219PRINTGEVB Figure 29. Startup Waveforms Showing Soft−Start Behavior; C1 = Vout, C4 = VCS/20 Board Layout 3. Use a single ground connection. 4. Keep sensitive nodes away from noisy nodes such as the drain of the power switch. 5. Place decoupling capacitors close to the pins of IC. 6. Sense output voltage at the output terminal to improve load regulation. Figure 30 shows the top layer of the PC board, including the silkscreen, copper, and soldermask. The evaluation board is built using a double sided FR4 board. Through hole components are placed on the top layer and surface mount components on the bottom layer. The board is constructed using 2 oz copper. During the layout process care was taken to: 1. Minimize trace length, especially for high current loops. 2. Use wide traces for high current connections. http://onsemi.com 15 NCP1219PRINTGEVB Figure 30. Layer 1 (Top) Figure 31. Layer 2 (Bottom) http://onsemi.com 16 NCP1219PRINTGEVB Design Validation Figure 31 shows the bottom layer of the PC board, including the silkscreen, copper, and soldermask. The layout files may be available. Please contact your sales representative for availability. The top and bottom view of the board are shown in Figures 32 and 33, respectively. Figure 32. NCP1219 Evaluation Board Top View Figure 33. NCP1219 Evaluation Board Bottom View http://onsemi.com 17 NCP1219PRINTGEVB The bill of materials that accompanies the evaluation board circuit schematic of Figure 2 is listed in Table 2. Table 2. BILL OF MATERIALS Manufacturer Part Number Substitution Allowed Lead Free Kemet/ Evox-Rifa PHE840MX6220MB06 Yes Yes SM/0805 Vishay VJ0805Y102KXXA Yes Yes 10% SM/0805 Vishay VJ0805Y104KXXA Yes Yes open - SM/0805 - - Yes Yes Capacitor, Ceramic, SMD 100 pF 10% SM/0805 Vishay VJ0805Y101KXXA Yes Yes 1 Capacitor, Electrolytic 100 uF, 400 V 20% Radial United Chemicon EKXG401ELL820MM25S Yes Yes C7 1 Capacitor, Electrolytic open - - - - Yes - C9 1 Capacitor, Ceramic, Y-cap 1 nF, 1000 V 20% Radial Kemet/ Evox-Rifa ERO610RJ4100M Yes Yes C10 1 Capacitor, Ceramic, Through Hole 4700 pF, 630 V 5% Radial TDK FK20C0G2J472J Yes Yes C14 1 Capacitor, Ceramic, Through Hole 470 pF, 250 V 10% Radial TDK FK18C0G2E471J Yes Yes C15 1 Capacitor, Electrolytic 1000 uF, 35 V 20% Radial United Chemicon EKZE350ELL102MK25S Yes Yes C16 1 Capacitor, Electrolytic 330 uF, 35 V 20% Radial United Chemicon EKZE350ELL331MJ16S Yes Yes C18 1 Capacitor, Ceramic, SMD open - SM/0805 - - Yes Yes C19 1 Capacitor, Ceramic, SMD 0.033 uF 10% SM/0805 Vishay VJ0805Y333KXJA Yes Yes C20 1 Capacitor, Electrolytic 220 uF, 6.3 V 20% Radial United Chemicon ESMG6R3ELL221ME11D Yes Yes C21 1 Capacitor, Electrolytic 22 uF, 25 V 20% Radial United Chemicon ESMG250ELL220ME11D Yes Yes D1, D2, D3, D4, D10, D13 6 Diode, Rectifier 1 A, 1000 V - Axial ON Semiconductor 1N4007RLG No Yes D5, D6 2 Switching Diode 100 V - SOD-123 ON Semiconductor MMSD914T1G No Yes D12 1 Diode, Ultrafast Rectifier 4 A, 200 V - Axial ON Semiconductor MUR420RLG No Yes F1 1 Fuse, Radial Lead 2 A, 250 V - Radial Littelfuse 3921200000 Yes Yes HS1 1 Heatsink - - Custom Yes Yes J1 1 AC Connector IEC 320-C8 - Through Hole Qualtek 770W-X2/10 Yes Yes J2 1 Electrical Connection on Top Layer of PCB - - - - - - - J3 1 Electrical Connection on Top Layer of PCB - - - - - - - J4 1 Electrical Connection on Top Layer of PCB - - - - - - - Designator Value Tolerance Qty Description Footprint Manufacturer C1 1 Capacitor, Metalized Poly Film 0.22 uF, 1000 V 20% Radial C2 1 Capacitor, Ceramic, SMD 1000 pF 10% C3 1 Capacitor, Ceramic, SMD 0.1 uF C4 1 Capacitor, Ceramic, SMD C5 1 C6 http://onsemi.com 18 NCP1219PRINTGEVB Table 2. BILL OF MATERIALS Manufacturer Manufacturer Part Number Substitution Allowed Lead Free 0.156 Molex 26-64-4030 Yes Yes - - - - - 22 AWG - - Belden 8021 Yes Yes Electrical Connection on Top Layer of PCB - - - - - - - 1 Inductor, Power 2.2 uH - Radial Coilcraft RFB0807-2R2L Yes Yes MECHA NICAL 1 Screw M3 8 mm - - Building Fasteners MPMS 003 0008 PH Yes Yes MECHA NICAL 2 Insulating tubing 22 AWG - - SPI Technology TTI-S22-1100-NAT Yes Yes Q3 1 Transistor, NPN Bipolar open - SOT-23 - - Yes - Q5 1 MOSFET, Power 7 A, 650 V - TO-220-3 -31, FullPAK Infineon SPA07N65C3 Yes Yes Q6 1 MOSFET, Small Signal 115 mA, 60 V - SOT-23 ON Semiconductor 2N7002LT1G No Yes R1, R2 2 Resistor, SMD 4.75 MW 0.01 SM/1206 Vishay CRCW12064754FN Yes Yes R3 1 Resistor, SMD 14 kW 0.01 SM/0805 Vishay CRCW080520K0FN Yes Yes R4 1 Resistor, SMD 412 W 0.01 SM/0805 Vishay CRCW08054120FN Yes Yes R5, R8 2 Resistor, SMD 1.4 MW 0.01 SM/1206 Vishay CRCW12061404FN Yes Yes R6 1 Resistor, SMD 10 W 0.01 SM/1206 Vishay CRCW120610R0FN Yes Yes R9 1 Resistor, Through Hole 20 W 0.01 Axial Yageo MFR-25FBF-20R0 Yes Yes R10 R11 2 Resistor, SMD open - SM/1206 - - Yes - R13 1 Resistor, Through Hole 0W Jumper Axial Panasonic ECG ERD-S2T0V Yes Yes R14 1 Resistor, Through Hole 120 kW 0.05 Axial Vishay HVR3700001203JR500 Yes Yes R15 1 Resistor, SMD 10 W 0.01 SM/1206 Vishay CRCW120610R0FN Yes Yes R16 1 Resistor, Through Hole open - Axial - - Yes - R18 1 Resistor, Through Hole 100 W 0.05 Axial Vishay 5093NW100R0JBC Yes Yes R20 1 Resistor, Through Hole open - Axial - - Yes - R23 1 Resistor, SMD 976 W 0.01 SM/0805 Vishay CRCW08059760FN Yes Yes R24 1 Resistor, SMD 2.49 kW 0.01 SM/1206 Vishay CRCW08052491FN Yes Yes R25 1 Resistor, SMD 0W 0.01 SM/0805 Vishay CRCW08050000FN Yes Yes R30 1 Resistor, SMD open - SM/0805 - - Yes - R31 1 Resistor, SMD 19.6 kW 0.01 SM/1206 Vishay CRCW080519K6FN Yes Yes R32 1 Resistor, SMD 2.26 kW 0.01 SM/0805 Vishay CRCW08052K26FN Yes Yes R33 1 Resistor, SMD 8.06 kW 0.01 SM/0805 Vishay CRCW08058061FN Yes Yes R34 1 Resistor, SMD 1 kW 0.01 SM/0805 Vishay CRCW08051K00FN Yes Yes R35, R37 2 Resistor, SMD 10 kW 0.01 SM/0805 Vishay CRCW08051001FN Yes Yes Value Tolerance Footprint Header, 1 Row of 3 - - 1 Electrical Connection on Top Layer of PCB - JP2 JP3 2 jumper wire JP4 1 L1 Designator Qty Description J5 1 JP1 http://onsemi.com 19 NCP1219PRINTGEVB Table 2. BILL OF MATERIALS Manufacturer Manufacturer Part Number Substitution Allowed Lead Free Qty Description Value Tolerance R41, R42 2 Resistor, SMD 1.8 kW 0.01 SM/1206 Vishay CRCW12061801FN Yes Yes R51, R52, R53, R54 4 Resistor, SMD 1.69 W 0.01 SM/1206 Vishay CRCW12061R69FN Yes Yes T1 1 Inductor, Common Mode Choke 10 mH -30%, +50% Through Hole Epcos B82732R2142B30 Yes Yes T2 1 Transformer, Flyback 400 uH - Custom, Through Hole ICE Components TO09002-1 Yes Yes U1 1 Switchmode Controller NCP1219 - SOIC-7 ON Semiconductor NCP1219AD65R2G No Yes U2 1 Optocoupler open - DIP-4 - - Yes - U3 1 Optocoupler 150% CTR - DIP-4 Vishay SFH615A-3 Yes Yes U4 1 Programmable Precision Reference TL431B - TO-92 ON Semiconductor TL431BCLPRMG Yes Yes ZD1 1 Diode, Zener open - SOD-123 - - Yes - ZD2, ZD4 2 Diode, Zener open - SOD-123 - - Yes - Designator Footprint 1. Coilcraft components can be ordered at http://www.coilcraft.com 2. Epcos components can be ordered at http://www.epcos.com 3. ICE Components can be ordered at http://www.icecomponents.com 4. Infineon components can be ordered at http://www.infineon.com 5. Kemet components can be ordered at http://www.kemet.com 6. TDK components can be ordered at http://www.tdk.com 7. Vishay Components can be ordered at http://www.vishay.com The converter performance is evaluated and compared to the original goals. From Table 1, the evaluation criteria includes: 1. Efficiency. 2. Standby input power. 3. Step load response. 4. Output voltage ripple. The efficiency of the converter is measured across the The average efficiency, havg, as defined by the Energy universal input voltage range. Figure 34 shows the Star 2.0 External Power Supply (EPS) specification, was efficiency vs output current at 90 Vac, 100 Vac, 115 Vac, calculated for various input voltages. The results are shown 230 Vac and 265 Vac. in Figure 35. The converter is Energy Star 2.0 compliant, maintaining havg greater than 83.5%. 100 90 Efficiency (%) 80 70 60 50 40 30 20 10 0 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% Load Current (1.25 A = 100%) 90 Vac−47 Hz 100 Vac−47 Hz 230 Vac−50 Hz 265 Vac−50 Hz 115 Vac−60 Hz Figure 34. Efficiency vs. output current http://onsemi.com 20 NCP1219PRINTGEVB 90 89 Average Efficiency (%) 88 87 86 85 84 83 82 81 80 50 100 150 200 250 300 Input Voltage (Vac) Figure 35. Average Efficiency vs. Line Voltage The standby input power requirement is less than 1 W over the range of input voltage. Figure 36 shows the standby input power versus input voltage. Starting at low line, the input power rises with increasing input voltage. At line voltages less than 180 Vac, the controller operates in DSS mode, because the forward auxiliary winding voltage is less than that required to maintain VCC greater than VCC(MIN). A portion of the standby input power is due to the startup circuit. As the input voltage increases, the auxiliary winding begins to supply the controller and the startup circuit is no longer active. A sudden drop in the standby input power is observed when DSS is disabled. As the input voltage continues to increase, so does the input power. 1200 1100 STANDBY POWER (mW) 1000 Aux winding mode 900 800 DSS mode 700 600 500 80 100 120 140 160 180 200 220 240 260 280 INPUT VOLTAGE (Vac) Figure 36. Standby Power versus Input Voltage (Forward Auxiliary Winding Connection) http://onsemi.com 21 NCP1219PRINTGEVB switching frequency appears as expected. The output filter eliminates the ripple associated with the switching frequency, leaving only low amplitude spikes of noise that are due to the switch transitions. The output voltage ripple is measured at 16 mV at high line and full load. It is significantly less than the 50 mV target. The output voltage ripple waveform at high line and full load is shown in Figure 37. The ripple measured at the Figure 37. Output Voltage Ripple at High−line and Full Load electromagnetic interference, EMI. The bandwidth of the system is not high enough to prevent this component. This is shown in Figure 38. The output ripple due to the frequency jitter is still within the target limits. If the output ripple is observed on a longer time scale, a component of the NCP1219 frequency jitter is observed. The frequency jitter generated by the controller spreads the energy generated during switching, reducing Figure 38. Frequency Jitter Component of Output Ripple at Nominal Load Current http://onsemi.com 22 NCP1219PRINTGEVB as 150 mV, and recovery occurs in less than 5 ms. Response to the transient load condition confirms the results of the loop stability analysis. The dynamic response of the converter at 24 V is evaluated stepping the load current from 0.92 A to 2.0 A and from 2.0 A to 0.92 A. The step load response is shown in Figure 39. The output response to the load step is measured Figure 39. Output Voltage Response to a Step Load from 0.92 A to 2.0 A The frequency jitter component of the output waveform previously described can be seen during the transient response measurement. http://onsemi.com 23 NCP1219PRINTGEVB Thermal Performance of the board during a continuous load step as described in Figure 1. Images include top and bottom layers at low and high line. All images were taken in open air conditions without forced airflow. This evaluation board is designed to operate with out forced airflow as in an external printer power supply. The thermal performance of the board is evaluated using an infrared camera. Figures 40 through 43 show several images Figure 40. Thermal Image of the Top of the Board at Low Line During a Continuous Load Step Condition Figure 41. Thermal Image of the Bottom of the Board at Low Line During a Continuous Load Step Condition http://onsemi.com 24 NCP1219PRINTGEVB Figure 42. Thermal Image of the Top of the Board at High Line During a Continuous Load Step Condition Figure 43. Thermal Image of the Bottom of the Board at High Line During a Continuous Load Step Condition http://onsemi.com 25 NCP1219PRINTGEVB achieved using a forward auxiliary winding with DSS operating at low line conditions only. The converter complies with Energy Star 2.0 EPS requirements. The converter provides excellent transient response by minimizing overshoot, undershoot, and recovery time. Output voltage ripple is measured at 16 mV. Phase margin and crossover frequency are measured at 60° and 1.3 kHz, respectively. This evaluation board is designed to demonstrate the features and flexibility of the NCP1219. This design is a guideline only and does not guarantee performance for any manufacturing or production purposes. Most of the losses on the board are on the main switch, transformer, secondary rectifier (D12) and secondary snubber resistor (R18). The main switch losses are dominated by on state conduction losses, but the aluminum heat sink reduces the power dissipation in the device. High peak currents during the load step create heating in the transformer, as seen in Figures 40 and 42. The losses in D12 during load step conditions are shown in the lower right−hand corner of the board in Figures 40 and 42. The heat spreading from D12 can also be seen on the bottom side of the board. The secondary snubber is designed to prevent overvoltage stress on the secondary rectifier. The power dissipation in R18 occurs at high line conditions when the snubber acts to clamp the voltage on the diode, as seen in the upper right hand corner of the board. At low line, DSS mode is active and the power dissipation in the controller and the series HV resistors (R41 and R42) can be seen in Figure 41. References 1. Basso, Christophe P. Switch−Mode Power Supplies SPICE Simulations and Practical Designs. 1st ed. New York, NY: MacGraw Hill. 2. Pressman, Abraham I. Switching Power Supply Design. 1st ed. New York, NY: MacGraw Hill. 3. PWM Controller with Adjustable Skip Level and External Latch Input Datasheet NCP1219, www.onsemi.com. Summary A 30 W (48 W) converter is designed and built using the flyback topology. The converter is implemented using the NCP1219. The average load efficiency is measured above 83.5% over the complete operating range. The standby input power is measured below 1 W under universal mains operating ranges. The low standby power is http://onsemi.com 26 NCP1219PRINTGEVB TEST PROCEDURE FOR THE NCP1219PRINTGEVB EVALUATION BOARD Required Equipment • • • • • 60minutes + (W h) 12 P IN + W h 5minutes 1hour Record the results in Table 5. Verify it is within the limits of Table 4. 22. Repeat steps 19 through 21 for a line voltage of 230 Vac / 50 Hz. 23. Set the ac power source to 115 Vac / 60 Hz. 24. Set the electronic load to 1.25 A. 25. Set the dc power supply to 5 V. 26. Perform a 5 minute burn in at the line and load conditions given in steps 23 and 24. 27. Measure and the output voltage (VOUT) using the corresponding multimeter. Record the results in Table 6. Verify it is within the limits of Table 4. 28. Measure the output current (IOUT) using the corresponding multimeter. Record the results in Table 6. 29. Measure the input power (PIN) using the power analyzer. Record the results in Table 6. 30. Calculate the efficiency (h) using the equation (*Equivalent test equipment may be submitted.) *Chroma 61604 AC Power Source *Chroma 66202 Digital Power Meter *Agilent 34401A Multimeter *Chroma 6314 Electronic Load with *Chroma 63102 Module *Agilent E3649A DC Power Supply Test Procedure 1. Set multimeter M1 to measure current. 2. Connect input terminal “I” of multimeter M1 to pin 3 of connector J5. 3. Connect the input terminal “LO” of multimeter M1 to the positive terminal of the electronic load. 4. Connect the negative terminal of the electronic load to pin 2 of connector J5. 5. Set multimeter M2 to measure voltage. 6. Connect the input terminal “HI” of multimeter M2 to pin 3 of connector J5. 7. Connect the input terminal “LO” of multimeter M2 to pin 2 of connector J5. 8. Connect the positive terminal of the dc power supply to pin 1 of connector J5. 9. Connect the negative terminal of the dc power supply to pin 2 of connector J5. 10. Connect the ac power source and power analyzer to connector J1 as shown in Figure 44. 11. Set the current compliance limit on the ac source to 4 A. 12. Set the ac source to 115 Vac / 60 Hz. 13. Set the electronic load to the lowest current range setting. 14. Set the electronic load to 70 mA. 15. Set the dc power supply connected to pin1 of J5 to 0 V. 16. High voltages are present on the primary side of the converter during testing. Use Caution. 17. Turn the dc source on. 18. Turn the ac source on. 19. Set the power analyzer to integrate power for 5 minutes and start the integration cycle. 20. Measure VOUT(standby) using the corresponding multimeter. Record the results in Table 5. Verify it is within the limits of Table 4. 21. Measure and the integrated PIN(standby). For some power analyzers it may be necessary to convert to PIN from W*h using the equation: I OUT V OUT 100% P IN Record the results in Table 6. 31. Repeat steps 27 - 30 for all ac source and electronic load settings (0.01 A, 0.3125 A, 0.625 A, 0.9375 A, 1.25 A, 2.00 A) specified in Table 3. 32. Calculate the average efficiency (havg) using the equation: h ) h 50% ) h 75% ) h 100% h avg + 25% 4 where h25%, h50%, h75% and h100% are the efficiencies calculated for the 25%, 50%, 75% and 100% load conditions given in Table 3. Record the results in Table 6. Verify it is within the limits of Table 4. 33. Turn off the ac source. 34. Turn off the dc source. 35. Disconnect the ac source. 36. Disconnect the dc source. 37. Disconnect the electronic load. 38. Disconnect both multimeters. 39. End of test. h+ http://onsemi.com 27 NCP1219PRINTGEVB Figure 44. Test Setup Table 3. NORMAL OPERATING CONDITIONS Input Voltage (Vac) Line Frequency (Hz) 115 60 Table 4. DESIRED RESULTS Input Voltage Load Current (A) For 115 Vac / 60 Hz input 0.675 (50%) 0.9375 (75%) 1.25 (100%) 2.00 50 70 mA 7 V < VOUT(standby) < 8V 70 mA PIN < 1 W IOUT specified in Table 3 VOUT = 24 ±0.2 V 25%, 50%, 75%, 100% havg > 83.5% 70 mA 7 V < VOUT(standby) < 8V 70 mA PIN < 1 W IOUT specified in Table 3 VOUT = 24 ±0.2 V 25%, 50%, 75%, 100% havg > 83.5% 0.01 0.3125 (25%) 230 IOUT 0.01 0.3125 (25%) For 230 Vac / 50 Hz input 0.675 (50%) 0.9375 (75%) 1.25 (100%) 2.00 Table 5. STANDBY MODE MEASURED RESULTS Input Voltage Parameter 115 Vac / 60 Hz Input VOUT(standby) 230 Vac / 50 Hz Input VOUT(standby) http://onsemi.com 28 PIN(standby) PIN(standby) Result NCP1219PRINTGEVB Table 6. NORMAL MODE MEASURED AND CALCULATED RESULTS Input Voltage Load Current (A) Parameter 0.01 VOUT (V) 0.3125 (25%) 0.01 IOUT (A) PIN (W) Result 0.3125 (25%) IOUT (A) PIN (W) PIN (W) VOUT (V) h25% 0.675 (50%) 0.9375 (75%) IOUT (A) h25% PIN (W) VOUT (V) 230 Vac / 50 Hz Input h50% 0.9375 (75%) IOUT (A) h50% PIN (W) VOUT (V) h75% 1.25 (100%) VOUT (V) PIN (W) IOUT (A) h75% PIN (W) VOUT (V) h100% 2.00 IOUT (A) VOUT (V) IOUT (A) PIN (W) PIN (W) h100% 2.00 VOUT (V) PIN (W) IOUT (A) 1.25 (100%) VOUT (V) PIN (W) IOUT (A) 115 Vac / 60 Hz Input VOUT (V) IOUT (A) IOUT (A) 0.675 (50%) VOUT (V) havg VOUT (V) IOUT (A) PIN (W) havg ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 29 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative EVBUM2161/D