Power-Up/-Down Behavior of Low-Power Flash Devices

Power-Up/-Down Behavior of Low Power Flash
Devices
Introduction
Microsemi’s low power flash devices are flash-based FPGAs manufactured on a 0.13 µm process node.
These devices offer a single-chip, reprogrammable solution and support Level 0 live at power-up (LAPU)
due to their nonvolatile architecture.
Microsemi's low power flash FPGA families are optimized for logic area, I/O features, and performance.
IGLOO® devices are optimized for power, making them the industry's lowest power programmable
solution. IGLOO PLUS FPGAs offer enhanced I/O features beyond those of the IGLOO ultra-low power
solution for I/O-intensive low power applications. IGLOO nano devices are the industry's lowest-power
cost-effective solution. ProASIC3®L FPGAs balance low power with high performance. The ProASIC3
family is Microsemi's high-performance flash FPGA solution. ProASIC3 nano devices offer the lowestcost solution with enhanced I/O capabilities.
Microsemi’s low power flash devices exhibit very low transient current on each power supply during
power-up. The peak value of the transient current depends on the device size, temperature, voltage
levels, and power-up sequence.
The following devices can have inputs driven in while the device is not powered:
•
IGLOO (AGL015 and AGL030)
•
IGLOO nano (all devices)
•
IGLOO PLUS (AGLP030, AGLP060, AGLP125)
•
IGLOOe (AGLE600, AGLE3000)
•
ProASIC3L (A3PE3000L)
•
ProASIC3 (A3P015, A3P030)
•
ProASIC3 nano (all devices)
•
ProASIC3E (A3PE600, A3PE1500, A3PE3000)
•
Military ProASIC3EL (A3PE600L, A3PE3000L, but not A3P1000)
•
RT ProASIC3 (RT3PE600L, RT3PE3000L)
The driven I/Os do not pull up power planes, and the current draw is limited to very small leakage current,
making them suitable for applications that require cold-sparing. These devices are hot-swappable,
meaning they can be inserted in a live power system.1
1.
For more details on the levels of hot-swap compatibility in Microsemi’s low power flash devices, refer to the "Hot-Swap
Support" section in the I/O Structures chapter of the FPGA fabric user’s guide for the device you are using.
D ece mb er 20 08
1
Flash Devices Support Power-Up Behavior
Flash Devices Support Power-Up Behavior
The flash FPGAs listed in Table 1 support power-up behavior and the functions described in this
document.
Table 1 • Flash-Based FPGAs
Family*
Series
IGLOO
ProASIC3
Description
IGLOO
Ultra-low power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology
IGLOOe
Higher density IGLOO FPGAs with six PLLs and additional I/O standards
IGLOO nano
The industry’s lowest-power, smallest-size solution
IGLOO PLUS
IGLOO FPGAs with enhanced I/O capabilities
ProASIC3
Low power, high-performance 1.5 V FPGAs
ProASIC3E
Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards
ProASIC3 nano
Lowest-cost solution with enhanced I/O capabilities
ProASIC3L
ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology
RT ProASIC3
Radiation-tolerant RT3PE600L and RT3PE3000L
Military ProASIC3/EL
Military temperature A3PE600L, A3P1000, and A3PE3000L
Automotive ProASIC3
ProASIC3 FPGAs qualified for automotive applications
Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics,
and packaging information.
IGLOO Terminology
In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed
in Table 1. Where the information applies to only one product line or limited devices, these exclusions will
be explicitly stated.
ProASIC3 Terminology
In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices
as listed in Table 1. Where the information applies to only one product line or limited devices, these
exclusions will be explicitly stated.
To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry’s
Lowest Power FPGAs Portfolio.
2
D ece mb er 20 08
Power-Up/-Down Behavior of Low Power Flash Devices
Power-Up/-Down Sequence and Transient Current
Microsemi's low power flash devices use the following main voltage pins during normal operation:2
•
VCCPLX
•
VJTAG
•
VCC: Voltage supply to the FPGA core
–
VCC is 1.5 V ± 0.075 V for IGLOO, IGLOO nano, IGLOO PLUS, and ProASIC3 devices
operating at 1.5 V.
–
VCC is 1.2 V ± 0.06 V for IGLOO, IGLOO nano, IGLOO PLUS, and ProASIC3L devices
operating at 1.2 V.
–
V5 devices will require a 1.5 V VCC supply, whereas V2 devices can utilize either a 1.2 V or
1.5 V VCC.
•
VCCIBx: Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number.
•
VMVx: Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. (Note:
IGLOO nano, IGLOO PLUS, and ProASIC3 nano devices do not have VMVx supply pins.)
The I/O bank VMV pin must be tied to the VCCI pin within the same bank. Therefore, the supplies that
need to be powered up/down during normal operation are VCC and VCCI. These power supplies can be
powered up/down in any sequence during normal operation of IGLOO, IGLOO nano, IGLOO PLUS,
ProASIC3L, ProASIC3, and ProASIC3 nano FPGAs. During power-up, I/Os in each bank will remain
tristated until the last supply (either VCCIBx or VCC) reaches its functional activation voltage. Similarly,
during power-down, I/Os of each bank are tristated once the first supply reaches its brownout
deactivation voltage.
Although Microsemi's low power flash devices have no power-up or power-down sequencing
requirements, Microsemi identifies the following power conditions that will result in higher than normal
transient current. Use this information to help maximize power savings:
Microsemi recommends tying VCCPLX to VCC and using proper filtering circuits to decouple VCC noise
from the PLL.
a. If VCCPLX is powered up before VCC, a static current of up to 5 mA (typical) per PLL may be
measured on VCCPLX.
The current vanishes as soon as VCC reaches the VCCPLX voltage level.
The same current is observed at power-down (VCC before VCCPLX).
b. If VCCPLX is powered up simultaneously or after VCC:
i.
Microsemi's low power flash devices exhibit very low transient current on VCC. For
ProASIC3 devices, the maximum transient current on VCC does not exceed the maximum
standby current specified in the device datasheet.
The source of transient current, also known as inrush current, varies depending on the FPGA technology.
Due to their volatile technology, the internal registers in SRAM FPGAs must be initialized before
configuration can start. This initialization is the source of significant inrush current in SRAM FPGAs
during power-up. Due to the nonvolatile nature of flash technology, low power flash devices do not
require any initialization at power-up, and there is very little or no crossbar current through PMOS and
NMOS devices. Therefore, the transient current at power-up is significantly less than for SRAM FPGAs.
Figure 1 on page 4 illustrates the types of power consumption by SRAM FPGAs compared to
Microsemi's antifuse and flash FPGAs.
2.
For more information on Microsemi FPGA voltage supplies, refer to the appropriate datasheet located at
http://www.microsemi.com/soc/techdocs/ds.
D ece mb er 20 08
3
Power-Up/-Down Sequence and Transient Current
Current
Power-On Inrush
SRAM FPGAs
SRAM
Microsemi
FPGAs
Active
Frequency
Dependent
System
Supply
Voltage
Configuration
SRAM FPGAs
Static
Time (or frequency)
Figure 1 • Types of Power Consumption in SRAM FPGAs and Microsemi Nonvolatile FPGAs
Transient Current on VCC
The characterization of the transient current on VCC is performed on nearly all devices within the
IGLOO, ProASIC3L, and ProASIC3 families. A sample size of five units is used from each device family
member. All the device I/Os are internally pulled down while the transient current measurements are
performed. For ProASIC3 devices, the measurements at typical conditions show that the maximum
transient current on VCC, when the power supply is powered at ramp-rates ranging from 15 V/ms to
0.15 V/ms, does not exceed the maximum standby current specified in the device datasheets. Refer to
the DC and Switching Characteristics chapters of the ProASIC3 Flash Family FPGAS datasheet and
ProASIC3E Flash Family FPGAs datasheet for more information.
Similarly, IGLOO, IGLOO nano, IGLOO PLUS, and ProASIC3L devices exhibit very low transient current
on VCC. The transient current does not exceed the typical operating current of the device while in active
mode. For example, the characterization of AGL600-FG256 V2 and V5 devices has shown that the
transient current on VCC is typically in the range of 1–5 mA.
Transient Current on VCCI
The characterization of the transient current on VCCI is performed on devices within the IGLOO, IGLOO
nano, IGLOO PLUS, ProASIC3, ProASIC3 nano, and ProASIC3L groups of devices, similarly to VCC
transient current measurements. For ProASIC3 devices, the measurements at typical conditions show
that the maximum transient current on VCCI, when the power supply is powered at ramp-rates ranging
from 33 V/ms to 0.33 V/ms, does not exceed the maximum standby current specified in the device
datasheet. Refer to the DC and Switching Characteristics chapters of the ProASIC3 Flash Family
FPGAS datasheet and ProASIC3E Flash Family FPGAs datasheet for more information.
Similarly, IGLOO, IGLOO PLUS, and ProASIC3L devices exhibit very low transient current on VCCI. The
transient current does not exceed the typical operating current of the device while in active mode. For
example, the characterization of AGL600-FG256 V2 and V5 devices has shown that the transient current
on VCCI is typically in the range of 1–2 mA.
4
D ece mb er 20 08
Power-Up/-Down Behavior of Low Power Flash Devices
I/O Behavior at Power-Up/-Down
This section discusses the behavior of device I/Os, used and unused, during power-up/-down of VCC and
VCCI. As mentioned earlier, VMVx and VCCIBx are tied together, and therefore, inputs and outputs are
powered up/down at the same time.
I/O State during Power-Up/-Down
This section discusses the characteristics of I/O behavior during device power-up and power-down.
Before the start of power-up, all I/Os are in tristate mode. The I/Os will remain tristated during power-up
until the last voltage supply (VCC or VCCI) is powered to its functional level (power supply functional
levels are discussed in the "Power-Up to Functional Time" section on page 6). After the last supply
reaches the functional level, the outputs will exit the tristate mode and drive the logic at the input of the
output buffer. Similarly, the input buffers will pass the external logic into the FPGA fabric once the last
supply reaches the functional level. The behavior of user I/Os is independent of the VCC and VCCI
sequence or the state of other voltage supplies of the FPGA (VPUMP and VJTAG). Figure 2 shows the
output buffer driving HIGH and its behavior during power-up with 10 kΩ external pull-down. In Figure 2,
VCC is powered first, and VCCI is powered 5 ms after VCC. Figure 3 on page 6 shows the state of the
I/O when VCCI is powered about 5 ms before VCC. In the circuitry shown in Figure 3 on page 6, the
output is externally pulled down.
During power-down, device I/Os become tristated once the first power supply (VCC or VCCI) drops
below its brownout voltage level. The I/O behavior during power-down is also independent of voltage
supply sequencing.
Figure 2 • I/O State when VCC Is Powered before VCCI
D ece mb er 20 08
5
I/O Behavior at Power-Up/-Down
Figure 3 • I/O State when VCCI Is Powered before VCC
Power-Up to Functional Time
At power-up, device I/Os exit the tristate mode and become functional once the last voltage supply in the
power-up sequence (VCCI or VCC) reaches its functional activation level. The power-up–to–functional
time is the time it takes for the last supply to power up from zero to its functional level. Note that the
functional level of the power supply during power-up may vary slightly within the specification at different
ramp-rates. Refer to Table 2 for the functional level of the voltage supplies at power-up.
Typical I/O behavior during power-up–to–functional time is illustrated in Figure 2 on page 5 and Figure 3.
Table 2 • Power-Up Functional Activation Levels for VCC and VCCI
VCC Functional
Activation Level (V)
VCCI Functional
Activation Level (V)
ProASIC3, ProASIC3 nano, IGLOO, IGLOO nano,
IGLOO PLUS, and ProASIC3L devices running at
VCC = 1.5 V*
0.85 V ± 0.25 V
0.9 V ± 0.3 V
IGLOO, IGLOO nano, IGLOO PLUS, and
ProASIC3L devices running at VCC = 1.2 V*
0.85 V ± 0.2 V
0.9 V ± 0.15 V
Device
Note: *V5 devices will require a 1.5 V VCC supply, whereas V2 devices can utilize either a 1.2 V or 1.5 V
VCC.
Microsemi’s low power flash devices meet Level 0 LAPU; that is, they can be functional prior to VCC
reaching the regulated voltage required. This important advantage distinguishes low power flash devices
from their SRAM-based counterparts. SRAM-based FPGAs, due to their volatile technology, require
hundreds of milliseconds after power-up to configure the design bitstream before they become
functional. Refer to Figure 4 on page 7 and Figure 5 on page 8 for more information.
6
D ece mb er 20 08
Power-Up/-Down Behavior of Low Power Flash Devices
VCC = VCCI + VT
Where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
but slower because VCCI is
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
below specifcation. For the
same reason, input buffers do not
speed, VIH/VIL , VOH /VOL , etc.
Region 1: I/O Buffers are OFF
meet VIH/VIL levels, and output
buffers do not meet VOH/VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification
Region 1: I/O buffers are OFF
Activation trip point:
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCCI
Figure 4 • I/O State as a Function of VCCI and VCC Voltage Levels for IGLOO V5, IGLOO nano V5,
IGLOO PLUS V5, ProASIC3L, and ProASIC3 Devices Running at VCC = 1.5 V ± 0.075 V
D ece mb er 20 08
7
I/O Behavior at Power-Up/-Down
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
Region 1: I/O Buffers are OFF
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL , VOH / VOL , etc.
VCC = 1.14 V
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Activation trip point:
Va = 0.85 V ± 0.2 V
Deactivation trip point:
Vd = 0.75 V ± 0.2 V
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Region 1: I/O buffers are OFF
Activation trip point:
Va = 0.9 V ± 0.15 V
Deactivation trip point:
Vd = 0.8 V ± 0.15 V
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
2.3 V, or 3.0 V
Figure 5 • I/O State as a Function of VCCI and VCC Voltage Levels for IGLOO V2, IGLOO nano V2,
IGLOO PLUS V2, and ProASIC3L Devices Running at VCC = 1.2 V ± 0.06 V
8
D ece mb er 20 08
VCCI
Power-Up/-Down Behavior of Low Power Flash Devices
Brownout Voltage
Brownout is a condition in which the voltage supplies are lower than normal, causing the device to
malfunction as a result of insufficient power. In general, Microsemi does not guarantee the functionality of
the design inside the flash FPGA if voltage supplies are below their minimum recommended operating
condition. Microsemi has performed measurements to characterize the brownout levels of FPGA power
supplies. Refer to Table 3 for device-specific brownout deactivation levels. For the purpose of
characterization, a direct path from the device input to output is monitored while voltage supplies are
lowered gradually. The brownout point is defined as the voltage level at which the output stops following
the input. Characterization tests performed on several IGLOO, ProASIC3L, and ProASIC3 devices in
typical operating conditions showed the brownout voltage levels to be within the specification.
During device power-down, the device I/Os become tristated once the first supply in the power-down
sequence drops below its brownout deactivation voltage.
Table 3 • Brownout Deactivation Levels for VCC and VCCI
VCC Brownout
VCCI Brownout
Deactivation Level (V) Deactivation Level (V)
Devices
ProASIC3, ProASIC3 nano, IGLOO, IGLOO nano,
IGLOO PLUS and ProASIC3L devices running at
VCC = 1.5 V
0.75 V ± 0.25 V
0.8 V ± 0.3 V
IGLOO, IGLOO nano, IGLOO PLUS, and
ProASIC3L devices running at VCC = 1.2 V
0.75 V ± 0.2 V
0.8 V ± 0.15 V
PLL Behavior at Brownout Condition
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels mentioned
above for 1.5 V and 1.2 V devices, the PLL output lock signal goes LOW and/or the output clock is lost.
The following sections explain PLL behavior during and after the brownout condition.
VCCPLL and VCC Tied Together
In this condition, both VCC and VCCPLL drop below the 0.75 V (± 0.25 V or ± 0.2 V) brownout level.
During the brownout recovery, once VCCPLL and VCC reach the activation point (0.85 ± 0.25 V or
± 0.2 V) again, the PLL output lock signal may still remain LOW with the PLL output clock signal toggling.
If this condition occurs, there are two ways to recover the PLL output lock signal:
1. Cycle the power supplies of the PLL (power off and on) by using the PLL POWERDOWN signal.
2. Turn off the input reference clock to the PLL and then turn it back on.
Only VCCPLL Is at Brownout
In this case, only VCCPLL drops below the 0.75 V (± 0.25 V or ± 0.2 V) brownout level and the VCC
supply remains at nominal recommended operating voltage (1.5 V ± 0.075 V for 1.5 V devices and 1.2 V
± 0.06 V for 1.2 V devices). In this condition, the PLL behavior after brownout recovery is similar to initial
power-up condition, and the PLL will regain lock automatically after VCCPLL is ramped up above the
activation level (0.85 ± 0.25 V or ± 0.2 V). No intervention is necessary in this case.
Only VCC Is at Brownout
In this condition, VCC drops below the 0.75 V (± 0.25 V or ± 0.2 V) brownout level and VCCPLL remains
at nominal recommended operating voltage (1.5 V ± 0.075 V for 1.5 V devices and 1.2 V ± 0.06 V for
1.2 V devices). During the brownout recovery, once VCC reaches the activation point again (0.85 ±
0.25 V or ± 0.2 V), the PLL output lock signal may still remain LOW with the PLL output clock signal
toggling. If this condition occurs, there are two ways to recover the PLL output lock signal:
1. Cycle the power supplies of the PLL (power off and on) by using the PLL POWERDOWN signal.
2. Turn off the input reference clock to the PLL and then turn it back on.
It is important to note that Microsemi recommends using a monotonic power supply or voltage regulator
to ensure proper power-up behavior.
D ece mb er 20 08
9
Cold-Sparing
Internal Pull-Up and Pull-Down
Low power flash device I/Os are equipped with internal weak pull-up/-down resistors that can be used by
designers. If used, these internal pull-up/-down resistors will be activated during power-up, once both
VCC and VCCI are above their functional activation level. Similarly, during power-down, these internal
pull-up/-down resistors will turn off once the first supply voltage falls below its brownout deactivation
level.
Cold-Sparing
In cold-sparing applications, voltage can be applied to device I/Os before and during power-up. Coldsparing applications rely on three important characteristics of the device:
1. I/Os must be tristated before and during power-up.
2. Voltage applied to the I/Os must not power up any part of the device.
3. VCCI should not exceed 3.6 V, per datasheet specifications.
As described in the "Power-Up to Functional Time" section on page 6, Microsemi’s low power flash I/Os
are tristated before and during power-up until the last voltage supply (VCC or VCCI) is powered up past
its functional level. Furthermore, applying voltage to the FPGA I/Os does not pull up VCC or VCCI and,
therefore, does not partially power up the device. Table 4 includes the cold-sparing test results on
A3PE600-PQ208 devices. In this test, leakage current on the device I/O and residual voltage on the
power supply rails were measured while voltage was applied to the I/O before power-up.
Table 4 • Cold-Sparing Test Results for A3PE600 Devices
Residual Voltage (V)
Device I/O
VCC
VCCI
Leakage Current
Input
0
0.003
<1 µA
Output
0
0.003
<1 µA
VCCI must not exceed 3.6 V, as stated in the datasheet specification. Therefore, ProASIC3E devices
meet all three requirements stated earlier in this section and are suitable for cold-sparing applications.
The following devices and families support cold-sparing:
10
•
IGLOO: AGL015 and AGL030
•
All IGLOO nano
•
All IGLOO PLUS
•
All IGLOOe
•
ProASIC3L: A3PE3000L
•
ProASIC3: A3P015 and A3P030
•
All ProASIC3 nano
•
All ProASIC3E
•
Military ProASIC3EL: A3PE600L and A3PE3000L
•
RT ProASIC3: RT3PE600L and RT3PE3000L
D ece mb er 20 08
Power-Up/-Down Behavior of Low Power Flash Devices
The following devices and families do not support cold-sparing:
•
IGLOO: AGL060, AGL125, AGL250, AGL600, AGL1000
•
ProASIC3: A3P060, A3P125, A3P250, A3P400, A3P600, A3P1000
•
ProASIC3L: A3P250L, A3P600L, A3P1000L
•
Military ProASIC3: A3P1000
Hot-Swapping
Hot-swapping is the operation of hot insertion or hot removal of a card in a powered-up system. The I/Os
need to be configured in hot-insertion mode if hot-swapping compliance is required. For more details on
the levels of hot-swap compatibility in low power flash devices, refer to the "Hot-Swap Support" section in
the I/O Structures chapter of the user’s guide for the device you are using.
The following devices and families support hot-swapping:
•
IGLOO: AGL015 and AGL030
•
All IGLOO nano
•
All IGLOO PLUS
•
All IGLOOe
•
ProASIC3L: A3PE3000L
•
ProASIC3: A3P015 and A3P030
•
All ProASIC3 nano
•
All ProASIC3E
•
Military ProASIC3EL: A3PE600L and A3PE3000L
•
RT ProASIC3: RT3PE600L and RT3PE3000L
The following devices and families do not support hot-swapping:
•
IGLOO: AGL060, AGL125, AGL250, AGL400, AGL600, AGL1000
•
ProASIC3: A3P060, A3P125, A3P250, A3P400, A3P600, A3P1000
•
ProASIC3L: A3P250L, A3P600L, A3P1000L
•
Military ProASIC3: A3P1000
Conclusion
Microsemi's low power flash FPGAs provide an excellent programmable logic solution for a broad range
of applications. In addition to high performance, low cost, security, nonvolatility, and single chip, they are
live at power-up (meet Level 0 of the LAPU classification) and offer clear and easy-to-use power-up/down characteristics. Unlike SRAM FPGAs, low power flash devices do not require any specific powerup/-down sequencing and have extremely low power-up inrush current in any power-up sequence.
Microsemi low power flash FPGAs also support both cold-sparing and hot-swapping for applications
requiring these capabilities.
D ece mb er 20 08
11
Related Documents
Related Documents
Datasheets
ProASIC3 Flash Family FPGAs
http://www.microsemi.com/soc/documents/PA3_DS.pdf
ProASIC3E Flash Family FPGAs
http://www.microsemi.com/soc/documents/PA3E_DS.pdf
List of Changes
The following table lists critical changes that were made in each revision of the chapter.
Date
Changes
Page
v1.2
(December 2008)
IGLOO nano and ProASIC3 nano devices were added to the document as
supported device types.
v1.1
(October 2008)
The "Introduction" section was updated to add Military ProASIC3EL and RT
ProASIC3 devices to the list of devices that can have inputs driven in while the
device is not powered.
1
The "Flash Devices Support Power-Up Behavior" section was revised to include
new families and make the information more concise.
2
The "Cold-Sparing" section was revised to add Military ProASIC3/EL and RT
ProASIC3 devices to the lists of devices with and without cold-sparing support.
10
The "Hot-Swapping" section was revised to add Military ProASIC3/EL and RT
ProASIC3 devices to the lists of devices with and without hot-swap support.
AGL400 was added to the list of devices that do not support hot-swapping.
11
v1.0
(August 2008)
This document was revised, renamed, and assigned a new part number. It now
includes data for the IGLOO and ProASIC3L families.
N/A
v1.3
(March 2008)
The "List of Changes" section was updated to include the three different I/O
Structure handbook chapters.
12
v1.2
(February 2008)
The first sentence of the "PLL Behavior at Brownout Condition" section was
updated to read, "When PLL power supply voltage and/or VCC levels drop below the
VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or
the output clock is lost."
9
v1.1
(January 2008)
The "PLL Behavior at Brownout Condition" section was added.
9
12
D ece mb er 20 08
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog
and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
© 2011 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
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