INFINEON HYB18RL25616AC

HYB18RL25632AC
HYB18RL25616AC
Graphics & Speciality DRAMs
256 Mbit DDR Reduced Latency DRAM
Version 1.60
July 2003
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Edition Jun. 2002
This edition was realized using the software system FrameMaker.
Published by Infineon Technologies,
Marketing-Kommunikation,
Balanstraße 73,
81541 München
© Infineon Technologies 6/30/2002.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing
material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of Infineon Technologies, may only be used in life-support devices or systems2 with the express written approval of Infineon Technologies.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they
fail, it is reasonable to assume that the health of the user may be endangered.
HYB18RL25616/32AC
Revision History: Current Version 1.60
Subjects (major changes since last revision)
Previous Version: 1.42
29,30
29,30
Reversed scan reg order to match device
Previous Version: 1.43
29,30
29,30
31
31
Renumbered scan registers starting with 0 to n-1
Added numbers to the scan chain portion of Figure 27
Previous Version: 1.44
36
36
added preliminary current values to the table.
23
23
Suppressed note 4 for tQSQ, restored to min and max value instead of absolute
16
16
Remove MRS only after power up restriction.
Previous Version: 1.50
15
Version 1.60
15
Suppressed note that 2k NOPs not needed in HSTL mode, 2k NOPs are needed.
23
23
changed tCKDQS from 2.7...3.7 to 2.9...3.9 ns.
23
23
Increased tQSQ from +/-0.3ns to +/-0.35 ns
34
34
VDDQ nominal changed to 1.85V, +/- 100mV
Page 2
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
1.3.1
1.4
1.5
1.5.1
1.5.2
2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.2.1
2.5.2.2
2.5.3
2.5.3.1
2.5.3.2
2.5.4
2.5.4.1
2.5.4.2
2.6
2.6.1
2.6.2
2.6.2.1
2.6.2.2
2.6.3
3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ball Configuration Package and Ballout . . . . . . . . . . . . . . . . . . . . . . .6
Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Clocks, Commands and Addresses . . . . . . . . . . . . . . . . . . . . . . . . .15
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . .17
Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Write - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Write - Cyclic Bank Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Write Data Mask Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Read - Cyclic Bank Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . 29
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.4
3.4.1
3.4.2
3.5
3.6
3.7
3.8
3.9
3.10
3.11
Version 1.60
Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Test Data-In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Test Data-Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Boundary Scan Exit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
x16 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
x32 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
TAP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
JTAG TAP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
JTAG TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . .34
JTAG DC Operating Conditons . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
JTAG AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
JTAG AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .35
JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Page 3
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1
4.2
4.3
4.4
4.5
4.6
Version 1.60
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Recommended Power & DC Operation Ratings . . . . . . . . . . . . . . . .37
AC Operation Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Page 4
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1
Overview
1.1
Features
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
256 Megabit (256M)
0.17µm process technology
Cyclic bank addressing for maximum data out bandwidth
Organization 8M x 32, 16M x 16 in 8 banks
Non-multiplexed addresses
Non-interruptible sequential bursts of 2 (2-bit prefetch) and 4 (4-bit prefetch), DDR
Up to 600Mb/sec/pin data rate
Programmable Read Latency (RL) of 5..6
Data valid signal (DVLD) activated as Read Data is available
Data Mask signals (DM0 / DM1) to mask first and second part of write data burst
IEEE 1149.1 compliant JTAG Boundary Scan
Pseudo-HSTL 1.8V IO Supply
Internal autoprecharge
Refresh requirements: 32ms at 100°C junction temperature (8k refresh for each bank, 64k refresh
commands must be issued in total each 32ms)
Package T-FBGA 144
2.5V VEXT, 1.8V VDD, 1.8V VDDQ
Table 1
Key timing parameters (Configuration Example x32, x16 device)
Speed Sort
-3.3
-4.0
-5.0
Units
Frequency
300
250
200
MHz
26.7
28.0
25.0
ns
8
7
5
cycles
6
5
5
cyles
tRC
Read latency
Version 1.60
Page 5
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.2
General Description
The Infineon 256M Reduced Latency DRAM (RLDRAM) contains 8 banks x 32 Mb of memory accessible
with 32bit or 16bit I/O’s in a double data rate (DDR) format where the data is provided and synchronized with
a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized
for fast random access and high data bandwidth.
RLDRAM is designed for communication data storages like transmit or receive buffers in telecommunication
systems as well as data or instruction cache applications requiring large amounts of memory.
1.3
Ball Configuration Package and Ballout
Figure 1
T-FBGA 144 package 256 Mbit DDR Reduced Latency DRAM
SIDE VIEW
BOTTOM VIEW
1.20 max
12
11
10
9
8
7
6
5
4
3
2
1
A
1
D
E
Ø 0.51 typ
B
C
F
G
J
17
18.5
H
K
L
M
N
P
R
T
U
V
4
0.8
8.8
11
Note: All dimensions in mm
Version 1.60
Page 6
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Figure 2
Version 1.60
Ballout of 256 Mbit Reduced Latency DRAM (x32 configuration)
1
2
3
4
A
VSS
VEXT
VREF
B
VSS
DQ8
C
VSS
D
5
6
9
10
11
12
VSS
VSS
VEXT
TMS
TCK
DQ9
VSSQ
VSSQ
DQ1
DQ0
VSS
DQ10
DQ11
VDDQ
VDDQ
DQ3
DQ2
VSS
VSS
DQS1
DQS1#
VSSQ
VSSQ
DQS0#
DQS0
VSS
E
VSS
DQ12
DQ13
VDDQ
VDDQ
DQ5
DQ4
VSS
F
DM0
DQ14
DQ15
VSSQ
VSSQ
DQ7
DQ6
DVLD
G
A5
A6
A7
VDD
VDD
A2
A1
A0
H
A8
A9
VSS
VSS
VSS
VSS
A4
A3
J
AS#
BA2
VDD
VDD
VDD
VDD
BA0
CK
K
WE#
REF#
VDD
VDD
VDD
VDD
BA1
CK#
L
A18
CS#
VSS
VSS
VSS
VSS
A14
A13
M
A15
A16
A17
VDD
VDD
A12
A11
A10
N
DM1
DQ22
DQ23
VSSQ
VSSQ
DQ31
DQ30
NC
P
VSS
DQ20
DQ21
VDDQ
VDD
VDDQ
DQ29
DQ28
VSS
R
VSS
DQS2
DQS2#
VSSQ
VSSQ
DQS3#
DQS3
VSS
T
VSS
DQ18
DQ19
VDDQ
VDDQ
DQ27
DQ26
VSS
U
VSS
DQ16
DQ17
VSSQ
VSSQ
DQ25
DQ24
VSS
V
VSS
VEXT
VREF
VSS
VSS
VEXT
TDO
TDI
Page 7
7
8
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Figure 3
Version 1.60
Ballout of 256Mbit Reduced Latency DRAM (x16 configuration)
1
2
3
4
A
VSS
VEXT
VREF
B
VSS
NC
C
VSS
D
5
6
9
10
11
12
VSS
VSS
VEXT
TMS
TCK
NC
VSSQ
VSSQ
DQ1
DQ0
VSS
NC
NC
VDDQ
VDDQ
DQ3
DQ2
VSS
VSS
NC
NC
VSSQ
VSSQ
DQS0#
DQS0
VSS
E
VSS
NC
NC
VDDQ
VDDQ
DQ5
DQ4
VSS
F
DM0
NC
NC
VSSQ
VSSQ
DQ7
DQ6
DVLD
G
A5
A6
A7
VDD
VDD
A2
A1
A0
H
A8
A9
VSS
VSS
VSS
VSS
A4
A3
J
AS#
BA2
VDD
VDD
VDD
VDD
BA0
CK
K
WE#
REF#
VDD
VDD
VDD
VDD
BA1
CK#
L
A19
CS#
VSS
VSS
VSS
VSS
A14
A13
M
A15
A16
A17
VDD
VDD
A12
A11
A10
N
DM1
NC
NC
VSSQ
VSSQ
DQ15
DQ14
A18
P
VSS
NC
NC
VDDQ
VDD
VDDQ
DQ13
DQ12
VSS
R
VSS
NC
NC
VSSQ
VSSQ
DQS1#
DQS1
VSS
T
VSS
NC
NC
VDDQ
VDDQ
DQ11
DQ10
VSS
U
VSS
NC
NC
VSSQ
VSSQ
DQ9
DQ8
VSS
V
VSS
VEXT
VREF
VSS
VSS
VEXT
TDO
TDI
Page 8
7
8
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Note: NC : No Connect : These signals are internally connected and have parasitic characterisitcs of an IO. They may optionally be
connected to ground for improved heat dissipation.
1.3.1
Ball Description
Table 2
Ball description
Ball
Type
Detailed Function
CK, CK#
Input
Input Clock: CK and CK# are differential clock inputs. Addresses and commands are
latched on the rising edge of CK, input data is latched on the both edges of CK. CK# is
ideally 180 degrees out of phase with CK.
CS#
Input
Chip Select: CS# enables the command decoder when low and disables it when high.
When the command decoder is disabled new commands are ignored, but internal
operations continue.
AS#, WE#,
REF#
Input
Command Inputs: Sampled at the positive edge of CK. AS#, WE# and REF# define
(together with CS#) the command to be executed.
A[19:0]
Input
Address Inputs: A[19:0] define the row and column addresses for READ and WRITE
operations. During an MODE REGISTER SET the address inputs A[17:0] define the
register settings. The addresses are sampled at the rising edge of CK. In the x32
configuration, A[19] is not used. In the x16 configuration with BL2, A[19] is used.
BA[0:2]
Input
Bank select: Select to which internal bank a command is being applied.
DQ[31:0]
Data Input / Output: The DQ signals form the 32 bit data bus. During READ commands the
Input/
data is referenced to both edges of DQS/DQS#. During WRITE commands the data is
Output
sampled at both edges of CK.
DQSx,
DQSx#
Data read strobes : DQSx and DQSx# are the differential data read strobes. During
READs, they are transmitted by the RLDRAM and edge-aligned with data. DQSx is ideally
Output 180 degrees out of phase with DQSx#. DQS0, DQS0# are aligned with DQ0-DQ7. DQS1,
DQS1# are aligned with DQ8-DQ15. DQS2, DQS2# are aligned with DQ16-DQ23. DQS3,
DQS3# are aligned with DQ24-DQ31.
DVLD
Output
Data Valid: The DVLD indicates valid output data. DVLD is edge-aligned with DQSx,
DQSx#.
DM0, DM1
Input
Data Mask: DM0 and DM1 are the input masks for WRITE data. The first half of the Input
data burst is masked when DM0 is sampled HIGH along with the WRITE command. The
second half of the input data burst is masked when DM1 is sampled HIGH along with the
WRITE command.
TCK
Input
IEEE 1149.1 Clock Input: JEDEC standard 1.8V IO levels. These pin must be tied to VSS
if the JTAG function is not used in the circuit.
TMS, TDI
Input
IEEE 1149.1 Test Inputs: JEDEC standard 1.8V IO levels. These pins may be left not
connected if the JTAG function is not used in the circuit.
TDO
Output IEEE 1149.1 Test Output: JEDEC standard 1.8V IO level tracking VDDQ.
VREF
Supply
Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input
buffers.
VEXT
Supply
Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions
for range.
VDD
Supply
Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions
for range.
VDDQ
Supply
Power Supply: Isolated Output Buffer Supply. 1.8V nominal. See DC Electrical
Characteristics and Operating Conditions for range.
VSS
VSSQ
Version 1.60
Supply Power Supply: GND
Supply Power Supply: Isolated Output Buffer Supply. GND
Page 9
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Table 2
Ball description
Ball
Type
NC
-
Version 1.60
Detailed Function
No Connect : These pins may be connected to ground to improve heat dissipation.
Page 10
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.4
Functional Block Diagram
Figure 4
Functional Block Diagram 8M x 32 Configuration
A0-A18, B0, B1, B2
Note:
Column Address Buffer
Row Address Buffer
Refresh Counter
Memory Array
Memory Array
Bank 1
Column Decoder
Memory Array
Bank 0
Bank 2
Sense Amp and Data Bus
Memory Array
Column Decoder
Row Decoder
Sense Amp and Data Bus
Row Decoder
Column Decoder
Row Decoder
Sense Amp and Data Bus
Row Decoder
Bank 3
Memory Array
Memory Array
Memory Array
VREF
DM1
DM0
REF#
DQ0-DQ31
Bank 7
Control Logic and Timing Generators
CS#
DQS[3:0], DQS#[3:0]
Output Buffers
WE#
DVLD
Input Buffers
AS#
Data read strobe
Bank 6
CK
Output Data Valid
Bank 5
CK#
Bank 4
Column Decoder
Memory Array
Sense Amp and Data Bus
Row Decoder
Column Decoder
Row Decoder
Sense Amp and Data Bus
Row Decoder
Column Decoder
Row Decoder
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
Column Address
Counter
When the BL4 setting is used, A18 is a "Don’t Care"
Version 1.60
Page 11
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Figure 5
Functional Block Diagram 16M x 16 Configuration
A0-A19, B0, B1, B2
Column Address Buffer
Row Address Buffer
Refresh Counter
Memory Array
Memory Array
Bank 1
Column Decoder
Memory Array
Bank 0
Bank 2
Sense Amp and Data Bus
Memory Array
Column Decoder
Row Decoder
Sense Amp and Data Bus
Row Decoder
Column Decoder
Row Decoder
Sense Amp and Data Bus
Row Decoder
Bank 3
Memory Array
Memory Array
Memory Array
VREF
DM1
DM0
REF#
DQ0-DQ15
Bank 7
Control Logic and Timing Generators
CS#
DQS[1:0], DQS#[1:0]
Output Buffers
WE#
DVLD
Input Buffers
AS#
Data read strobe
Bank 6
CK
Output Data Valid
Bank 5
CK#
Bank 4
Column Decoder
Memory Array
Sense Amp and Data Bus
Row Decoder
Column Decoder
Row Decoder
Sense Amp and Data Bus
Row Decoder
Column Decoder
Row Decoder
Sense Amp and Data Bus
Column Decoder
Column Decoder
Sense Amp and Data Bus
Sense Amp and Data Bus
Column Address
Counter
Note: 1 When the BL4 setting is used, A19 is a "Don’t Care".
Note: 2 In the 16Mx16 configuration, only DQS[1:0] & DQS#[1:0] are used
Version 1.60
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.5
Commands
1.5.1
Command Table
According to the functional signal description the following command sequences are possible. All input
states or sequences not shown are illegal or reserved. All command and address inputs must meet setup
and hold times around the rising edge of CK.
Table 3
Truth table
Operation
Device
State
No Operation
Any
Deselect4)
Any
Mode Register Set2)
Idle
Code
NOP
MRS
CS#
AS#
WE# REF#
A[19:0]1)3)
BA]2:0]
DM]1:0]
L
H
H
H
X
X
X
H
X
X
X
X
X
X
L
L
L
L
Valid
X
X
Read
Any
READ
L
L
H
H
Valid
Valid
X
Write
Any
WRITE
L
L
L
H
Valid
Valid
Valid
Auto Refresh
Idle
L
H
H
L
X
Valid
X
Note: 1: X = “Don’t Care” ; H = Logic HIGH; L = Logic LOW
Note: 2: Only A[17:0] are used for the MRS command.
Note: 3: See Table 4
Table 4
Address Width table
Data Width
32
16
BL 2
A[18:0]
A[19:0]
BL 4
A[17:0]
A[18:0]
Burst Length
Note: 1: The x32 and x16 configurations have different ballouts (see Fig. 2 & Fig. 3)
Version 1.60
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.5.2
Description of Commands
Table 5
Description of Commands
Command Description
DESEL /
NOP
The NOP command is used to perform a no operation to the RLDRAM; this is equal to deselecting
the chip. Use NOP command to prevent unwanted commands from being registered during idle
or wait states. Operations already in progress are not affected. Output values depend on
command history.
MRS
The Mode Register is set via the address inputs A[17:0]. See the mode register description in the
register description section. The MRS command can only be issued when all banks are idle and
no bursts are in progress.
READ
The READ command is used to initiate a burst read access to a bank. The value on the BA[2:0]
inputs selects the bank, and the address provided on inputs A[19:0] selects the data location
within the bank.
WRITE
The WR command is used to initiate a burst write access to a bank. The value on the BA[2:0]
inputs selects the bank, and the address provided on inputs A[19:0] selects the data location
within the bank. Input data appearing on the DQs is written to the memory array subject to the
DMx input logic levels appearing coincident with the WRITE command. If DM0 is registered LOW,
the first half of the burst Write data will be written to the memory array, if registerd HIGH this data
will be ignored i.e, this part of the data word will not be written. If DM1 is registered LOW the
second half of the burst Write data will be written to the memory array, if registerd HIGH this data
will be ignored i.e, this part of the data word will not be written.
AREF
The AREF is used during normal operation of the RLDRAM to refresh the memory content of a
bank. The value on the BA[2:0] inputs selects the bank. The refresh address is generated by the
internal refresh controller. This makes the address bits “Don’t Care” during an AREF command.
The RLDRAM requires 64k AREF cycles at an average periodic interval of 0.49 µs1) (maximum).
To improve efficiency a burst of eight AREF commands (One AREF for each bank) can be posted
to the RLDRAM at an average periodic interval of 3.9µs2).
Note: 1: Actual refresh is 32ms/8K/8 = 0.488µs
Note: 2: Actual refresh is 32ms/8K = 3.90µs
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HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2
Functional Description
2.1
Clocks, Commands and Addresses
Figure 6
Clock Command/Address Timings
tCKH
tCK
tCKL
CK#
CK
CMD,
ADDR
Vaild
Vaild
Vaild
tAS, tCS
tAH, tCH
Don't Care
Table 6
General Timing Parameters for -2.5, -3.3 and -5.0 ns speed sorts
-3.3
Parameter
Symbol
-4.0
-5.0
Units
min
max
min
max
min
max
tCK
3.3
-
4.0
-
5.0
-
ns
Clock high level width
tCKH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCKL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
1.0
–
1.0
–
1.0
–
ns
1.0
–
1.0
–
1.0
–
ns
Clock
Clock Cycle Time
Setup Times
Address/Command input setup time tAS, tCS
Hold Times
Address/Command input hold time
tAH, tCH
Note: 1. All timings are measured relatively to the crossing point of CK/CK# and to the crossing point with VREF of the Command and
Address signals.
Note: 2. The signal imput slew rate must be ≥ 1V/ns.
Note: 3. CK/CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.2
Initialization
The RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation or permanent damage to the device.
The following sequence is used for Power-Up:
1. Apply power (VEXT, VDD, VDDQ, VREF) and start clock as soon as the supply voltages are stable. Apply
VDD and VEXT before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF.
There is no timing relation between VEXT and VDD, the chip starts the power up sequence only when
both voltages are at their nominal level. However, the pad supply must not be applied before the core
supplies. Maintain all pins in NOP conditions.
2. Maintain stable conditions for 200 µs minimum.
3. Issue three Mode Register Set commands - 2 dummies plus 1 valid MRS (Figure 7).
4. After tMRSC issue 8 Auto Refresh commands, one on each bank and separated by 2048 cycles.
5. After tRC the chip is ready for normal operation.
Figure 7
Power Up Sequence
VEXT
VDD
VDDQ
VREF
CK#
CK
Com.
MRS
MRS
MRS
Add
tMRSC
min. 200 µs
RF
RF
RF
BA0
BA1
BA7
min. 2048 6 x 2048
cycles
cycles
MRS:
RF:
A.C.:
A.C.
tRC
MRS command
REFRESH
Any command
Don't Care
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.3
Mode Register Set Command (MRS)
The mode register stores the data for controlling the operating modes of
the memory. It programs the RLDRAM configuration, burst length, test
mode and IO options. During a Mode Register Set command the address
inputs A<17:0> are sampled and stored in the mode register. tMRSC
must be met before any command can be issued to the RLDRAM. The
mode register may be set anytime as long as all command are
completed, and the RLDRAM is in an idle state (no persistent
commands).
Figure 8
Mode Register Set
CK#
CK
CS#
AS#
Figure 9
Mode Register Set Timing
WE#
CK#
CK
Command
REF#
MRS
NOP
NOP
A.C.
COD
A[17:0]
tMRSC
A[19:18]
MRS:
command
MRS
A.C.:
Any command
BA<2:0>
Don't Care
COD: Code to be loaded into
the register
Table 7
Timing Parameters MRS
Don't Care
-3.3
Parameter
Symbol
Mode Register Set cycle time
-4.0
-5.0
min max min max min max
4
tMRSC
–
4
–
4
–
Units
Notes
tCK
Figure 10 Mode Register Bitmap
A2
A<17:7>
A6
A5
A4
A3
Reserved2
Test Mode
Driver
Strength
Matched
Mode
Burst
Length
A1
A0
RLDRAM Configuration
A5
Driver Strength1
A3
Burst Length
A2
A1
A0
RLDRAM
configuration
0
8mA (default)
0
2 (default)
0
0
0
3 (default)
1
Do not use
1
4
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
Do not use
A6
Test Mode
A4
Matched Mode
0
(default)
0
inactive (default)
1
0
1
1
test mode
1
active3
1
1
0
Do not use
1
1
1
Do not use
Note: 1 HSTL compliant current specification
Note: 2 Bits A<17:6> must be set to zero
Note: 3 Automatic IO impedance calibration is activated in Matched Mode
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.4
Configuration Table
The following table shows, for different operating frequencies, the different RLDRAM configurations that can
be programmed into the Mode Register. The Read Latency (tRL) and the Write Latency (tWL) used by the
RLDRAM for the two Burst Lengths (BL) are also indicated. Finally the minimum row cycle time (tRC) in clock
cycles and in ns are shown as well. The shaded areas correspond to configurations that are not allowed.
Table 8
RLDRAM configuration table
Configuration
Frequency
300 MHz (-3.3)
250 MHz (-4.0)
200 MHz (-5.0)
Unit
1
2
3
4
tRC
cycles
5
6
7
8
tRL
cycles
5
5
5
6
tWL (BL2)
cycles
2
2
2
3
tWL (BL4)
cycles
1
1
1
tRC
ns
26.7
tRL
ns
20
tWL (BL2)
ns
10
tWL (BL4)
ns
tRC
ns
28.0
32.0
tRL
ns
20.0
24.0
tWL (BL2)
ns
8.0
12.0
tWL (BL4)
ns
4.0
8.0
tRC
ns
25.0
30.0
35.0
40.0
tRL
ns
25.0
25.0
25.0
30.0
tWL (BL2)
ns
10.0
10.0
10.0
15.0
tWL (BL4)
ns
5.0
5.0
5.0
10.0
2
6.7
Note: 1: The speed sort -3.3 provides parts functional up to 300MHz in the configuration 4 only. The functionality of the configurations
1,2 and 3 is not guaranteed for speed sort -3.3.
Note: 2: The speed sort -4.0 provides parts functional up to 250MHz in the configurations 3 and 4 only. The functionality of the
configurations 1 and 2 is not guaranteed for speed sort -4.0.
Note: 3: The speed sort -5.0 provides parts functional in all configurations.
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HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.5
Writes (WR)
2.5.1
Write - Basic Information
Figure 11
Write command
CK#
Write accesses are initiated with a WRITE command, as shown in
Figure 11. Row and bank addresses are provided together with the
WRITE command.
CK
CS#
During WRITE commands, data will be registered at both edges of CK
according to the programmed burst length BL. The first valid data is
registered with the first rising CK edge WL (Write Latency) cycles after
the WRITE command has been issued.
AS#
Any WRITE burst may be followed by a subsequent READ command.
Figure 17 and Figure 18 illustrate the timing requirements for a WRITE
followed by a READ for a burst of 2 and 4 respectively.
WE#
REF#
Setup and hold time for incoming DQs relative to the CK edges are
specified as tDS and tDH.
The first or the second part of the incoming data burst is masked if the
corresponding DMx signal is sampled HIGH along with the WRITE
command. Setup and hold time for DM is the same as for addresses
and commands.
DM[1:0]
DM
A[19:0]
A
BA[2:0]
BA
A:
BA:
DM:
Address
Bank Address
Data Mask
Don't Care
Figure 12 Basic Write Burst Timing
CK#
CK
Write Latency
tDS
DQ
tDH
tDS
D0
D1
D2
tDH
D3
Don't Care
Table 9
WRITE Timing Parameters
-3.3
Parameter
Symbol
-4.0
-5.0
min
max
min
max
min
max
Units
Data-in to CK Setup Time
tDS
0.5
–
0.5
–
0.5
–
ns
Data-in to CK Hold Time
tDH
0.5
–
0.5
–
0.5
–
ns
Notes
Note: 1. All timings are measured relatively to the crossing point of CK/CK# and to the crossing point with VREF of the Command and
Address signals.
Note: 2. The signal imput slew rate must be ≥ 1V/ns.
Note: 3. CK/CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
Version 1.60
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HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.5.2
Write - Cyclic Bank Access
2.5.2.1 Burst Length (BL) = 2
Figure 13 Write Burst Basic Sequence, BL = 2, WL = 3
0
1
2
3
4
5
6
7
8
Com
WR
WR
WR
WR
WR
WR
WR
WR
WR
Add
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA6
A
BA7
A
BA0
CK#
CK
WL = 3
D0a
DQ
D0b
D1a
D0d
D1b
D2a
D2b
D3a
D3b
A/BAx:
WR:
Dxy:
WL:
D4a
D4b
D5a
address A of bank x
WRITE
Data part y to bank x
Write Latency
Don't Care
2.5.2.2 Burst Length (BL) = 4
Figure 14 Write Burst Basic Sequence, BL = 4, WL = 2
0
1
2
3
4
5
6
7
8
Com
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
Addr
A
BA0
CK#
CK
A
BA1
A
BA2
A
BA3
A
BA0
WL = 2
DQ
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
D3a
A / BAx:
WR:
address A of bank x
WRITE
Dxy:
WL:
Data part y to bank x
Write Latency
Don't Care
Version 1.60
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.5.3
Write Data Mask Timing
2.5.3.3 Burst Length (BL) = 2
Figure 15 Write Data Mask Timing, BL = 2, WL = 2
0
1
2
3
4
5
6
7
8
Com
WR
WR
WR
WR
WR
WR
WR
WR
WR
Add
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA6
A
BA7
A
BA0
CK#
CK
DM0
DM1
WL = 2
D0a
DQ
D0b
D1b
D0d
D2a
D4a
D4b
D5a
A/BAx:
WR:
Dxy:
WL:
Data not written
into the memory
D5b
D6a
address A of bank x
WRITE
Data part y to bank x
Write Latency
Don't Care
2.5.3.4 Burst Length (BL) = 4
Figure 16 Write Data Mask Timing, BL=4, WL = 1
0
1
2
3
4
5
6
7
8
Com
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
Addr
A
BA0
CK#
CK
A
BA1
A
BA2
A
BA3
A
BA0
DM0
WL = 1
DM1
DQ
D0a
D0b
D0c
D0d
D1c
D1d
D2a
D2b
Data not written
into the memory
A / BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
Don't Care
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HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.5.4
Write followed by Read
2.5.4.5 Burst Length (BL) = 2
Figure 17 Write followed by Read BL = 2, RL = 5, WL = 2
0
1
2
3
4
5
6
7
8
9
Com
WR
RD
RD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Addr
A
BA0
A
BA1
A
BA2
CK#
CK
WL = 2
RL = 5
tCKDQS
D0a
DQ
D0b
Q1a Q1b Q2a
Q2b
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
RD:
Qxy:
RL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
READ
Data part y of bank x
Read Latency
Don't Care
2.5.4.6 Burst Length (BL) = 4
Figure 18 Write followed by Read BL = 4, RL = 5, WL = 1
0
1
2
3
4
5
6
7
8
9
Com
WR
RD
NOP
RD
NOP
NOP
NOP
NOP
NOP
NOP
Addr
A
BA0
A
BA1
CK#
CK
A
BA1
WL = 1
RL = 5
tCKDQS
DQ
D0a
D0b
D0c
D0d
Q1a
Q1b
Q1c
Q1d
Q2a
Q2b
Q2c
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
Version 1.60
Page 21
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y of bank x
Read Latency
Don't Care
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.6
Reads (RD)
2.6.1
Read - Basic Information
Figure 19
READ command
CK#
Read accesses are initiated with a READ command, as shown in
Figure 19. Row and bank addresses are provided with the READ
command.
CK
CS#
During READ bursts the memory device drives the read data edge
aligned with the DQS signal. After a programmable read latency, data
is available at the outputs. The data valid signal indicates that valid
read data will be present on the bus after 0.5clock cycles.
AS#
The skew between DQS and CK is specified as tCKDQS.
WE#
tQSQ is the skew between DQS edge and the last valid data edge.
tQSQ is derived at each DQS clock edge and is not cumulative over
time.
REF#
After completion of a burst, assuming no other commands have been
initiated, output data will go High-Z. Back to back READ commands are
possible, producing a continuous flow of output data.
A<19:0>
A
The data valid window is derived for each DQS transition and is defined
as: min(tDQSH, tDQSL) - 2* tQSQmax.
BA<2:0>
BA
Any READ burst may be followed by a subsequent WRITE command.
Figure 23 shows the corresponding timing requirements for a READ
followed by a WRITE. A READ to WRITE delay has to be buit in in order
to prevent bus contention. Some systems having long line lengths or
severe skews may need additional idle cycles inserted.
A:
BA:
Address
Bank Address
Don't Care
Figure 20 Basic Read Burst Timing
tCKH
tCKL
tCK
CK#
CK
tDQSL
tCKDQS
tDQSH
DQS
DQS#
tQSVLD
tQSVLD
DVLD
DQ
D0
tQSQ
D1
D2
D3
tQSQ
data
valid
window
Version 1.60
Page 22
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Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Table 10 READ Timing Parameters for -2.5, -3-3 and -5.0 speed sorts
Parameter
-3.3
Symbol
min
-4.0
max
min
Units Notes
-5.0
max
min
max
Read Cycle Timing Parameters for Data and Data Strobe
DQS / DQS# high pulse width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS / DQS# low pulse width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS edge to Clock edge skew
tCKDQS
2.9
3.9
2.9
3.9
2.9
3.9
ns
DQS edge to output data edge
tQSQ
-0.35
0.35
-0.35
0.35
-0.35
0.35
ns
0.4
ns
0.4
ns
DQS edge to Data Out HiZ
tQSQHZ
DQS edge to DVLD edge
tQSVLD
0.4
-0.4
0.4
0.4
-0.4
0.4
-0.4
4
Note: 1 All timings are measured relatively to the crossing point of CK/CK# (DQSx/DQSx#), and to the crossing point with VREF of
the Command and Address signals.
Note: 2. The signal imput slew rate must be ≥ 1V/ns.
Note: 3. CK/CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
Note: 4. tDQSQ and tQSQHZ are absolute values.
Version 1.60
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.6.2
Read - Cyclic Bank Access
2.6.2.1 Burst Length (BL) = 2
Figure 21 Read Burst, BL = 2, RL = 5
0
1
2
3
4
5
6
7
8
Com.
RD
RD
RD
RD
RD
RD
RD
RD
RD
Addr.
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA6
A
BA7
A
BA0
CK#
CK
tCKDQS
RL = 5
DQS
DQS#
DQ
Q0a
Q0b
Q1a
Q1b
Q2a
Q2b
A / BAx:
address A of bank x
RD:
Qxy:
RL:
READ
Data part y from bank x
Read Latency
Q3a
Don't Care
2.6.2.2 Burst Length (BL) = 4
Figure 22 Read Burst, BL = 4, RL = 5
0
1
2
3
4
5
6
7
8
Com.
RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
Addr.
A
BA0
CK#
CK
A
BA1
A
BA2
A
BA3
A
BA0
tCKDQS
RL = 5
DQS
DQS#
DQ
Q0a
Q0b
Q0c
A / BAx:
RD:
Qxy:
RL:
Q0d
Q1a
Q1b
Q1c
address A of bank x
READ
Data part y from bank x
Read Latency
Don't Care
Version 1.60
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This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.6.3
Read followed by Write
Figure 23 Read followed by Write, BL=2, RL = 5, WL = 2
0
1
2
3
4
5
6
7
8
Com.
RD
NOP
NOP
NOP
NOP
WR
WR
NOP
NOP
Addr.
A
BA0
A
BA1
A
BA2
CK#
CK
WL = 2
RL = 5
tCKDQS
DQ
Q0a
Q0b
D1a
D1b
D2a
D2b
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
RD:
Qxy:
RL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
READ
Data part y from bank x
Read Latency
Don't Care
Figure 24 Read followed by Write, Write data on bus prior Read data, BL=2, RL=5, WL=2
0
1
2
3
4
5
6
7
8
Com.
RD
WR
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Addr.
A
BA0
A
BA1
CK#
CK
WL = 2
RL = 5
tCKDQS
DQ
D1a
D1b
Q0a
Q0b
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
Version 1.60
Page 25
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y from bank x
Read Latency
Don't Care
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Figure 25 Read followed by Write, BL=4, RL = 5, WL = 1
0
1
2
3
4
5
6
7
8
9
10
Com.
RD
NOP
NOP
NOP
NOP
NOP
NOP
WR
NOP
NOP
Addr.
A
BA0
D1a
D1b D1c
CK#
CK
NOP
A
BA1
WL = 1
RL = 5
tCKDQS
DQ
Q0a
Q0c
Q0b
Q0d
D1d
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y from bank x
Read Latency
Don't Care
Figure 26 Read followed by Write, write data on system bus prior read data, BL=4, RL=5, WL=1
0
1
2
3
4
5
6
7
8
Com.
RD
WR
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Addr.
A
BA0
A
BA1
CK#
CK
WL = 1
RL = 5
tCKDQS
DQ
D1a
D1b
D1c
D1d
Q0a
Q0b
Q0c
Q0d
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
Version 1.60
Page 26
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y from bank x
Read Latency
Don't Care
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3
IEEE 1149.1 Serial Boundary Scan (JTAG)
The RLDRAM incorporates a serial boundary scan Test Access Port (TAP). This port operates fully
complient with IEEE Standard 1149.1-1990. It contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID code register.
It is possible to operate the RLDRAM without using the JTAG feature. To disable the TAP controller, TCK
must be tied low while TDI, TMS and TDO may be left unconnected. Upon power-up, the TAP will come up
in a reset state which will not interfere with the normal operation of the device.
3.1
Test Access Port (TAP)
3.1.1
Test Clock (TCK)
The test clock is used only with the TAP controller. The pin must be tied low if the TAP is not used.
3.1.2
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK.
This pin may be left unconnected if the TAP is not used.
3.1.3
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most
significant bit (MSB) of any register (see Figure 27). This pin may be left unconnected if the TAP is not used.
3.1.4
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon
the current state of the TAP state machine (see Figure 28). The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register (see Figure 27). This pin may be left
unconnected if the TAP is not used.
3.2
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and shifted out
of the RLDRAM test circuitry (see Figure 27). Only one register is selected at a time through the instruction
register. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
3.2.1
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in Figure 27. Upon power-up, the instruction register is
internally preloaded with the IDCODE instruction.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01"
pattern to allow for fault isolation of the board-level serial test data path.
3.2.2
Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO pins. This allows
data to be shifted through the RLDRAM with minimal delay.
The bypass register is set LOW during the Capture-DR state when the BYPASS instruction is loaded in the
instruction register.
Version 1.60
Page 27
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.2.3
Boundary Scan Register
The boundary scan register is connected to all the IO pins on the RLDRAM. It allows to observe and control
the data flowing into and out of the device, depending on the instruction being loaded in the instruction
register.
The boundary scan register is 104 bits long. The register is the same for the x16 and x32 configurations of
the RLDRAM. Pins not used in the x16 configurations read a HIGH into the boundary scan register in the
Capture-DR controller state.
Differential inputs (CK/CK#) and outputs (DQSx/DQSx#) are equipped with two boundary scan cells each.
Thus, the differential nature of these pins is not visible to the test circuitry. However, it is recommended that
during testing differential signals are always applied to these pin pairs.
3.2.4
Identification (ID) Register
The ID register is loaded with a hardwired, vendor-specific, 32-bit code during the Capture-DR state when
the IDCODE instruction is loaded in the instruction register. The code can be shifted out when the TAP
controller is in the Shift-DR state. Two different codes are implemented for the x16 and x32 configurations
of the RLDRAM (see Table 11).
.
Table 11 ID Register Definition
Revision
Number
Part Number
Infineon JEDEC Code
L
S
B
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x16 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1
x32 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1
3.3
TAP Instructions
The TAP implements the 6 instructions BYPASS, EXTEST, SAMPLE/PRELOAD and IDCODE for user
access (see Table 12). The implementation of these instructions fully complies with the IEEE standard. All
other instructions are reserved and should not be used.
Table 12 JTAG Instruction Register
Instruction Register
Code
Instruction
Description
EXTEST
Selects the boundary scan register to be connected between TDI
and TDO. Data received at input pins are sampled and loaded into
the boundary scan register. Data driven by output pins are
determined from values contained in the boundary scan register.
Hex
x7 .. x0
00
0000 0000
05
0000 0101
21
0010 0001
IDCODE
Selects the ID code register to be connected to TDI and TDO.
Instructin does not interfere with the normal operation of the device.
FF
1111 1111
BYPASS
Selects the bypass register to be connected between TDI and TDO.
Instruction does not interfere with the normal operation of the
device.
Version 1.60
SAMPLE / PRELOAD Selects the boundary scan register to be connected between TDI
and TDO. Data receivedat input pins are sampled and loaded int the
boundary scan register. initial ouput data are shifted into the
boundary scan register prior to an EXTEST intruction. Instruction
does not interfere with the normal operation of the device.
Page 28
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.4
Boundary Scan Exit Order
3.4.1
x16 Configuration
Note:
Note:
Note:
Note:
Pin
Descr
.
Pin
Name
Ball #
Ball #
Pin
Name
Pin
Descr
.
Reg
Content
Scan
Reg #
I/O
DQ1
B10
B3
DQ9
I/O
Enb
Data
78
79
I/O
DQ0
B11
B2
DQ8
I/O
I/O
DQ3
C10
C3
DQ11
I/O
Enb
Data
Enb
Data
Enb
Data
80
81
82
83
84
85
Data
Data
Enb
Data
Enb
Data
86
87
88
89
90
91
Enb
Data
Enb
Data
Data
Data
Data
Data
Data
Data
Data
Data
92
93
94
95
96
97
98
99
100
101
102
103
Data
Data
Data
Data
Data
Data
Data
Data
Enb
Data
Enb
Data
Enb
Data
Enb
Data
Data
Data
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Enb
Data
Enb
Data
Enb
Data
18
19
20
21
22
23
Enb
Data
24
25
Scan
Reg#
Reg
Content
77
76
75
74
Data
Enb
Data
Enb
73
72
71
70
69
Data
Enb
Data
Enb
Data
68
67
66
65
64
63
62
Data
Data
Enb
Data
Enb
Data
Enb
61
60
Data
Enb
I/O
59
58
57
56
55
54
53
52
Data
Data
Data
Data
Data
Data
Data
Data
O
I
I
I
I
I
I
I
51
50
49
48
47
46
45
44
43
42
41
40
Data
Data
Data
Data
Data
Data
Data
Data
Data
Enb
Data
Enb
I
I
I
I
I
I
I
I
39
38
37
36
35
34
33
32
Data
Enb
Data
Enb
Data
Data
Data
Enb
31
30
29
28
27
26
Data
Enb
Data
Enb
Data
Enb
I/O
DQ2
C11
C2
DQ10
I/O
O
DQS0#
D10
O
DQS0
D11
D3
D2
DQS1#
DQS1
O
O
I/O
DQ4
E11
E2
DQ12
I/O
I/O
DQ5
E10
E3
DQ13
I/O
I/O
DQ6
F11
F2
DQ14
I/O
DQ7
F10
F3
DQ15
I/O
DVLD
A1
A2
A0
A3
A4
B0
CK
F12
G11
G10
G12
H12
H11
J11
J12
F1
G2
G3
G1
H1
H2
J2
J1
DM0
A6
A7
A5
A8
A9
B2
AS#
I
I
I
I
I
I
I
I
CK#
B1
A14
A13
A10
A12
A11
A18
K12
K11
L11
L12
M12
M10
M11
N12
K1
K2
L2
L1
M1
M3
M2
N1
WE#
REF#
CS#
A19
A15
A17
A16
DM1
I
I
I
I
I
I
I
I
I/O
DQ31
N10
N3
DQ23
I/O
I/O
DQ30
N11
N2
DQ22
I/O
I/O
DQ29
P10
P3
DQ21
I/O
I/O
DQ28
P11
P2
DQ20
I/O
O
O
DQS3
DQS3#
R11
R10
R2
R3
DQS2
DQS2#
O
O
I/O
DQ26
T11
T2
DQ18
I/O
I/O
DQ27
T10
T3
DQ19
I/O
I/O
DQ24
U11
U2
DQ16
I/O
I/O
DQ25
U10
U3
DQ17
I/O
1: Input pins are connected to Observe-Only Boundary Scan Register Cells.
2: Output pins are connected to Force-Only Boundary Scan Register Cells.
3: IO pins are connected to Control-and-Observe Boundary Scan Register Cells.
4: For BL 4 the content of the register 101 will be set to 0 if A19 is not connected. Otherwise, the register content will be equal
to the logical value applied to pin A19.
Version 1.60
Page 29
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.4.2
Note:
Note:
Note:
Note:
x32 Configuration
Scan
Reg#
Reg
Content
77
76
75
74
73
72
71
70
Data
Enb
Data
Enb
Data
Enb
Data
Enb
69
68
67
66
Data
Data
Data
Enb
65
64
63
62
Data
Enb
Data
Enb
61
60
59
Data
Enb
Data
58
57
56
55
54
53
52
Pin
Descr
.
Pin
Name
Ball #
Ball #
Pin
Name
Pin
Descr
.
I/O
DQ1
B10
B3
DQ9
I/O
I/O
DQ0
B11
B2
DQ8
I/O
I/O
DQ3
C10
C3
DQ11
I/O
I/O
DQ2
C11
C2
DQ10
I/O
O
O
DQS0#
DQS0
D10
D11
D3
D2
DQS1#
DQS1
O
O
I/O
DQ4
E11
E2
DQ12
I/O
I/O
DQ5
E10
E3
DQ13
I/O
I/O
DQ6
F11
F2
DQ14
I/O
Reg
Content
Scan
Reg #
Enb
Data
Enb
Data
Enb
Data
78
79
80
81
82
83
Enb
Data
Data
Data
84
85
86
87
Enb
Data
Enb
Data
88
89
90
91
Enb
Data
Enb
Data
92
93
94
95
I/O
DQ7
F10
F3
DQ15
I/O
O
DVLD
F12
Data
Data
Data
Data
Data
Data
Data
I
I
I
I
I
I
I
A1
A2
A0
A3
A4
B0
CK
G11
G10
G12
H12
H11
J11
J12
F1
G2
G3
G1
H1
H2
J2
J1
DM0
A6
A7
A5
A8
A9
B2
AS#
I
I
I
I
I
I
I
I
Data
Data
Data
Data
Data
Data
Data
Data
96
97
98
99
100
101
102
103
51
50
49
48
47
46
45
44
43
42
Data
Data
Data
Data
Data
Data
Data
Data
Data
Enb
I
I
I
I
I
I
I
I
CK#
B1
A14
A13
A10
A12
A11
A18
K12
K11
L11
L12
M12
M10
M11
N12
K1
K2
L2
L1
M1
M3
M2
N1
WE#
REF#
CS#
A19
A15
A17
A16
DM1
I
I
I
I
I
I
I
I
I/O
DQ31
N10
N3
DQ23
I/O
41
40
39
38
37
36
Data
Enb
Data
Enb
Data
Enb
I/O
DQ30
N11
N2
DQ22
I/O
I/O
DQ29
P10
P3
DQ21
I/O
I/O
DQ28
P11
P2
DQ20
I/O
35
34
33
32
31
30
29
28
Data
Data
Data
Enb
Data
Enb
Data
Enb
O
O
DQS3
DQS3#
R11
R10
R2
R3
DQS2
DQS2#
O
O
I/O
DQ26
T11
T2
DQ18
I/O
I/O
DQ27
T10
T3
DQ19
I/O
Data
Data
Data
Data
Data
Data
Data
Data
Enb
Data
Enb
Data
Enb
Data
Enb
Data
Data
Data
Enb
Data
Enb
Data
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
I/O
DQ24
U11
U2
DQ16
I/O
27
26
Data
Enb
I/O
DQ25
U10
U3
DQ17
I/O
Enb
Data
Enb
Data
22
23
24
25
1: Input pins are connected to Observe-Only Boundary Scan Register Cells.
2: Output pins are connected to Force-Only Boundary Scan Register Cells.
3: IO pins are connected to Control-and-Observe Boundary Scan Register Cells.
4: For BL 4 the content of the register 101 will be set to 0 if A18 is not connected. Otherwise, the register content will be equal
to the logical value applied to pin A18.
Version 1.60
Page 30
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.5
TAP Operation
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while
the RLDRAM clock operates much faster. As a consequence, it is possible that an input or output will
undergo a transition right at the moment when the TAP takes the snapshot in the Capture-DR state of the
SAMPLE/PRELOAD instruction. The TAP may then try to capture a signal while in transition (metastable
state). This will not harm the device, but there is no guarantee as to the value that will be captured. To
guarantee that the boundary scan register will capture the correct value of a signal, the signal must meet the
TAP's setup and hold time ( tCS plus tCH) around the rising edge of TCK.
3.6
JTAG TAP Block Diagram
Figure 27 TAP Block Diagram
TMS
TCK
Test Access Port (TAP) Controller
0
Bypass Register
TDI
7
6
5
4
3
2
1
TDO
0
Instruction Register
31 30
1
0
ID Code Register
Version 1.60
103
0
102
1
Page 31
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.7
JTAG TAP Controller State Diagram
Figure 28 TAP Controller State Diagram
TM S
TCK
T e s t A c c e s s P o r t (T A P ) C o n tr o lle r
0
B y p a s s R e g is te r
TDI
7
6
5
4
3
2
1
TDO
0
In s tr u c tio n R e g is te r
31
30
1
0
ID C o d e R e g is te r
3.8
103
0
102
1
JTAG DC Operating Conditons
Parameter
Symbol
Limit Values
Unit Notes
min.
typ.
max.
Input logic high voltage, VTIH
DC
VREF
+ 0.15
-
VDDQ
+ 0.3
V
Input logic low voltage,
DC
VSSQ
-0.3
-
VREF
- 0.15
V
Output logic high
VTOH
voltage (IOH = -tbd mA)
VREF
+ tbd
-
-
V
Output logic low voltage VTOL
(IOL = tbd mA)
-
-
VREF
- tbd
V
Version 1.60
VTIL
Page 32
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.9
JTAG AC Operating Conditions
Parameter
Input logic high voltage, AC
Input logic low voltage, AC
Input Slew Rate
Input and Output Timing
Reference Level
3.10
min.
typ.
max.
Unit
VTIH
VTIL
VREF+0.3
VSSQ-0.3
-
V
-
VDDQ+0.3
VREF-0.3
V
TTSL
VREF
1.0
-
-
V/ns
VDDQ/2
Notes
V
JTAG AC Electrical Characteristics
Parameter
Symbol
min.
max.
Unit
TCK Cycle Time
TCK High Pulse Width
TTCK
TTCKH
20
-
ns
10
-
ns
TCK Low Pulse Width
TTCKL
10
-
ns
TCK Low to TDO Valid
TTCKDO
-
10
ns
TDI Set Up Time
TTDIS
TTMSS
5
-
ns
5
-
ns
TTDIH
TTMSH
5
-
ns
5
-
ns
TMS Set Up Time
TDI Hold Time
TMS Hold Time
3.11
Symbol
Notes
JTAG Timing Diagram
TTCK
TTCKH TTCKL
TCK
TTMSH
TTMSS
TTDIH
TTDIS
TMS
TDI
TTCKDO
TDO
Version 1.60
Page 33
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
z
z
z
z
z
z
z
Storage temperature range............................................– 55 to + 150 ° C
Input/output pins voltage........................................– 0.3 to VDDQ + 0.3V
Inputs and VREF voltage.......................................– 0.3 to VDDQ + 0.3V
Power supply voltage VDD ............................................... – 0.3 to + 2.1V
Power supply voltage VEXT ................................ ........... – 0.3 to + 2.8V
Power supply voltage VDDQ ............................................ – 0.3 to + 2.1V
Junction Temperature......................................................... 0°C to 100°C
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
4.2
Recommended Power & DC Operation Ratings
All values are recommended operating conditions unless otherwise noted.
Table 13 Power & DC Operating Conditions
Parameter
Symbol
min.
typ.
max.
Unit Notes
VEXT
2.38
2.5
2.63
V
VDD
1.75
1.8
1.85
V
Power Supply Voltage for I/O
VDDQ
1.75
1.85
1.95
V
Reference Voltage
Vref
0.9
IIL
IILC
0.51*
VDDQ
+5
V
Input leakage current
0.49*
VDDQ
-5
µA
-5
+5
µA
-5
+5
µA
-5
+5
µA
Power Supply Voltages
CLK Input leakage current
Output leakage current
VREF Current
IOL
IREF
1,2,3
Matched Impedance 1.8V
Input logic high voltage, DC
VIH
Vref + 0.15
–
VDDQ + 0.3 V
Input logic low voltage, DC
VIL
VSSQ - 0.3
–
Vref - 0.15 V
Output high voltage
VOH
VDDQ
-
-
V
Output low voltage
VOL
-
-
0
V
Input logic high voltage, DC
VIH
Vref + 0.1
–
Input logic low voltage, DC
VIL
VSSQ - 0.3
–
Output high voltage
VOH
VDDQ-0.4
-
-
V
Output low voltage
VOL
-
-
0.4
V
HSTL strong
Note:
Note:
Note:
Note:
VDDQ + 0.3 V
Vref - 0.1 V
1. Typically the value of Vref is expected to be 0.5 * VDDQ of the transmitting device. Vref is expected to track variations in VDDQ
2. Peak to peak AC noise on Vref may not exceed 2% Vref (DC)
3. Vtt of the transmitting device must track Vref of the receiving device.
4. Recommanded on board decouping capacitors : VDDQ: 2 x 0.1µF / device, VDD: 2 x 0.1µF / device, VREF : 0.1µF / device,
VEXT: 0.1µF / device.
Version 1.60
Page 34
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
4.3
AC Operation Ratings
Table 14 AC Operation Conditions for Matched Impedance mode
Parameter
Symbol
min.
typ.
max.
Unit
Input logic high voltage, AC DDR
VIH
Vref + 0.3
–
V
Input logic low voltage, AC DDR
VIL
VSSQ - 0.3
–
VDDQ + 0.3
Vref - 0.3
V
Clock Differential Input Voltage (CLK/ CLK#)
VID
0.6
–
VDDQ + 0.6
V
Clock Input Crossing Point (CLK/ CLK#)
VIX
Vref - 0.15
Vref
Vref + 0.15
V
I/O Reference Voltage
Vref
0.49*VDDQ
0.51*VDDQ
V
Input logic high voltage, AC DDR
VIH
Vref + 0.3
–
V
Input logic low voltage, AC DDR
VIL
VSSQ - 0.3
–
VDDQ + 0.3
Vref - 0.3
V
Clock Differential Input Voltage (CLK/ CLK#)
VID
0.6
–
VDDQ + 0.6
V
Clock Input Crossing Point (CLK/ CLK#)
VIX
Vref
Vref - 0.15
Vref
0.49*VDDQ
Notes
Matched Impedance 1.8V
HSTL strong
I/O Reference Voltage
4.4
Vref + 0.15
V
0.51*VDDQ
V
Output Test Conditions
Figure 29 Output Test Circuits
+ Vtt = 0.5 x V DDQ
50 Ohm
Test point
DQ
Test point
DQ
10 pF
20 pF
HSTL
Matched Impedance Mode
Note: VDDQ=1.8V ±0.1V, TJ = 0 ° C to 100 ° C
4.5
Pin Capacitances
Table 15 Pin Capacitances
Pin
A<19:0>, BA<2:0>, CS#, AREF#, WE#
Min
2.0
Typ.
3.0
Max
4.0
Unit
pF
CLK, CLK#
2.0
3.0
4.0
pF
DQ<31:0>, DQS0, DQS0#, DQS1, DQS1#, DVLD, DM
2.0
3.0
4.0
pF
Version 1.60
Page 35
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
4.6
Operating Currents
Table 16 IDD Specifications and Conditions (these values are preliminary and will change)
Parameter
IDD1 (*)
Operating Current
(Average Power
Supply Current)
IDD4R (*)
Operating Current
(Average Power
Supply Current)
IDD8 (*)
Operating Current
(Average Power
Supply Current)
Version 1.60
x16
x32
Unit
Notes
Burst Length = 2
tCK=min, tRC=min,
1 bank active,
Address change one time
during min tRC,
Read/Write command
cycling1.)
Burst Length = 4
tCK=min, tRC=min,
4 banks interleave,
address change with
each bank activation,
continuous read
operation 1.)
Burst Length = 2
tCK=min, tRC=min,
8banks interleave,
address change with
each bank activation,
continuous read
operation 1.)
300MHz
VDD
VEXT
tbd
tbd
tbd
tbd
mA
mA
250MHz
VDD
VEXT
205
tbd
tbd
tbd
mA
mA
200MHz
VDD
VEXT
200
85
230
85
mA
mA
300MHz
VDD
VEXT
tbd
tbd
tbd
tbd
mA
mA
250MHz
VDD
VEXT
500
75
tbd
tbd
mA
mA
200MHz
VDD
VEXT
415
115
480
115
mA
mA
300MHz
VDD
VEXT
tbd
tbd
tbd
tbd
mA
mA
250MHz
VDD
VEXT
435
135
tbd
tbd
mA
mA
200MHz
VDD
VEXT
375
115
480
115
mA
mA
300MHz
VDD
VEXT
tbd
tbd
tbd
tbd
mA
mA
250MHz
VDD
VEXT
150
75
tbd
tbd
mA
mA
200MHz
VDD
VEXT
120
75
135
80
mA
mA
300MHz
VDD
VEXT
tbd
tbd
tbd
tbd
mA
mA
250MHz
VDD
VEXT
155
135
tbd
tbd
mA
mA
200MHz
VDD
VEXT
125
120
135
tbd
mA
mA
Standby Current
Auto Refresh Current
Limit Values
Symbol/
Freq
Page 36
tCK=min
All banks idle, CS=1
address/data toggling
one time/4 clk clock
inputs
tCK=min
All banks idle, CS=1
64k refresh commands/
32ms
Infineon Technologies
This specification is preliminary and subject to change without notice