INFINEON PSB21381

Data She et, DS 1, M arch 2001
SCOUT-S
S i e m e n s C o d e c w i t h S /T
Transceiver
PSB 21381/2 Version 1.3
SCOUT-SX
Siemens Codec with S/T
Transceiver Featuring
S p e a k e r p h o n e F u n c t i o n a l it y
PSB 21383/4 Version 1.3
Wired
Communications
N e v e r
s t o p
t h i n k i n g .
Edition 2001-03-12
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data She et, DS 1, M arch 2001
SCOUT-S
S i e m e n s C o d e c w i t h S /T
Transceiver
PSB 21381/2 Version 1.3
SCOUT-SX
Siemens Codec with S/T
Transceiver Featuring
S p e a k e r p h o n e F u n c t i o n a l it y
PSB 21383/4 Version 1.3
Wired
Communications
N e v e r
s t o p
t h i n k i n g .
PSB 21381/2
PSB 21383/4
Revision History:
2001-03-12
Previous Version:
09.99
Page
Subjects (major changes since last revision)
35
Figure with clock signals added
67
BCL=’ 0’ changed to BCL=’1’
90
BCL changed from ’low’ to ’high’
118
Note regarding AXI input added
169
170
BCL is inverted compared to last description (DS1); figure added
173
’Rising’ BCL edge changed to ’falling’ edge
245
Figure 95 modified
250
251
Timings added
251
Power supply currents added
DS 1
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PSB 21381/2
PSB 21383/4
Table of Contents
Page
1
1.1
1.2
1.3
1.4
1.5
1.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Definitions and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . . .20
2
2.1
2.1.1
2.1.1.1
2.1.2
2.1.3
2.1.4
2.2
2.2.1
2.2.2
2.2.2.1
2.2.3
2.2.3.1
2.2.3.2
2.2.4
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
2.2.4.5
2.2.4.6
2.2.5
2.2.5.1
2.2.6
2.2.7
2.2.7.1
2.2.7.2
2.2.8
2.3
2.3.1
2.3.2
2.3.3
2.3.3.1
2.3.4
2.3.5
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Microcontroller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
IOM-2 Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Serial Data Strobe Signal and strobed Data Clock . . . . . . . . . . . . . . . . .47
Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Strobed IOM-2 Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IOM-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
MONITOR Channel Programming as a Master Device . . . . . . . . . . . .57
MONITOR Channel Programming as a Slave Device . . . . . . . . . . . . .57
MONITOR Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
CIC Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Settings after Reset (see also chapter 7.3) . . . . . . . . . . . . . . . . . . . . . . .61
D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
TIC Bus D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . .62
S-Bus Priority Mechanism for D-Channel . . . . . . . . . . . . . . . . . . . . . .64
Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . .67
S/T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Wiring Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Multi-Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Interrupt Handling for Multi-Framing . . . . . . . . . . . . . . . . . . . . . . . . . .75
Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Phase Deviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Data Sheet
2001-03-12
PSB 21381/2
PSB 21383/4
Table of Contents
2.3.6
2.3.7
2.3.7.1
2.3.7.2
2.3.8
2.3.9
2.3.10
2.3.10.1
2.3.10.2
2.3.11
2.3.12
2.3.13
2.3.13.1
Page
Data Transfer and Delay between IOM and S/T Interface . . . . . . . . . . . 76
Control of Layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Internal Layer-1 Statemachine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
External Layer-1 Statemachine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Level Detection and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Transceiver Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
External Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.3
3.3.2
3.4
3.5
3.5.1
3.5.2
3.6
3.7
HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Non-Auto Mode (MDS2-0 = ’01x’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Transparent Mode 0 (MDS2-0 = ’110’). . . . . . . . . . . . . . . . . . . . . . . . . . .98
Transparent Mode 1 (MDS2-0 = ’111’). . . . . . . . . . . . . . . . . . . . . . . . . . .98
Transparent Mode 2 (MDS2-0 = ’101’). . . . . . . . . . . . . . . . . . . . . . . . . . .98
Extended Transparent Mode (MDS2-0 = ’100’). . . . . . . . . . . . . . . . . . . .98
Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Structure and Control of the Receive FIFO . . . . . . . . . . . . . . . . . . . . . . .98
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Possible Error Conditions during Reception of Frames . . . . . . . . . . . 102
Data Reception Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Receive Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Structure and Control of the Transmit FIFO . . . . . . . . . . . . . . . . . . . . .107
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Possible Error Conditions during Transmission of Frames . . . . . . . .109
Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Access to IOM Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
HDLC Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
4
4.1
4.1.1
4.2
Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Analog Front End (AFE) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
AFE Attenuation Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Signal Processor (DSP) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Data Sheet
2001-03-12
PSB 21381/2
PSB 21383/4
Table of Contents
Page
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
4.4.1
4.4.2
4.4.3
4.4.3.1
4.4.3.2
4.4.4
4.4.4.1
4.4.4.2
4.4.4.3
4.4.5
4.4.6
4.5
4.6
4.7
4.8
4.8.1
4.8.1.1
4.8.2
4.8.2.1
4.8.3
Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Programmable Coefficients for Transmit and Receive . . . . . . . . . . . . .124
Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Four Signal Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Sequence Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Control Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Tone Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Tone Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
DTMF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Speakerphone Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Attenuation Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Speakerphone Test Function and Self Adaption . . . . . . . . . . . . . . . . . .136
Speech Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Background Noise Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Speech Comparators (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Speech Comparator at the Acoustic Side (SCAE) . . . . . . . . . . . . . . .139
Speech Comparator at the Line Side (SCLE) . . . . . . . . . . . . . . . . . .142
Automatic Gain Control of the Transmit Direction (AGCX) . . . . . . . .144
Automatic Gain Control of the Receive Direction (AGCR) . . . . . . . . . . .147
Speakerphone Coefficient Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Controlled Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Voice Data Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Programming of the Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Indirect Programming of the Codec (SOP, COP, XOP) . . . . . . . . . . . .155
Description of the Command Word (CMDW) . . . . . . . . . . . . . . . . . . .156
Direct Programming of the Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
CRAM Back-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Reference Tables for the Register and CRAM Locations . . . . . . . . . . .160
5
5.1
5.1.1
5.1.2
5.1.3
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Jitter on IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Jitter on S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Jitter on MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
6
6.1
6.2
6.3
6.4
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Software Reset Register (SRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Pin Behavior during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Data Sheet
2001-03-12
PSB 21381/2
PSB 21383/4
Table of Contents
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
7.1.16
7.1.17
7.1.18
7.1.19
7.1.20
7.1.21
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.3
7.3.1
7.3.2
7.3.3
Data Sheet
Page
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
HDLC Control and C/I Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
RFIFO - Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
XFIFO - Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
ISTAH - Interrupt Status Register HDLC . . . . . . . . . . . . . . . . . . . . . . . .182
MASKH - Mask Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
STAR - Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
CMDR - Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
MODEH - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
EXMR- Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
TIMR - Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
SAP1 - SAPI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
RBCL - Receive Frame Byte Count Low . . . . . . . . . . . . . . . . . . . . . . . .189
SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
RBCH - Receive Frame Byte Count High . . . . . . . . . . . . . . . . . . . . . . .189
TEI1 - TEI1 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
RSTA - Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
TEI2 - TEI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
TMH -Test Mode Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . . .194
CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . .195
CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . . .195
CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . .196
Transceiver, Interrupt and General Configuration Registers . . . . . . . . . . . 197
TR_CONF0 - Transceiver Configuration Register . . . . . . . . . . . . . . . . .197
TR_CONF1 - Receiver Configuration Register . . . . . . . . . . . . . . . . . . .198
TR_CONF2 - Transmitter Configuration Register . . . . . . . . . . . . . . . . .198
TR_STA - Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . . .199
TR_CMD - Transceiver Command Register . . . . . . . . . . . . . . . . . . . . .200
SQRR- S/Q-Channel Receive Register . . . . . . . . . . . . . . . . . . . . . . . . .201
SQXR- S/Q-channel Transmit Register . . . . . . . . . . . . . . . . . . . . . . . . .201
ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . . .202
MASKTR - Mask Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .203
ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
IOM-2 and MONITOR Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . . 209
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . . .210
CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . . .211
2001-03-12
PSB 21381/2
PSB 21383/4
Table of Contents
Page
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.3.14
7.3.15
7.3.16
7.3.17
7.3.18
7.3.19
7.3.20
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.4.12
7.4.13
7.4.14
CO_CR - Control Register Codec Data . . . . . . . . . . . . . . . . . . . . . . . . .212
TR_CR - Control Register Transceiver Data . . . . . . . . . . . . . . . . . . . . .212
HCI_CR - Control Register for HDLC and CI1 Data . . . . . . . . . . . . . . .213
MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . . .213
SDSx_CR - Control Register Serial Data Strobe x . . . . . . . . . . . . . . . .214
IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . . .215
MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .217
ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . . .218
MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . .218
SDS_CONF - Configuration Register for Serial Data Strobes . . . . . . . .219
MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . .219
MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . . .219
MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . . .220
MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .221
MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . . .222
Codec Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
General Configuration Register (GCR) . . . . . . . . . . . . . . . . . . . . . . . . .223
Programmable Filter Configuration Register (PFCR) . . . . . . . . . . . . . .224
Tone Generator Configuration Register (TGCR) . . . . . . . . . . . . . . . . . .225
Tone Generator Switch Register (TGSR) . . . . . . . . . . . . . . . . . . . . . . .226
AFE Configuration Register (ACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
AFE Transmit Configuration Register (ATCR) . . . . . . . . . . . . . . . . . . . .228
AFE Receive Configuration Register (ARCR) . . . . . . . . . . . . . . . . . . . .229
Data Format Register (DFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
Data Source Selection Register (DSSR) . . . . . . . . . . . . . . . . . . . . . . . .231
Extended Configuration (XCR) and Status (XSR) Register . . . . . . . . . .232
Mask Channel x Register (MASKxR) . . . . . . . . . . . . . . . . . . . . . . . . . . .234
Test Function Configuration Register (TFCR) . . . . . . . . . . . . . . . . . . . .235
CRAM Control (CCR) and Status (CSR) Register . . . . . . . . . . . . . . . . .236
CRAM (Coefficient RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.7.1
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Electrical Characteristics (general part) . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
DC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Serial Control Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . . . . .247
Data Sheet
2001-03-12
PSB 21381/2
PSB 21383/4
Table of Contents
Page
8.1.7.2
8.1.8
8.2
8.3
8.3.1
8.3.2
8.3.3
Parallel Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . .248
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Electrical Characteristics (Transceiver Part) . . . . . . . . . . . . . . . . . . . . . .251
Electrical Characteristics (Codec Part) . . . . . . . . . . . . . . . . . . . . . . . . . . .253
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
Analog Front End Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .256
Analog Front End Output Characteristics . . . . . . . . . . . . . . . . . . . . . . .256
9
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Data Sheet
2001-03-12
PSB 21381/2
PSB 21383/4
Overview
1
Overview
The SCOUT-S or SCOUT-SX respectively integrates all necessary functions for the
completion of a cost effective ISDN voice terminal solution.
Please note: Throughout the whole document “SCOUT™“ refers to “SCOUT™-S“
and “SCOUT™-SX“
The SCOUT combines the functionality of the ARCOFI®-BA PSB 2161 (Audio Ringing
Codec Filter Basic Function) or ARCOFI®-SP PSB 2163 (Audio Ringing Codec Filter with
Speakerphone) respectively and the ISAC®-S TE PSB 2186 (ISDN Subscriber Access
Controller for Terminals) on a single chip.
The SCOUT-S is suited for the use in basic ISDN voice terminals just as it is, and in
combination with an additional device on the modular IOM®-2 interface, in high end
featurephones e.g. with acoustic echo cancellation.
The SCOUT-SX PSB 21383 is an extended SCOUT-S PSB 21381 which provides the
speakerphone performance of the ARCOFI-SP PSB 2163.
The transceiver implements the subscriber access functions for an ISDN terminal to be
connected to a four wire S/T interface. It covers complete layer-1 and basic layer-2
functions for digital terminals.
The codec performs encoding, decoding, filtering functions and tone generation (ringing,
audible feedback tones and DTMF signal). An analog front end offers three analog inputs
and two analog outputs with programmable amplifiers.
The IOM-2 interface allows a modular design with functional extensions (e.g. acoustic
echo cancellation, tip/ring extension, modem extension, answering machine, video or
data terminal) by connecting other voice/data devices to the SCOUT.
In the P-MQFP-44 package (PSB21381/3) only a serial microcontroller interface (SCI) is
supported.
In the P-MQFP-64 package (PSB21382/4) a serial and parallel microcontroller interface
are supported. A clock signal and a reset input and output pin complete the
microcontroller interface.
The SCOUT is a CMOS device and operates with a 3.3 V or 5 V supply.
Data Sheet
1
2001-03-12
PSB 21381/2
PSB 21383/4
Overview
Comparison of the SCOUT with the two chip solution ISAC-S TE and
ARCOFI-BA; -SP
SCOUT
ISAC-S TE / ARCOFI
Operating modes
TE
TE
Supply voltage
3.3V ± 5 % or 5V ± 5 %
5V ± 5 %
Technology
CMOS
CMOS, BICMOS
Package
P-MQFP-44, P-MQFP-64
P-MQFP-64 / P-DSO-28
Transformer ratio for
receiver and transmitter
1:1
2:1
Test Functions
- Dig. loop via Layer-2 (TLP)
- Layer-1 disable (DIS_TR)
- Analog loop (LP_A- bit
EXLP- bit, ARL)
- Dig. loop via Layer-2
(TLP)
- Layer-1 disable (TEM)
- Analog loop (ARL)
Microcontroller Interface
Serial (SCI)
Not provided
8-bit parallel (MQFP-64):
Motorola Mux
Siemens/Intel Mux
Siemens/Intel Non-Mux
direct/ indirect Addressing
8-bit parallel:
Motorola Mux
Siemens/Intel Mux
Siemens/Intel Non-Mux
Microcontroller clock
Provided
( 7.68, 3.84, 0.96MHz,
disabled)
Not provided
Register address space
256 byte (32 byte FIFO, 96 204 byte (32 byte FIFO,
byte configuration, 128 byte 32+12 byte configuration,
128 byte CRAM)
CRAM)
Codec CRAM access
(128 byte)
Indirect and direct
addressing (general
purpose RAM)
Indirect addressing
Command structure of the
register access
Header/
address(command)/data
Address (command)/data
Controller data access to
IOM-2 timeslots
All timeslots; various
possibilities of data access
Restricted access to B- and
IC-channel
Transceiver
Data Sheet
2
2001-03-12
PSB 21381/2
PSB 21383/4
Overview
SCOUT
Data control and
manipulation
ISAC-S TE / ARCOFI
Various possibilities of data B- and IC-channel looping
control and data
manipulation (enable/
disable, shifting, looping,
switching)
IOM-2
IOM-2 Interface
Double clock (DCL),
Double clock (DCL),
bit clock (BCL),
bit clock pin (BCL),
serial data strobe 1 (SDS1) serial data strobe (SDS)
serial data strobe 2 (SDS2/
RSTO)
Monitor channel
programming
Provided
(MON0, 1 or 2)
Provided
(MON0 or 1)
C/I channels
CI0 (4bits),
CI1 (4/6bits)
CI0 (4bits),
CI1 (6bits)
Layer-1 statemachine
With changes in ISAC-S for
correspondence with the
actual ITU Specification
Statemachine in software
Possible
Not possible
IDSL (144kBit/s)
Provided (HDLC, SDS)
Not provided
HDLC support
D- and B- channels;
Non-auto mode,
transparent mode 0-2,
extended transparent mode
D-channels;
auto mode,
non-auto mode,
transparent mode 1-3
FIFO size
64 bytes per direction with
programmable FIFO
thresholds
2x32 bytes per direction
Reset Sources
RST Input
Watchdog
C/I Code Change
EAW Pin
Software Reset
RST Input
Watchdog
C/I Code Change
EAW Pin
Codec
Analog inputs
1 single ended, 2 differential 1 single ended, 2
differential
Band gap reference
Externally buffered
Data Sheet
3
Internally buffered
2001-03-12
PSB 21381/2
PSB 21383/4
Overview
SCOUT
ISAC-S TE / ARCOFI
Max. AFE gain transmit
(guaranteed transmission
characteristics)
36 dB differential inputs
24 dB single ended input
42 dB differential inputs
24 dB single ended input
Analog gain steps earpiece
3 dB
6 dB
Status indication
Register status bits
Piezo pins
AGC initialization
Initial value
Maximum gain
Voice data manipulation
Three party conferencing
(adding receive and
transmit data)
Voice monitoring on IOM-2
Three party conferencing
(adding receive data)
A-/µ-Law, 8 or 16 bit linear
A-/µ-Law, 16 bit linear
Speakerphone
Voice data formats
Voice monitoring on piezo
output
Mask register for voice data Provided
Not provided
Tone Generator Output
Loudspeaker, earpiece,
piezo pins
Loudspeaker, earpiece
Direct tone generator output Provided
Provided
to loudspeaker
Tone generator signal is
attenuated by -6dB
compared to the ARCOFI;
extended gain range (-24.5,
-27.5dB) in the loudspeaker
amplifier control setting
Saturation amplification of
tone filter, i.e. CRAM
Parameter GE
Data Sheet
As specified
Adjusted to fix value
4
2001-03-12
Siemens Codec with UPN Transceiver
SCOUT-S, SCOUT-SX
PSB 21381/2
PSB 21383/4
Version 1.3
1.1
CMOS
Features
• 8-bit parallel microcontroller interface
(only PSB 21382/4 in P-MQFP-64 package),
Motorola, Siemens/Intel bus type
multiplexed or non-multiplexed,
direct-/indirect register addressing
• Serial control interface (SCI)
• IOM-2 interface in TE mode, single/double clock,
two serial data strobe signals
• Various possibilities of microcontroller data access,
data control and data manipulation to all IOM-2
timeslots
• Power supply 3.3V or 5V
• Monitor channel handler (master/slave)
• Sophisticated power management for restricted
power mode
• Programmable microcontroller clock output and
reset (input/output) pins
• Advanced CMOS technology
P-MQFP-44-1
P-MQFP-64-1
Transceiver part
•
•
•
•
•
•
Full duplex 2B+D S/T interface transceiver according to ITU-T I.430
Conversion of the frame structure between the S/T interface and IOM-2
Receive timing recovery
Continuously adapted receive thresholds
D-channel access control
Access to S and Q bits of S/T interface
Type
Package
PSB 21381
SCOUT-S
P-MQFP-44-1
PSB 21383
SCOUT-SX
P-MQFP-44-1
PSB 21382
SCOUT-S
P-MQFP-64-1
PSB 21384
SCOUT-SX
P-MQFP-64-1
Data Sheet
5
2001-03-12
PSB 21381/2
PSB 21383/4
Overview
• Activation and deactivation procedures with automatic activation from power down
state
• HDLC controller. Operating in non-auto mode, transparent mode 0-2 or extended
transparent mode. Access to B1, B2 or D channels or the combination of them e.g.
for 144 kbit/s data transmission (2B+D)
• FIFO buffer with 64 bytes per direction and programmable FIFO thresholds for
efficient transfer of data packets
• Implementation of IOM-2 MONITOR and C/I-channel protocol to control peripheral
devices
• Realization of layer-1 statemachine in software possible
• Watchdog timer
• Programmable reset sources
• Test loops and functions
Codec part
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Applications in digital terminal equipment featuring voice functions
Digital signal processing performs all CODEC functions
Fully compatible with the ITU-T G.712 and ETSI (NET33) specification
PCM A-Law/µ-Law (ITU-T G.711) and 8/16-bit linear data; maskable codec data
Flexible configuration of all internal functions
Three analog inputs for the handset microphone, the speakerphone and the headset
Two differential outputs for a handset earpiece (200 Ω) and a loudspeaker (50 Ω for
5V power supply, 25 Ω for 3.3V power supply)
Flexible test and maintenance loopbacks in the analog front end and the digital signal
processor
Independent gain programmable amplifiers for all analog inputs and outputs
Full digital speakerphone (SCOUT-SX only) and loudhearing support without any
external components (speakerphone test and optimization function is available)
Enhanced voice data manipulation for features like:
- Three-party conferencing
- Voice monitoring
Two transducer correction filters
Side tone gain adjustment
Flexible DTMF, tone and ringing generator
Direct and indirect CRAM access
Data Sheet
6
2001-03-12
PSB 21381/2
PSB 21383/4
Overview
Pin Configuration
SR2
SR1
VDDL
VSSL
SX2
SX1
VDDPLL
VSSPLL
FSC
DCL
BCL
1.2
33 32 31 30 29 28 27 26 25 24
34
35
36
37
SCOUT-S(X)
38
PSB 21381
39
(PSB 21383)
40
P-MQFP-44
41
42
43
44
1 2 3 4 5 6 7 8 9 10
23
22
21
20
19
18
17
16
15
14
13
12
11
DU
DD
SDX
SDR
SCLK
VSSD
VDDD
EAW
XTAL1
XTAL2
MCLK
SR2
SR1
VDDL
VDDP
VSSL
LSP
SX2
VSSP
SX1
LSN
VDDPLL
HOP
VSSPLL
HON
A4
CS
A3
INT
A2
RST
A1
RSTO/SDS2
A0
SDS1
FSC
DCL
BCL
VDDSEL
reserved
VDDA
VSSA
VREF
BGREF
AXI
MIN2
MIP2
MIN1
MIP1
48 47 46 45 44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1 2 3 4 5
43 42 41 40 39 38 37 36 35 34 33
SCOUT-S(X)
PSB 21382
(PSB 21384)
P-MQFP-64
6 7 8 9 10
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
11 12 13 14 15 16
VDDP
LSP
VSSP
LSN
HOP
HON
VSSD2
VDDD2
ALE
WR / RW
RD / DS
CS
INT
RST
RSTO/SDS2
SDS1
VDDSEL
reserved
reserved
A7
A6
A5
VDDA
VSSA2
VSSA1
VREF
BGREF
AXI
MIN2
MIP2
MIN1
MIP1
DU
DD
AD7 / SDX
AD6 / SDR
AD5 / SCLK
AD4
VSSD1
VDDD1
AD3
AD2
AD1
AD0
EAW
XTAL1
XTAL2
MCLK
mqfp44_64_pin_s.vsd
Figure 1
Pin Configuration
Data Sheet
7
2001-03-12
PSB 21381/2
PSB 21383/4
Overview
1.3
Logic Symbol
IOM-2 Interface
P-MQFP- 44
5
VREF
BGREF
VDD
5
VSS VDDSEL DD
DU FSC DCL BCL SDS1 RSTO/
SDS2
RST
Analog Front End
AXI
MIP1
MIN1
SR1
SR2
SX1
MIP2
MIN2
S Interface
SX2
XTAL2
HOP
HON
XTAL1
LSP
LSN
7.68 MHz
EAW
SCLK SDR SDX CS INT
MCLK
Serial Control Interface (SCI)
VDD:
VSS:
5 seperate power pins
5 seperate ground pins
IOM-2 Interface
P-MQFP- 64
6
Analog Front End
VREF
BGREF
(VDDL,VDDD,VDDA,VDDP,VDDPLL)
(VSSL,VSSD,VSSA,VSSP,VSSPLL)
VDD
7
VSS VDDSEL DD
DU FSC DCL BCL SDS1 RSTO/
SDS2
RST
AXI
MIP1
MIN1
SR1
SR2
SX1
MIP2
MIN2
S Interface
SX2
XTAL2
HOP
HON
XTAL1
LSP
LSN RD/ WR/
SCLK/ SDR/ SDX/
DS R/W ALE A0...7 AD0...4 AD5 AD6 AD7 CS INT
7.68 MHz
EAW
MCLK
Serial Control Interface (SCI)
Parallel µC Interface
VDD:
VSS:
6 seperate power pins
7 seperate ground pins
(VDDL,VDDD1,VDDD2,VDDA,VDDP,VDDPLL)
(VSSL,VSSD1,VSSD2,VSSA1,VSSA2,VSSP,VSSPLL)
logsym_s.vsd
Figure 2
Logic Symbol of the SCOUT in P-MQFP-44 and P-MQFP-64
Data Sheet
8
2001-03-12
PSB 21381/2
PSB 21383/4
Overview
1.4
Pin Definitions and Function
Table 1
Pin No.
Pin No.
Symbol
MQFP-44 MQFP-64
Input (I)
Function
Output (O)
Open Drain
(OD)
Power supply (3.3 V or 5 V ± 5 %)
31
46
16
VDDL
–
Supply voltage for line driver
–
Supply voltage for digital parts
–
Supply voltage for analog parts
–
Supply voltage for loudspeaker
–
Supply voltage for internal PLL
–
Ground for line driver
–
Ground for digital parts
–
Ground for analog parts
–
Ground for loudspeaker
3
3
26
41
VDDD
VDDD1
VDDD2
VDDA
VDDP
VDDPLL
VSSL
VSSD
VSSD1
VSSD2
VSSA
VSSA2
VSSA1
VSSP
VSSPLL
–
Ground for internal PLL
34
49
VDDSEL I
VDD Selection
’0’: 3.3 V supply voltage
’1’: 5 V supply voltage
25
8
36
55
1
1
27
42
30
45
17
26
7
37
57
56
IOM-2 Interface
21
31
DD
I/OD/O
Data Downstream
22
32
DU
I/OD/O
Data Upstream
25
35
FSC
I/O
Frame Synchronization Clock (8 kHz)
24
34
DCL
I/O
Data Clock
I: single or double clock
(programmable)
O: double clock, 1.536 MHz
23
33
BCL
O
Bit Clock (768kHz)
Data Sheet
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Table 1 (cont’d)
Pin No.
Pin No.
Symbol
MQFP-44 MQFP-64
Function
Input (I)
Output (O)
Open Drain
(OD)
11
16
SDS1
O
Programmable strobe signal or bit
clock
10
15
RSTO/
SDS2
OD
O
Reset Output (active low)
Programmable strobe signal or bit
clock
RESET
9
14
RST
I
Reset (active low)
Transceiver
32
33
47
48
SR1
SR2
I
I
S-Bus receiver input
S-Bus receiver input
28
29
43
44
SX1
SX2
O
O
S-Bus transmitter output (positive)
S-Bus transmitter output (negative)
13
14
18
19
XTAL2
XTAL1
OI
I
Oscillator output
Oscillator or 7.68 MHz input
15
20
EAW
I
External Awake.
A low level on this input starts the
oscillator from the power down state
and generates a reset pulse if
enabled (see chapter 7.2.12)
In addition an interrupt request is
generated at pin INT.
Microcontroller Interface
8
13
INT
OD
Interrupt request (active low)
12
17
MCLK
O
Microcontroller Clock
7
12
CS
I
Chip Select (active low)
During reset also used as interface
selection pin (see chapter 2.1)
-
9
ALE
I
Multiplexed bus mode: Address Latch
Enable
Non-multiplexed bus and serial mode:
Interface selection pin (see chapter
2.1)
Data Sheet
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Table 1 (cont’d)
Pin No.
Pin No.
Symbol
MQFP-44 MQFP-64
-
10
Input (I)
Function
Output (O)
Open Drain
(OD)
WR
I
R/W
I
RD
I
DS
I
28
SCLK
SCLK
AD5
I
I
I/O
Clock for the serial control interface
Serial control interface: Clock
Multiplexed bus mode: Address/data
line bit 5
Non-multiplexed bus mode: Data line
bit 5
29
SDR
SDR
AD6
I
I
I/O
Serial Data Receive
Serial control interface: Data receive
Multiplexed bus mode: Address/data
line bit 6
Non-multiplexed bus mode: Data line
bit 6
11
18
19
Write access in Intel bus mode (active
low)
Read/write access in Motorola bus
mode
During reset also used as interface
selection pin (see chapter 2.1)
Read access in Intel bus mode (active
low)
Data strobe in Motorola bus mode
(active low)
During reset also used as interface
selection pin (see chapter 2.1)
20
30
SDX
SDX
AD7
OD/O
OD/O
Serial Data Transmit
Serial control interface: Data transmit
Multiplexed bus mode: Address/data
line bit 7
Non-multiplexed bus mode: Data line
bit 7
-
21
22
23
24
27
AD0
AD1
AD2
AD3
AD4
I/O
I/O
I/O
I/O
I/O
Multiplexed bus mode: Address/data
lines
Non-multiplexed bus mode: Data lines
Data Sheet
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Overview
Table 1 (cont’d)
Pin No.
Pin No.
Symbol
MQFP-44 MQFP-64
-
Data Sheet
36
37
38
39
40
54
53
52
A0
A1
A2
A3
A4
A5
A6
A7
Input (I)
Function
Output (O)
Open Drain
(OD)
I
I
I
I
I
I
I
I
Multiplexed bus mode: Not used, has
to be connected to VDD
Non-multiplexed bus mode: Address
bus. For indirect address mode only
A0 is valid
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Table 1 (cont’d)
Pin No.
Pin No.
Symbol
MQFP-44 MQFP-64
Function
Input (I)
Output (O)
Open Drain
(OD)
Analog Frontend
38
58
VREF
O
2.4V Reference voltage for biasing
external circuitry
An external capacity of ≥ 100nF has to
be connected
39
59
BGREF
I/O
Reference Bandgap voltage for
internal references
An external capacity of ≥ 22nF has to
be connected
40
60
AXI
I
Single-ended Auxiliary Input
44
43
64
63
MIP1
MIN1
I
I
Symmetrical differential Microphone
Input 1
42
41
62
61
MIP2
MIN2
I
I
Symmetrical differential Microphone
Input 2
5
6
5
6
HOP
HON
O
O
Differential Handset earpiece output
for 200 Ω transducers
2
4
2
4
LSP
LSN
O
O
Differential Loudspeaker output for
50 Ω or 25 Ω loudspeaker using a
power supply of 5 V or 3.3 V
respectively
Reserved Pins
35
Data Sheet
50
reserved I
This input is not used for normal
operation and must be connected to
VDD.
51
reserved I
This input is not used for normal
operation and must be connected to
VSS.
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Overview
1.5
Typical Applications
The SCOUT can be used in a variety of applications like
•
•
•
•
•
•
•
•
•
•
•
ISDN voice terminal (Figure 3)
ISDN voice terminal with speakerphone (Figure 4)
ISDN voice terminal as featurephone with acoustic echo cancellation (Figure 5)
ISDN voice terminal with tip/ring extension (Figure 6)
ISDN voice terminal with answering machine (Figure 7)
ISDN voice terminal with full duplex speakerphone and answering machine (Figure 8)
ISDN videophone with speakerphone (Figure 9)
ISDN videophone with full duplex speakerphone (Figure 10)
ISDN voice/data terminal on a PC card (Figure 11)
ISDN voice/data terminal with tip/ring extension (Figure 12)
Terminal Adapter with dual tip/ring (Figure 13)
SCOUT-S
S-Interface
SCI
µC
pbx_voice_s.vsd
Figure 3
ISDN Voice Terminal
Data Sheet
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Overview
SCOUT-SX
S-Interface
SCI
µC
voice_te_s.vsd
Figure 4
ISDN Voice Terminal with Speakerphone
SCOUT-S
S-Interface
IOM-2
SCI
µC
ACE
vt_ace_s.vsd
Figure 5
ISDN Voice Terminal as Featurephone with Acoustic Echo Cancellation
Data Sheet
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Overview
SCOUT-SX
S-Interface
IOM-2
SLIC
SCI
ARCOFI-BA
µC
Fax
vt_tipring_s.vsd
Figure 6
ISDN Voice Terminal with Tip/Ring Extension
SCOUT-SX
SCI
S-Interface
IOM-2
Memory
SAM
Microcontroller
vt_sam_s.vsd
Figure 7
ISDN Voice Terminal with Answering Machine
Data Sheet
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Overview
SCOUT-S
SCI
S-Interface
IOM-2
Memory
SAM_EC
Microcontroller
vt_samec_s.vsd
Figure 8
ISDN Voice Terminal with Full Duplex Speakerphone and Answering Machine
SCOUT-SX
S-Interface
IOM-2
Video
Codec
JADE
Video
Microcontroller
vt_video_s.vsd
Figure 9
ISDN Videophone with Speakerphone
Data Sheet
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Overview
SCOUT-S
S-Interface
IOM-2
Video
Codec
JADE
ACE
SCI
Video
Microcontroller
vt_video_fullduplex_s.vsd
Figure 10
ISDN Videophone with Full Duplex Speakerphone
SCOUT-SX
IOM-2
ISAR
Bus Interface
vt_data_pc_s.vsd
Figure 11
ISDN Voice/Data Terminal on a PC Card
Data Sheet
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Overview
SCOUT-SX
S-Interface
IOM-2
SLIC
ARCOFI-BA
ISAR
Microcontroller
vt_data_tipring_s.vsd
V.24 Interface
Figure 12
ISDN Voice/Data Terminal with Tip/Ring Extension
SLIC
SCOUT-S
S-Interface
IOM-2
SLIC
ARCOFI-BA
SCI
µC
Fax
vt_dualtipring_s.vsd
Figure 13
Terminal Adapter with Dual Tip/Ring
Data Sheet
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Overview
1.6
General Functions and Device Architecture
Figure 14 shows the architecture of the SCOUT containing the following functional
blocks:
•
•
•
•
•
•
•
•
•
S/T interface transceiver with ISAC-S TE PSB 2186 functionality respectively
Serial and parallel microcontroller interface
HDLC controller with 64 byte FlFOs per direction and programmable FIFO threshold
IOM-2 handler and interface for terminal application, MONITOR handler
Clock and timing generation
Digital PLL to synchronize IOM-2 to S/T
Reset generation (watchdog timer)
Analog Front End (AFE) of the codec part
Digital Signal Processer (DSP) for codec/filter functions, tone generation, voice data
manipulation and speakerphone function (SCOUT-SX)
These functional blocks are described in the following chapters.
Data Sheet
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Overview
VR E F
AXI
BGR E F
MIP1
MIN1
MIP2
MIN2
VR E F
AINMUX
AMI
A/D
D/A
Dec
Int
Dec
Int
LP-F ilter
F requency
Correction
F ilter
Digital Gain
Adjus tment
S peakerphone
F unction
Codec
Data
HDLCData
IOM-2 Interface
IOM-2 Handler
L APD
HDLC HDLC
T rans - R ecei- Controller
S tatus
ver
mitter
Command
R egis ter
F IF O
X-F IF O R -F IF O Controller
Monitor
D ata
MCLK
R es et
Handler
MONIT OR
T I C B us
D ata
Interrupt
C/I
S 0-Data
C/I-Data
T rans c.
Control /
Config.
Generation
S -T rans ceiver
DPLL
0
T one Generator
FSC
Microcontroller Interface
MUX
Contr oller D ata Acces s
S CI
OS C
VD D x
VS S x
C/I D ata
C/I D ata
D CL
CS
S X1
S X2
S R1
S R2
XT AL1
XT AL2
2001-03-12
21
Data Sheet
8-bit parallel
E AW
VD D S E L
B CL
S DS 1
S DS 2
S DX
S DR
S CL K
Monitor D ata
DD
H DL C
Control
AL E
S idetone
Codec Control / Config.
DS P
R D /D S
T IC
DU
W R / R /W
ALS
AHO
AF E
A0 -A7
T I C B us D ata
RSTO
RST
MCL K
INT
H DL C
D ata
AD 0-7 /D 0 -7
LS P
LS N
HOP
HON
AR CHIT .VS D
D ata S ource S election, Voice D ata Manipulation
(Coding, Mas k ing, Confer encing)
Figure 14
Architecture of the SCOUT
PSB 21381/2
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Interfaces
2
Interfaces
The SCOUT provides the following interfaces:
• Serial and 8-bit microcontroller interface together with a reset and microcontroller
clock generation.
• IOM-2 interface as an universal backplane for terminals
• S/T interface towards the four wire subscriber line
• Analog Front End (AFE) as interface between the analog transducers and the digital
signal processor of the codec part
The microcontroller and IOM-2 interface are described in chapter 2.1 or 2.2
respectively. The S/T interface is described in the chapter 2.3, the analog front end
(AFE) in chapter 4.1
Data Sheet
22
02.01
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Interfaces
2.1
Microcontroller Interface
Depending of the package the SCOUT supports a serial or a parallel microcontroller
interface. In the P-MQFP-44 package only a serial interface is supported whereas in the
P-MQFP-64 package either a serial or a parallel microcontroller interface can be
selected.
For applications where no controller is connected to the SCOUT microcontroller interface
programming is done via the IOM-2 MONITOR channel from a master device. In such
applications the SCOUT operates in the IOM-2 slave mode (refer to the corresponding
chapter of the IOM-2 MONITOR handler).
The interface selections are all done by pinstrapping. The possible interface selections
are listed in table 2 for the P-MQFP-44 package and in table 3 for the P-MQFP-64
package. The selection pins are evaluated when the reset input RST is released. For the
pin levels stated in the tables the following is defined:
’High’:
dynamic pin value which must be ’High’ when the pin level is evaluated
VDD, VSS: static ’High’ or ’Low’ level
Table 2
Interface Selection for the P-MQFP-44 Package
PIN
CS
Interface
Type/Mode
‘High’
Serial Control Interface
(SCI)
VSS
IOM-2 MONITOR Channel
(Slave Mode)
Table 3
Interface Selection for the P-MQFP-64 Package
PINS
WR
(R/W)
RD
(DS)
’High’ ’High’
VSS
VSS
Serial /Parallel
Interface
Parallel
Serial
PINS
ALE
Interface
Type/Mode
VDD
Motorola
VSS
Siemens/Intel Non-Mux
edge
Siemens/Intel Mux
’High’
VSS
Serial Control Interface(SCI)
VSS
VSS
IOM-2 MONITOR Channel
(Slave Mode)
CS
‘High’
Note: For a selected interface mode that does not need all input selection and address
pins the unused pins must be tied to VDD or VSS.
Data Sheet
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Interfaces
The mapping of all accessible registers can be found in figure 92 in chapter 7.
The microcontroller interface also consists of a microcontroller clock generation at pin
MCLK and an interrupt request at pin INT.
2.1.1
Serial Control Interface (SCI)
The serial control interface (SCI) is compatible to the SPI interface of Motorola or
Siemens C510 family of microcontrollers.
The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data are transferred via the lines
SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning
of a serial access to the registers. Incoming data is latched at the rising edge of SCLK
and shifts out at the falling edge of SCLK. Each access must be terminated by a rising
edge of CS. Data is transferred in groups of 8 bits with the MSB first.
Figure 15 shows the timing of a one byte read/write access via the serial control
interface.
Data Sheet
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Interfaces
Figure 15
Serial Control Interface Timing
Data Sheet
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Interfaces
2.1.1.1
Programming Sequences
The principle structure of a read/write access to the SCOUT registers via the serial
control interface is shown in figure 16.
write sequence:
write
byte 2
header
SDR
7
0
0 7
read sequence:
byte 3
address (command)
6
write data
0
7
0
7
0
read
byte 2
header
SDR
7
1
0 7
address (command)
6
SDX
byte 3
0
read data
Figure 16
Serial Command Structure
A new programming sequence starts with the transfer of a header byte. The header byte
specifies different programming sequences allowing a flexible and optimized access to
the individual functional blocks of the SCOUT.
The possible sequences are listed in table 4 and are described afterwards.
Table 4
Header Byte Code
Header
Byte
Sequence Type
Access to
00H
Cmd-Data-Data-Data ARCOFI compatible,
non-interleaved
Codec reg./CRAM
(indirect)
08H
ARCOFI compatible,
interleaved
40H
non-interleaved
44H
48H
Sequence
Adr-Data-Adr-Data
CRAM (80H-FFH)
interleaved
4CH
Data Sheet
Address Range 00H-6FH
Address Range 00H-6FH
CRAM (80H-FFH)
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Table 4 (cont’d)
Header Byte Code
4AH
Read-/Write-only
4EH
(address autoincrement) CRAM (80H-FFH)
Adr-Data-Data-Data
43H
Address Range 00H-6FH
Read-/Write-only
41H
non-interleaved
49H
interleaved
Address Range 00H-6FH
Header 00H: ARCOFI Compatible Sequence
This programming sequence is compatible to the SOP, COP and XOP command
sequences of the ARCOFI. It gives indirect access to the codec registers 60H-6FH and
the CRAM (80H-FFH). The codec command word (cmdw) is followed by a defined
number of data bytes (data n; n = 0, 1, 4 or 8). The number of data bytes depends on the
codec command word. The commands can be applied in any order and number. The
coding of the different SOP, COP and XOP commands is listed in the description of the
command word (CMDW) in chapter 4.8.
Structure of the ARCOFI compatible sequence:
defined length
defined length
00H
cmdw
data n
data 1
cmd
data n
data 1
Header 40H, 44H: Non-interleaved A-D-A-D Sequences
The non-interleaved A-D-A-D sequences give direct read/write access to the address
range 00H-6FH (header 40H) or the CRAM range 80H-FFH (header 44H) respectively and
can have any length. In this mode SDX and SDR can be connected together allowing
data transmission on one line.
Example for a read/write access with header 40H or 44H:
SDR
header
SDX
Data Sheet
wradr
wrdata
rdadr
rdadr
rddata
27
wradr
wrdata
rdata
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Header 48H, 4CH: Interleaved A-D-A-D Sequences
The interleaved A-D-A-D sequences give direct read/write access to the address range
00H-6FH (header 48H) or the CRAM range 80H-FFH (header 4CH) respectively and can
have any length. This mode allows a time optimized access to the registers by
interleaving the data on SDX and SDR.
Example for a read/write access with header 48H or 4CH:
SDR
header
wradr
wrdata
rdadr
SDX
rdadr
wradr
rddata
rddata
wrdata
Header 4AH, 4EH: Read-/Write-only A-D-D-D Sequences (Address Autoincrement)
The A-D-D-D sequences give a fast read-/write-only access to the address range 00H6FH (header 4AH) or the CRAM range 80H-FFH (header 4EH) respectively.
The starting address (wradr, rdadr) is incremented automatically after every data byte.
The sequence can have any length and is terminated by the rising edge of CS.
Example for a write access with header 4AH or 4EH:
SDR
header
wradr
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
(wradr)
(wradr+1)
(wradr+2)
(wradr+3)
(wradr+4)
(wradr+5)
(wradr+6)
SDX
Example for a read access with header 4AH or 4EH:
SDR
header
SDX
Data Sheet
rdadr
rddata
rddata
rddata
rddata
rddata
rddata
rddata
(rdadr)
(rdadr+1)
(rdadr+2)
(rdadr+3)
(rdadr+4)
(rdadr+5)
(rdadr+6)
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Header 43H: Read-/Write- only A-D-D-D Sequence
This mode (header 43H) can be used for a fast access to the HDLC FIFO data. Any
address (rdadr, wradr) in the range between 00h and 1F gives access to the current
FIFO location selected by an internal pointer which is automatically incremented with
every data byte following the first address byte. The sequence can have any length and
is terminated by the rising edge of CS.
Example for a write access with header 43H:
SDR
header
wradr
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
SDX
Example for a read access with header 43H:
SDR
header
rdadr
SDX
rddata
rddata
rddata
rddata
rddata
rddata
rddata
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
Header 41H: Non-interleaved A-D-D-D Sequence
This sequence (header 41H) allows in front of the A-D-D-D write access a noninterleaved A-D-A-D read access. This mode is useful for reading status information
before writing to the HDLC XFIFO. The termination condition of the read access is the
reception of the wradr. The sequence can have any length and is terminated by the rising
edge of CS.
Example for a read/write access with header 41H:
SDR
header
rdadr
SDX
rdadr
rddata
wradr
wrdata
wrdata
wrdata
(wradr)
(wradr)
(wradr)
rddata
Header 49H: Interleaved A-D-D-D Sequence
This sequence (header 49H) allows in front of the A-D-D-D write access an interleaved
A-D-A-D read access. This mode is useful for reading status information before writing
to the HDLC XFIFO. The termination condition of the read access is the reception of the
wradr. The sequence can have any length and is terminated by the rising edge of the CS
line.
Example for a read/write access with header 49H:
SDR
header
SDX
Data Sheet
rdadr
rdadr
rddata
wradr
wrdata
wrdata
wrdata
(wradr)
(wradr)
(wradr)
rddata
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Interfaces
2.1.2
Parallel Microcontroller Interface
The 8-bit parallel microcontroller interface with address decoding on chip allows an easy
and fast microcontroller access.
The parallel interface provides three types of µP buses which are selected via pin ALE.
The bus operation modes with corresponding pins are listed in table 5.
Table 5
Bus Operation Modes
Bus Mode
Pin ALE
Control Pins
(1) Motorola
VDD
CS, R/W, DS
(2) Siemens/Intel non-multiplexed
VSS
CS, WR, RD
(3) Siemens/Intel multiplexed
Edge
CS, WR, RD, ALE
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects the interface type (3). A return to one of the other interface
types is possible only if a hardware reset is issued.
Note: If the multiplexed address/data bus type (3) is selected, the unused address pins
A0-A7 must be tied to VDD.
A read/write access to the registers can be done in multiplexed or non-multiplexed
mode.
In non-multiplexed mode the register address must be applied to the address bus (A0A7) for the data access via the data bus (D0-D7).
In multiplexed mode the address on the address bus (AD0-AD7) is latched in by ALE
before a read/write access via the address/data bus is performed.
Depending on the AMOD bit in the MODE2 register (see chapter 7.2.13) the direct or
indirect address mode can be selected.
The address mode after reset is the indirect address mode (AMOD = ’0’).
Reprogramming into the direct address mode (AMOD = ’1’) has to take place in the
indirect address mode. Figure 17 illustrates both register addressing modes.
Direct address mode (AMOD = ’1’): The register address to be read or written is directly
set in the way described above.
Indirect address mode (AMOD = ’0’): Only the LSB of the address line (A0) is used to
select either the address register (A0 = ’0’) or the data register (A0 = ’1’). The
microcontroller writes the register address to the ADDRESS register before it reads/
writes data from/to the corresponding DATA register.
In indirect address mode only the address line A0 is evaluated. The remaining address
lines have to be tied to logical ’1’.
Note: The CRAM back-up procedure (see chapter 4.8.2.1) only applies to the direct
address mode
Data Sheet
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Interfaces
Figure 17
Direct/Indirect Register Address Mode
Data Sheet
31
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Interfaces
2.1.3
Interrupt Structure and Logic
Special events in the SCOUT are indicated by means of a single interrupt output, which
requests the host to read status information from the SCOUT or transfer data from/to the
SCOUT.
Since only one INT request output is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the SCOUT.
The structure of the interrupt status registers is shown in figure .
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
MASK
ISTA
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
INT
STI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
ASTI
ACK21
ACK20
ACK11
ACK10
CIC0
CIC1
CIR0
CI1E
CIX1
MASKTR
LD
RIC
RME
RPF
RFO
XPR
RME
RPF
RFO
XPR
XMR
XDU
XMR
XDU
MASKH
ISTAH
ISTATR
LD EAW
RIC
MRE
MDR
MER
MIE
MDA
MAB
MOSR
MOCR
Figure18
SCOUT Interrupt Status Registers
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Five interrupt bits in the ISTA register point at interrupt sources in the HDLC Controller
(HDLC), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN) and the
synchronous transfer (ST). The timer interrupt (TIN) and the watchdog timer overflow
(WOV) can be read directly from the ISTA register. All these interrupt sources are
described in the corresponding chapters. After the SCOUT has requested an interrupt
by setting its INT pin to low, the host must read first the SCOUT interrupt status register
(ISTA) in the associated interrupt service routine. The INT pin of the SCOUT remains
active until all interrupt sources are cleared by reading the corresponding interrupt
register. Therefore it is possible that the INT pin is still active when the interrupt service
routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FFH into the MASK register)
and write back the old mask to the MASK register.
A low level at pin EAW generates an interrupt indication which is set at the LD bit of the
ISTATR register. If this LD bit has been set due to an level detect interrupt, the LD bit in
the transceiver status register TR_STA is set additionally.
Therefore pin EAW has to be connected to ’1’, if no interrupt should be generated.
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2.1.4
Microcontroller Clock Generation
The microcontroller clock is provided by the pin MCLK. Three clock rates are selectable
by a programmable prescaler (see chapter clock generation figure 89) which is
controlled by the MODE1.MCLK bit corresponding to the following table.
The possible MCLK frequencies are listed in table 6.
Table 6
MCLK Frequencies
MCLK
Bits
MCLK Frequency
’00’
3.84 MHz (default)
’01’
0.96 MHz
’10’
7.68 MHz
’11’
disabled
The clock rate is changed after CS becomes inactive.
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2.2
IOM-2 Interface
The SCOUT supports the IOM-2 interface in terminal mode with single clock and double
clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge
of FSC indicates the start of an IOM-2 frame. The FSC signal is generated by the receive
DPLL which synchronizes to the received line frame. The DCL and the BCL output clock
signals synchronize the data transfer on both data lines. The DCL is twice the bit rate,
the BCL output rate is equal to the bit rate. The bits are shifted out with the rising edge
of the first DCL clock cycle and sampled at the falling edge of the second clock cycle.
The BCL clock together with the two serial data strobe signals (SDS1, SDS2) can be
used to connect time slot oriented standard devices to the IOM-2 interface.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register. The BCL clock output can be enabled separately with the EN_BCL bit.
The clock rate or frequency respectively of the IOM-signals in TE mode are:
DD, DU: 768 kbit/s
DCL: 1536 kHz (double clock rate); 768 kHz (single clock rate if DIS_TR = ’1’)
FSC: 8 kHz.
If the transceiver is disabled (TR_CONF.DIS_TR) the DCL and FSC pins become input
and the HDLC and codec parts can still work via IOM-2. In this case it can be selected
with the clock mode bit (IOM_CR.CLKM) between a double clock and a single clock
input.
Note: One IOM-2 frame has to consist of a multiple of 64 (32) DCL clocks for a double
(single) clock selection.
FSC
DCL
BCL
Figure 19
Clock waveforms
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2.2.1
IOM-2 Frame Structure
The frame structure on the IOM-2 data ports (DU,DD) in IOM-2 terminal mode is shown
in figure 20
.
Figure 20
IOM-2 Frame Structure in Terminal Mode
The frame is composed of three channels
• Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (MON0) and a command/indication channel (CI0) for control
and programming of the layer-1 transceiver.
• Channel 1 contains two 64-kbit/s intercommunication channels (IC) plus a MONITOR
and command/indicate channel (MON1, CI1) to program or transfer data to other IOM2 devices.
• Channel 2 is used for the TlC-bus access. Additionally channel 2 supports further IC
and MON channels.
Note: Each octet related to any integrated functional block can be programmed to any
timeslot (see chapter 7.3.2) except the C/I0- and D- channels that are always
related to timeslot 0.
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2.2.2
IOM-2 Handler
The IOM-2 handler offers a great flexibility for handling the data transfer between the
different functional units of the SCOUT and voice/data devices connected to the IOM-2
interface. Additionally it provides a microcontroller access to all time slots of the IOM-2
interface via the four controller data access registers (CDA). Figure 21 shows the
architecture of the IOM-2 handler. For illustrating the functional description it contains all
configuration and control registers of the IOM-2 handler. A detailed register description
can be found in chapter 7.3
The PCM data of the functional units
• Codec (CO)
• Transceiver (TR) and the
• Controller data access (CDA)
can be configured by programming the time slot and data port selection registers
(TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can
be assigned to each of the 12 PCM time slots of the IOM-2 frame. With the DPS bit (Data
Port Selection) the output of each functional unit is assigned to DU or DD respectively.
The input is assigned vice versa. With the control registers (CR) the access to the data
of the functional units can be controlled by setting the corresponding control bits ( EN,
SWAP).
To avoid data collisions it has to be noticed that the C/I and D channels of the enabled
transceiver are always related to time slot 3. If the monitor handler is enabled its data is
related to time slot TS (2, 6 or 10) and the appropriate MR and MX bits to time slot TS+1
depending on the MCS bits of register MON_CR.
The IOM-2 handler provides also access to the
• MONITOR channel (MON)
• C/I channels (CI0,CI1)
• TIC bus (TIC) and
• D- and B-channel for HDLC control
The access to these channels is controlled by the registers HCI_CR and MON_CR.
The IOM-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the
control registers IOM_CR, SDS1_CR and SDS2_CR.
The reset configuration of the SCOUT IOM-2 handler corresponds to the defined frame
structure and data ports in IOM-2 terminal mode (see figure 20).
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Interfaces
.
Codec D ata (CO)
CO10X
CO11X
CO20X
CO21X
CO10R
CO11R
CO20R
CO21R
IOMHAND.VSD
DU
DD
CDA
R egis ter
Controller Data
Acces s (CDA)
IOM-2 Handler
Control
Codec Data
(T S S , DPS ,
E N)
CDA11
CDA10
CI0
S DS 1 S DS 2
(E N, T L E N, T S S )
DU DD F S C DCL B CL
IOM_CR
T IC
D /B 1/B 2 D ata
CI1
HDL C F IF O
HCI_CR
Control
Control
HDLC
C/I1
D-, BData
Data
(DPS ,E N)
(E N)
CI 1 D ata
IOM-2 Interface
(E N, OD)
MON_CR
MON
Handler
CI 0 D ata
Data
Control
Monitor T IC Bus
Data
Dis able
(DPS ,E N (T IC_DIS )
MCS )
T IC B us D ata
Microcontroller Interface
S DS 1/2_CR
IOM_CR
Control
Data Acces s
(T S DP, DPS ,
E N, S WAP,
T BM, MCDA,
S T I)
MCDA
CDA_T S DPxy
CDA_CR x
CO_CR
CO_T S DPxy
CDA20
CDA21
CD A D ata
STI
MS T I
AS T I
x,y = 1 or 2
Monitor D ata
DU
DD
C/I O - D ata
T R _T S DP_B 1
Control
T rans ceiver
Data
Acces s
(T S S , DPS ,
E N)
B 1 /B 2 /D - D ata
T R _CR
T R _T S DP_B 2
T R _B1_X
T R _B2_X
T R _D_X
T R _D_R
T R _B 1_R
T R _B 2_R
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Data Sheet
Codec D ata
T rans ceiver
D ata (T R )
Figure 21
Architecture of the IOM Handler
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2.2.2.1
Controller Data Access (CDA)
The IOM-2 handler provides with its four controller data access registers (CDA10,
CDA11, CDA20, CDA21) a very flexible solution for the access to the 12 IOM-2 time slots
by the microcontroller.
The functional unit CDA (controller data access) allows with its control and configuration
registers
• looping of up to four independent PCM channels from DU to DD or vice versa with the
four CDA registers
• shifting or switching of two independent PCM channels to another two independent
PCM channels on both data ports (DU, DD)
• monitoring of up to four time slots on the IOM-2 interface simultaneously
• microcontroller read and write access to each PCM channel
The access principle which is identical for the two channel register pairs CDA10/11 and
CDA20/21 is illustrated in figure 22. The index variables x,y used in the following
description can be 1 or 2 for x, and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a CDA_TSDPxy register is assigned by which
the time slot and the data port can be determined. With the TSS (Time Slot Selection)
bits a time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the
output of the CDAxy register can be assigned to DU or DD respectively. The time slot
and data port for the output of CDAxy is always defined by its own CDA_TSDPxy
register. The input of CDAxy depends on the SWAP bit in the control registers CRx.
If the SWAP bit = ’0’ the time slot and data port for the input and output of the CDAxy
register is defined by its own CDA_TSDPxy register. The data port for the CDAxy input
is vice versa to the output setting for CDAxy.
If the SWAP bit = ’1’, the input port and time slot of the CDAx0 is defined by the
CDA_TSDP register of CDAx1 and the input port and time slot of CDAx1 is defined by
the CDA_TSDP register of CDAx0.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
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.
TSa
TSb
DU
Control
Register
CDAx0
0
1
1
Time Slot
Selection (TSS)
Enable
input
output
(EN_I1)
(EN_O1)
Input
Swap
(SWAP)
1
1
1
1
CDAx1
1
1
0
CDA_TSDPx1
1
0
Data Port
Selection (DPS)
Time Slot
Selection (TSS)
Enable
output
input
(EN_O0) (EN_I0)
Data Port
Selection (DPS)
CDA_TSDPx0
CDA_CRx
0
1
DD
TSa
TSb
IOM_HAND.FM4
x = 1 or 2; a,b = 0...11
Figure 22
Data Access via CDAx0 and CDAx1 register pairs
2.2.2.1.1 Looping and Shifting Data
Figure 23 gives examples for typical configurations with the above explained control and
configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = ’0’)
b) shifting data from TSa to TSb on DU and DD (SWAP = ’1’)
c) switching data from TSa (DU) to TSb(DD) and TSb (DU) to TSa (DD)
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a) Looping Data
TSa
TSb
CDAx0
CDAx0
.TSS: TSa
TSb
.DPS ’0’
’1’
.SWAP
’0’
DU
DD
b) Shifting Data
TSa
TSb
DU
CDAx0
CDAx0
DD
.TSS: TSa
.DPS ’0’
.SWAP
TSb
’1’
’1’
c) Switching Data
TSa
TSb
CDAx0
CDAx0
.TSS: TSa
.DPS ’0’
.SWAP
TSb
’0’
DU
DD
.x = 1 or 2
’1’
Figure 23
Examples for Data Access via CDAxy Registers
a) Looping Data
b) Shifting Data
c) Switching Data
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2.2.2.1.2 Monitoring Data
Figure 24 gives an example for monitoring of two IOM-2 time slots each on DU or DD
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd
numbers TS(2m+1) (n,m = 0...5). The user has to take care of this restriction by
programming the appropriate time slots.
.
a) Monitoring Data
EN_O: ’0’
CDA_CR1. EN_I: ’1’
DPS: ’0’
TSS: TS(2n)
’0’
’1’
’0’
TS(2m+1)
DU
CDA10
CDA11
CDA20
CDA21
TSS: TS(2n)
’1’
DPS:
CDA_CR2.
EN_I: ’1’
EN_O: ’0’
TS(2m+1)
’1’
’1’
’0’
DD
n,m = 0...5
Figure 24
Example for Monitoring Data
2.2.2.1.3 Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. The TSDPx0 must be set to 08h for monitoring from DU
or 88h for monitoring from DD respectively.
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2.2.2.1.4 Synchronous Transfer
While looping, shifting and switching (see figure 28 and 29) the data can be accessed by
the controller between the synchronous transfer interrupt (STI) and the synchronous
transfer overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy) and synchronous transfer
overflow interrupts (STOVxy) in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
A non masked synchronous transfer overflow (STOVx0y0) interrupt is generated if the
appropriate STIx1y1 is not acknowledged in time. The STIx1y1 is acknowledged in time if
bit ACKx1y1 in the ASTI register is set to ’1’ one BCL clock (for DPS=’0’) or zero BCL
clocks (for DPS=’1’) before the time slot which is selected for the appropriate STOVx0y0.
If STIx1y1 and STOVx1y1 are not masked STOVx1y1 is only related to STIx1y1 (see
example a), c) and d) of figure 26).
If STIx1y1 is masked but STOVx1y1 is not masked, STOVx0y0 is related to each enabled
STIxy (see example b) and d) of figure 26).
Setting the corresponding bits in the MSTI (Mask Synchronous Transfer Interrupts)
register masks the STIxy and the STOVxy interrupt. The interrupt structure of the
synchronous transfer is shown in figure 25. Examples of the described synchronous
transfer interrupt controlling are illustrated in Figure 26. A read to the STI register clears
the STIxy and STOVxy interrupts.
.
INT
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
MASK
ISTA
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
STI
ACK21
ACK20
ACK11
ACK10
ASTI
Figure 25
Interrupt Structure of the Synchronous Data Transfer
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.
: STI interrupt generated
: STOV interrupt generated for a not acknowledged STI interrupt
a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
’0’
’0’
11
TS1
’1’
’1’
21
TS5
’1’
’1’
TS11 TS0 TS1 TS2 TS3
20
TS11
’1’
’1’
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "last possible CDA
access"; MSTI.STI10 and MSTI.STOV20 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
’0’
’1’
11
TS1
’1’
’1’
21
TS5
’1’
’1’
TS11 TS0 TS1 TS2 TS3
20
TS11
’1’
’0’
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
c) Interrupts for data access to time slot 0 and 1 (B1 and B2 after reset), MSTI.STI10, MSTI.STOV10,
MSTI.STI11 and MSTI.STOV11 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
’0’
’0’
11
TS1
’0’
’0’
21
TS5
’1’
’1’
TS11 TS0 TS1 TS2 TS3
20
TS11
’1’
’1’
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
d) Interrupts for data access to time slot 0 (B1 after reset), STOV20 interrupt used as flag for "last possible CDA
access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and
MSTI.STOV20 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
’0’
’0’
11
TS1
’1’
’1’
21
TS5
’1’
’1’
TS11 TS0 TS1 TS2 TS3
20
TS11
’1’
’0’
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
sti_stov.vsd
Figure 26
Examples for the Synchronous Transfer Interrupt Control with one enabled STIxy
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Figure 27 shows the timing of looping TSa on DU to TSa on DD (a = 0...11) via CDAxy
register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...11
FSC
DU
TSa
TSa
WR
RD
µC
DD
TSa
STOV
*)
STI
ACK
STI
CDAxy
TSa
*) if access by the µC is required
Figure 27
Data Access when Looping TSa from DU to DD
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Figure 28 shows the timing of shifting data from TSa to TSb on DU(DD). In figure 28a)
shifting is done in one frame because TSa and TSb didn’t succeed direct one another
(a,b = 0...9 and b ≥ a+2). In figure 28b) shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
a) Shifting TSa → TSb within one frame
(a,b: 0...11 and b ≥ a+2)
FSC
DU
(DD)
TSa
TSb
TSa
µC
ACK
*)
STI
STOV
WR
STI
RD
CDAxy
b) Shifting TSa → TSb in the next frame
(a,b: 0...11 and (b = a+1 or b <a)
FSC
DU
(DD)
TSa
TSa
TSb
TSb
µC
*)
STI
STOV
WR
RD
STI
CDAxy
ACK
*) if access by the µC is required
Figure 28
Data Access when Shifting TSa to TSb on DU (DD)
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2.2.3
Serial Data Strobe Signal and strobed Data Clock
For time slot oriented standard devices connected to the IOM-2 interface the SCOUT
provides two independent data strobe signals SDS1 and SDS2. The SDS2 function is
shared with the RSTO function at pin RSTO/SDS2, therefore the SDS2 functionality
must be selected by setting the RSS bits in the MODE1 register to ’01’.
Instead of a data strobe signal a strobed IOM bit clock can be provided on pin SDS1 and
SDS2.
2.2.3.1
Serial Data Strobe Signal
The two strobe signals can be generated with every 8-kHz frame and are controlled by
the registers SDS1/2_CR. By programming the TSS bits and three enable bits
(ENS_TSS, ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM-2
time slots TS, TS+1 and TS+3 and any combination of them.
The data strobes for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data
strobe for TS+3 is always 2 bits long (bit7, bit6).
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Figure 29 shows three examples for the generation of a strobe signal. In example 1 the
SDS is active during channel B2 on IOM-2 whereas in the second example during IC1
and IC2. The third example shows a strobe signal for 2B+D channels which is used e.g.
at an IDSL (144kbit/s) transmission.
FSC
DD,DU
B1
B2
MON0
TS0
TS1
TS2
D CI0
MM
RX
TS3
IC1
IC2 MON1
TS4
TS5
TS6
CI1
MM
RX
TS7
TS8
TS9
TS10 TS11
TS0
TS1
SDS1,2
(Example1)
SDS1,2
(Example2)
SDS1,2
(Example3)
Example 1:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= ’0H’
= ’0’
= ’1’
= ’0’
Example 2:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= ’5H’
= ’1’
= ’1’
= ’0’
Example 3:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= ’0H’
= ’1’
= ’1’
= ’1’
strobe.vsd
Figure 29
Data Strobe Signal
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2.2.3.2
Strobed IOM-2 Bit Clock
The strobed IOM bit clock is active during the programmed window (see chapter 7.3.8).
Outside the programmed window a ’0’ is driven. Two examples are shown in figure 30.
FSC
DD,DU
B1
B2
TS0
TS1
M
MON0 D CI0 M
R X IC1
TS2
TS3
TS4
IC2 MON1
TS5
TS6
CI1
MM
RX
TS7
TS8
TS9
TS10 TS11
TS0
TS1
SDS1
(Example1)
SDS1
(Example2)
Setting of SDS1_CR:
Example 1:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= ’0H’
= ’0’
= ’0’
= ’1’
Example 2:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= ’5H’
= ’1’
= ’1’
= ’0’
bcl_strobed.vsd
Figure 30
Strobed IOM Bit Clock. Register SDS_CONF programmed to 01H or 03H
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2.2.4
IOM-2 Monitor Channel
The IOM-2 MONITOR channel (see figure 20) is utilized for information exchange
between the SCOUT and other devices connected to the MONITOR channel.
The MONITOR channel data can be controlled by the bits in the MONITOR control
register (MON_CR). For the MONITOR data one of the three IOM channels can be
selected by setting the MONITOR channel selection bits (MCS). The DPS bit in the same
register selects between an output on DU or DD respectively and with EN_MON the
MONITOR data can be enabled/disabled. The default value is MONITOR channel 0
(MON0) enabled and transmission on DD.
IOM-2 MONITOR Channel
V/D Module
e.g. ARCOFI-BA
PSB 2161
IOM-2 MONITOR Channel
V/D Module
e.g. Jade
PSB 7238
MONITOR Handler
CODEC
Layer 1
MONITOR Handler
CODEC
Layer 1
SCOUT
SCOUT
SCOUT as
Master Device
SCOUT as
Slave Device
µC
µC
IOM-2 MONITOR Channel
V/D Module
e.g. Jade
PSB 7238
MONITOR Handler
CODEC
Layer 1
SCOUT
SCOUT as
Master Device
µC
µC
monappl.vsd
Data Exchange between two Microcontroller Systems
Figure 31
Examples of MONITOR Channel Applications
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The MONITOR channel can be used in following applications which are illustrated in
figure 31:
• As a master device the SCOUT can program and control other devices attached to
the IOM-2 which do not need a microcontroller interface e.g. ARCOFI-BA PSB 2161.
This facilitates redesigning existing terminal designs in which e.g. an interface of an
expansion slot is realized with IOM-2 interface and monitor programming.
• As a slave device the codec and the transceiver part of the SCOUT is programmed
and controlled from a master device on IOM-2 (e.g. JADE PSB 7238). This is used in
applications where no microcontroller is connected directly to the SCOUT. The HDLC
controlling is processed by the master device therefore the HDLC data is transferred
via IOM-2 interface directly to the master device.
• For data exchange between two microcontroller systems attached to two different
devices on one IOM-2 backplane. Use of the MONITOR channel avoids the necessity
of a dedicated serial communication path between the two systems. This simplifies the
system design of terminal equipment.
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2.2.4.1
Handshake Procedure
The MONITOR channel operates on an asynchronous basis. While data transfers on the
bus take place synchronized to frame sync, the flow of data is controlled by a handshake
procedure using the MONITOR Channel Receive (MR) and MONITOR Channel
Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is
activated. This data will be transmitted once per 8-kHz frame until the transfer is
acknowledged via the MR bit.
The MONITOR channel protocol is described In the following section and illustrated in
Figure 32. The relevant control and status bits for transmission and reception are listed
in table 7 and table 8.
Table 7
Transmission of MONITOR Data
Control/
Status Bit
Register
Bit
Function
Control
MOCR
MXC
MX Bit Control
MIE
Interrupt (MDA, MAB, MER) Enable
MDA
Data Acknowledged Interrupt
MAB
Data Abort Interrupt
MAC
Transmission Active
Status
MOSR
MSTA
Table 8
Reception of MONITOR Data
Control/
Status Bit
Register
Bit
Function
Control
MOCR
MRC
MR Bit Control
MRE
Receive Interrupt (MDR) Enable
MDR
Data Received Interrupt
MER
End of Reception Interrupt
Status
Data Sheet
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Transmission
Reception
µC
MIE=1
MOX=ADR
MXC=1
MAC=1
MDA Int.
MOX=DATA1
MDA Int.
MOX=DATA2
MDA Int.
MXC=0
MAC=0
µC
MON
MX
MR
FF
FF
ADR
ADR
1
1
0
0
1
1
1
1
ADR
ADR
DATA1
DATA1
0
0
1
0
0
0
0
0
DATA1
DATA1
0
0
1
0
DATA2
DATA2
1
0
0
0
DATA2
DATA2
0
0
1
0
FF
FF
1
1
0
0
1
1
1
1
FF
FF
MRE=1
125µs
MDR Int.
RD MOR (=ADR)
MRC=1
MIE=1
MDR Int.
RD MOR
(=DATA1)
MDR Int.
RD MOR
(=DATA2)
MER Int.
MRC=0
Figure 32
MONITOR Channel Protocol (IOM-2)
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Before starting a transmission, the microcontroller should verify that the transmitter is
inactive, i.e. that a possible previous transmission has been terminated. This is indicated
by a ’0’ in the MONITOR Channel Active MAC status bit.
After having written the MONITOR Data Transmit (MOX) register, the microcontroller
sets the MONITOR Transmit Control bit MXC to ’1’. This enables the MX bit to go active
(0), indicating the presence of valid MONITOR data (contents of MOX) in the
corresponding frame. As a result, the receiving device stores the MONITOR byte in its
MONITOR Receive MOR register and generates an MDR interrupt status (MRE must be
’1’).
Alerted by the MDR interrupt, the microcontroller reads the MONITOR Receive (MOR)
register. When it is ready to accept data (e.g. based on the value in MOR, which in a
point-to-multipoint application might be the address of the destination device), it sets the
MR control bit MRC to ’1’ to enable the receiver to store succeeding MONITOR channel
bytes and acknowledge them according to the MONITOR channel protocol. In addition,
it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable
(MIE) to ’1’.
As a result, the first MONITOR byte is acknowledged by the receiving device setting the
MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA interrupt status at the
transmitter.
A new MONITOR data byte can now be written by the microcontroller in MOX. The MX
bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR
channel by returning the MX bit active after sending it once in the inactive state. As a
result, the receiver stores the MONITOR byte in MOR and generates a new MDR
interrupt status. When the microcontroller has read the MOR register, the receiver
acknowledges the data by returning the MR bit active after sending it once in the inactive
state. This in turn causes the transmitter to generate an MDA interrupt status.
This "MDA interrupt – write data – MDR interrupt – read data – MDA interrupt"
handshake is repeated as long as the transmitter has data to send.
When the last byte has been acknowledged by the receiver (MDA interrupt status), the
microcontroller sets the MONITOR Transmit Control bit MXC to ’0’. This enforces an
inactive (’1’) state in the MX bit. Two frames of MX inactive signifies the end of a
message. Thus, a MONITOR Channel End of Reception MER interrupt status is
generated by the receiver when the MX bit is received in the inactive state in two
consecutive frames. As a result, the microcontroller sets the MR control bit MRC to 0,
which in turn enforces an inactive state in the MR bit. This marks the end of the
transmission, making the MONITOR Channel Active MAC bit return to ’0’.
During a transmission process, it is possible for the receiver to ask a transmission to be
aborted by sending an inactive MR bit value in two consecutive frames. This is effected
by the microcontroller writing the MR control bit MRC to ’0’. An aborted transmission is
indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter.
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The MONITOR transfer protocol rules are summarized in the following section
• A pair of MX and MR in the inactive state for two or more consecutive frames indicates
an idle state or an end of transmission.
• A start of a transmission is initiated by the transmitter by setting the MXC bit to ’1’
enabling the internal MX control. The receiver acknowledges the received first byte by
setting the MR control bit to ’1’ enabling the internal MR control.
• The internal MX,MR control indicates or acknowledges a new byte in the MON slot by
toggling MX,MR from the active to the inactive state for one frame.
• Two frames with the MX-bit in the inactive state indicate the end of transmission.
• Two frames with the MR-bit set to inactive indicate a receiver request for abort.
• The transmitter can delay a transmission sequence by sending the same byte
continuously. In that case the MX-bit remains active in the IOM-2 frame following the
first byte occurrence.
• Since a double last-look criterion is implemented the receiver is able to receive the
MON slot data at least twice (in two consecutive frames). The receiver acknowledge
the data after the reception of two identical bytes in two successive frames.
• To control this handshake procedure a collision detection mechanism is implemented
in the transmitter. This is done by making a collision check per bit on the transmitted
MONITOR data and the MX bit.
• Monitor data will be transmitted repeatedly until its reception is acknowledged or the
transmission time-out timer expires.
• Two frames with the MX bit in the inactive state indicates the end of a message
(EOM).
• Transmission and reception of monitor messages can be performed simultaneously.
This feature is used by the SCOUT to send back the response before the transmission
from the controller is completed (the SCOUT does not wait for EOM from the
controller). MONITOR control commands nevertheless are processed sequential that
means e.g. during a read on a register no further command is executed.
2.2.4.2
Error Treatment
In case the SCOUT does not detect identical monitor messages in two successive
frames, transmission is not aborted. Instead the SCOUT will wait until two identical bytes
are received in succession.
A transmission is aborted by the SCOUT if
• an error in the MR handshaking occurs
• a collision on the IOM bus of the MONITOR data or MX bit occurs
• the transmission time-out timer expires
A reception is aborted by the SCOUT if
• an error in the handshaking occurs or
• an abort request from the opposite device occurs
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MX/MR Treatment in Error Case:
In the master mode the MX/MR bits are under control of the microcontroller through MXC
or MRC respectively. An abort is indicated by an MAB interrupt or MER interrupt
respectively.
In the slave mode the MX/MR bits are under control of the SCOUT. An abort is always
indicated by setting the MX/MR bit inactive for two or more IOM-2 frames. The controller
must react with EOM.
Figure 33 shows an example for an abort requested by the receiver, Figure 34 shows
an example for an abort requested by the transmitter and Figure 35 shows an example
for a successful transmission.
IOM -2 Frame No.
MX (DU)
1
2
3
4
5
6
7
1
EOM
0
MR (DD)
1
0
Abort Request from Receiver
mon_rec-abort.vsd
Figure 33
Monitor Channel, Transmission Abort requested by the Receiver
IOM -2 Frame No.
MR (DU)
1
2
3
4
5
6
7
1
EOM
0
MX (DD)
1
0
Abort Request from Transmitter
mon_tx-abort.vsd
Figure 34
Monitor Channel, Transmission Abort requested by the Transmitter
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IOM -2 Frame No.
MR (DU)
1
2
3
4
5
6
7
8
1
EOM
0
MX (DD)
1
0
mon_norm.vsd
Figure 35
Monitor Channel, normal End of Transmission
2.2.4.3
MONITOR Channel Programming as a Master Device
As a master device the SCOUT can program and control other devices attached to the
IOM-2 interface. The master mode is selected by default if the microcontroller interface
is used. The monitor data is written by the microcontroller in the MOX register and
transmitted via IOM-2 DD(DU) line to the programmed/controlled device e.g. ARCOFIBA PSB 2161. The transfer of the commands in the MON channel is regulated by the
handshake protocol mechanism with MX, MR which is described in the previous
chapters 2.2.4.1 and 2.2.4.2.
If the transmitted command was a read command the slave device responds by sending
the requested data.
The data structure of the transmitted monitor message depends on the device which is
programmed. Therefore the first byte of the message is a specific address code which
contains in the higher nibble a MONITOR channel address to identify different devices.
The length of the messages depends on the accessed device and the command
following the address byte.
2.2.4.4
MONITOR Channel Programming as a Slave Device
Applications in which no controller is connected to the SCOUT it must operate in the
MONITOR slave mode which can be selected by pinstrapping the microcontroller
interface pins according to chapter 2.1. As a slave device the codec and the transceiver
part of the SCOUT is programmed and controlled by a master device at the IOM-2
interface. All programming data required by the SCOUT are received in the MONITOR
time slot of channel 0 on the IOM-2 and is transferred in the MOR register. The transfer
of the commands in the MON channel is regulated by the handshake protocol
mechanism with MX, MR which is described in the previous chapters 2.2.4.1 and 2.2.4.2
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The first byte of the MONITOR message must contain in the higher nibble the MONITOR
channel address code which is ’1010’ for the SCOUT. The lower nibble distinguishes
between a programming command or an identification command.
Identification Command
In order to be able to identify unambiguously different hardware designs of the SCOUT
by software, the following identification command is used:
DD 1st byte value
1
0
1
0
0
0
0
0
DD 2nd byte value
0
0
0
0
0
0
0
0
The SCOUT responds to this DD identification sequence by sending a DU identification
sequence:
DU 1st byte value
1
0
DU 2nd byte value
1
0
1
0
0
0
0
0
DESIGN
<IDENT>
DESIGN: six bit code, specific for each device in order to identify differences in operation
(see chapter 7.2.14).
This identification sequence is usually done once, when the terminal is connected for the
first time. This function is used by the software to distinguish between different possible
hardware configurations. However this sequence is not compulsory.
Programming Sequence
The programming sequence is characterized by a ’1’ being sent in the lower nibble of the
received address code. The data structure after this first byte is equivalent to the
structure of the serial control interface described in chapter 2.1.1.
DD 1st byte value
1
0
1
DD 2nd byte value
DD 3rd byte value
0
0
0
0
1
Header Byte
R/W
Command/
Register Address
DD 4th byte value
Data 1
DD (nth + 3) byte value
Data n
All registers can be read back when setting the R/W bit to ’1’ in the byte for the command/
register address. The SCOUT responds by sending his IOM specific address byte (A1h)
followed by the requested data.
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2.2.4.5
MONITOR Time-Out Procedure
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be
enabled by setting the time-out bit (TOUT) in the MONITOR configuration register
(MCONF). An internal timer is always started when the transmitter must wait for the reply
of the addressed device or for transmit data from the microcontroller. After 40 IOM
frames (5ms) without reply the timer expires and the transmission will be aborted.
2.2.4.6
MONITOR Interrupt Logic
Figure 36 shows the MONITOR interrupt structure of the SCOUT. The MONITOR Data
Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable
(MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER,
MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB
interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE inactive (0) prevents the occurrence of MDR status, including when the first byte of
a packet is received. When MRE is active (1) but MRC is inactive, the MDR interrupt
status is generated only for the first byte of a receive packet. When both MRE and MRC
are active, MDR is always generated and all received MONITOR bytes - marked by a 1to-0 transition in MX bit - are stored. (Additionally, an active MRC enables the control of
the MR handshake bit according to the MONITOR channel protocol.)
MASK
ISTA
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
MRE
MDR
MER
MIE
MDA
MAB
MOSR
MOCR
INT
Figure 36
MONITOR Interrupt Structure
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2.2.5
C/I Channel Handling
The Command/Indication channel carries real-time status information between the
SCOUT and another device connected to the IOM.
1) One C/I channel (called C/I0) conveys the commands and indications between the
layer-1 and the layer-2 parts of the SCOUT. It can be accessed by an external layer-2
device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel
access may be arbitrated via the TIC bus access protocol. In this case the arbitration is
done in C/I channel 2 (see figure 20).
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2)
and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits
long. A listing and explanation of the layer-1 C/I codes can be found in chapter 2.3.7.1.3
and 2.3.7.1.5. In the receive direction, the code from layer-1 is continuously monitored,
with an interrupt being generated anytime a change occurs (ISTA.CIC). A new code
must be found in two consecutive IOM frames to be considered valid and to trigger a C/
I code change interrupt status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
2) A second C/I channel (called C/I1) can be used to convey real time status information
between the SCOUT and various non-layer-1 peripheral devices e.g. PSB 2161
ARCOFI-BA. The C/I1 channel consists of four or six bits in each direction.The width can
be changed from 4bit to 6bit by setting bit CIX1.CICW.
The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received
C/I1 code is indicated by an interrupt status without double last look criterion.
2.2.5.1
CIC Interrupt Logic
Figure 37 shows the CIC interrupt structure.
A CIC interrupt may originate
– from a change in received C/I channel 0 code (CIC0)
or
– from a change in received C/I channel 1 code (CIC1).
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is issued every time a valid new code is loaded into CIR0 or CIR1.
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0.
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If several consecutive codes are detected, only the first and the last code is obtained at
the first and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
MASK
ISTA
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
CI1E
CIX1
CIC0
CIC1
CIR0
INT
Figure 37
CIC Interrupt Structure
2.2.6
Settings after Reset (see also chapter 7.3)
After reset the codec, the TIC-bus access, the serial data strobes (pin SDS1 and SDS2)
and the controller data access are disabled.
The IOM handler is enabled except the generation of the bit clock (pin BCL).
The monitor handler is enabled for channel MON0 and the transceiver for the channels
B1, B2, C/I0 and D.
The HDLC controller is connected to the D channels.
The pins DD and DU are in open drain state.
The synchronous transfer interrupts and synchronous transfer overflow interrupts are
masked.
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2.2.7
D-Channel Access Control
D-channel access control was defined to guarantee all connected HDLC controllers a fair
chance to transmit data in the D-channel.
Collisions are possible on the IOM-2 interface, if there are more than one HDLC
controller connected, or on the S-interface if there are more than one terminal connected
in a point to multipoint configuration (NT -> TE1 ... TE8). Both arbitration mechanisms
are implemented in the SCOUT and will be described in the following two chapters.
2.2.7.1
TIC Bus D-Channel Access Control
The TIC bus is implemented to organize the access to the layer-1 functions provided in
the SCOUT (C/I-channel) and to the D-channel from up to 7 external communication
controllers (see figure 38).
To this effect the outputs of the controllers (ICC:ISDN Communication Controller PEB
2070) are wired-or and connected to pin DU. The inputs of the ICCs are connected to
pin DD. External pull-up resistors on DU/DD are required. The arbitration mechanism
must be activated by setting MODEH.DIM2-0=00x.
µC-Interface
IOM-2 Interface
ICC(7)
B-channel
Voice/Data
Communication
with D-channel
Signaling
ICC(1)
TIC Bus
D-channel
Telemetry/
Packet
Communication
S-Interface
B-channel
Voice/Data
Communication
with D-channel
Signaling
TIC Bus
D-channel
Access Control
S-Transceiver
U-Interface
NT
SCOUT-S(X)
TIC_ARBI-S0.vsd
Figure 38
Applications of TIC Bus in IOM-2 Bus Configuration
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The arbitration mechanism is implemented in the last octet in IOM channel 2 of the IOM2 interface (see figure 39). An access request to the TIC bus may either be generated
by software (µP access to the C/I channel) or by the SCOUT itself (transmission of an
HDLC frame in the D-channel). A software access request to the bus is effected by
setting the BAC bit (CIX0 register) to ’1’.
In the case of an access request, the SCOUT checks the Bus Accessed-bit BAC (bit 5
of DU last octet of channel 2, see figure 39) for the status "bus free“, which is indicated
by a logical ’1’. If the bus is free, the SCOUT transmits its individual TIC bus address TAD
programmed in the CIX0 register and compares it bit by bit with the value on DU. If a sent
bit set to ’1’ is read back as ’0’ because of the access of another D-channel source with
a lower TAD, the SCOUT withdraws immediately from the TIC bus. The TIC bus is
occupied by the device which sends its address error-free. If more than one device
attempt to seize the bus simultaneously, the one with the lowest address wins and starts
D-channel transmission.
MR
MX
DU
%
%
021 ' &,
,&
MR
MX
,&
021
TAD
BAC
&,
%$&
7$'
TIC-Bus Address (TAD 2-0)
Bus Accessed (’1’ no TIC-Bus Access)
tic_octet-du.vsd
Figure 39
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the SCOUT, the bus is identified to other devices as
occupied via the DU channel 2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the SCOUT is automatically set into a lower
priority class, that is, a new bus access cannot be performed until the status "bus free"
is indicated in two successive frames.
If none of the devices connected to the IOM interface requests access to the D and C/I
channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Note: Bit BAC (CIX0 register) should be reset by the µP when access to the C/I channels
is no more requested, to grant other devices access to the D and C/I channels.
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The availability of the line interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the
DD last octet of channel 2 (figure 40).
S/G = 1 : stop
S/G = 0 : go
MR
MX
DD
%
%
021
'
&,
,&
MR
MX
,&
(
021
(
6*
A/B
S/G
&,
$%
Available/Blocked
Stop/Go
E bits received on S
tic_octetdd-s0.vsd
Figure 40
Structure of Last Octet of Ch2 on DD
The Stop/Go bit is available to other layer-2 devices connected to the IOM to determine
if they can access the D channel of the S/T interface.
For test purposes the E bits received on the S/T interface are transparently transferred
data downstream to bits 7 and 6 of the last octet of channel 2.
2.2.7.2 S-Bus Priority Mechanism for D-Channel
The S-bus D-channel access procedure specified in ITU I.430 was defined to organize
D-channel access with multiple TEs connected to a single S-bus (see figure 41).
The D-channel S-bus status is indicated towards the IOM-2 interface with the S/G bit
(see previous section).
The priority mechanism as specified in ITU I.430 is fully implemented in the SCOUT. For
this purpose the D-channel collision detection according to ITU I.430 must be enabled
by setting DIM2-0 in the register MODEH to ’0x1’.
In this case the SCOUT continuously compares the D data bits with the received E-echo
bits. If the S/G bit is set to ’0’ the 1st D-bit, contained in the IOM-2 frame following the S/
G bit appears on the S/T bus in time (after 8, 9, 10, 11 consecutive logical ’1’s).
The priority class (priority 8 or priority 10) is selected by transferring the appropriate
activation command via the Command/Indication (C/I) channel of the IOM-2 interface to
the SCOUT S-interface. If the activation is initiated by a TE, the priority class is selected
implicitly by the choice of the activation command. If the S-interface is activated from the
NT, an activation command selecting the desired priority class should be programmed
at the TE on reception of the activation indication (AI8 or AI10).
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In the activated state the priority class may be changed whenever required by simply
programming the desired activation request command (AR8 or AR10). Priority change is
accepted without the double last-look criterion.
The S-transceiver will not be transparent in transmit direction for the B- and D- channels
before an AR command has been written to CIX0.
Figure 41
D-Channel Access Control on the S-Interface
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The following scheme illustrates a priority class 8/10 selection with NT initiated activation
and with TE initiated activation
1. Priority Class 8/10 Selection with NT Initiated Activation
TE IOM-2
NT IOM-2
←
C/I
DC
(1111b)
C/I
DC
(1111b)
←
→
C/I
DI
(1111b)
C/I
DI
(1111b)
→
←
C/I
AR
(1000b)
C/I
AR
(1000b)
➞
; Start activation from
←
C/I
AI8
(1100b)
C/I
AR
(1000b)
→
; NT side
C/I
Al
(1100b)
→
; Allocate highest priority
C/I
Al
(1100b)
➞
; (e.g. for signaling data)
➞
➞
C/I
AR8
(1000b)
D: transfer signalling
; Allocate lower priority
C/I
; for packet data
AR10 (1001b)
D: transfer packet data
←
C/I
AI10
(1101b)
2. Priority Class 8/10 Selection with TE Initiated Activation
TE IOM-2
NT IOM-2
←
C/I
DC
(1111b)
C/I
DC
(1111b)
←
→
C/I
DI
(1111b)
C/I
DI
(1111b)
→
➞
C/I
AR10 (1001b)
C/I
AR
(1000b)
; Start activation with lower
D: transfer packet data
; priority for packet data
←
←
C/I
RSY
(0100b)
C/I
AR
(1000b)
➞
C/I
AR
(1000b)
C/I
AI
(1100b)
→
←
C/I
AI10
(1101b)
C/I
AI
(1100b)
➞
➞
C/I
AR8
(1000b)
;
; Allocate highest priority
D: transfer signalling
←
C/I
Data Sheet
AI8
(1100b)
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2.2.8
Activation/Deactivation of IOM-2 Interface
The IOM-2 interface can be switched off in the inactive state, reducing power
consumption to a minimum. In this deactivated state is FSC = ’1’, DCL = ’0’ and BCL =
’1’ ’ and the data lines are ’1’. The data between the functional blocks of the SCOUT is
then transferred internally.
The IOM-2 interface can be kept active while the line interface is deactivated by setting
the CFS bit to "0" (MODE register). This is the case after a hardware reset. If the IOM-2
interface should be switched off while the S interface is deactivated, the CFS bit should
be set to ’1’. In this case the internal oscillator is disabled when no signal (info 0) is
present on the line interface and the C/I command is ’1111’ = DIU (see chapter 2.3.8
and 2.3.7.1.3). If the TE wants to activate the line, it has first to activate the IOM-2
interface either by using the "Software Power Up" function (IOM_CR.SPU bit) or by
setting the CFS bit to "0" again.
The deactivation procedure is shown in figure 42. After detecting the code DI
(Deactivate Indication) the layer 1 of the SCOUT responds by transmitting DC
(Deactivate Confirmation) during subsequent frames and stops the timing signals
synchronously with the end of the last C/I (C/I0) channel bit of the 10th frame.
IOM-2
IOM-2
Deactivated
FSC
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DR
DR
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DU
DR
DD
B1
B2
D
D CIO
CIO
DCL
ITD09655
Figure 42
Deactivation of the IOM®-Interface
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The clock pulses will be enabled again when the DU line is pulled low (e.g. bit SPU in
the IOM_CR register) or when a non-zero level on the line interface is detected and
TR_CONF0.LDD is set to ’0’. The clocks are turned on after approximately 0.2 to 4 ms
depending on the capacitances on XTAL 1/2.
DCL is activated such that its first rising edge occurs with the beginning of the bit
following the C/I (C/I0) channel.
After the clocks have been enabled this is indicated by the PU code in the C/I channel
and by a CIC interrupt. The DU line may be released by resetting the Software Power
Up bit IOM_CR.SPU = ’0’ and the C/I code written to CIX0 before (e.g. TIM or AR8) is
output on DU.
The SCOUT supplies IOM timing signals as long as there is no DIU command in the C/
I (C/I0) channel. If timing signals are no longer required and activation is not yet
requested, this is indicated by programming DIU in the CIX0 register.
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CIC : CIXO = TIM
Int. SPU = 0
~~
SPU = 1
FSC
TIM
TIM
TIM
PU
PU
PU
~~
DU
~~
PU
PU
~~
DD
~~
IOM -CH1
IOM -CH2
IOM -CH2
~~
~~
~~ ~~
DU
~~ ~~
FSC
~~
R
R
B1
DD
MR MX
~~
~~
0.2 to 4 ms
R
R
IOM -CH1
B1
~~
DCL
132 x DCL
ITD09656
Figure 43
Activation of the IOM-Interface
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2.3
S/T Interface
The layer-1 functions for the S/T interface of the SCOUT are:
– line transceiver functions for the S/T interface according to the electrical specifications
of ITU-T I.430
– conversion of the frame structure between IOM and S/T interface
– conversion from/to binary to/from pseudo-ternary code
– level detection
– receive timing recovery
– IOM timing synchronous to the S/T interface
– D-channel access as specified in ITU I.430 (see chapter 2.2.7.2)
– activation/deactivation procedures, triggered by primitives received over the IOM C/I
channel or by INFO's received from the line
– execution of test loops.
2.3.1
Wiring Configurations
The wiring configurations in user premises, in which the SCOUT can be used, are
illustrated in figure 44.
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Point-to-Point
Configurations
Short Passive
Bus
...
Extended
Passive
Bus
...
Figure 44
Wiring Configurations in User Premises
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2.3.2
Frame Structure
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see figure 45).
In the direction TE → NT the frame is transmitted with a two bit offset. For details on the
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT → TE and TE → NT) with all framing
and maintenance bits.
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Figure 45
Frame Structure at Reference Points S and T (ITU I.430)
– F
Framing Bit
F = (0b) → identifies new frame (always
positive pulse)
– L.
D.C. Balancing Bit
L. = (0b) → number of binary ZEROs sent
after the last L. bit was odd
– D
D-Channel Data Bit
Signaling data specified by user
– E
D-Channel Echo Bit
E = D → no D-channel collision. ZEROs
overwrite ONEs
– FA
Auxiliary Framing Bit
See section 6.3 in ITU I.430
– N
N = FA
– B1
B1-Channel Data Bit
User data
– B2
B2-Channel Data Bit
User data
– A
Activation Bit
A = (0b) → INFO 2 transmitted
A = (1b) → INFO 4 transmitted
– S
S-Channel Data Bit
S1 channel data (see note below)
– M
Multiframing Bit
M = (1b) → Start of new multi-frame
Note: The ITU I.430 standard specifies S1 - S5 for optional use.
The SCOUT supports S1
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2.3.3
Multi-Framing
According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in
the TE-to-NT direction through the use of an extra channel between the TE and NT (Qchannel). The Q bits are defined to be the bits in the FA bit position.
In the NT-to-TE direction the S-channel bits are used for information transmission. One
S-channel (S1) out of five possible S-channels can be accessed by the SCOUT.
The S- and Q-channels are accessed via the µC interface or the IOM-2 MONITOR
channel respectively by reading/writing the SQR or SQX bits in the S/Q channel registers
(SQRR, SQXR).
Table 9 shows the S and Q bit positions within the multi-frame.
Table 9 S/Q-Bit Position Identification and Multi-Frame Structure
Frame Number
NT-to-TE
FA Bit Position
NT-to-TE
M Bit
NT-to-TE
S Bit
TE-to-NT
FA Bit Position
1
2
3
4
5
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
S11
ZERO
ZERO
ZERO
ZERO
Q1
ZERO
ZERO
ZERO
ZERO
6
7
8
9
10
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S12
ZERO
ZERO
ZERO
ZERO
Q2
ZERO
ZERO
ZERO
ZERO
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S13
ZERO
ZERO
ZERO
ZERO
Q3
ZERO
ZERO
ZERO
ZERO
16
17
18
19
20
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S14
ZERO
ZERO
ZERO
ZERO
Q4
ZERO
ZERO
ZERO
ZERO
1
2
ONE
ZERO
ONE
ZERO
S11
ZERO
Q1
ZERO
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After multi-frame synchronization has been established, the Q data will be inserted at the
upstream (TE → NT) FA bit position in each 5th S/T frame (see table 9).
When synchronization is not achieved or lost, each received FA bit is mirrored to the next
transmitted FA bit.
Multi-frame synchronization is achieved after two complete multi-frames have been
detected with reference to FA/N bit and M bit positions. Multi-frame synchronization is lost
if bit errors in FA/N bit or M bit positions have been detected in two consecutive multiframes. The synchronization state is indicated by the MSYN bit in the S/Q-channel
receive register (SQRR).
The multi-frame synchronization can be enabled or disabled by programming the MFEN
bit in the S/Q-channel transmit register (SQXR).
2.3.3.1
Interrupt Handling for Multi-Framing
To trigger the microcontroller for a multi-frame access an interrupt can be generated
once per multi-frame or if the 4 bits of the received S-channel have changed (see
chapter 7.2.8).
In both cases the microcontroller has access to the multi-frame within 18 S frames (4.5
ms).
2.3.4
Line Code
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
The first binary ZERO following the framing balance bit is of the same polarity as the
framing-balancing bit and the last binary ZERO before the framing bit is of the same
polarity as the framing bit (required code violations).
Figure 46
S/T -Interface Line Code (without code violation)
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2.3.5
Phase Deviation
The S/T transmitter is shifted by two S/T bits - 7 oscillator periods (plus analog delay plus
delay of the external circuitry) with respect to the received frame. To compensate
additional delay introduced into the receive and transmit path by the external circuit the
delay of the transmit data can be reduced by another two oscillator periods (260 ns).
Therefore PDS of the TR_CONF2 register must be programmed to ’1’. This delay
compensation might be necessary in order to comply with the "total phase deviation input
to output" requirement of ITU-T recommendation I.430 which specifies a phase deviation
in the range of – 7% to + 15% of a bit period.
2.3.6
Data Transfer and Delay between IOM and S/T Interface
In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register TR_CMD is programmed to ’011’ the B1, B2, D and E bits are transferred
transparently from the S/T to the IOM interface. In all other states ’1’s are transmitted to
the IOM interface.
To transfer data transparently to the S/T interface any activation request C/I command
(AR8, AR10 or ARL) is additionally necessary or if the internal layer-1 statemachine is
disabled bit TDDIS of register TR_CMD has additionally to be programmed to ’0’.
Figure 47 shows the data delay between the IOM and the S/T interface and vise versa.
For the D channel the delay from the IOM to the S/T interface is only valid if S/G
evaluation is disabled (see chapter 2.2.7.2).
E
NT -> TE
F
D
E
B1
D
B2
D
TE -> NT
F
B1
E
D
E
B1
B2
D
D
B2
B1
D
E
F
E
B1
D
B2
D
F
D
B2
D
B1
B2
E
D
E
B1
B2
D
D
B1
D
D
B2
FSC
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
DD
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
line_iom_s.vsd
Figure 47
Data Delay between IOM and S/T Interface
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2.3.7
Control of Layer-1
The layer-1 activation/ deactivation can be controlled by an internal statemachine via the
IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the default
state the internal layer-1 state machine of the SCOUT-SX) is used.
To disable the internal state machine TR_CONF0.L1SW must be set to ’1’ and a C/I code
TIM (’0000’) has to be programmed into CIX0.CODX0
If the internal state machine is disabled the layer-1 commands, which are normally
generated by the internal state machine can be written directly into the TR_CMD register
or the received status read out from the TR_STA register respectively. The SCOUT
layer-1 control flow is shown in figure 48.
Disable internal
Statemachine
(TR_CONF.L1SW)
CIX0
CIR0
Register
C/I
Command
C/I
Indication
Layer-1
State
Machine
Transmit
Command Register
INFO
for Transmitter
Transmitter
(TR_CMD)
Receive
Status Register
INFO
of Receiver
Receiver
(TR_STA)
Layer-1 Control
Microcontroller Interface
layer1_ctl.vsd
Figure 48
Layer-1 Control
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2.3.7.1
Internal Layer-1 Statemachine
In the following sections the layer-1 control by the SCOUT statemachine will be
described. For the description of the IOM-2 C/I0 channel see also chapter 2.2.5.
The layer-1 functions are controlled by commands issued via the C/I channel 0 of the
IOM interface to the layer-1 to trigger certain procedures, such as activation/
deactivation, switching of test loops and transmission of special pulse patterns.
Responses from layer-1 are obtained by indications via the C/I channel 0 of the IOM
interface.
2.3.7.1.1 State Transition Diagram
The activation/deactivation procedure implemented in the SCOUT agrees to the
requirements set forth in ITU recommendations. State identifiers F1-F8 are in
accordance with ITU I.430.
The statemachine includes all information relevant to the user. The state diagram
notation is given in figure 49.
The informations contained in the state diagrams are:
– state name (based on ITU I.430)
– Signal received from the S/T interface (INFO)
– Signal transmitted to the S/T interface (INFO)
– C/I code received (commands)
– C/I code transmitted (indications)
– transition criteria
The transition criteria are grouped into:
– C/I commands
– Signals received from the S/T interface (INFOs)
– Reset
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OUT
IOM-2 Interface
C/I code
IN
Unconditional
Transition
Ind. Cmd.
State
S/T Interface
INFO
ix
ir
statem_notation_s.vsd
Figure 49
State Diagram Notation
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “∗” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
The sections following the state diagram contain detailed information on all states and
signals used.
Figure 50 shows the state transition diagram of the SCOUT statemachine.
Figure 51 shows this for the unconditional transitions (Reset, Loop, Test Modi i).
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DI
TIM
F3
Power Down
DC
i4
i0
i0
AR i2
DI
PU AR1)
DI
AR
F4
Pending Act.
i1
TIM
i0
RSY
i2
i0
i4
X
TIM
F5
Unsynchronized
DI
i0
TIM
F3
Power Up
i0
i0
i4
PU
X
DI
TIM
Uncond. State
ix
i2
AR
X
X3)
F6
Synchronized
i3
i2
ix+i0
i4
i2
i4
i2
RSY
X
DI
TIM
F8
Lost Framing
i0*TO1
ix
i0
i2 DI
ix+i0
AI2) AR1)
i4
F7
Activated
i3
i4
1)
AR stands for AR8 or AR10
2)
AI stands for AI8 or AI10
3)
X stands for commands initiating unconditional
transitions (RES, ARL, TM1 or TM2)
DR
X
TIM
F3
Pending Deact.
i0
TO1:
TO2:
i0
16 ms
0.5 ms
statem_te_s.vsd
Figure 50
State Transition Diagram
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TMi
TIM
DI
TMi
TMi
Test Mode i
iti
RESET1)
ARL
TIM
DI
*
PU
ARL
Loop A Closed
i3
DI
RES RES
Reset
i0
*
i3
AIL ARL
Loop A Activated
i3
1)
DI
*
i3
TIM
TIM
*
Possible reset sources:
C/I command RES
software reset via SRES.RES_TR or
reset from pin RST
statem_te_aloop_s.vsd
Figure 51
State Transition Diagram of the Unconditional Transitions
2.3.7.1.2 States
F3 Pending Deactivation
State after deactivation from the S/T interface by info 0. Note that no activation from the
terminal side is possible starting from this state. A ’DI’ command has to be issued to enter
the state ’Power Down’.
F3 Power Down
The S/T interface is deactivated and the IOM-2 interface is or will be deactivated if the
CFS bit of the MODE1 register is set to “1“. Activation is possible from the S/T interface
and from the IOM-2 interface.
F3 Power Up
The S/T interface is deactivated and the IOM-2 interface is activated, i.e. the clocks are
running.
F4 Pending Activation
The SCOUT transmits info 1 towards the network, waiting for info 2.
F5 Unsynchronized
Any signal except info 2 or 4 detected on the S/T interface.
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F6 Synchronized
The receiver has synchronized and detects info 2. Info 3 is transmitted to synchronize
the NT.
F7 Activated
The receiver has synchronized and detects info 4. All user channels are now conveyed
transparently to the IOM interface.
To transfer user channels transparently to the S/T interface either the command AR8 or
AR10 has to be issued.
F8 Lost Framing
The receiver has lost synchronization in the states F6 or F7 respectively.
Unconditional States
Loop A Closed (internal or external, see chapter 2.3.10.1)
The SCOUT loops back the transmitter to the receiver and activates by transmission of
info 3. The receiver has not yet synchronized.
For a non transparent internal loop the DIS_TX bit of register TR_CONF2 has to be set
to ’1’.
Loop A Activated (internal or external, see chapter 2.3.10.1)
The receiver has synchronized to info 3. Data may be sent. The indication “AIL” is output
to indicate the activated state.
Test Mode 1
Single alternating pulses are transmitted to the S/T-interface resulting in a frequency of
the fundamental mode of 2 kHz.
Test Mode 2
Continuous alternating pulses are transmitted to the S/T-interface resulting in a
frequency of the fundamental mode of 96 kHz.
Reset
A hardware reset, the C/I command RES or setting the RES_TR bit in the SRES register
to ’1’ forces the SCOUT to an idle state where info 0 is transmitted. Thus activation from
the NT is not possible.
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2.3.7.1.3 C/I Commands
Command
Abbr. Code Remark
Activation Request with
priority class 8
AR8
1000
Activation requested by the SCOUT, Dchannel priority set to 8 (see note)
Activation Request with
priority class 10
AR10 1001
Activation requested by the SCOUT, Dchannel priority set to 10 (see note)
Activation Request Loop ARL
1010
Activation requested for the internal or
external Loop A (see note).
For a non transparent internal loop bit
DIS_TX of register TR_CONF2 has to be set
to ’1’ additionally.
Deactivation Indication
DI
1111
Deactivation Indication
Reset
RES
0001
Reset of the layer-1 statemachine
Timing
TIM
0000
Layer-2 device requires clocks to be
activated
Test mode 1
TM1
0010
One AMI-coded pulse transmitted in each
frame, resulting in a frequency of the
fundamental mode of 2 kHz
Test mode 2
TM2
0011
AMI-coded pulses transmitted continuously,
resulting in a frequency of the fundamental
mode of 96 kHz
Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only
transferred transparently to the S/T interface if one of the three “Activation
Request” commands is issued.
2.3.7.1.4 Receive Infos on S/T (Downstream)
Name
Abbr. Description
info 0
i0
No signal on S/T
info 2
i2
4 kHz frame
A=’0’
info 4
i4
4 kHz frame
A=’1’
info X
ix
Any signal except info 2 or info 4
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2.3.7.1.5 C/I Indications
Indication
Abbr. Code Remark
Deactivation Request
DR
0000
Deactivation request via S/T-interface if left
from F7/F8
Reset
RES
0001
Reset acknowledge
Test mode 1
TM1
0010
TM1 acknowledge
Test mode 2
TM1
0010
TM2 acknowledge
Resynchronization
during level detect
RSY
0100
Signal received, receiver not synchronous
Power up
PU
0111
IOM-2 interface clocking is provided
Activation request
AR
1000
Info 2 received
Activation request loop ARL
1010
Internal or external loop A closed
Far-end-code-violation CVR
1011
Illegal code violation received. This function
has to be enabled by setting the EN_FECV bit
of register TR_CONF0 (see chapter 7.2.1).
Activation indication
loop
AIL
1110
Internal or external loop A activated
Activation indication
with priority class 8
AI8
1100
Info 4 received,
D-channel priority is 8 or 9.
Activation indication
with priority class 10
AI10
1101
Info 4 received,
D-channel priority is 10 or 11.
Deactivation
confirmation
DC
1111
Clocks will be disabled if CFS bit of register
MODE1 is set to ’1’ (see chapter 7.2.12),
quiescent state
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2.3.7.1.6 Transmit Infos on S/T (Upstream)
Name
Abbr. Description
info 0
i0
No signal on S/T
info 1
i1
Continuous bit sequence of the form ’00111111’
Pulses are AMI-coded
info 3
i3
4 kHz frame
Test info 1
it1
One AMI-coded pulse is transmitted in each frame,
resulting in a frequency of the fundamental mode of
2 kHz
Test info 2
it2
AMI-coded pulses are transmitted continuously,
resulting in a frequency of the fundamental mode of
96 kHz
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2.3.7.1.7 Example of Activation/Deactivation
An example of an activation/deactivation of the S/T interface initiated by the terminal with
the time relationships mentioned in the previous chapters is shown in figure 52.
µC Interface
SPU=0, CFS=1
IOM-2 Interface (C/I)
TE
S/T Interface
DC
NT
IOM-2 Interface (C/I)
DC
INFO 0
DI
DI
SPU=1
PU
SPU=0
INFO 1
AR
AR
INFO 2
RSY
T1
ARD
INFO 3
AR
T1
AI
INFO 4
AID
T2
AI
INFO 0
DR
T3
TIM
DR
INFO 0
DI
T3
DC
DI
INFO 0
DC
T1: < 1.5 ms time for synchronization
T2:
0.5 ms time for detecting INFO4
T3:
16 ms time for error free detection of INFO 0
act_deac_te_int_s.vsd
Figure 52
Example of Activation/Deactivation initiated by the Terminal (TE).
Activation/Deactivation under Control of the internal Layer-1 Statemachine
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2.3.7.2
External Layer-1 Statemachine
Instead of using the integrated layer-1 statemachine it is also possible to implement the
layer-1 statemachine completely in software.
The internal layer-1 statemachine can be disabled by setting the L1SW bit in the
TR_CONF0 register to ’1’.
The transmitter is completely under control of the microcontroller via register TR_CMD ).
The status of the receiver is stored in register TR_STA and has to be evaluated by the
microcontroller. This register is updated continuously. If not masked a RIC interrupt is
generated by any change of the register contents. The interrupt is cleared after a read
access to this register.
Data Sheet
87
2001-03-12
PSB 21381/2
PSB 21383/4
Interfaces
2.3.7.2.1 Activation initiated by the Terminal (TE, SCOUT)
INFO 1 has to be transmitted as long as INFO 0 is received.
INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is
received.
After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started.
Data can be transmitted if INFO 4 has been received.
µC Interface
TE
S/T Interface
NT
INFO 0
TDDIS='1', XINF=’010’
INFO 1
INFO 2
RINF=’01’
XINF=’000’
T1TE
INFO 0
RINF=’10’
INFO 3
XINF=’011’
INFO 4
RINF='11'
T2TE
TDDIS='0'
INFO 0
RINF='00'
TDDIS='1', XINF=’000’
T3TE
INFO 0
INFO 0
T1TE: 2 to 6 frames (0.5 ms to 1.5 ms)
T2TE:
2 frames (0.5 ms)
T3TE:
4 frames (1 ms)
act_deac_te-ext_s.vsd
Figure 53
Example of Activation/Deactivation initiated by the Terminal (TE).
Activation/Deactivation completely under Software Control
Data Sheet
88
2001-03-12
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PSB 21383/4
Interfaces
2.3.7.2.2 Activation initiated by the Network Termination NT
INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received.
After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started.
Data can be transmitted if INFO 4 has been received.
µC Interface
TE
S/T Interface
NT
INFO 0
RINF=’01’
INFO 2
T1TE
RINF=’10’
TDDIS='1', XINF=’011’
INFO 3
INFO 4
RINF=’11’
T2TE
TDDIS='0'
INFO 0
RINF=’00’
T3TE
TDDIS='1', XINF=’000’
INFO 0
INFO 0
T1TE: 2 to 6 S/T frames (0.5 ms to 1.5 ms)
2 S/T frames (0.5 ms)
T2TE:
4 S/T frames (1 ms)
T3TE:
act_deac_lt_ext_s.vsd
Figure 54
Example of Activation/Deactivation initiated by the Network Termination (NT).
Activation/Deactivation completely under Software Control
Data Sheet
89
2001-03-12
PSB 21381/2
PSB 21383/4
Interfaces
2.3.8
Level Detection and Power Down
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state.
If CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM interface, are stopped (DD, DU are ’high’, whereas DCL is ’low’ and
BCL is ’high’).
If TR_CONF0.LDD is set to ’0’ an activation initiated from the exchange side will have
the consequence that the clock signals are provided automatically. If TR_CONF0.LDD
is set to ’1’ the microcontroller has to take care of an interrupt caused by the level detect
circuit (ISTATR.LD, see chapter 7.2.8).
From the terminal side an activation must be started by setting and resetting the SPUbit in the IOM_CR register and issuing the command TIM or by resetting MODE1.CFS=0.
2.3.9
Transceiver Enable/Disable
The layer-1 part of the SCOUT can be enabled/disabled by configuration with the two
bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX (see chapter 7.2.3).
By default all layer-1 functions with the exception of the transmit buffers is enabled
(DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface,
another terminal may keep the interface activated although the SCOUT does not
establish a connection. The receiver will monitor for incoming calls in this configuration.
If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including
the level detection circuit of the receiver. In this case the power consumption of the layer1 is reduced to a minimum. All other functional blocks of the SCOUT can still operate via
IOM-2. The DCL and FSC pins become input.
Data Sheet
90
2001-03-12
PSB 21381/2
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Interfaces
2.3.10
Test Functions
The test and diagnostic functions for the S/T interface provided by the SCOUT are
described in the following two chapters.
2.3.10.1
Transceiver Tests
– The internal local loop (internal Loop A) is activated by a C/I0 ARL command or by
setting the bit LP_A (Loop Analog) in the TR_CMD register if the layer-1 statemachine
is disabled.
The transmit data of the transmitter is looped back internally to the receiver. The data
of the IOM-2 upstream B- and D-channels is looped back to the downstream B- and
D-channels.
The S/T interface awake detector is enabled, i.e. if a level is detected this will be
reported by the Resynchronization Indication (RSY) but the loop function is not
effected.
Depending on the DIS_TX bit in the TR_CONF2 register (see chapter 7.2.3) the
internal local loop can be transparent or non transparent to the S/T line.
– The external local loop (external Loop A) is activated in the same way as the internal
local loop described above. Additionally the EXLP bit in the TR_CONF0 register (see
chapter 7.2.1) has to be programmed and the loop has to be closed externally as
described in figure 55.
The S/T interface awake detector is disabled.
This allows complete systems diagnostics including transformers and external
circuits.
SX1
100 Ω
SX2
SCOUT-S(X)
SR1
100 Ω
SR2
Figure 55
External Loop at the S/T-Interface
Data Sheet
91
2001-03-12
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Interfaces
2.3.10.2
Test Signals
Two kinds of test signals may be transmitted by the SCOUT:
– The single pulses are of alternating polarity. One pulse is transmitted in each frame
resulting in a frequency of the fundamental mode of 2 kHz). The corresponding C/I0
command is TM1 (transmission of single pulses.
– The continuous pulses are of alternating polarity. 48 pulses are transmitted in each
frame resulting in a frequency of the fundamental mode of 96 kHz. The corresponding
C/I0 command is TM2 (transmission of continuous pulses).
2.3.11
Transmitter Characteristics
The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter
which is realized as a symmetrical current limited voltage source (VSX1/SX2 = +/-1.05V;
Imax = 26 mA). The equivalent circuit of the transmitter is shown in figure 56.
The nominal pulse amplitude on the S/T-interface of 750 mV (zero-peak) is adjusted with
external resistors ( see chapter 2.3.13.1).
VCM+0.525V
VCM
VCM-0.525V
’+0’
’1’
+
’-0’
SX1
V=1
-
’+0’ ’1’ ’-0’
Level
VCM
TR_CONF2.DIS_TX
-
VCM-0.525V
VCM
VCM+0.525V
’+0’
’1’
SX2
V=1
+
’-0’
trans_stage_s.vsd
Figure 56
Equivalent Internal Circuit of the Transmitter Stage
Data Sheet
92
2001-03-12
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Interfaces
2.3.12
Receiver Characteristics
The receiver consists of a differential input stage, a peak detector and a set of
comparators. Additional noise immunity is achieved by digital oversampling after the
comparators. A simplified equivalent circuit of the receiver is shown in figure 57.
100 kOhm
Figure 57
Equivalent Internal Circuit of the Receiver Stage
The input stage works together with external 10 kΩ resistors to match the input voltage
to the internal thresholds. The data detection threshold Vref is continuously adapted
between a maximal (Vrefmax) and a minimal (Vrefmin) reference level related to the line
level. The peak detector requires maximum 2 µs to reach the peak value while storing
the peak level for at least 250 µs (RC > 1 ms).
The additional level detector for power up/down control works with a fixed threshold
VrefLD. The level detector monitors the line input signals to detect whether an INFO is
present. When closing the internal local loop it is therefore possible to indicate an
incoming signal during activated loop.
In order to additionally reduce the bit error rate in severe conditions, the SCOUT
performs oversampling of the received signal and uses majority decision logic. The
receive signal is sampled at 7.68MHz clock intervals (XTAL).
Data Sheet
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Interfaces
2.3.13
Interface Circuitry
For both, receive and transmit direction a 1:1 transformer is used to connect the SCOUT
transceiver to the 4 wire S/T interface. The connections of the line transformers are
shown in figure 58.
Figure 58
Connection of the Line Transformers and Power Supply to the SCOUT
2.3.13.1
External Protection Circuitry
The ITU-T I.430 specification for both transmitter and receiver impedances in TEs results
in a conflict with respect to external S-protection circuitry requirements:
– To avoid destruction or malfunction of the S-device it is desirable to drain off even
small overvoltages reliably.
– To meet the 96 kHz impedance test specified for transmitters and receivers (for TEs
only, ITU-T I.430 sections 8.5.1.2a and 8.6.1.1) the protection circuit must be
dimensioned such that voltages below 1.2 V (ITU-T I.430 amplitude) x transformer
ratio are not affected.
This requirement results from the fact that this test is also to be performed with no supply
voltage being connected to the TE. Therefore the second reference point for
overvoltages VDD, is tied to GND. Then, if the amplitude of the 96 kHz test signal is
greater than the combined forward voltages of the diodes, a current exceeding the
specified one may pass the protection circuit.
The following recommendations aim at achieving the highest possible device protection
against overvoltages while still fulfilling the 96 kHz impedance tests.
Data Sheet
94
2001-03-12
PSB 21381/2
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Interfaces
2.3.13.1.1 Protection Circuitry for Transmitter
10 Ω
1:1
SX1
GND
VDD
S Bus
10 Ω
SX2
diod_sx_s.vsd
Figure 59
External Circuitry for Transmitter
Figure 59 illustrates the secondary protection circuit recommended for the transmitter.
The external resistors (8 ... 10 Ω) are required in order to adjust the output voltage to the
pulse mask on the one hand and in order to meet the output impedance of minimum 20 Ω
(transmission of a binary zero according to ITU-T I.430) on the other hand.
Two mutually reversed diode paths protect the device against positive or negative
overvoltages on both lines.
An ideal protection circuit should limit the voltage at the SX pins from – 0.4 V to VDD
+ 0.4 V. With the circuit In figure 59 the pin voltage range is increased from – 1.4 V to
VDD + 0.7 V. The resulting forward voltage of 2.1 V will prevent the protection circuit to
become active if the 96 kHz test signal is applied while no supply voltage is present.
2.3.13.1.2 Protection Circuitry for Receiver
Figure 60 illustrates the external circuitry used in combination with a symmetrical
receiver. Protection of symmetrical receivers is rather comfortable.
Data Sheet
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2001-03-12
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Interfaces
1:1
Figure 60
External Circuitry for Symmetrical Receivers
Between each receive line and the transformer a 10 kΩ resistor is used. This value is
split into two resistors: one between transformer and protection diodes for current limiting
during the 96 kHz test, and the second one between input pin and protection diodes to
limit the maximum input current of the chip.
With symmetrical receivers no difficulties regarding LCL measurements are observed;
compensation networks thus are obsolete.
In order to comply to the physical requirements of ITU-T recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the SCOUT may need additional circuitry.
Data Sheet
96
2001-03-12
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HDLC Controller
3
HDLC Controller
The HDLC controller handles layer-2 functions of the D- channel protocol (LAPD) or Bchannel protocols. It can access the D or B-channels or any combination of them e.g. 18
bit IDSL data (2B+D) by setting the enable HDLC channel bits (EN_D, EN_B1H,
EN_B2H) in the HCI_CR register.
It performs the framing functions used in HDLC based communication: flag generation/
recognition, bit stuffing, CRC check and address recognition.
One 64 byte FIFO for the receive and one for the transmit direction are available. They
are implemented as cyclic buffers. The transceiver reads and writes data sequentially
with constant data rate whereas the data transfer between FIFO and microcontroller
uses a block oriented protocol with variable block sizes.
The configuration, control and status bits related to the HDLC controller are all assigned
to the address range 20H-29H. (see chapter 7.1).
3.1
Message Transfer Modes
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a LAPD two-byte address is shown below.
High Address Byte
SAPI1, 2, SAPG
Low Address Byte
C/R 0
TEI 1, 2, TEIG
EA
For the address recognition the HDLC controller contains four programmable registers
for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values for the
“group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which is set to ’1’ for LAPD protocol.
There are 5 different operating modes which can be selected via the mode selection bits
MDS2-0 in the MODEH register:
Data Sheet
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HDLC Controller
3.1.1
Non-Auto Mode (MDS2-0 = ’01x’)
Characteristics:
Full address recognition with one-byte (MDS = ’010’) or
two-byte (MDS = ’011’) address comparison
All frames with valid addresses are accepted and the bytes following the address are
transferred to the µP via RFIFO.
3.1.2
Transparent Mode 0 (MDS2-0 = ’110’).
Characteristics:
no address recognition
Every received frame is stored in RFIFO (first byte after opening flag to CRC field).
3.1.3
Transparent Mode 1 (MDS2-0 = ’111’).
Characteristics:
SAPI recognition
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FEH/FCH). In the case of a match, all following bytes are stored in RFIFO.
3.1.4
Transparent Mode 2 (MDS2-0 = ’101’).
Characteristics:
TEI recognition
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FFH). In case of a match the rest of the frame is stored in the RFIFO.
3.1.5
Extended Transparent Mode (MDS2-0 = ’100’).
Characteristics:
fully transparent
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check, bitstuffing mechanism. This allows user specific protocol variations.
Also refer to chapter 3.5.
3.2
Data Reception
3.2.1
Structure and Control of the Receive FIFO
3.2.1.1
General Description
The 64-byte cyclic RFIFO buffer has variable FIFO block sizes (thresholds) of 4, 8, 16 or
32 bytes which can be selected by setting the corresponding RFBS bits in the EXMR
register. The variable block size allows an optimized HDLC processing concerning frame
length, I/O throughput and interrupt load.
Data Sheet
98
2001-03-12
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HDLC Controller
The transfer protocol between HDLC FIFO and microcontroller is block orientated with
the microcontroller as master. The control of the data transfer between the CPU and the
HDLC controller is handled via interrupts (HDLC controller → Host) and commands
(Host → HDLC controller).
There are three different interrupt indications in the ISTAH register concerned with the
reception of data:
– RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length
(EXMR.RFBS) can be read from RFIFO. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
– RME (Receive Message End) interrupt, indicating that the reception of one message
is completed, i.e. either
• a short message is received
(message length ≤ the defined block size (EXMR.RFBS) or
• the last part of a long message is received
(message length > the defined block size (EXMR.RFBS))
and is stored in the RFIFO.
– RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not
be stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the
host fails to respond quickly enough to RPF/RME interrupts since previous data was
not read by the host.
There are two control commands (bits of CMDR) that are used with the reception of data:
– RMC (Receive Message Complete) command, telling the HDLC controller that a data
block has been read from the RFIFO and the corresponding FIFO space can be
released for new receive data.
– RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the
receive FIFO of any data (e.g. used before start of reception). It has to be used after
having changed the mode.
Data Sheet
99
2001-03-12
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HDLC Controller
The following description of the receive FIFIO operation is illustrated in figure 61 for a
RFIFO block size (threshold) of 16 and 32 bytes.
The RFIFO requests service from the microcontroller by setting a bit in the ISTAH
register, which causes an interrupt (RPF, RME, RFO). The microcontroller then reads
status information (RBCH,RBCL), data from the RFIFO and changes the RFIFO block
size (EXMR.RFBS). A block transfer is completed by the microcontroller via a receive
message complete (CMDR.RMC) command. This causes the space of the transferred
bytes being released for new data and in case the frame was complete (RME) the reset
of the receive byte counter RBC (RBCH,RBCL).
The total length of the frame is contained in the RBCH and RBCL registers (RBC11...0).
If a frame is longer than 4095 bytes, the RBCH.OV (overflow) bit will be set. The least
significant bits of RBCL contain the number of valid bytes in the last data block indicated
by RME (length of last data block ≤ selected block size). Table 10 shows which RBC bits
contain the number of bytes in the last data block or number of complete data blocks
respectively. If the number of bytes in the last data block is ’0’ the length of the last
received block is equal to the block size.
Table 10
Receive Byte Count with RBC11...0 in the RBCH and RBCL registers
EXMR.RFBS
bits
Selected
block size
’00’
Number of
complete
data blocks in
bytes in the last
data block in
32 byte
RBC11...5
RBC4...0
’01’
16 byte
RBC11...4
RBC3...0
’10’
8 byte
RBC11...3
RBC2...0
’11’
4 byte
RBC11...2
RBC1...0
The transfer block size (EXMR.RFBS) is 32 bytes by default. If it is necessary to react to
an incoming frame within the first few bytes the microcontroller can set the RFIFO block
size to a smaller value. Each time a CMDR.RMC or CMDR.RRES command is issued,
the RFIFO access controller sets its block size to the value specified in EXMR.RFBS, so
the microcontroller has to write the new value for RFBS before the RMC command.
When setting an initial value for RFBS before the first HDLC activities, a RRES
command must be issued afterwards.
The RFIFO can hold any number of frames fitting in the 64 bytes. At the end of a frame,
the RSTA byte is always appended.
All generated interrupts are inserted together with all additional information into a wait
line to be individually passed to the host. For example if several data blocks have been
received to be read by the host and the host acknowledges the current block, a new RPF
or RME interrupt from the wait line is immediately generated to indicate new data.
Data Sheet
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PSB 21383/4
HDLC Controller
RAM
RAM
EXMR.RFBS=11
so after the first 4
bytes of a new frame
have been stored in the
fifo an receive pool full
interrupt ISTAH.RPF
is set.
32
RFACC
RFIFO ACCESS
CONTROLLER
16
RFBS=11
RFACC
RFIFO ACCESS
CONTROLLER
16
RFBS=01
8
4
4
HDLC
Receiver
RPF
RFIFO
32
8
RBC=4h
HDLC
Receiver
The µP has read
the 4 bytes, sets
RFBS=01 (16 bytes)
and completes the
block transfer by
an CMDR.RMC command.
Following CMDR.RMC
the 4 bytes of the
last block are
deleted.
EXMR.RFBS=01
RMC
µP
RAM
RAM
HDLC
Receiver
32
RSTA
RSTA
RSTA
16
HDLC
Receiver
RFIFO ACCESS
CONTROLLER
RSTA
16
RFBS=01
CONTROLLER
RFBS=01
8
8
RME
RBC=16h
RMC
RFIFO
RPF
RSTA
RSTA
RBC=14h
FIFO.
RFACC
RFIFO ACCESS
RFIFO
The HDLC
receiver has
written further
data into the FIFO.
When a frame
is complete, a
status byte (RSTA)
is appended.
Meanwhile two
more short frames
have been
received.
32
RFACC
µP
µP
When the RFACC detects 16 valid bytes,
it sets an RPF interrupt. The µP reads the 16 bytes
and acknowledges the transfer by setting CMDR.RMC.
This causes the space occupied by the 16 bytes being
released.
After the RMC acknowledgement the
RFACC detects an RSTA byte, i.e. end of
the frame, therefore it asserts
an RME interupt and increments the
RBC counter by 2.
Figure 61
RFIFO Operation
Data Sheet
101
2001-03-12
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HDLC Controller
3.2.1.2
Possible Error Conditions during Reception of Frames
If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow
(RDO) byte in the RSTA byte will be set. If a complete frame is lost, i.e. if the FIFO is full
when a new frame is received, the receiver will assert a Receive Frame Overflow (RFO)
interrupt.
The microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it
reads the same data again and again. On the other hand, if it doesn’t read or doesn’t
want to read all data, they are deleted anyway after the RMC command.
If the microcontroller reads data without a prior RME or RPF interrupt, the read data is
undefined but the content of the RFIFO would not be corrupted.
Data Sheet
102
2001-03-12
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HDLC Controller
3.2.1.3
Data Reception Procedure
The general procedures for a data reception sequence are outlined in the flow diagram
in figure 62.
START
Receive
Message End
RME
?
Y
N
Receive
Pool Full
RPF
?
N
Y
Read Counter
RD_Count := RFBS
or
RD_Count := RBC
Read RBC
RD_Count := RBC
1)
Read RD_Count
bytes from RFIFO
*
Change Block Size
Write EXMR.RFBS
(optional)
Receive Message
Complete
Write RMC
1)
*
RBC = RBCH + RBCL register
RFBS: Refer to EXMR register
In case of RME the last byte in RFIFO contains
the receive status information RSTA
HDLC_Rflow.vsd
Figure 62
Data Reception Procedures
Data Sheet
103
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
Figure 63 gives an example of an interrupt controlled reception sequence, supposed
that a long frame (68 byte) followed by two short frames (12 byte each) is received. The
FIFO threshold (block size) is set to 32 byte (EXMR.RFBS = ’00’) in this example:
• After 32 bytes of frame 1 have been received an RPF interrupt is generated to indicate
that a data block can be read from the RFIFO.
• The host reads the first data block from RFIFO and acknowledges the reception by
RMC. Meanwhile the second data block is received and stored in RFIFO.
• The second 32 byte block is indicated by RPF which is read and acknowledged by the
host as described before.
• The reception of the remaining 4 bytes plus RSTA are indicated by RME.
• The host gets the number of received bytes (COUNT = 5) from RBCL/RBCH and
reads out the RFIFO. The frame is acknowledged by RMC.
• The second frame is received and indicated by RME interrupt.
• The host gets the number of bytes (COUNT = 13) from RBCL/RBCH and reads out
the RFIFO. The RFIFO is acknowledged by RMC.
• The third frame is transferred in the same way.
IOM Interface
Receive
Frame
68
Bytes
32
32
RD
32 Bytes
12
12
Bytes Bytes
4
12
12
RD
32 Bytes
RD
RD
Count 5 Bytes
RD
RD
Count 13 Bytes
1)
1)
*
RPF
RMC RPF
RMC RME
RD
RD
Count 13 Bytes
1)
*
RMC RME
*
RMC RME
RMC
CPU Interface
1)
*
The last byte contains the receive status information <RSTA>
fifoseq_rec.vsd
Figure 63
Reception Sequence, Example
Data Sheet
104
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
3.2.2
Receive Frame Structure
The management of the received HDLC frames as affected by the different operating
modes (see chapter 3.1) is shown in figure 64.
FLAG
0'6
0'6
0'6
02'(
ADDR
CTRL
$''5(66
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fifoflow_rec.vsd
Figure 64
Receive Data Flow
Data Sheet
105
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
The HDLC controller indicates to the host that a new data block can be read from the
RFIFO by means of an RPF interrupt (see previous chapter). User data is stored in the
RFIFO and information about the received frame is available in the RSTA, RBCL and
RBCH registers which are listed in table 11.
Table 11
Receive Information at RME Interrupt
Information
Location
Bit
Mode
Type of frame
(Command/
Response)
RFIFO
(last byte)
C/R
Non-auto mode,
2-byte address field
Transparent mode 1
Recognition of SAPI
RFIFO
(last byte)
SA1, 0
Non-auto mode,
2-byte address field
Transparent mode 1
Recognition of TEI
RFIFO
(last byte)
TA
All except
transparent mode 0
Result of CRC check
(correct/incorrect)
RFIFO
(last byte)
CRC
All
Valid Frame
RFIFO
(last byte)
VFR
All
Abort condition detected
(yes/no)
RFIFO
(last byte)
RAB
All
Data overflow during reception RFIFO
of a frame (yes/no)
(last byte)
RDO
All
Number of bytes received in
RFIFO
RBCL Reg. RBC4-0
Message length
RBCL Reg. RBC11-0 All
RBCH Reg.
RFIFO Overflow
RBCH Reg. OV
Data Sheet
106
All
All
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
3.3
Data Transmission
3.3.1
Structure and Control of the Transmit FIFO
3.3.1.1
General Description
The 64-byte cyclic XFIFO buffer has variable FIFO block sizes (thresholds) of 16 or 32
bytes, selectable by the XFBS bit in the EXMR register.
There are three different interrupt indications in the ISTAH register concerned with the
transmission of data:
– XPR (Transmit Pool Ready) interrupt, indicating that a data block of up to 16 or 32 byte
(block size selected via EXMR:XFBS) can be written to the XFIFO.
An XPR interrupt is generated either
• after an XRES (Transmitter Reset) command (which is issued for example for frame
abort) or
• when a data block from the XFIFO is transmitted and the corresponding FIFO
space is released to accept further data from the host.
– XDU (Transmit Data Underrun) interrupt, indicating that the transmission of the
current frame has been aborted (seven consecutive ’1’s are transmitted) as the XFIFO
holds no further transmit data. This occurs if the host fails to respond to an XPR
interrupt quickly enough.
– XMR (Transmit Message Repeat) interrupt, indicating that the transmission of the
complete last frame has to be repeated as a collision on the S bus has been detected
and the XFIFO does not hold the first data bytes of the frame (collision after the 16th
or 32nd byte of the frame, respectively).
Note: For proper operation the XMR bit must not be masked
Three different control commands are used for transmission of data:
– XTF (Transmit Transparent Frame) command, telling the HDLC controller that up to
16 or 32 byte (according to selected block size) have been written to the XFIFO and
should be transmitted. A start flag is generated automatically.
– XME (Transmit Message End) command, telling the HDLC controller that the last data
block written to the XFIFO completes the corresponding frame and should be
transmitted. This implies that according to the selected mode a frame end (CRC +
closing flag) is generated and appended to the frame.
– XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the
transmit FIFO of any data.
Optionally two additional status conditions can be read by the host:
– XDOV (Transmit Data Overflow), indicating that the data block size has been
exceeded, i.e. more than 16 or 32 byte were entered and data was overwritten.
Data Sheet
107
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
– XFW (Transmit FIFO Write Enable), indicating that data can be written to the XFIFO.
This status flag may be polled instead of or in addition to XPR.
The XFIFO requests service from the microcontroller by setting a bit in the ISTAH
register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read
the status register STAR (XFW, XDOV), write data in the FIFO and it can change the
transmit FIFO block size (EXMR.XFBS) if required.
The instant of the initiation of a transmit pool ready (XPR) interrupt after different transmit
control commands is listed in table 12.
Table 12
XPR Interrupt (availability of the XFIFO) after XTF, XME Commands
CMDR.
Transmit pool ready (XPR) interrupt initiated...
XTF
as soon as the selected buffer size in the FIFO is available
XTF &
XME
after the successful transmission of the closing flag. The transmitter
sends always an abort sequence
XME
as soon as the selected buffer size in the FIFO is available, two
consecutive frames share flags
When setting XME the transmitter appends the FCS and the end flag at the end of the
frame. When XTF & XME has been set, the XFIFO is locked until successful
transmission of the current frame, so a consecutive XPR interrupt also indicates
successful transmission of the frame whereas after XME or XTF the XPR interrupt is
asserted as soon as there is space for one data block in the XFIFO.
The transfer block size is 32 bytes by default, but sometimes, if the microcontroller has
a high computational load, it is useful to increase the maximum reaction time for an XPR
interrupt. The maximum reaction time is:
tmax = (XFIFO size - XFBS) / data transmission rate
A selected block size of 16 bytes means that an XPR interrupt is indicated when there
are still 48 bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes block size the
XPR is initiated when there are still 32 bytes (64 bytes - 32 bytes), i.e. the maximum
reaction time for the smaller block size is 50 % higher with the trade off of a doubled
interrupt load. A selected block size of 32 or 16 bytes respectively always indicates the
available space in the XFIFO. So any number of bytes smaller than the selected XFBS
may be stored in the FIFO during one “write block“ access cycle.
Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next
XTF,XME or XRES command. XRES resets the XFIFO.
The XFIFO can hold any number of frames fitting in the 64 bytes.
Data Sheet
108
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
3.3.1.2
Possible Error Conditions during Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly
enough to an XPR interrupt, an XDU (transmit data underrun) interrupt will be raised. If
the HDLC channel becomes unavailable during transmission the transmitter tries to
repeat the current frame as specified in the LAPD protocol. This is impossible after the
first data block has been sent (16 or 32 bytes), in this case an XMR transmit message
repeat interrupt is set and the microcontroller has to send the whole frame again.
Both XMR and XDU interrupts cause a reset of the XFIFO. The XFIFO is locked while
an XMR or XDU interrupt is pending, i.e. all write actions of the microcontroller will be
ignored as long as the microcontroller has not read the ISTAH register with the set XDU,
XMR interrupts.
If the microcontroller writes more data than allowed (16 or 32 bytes) , then the data in the
XFIFO will be corrupted and the STAR.XDOV bit is set. If this happens, the
microcontroller has to abort the transmission by CMDR.XRES and to restart.
Data Sheet
109
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
3.3.1.3
Data Transmission Procedure
The general procedures for a data transmission sequence are outlined in the flow
diagram in figure 65.
START
N
Transmit
Pool Ready
XPR
?
Y
Write Data
(up to 32 Bytes)
to XFIFO
Command
XTF
N
End of
Message
?
Y
Command
XTF+XME
End
HDLC_Tflow.vsd
Figure 65
Data Transmission Procedure
Data Sheet
110
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
The following description gives an example for the transmission of a 76 byte frame with
a selected block size of 32 byte (EXMR:XFBS=0):
• The host writes 32 bytes to the XFIFO, issues an XTF command and waits for an XPR
interrupt in order to continue with entering data.
• The HDLC controller immediately issues an XPR interrupt (as remaining XFIFO space
is not used) and starts transmission.
• Due to the XPR interrupt the host writes the next 32 bytes to the XFIFO, followed by
the XTF command, and waits for XPR.
• As soon as the last byte of the first block is transmitted, the HDLC controller issues an
XPR interrupt (XFIFO space of first data block is free again) and continues
transmitting the second block.
• The host writes the remaining 12 bytes of the frame to the XFIFO and issues the XTF
command together with XME to indicate that this is the end of frame.
• After the last byte of the frame has been transmitted the HDLC controller releases an
XPR interrupt and the host may proceed with transmission of a new frame.
IOM Interface
76 Bytes
Transmit
Frame
32
WR
32 Bytes
32
WR
12 Bytes
WR
32 Bytes
XTF XPR
12
XTF
XTF+XME
XPR
XPR
CPU Interface
fifoseq_tran.vsd
Figure 66
Transmission Sequence, Example
Data Sheet
111
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
3.3.2
Transmit Frame Structure
The transmission of transparent frames (XTF command) is shown in figure 67.
For transparent frames, the whole frame including address and control field must be
written to the XFIFO. The host configures whether the CRC is generated and appended
to the frame (default) or not (selected in EXMR.XCRC).
Furthermore, the host selects the interframe time fill signal which is transmitted between
HDLC frames (EXMR:ITF). One option is to send continuous flags (’01111110’),
however if D-channel access handling is required, the signal must be set to idle
(continuous ’1’s are transmitted).
FLAG
ADDR
CTRL
$''5(66
&21752/
I
'$7$
CRC
FLAG
&+(&.5$0
7UDQVPLW7UDQVSDUHQW)UDPH
;),)2
;7)
7KH&5&LVJHQHUDWHGE\GHIDXOW
fifoflow_tran.vsd
,I(;05;&5&LVVHWQR&5&LVDSSHQGHG
Figure 67
Transmit Data Flow
3.4
Access to IOM Channels
By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register
the HDLC controller can access the D, B1, B2 channels or the combination of them (e.g.
18 bit IDSL data (2B+D)). In all modes sending works always frame aligned, i.e. it starts
with the first selected channel whereas reception looks for a flag anywhere in the serial
data stream.
Data Sheet
112
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
3.5
Extended Transparent Mode
This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent
mode fully transparent data transmission/reception without HDLC framing is performed
i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism.
This allows user specific protocol variations.
3.5.1
Transmitter
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOM-frame aligned and byte aligned, i.e. transmission starts in the first selected
channel (B1, B2, D, according to the setting of register HCI_CR in the IOM Handler) of
the next IOM frame.
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with an XPR interrupt
after sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the collision detection is enabled (MODE.DIM = ’0x1’) the stop go bit (S/G) can be used
as clear to send indication as in any other mode. If the S/G bit is set to ’1’ (stop) during
transmission the transmitter responds always with an XMR (transmit message repeat)
interrupt.
If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs
out of data then it will assert an XDU (transmit data underrun) interrupt.
3.5.2
Receiver
The reception is IOM-frame aligned and byte aligned, like transmission, i.e. reception
starts in the first selected channel (B1, B2, D, according to the setting of register HCI_CR
in the IOM Handler) of the next IOM frame. The FIFO indications and commands are the
same as in others modes.
All incoming data bytes are stored in the RFIFO and additionally made available in
RSTA.
Data Sheet
113
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
3.6
HDLC Controller Interrupts
The cause of an interrupt related to the HDLC controller is indicated by the HDLC bit in
the ISTA register. This bit points at the different interrupt sources of the HDLC controller
part in the ISTAH register. The individual interrupt sources of the HDLC controller during
reception and transmission of data are explained in chapter 3.2.1 or 3.3.1 respectively.
MASK
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
ISTA
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
MASKH
ISTAH
RME
RME
RPF
RFO
XPR
RPF
RFO
XPR
XMR
XDU
XMR
XDU
INT
Figure 68
Interrupt Status Registers of the HDLC Controller
Each interrupt source in ISTAH register can be selectively masked by setting to “1” the
corresponding bit in MASKH.
Data Sheet
114
2001-03-12
PSB 21381/2
PSB 21383/4
HDLC Controller
3.7
Test Functions
The following test and diagnostic functions for the D-channel are available:
– Digital loop via TLP (Test Loop, TMH register) command bit (figure 69): The TX path
of layer 2 is internally connected with the RX path of layer 2. The output from layer 1
on DD is ignored. This is used for testing layer 2 functionality excluding layer 1 (loop
back between XFIFO and RFIFO).
– Test of layer-2 functions while disabling all layer-1 functions and pins associated with
them (including clocking) via bit TR_CONF0.DIS_TR. The HDLC controller and codec
part can still operate via IOM-2. DCL and FSC pins become input.
Figure 69
Layer 2 Test Loops
Data Sheet
115
2001-03-12
PSB 21381/2
PSB 21383/4
Codec
4
Codec
The codec bridges the gap between the audio world of microphones, earphones,
loudspeakers and the PCM digital world by providing a full PCM codec with all the
necessary transmit and receive filters.
Because the requirements for the codec correspond to the ARCOFI-SP PSB 2163 or
ARCOFI®-BA PSB 2161 respectively the architecture, functionality and transmission
characteristics are similar to those devices.
A block diagram of the codec is shown in figure 70.
The codec can be subdivided into three main blocks:
• Analog Front End (AFE)
• Digital Signal Processor (DSP)
• Codec Digital Interface (CDI)
A detailed description can be found in the following chapters.
VREF
Frequency
Correction
Filter
AXI
MIP1
MIN1
AINMUX
AMI
A/D
Dec
Dec
MIP2
MIN2
LSP
LSN
Digital Gain
Adjustment
Speakerphone
Function
ALS
D/A
HOP
HON
AHO
Int
Tone Generator
Int
Sidetone
CDI
CH1X C010X
C011X
CH2X C020X
C021X
CH2R C020R
C021R
Codec Voice Data
VREF
BGREF
DSP
Data Source Selection, Voice Data Manipulation
(Coding, Masking, Conferencing)
AFE
IOM-2 Handler
CH1R C010R
C011R
Control/
config.
Data
µC Interface or
Monitor Handler
codec_arch.vsd
Figure 70
Architecture of the codec
Data Sheet
116
2001-03-12
PSB 21381/2
PSB 21383/4
Codec
The controlling and programming of the various operation modes, configurations and
coefficients can be done via the microcontroller interface or the IOM-2 monitor channel
and is described in the corresponding interface section. An overview on these
programmable parameters can be found in chapter 4.8.
4.1
Analog Front End (AFE) Description
The Analog Front End section of the codec is the interface between the analog
transducers and the digital signal processor. In the transmit direction the AFE function is
to amplify the transducer input signals (microphones) and to convert them into digital
signals. In the AFE receive section the incoming digital signal is converted to an analog
signal which is output to an earpiece and/or a loudspeaker.
The three AFE configuration registers (ACR, ATCR, ARCR) provide a high flexibility to
accommodate an extensive set of user procedures and terminal attributes.
Figure 71 shows the block diagram of the Analog Front End:
.
DREF
Figure 71
Block Diagram of AFE
Data Sheet
117
2001-03-12
PSB 21381/2
PSB 21383/4
Codec
Two differential inputs (MIP1/MIN1 and MIP2/MIN2) and one single-ended input (AXI)
can be connected to the amplifier AMI via an analog input multiplexer (ATCR.AIMX). The
programmable amplifier AMI (ATCR.MIC) provides a coarse gain adjustment range from
0...42dB in 6dB steps. The maximum value of the programmable gain adjustment of the
microphone amplifier with specified transmission characteristics is 36dB for the
differential input. The maximum gain value with specified transmission characteristics of
the single ended input AXI is 24dB. Fine gain adjustment is performed in the digital
domain via the programmable gain adjustment stage GX (see signal processor section).
This allows a perfect level adaptation to various types of microphone transducers without
loss in the signal to noise performance.
The fully differential output HOP/HON connects the amplifier AHO to a handset earpiece.
Differential output LSP/LSN is provided for use with a 50Ω (5V supply voltage) or 25Ω
(3.3V supply voltage) respectively loudspeaker. The programmable amplifiers AHO and
ALS (ARCR.HOC, ARCR.LSC) provide a coarse gain adjustment range from 11.5dB...21.5dB (ALS) or 2.5dB...-21.5dB (AHO) respectively. The step size is for both amplifiers
3dB. Fine gain adjustment is performed in the digital domain via the programmable
adjustment stage GR.
Each output of the differential amplifiers AHO and ALS can be powered down separately
(ACR.DHOP, DHON, DLSP, DLSN). By setting ACR.SEM, a powered down
loudspeaker output can be grounded internally for a single ended operation.
The bandgap reference voltage is low-pass filtered via a capacity connected to pin
BGREF. The internal and external reference voltages are derived from this filtered
bandgap reference voltage providing a good noise performance.
A square wave signal from the tone generator can be output directly to the loudspeaker
amplifier (TGSR.TRL) via a level shifter.
Note: The single-ended input (AXI) is internally connected to VREF. To avoid an
unsymmetric input signal to the internal amplifer module, external resitors must
not be connected between AXI and GND or AXI and VREF.
4.1.1
AFE Attenuation Plan
Figure 72 shows the attenuation plan of the AFE for the transmit and receive direction.
The levels are given for the digital reference level (0dBm0) and the max. PCM level in
A-law coding (3.14dBm0) at the two supply voltages 3.3V and 5V.
The stated microphone amplifier gain is the maximum gain for guaranteed transmission
characteristics.
In the receive path the stated loudspeaker or handset output amplification is the
maximum selectable gain at the maximum digital PCM level (3.14dBm0) for guaranteed
transmission characteristics.
Data Sheet
118
2001-03-12
PSB 21381/2
PSB 21383/4
Codec
.
Figure 72
AFE Attenuation Plan
Data Sheet
119
2001-03-12
PSB 21381/2
PSB 21383/4
Codec
4.2
Signal Processor (DSP) Description
The signal processor (DSP) has been conceived to perform all ITU-T and ETSI (NET33)
recommended filtering in transmit and receive paths and is therefore fully compatible to
the ITU-T G.712 and ETSI (NET33) specifications. The data processed by the DSP is
provided in the transmit direction by an oversampling A/D-converter situated in the
analog front end (AFE). Once processed, the speech signal is converted into an 8-bit Alaw or µ-law PCM format or remains as a 16-bit linear word (2s complement) if the
compression stage is bypassed. In the receive direction, the incoming PCM data is
expanded into a linear format (if the linear mode is selected, the expansion logic is
bypassed) and subsequently processed until it is passed to the oversampling D/Aconverter.
Additionally to these standard codec functions an universal tone generation unit and a
high quality speakerphone function (only SCOUT-SX) is provided. Figure 73 shows the
processor signal flow graph which illustrates the following description of the signal
processing in receive and transmit direction, the tone generation and speakerphone
function.
Data Sheet
120
2001-03-12
AF E
121
E RA
1
square
T RR
INT
R eceive
1
T RX
DE C
to ALS ampl.
1
DLS
T rans mit
LP
LP
sine
trapezoid
square
DT MF
LP
0...-6 dB
GHR
<T GS R >
GX
GX
6...0 dB
DT MF -
<T GCR >
GR
GR
T one Generator
DT MF
1
DT MF
FX
FX
SC
FR
FR
1
DHPX
MAAR
SC
AGCR
AGCR
PGCR
SD
S upport
SC
HPX
S peakerphone
S C,S D
1
DT MF
1
DHPX
GZ
1
1
DHPR
GHX
HPR
0...- ∞ dB
GZ
DHPR
PGZ
1
AGCX
AGCX
SCOUT-SX only
us er programmable
0
S PS T
Speakerphone support
SP
RDAT
XDAT
DS S R
idle
MAS K2
MAS K1
16-bit LIN
8-bit LIN
µ-Law
A-Law
16-bit LIN
MAS K1
8-bit LIN MAS K2
µ -Law
A-Law
Manipulation
Voice Data
16-bit LIN
8-bit LIN
µ -Law
A-Law
16-bit LIN
8-bit LIN
µ-Law
A-Law
1
E NX2
1
E NX1
MPx
DS S 2X
AT T 2R AT T 1R
idle
idle
MAS Kx
DF xR
DF xX
DS S 1X
1
CH2X
CH1X
CH1R
CH2R
D L P 2
Data Sheet
D L P 1
CME
1
CH10X
CH11R
CH10R
CH21R
CH20R
CH21X
CH20X
CH11X
PSB 21381/2
PSB 21383/4
Codec
Figure 73
Processor Signal Flow Graph
2001-03-12
to I O M - H a n d le r
C o d e c V o ic e D a ta
PSB 21381/2
PSB 21383/4
Codec
4.2.1
Transmit Signal Processing
In the transmit direction a series of decimation filters reduces the sampling rate down to
the 8-kHz PCM-rate. These filters attenuate the out-of-band noise by limiting the transmit
signal to the voice band. The decimation stages end with a low-pass filter (LP).
If the tone generation unit is connected to the transmit direction (TGSR.DTMF = ’1’), a
special 2-kHz DTMF low-pass filter is placed in the transmit path. This filter guarantees
an attenuation of all unwanted frequency components, if DTMF signals are transmitted.
Additionally, it is possible to add a programmable tone signal to the transmit voice signal
(TGSR.TRX = ’1’).
The GX-gain adjustment stage is digitally programmable allowing the gain to be
programmed from + 6 to 0 dB in steps of ≤ 0.25 dB (values from – ∞ dB to 12 dB are
programmable but the transmission characteristics are only guaranteed in a specific
range, see table 13 and 14). Two bytes are necessary to set GX to the desired value.
After reset, the GX-gain stage is bypassed.
The transmit path contains a programmable high performance frequency response
correction filter FX allowing an optimum adaptation to different types of microphones
(dynamic, piezoelectric or electret). Twelve bytes are necessary to set FX to the desired
frequency correction function. After reset, the FX-frequency correction filter is bypassed.
Figure 74 shows the architecture of the FX/FR-filter.
A high-pass filter (HPX) is also provided to remove unwanted DC components.
In the voice data manipulation block a data format selection (A-law, µ-law, 8-bit linear,
16 bit linear), the masking of the 8-bit data and the data source selection for the two data
channels at the interface to the IOM handler is realized.
4.2.2
Receive Signal Processing
The incoming data from the IOM handler is similar to transmit direction processed by the
VDM block. A programmable sidetone gain stage GZ adds a sidetone signal to the
incoming voice signal. The sidetone gain can be programmed from – 54 to 0 dB within a
± 1 dB tolerance range (values from – ∞ dB to 12 dB are programmable but the
transmission characteristics are only guaranteed in a specific range, see table 13 and
14). Respectively two bytes are coded in the CRAM to set GZ to the desired value. After
reset, the GZ-gain stage is disabled (– ∞ dB).
A high-pass filter (HPR) is also provided to remove disturbances from 0 to 50/60 Hz due
to the telecommunication network.
The frequency response correction filter (FR) is similar to the FX-filter allowing an
optimum adaptation to different types of loudspeakers or earpieces. Twelve bytes are
necessary to set FR to the desired frequency correction function. After reset, the
FR-frequency correction filter is bypassed.
Data Sheet
122
2001-03-12
PSB 21381/2
PSB 21383/4
Codec
The GR-gain adjustment stage is digitally programmable from – 6 to 0 dB in steps
≤ 0.25 dB (– ∞ dB and others are also possible). Respectively two bytes are coded in the
CRAM to set GR to the desired value. After reset, the GR-gain stage is bypassed.
A low-pass filter limits the signal bandwidth in the receive direction according to ITU-T
and ETSI (NET33) recommendations.
A series of low-pass interpolation filters increases the sampling frequency up to the
desired value. The last interpolator feeds the D/A-converter.
Equalizer 1
Equalizer 2
High- / Low- Pass
ITD02288
Figure 74
Architecture of the FX- and FR-Correction Filter
Data Sheet
123
2001-03-12
PSB 21381/2
PSB 21383/4
Codec
4.2.3
Programmable Coefficients for Transmit and Receive
This section gives a short overview of important programmable coefficients. For more
detailed information a coefficient software package is available (SCOUT MASTER
SIPO 21383).
Table 13 Description of the programmable Level Adjustment Parameters
Parameter
# of CRAM
Bytes
Range
Comment
GX
2
12 to – ∞ dB Transmit gain adjustment
6 to 0 dB
Transmission characteristics guaranteed
GR
2
12 to – ∞ dB Receive gain adjustment
0 to -6 dB
Transmission characteristics guaranteed
GZ
2
12 to – ∞ dB Sidetone gain adjustment
Table 14 Subset of Coefficients for GX, GR and GZ:
Gain [dB]
MSB
LSB
Gain [dB]
MSB
LSB
Gain [dB]
MSB
LSB
12.0
10H
01H
0
A0H
01H
-12.0
A9H
01H
11.0
10H
31H
-0.5
B3H
42H
-13.0
9CH
51H
10.0
10H
13H
-1.0
A3H
2BH
-14.0
99H
13H
9.0
01H
4BH
-1.5
A2H
32H
-15.0
8CH
1BH
8.0
20H
94H
-2.0
BBH
4AH
-16.0
82H
7BH
7.0
30H
94H
-2.5
BBH
13H
-17.0
84H
4BH
6.0
13H
51H
-3.0
BAH
29H
-18.0
89H
6AH
5.5
B0H
39H
-3.5
BAH
5BH
-19.0
8BH
0CH
5.0
A0H
49H
-4.0
A2H
01H
-20.0
84H
1CH
4.5
23H
01H
-4.5
AAH
1BH
-21.0
8CH
1CH
4.0
22H
B4H
-5.0
9BH
3AH
-22.0
82H
7CH
3.5
23H
12H
-5.5
AAH
33H
-23.0
84H
4CH
3.0
32H
A4H
-6.0
AAH
22H
-24.0
89H
6BH
2.5
B1H
BCH
-7.0
B9H
2CH
-25.0
8BH
0DH
2.0
B1H
03H
-8.0
9AH
BCH
-26.0
84H
1DH
1.5
33H
39H
-9.0
9BH
13H
–∞
88H
01H
1.0
B2H
5AH
-10.0
9BH
32H
0.5
B3H
49H
-11.0
93H
02H
Data Sheet
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4.3
Tone Generation
The ASP contains a universal tone generator which can be used for tone alerting, call
progress tones, DTMF-signals or other audible feedback tones.
All the tone generation configurations are programmable in the registers TGCR (Tone
Generator Configuration Register) and TGSR (Tone Generator Switch Register) and the
CRAM parameters.
The tone generation unit consists of following main blocks:
• Four Signal Generators
• Sequence Generator
• Control Generator
• Tone Filter
• Tone Level Adjustment
Figure Chapter 75 shows the signal flow graph of the tone generation unit and
illustrates the following functional description.
4.3.1
Four Signal Generators
The four signal generators can be programmed by CRAM parameters in frequency
(Fn,FD) and gain (Gn,GDn). For the signal generators F1,F2,F3 a trapezoid or square
waveform can be selected by setting the TGCR.SQTR bit. The signal generator FD has
a trapezoid waveform.
The signal generators in conjunction with the tone sequence generator and the control
generator allow to generate different multitone patterns without reprogramming the
necessary parameters.
4.3.2
Sequence Generator
The sequence generator can be enabled or disabled by setting the TGCR.SEQ
(Sequence Generator) bit. If the sequence generator is enabled depending on the
TGCR.TM (Tone Mode) bit two or three tone sequences of the signals (F1, G1), (F2,G2)
and (F3,G3) are generated. The CRAM parameters T1, T2, T3 determine the duration of
these individual signals.
If the sequence generator is disabled a continuos tone is generated. The selected signal
generator depends on the TGCR.TM (Tone Mode) bit.
By setting the TGSR.DT (Dual Tone Mode) bit the output of the signal generator FD (FD,
GDn) can be added to the tone signal which is determined by the SEQ and TM bit.
Note: The dual tone mode and the three tone sequence can only be used if the DTMF
mode is disabled (TGSR.DTMF = ’0’)
Table 15 shows the programmable CRAM Parameters of the tone and sequence
generator.
In Table 16 possible tone signals are listed which can be realized with the control bits
SEQ, TM and DT.
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Data Sheet
S QT R
trapezoid
s quare/
trapezoid
s quare/
126
trapezoid
trapezoid
F D,
GD1
GD2
GD3
S ignal Generator
F 3, G3
s quare/
S ignal Generator
DT MF
F 2, G2
S ignal Generator
F 1, G1
S ignal Generator
T one Generator
S equence
Generator
T one
S EQ
T3
T2
T1
T 1, T 2, T 3
SM
1
1
1
R es
et
DT MF
TM
DT
ET
1
T ON, T OF F
T one
Generator
Control
PT
ET
F
T one
1
S aturatio
n
T one F ilter ( A1, A2, K, GE )
E qualiz
er
1 ET
F
GT R
GT X
DT MF
T rans mit
s witch
to T R R
s witch
to T R X
T ONGE N.VS D
Adjus t.
T one L evel
via T R L s witch
to ALS ampl.
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Figure 75
Signal Flow Graph of the Tone Generation Unit
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Table 15 CRAM Parameters of the Signal and Sequence Generator
Parameter
# of CRAM
Bytes
Range
Comment
Fn
2/2/2
50 Hz to 4 kHz
Trapezoid shaped tone
16 kHz/m; (m ≥ 3)
Square-wave signal
Gn
1/1/1
0 dB to – 48 dB
Gain adjustment for
square/trapezoid generator
Tn
2/2/2
10 ms to 8 s
Period of time for two- or threetone sequences
FD
2
50 Hz to 4 kHz
Trapezoid shaped tone
GDn
1/1/1
0 dB to – 48 dB
Gain adjustment for
trapezoid generator
n is either 1, 2 or 3
Note: 0-dB gain setting of G1, G2 or G3 and GD1, GD2 or GD3 corresponds to the
maximum PCM-level (A-Law: + 3.14 dBm0)
Table 16 Tone Generation
SEQ TM DT
Generated tone
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Continuous signal
Continuous signal
Continuous signal
Continuous signal
tone sequence
tone sequence
1
1
1
1
0
1
tone sequence
tone sequence
Data Sheet
[F1, G1]
[F1, G1] + [FD, GD1]
[F2, G2]
[F2, G2] + [FD, GD2]
[F1, G1, T1] / [F2, G2, T2]
[(F1, G1) + (FD, GD1), T1)] /
[(F2, G2) + (FD, GD2), T2)]
(F1, G1, T1) / (F2, G2, T2) / (F3, G3, T3)
[(F1, G1) + (FD, GD1), T1] /
[(F2, G2) + (FD, GD2), T2] /
[(F3, G3) + (FD, GD3), T3]
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4.3.3
Control Generator
Controlling of the generated tone follows the setting of the control bits ET (Enable Tone)
and PT (Pulsed Tone) and the CRAM parameters TON and TOFF corresponding table
17 and table 18.
Table 17 Control Generator
ET
PT
Generator Output
0
0
0
1
1
1
0
1
No tone
the tone is pulsed with the programmable parameters TON,
TOFF
continuous tone generation without breaks
the tone is pulsed with the programmable parameters TON,
TOFF
Table 18 CRAM Parameters of the Control Generator
Parameter
# of CRAM
Bytes
Range
Comment
TON
2
20 ms to 16 min
TOFF
2
20 ms to 16 min
Period while the tone generator
is turned on
Period while the tone generator
is turned off
Four typical examples for the control generator programming are shown in Figure 76.
In the automatic stop mode (TGCR.SM = ’1’) the selected tone sequence is only stopped
after a sequence is completed. This avoids unpleasant sounds when stopping the tone
generator.
The tone signal can be fed directly to the input of the loudspeaker amplifier by setting the
TGSR.TRL bit to ’1’. In this mode only a square wave (fixed amplitude of VDD) is
available from the signal generators (F1, F2, F3)and the TGCR.SQTR bit has no effect.
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Figure 76
Typical Control Generator Applications
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4.3.4
Tone Filter
A programmable tone filter can be switched in the tone signal path by setting the ETF
(Enable Tone Filter) bit. The tone filter contains a programmable equalizer and a
saturation amplifier (see figure Chapter 75).
A generated square-wave or trapezoid signal can be converted by the equalizer into a
sine-wave signal. The equalizer is realized as a band-pass filter. The filter parameters
(center frequency, bandwidth and attenuation of the stop-band) are programmable by
the CRAM parameters listed in Table Chapter 19
Table 19 CRAM Parameters of the Tone Filter
Parameter
# of CRAM
Bytes
Range
Comment
A1
A2
1
1
200 Hz to 4 kHz
0 to – 1
K
GE
1
1
0 to 54 dB
+ 12 to – 12 dB
Center frequency
Determines with A1 and K the
bandwidth. The closer A2 comes
to -1, the smaller the bandwidth.
Attenuation of the stop-band
Saturation amplification
A maximum attenuation of the first harmonic frequency of 50 dB is possible. Figure
Chapter 77 shall illustrate the equalizer parameters.
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Figure 77
Filter Parameters of the Equalizer
The two main purposes of the programmable saturation amplification are:
• Level balancing of the filtered signal (avoidance of overload effects).
• Amplification up to + 12 dB followed by a saturation (3.14 dBm0) of the incoming
signal. This saturation amplification converts a sine-wave signal into a square-wave
or a trapezoid signal where their edges are eliminated. This method produces
pleasant ringing tones.
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4.3.5
Tone Level Adjustment
The generated tone signal can be amplified separate for transmit and receive direction
with the gain parameters GTX, GTR and switched to the transmit/receive channels by
setting TGSR.TRX (Tone Ringing Transmit) and TRR (Tone Ringing Receive).
Table 20 CRAM Parameters of the Tone Level Adjustment
Parameter
# of CRAM
Bytes
Range
Comment
GTX
1
0 dB to – 50 dB
(also – ∞ dB)
Level adjustment in transmit direction
GTR
1
0 dB to – 50 dB
(also – ∞ dB)
Level adjustment in receive direction
4.3.6
DTMF Mode
The DTMF mode of the tone generator is selected by setting the TGSR.DTMF to ’1’. The
trapezoid output signal of the signal generators (F3, G3) and (FD, GD3) are added and
fed in the transmit path. The CRAM parameters for the DTMF signals are listed in table
21
In the DTMF mode a special DTMF filter is switched to the transmit channel. Undesirable
frequency components are filtered by this special DTMF-low-pass filter to the following
limits:
Frequency Band
Min. Attenuation
0 – 300 Hz
300 – 3400 Hz
3400 – 4000 Hz
33 dB
20 dB
33 dB
The pre-emphasis of 2 dB between the high and the low DTMF-frequency groups has to
be set with the independent gain parameters (G3 and GD3 resp.) of the trapezoid
generators . All generated DTMF-frequencies are guaranteed within a ± 1 % deviation.
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Table 21 DTMF-frequency (F3,FD) Programming
ITU-T Q.23
[Hz]
Low Group
697
770
852
941
High Group
1209
1336
1477
1633
SCOUT
Relative Deviation
Coefficients
Nominal [Hz]
from ITU-T
high [HEX]
low [HEX]
697.1
770.3
852.2
941.4
+ 143 ppm
+ 390 ppm
+ 235 ppm
+ 425 ppm
4F
A6
45
20
16
18
1B
1E
1209.5
1336.9
1477.7
1632.8
+ 414 ppm
+ 674 ppm
+ 474 ppm
– 122 ppm
B4
C8
49
40
26
2A
2F
34
Note: The deviations due to the inaccuracy of the incoming clock DCL/MCLK, when
added to the nominal deviations tabulated above give the total absolute deviation
from the CCITT-recommended frequencies
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4.4
Speakerphone Support
The speakerphone option of the SCOUT-SX performs all functions required for echo
suppression without any external components, just by software. All these operational
functions realized by the signal processor are completely parameterized. This technique
offers a high level of flexibility and reproducibility.
Basically, three static mode of operation can be distinguished: “transmit mode”, “receive
mode”, and “idle mode”. In the speech mode the receive path is attenuated while in listen
mode the attenuation is switched to the transmit path. In the idle mode the attenuation is
halved between transmit and receive paths. The amount of switchable attenuation can
be chosen by software. The speakerphone goes into transmit mode if both, the speech
detector and the speech comparator SCAE, indicate the presence of a speech signal in
the transmit direction that is strong enough. Switching into receive mode appears if the
speech comparator SCLE and the speech detector in the receive path both detect a
speech signal that is strong enough. If no speech is detected at all, the speakerphone
goes into idle mode.
As the signal flow graph of the speakerphone option shows (see figure Chapter 78), the
complete operational algorithm is situated between the analog front end/signal
processing and the compression/expansion logic. Thus telephone sets can be optimized
and adjusted to the particular physical and acoustic environment.
The main features of the speakerphone signal processing are:
• Two separate attenuation stages activated by voice, one for the transmit and one for
the receive path. They are controlled by the current and past speech activities.
• Immediate mode switching mainly controlled by two comparators, one at the acoustic
side and one at the line side. Capable of handling very long echo times.
• All parameters can be adjusted independently and are closely related to the physical
phenomenons.
• Speech detection by special speech detectors in the respective transmit and receive
directions. Different time constants are separately programmable for signal and noise.
• Background noise monitoring to eliminate continuous background noise from speech
control. All time constants are user programmable.
Data Sheet
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Signal-Processing
&
Analog Front End
COMP
GHX
AGCX
SX´
SX
PCM
SD
Attenuation
SCAE
SCLE
Control
SD
Signal-Processing
&
Analog Front End
SR´
SR
GR
GHR
AGCR
EXP
PCM
Figure 78
Speakerphone Signal Flow Graph of the SCOUT-SX
4.4.1
Attenuation Control Unit
The Attenuation Control unit controls the attenuation stages GHX of the transmit and
GHR of the receive directions respectively. The programmable loss is switched either
completely to a single path or, in the “IDLE” mode, is halved to each direction.
In addition, attenuation is also influenced by the Automatic Gain Control stages (AGCX
and AGCR). In order to keep the total loop gain always constant, the sweep range (of
ATT) is automatically enlarged with high-gain amplification of the AGCs while it will be
accordingly reduced with low-gain.
Changing from one speakerphone mode into another one depends on the
determinations of one comparator plus the corresponding speech detector. Hence
attenuation is influenced by the current and past speech activities. Also rate of change
varies: changing from “transmit mode” or “receive mode” to “idle mode” is programmable
by the rate factor DS. Direct changes from “transmit mode” to “receive mode” or viceversa and changes from “idle mode” to “transmit mode” or “receive mode” can be
programmed via the factor SW in a large range.
Data Sheet
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Description of the programmable parameters:
Parameter
# of CRAM
Bytes
Range
TW
ATT
1
1
16 ms to 4 s
0 dB to 95 dB
DS
1
SW
1
4.4.2
Comment
Wait time
Attenuation programmed in GHR or
GHX if speech activity for the other
side was detected
0.6 to 680 ms/dB
Decay Speed
(Decay Time TD = DS × ATT/2)
0.0052 to 10 ms/dB Switching time (dependent on ATT)
Speakerphone Test Function and Self Adaption
For optimizing the speakerphone performance the SCOUT-SX provides following test
functions:
- The two register bits (XCSR.SPST) indicate the different speakerphone states (receive,
transmit and idle).
- The momentary magnitude of the AGC attenuation in receive direction can be read out
by an SOP_D command.
4.4.3
Speech Detector
The speech detectors (see figure Chapter 79) contained in both transmit and receive
directions consist of two main blocks:
• Background Noise Monitor (BNM)
• Signal Processing
Although the speech detector is fully parameterized, the standard coefficient set for the
speech detector fits perfectly to almost every application and normally don’t have to be
altered.
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Figure 79
Speech Detector Signal Flow Graph
4.4.3.1
Background Noise Monitor
The tasks of the noise monitor are to differentiate voice signals from background noise,
even if it exceeds the voice level, and to recognize voice signals without any delay.
Therefore the background noise monitor consists of the low-pass filter 2 (LP2) and the
offset in two separate branches. Basically it works on the burst-characteristic of the
speech: voice signals consist of short peaks with high power (bursts). In contrast,
background noise can be regarded approximately stationary from its average power.
Low-pass filter 2 provides different time constants for noise (non-detected speech) and
speech. It determines the average of the noise reference level. In case of background
noise the level at the output of LP2 is approximately the level of the input. Due to the
offset OFF the comparator remains in the initial state. In case of speech at the
comparator input the difference between the signal levels of the offset branch and of the
LP2-branch increases and the comparator changes state. At speech bursts the digital
signals arriving at the comparator via the offset branch change faster than those via the
LP2-branch so that the comparator changes its polarity. Hence two logical levels are
generated: one for speech and one for noise.
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A small fade constant (LP2N) enables fast settling down the LP2 to the average noise
level after the end of speech recognition. However, a too small time constant for LP2N
can cause rapid charging to such a high level that after recognizing speech the danger
of an unwanted switching back to noise exists. It is recommended to choose a large
rising constant (LP2S) so that speech itself charges the LP2 very slowly. Generally, it is
not recommended to choose an infinite LP2S because then approaching the noise level
is disabled. During continuous speech or tones the LP2 will be charged until the limitation
LP2L is reached. Then the value of LP2 is frozen until a break discharges the LP2. This
limitation LP2L of this charging especially on the RX-path permits transmission of
continuous tones and “music on hold”.
The offset stage represents the exact level threshold in [dB] between the speech signal
and averaged noise.
4.4.3.2
Signal Processing
As described in the preceding chapter, the background noise monitor is able to
discriminate between speech and noise. In very short speech pauses e.g. between two
words, however, it changes immediately to non-speech, which is equal to noise.
Therefore a peak detection is required in front of the Noise Monitor.
The main task of the Peak Detector is to bridge the very short speech pauses during a
monologue so that this time constant has to be long. Furthermore, the speech bursts are
stored so that a sure speech detection is guaranteed. But if no speech is recognized the
noise low-pass LP2 must be charged rapidly to the average noise level.
Additionally the noise edges are to be smoothed. Therefore two time constants are
necessary and are separately programmable: PDS for speech and PDN for space
(background noise) signals.
The Peak Detector is very sensitive to spikes. The LP1 filters the incoming signal
containing noise in a way that main spikes are eliminated. Due to the programmable time
constant it is possible to refuse high-energy sibilants and noise edges.
To compress the speech signals in their amplitudes and to ease the detection of speech,
the signals have to be companded logarithmically. Hereby, the speech detector should
not be influenced by the system noise which is always present but should discriminate
between speech and background noise. The limitation of the logarithmic amplifier can be
programmed via the parameter LIM, where the upper half-byte features LIMX and the
lower half-byte LIMR. LIM is related to the maximum PCM level (+3.14 dBm0). A signal
exceeding the limitation defined by LIM is getting amplified logarithmically, while very
smooth system noise below is neglected. It should be the level of the minimum system
noise which is always existing; in the transmit path the noise generated by the telephone
circuitry itself and in receive direction the level of the first bit which is stable without any
speech signal at the receive path.
Data Sheet
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Description of the programmable speech detector parameters:
Parameter
# of CRAM
Bytes
Range
Comment
LP1
OFF
PDS
PDN
LP2S
LP2N
LP2L
LIMX, LIMR
1
1
1
1
1
1
1
1
1 to 512 ms
0 to 50 dB
1 to 512 ms
1 to 512 ms
4 to 2000 ms
1 to 512 ms
0 to 95 dB
– 36 to – 78 dB
Time constant LP1
Level offset up to detected noise
Time constant PD (signal)
Time constant PD (noise)
Time constant LP2 (signal)
Time constant LP2 (noise)
Limitation of LP2, related to LIM
Limitation of logarithmic amplifier
4.4.4
Speech Comparators (SC)
Switching from one active mode to another one is controlled by the speech comparators,
provided the speech detectors are indicating speech. There are two speech
comparators, one at the acoustic (AE) and one at the line side (LE). These comparators
continuously compare the signal levels of both signal paths and control the effect of the
echoes at the acoustic side and the line side. Once speech activity has been detected,
the comparator switches at once in that direction in which the speech signal is stronger.
For this purpose each signal is compared to the sum of the other and the returned echo.
4.4.4.1
Speech Comparator at the Acoustic Side (SCAE)
In principle, the SCAE works according to the following equation:
if
SX > SR + VAE then TX
else RX
Being in RX-mode, the speech comparator at the acoustic side controls the switching to
TX-mode. Only if the SX-signal is higher than the SR-signal plus the expected/measured
acoustic level enhancement (VAE), the comparator switches immediately to TX-mode.
Physically the level enhancement (VAE) is divided into two parts: GAE and GDAE.
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Figure 80
Speech Comparator at the Acoustic Side
At the SCAE-input, logarithmic amplifiers compress the signal range. Hence after the
required signal processing for controlling the acoustic echo, pure logarithmic levels on
both paths are compared.
Principally, the main task of the comparator is to control the echo. The internal coupling
due to the direct sound and mechanical resonances are covered by GAE. The external
coupling, mainly caused by the acoustic feedback, is controlled by GDAE/PDAE.
The Gain of the Acoustic Echo (GAE) corresponds to the terminal couplings of the
complete telephone: GAE is the measured or calculated level enhancement between
both receive and transmit inputs of the SCAE (see figure Chapter 78). It equals the sum
of the amplification of ALS plus the gain due to the loudspeaker/microphone coupling
plus the TX-amplification of AMIC1 and GX1. To succeed in a sure differentiation
between original speech and echo, it must be guaranteed that the TX-signal does not
run into saturation due to the loudspeaker/microphone coupling. Therefore, it is
recommended to reduce the TX-gain by 10 dB in front of the SCAE at least in the loudest
loudspeaker volume step. To fulfill the sending loudness rating, this gain is realized by
the LGAX/AGCX which follows the SCAE. Of course, the GAE has to be reduced by the
same amount.
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To control the acoustic feedback two parameters are necessary: GDAE-features the
actual reserve on the measured GAE. Together with the Peak Decrement (PDAE) it
simulates the echo behaviour at the acoustic side: After RX-speech has ended there is
a short time during which hard couplings through the mechanics and resonances and the
direct echo are present. Till the end of that time (∆t) the level enhancement VAE must
be at least equal to GAE to prevent clipping caused by these internal couplings. Then,
only the acoustic feedback is present. This coupling, however, is reduced by air
attenuation. For this in general the longer the delay, the smaller the echo being valid.
This echo behaviour is featured by the decrement PDAE.
Figure 81
Interdependence of GDAE and PDAE
According to figure 81, a compromise between the reserve GDAE and the decrement
PDAE has to be made: a smaller reserve (GDAE) above the level enhancement GAE
requires a longer time to decrease (PDAE). It is easy to overshout the other side but the
intercommunication is harder because after the end of the speech, the level of the
estimated echo has to be exceeded. On the contrary, with a higher reserve (GDAE*) it
is harder to overshout continuous speech or tones, but it enables a faster
intercommunication because of a stronger decrement (PDAE*).
Two pairs of coefficients, GDSAE/PDSAE when speech is detected, and GDNAE/
PDNAE in case of noise, offer a different echo handling for speech and non-speech.
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With speech, even if very strong resonances are present, the performance will not be
worsened by the high GDSAE needed. Only when speech is detected, a high reserve
prevents clipping. A time period ETAE [ms] after speech end, the parameters of the
comparator are switched to the “noise” values. If both sets of the parameters are equal,
ETAE has no function.
Description of the programmable parameters:
Parameter
# of CRAM
Bytes
Range
Comment
GAE
GDSAE
PDSAE
1
1
1
– 48 to + 48 dB
0 to 48 dB
0.16 to 42 ms/dB
GDNAE
PDNAE
1
1
0 to 48 dB
0.16 to 42 ms/dB
ETAE
1
0 to 1020 ms
Gain of Acoustic Echo
Reserve when speech is detected
Peak Decrement
when speech is detected
Reserve when noise is detected
Peak Decrement
when noise is detected
Echo time
4.4.4.2
Speech Comparator at the Line Side (SCLE)
Principally, the SCLE works similarly to the SCAE. The formula of SCLE is the following:
if
SR > SX + VLE then RX
else TX
Being in TX-mode, the speech comparator at the line side controls the switching to RXmode. When the SR-signal is higher than the SX-signal plus the expected/measured
echo return loss (VLE) and if SDR has detected speech, the comparator switches
immediately to RX-mode.
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Figure 82
Speech Comparator at the Line Side
The Gain of the Line Echo (GLE) directly corresponds to the echo return loss of the link.
Generally, it is specified to 27 dB. However, the worst case loss can be estimated to
10 dB. This means, the echo returns at least attenuated by 10 dB.
Similarly to the acoustic side, GDLE at the line side features the reserve above GLE
which is necessary to control the echo via the decrement PDLE. GDLE and PDLE are
interdependent. Exactly ∆t [ms] after the end of RX-speech the level enhancement VLE
must be at least GLE to prevent clipping.
Two pairs of coefficients are available: GDSLE/PDSLE while speech is detected and
GDNLE/PDNLE in case of noise. This offers the possibility to control separately the farend echo during speech and the near-end echo while noise is detected. However, this
requires an attenuation between the speech detectors SDX and SDR: If the SDX does
not recognize any speech, the SDR must not detect speech due to the far-end echo.
Note, that LIMX and LIMR are also influencing the sensitivity of the speech detection.
ETLE [ms] after the final speech detection the parameter sets are switched. If both sets
are equal, ETLE has no meaning.
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Description of the programmable parameters:
Parameter
# of CRAM
Bytes
Range
Comment
GLE
GDSLE
PDSLE
1
1
1
– 48 to + 48 dB
0 to 48 dB
0.16 to 42 ms/dB
GDNLE
PDNLE
1
1
0 to 48 dB
0.16 to 42 ms/dB
ETLE
1
0 to 1020 ms
Gain of Line Echo
Reserve when speech is detected
Peak Decrement
when speech is detected
Reserve when noise is detected
Peak Decrement
when noise is detected
Echo time
4.4.4.3
Automatic Gain Control of the Transmit Direction (AGCX)
Optionally an AGCX is inserted into the transmit path (see figure 83) to reach nearly
constant loudness ratings independent from the varying distance between the speaking
person and the microphone. The AGCX works only together with the speakerphone
function (GCR.SP=1).
Operation of the AGCX depends on a threshold level. The threshold is defined by the
parameter COMX (value relative to the maximum PCM-value). Regulation follows two
time constants: TMHX for signal amplitudes above the threshold and TMLX for
amplitudes below. Usually TMHX will be chosen up to 10 times faster than TMLX. The
bold line in figure Chapter 84 depicts the steady-state output level of the AGCX as a
function of the input level.
Data Sheet
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Codec
Figure 83
Block Diagram of the AGC in Transmit Direction
For reasons of physiological acceptance the AGCX gain is automatically reduced in case
of continuous background noise e.g. by ventilators. The reduction is programmed via the
NOlSX-parameter. When the noise level increases the threshold determined by NOISX,
the amplification will be reduced by the same amount the noise level is above the
threshold.
A programmable Loudness Gain Adjustment stage (LGAX) offers the possibility to
amplify the transmit signal after the speech detector SDX. If a lower signal range in front
of the SDX is necessary to determine between speech and echo a part of the transmit
signal amplification can be transferred to the LGAX. It is enabled with the bit GCR.SP.
Note: Even if the AGCX is disabled in speakerphone mode the LGAX remains enabled.
If the speakerphone is in receive mode, the AGCX is not working; instead the last gain
setting is used and regulation starts with this value as soon as the speakerphone returns
into transmit mode again. For transmission measurements with this transient behavior it
is recommended not to use a continuous sinewave signals but some kind of synthetic
speech (e.g. switched noise or Composite Source Signal CSS). The sweep range of the
switchable attenuation ATT (see chapter 4.4.1) is affected by the AGCX.
If the automatic gain control enlarges the signal level, the sweep range will be increased
accordingly in order to obtain a constant over-all gain in transmit and receive direction
(constant TCL, constant echo return loss).
Data Sheet
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The initial gain (AGIX) is used immediately after enabling the AGCX to allow a fast
settling time of the AGC.
AGC INPUT LEVEL
-50dBm0
-40dBm0
-30dBm0
-20dBm0
-10dBm0
MAX. PCM
MAX. PCM
-10dBm0
AGX=0...+18dB
AGC
OUTPUT
LEVEL
AGX+|AAX|
-20dBm0
COMX
-30dBm0
-40dBm0
AGX
-50dBm0
XKEN.DRW
Figure 84
Level Diagram For the AGC in Transmit Direction
Data Sheet
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Description of the programmable parameters:
Parameter # of CRAM
Bytes
Range
Comment
LGAX
COMX
AAX
AGX
AGIX
TMLX
TMHX
NOISX
– 12 to 12 dB
0 to – 73 dB
0 to 47 dB
0 to 18 dB
0 to 18 dB
1 to 2700 ms/dB
1 to 340 ms/dB
0 to – 95 dB
Loudness Gain Adjustment
Compare level rel. to max. PCM-value
Attenuation range of Automatic Control
Gain range of Automatic control
Initial AGC gain transmit
Settling time constant for lower levels
Settling time constant for higher levels
Threshold for AGC-reduction
by background noise
4.4.5
1
1
1
1
1
1
1
1
Automatic Gain Control of the Receive Direction (AGCR)
The Automatic Gain Control of the receive direction AGCR (see figure Chapter 85) is
similar to the transmit AGC. One additional parameter (AAR) offers more flexibility since
the AGCR is able to attenuate signals as well. Depending on the parameters AAR and
AGR different behaviours of the AGCR are possible as figure Chapter 86 illustrates. For
example with AGR set to 0dB and AAR set to maximum (-48 dB) the AGCR acts as a
limiter.
The AGCR is working only together with the speakerphone function (GCR.SP=1). The
digital gain stage LGAR is always enabled in speakerphone mode, independent of the
setting of GCR.AGCR.
It is highly recommended to program reasonable amplifications in the digital gain stages.
Otherwise the ASP will run into saturation above the 3.14 dB PCM-value.
Note that the speech detector for the receive direction is supplied with the signal that
comes out of the AGR-block unless XCR.PGCR = ’1’.
Data Sheet
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Figure 85
Function of the Receive AGC
Data Sheet
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AGC INPUT LEVEL
-50dBm0
-40dBm0
-30dBm0
-20dBm0
-10dBm0
MAX. PCM
MAX. PCM
-10dBm0
AGR=0...+18dB
AGC
OUTPUT
LEVEL
AAR=0...-48dB
AGR+|AAR|
-20dBm0
COMR
-30dBm0
AGR>0
-40dBm0
AGR=0
-50dBm0
RKEN.DRW
Figure 86
Level Diagram For the AGC in Receive Direction
If the speakerphone is in transmit mode, the AGCR is not working; instead the last gain
setting is used and the regulation starts with this value when the speakerphone has gone
back into receive mode again.
The initial attenuation (AGIR) is used immediately after enabling the AGCR to allow a
fast settling time of the AGC.
The sweep range of the switchable attenuation ATT is affected by the AGCR. If the
automatic gain control enlarges or reduces the signal level, the sweep range will be
adjusted automatically in a way, that the over-all gain in transmit and receive direction
remains constant (constant TCL, constant echo return loss).
Because of this the AGCR can be used for a comfortable receive volume control where
the TCL value is the same for each volume setting and thus providing an optimal
speakerphone performance. For such a volume control the momentary attenuation of the
AGCR has to be read out by a SOP_D command. The parameters AGIR, COMR, can
be determined for the desired volume change and written back in the CRAM.
Data Sheet
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Description of the programmable parameters:
Parameter # of CRAM
Bytes
Range
Comment
LGAR
COMR
AAR
AGIR
AGR
TMLR
TMHR
NOISR
– 12 to 12 dB
0 to – 73 dB
0 to – 47 dB
18 to – 47 dB
0 to 18 dB
1 to 2700 ms/dB
1 to 340 ms/dB
0 to – 95 dB
Loudspeaker Gain Adjustment
Compare level rel. to max. PCM-value
Attenuation range of Automatic control
Initial AGC attenuation/ gain receive
Gain range of Automatic control
Settling time constant for lower levels
Settling time constant for higher levels
Threshold for AGC-reduction
by background noise
4.4.6
1
1
1
1
1
1
1
1
Speakerphone Coefficient Set
Table 22 shows a possible configuration for a speakerphone application and can be
used as a basic programming set.
Table 22 Basic Coefficient Set
CMD Sequence
Coefficient
Code
Value
COP_A
COP_A
COP_A
COP_A
COP_A
COP_A
COP_A
COP_A
GAE
GLE
ATT
ETAE
ETLE
TW
DS
SW
0EH
E5H
48H
0CH
32H
09H
25H
64H
5.3 dB
– 10.2 dB
28.2 dB
48.0 ms
200.0 ms
144.0 ms
99 ms/dB
0.6 ms/dB
COP_B
COP_B
COP_B
COP_B
COP_B
COP_B
COP_B
COP_B
GDSAE
PDSAE
GDNAE
PDNAE
GDSLE
PDSLE
GDNLE
PDNLE
20H
05H
20H
05H
40H
02H
40H
02H
6.0 dB
8.5 ms/dB
6.0 dB
8.5 ms/dB
12.0 dB
21.3 ms/dB
12.0 dB
21.3 ms/dB
Data Sheet
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Table 22 Basic Coefficient Set (cont’d)
CMD Sequence
Coefficient
Code
Value
COP_C
COP_C
COP_C
COP_C
COP_C
COP_C
COP_C
COP_C
LIMX, LIMR
OFFX
OFFR
LP2LX
LP2LR
LP1X
LP1R
reserved 00H
44H
0CH
0CH
20H
20H
E1H
E1H
– 54 dB, – 54 dB
4.5 dB
4.5 dB
12 dB
12 dB
4.0 ms
4.0 ms
COP_D
COP_D
COP_D
COP_D
COP_D
COP_D
COP_D
COP_D
PDSX
PDNX
LP2SX
LP2NX
PDSR
PDNR
LP2SR
LP2NR
26H
F4H
20H
44H
26H
F4H
20H
44H
102.3 ms
32.0 ms
6.6 s
30.0 ms
102.3 ms
32.0 ms
6.6 s
30.0 ms
COP_E
COP_E
COP_E
COP_E
COP_E
COP_E
COP_E
COP_E
LGAX
COMX
AAX
AGX
TMHX
TMLX
NOISX
AGIX
13H
C3H
20H
01H
0AH
24H
4FH
20H
4.50 dB
– 20.4 dB
12.0 dB
12.0 dB
14.0 ms/dB
383.0 ms/dB
– 66.2 dB
0 dB
COP_F
COP_F
COP_F
COP_F
COP_F
COP_F
COP_F
COP_F
LGAR
COMR
AAR
AGR
TMHR
TMLR
NOISR
AGIR
12H
B2H
55H
00H
0AH
2FH
4FH
5.5 dB
– 15.1 dB
– 33.2 dB
18.1 dB
14.0 ms/dB
500.9 ms/dB
– 66.23 dB
0 dB
Data Sheet
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4.5
Controlled Monitoring
A so called “controlled monitoring” can be done when the bit GCR.CME is set. This mode
can only be used together with the speakerphone mode (GCR.SP). With CME = ’1’ the
attenuation stage GHR is fixed to a value of 0 dB but the attenuation takes place in the
analog loudspeaker amplifier ALS in a way that the amplification of the ALS is set to –
9.5 dB or -21.5 dB (depends on ATCR.CMAS setting) as soon as the attenuation control
unit switches to transmit mode. Therefore in transmit direction the same behavior as in
speakerphone mode occurs but in the receive direction the handset output offers a signal
as in normal handset mode while the volume at the loudspeaker output will be reduced
to a low level during transmit mode. If the programming for the loudspeaker output
(ARCR.LSC) is already chosen for values of less or equal – 9.5 dB, no further attenuation
takes place.
In order to get a stable controlled monitoring due to the feedback of the microphone
signal to the loudspeaker via the sidetone stage it is possible to change the tap of the
sidetone signal from before to after the attenuation stage (PFCR.PGZ = ’1’).
4.6
Voice Data Manipulation
The codec offers several possibilities of manipulating and controlling the codec data to
support a variety of applications and operating modes. All the functions and modes can
be selected by setting the register bits listed in table 23. The signal paths and functions
are illustrated in the voice data manipulation block of figure 73.
Possible applications and operating modes which can be realized by the voice data
manipulation of the codec together with the time slot and data port selection of the
integrated IOM-2 Handler are e.g.:
• Three party conferencing with
- 1 device internal and 2 external subscribers or
- 2 device internal, tip-ring extension and 1 external subscriber
The addition of the subscriber information can be done completely in the terminal by
the integrated codec
• Communication between codec and other voice data processing devices on IOM-2
(e.g. ACE, Jade, SAM and ISAR)
• The data formats
PCM A-Law
PCM µ-Law
8-bit Linear and 16-bit Linear are provided.
The 8-bit formats of CH1 and CH2 in both directions can be masked by an
implemented mask register
• Monitoring a running phone call
• Intercommunication: During a running phone call a voice announcement or a query
can be switched or added to the desired outputs (handset, loudspeaker or transmit
direction)
Data Sheet
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Table 23 Voice Data Manipulation
Register
Bits
DSSR
DSS1X, DSS2X:
Data Source
Data Source
Selection Register Selection CH1X,
Data Source
Selection CH2X
Description
As data source for the transmit data channels
CH1X or CH2X respectively can be selected:
- Codec voice data XDAT
- Addition of XDAT and the receive channel
CH2R or CH1R respectively.
- Receive channel CH2R or CH1R respectively
- Idle code
The data of the receive channels can be
attenuated individually by ATT1R, ATT2R to
ensure an acceptable speech quality in the
three party conferencing
DSSR:
As data source for the codec receive data
Data Source
channel RDAT can be selected:
Selection Receive - Receive channel CH1R
- Receive channel CH2R
- Addition of CH1R and CH2R
- Idle code
ENX1, ENX2:
Enable Transmit
CH1, CH2
The transmit data of CH1X, CH2X can be
enabled or disabled
DF1R, DF2R:
Data Format
CH1R, CH2R
The data format
A-Law
µ-Law
8-bit linear and
16-bit linear can be selected
8LIN1, 8LIN2:
8-bit Linear CH1,
8-bit Linear CH2
An 8-bit linear code can be selected for transmit
and receive separately
MASK1, MASK2:
MASK1R,
Mask Data CH1,
MASK2R
Mask Channel 1,2 CH2
Register
The 8-bit formats of CH1 and CH2 in both
directions can be masked by an implemented
mask register
DFR
Data Format
Register
Data Sheet
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4.7
Test Functions
The codec provides several test and diagnostic functions which can be grouped as
follows:
•
•
•
•
•
•
•
•
All programmable configuration registers and coefficient RAM-locations are readable
Digital loop via PCM-register (DLP)
Digital loop via signal processor (DLS)
Digital loop via noise shaper (DLN)
Analog loop via analog front end (ALF)
Analog loop via converter (ALC)
Analog loop via noise shaper (ALN)
Analog loop via Z-sidetone (ALZ); sidetone gain stage GZ must be enabled
(PFCR.GZ = 1) and sidetone gain must be programmed with 0 dB; depending on the
DSSR bit setting in the Data Source Selection Register (DSSR) an addition to the
incoming voice signal is executed.
Data Sheet
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4.8
Programming of the Codec
During initialization of the codec a subset of configuration registers and coefficient RAM
(CRAM) locations has to be programmed to set the configuration parameters according
to the application and desired features.
The codec can be programmed via microcontroller interface (see chapter 2.1) or the
IOM-2 MONITOR channel (see chapter 2.2.4).
The coefficient RAM (CRAM) can generally be programmed in power-up as well as in
power-down mode. However, due to the general possibility of concurrent accesses of the
ARCOFI®-DSP and the microcontroller, access collisions can not totally be eliminated.
To ensure the error free programming of the CRAM, it’s recommended to delay the
access after switching from power-down to power-up ( or after switching from power-up
to power-down respectively) by a setup time of 4 IOM-2 frames, i.e 500 µs.
An ARCOFI® compatible programming sequence is available (see chapter 2.1.1.1 and
chapter 4.8.1) which allows using the SOP, COP and XOP command sequences of the
ARCOFI.
The codec can also be programmed by addressing the configuration registers and
coefficient RAM (CRAM) locations directly (see chapter 4.8.2).
The following two chapters 4.8.1 and 4.8.2 give an overview of the access to the codec
parameters.
For more detailed information about the individual parameters refer to the corresponding
sections in the functional and register description of the codec .
4.8.1
Indirect Programming of the Codec (SOP, COP, XOP)
This programming sequence is compatible to the SOP, COP and XOP command
sequences of the ARCOFI. It gives indirect access to the codec registers 60H-6EH and
the CRAM (80H-FFH). The codec command word (cmdw) is followed by a defined
number of data bytes (data n; n = 0, 1, 4 or 8). The number of data bytes depends on the
codec command. The commands can be applied in any order and number. The coding
of the different SOP, COP and XOP commands is listed in the description of the
command word (CMDW) in chapter 4.8.1.1.
Structure of the ARCOFI compatible sequence:
defined length
defined length
00H
Data Sheet
cmdw
data1
data n
cmd
155
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data n
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4.8.1.1
Description of the Command Word (CMDW)
Value after reset: BFH
7
CMDW
0
R/W
0
CMD5
CMD4
CMD3
CMD2
CMD1
R/W
0:
1:
CMDx
Address to internal programmable locations
CMD 5 4 3 2 1 0
0 0 X X X X code reserved
0 1 X X X X status operation (SOP)
1 0 X X X X coefficient operation (COP)
1 1 X X X X extended operation (XOP)
CMD0
writing to configuration registers or to coefficient RAM
reading from configuration registers or from coefficient RAM
Coding of Status Operations (SOP):
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1
0
CMD
Name
Status
CMD
Seq. Len.
CMD Sequence
Description
(Registers being
accessed)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SOP_0
SOP_1
SOP_2
SOP_3
SOP_4
SOP_5
SOP_6
SOP_7
SOP_8
SOP_9
SOP_A
SOP_B
SOP_C
SOP_D
SOP_E
SOP_F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
9
<GCR>
<PFCR>
<TGCR>
<TGSR>
<ACR>
<ATCR>
<ARCR>
<DFR>
<DSSR>
<XCR/XSR>
<MASK1R>
<MASK2R>
<TFCR>
<TMR1>
<TMR2>
<DFR>..<GCR>
Data Sheet
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Coding of Coefficient Operations (COP)
Bit 3
2
1
0
CMD
Name
Status
CMD
Seq.
Len.
CMD
Sequence
Description
Comments
0
0
0
0
COP_0
R/W
9
Tone generator 1
0
0
0
1
COP_1
R/W
9
<F1> <F1> <G1> <GD1>
<T1> <T1> <..> <..>
<F2> <F2> <G2> <GD2>
<T2> <T2>
<GTR> <GTX>
<F3> <F3> <G3> <GD3>
<T3> <T3>
<FD> <FD>
<K> <A1> <A2> <GE>
<TON> <TON>
<TOFF> <TOFF>
<GX> <GX>
<GR> <GR>
<ATT1R> <ATT2R>
<..> <..>
<GZ> <GZ>
<..> <..>
<FX1>..<FX8>
<FX9>..<FX12>
<FR9>..<FR12>
<FR1>..<FR8>
<SP1>..<SP8>
<SP9>..<SP16>
<SP17>..<SP24>
<SP25>..<SP32>
<AGCX1>..<AGCX8>
<AGCR1>..<AGCR8>
0
0
1
0
COP_2
R/W
9
0
0
0
1
1
0
1
0
COP_3
COP_4
R/W
R/W
5
5
0
1
0
1
COP_5
R/W
9
0
1
1
0
COP_6
R/W
5
0
1
1
0
1
0
1
0
COP_7
COP_8
R/W
R/W
9
9
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
COP_9
COP_A
COP_B
COP_C
COP_D
COP_E
COP_F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9
9
9
9
9
9
9
Tone generator 2
Additional TG gain
Tone generator 3
Dual tone frequency
Tone filter
Control generator
Transmit gain
Receive gain
Conferencing Atten.
Sidetone gain
Correction filter FX
Correction filter FR
Coefficients for
Speakerphone
AGC transmit
AGC receive
Coding of Extended Operations (XOP)
Bit 3
2
1
0
CMD
Name
Status
CMD
Seq.
Len.
Comments
0
1
1
0
XOP_6
R/W
6
1
1
1
1
XOP_F
R/W
1
Sequence for volume control of the loudspeaker
(SEQ = <ARCR register> <CRAM.LGAR>
<CRAM.ATT> <CRAM.GAE> <CRAM.COMR>)
No operation (NOP)
Data Sheet
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4.8.2
Direct Programming of the Codec
The codec registers (60H-6FH) and the CRAM (80H-FFH) are directly accessible (see
chapter 2.1 and 4.8.2.1).
4.8.2.1
CRAM Back-Up Procedure
For the direct access to individual CRAM coefficients via microcontroller a back-up
procedure is provided. This ensures that the codec DSP always works with a consistent
and valid coefficient block during the changing of CRAM parameters. The following
section describes this back-up procedure.
Note: For the ARCOFI compatible programming sequence (see chapter 2.1.1.1) such a
back-up procedure for the CRAM blocks is not necessary because it is done
automatically.
The control of the back-up procedure is done with the CRAM Control Register (CCR) and
the CRAM Status Register (CSR).The Control and Status bits in these registers are
explained in the following section:
CRAM Block Address (CBADR)
The CRAM range (80H to FFH) is subdivided in 16 CRAM blocks with the block address
CBADR = ’0H’ to ’FH’. Each coefficent block has 8 bytes. The mapping of the CRAM
coefficents corresponds to the COP_x sequences of the ARCOFI (see table 25 and
chapter 4.8.1.1).
DSP CRAM Access (DCA)
By setting this bit it is possible to select whether the codec DSP has access to the CRAM
blocks in the normal CRAM range (’0’) or to a temporary 8-byte CRAM block (’1’).
Start Back-up Procedure (SBP)
Setting this bit starts the transfer of a CRAM block (CBADR) to the temporary 8-byte
CRAM block.
Busy Back-up Procedure (BSYB)
This status bit indicates if a transfer of a CRAM block (CBADR) to the temporary 8-byte
CRAM block is running (’1’) or not (’0’). If the transfer is running no CRAM access via
microcontroller interface is allowed.
Figure 87 shows the access structure of CRAM and temporary CRAM. Figure 88 gives
a signal flow of the back-up procedure of a CRAM block x (x = 0...F).
Data Sheet
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Codec
µC
Access
Data Flow
<CBADR_F>
<CBADR_E>
<CBADR_D>
<CBADR_C>
<CBADR_B>
<CBADR_A>
<CBADR_9>
<CBADR_8>
<CBADR_7>
<CBADR_6>
<CBADR_5>
<CBADR_4>
<CBADR_3>
<CBADR_2>
<CBADR_1>
<CBADR_0>
DCA = ’0’
DSP
Access
DCA = ’1’
Temporary CRAM
Figure 87
CRAM Access Structure
Write:
CCR.DCA = ’1’
CCR.SBP = ’1’
CCR.CBADR = ’x’’
Start back-up procedure block x
DSP access to temp. CRAM block
as soon as transfer has completed
Transfer busy
Read CSR.BSYB
Back-up procedure busy?
Transfer not busy
- µC access to CRAM possible
- Switching the DSP access
between CRAM and temporary
CRAM block is possible by DCA
Write <Block X>
Update CRAM block x
Write CCR.DCA = ’0’
DSP access to CRAM block x
Figure 88
Signal Flow of the Back-up Procedure
Data Sheet
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Codec
4.8.3
Reference Tables for the Register and CRAM Locations
Table 24 Configuration Registers
Address CMDW
WR/RD
Register
Bit
Effect
GCR
SP
AGCX
Speakerphone ON/OFF
TX-automatic gain control (if
GCR.SP = 1)
RX-automatic gain control (if
GCR.SP = 1)
Modified gain control receive
Controlled monitoring enable
Power-up/down mode
Attenuation of the receive channel
related
to transmit channel 2
Attenuation of the receive channel
related
to transmit channel 1
SOP_0
60H
10H/90H
AGCR
MGCR
CME
PU
ATT2R
ATT1R
SOP_1
61H
11H/91H
PFCR
GX
GR
GZ
FX
PGZ
FR
DHPR
DHPX
TX digital gain
RX digital gain
Sidetone gain
TX-frequency correction filter
Position sidetone gain
RX-frequency correction filter
Disable high-pass (50 Hz) receive
Disable high-pass (50 Hz) transmit
12H/92H
TGCR
ET
DT
ETF
PT
SEQ
TM
SM
SQTR
Enable tone generator
Dual tone mode
Enable tone filter
Pulsed tone
Sequence generator
Tone mode
Stop mode
Square/trapezoid shaped signal
SOP_2
62H
Data Sheet
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Codec
Table 24 Configuration Registers (cont’d)
Address CMDW
WR/RD
Register
Bit
Effect
13H/93H
TGSR
TRL
TRR
DTMF
TRX
-
Reserved
Tone ringing via loudspeaker
Reserved
Tone ringing in receive direction
DTMF mode
Tone ringing in transmit direction
Reserved
Reserved
14H/94H
ACR
SEM
Reserved
Single ended mode of loudspeaker
amplifier
Disable HOP (tristate)
Disable HON (tristate)
Disable LSP (tristate)
Disable LSN (tristate)
SOP_3
63H
SOP_4
64H
DHOP
DHON
DLSP
DLSN
SOP_5
65H
15H/95H
ATCR
MIC(7:4)
CMAS
AIMX(1:0)
Microphone amplifier control
Reserved
Controlled monitoring attenuation
select
Analog input multiplexer
SOP_6
66H
16H/96H
ARCR
HOC(7:4)
LSC(3:0)
Handset output amplifier control
Loudspeaker output amplifier control
17H/97H
DFR
DF2R(7:6)
DF2X(5:4)
DF1R(3:2)
DF1X(1:0)
Data format CH2 receive
Data format CH2 transmit
Data format CH1 receive
Data format CH1 transmit
SOP_7
67H
Data Sheet
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Codec
Table 24 Configuration Registers (cont’d)
Address CMDW
WR/RD
Register
Bit
Effect
18H/98H
DSSR
DSSR(7:6)
ENX2
ENX1
DSS2X(3:2)
DSS1X(1:0)
Data source selection receive
Enable transmit CH2
Enable transmit CH2
Data source selection CH2 Transmit
Data source selection CH1 Transmit
19H/-
XCR
PGCR
PGCX
ERA
MAAR
Position of gain control receive
Position of gain control transmit
Enhanced reverse attenuation
Reserved
Reserved
Reserved
Reserved
Monitoring AGC Attenuation Receive
-/99H
XSR
if MAAR
= ’0’
PGCR
Read-back position of gain control
receive
Read-back position of gain control
transmit
Read-back enhanced reverse
attenuation
Reserved
Reserved
Reserved
Speakerphone state
SOP_8
68H
SOP_9
69H
PGCX
ERA
SPST(1:0)
-/99H
XSR
if MAAR
= ’1’
Value of the momentary AGC
attenuation
SOP_A
6AH
1AH/9AH MASK1R
MASK1(7:2) Mask register CH1
MP1(1:0)
Mask Position CH1
1BH/9BH MASK2R
MASK2(7:2) Mask register CH2
MP2(1:0)
Mask Position CH2
SOP_B
6BH
Data Sheet
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Codec
Table 24 Configuration Registers (cont’d)
Address CMDW
WR/RD
Register
Bit
Effect
ALTF(5:3)
DLTF(2:0)
Reserved
Reserved
Analog Loops and test functions
Digital Loops and test functions
SOP_C
6CH
1CH/9CH TFCR
SOP_D
6DH
1DH/9DH TMR1
Reserved
1EH/9EH TMR2
Reserved
1FH/9FH
ARCOFI related sequence for WR/RD
of 8 bytes (Registers)
SOP_E
6EH
SOP_F
-
<DFR>
<ARCR>
<ATCR>
<ACR>
<TGSR>
<TGCR>
<PFCR>
<GCR>
For the register below there is no command word available
6FH
Data Sheet
WR/
CCR
DCA
SBP
CBADR(3:0)
Reserved
Reserved
DSP CRAM access
Start back-up procedure
CRAM block address
RD
CSR
DCA
BSYB
CBADR(3:0)
Reserved
Reserved
DSP CRAM access
Busy back-up procedure
CRAM block address
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Codec
Table 25 Coefficient RAM (CRAM)
Address CMDW
WR/RD
Mnemonic Description
COP_0: Tone generator parameter set 1
87H
86H
85H
84H
83H
82H
81H
80H
20H/A0H
F1
G1
GD1
T1
-
Tone generator frequency higher byte
Tone generator frequency lower byte
Tone generator amplitude
Trapezoid generator amplitude
Beat tone time higher byte
Beat tone time lower byte
Reserved
Reserved
COP_1: Tone generator parameter set 2; tone generator level adjustment
8FH
8EH
8DH
8CH
8BH
8AH
89H
88H
21H/A1H
F2
G2
GD2
T2
GTR
GTX
Tone generator frequency higher byte
Tone generator frequency lower byte
Tone generator amplitude
Trapezoid generator amplitude
Beat tone time span higher byte
Beat tone time span lower byte
Level adjustment for receive path
Level adjustment for transmit path
COP_2: Tone generator parameter set 3;
Parameter set for the DTMF-generator (TGSR.DTMF = 1)
97H
96H
95H
94H
93H
92H
91H
90H
22H/A2H
F3
G3
GD3
T3
FD
Tone generator frequency higher byte
Tone generator frequency lower byte
Tone generator amplitude
Trapezoid generator amplitude
Beat tone time span higher byte
Beat tone time span lower byte
Dual tone frequency higher byte
Dual tone frequency lower byte
COP_3: Tone filter
9BH
9AH
99H
98H
Data Sheet
23H/A3H
K
A1
A2
GE
Attenuation of the stop-band
Center frequency
Bandwidth
Saturation amplification
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Codec
Table 25 Coefficient RAM (CRAM) (cont’d)
Address CMDW
WR/RD
Mnemonic Description
COP_4: Control generator
A3H
A2H
A1H
A0H
24H/A4H
TON
TOFF
Turn-on period of the tone generator higher byte
Turn-on period of the tone generator lower byte
Turn-off period of the tone generator higher byte
Turn-off period of the tone generator lower byte
COP_5: Receive and transmit gain
AFH
AEH
ADH
ACH
ABH
AAH
A9H
A8H
25H/A5H
GX
GR
ATT1R
ATT2R
-
Transmit gain higher byte
Transmit gain lower byte
Receive gain higher byte
Receive gain lower byte
Conferencing attenuation CH1R
Conferencing attenuation CH2R
Reserved
Reserved
COP_6:Sidetone gain
B3H
B2H
B1H
B0H
26H/A6H
GZ
-
Sidetone gain higher byte
Sidetone gain lower byte
Reserved
Reserved
COP_7:Transmit correction filter part 5 to part 12
BFH
BEH
BDH
BCH
BBH
BAH
B9H
B8H
Data Sheet
27H/A7H
FX
Transmit correction filter coefficients part 1
Transmit correction filter coefficients part 2
Transmit correction filter coefficients part 3
Transmit correction filter coefficients part 4
Transmit correction filter coefficients part 5
Transmit correction filter coefficients part 6
Transmit correction filter coefficients part 7
Transmit correction filter coefficients part 8
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Codec
Table 25 Coefficient RAM (CRAM) (cont’d)
Address CMDW
WR/RD
Mnemonic Description
COP_8:Transmit correction filter part 1 to part 4 and receive correction filter part 9 to
part 12
C7H
C6H
C5H
C4H
C3H
C2H
C1H
C0H
28H/A8H
FX
FR
Transmit correction filter coefficients part 9
Transmit correction filter coefficients part 10
Transmit correction filter coefficients part 11
Transmit correction filter coefficients part 12
Receive correction filter coefficients part 9
Receive correction filter coefficients part 10
Receive correction filter coefficients part 11
Receive correction filter coefficients part 12
COP_9:Receive correction filter part 1 to part 8
CFH
CEH
CDH
CCH
CBH
CAH
C9H
C8H
29H/A9H
FR
Receive correction filter coefficients 1
Receive correction filter coefficients 2
Receive correction filter coefficients 3
Receive correction filter coefficients 4
Receive correction filter coefficients 5
Receive correction filter coefficients 6
Receive correction filter coefficients 7
Receive correction filter coefficients 8
COP_A:Parameter set for transmit and receive speech comparator
Parameter set for speakerphone control unit
D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H
Data Sheet
2AH/AAH GAE
GLE
ATT
ETAE
ETLE
TW
DS
SW
Gain of acoustic echo
Gain of line echo
Attenuation programmed in GHR or GHX
Echo time (acoustic side)
Echo time (line side)
Wait time
Decay speed
Switching time
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Codec
Table 25 Coefficient RAM (CRAM) (cont’d)
Address CMDW
WR/RD
Mnemonic Description
COP_B:Parameter set for transmit and receive speech comparator
DFH
DEH
2BH/ABH GDSAE
PDSAE
DDH
DCH
GDNAE
PDNAE
DBH
DAH
GDSLE
PDSLE
D9H
D8H
GDNLE
PDNLE
Reserve when speech is detected (acoustic side)
Peak decrement when speech is detected (acoustic
side)
Reserve when noise is detected (acoustic side)
Peak decrement when noise is detected (acoustic
side)
Reserve when speech is detected (line side)
Peak decrement when speech is detected (line
side)
Reserve when noise is detected (line side)
Peak decrement when noise is detected (line side)
COP_C:Parameter set for transmit and receive speech detector
E7H
E6H
E5H
E4H
E3H
E2H
E1H
E0H
2CH/ACH LIM
OFFX
OFFR
LP2LX
LP2LR
LP1X
LP1R
-
Starting level of the logarithmic amplifiers
Level offset up to detected noise (transmit)
Level offset up to detected noise (receive)
Limitation for LP2 (transmit)
Limitation for LP2 (receive)
Time constant LP1 (transmit)
Time constant LP1 (receive)
Reserved
COP_D:Parameter set for receive and transmit speech detector
EFH
EEH
EDH
ECH
EBH
EAH
E9H
E8H
Data Sheet
2DH/ADH PDSX
PDNX
LP2SX
LP2NX
PDSR
PDNR
LP2SR
LP2NR
Time constant PD for signal (transmit)
Time constant PD for noise (transmit)
Time constant LP2 for signal (transmit)
Time constant LP2 for noise (transmit)
Time constant PD for signal (receive)
Time constant PD for noise (receive)
Time constant LP2 for signal (receive)
Time constant LP2 for noise (receive)
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Codec
Table 25 Coefficient RAM (CRAM) (cont’d)
Address CMDW
WR/RD
Mnemonic Description
COP_E:Parameter set for transmit AGC
F7H
F6H
F5H
F4H
F3H
F2H
F1H
F0H
2EH/AEH LGAX
COMX
AAX
AGX
TMHX
TMLX
NOISX
AGIX
Loudness gain adjustment
Compare level rel. to max. PCM-value
Attenuation range of automatic control
Gain range of automatic control
Settling time constant for higher levels
Settling time constant for lower levels
Threshold for AGC-reduction by background noise
Initial AGC gain transmit
COP_F:Parameter set for receive AGC
FFH
FEH
FDH
FCH
FBH
FAH
F9H
F8H
Data Sheet
2FH/AFH
LGAR
COMR
AAR
AGR
TMHR
TMLR
NOISR
AGIR
Loudness gain adjustment
Compare level rel. to max. PCM-value
Attenuation range of automatic control
Gain range of automatic control
Settling time constant for higher lower levels
Settling time constant for lower levels
Threshold for AGC-reduction by background noise
Initial AGC attenuation/gain receive
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Clock Generation
5
Clock Generation
Figure 89 shows the clock system of the SCOUT. The oscillator is used to generate a
7.68 MHz clock signal. The DPLL generates the IOM-2 clocks FSC (8 kHz), DCL (1536
kHz) and BCL (768 kHz) synchronous to the received S/T frames (see figure 90).
The prescaler for the microcontroller clock output (MCLK) divides the 7.68 MHz clock by
1, 2 and 8 corresponding to the MCLK control bits in the MODE1 register. Additionally it
is possible to disable the MCLK output by setting the MCLK bits to ’11’.
XTAL
7.68 MHz
OSC
7.68 MHz
FSC
DCL
BCL
DPLL
3
CPLL
Codec
Clock
Reset Generation
C/I change
EAW
Watchdog
125 µs < t < 250 µs
125 µs < t < 250 µs
t = 125 µs
MCLK Prescaler
'00':
'01':
'10':
'11':
2
8
1
MCLK disabled
MCLK
MODE1.MCLK
clock_gen_s.vsd
Figure 89
Clock System of the SCOUT
Data Sheet
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Clock Generation
5.1
Jitter
5.1.1
Jitter on IOM-2
The DPLL only readjusts with each received F/L edge of the S interface.
If the receiver has not yet synchronized the DPLL will adjust in one step.
5.1.2
Jitter on S
The S transmit clock is derived from the S receive clock.
5.1.3
Jitter on MCLK
Jitter on the MCLK output is directly related to the crystal tolerance. Only clock dividers
are involved.
FSC
DCL
BCL
Figure 90
Clock waveforms
Data Sheet
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Reset
6
Reset
The SCOUT can be reset completely by a hardware reset (pin RST). Additionally each
functional block can be reset separately via register SRES.
If enabled an exchange awake, subscriber awake or watchdog time-out can generate a
reset on pin RSTO/SDS2. A hardware reset always generates a reset on pin RSTO/
SDS2 (see figure 91).
SDSx_CR Register
SDS1 Pin
SDSx
EAW
(Subscriber Awake)
RSS(2:1) = ’01’
C/I Code Change
(Exchange Awake)
SDS2
125 µs < t < 250 µs
125 µs < t < 250 µs
t = 125 µs
Watchdog
RSTO/
SDS2 Pin
Register
HDLC:
TR:
IOM:
MON:
CO:
CPLL:
(00H-2FH)
(30H-3BH)
(40H-5BH)
(5CH-5FH)
(60H-6FH)
-
RSS2 = ’0’
Reset Functional Block
Block
RSS1 = ’1’
1
Software Reset
(Register SRES)
Reset MODE1 Register
Internal Reset of all Registers
RST Pin
res_gen_s.vsd
Figure 91
Reset Generation. The above mentioned reset pulse widths are controlled by the
clock pin FSC
Data Sheet
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Reset
6.1
Reset Source Selection
The internal reset sources C/I code change, EAW and Watchdog can be output at the
low active reset pin RSTO/SDS2. The selection of these reset sources can be done with
the RSS2,1 bits in the MODE1 register according table 26.
If RSS2,1 = ’01’ the RSTO/SDS2 pin has SDS2 functionality and a serial data strobe
signal (see chapter 2.2.3) is output at the RSTO/SDS2 pin. In this case only a hardware
reset is output at RSTO/SDS2. The internal reset sources set the MODE1 register to its
default value.
Table 26
Reset Source Selection
RSS2
Bit 1
RSS1
Bit 0
C/I Code
Change
EAW
Watchdog
Timer
SDS2
Functionality
0
0
--
--
--
--
0
1
--
--
--
x
1
0
x
x
--
--
1
1
--
--
x
--
• C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/
I0) generates a reset pulse of 125µs ≤ t ≤ 250µs.
• EAW (Subscriber Awake)
A low pulse of at least 65 ns pulse width on the EAW input starts the oscillator from
the power down state and generates a reset pulse of 125 µs ≤ t ≤ 250 µs.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog
timer:
1.
2.
WTC1
WTC2
1
0
0
1
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset
pulse of 125 µs is generated.
If the watchdog timer is enabled (RSS = ’11’) the RSS bits can only be changed by a
hardware reset.
Data Sheet
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Reset
6.2
External Reset Input
At the active low RST input pin an external reset can be applied forcing the device into
the reset state. This external reset signal is additionally fed to the RSTO/SDS2 output.
The length of the reset signal is specified in chapter 8.1.8.
After an external reset all internal registers are set to their reset values (see register
description in chapter 7).
6.3
Software Reset Register (SRES)
Every internal functional block can be reset separately by setting the corresponding bit
in the SRES register (see chapter 7.2.15). The reset state is activated as long as the bit
is set to ’1’. The address range of the registers which will be reset at each SRES bit is
listed in figure 91.
6.4
Pin Behavior during Reset
During each reset the reference voltage (VREF) stays applied, the oscillator, data clock
(DCL) and microcontroller clock (MCLK) keep running.
During any reset that has an influence on the IOM handler (see figure 91) the pin FSC
is set to ’1’, the pin SDS1 is set to ’0’ and pin BCL, DD and DU are in the high-impedance
state.
During any reset that has an influence on the codec (see figure 91) the pins LSP, LSN,
HOP and HON are in the high-impedance state.
During any reset that has an influence on the transceiver (see figure 91) the line
transceiver pins are in the high-impedance state.
During hardware reset the pins SDX and INT are in the high-impedance state.
A hardware reset is always output at pin RSTO/SDS2. This reset will be released by the
falling edge of BCL following the release of the pin RST.
Data Sheet
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Detailed Register Description
7
Detailed Register Description
The register mapping is shown in Figure 92.
FFH
Codec Coefficient RAM
80H
70H
60H
40H
30H
20H
Reserved
Codec Configuration
IOM Handler (CDA, TSDP,
CR, STI), MONITOR Register
Transc., Interrupt, Mode Reg.
HDLC Control, CI Reg.
HDLC RFIFO/XFIFO
00H
Figure 92
Register Mapping
The register address range from 00-1FH is assigned to the two FIFOs having an identical
address range. The address range 20-2FH pertains to the HDLC controller and the CI
handler. The register set ranging from 30-3FH pertains to the transceiver, interrupt and
general configuration registers. The address range from 40-59H is assigned to the IOM
handler with the registers for timeslot and data port selection (TSDP) and the control
registers (CR) for the codec data (CO), transceiver data (TR), Monitor data (MON),
HDLC/CI data (HCI) and controller access data (CDA), serial data strobe signal (SDS),
IOM interface (IOM) and synchronous transfer interrupt (STI). The address range from
5C-5FH pertains to the MONITOR handler. The codec configuration registers and the
codec coefficient RAM (CRAM) are assigned to the address range 60-6FH or 80-FFH
respectively.
The register summaries are shown in the following tables containing the abbreviation of
the register name and the register bits, the register address, the reset values and the
register type (Read/Write). A detailed register description follows these register
summaries. The register summaries and the description are sorted in ascending order
of the register address.
Data Sheet
174
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Detailed Register Description
HDLC Control Registers, CI Handler
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
RFIFO
D-Channel Receive FIFO
00H-1FH R
XFIFO
D-Channel Transmit FIFO
00H-1FH W
ISTAH
RME
RPF
RFO
XPR
XMR
XDU
0
0
20H
R 10H
MASKH
RME
RPF
RFO
XPR
XMR
XDU
0
0
20H
W FCH
0
21H
R 40H
STAR
XDOV XFW
0
0
RACI
0
XACI
CMDR
RMC RRES
0
STI
XTF
0
XME XRES
21H
W 00H
0
RAC
DIM2 DIM1 DIM0
22H
R/W C0H
23H
R/W 00H
24H
R/W 00H
MODEH MDS2 MDS1 MDS0
EXMR
XFBS
TIMR
RFBS
SRA XCRC RCRC
CNT
0
ITF
VALUE
SAP1
SAPI1
0
MHA
25H
W FCH
SAP2
SAPI2
0
MLA
26H
W FCH
RBC0
26H
R 00H
RBC8
27H
R 00H
RBCL
RBC7
RBCH
0
0
0
OV RBC11
TEI1
TEI1
EA
27H
W FFH
TEI2
TEI2
EA
28H
W FFH
RSTA
VFR
RDO
CRC
RAB
SA1
SA0
C/R
TA
28H
R 0EH
TMH
0
0
0
0
0
0
0
TLP
29H
R/W 00H
Reserved
2AH2DH
CIR0
CODR0
CIC0
CIX0
CODX0
TBA2 TBA1 TBA0
CIR1
CODR1
CIX1
CODX1
Data Sheet
CIC1
S/G
0
BAS
2EH
R F3H
BAC
2EH
W FEH
0
2FH
R FCH
2FH
W FEH
CICW CI1E
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Detailed Register Description
Transceiver, Interrupt, General Configuration Registers
NAME
7
6
5
4
3
2
1
0
TR_
CONF0
DIS_
TR
0
EN_
FECV
0
L1SW
0
EXLP
LDD
30H
R/W 01H
TR_
CONF1
0
0
EN_
SFSC
0
0
1
1
1
31H
R/W 07H
TR_
CONF2
DIS_
TX
PDS
0
0
0
0
0
0
32H
R/W 80H
0
FECV
0
FSYN
0
LD
33H
R 00H
PD
LP_A
0
34H
R/W 08H
TR_STA
RINF
TR_CMD
SQRR
SQXR
XINF
MSYN MFEN
0
MFEN
DPRIO TDDIS
ADDR R/WRES
0
0
SQR1 SQR2 SQR3 SQR4
35H
R 40H
0
0
SQX1 SQX2 SQX3 SQX4
35H
W 4FH
Reserved
36H-37H
ISTATR
0
x
x
x
LD
RIC
SQC
SQW
38H
R 00H
MASKTR
0
1
1
1
LD
RIC
SQC
SQW
39H
R/W 7FH
Reserved
3AH3BH
ISTA
0
ST
CIC
TIN
WOV TRAN MOS HDLC
3CH
R 01H
MASK
0
ST
CIC
TIN
WOV TRAN MOS HDLC
3CH
W 7FH
MODE1
MCLK
MODE2
0
0
ID
0
0
SRES
0
0
Data Sheet
0
0
WTC1 WTC2 CFS
0
0
RSS2 RSS1
3EH
R/W 00H
DESIGN
3FH
R 0xH
RES_ RES_ RES_ RES_ RES_ RES_
CPLL MON HDLC IOM
TR
CO
3FH
W 00H
176
DREF AMOD PPSDX
3DH R/W 00H
2001-03-12
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Detailed Register Description
IOM Handler (Timeslot , Data Port Selection,
CDA Data and CDA Control Register)
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
CDA10
Controller Data Access Register (CH10)
40H R/W FFH
CDA11
Controller Data Access Register (CH11)
41H R/W FFH
CDA20
Controller Data Access Register (CH20)
42H R/W FFH
CDA21
Controller Data Access Register (CH21)
43H R/W FFH
CDA_
TSDP10
DPS
0
0
0
TSS
44H R/W 00H
CDA_
TSDP11
DPS
0
0
0
TSS
45H R/W 01H
CDA_
TSDP20
DPS
0
0
0
TSS
46H R/W 80H
CDA_
TSDP21
DPS
0
0
0
TSS
47H R/W 81H
CO_
TSDP10
DPS
0
0
0
TSS
48H R/W 80H
CO_
TSDP11
DPS
0
0
0
TSS
49H R/W 81H
CO_
TSDP20
DPS
0
0
0
TSS
4AH R/W 81H
CO_
TSDP21
DPS
0
0
0
TSS
4BH R/W 85H
TR_
DPS
TSDP_B1
0
0
0
TSS
4CH R/W 00H
TR_
DPS
TSDP_B2
0
0
0
TSS
4DH R/W 01H
Data Sheet
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Detailed Register Description
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
CDA1_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4EH R/W 00H
CDA2_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4FH R/W 00H
IOM Handler (Control Registers, Synchronous Transfer
Interrupt Control), MONITOR Handler
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
EN21 EN20 EN11 EN10
50H R/W 00H
EN_
B2R
EN_
B1R
EN_
B2X
EN_
B1X
0
51H R/W 3EH
EN_
D
EN_
B2H
EN_
B1H
0
0
0
52H R/W A0H
0
0
0
0
CO_CR
0
0
0
0
TR_CR
0
0
EN_
D
HCI_CR
DPS_
CI1
EN_
CI1
MON_CR DPS
EN_
MON
MCS
53H R/W 40H
SDS1_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
0
TSS
54H R/W 00H
SDS2_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
0
TSS
55H R/W 00H
IOM_CR
MCDA
STI
ASTI
MSTI
Data Sheet
SPU
0
MCDA21
0
TIC_
DIS
MCDA20
STOV STOV STOV STOV
21
20
11
10
0
0
0
0
STOV STOV STOV STOV
21
20
11
10
EN_ CLKM DIS_
BCL
OD
MCDA11
DIS_
IOM
MCDA10
56H R/W 00H
57H
R FFH
STI
21
STI
20
STI
11
STI
10
58H
R 00H
ACK
21
ACK
20
ACK
11
ACK
10
58H
W 00H
STI
21
STI
20
STI
11
STI
10
59H R/W FFH
178
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Detailed Register Description
Name
SDS_
CONF
7
6
5
0
4
0
3
0
0
2
1
0
0
ADDR R/WRES
SDS2_ SDS1_ 5AH R/W 00H
BCL BCL
0
Reserved
5BH
MOR
MONITOR Receive Data
5CH
R FFH
MOX
MONITOR Transmit Data
5CH
W FFH
R 00H
MOSR
MDR
MER
MDA
MAB
0
0
0
0
5DH
MOCR
MRE
MRC
MIE
MXC
0
0
0
0
5EH R/W 00H
MSTA
0
0
0
0
0
MAC
0
TOUT
5FH
R 00H
MCONF
0
0
0
0
0
0
0
TOUT
5FH
W 00H
2
1
0
Codec Configuration Registers
Name
7
6
5
4
3
GCR
SP
PFCR
GX
GR
GZ
FX
TGCR
ET
DT
ETF
PT
TGSR
0
TRL
0
TRR DTMF TRX
ACR
0
0
0
SEM DHOP DHON DLSP DLSN
AGCX AGCR MGCR CME
ATCR
MIC
ARCR
HOC
ADDR R/WRES
PU
ATT2R ATT1R 60H R/W 00H
PGZ
FR
DHPR DHPX
SEQ
TM
0
61H R/W 00H
SM
SQTR
62H R/W 00H
0
0
63H R/W 00H
CMAS
AIMX
LSC
64H R/W 00H
65H R/W 00H
66H R/W 00H
DFR
DF2R
DF2X
DF1R
DF1X
67H R/W 00H
DSSR
DSSR
ENX2 ENX1
DSS2X
DSS1X
68H R/W 00H
0
69H
W 00H
SPST
69H
R 00H
Momentary AGC Attenuation (if XCR.MAAR = ’1’)
69H
R 00H
XCR
XSR
Data Sheet
PGCR PGCX ERA
0
0
0
PGCR PGCX ERA
0
0
0
179
MAAR
2001-03-12
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Detailed Register Description
MASK1R
MASK1
MP1
6AH R/W 00H
MASK2R
MASK2
MP2
6BH R/W 00H
TFCR
0
0
ALTF
6CH R/W 00H
Reserved
6DH
Reserved
6EH
CCR
0
0
DCA
CSR
0
0
DCA BSYB
Name
7
6
5
DLTF
SBP
4
3
CBADR
6FH
W 00H
CBADR
6FH
R 00H
2
1
0
Reserved
NOP
1
1
1
1
1
ADDR R/WRES
70H7EH
1
1
1
7FH
R FFH
Note: Address 80H-FFH belong to the coefficient RAM (see chapter 4.8.3 and chapter
7.4.14)
Data Sheet
180
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Detailed Register Description
7.1
HDLC Control and C/I Registers
7.1.1
RFIFO - Receive FIFO
7
RFIFO
0
Receive data
RD (00H-1FH)
A read access to any address within the range 00h-1Fh gives access to the “current”
FIFO location selected by an internal pointer which is automatically incremented after
each read access. This allows for the use of efficient “move string” type commands by
the microcontroller.
The RFIFO contains up to 32 bytes of received data.
After an ISTAH.RPF interrupt, a complete data block is available. The block size can be
4, 8, 16, 32 bytes depending on the EXMR.RFBS setting.
After an ISTAH.RME interrupt, the number of received bytes can be obtained by reading
the RBCL register.
7.1.2
XFIFO - Transmit FIFO
7
XFIFO
0
Transmit data
WR (00H-1FH)
A write access to any address within the range 00-1FH gives access to the “current” FIFO
location selected by an internal pointer which is automatically incremented after each
write access. This allows the use of efficient “move string” type commands by the
microcontroller.
Depending on EXMR.XFBS up to 16 or 32 bytes of transmit data can be written to the
XFIFO following an ISTAH.XPR interrupt.
Data Sheet
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Detailed Register Description
7.1.3
ISTAH - Interrupt Status Register HDLC
Value after reset: 10H
7
ISTAH
RME
0
RME
RPF
RFO
XPR
XMR
XDU
0
0
RD (20H)
... Receive Message End
One complete frame of length less than or equal to the defined block size (EXMR.RFBS)
or the last part of a frame of length greater than the defined block size has been received.
The contents are available in the RFIFO. The message length and additional information
may be obtained from RBCH and RBCL and the RSTA register.
RPF
... Receive Pool Full
A data block of a frame longer than the defined block size (EXMR.RFBS) has been
received and is available in the RFIFO. The frame is not yet complete.
RFO
... Receive Frame Overflow
The received data of a frame could not be stored, because the RFIFO is occupied. The
whole message is lost.
This interrupt can be used for statistical purposes and indicates that the microcontroller
does not respond quickly enough to an RPF or RME interrupt (ISTAH).
XPR
... Transmit Pool Ready
A data block of up to the defined block size (EXMR.XFBS) can be written to the XFIFO.
An XPR interrupt will be generated in the following cases:
• after an XTF or XME command as soon as the 16 or 32 respectively bytes in the
XFIFO are available and the frame is not yet complete
• after an XTF together with an XME command is issued, when the whole frame has
been transmitted
XMR
... Transmit Message Repeat
The transmission of the last frame has to be repeated because a collision has been
detected after the 16th/32th data byte of a transmit frame.
XDU
... Transmit Data Underrun
The current transmission of a frame is aborted by transmitting seven ’1’s because the
XFIFO holds no further data. This interrupt occurs whenever the microcontroller has
failed to respond to an XPR interrupt (ISTAH register) quickly enough, after having
initiated a transmission and the message to be transmitted is not yet complete.
Data Sheet
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Detailed Register Description
7.1.4
MASKH - Mask Register HDLC
Value after reset: FCH
7
MASKH
0
RME
RPF
RFO
XPR
XMR
XDU
0
0
WR (20H)
Each interrupt source in the ISTAH register can be selectively masked by setting to ’1’
the corresponding bit in MASK. Masked interrupt status bits are not indicated when
ISTAH is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
7.1.5
STAR - Status Register
Value after reset: 40H
7
STAR
XDOV
0
XDOV XFW
0
0
RACI
0
XACI
0
RD (21H)
... Transmit Data Overflow
More than 16/32 bytes have been written in one pool of the XFIFO, i.e. data has been
overwritten.
XFW
... Transmit FIFO Write Enable
Data can be written in the XFIFO. This bit may be polled instead of (or in addition to)
using the XPR interrupt.
RACI
... Receiver Active Indication
The HDLC receiver is active when RACI = ’1’. This bit may be polled. The RACI bit is set
active after a begin flag has been received and is reset after receiving an abort
sequence.
XACI
... Transmitter Active Indication
The HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The XACI-bit is
active when an XTF-command is issued and the frame has not been completely
transmitted.
Data Sheet
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Detailed Register Description
7.1.6
CMDR - Command Register
Value after reset: 00H
7
CMDR
RMC
0
RMC RRES
0
STI
XTF
0
XME
XRES
WR (21H)
... Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the microcontroller confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFO may be released.
RRES
... Receiver Reset
HDLC receiver is reset, the RFIFO is cleared of any data.
STI
... Start Timer
The hardware timer is started when STI is set to one. The timer may be stopped by a
write to the TIMR register.
XTF
... Transmit Transparent Frame
After having written up to 16 or 32 bytes (EXMR.XFBS) in the XFIFO, the microcontroller
initiates the transmission of a transparent frame by setting this bit to ’1’. Except in the
extended transparent mode the opening flag is automatically added to the message.
XME
... Transmit Message End
By setting this bit to ’1’ the microcontroller indicates that the data block written last in the
XFIFO completes the corresponding frame. Except in the extended transparent mode
the transmission is terminated by appending the CRC and the closing flag sequence to
the data.
XRES
... Transmitter Reset
HDLC transmitter is reset and the XFIFO is cleared of any data. This command can be
used by the microcontroller to abort a frame currently in transmission.
Note: After an XPR interrupt further data has to be written to the XFIFO and the
appropriate Transmit Command (XTF) has to be written to the CMDR register
again to continue transmission, when the current frame is not yet complete (see
also XPR in ISTAH).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically except in the extended mode.
Data Sheet
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Detailed Register Description
7.1.7
MODEH - Mode Register
Value after reset: C0H
7
MODEH
0
MDS2 MDS1 MDS0
MDS2-0
0
RAC
DIM2
DIM1
DIM0 RD/WR (22H)
... Mode Select
Determines the message transfer mode of the HDLC controller, as follows:
MDS2-0
Mode
0
0
0 Reserved
0
0
1 Reserved
0
1
0 Non-Auto
Number of Address Comparison
Address
1.Byte
2.Byte
Bytes
Remark
1
TEI1,TEI2
–
One-byte address
compare.
2
SAP1,SAP2,SAPG
TEI1,TEI2,TEIG Two-byte address
compare.
–
–
No address
compare. All
frames accepted.
SAP1,SAP2,SAPG
–
High-byte address
compare.
–
TEI1,TEI2,TEIG Low-byte address
compare.
mode
0
1
1 Non-Auto
mode
1
0
0 Extended
transparent
mode
1
1
0 Transparent –
mode 0
1
1
1 Transparent > 1
mode 1
1
0
1 Transparent > 1
mode 2
Note: SAP1, SAP2: two programmable address values for the first received address
byte (in the case of an address field longer than 1 byte);
SAPG = fixed value FC / FEH.
TEI1, TEI2: two programmable address values for the second (or the only, in the
case of a one-byte address) received address byte; TEIG = fixed value FFH
Two different methods of the high byte and/or low byte address comparison can
be selected by setting SAP1.MHA and/or SAP2.MLA (see also description of
these bits in chapter 7.1.10 or 7.1.12 respectively)
Data Sheet
185
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Detailed Register Description
RAC
... Receiver Active
The HDLC receiver is activated when this bit is set to ’1’. If it is ’0’ the HDLC data is not
evaluated in the receiver.
DIM2-0
... Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit
enables/disables the collision detection. The DIM1 bit enables/disables the TIC bus
access. The effect of the individual DIM bits is summarized in table 27.
Table 27
IOM®-2 Terminal Modes
DIM0 Characteristics
DIM2
DIM1
0
x
0
Transparent D-channel, the collision detection is disabled
0
x
1
Stop/go bit evaluated for D-channel access handling
0
0
x
Last octet of IOM channel 2 used for TIC bus access
0
1
x
TIC bus access is disabled
1
x
x
Reserved
7.1.8
EXMR- Extended Mode Register
Value after reset: 00H
7
EXMR
XFBS
0
XFBS
RFBS
SRA
XCRC RCRC
0
ITF
RD/WR (23H)
… Transmit FIFO Block Size
0: Block size for the transmit FIFO data is 32 byte
1: Block size for the transmit FIFO data is 16 byte
Note: A change of XFBS will take effect after a transmitter command (CMDR.XME,
CMDR.XRES, CMDR.XTF) has been written
Data Sheet
186
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Detailed Register Description
RFBS
… Receive FIFO Block Size
RFBS
Bit6
RFBS Block Size
Bit5
Receive FIFO
0
0
32 byte
0
1
16 byte
1
0
8 byte
1
1
4 byte
Note: A change of RFBS will take effect after a receiver command (CMDR.RMC,
CMDR.RRES,) has been written
SRA
… Store Receive Address
0: Receive Address is not stored in the RFIFO
1: Receive Address is stored in the RFIFO
XCRC
… Transmit CRC
0: CRC is transmitted
1: CRC is not transmitted
RCRC
… Receive CRC
0: CRC is not stored in the RFIFO
1: CRC is stored in the RFIFO
ITF
… Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0: Idle (continuous ’1’)
1: Flags (sequence of patterns: ‘0111 1110’)
Note: ITF must be set to ’0’ for power down mode.
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ’1’). Otherwise the D-channel on
the line interface can not be accessed
Data Sheet
187
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Detailed Register Description
7.1.9
TIMR - Timer Register
Value after reset: 00H
7
5
TIMR
4
0
CNT
CNT
RD/WR (24H)
VALUE
...
CNT together with VALUE determine the time period T2 after which a TIN interrupt will
be generated in the normal case:
T = CNT x 2.048 sec + T1 with T1 = ( VALUE+1 ) x 0.064 sec
The timer can be started by setting the STI-bit in CMDR and will be stopped when a TIN
interrupt is generated or the TIMR register is written.
Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every expiration of
T1.
VALUE
... Determines the time period T1
T1 = ( VALUE + 1 ) x 0.064 sec
7.1.10
SAP1 - SAPI1 Register
Value after reset: FCH
7
SAP1
SAPI1
0
SAPI1
0
MHA
WR (25H)
... SAPI1 value
Value of the first programmable Service Access Point Identifier (SAPI) according to the
ISDN LAPD protocol.
MHA
... Mask High Address
0: The SAPI address of an incoming frame is compared with SAP1, SAP2, SAPG
1: The SAPI address of an incoming frame is compared with SAP1 and SAPG.
SAP1 can be masked with SAP2 thereby bit positions of SAP1 are not compared
if they are set to ’1’ in SAP2.
Data Sheet
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Detailed Register Description
7.1.11
RBCL - Receive Frame Byte Count Low
Value after reset: 00H
7
RBCL
0
RBC7
RBC7-0
RBC0
RD (26H)
... Receive Byte Count
Eight least significant bits of the total number of bytes in a received message.
7.1.12
SAP2 - SAPI2 Register
Value after reset: FCH
7
0
SAP2
SAPI2
SAPI2
0
MLA
WR (26H)
... SAPI2 value
Value of the second programmable Service Access Point Identifier (SAPI) according to
the ISDN LAPD-protocol.
MLA
0:
1:
... Mask Low Address
The TEI address of an incoming frame is compared with TEI1, TEI2, TEIG
The TEI address of an incoming frame is compared with TEI1 and TEIG.
TEI1 can be masked with TEI2 thereby bit positions of TEI1 are not compared
if they are set to ’1’ in TEI2
7.1.13
RBCH - Receive Frame Byte Count High
Value after reset: 00H.
7
RBCH
OV
0
0
0
0
OV
RBC11
RBC8
RD (27H)
... Overflow
A ’1’ in this bit position indicates a message longer than (212 - 1) = 4095 bytes .
Data Sheet
189
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Detailed Register Description
RBC11-8
... Receive Byte Count
Four most significant bits of the total number of bytes in a received message.
Note: Normally RBCH and RBCL should be read by the microcontroller after an RMEinterrupt in order to determine the number of bytes to be read from the RFIFO, and
the total message length. The contents of the registers are valid only after an RME
or RPF interrupt, and remain so until the frame is acknowledged via the RMC bit
or RRES.
7.1.14
TEI1 - TEI1 Register 1
Value after reset: FFH
7
TEI1
0
TEI1
EA
WR (27H)
TEI1 ... Terminal Endpoint Identifier
In all message transfer modes except in transparent modes 0, 1 and extended
transparent mode, TEI1 is used for address recognition. In the case of a two-byte
address field, it contains the value of the first programmable Terminal Endpoint Identifier
according to the ISDN LAPD-protocol.
In non-auto-modes with one-byte address field, TEI1 is a command address, according
to X.25 LAPB.
EA
... Address field Extension bit
This bit is set to ’1’ according to HDLC/LAPD.
Data Sheet
190
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Detailed Register Description
7.1.15
RSTA - Receive Status Register
Value after reset: 0EH
7
RSTA
VFR
0
VFR
RDO
CRC
RAB
SA1
SA0
C/R
TA
RD (28H)
... Valid Frame
Determines whether a valid frame has been received.
The frame is valid (1) or invalid (0).
A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag,
abort).
RDO
... Receive Data Overflow
If RDO=1, at least one byte of the frame has been lost, because it could not be stored in
RFIFO.
CRC
... CRC Check
The CRC is correct (1) or incorrect (0).
RAB
... Receive Message Aborted
The receive message was aborted by the remote station (1), i.e. a sequence of seven
1’s was detected before a closing flag.
SA1-0
TA
... SAPI Address Identification
... TEI Address Identification
SA1-0 are significant in non-auto-mode with a two-byte address field, as well as in
transparent mode 3. TA is significant in all modes except in transparent modes 0 and 1.
Two programmable SAPI values (SAP1, SAP2) plus a fixed group SAPI (SAPG of value
FC/FEH), and two programmable TEI values (TEI1, TEI2) plus a fixed group TEI (TEIG
of value FFH), are available for address comparison.
The result of the address comparison is given by SA1-0 and TA, as follows:
C/R
... Command/Response
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address)
Note: The contents of RSTA corresponds to the last received HDLC frame; it is
duplicated into RFIFO for every frame (last byte of frame)
Note: If SAP1 and SAP2 contains identical values, the combination 001 will be omitted.
Data Sheet
191
2001-03-12
PSB 21381/2
PSB 21383/4
Detailed Register Description
Address Match with
Number of
Address
Bytes = 1
Number of
address
Bytes=2
7.1.16
SA1
SA0
TA
1st Byte
2nd Byte
x
x
x
x
0
1
TEI2
TEI1
-
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
x
SAP2
SAP2
SAPG
SAPG
SAP1
SAP1
TEIG
TEI2
TEIG
TEI1 or TEI2
TEIG
TEI1
reserved
TEI2 - TEI2 Register
Value after reset: FFH
7
TEI2
TEI2
0
TEI2
EA
WR (28H)
... Terminal Endpoint Identifier
In all message transfer modes except in transparent modes 0, 1 and extended
transparent mode, TEI2 is used for address recognition. In the case of a two-byte
address field, it contains the value of the second programmable Terminal Endpoint
Identifier according of the ISDN LAPD-protocol.
In non-auto-modes with one-byte address field, TEI2 is a response address, according
to X.25 LAPD.
EA
... Address field Extension bit
This bit is to be set to ’1’ according to HDLC/LAPD.
Data Sheet
192
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Detailed Register Description
7.1.17
TMH -Test Mode Register HDLC
Value after reset: 00H
7
TMH
TLP
0
0
0
0
0
0
0
0
TLP
RD/WR (29H)
... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming
from the layer 1 controller will not be forwarded to the layer 2 controller (see chapter
3.7).
Bit 7:1 have always be programmed to ’0’.
Data Sheet
193
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PSB 21383/4
Detailed Register Description
7.1.18
CIR0 - Command/Indication Receive 0
Value after reset: F3H
7
0
CIR0
CODR0
CODR0
CIC0
CIC1
S/G
BAS
RD (2EH)
... C/I Code 0 Receive
Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only
after being the same in two consecutive IOM-frames and the previous code has been
read from CIR0.
AR8
AR10
ARL
DI
RES
TIM
TM1
TM2
1000
1001
1010
1111
0001
0000
0010
0011
CIC0
... C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is set
only when a new code is detected in two consecutive IOM-frames. It is reset by a read
of CIR0.
CIC1
... C/I Code 1 Change
A change in the received Command/Indication code in IOM-channel 1 has been
recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by
a read of CIR0.
S/G
... Stop/Go Bit Monitoring
Indicates the availability of the D-channel on the line interface.
1: Stop
0: Go
BAS
... Bus Access Status
Indicates the state of the TIC-bus:
0: The SCOUT itself occupies the D- and C/I-channel
1: Another device occupies the D- and C/I-channel
Note: The CODR0 bits are updated every time a new C/I-code is detected in two
consecutive IOM-frames. If several consecutive valid new codes are detected and
CIR0 is not read, only the first and the last C/I code is made available in CIR0 at
the first and second read of that register, respectively.
Data Sheet
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Detailed Register Description
7.1.19
CIX0 - Command/Indication Transmit 0
Value after reset: FEH
7
0
CIX0
CODX0
CODX0
TBA2 TBA1 TBA0
BAC
WR (2EH)
... C/I-Code 0 Transmit
Code to be transmitted in the C/I-channel 0.
DR
DR6
RES
TM1
TM2
RSY
PU
0000
0101
0001
0010
0011
0100
0111
AR
ARL
CVR
AIL
AI8
AI10
DC
1000
1010
1011
1110
1100
1101
1111
TBA2-0
... TIC Bus Address
Defines the individual address for the SCOUT on the IOM bus.
This address is used to access the C/I- and D-channel on the IOM interface.
Note: If only one device is liable to transmit in the C/I- and D-channels of the IOM it
should always be given the address value ’7’.
BAC
... Bus Access Control
Only valid if the TIC-bus feature is enabled (MODE:DIM2-0).
If this bit is set, the SCOUT will try to access the TIC-bus to occupy the C/I-channel even
if no D-channel frame has to be transmitted. It should be reset when the access has been
completed to grant a similar access to other devices transmitting in that IOM-channel.
Note: If the TIC-bus address (TBA2-0) is programmed to ’7’ and is not blocked by
another device the SCOUT writes its C/I0 code to IOM continuously.
7.1.20
CIR1 - Command/Indication Receive 1
Value after reset: FCH
7
CIR1
CODR1
0
CODR1
0
0
RD (2FH)
... C/I-Code 1 Receive
Value of the received Command/Indication code.
Data Sheet
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Detailed Register Description
7.1.21
CIX1 - Command/Indication Transmit 1
Value after reset: FEH
7
0
CIX1
CODX1
CODX1
CICW
CI1E
WR (2FH)
... C/I-Code 1 Transmit
Bits 7-2 of C/I-channel 1
CICW
... C/I-Channel Width
CICW selects between a 4 bit (’0’) and 6 bit (’1’) C/I1 channel width
CI1E
... C/I-channel 1 interrupt enable
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled (1) or masked (0).
Data Sheet
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Detailed Register Description
7.2
Transceiver, Interrupt and General Configuration Registers
7.2.1
TR_CONF0 - Transceiver Configuration Register
Value after reset: 01H
7
TR_
CONF0
DIS_TR
0
DIS_
TR
0
EN_
FECV
0
L1SW
0
EXLP
LDD RD/WR (30H)
... Disable Transceiver
0: All layer-1 functions are enabled
1: All layer-1 functions are disabled. All other functional blocks of the SCOUT can still
operate via IOM-2. DCL and FSC pins become input
EN_FECV
... Enable Far-End-Code-Violation
0: normal operation
1: Far-end-code-violation (FECV) function according to ANSI T1.605 enabled. The
receipt of at least one illegal code violation within one multi-frame is indicated by the
C/I indication ’1011’ (CVR) in two consecutive IOM frames
L1SW
... Enable Layer 1 State Machine in Software
0: Layer-1 statemachine of the SCOUT is used
1: Layer-1 statemachine is disabled. The functionality can be realized in software. The
commands can be written into the register TR_CMD and the status read from the
register TR_STA
EXLP
... External Loop
If the local loop is activated with the C/I command ARL or with the LP_A bit of the
TR_CMD register the loop is an
0: internal loop next to the line pins
1: external loop which has to be closed between SR1/2 and SX1/2
Note: The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’.
Data Sheet
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Detailed Register Description
LDD
... Level Detection Discard
0: Clock generation after detection of any signal on the line in the power down state
1: No clock generation after detection of any signal on the line in the power down state
if bit CFS of register MODE1 is set to’1’
Note: If an interrupt is generated by the internal level detect circuitry, the microcontroller
has to set this bit to ’0’ for an activation of the line interface.
7.2.2
TR_CONF1 - Receiver Configuration Register
Value after reset: 07H
7
TR_
CONF1
0
0
EN_SFSC
0
EN_
SFSC
0
0
1
1
1
RD/WR (31H)
... Enable Short FSC
0: No short FSC is generated
1: A short FSC with a pulse length of 1 DCL is generated once per multi-frame (each
7.2.3
TR_CONF2 - Transmitter Configuration Register
Value after reset: 80H
7
TR_
CONF2
DIS_TX
0
DIS_
TX
PDS
0
0
0
0
0
RD/WR (32H)
... Disable Line Driver
The transmitter of the transceiver can be disabled or enabled by setting DIS_TX. This
can be used to make the internal Loop_A transparent (DIS_TX = ’0’) or not
(DIS_TX = ’1’) (see chapter 2.3.10.1).
0: Transmitter is enabled
1: Transmitter is disabled
PDS
... Phase Deviation Selection
Defines the phase deviation of the transmitter (see chapter 2.3.5)
0: The phase deviation is two S-bits - 2 oscillator periods plus analog delay plus delay
of the external circuitry
1: The phase deviation is two S-bits - 4 oscillator periods plus analog delay plus delay
of the external circuitry
Data Sheet
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Detailed Register Description
7.2.4
TR_STA - Transceiver Status Register
Value after reset: 00H
7
TR_
STA
RINF
0
RINF
0
FECV
0
FSYN
0
LD
RD (33H)
... Receiver INFO
00: Received INFO 0
01: Received any signal except INFO 2 or INFO 4
10: Received INFO 2
11: Received INFO 4
FECV
... Far-End-Code-Violation
0: No illegal code violation detected
1: An illegal code violation according to ANSI T1.605 (far-end-code-violation) was
detected
FSYN
... Frame Synchronization State
0: The S/T receiver has not yet synchronized or has lost synchronization
1: The S/T receiver has synchronized
LD
... Level Detected
0: No receive signal has been detected on the line
1: Any receive signal has been detected on the line
Data Sheet
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Detailed Register Description
7.2.5
TR_CMD - Transceiver Command Register
Value after reset: 08H
7
TR_
CMD
0
XINF
DPRIO TDDIS
PD
LP_A
0
RD/WR (34H)
Normally the signals in this register are generated by the layer-1 statemachine. If the
internal layer-1 statemachine is disabled (bit L1SW in TR_CONF = ’1’) this register can
be written by the microcontroller.
XINF
... Transmit INFO
000:
001:
010:
011:
100:
Transmit INFO 0
Reserved
Transmit INFO 1
Transmit INFO 3
Send continuos pulses (Test Mode 2, frequency of the fundamental mode is
96 kHz)
101: Send single pulses (Test Mode 1, frequency of the fundamental mode is 2 kHz)
11x: reserved
DPRIO
... D Channel Priority
0: Priority 8 for D-channel handling
1: Priority 10 for D-channel handling
TDDIS
...Transmit Data Disable
0: The B- and D-channel data is transmitted transparently to the S/T interface if INFO 3
is being transmitted
1: Logical ’1’s are transmitted to the S/T interface in the B- and D-channel data if INFO
3 is being transmitted
PD
... Power Down
0: Transceiver in operational mode
1: Transceiver in power down mode. From the analog part only the level detector is
active. Additionally no clocks are provided and the complete digital part of the
transceiver is inactive if the CFS bit (see chapter 7.2.12) is set to ’1’
Data Sheet
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Detailed Register Description
LP_A
... Loop Analog
The setting of this bit corresponds to the C/I command ARL.
0: Analog loop is open
1: Analog loop is closed internally or externally according to the EXLP bit of the
TR_CONF0 register
7.2.6
SQRR- S/Q-Channel Receive Register
Value after reset: 40H
7
SQRR
0
MSYN MFEN
MSYN
0
0
SQR1 SQR2 SQR3 SQR4
RD (35H)
... Multi-Frame Synchronization State
0: The S/T receiver has not yet synchronized to the multi-frame (see chapter 2.3.3)
1: The S/T receiver has synchronized to the multi-frame
MFEN
... Multi-Frame Enable
Read-back of the MFEN bit of register SQXR
SQR1-4
... Received S Bits
Received S bits of frames 1, 6, 11 and 16 of the multi-frame (see chapter 2.3.3)
7.2.7
SQXR- S/Q-channel Transmit Register
Value after reset: 4FH
7
SQXR
MFEN
0
0
MFEN
0
0
SQX1 SQX2 SQX3 SQX4
WR (35H)
... Multi-Frame Enable
Used to enable multi-framing (see chapter 2.3.3)
0: S/T multi-framing is disabled
1: S/T multi-framing is enabled
SQX1-4
... Q Bits to be transmitted
Q bits to be transmitted at FA bit position of frames 1, 6, 11 and 16 of the multi-frame (see
chapter 2.3.3)
Data Sheet
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Detailed Register Description
7.2.8
ISTATR - Interrupt Status Register Transceiver
Value after reset: 00H
7
ISTATR
0
0
x
x
x
LD
RIC
SQC
SQW
RD (38H)
For all interrupts in the ISTATR register following logical states are defined:
0: Interrupt is not activated
1: Interrupt is activated
x
... Reserved
LD
... Level Detection
Any receive signal has been detected on the line. This bit is active as long as any receive
signal is detected on the line
RIC
... Receiver INFO Change
Any bit of register TR_STA has changed. This bit is reset by reading this register
SQC
... S/Q Channel Change
A change in the received 4-bit S-channel (contents of one multi-frame, see
chapter 2.3.3) has been detected. The new code can be read out from the SQRx bits of
register SQRR within the next 18 S-frames (4.5 ms). This bit is reset by a read access
to the SQRR register
SQW
... S/Q Channel Writable
The S/Q channel data for the next multi-frame is writable (see chapter 2.3.3).
The register for the Q (S) bits to be transmitted (having received) has to be written (read)
within the next 18 multi-frames (4.5 ms). This bit is reset by writing register SQXR
Data Sheet
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Detailed Register Description
7.2.9
MASKTR - Mask Transceiver Interrupt
Value after reset: 7FH
7
MASKTR
0
0
1
1
1
LD
RIC
SQC
SQW RD/WR (39H)
0: The corresponding transceiver interrupt is enabled
1: The corresponding transceiver interrupt is disabled
Data Sheet
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Detailed Register Description
7.2.10
ISTA - Interrupt Status Register
Value after reset: 01H
7
ISTA
0
0
ST
CIC
TIN
WOV TRAN MOS HDLC
RD (3CH)
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not activated
1: Interrupt is activated
ST
... Synchronous Transfer
When programmed (STI register), this interrupt is generated to enable the
microcontroller to lock on to the IOM timing, for synchronous transfers.
CIC
... C/I Channel Change
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can
be read from CIR0 or CIR1.
TIN
... Timer Interrupt
The internal timer and repeat counter has expired (see TIMR register).
WOV
... Watchdog Timer Overflow
Used only if terminal specific functions are enabled (MODE.TSF=1).
Signals the expiration of the watchdog timer, which means that the microcontroller has
failed to set the watchdog timer control bits WTC1 and WTC2 (ADF1 register) in the
correct manner. A reset pulse has been generated by the SCOUT.
TRAN
... Transceiver Interrupt
An interrupt originated in the transceiver interrupt status register (ISTATR) has been
recognized.
MOS
... MONITOR Status
A change in the MONITOR Status Register (MOSR) has occurred.
HDLC
... HDLC Interrupt
An interrupt originated in the HDLC interrupt sources has been recognized.
Note: A read of the ISTA register clears only the TIN and WOV interrupts. The other
interrupts are cleared by reading the corresponding status register
Data Sheet
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Detailed Register Description
7.2.11
MASK - Mask Register
Value after reset: 7FH
7
MASK
0
0
ST
CIC
TIN
WOV TRAN MOS HDLC
WR (3CH)
For the MASK register following logical states are applied:
0: Interrupt is not masked
1: Interrupt is masked
Each interrupt source in the ISTA register can be selectively masked by setting to ’1’ the
corresponding bit in MASK. Masked interrupt status bits are not indicated when ISTA is
read. Instead, they remain internally stored and pending, until the mask bit is reset to ’0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
mask bit in MASK is active, but no interrupt is generated.
7.2.12
MODE1 - Mode1 Register
Value after reset: 00H
7
MODE1
0
MCLK
MCLK
0
WTC1 WTC2
CFS
RSS2 RSS1 RD/WR (3DH)
... Master Clock Frequency
The Master Clock Frequency bits control the microcontroller clock output corresponding
to the following table.
Bit 7 Bit 6 MCLK frequency
with
MODE1.CDS = ’0’
0
0
3.84 MHz
0
1
0.96 MHz
1
0
7.68 MHz
1
1
disabled
Data Sheet
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Detailed Register Description
WTC1, 2
... Watchdog Timer Control 1, 2
If the watchdog timer is enabled (RSS = ’11’) the microcontroller has to program the
WTC1 and WTC2 bit within each time period of 128 ms in the following sequence:
1.
2.
WTC1
WTC2
1
0
0
1
(See chapter 6.1).
CFS
... Configuration Select
This bit determines clock relations and recovery on the line and IOM interfaces
0: The IOM interface clock and frame signals are always active,
"Power Down" state included.
The states "Power Down" and "Power Up" are thus functionally identical except for
the indication: PD = 1111 and PU = 0111.
With the C/I command Timing (TIM) the microcontroller can enforce the
"Power Up" state.
With C/I command Deactivation Indication (DI) the "Power Down" state is
reached again.
It is also possible to activate the line Interface directly with the
C/I command Activate Request (AR) without the TIM command.
1: The IOM interface clock and frame signals are normally inactive ("Power Down").
For activating the IOM-2 clocks the "Power Up" state can be induced by software
(SPU-bit in SPCR register) or by resetting again CFS.
After that the line interface can be activated with the C/I command Activate Request
(AR ). The "Power Down" state can be reached again with the C/I command
Deactivation Indication (DI).
Note:After reset the IOM interface is always active. To reach the "Power Down" state the
CFS-bit has to be set.
Data Sheet
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Detailed Register Description
.RSS2, RSS1
... Reset Source Selection 2,1
The reset sources and the SDS2 functionality for the RSTO/SDS2 output pin can be
selected according to the table below.
RSS2 RSS1
Bit 1 Bit 0
C/I Code
Change
EAW
Watchdog
Timer
SDS2
Functionality
0
0
--
--
--
--
0
1
--
--
--
x
1
0
x
x
--
--
1
1
--
--
x
--
For RSS = ’00’ no reset is generated at pin RSTO/SDS2.
For RSS = ’01’ a serial data strobe is output at pin RSTO/SDS2 (see chapter 2.2.3).
For RSS = ’10’ an External Awake or a change in the downstream C/I0 channel
generates a reset of 125 µs ≤ t ≤ 250 µs pulse length at the pin RSTO
(see chapter 6.1).
For RSS = ’11’ the watchdog function is enabled (see chapter 6.1).
A hardware reset is always output at pin RSTO/SDS2.
After a reset pulse and the corresponding interrupt (WOV or CIC) have been generated
by the SCOUT the actual reset source can be read from the ISTA.
Data Sheet
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Detailed Register Description
7.2.13
MODE2 - Mode2 Register
Value after reset: 00H
7
MODE2
0
0
DREF
0
0
0
0
DREF AMOD PPSDX RD/WR (3EH)
... Disable References
0: Reference voltages and currents are enabled.
1: Reference voltages and currents are disabled.
AMOD
... Address Mode
Selection between direct and indirect register access of the parallel microcontroller
interface.
0: Indirect address mode is selected. The address line A0 is used to select between
address (A0 = ’0’) and data (A0 = ’1’) register
1: Direct address mode is selected. The address is applied to the address bus (A0-A7)
PPSDX
... Push/Pull Output for SDX
0: The SDX pin has open drain characteristic
1: The SDX pin has push/pull characteristic
7.2.14
ID - Identification Register
Value after reset: 0xH
7
ID
DESIGN
0
0
0
DESIGN
RD (3FH)
... Design Number
The design number (DESIGN) allows to identify different hardware designs of the
SCOUT by software.
000000: SCOUT-S V1.3 PSB 21381/2
000001: SCOUT-SX V1.3 PSB 21383/4
Data Sheet
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Detailed Register Description
7.2.15
SRES - Software Reset Register
Value after reset: 00H
7
SRES
0
0
RES_xx
0
RES_ RES_ RES_ RES_ RES_ RES_
CPLL MON HDLC IOM
TR
CO
WR (3FH)
... Reset_xx
0: Deactivates the reset of the functional block xx
1: Activates the reset of the functional block xx
The reset state is activated as long as the bit is set to ’1’
Meaning of xx:
CPLL:
MON:
HDLC:
IOM:
TR:
CO:
Codec PLL
Monitorhandler
HDLC controller,
IOM Handler,
Transceiver,
Codec
7.3
IOM-2 and MONITOR Handler
7.3.1
CDAxy - Controller Data Access Register xy
Value after reset: See table below
7
CDAxy
0
Controller Data Access Register
RD/WR
(40H-43H)
Data register CDAxy which can be accessed from the controller.
Register
Value after Reset
Register Address
CDA10
FFH
40H
CDA11
FFH
41H
CDA20
FFH
42H
CDA21
FFH
43H
Data Sheet
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Detailed Register Description
7.3.2
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
Value after reset: See table below
7
XXX_
TSDPxy
DPS
0
0
0
0
TSS
Register
Value after Reset
Register Address
CDA_TSDP10
00H ( = output on B1-DD)
44H
CDA_TSDP11
01H ( = output on B2-DD)
45H
CDA_TSDP20
80H ( = output on B1-DU)
46H
CDA_TSDP21
81H ( = output on B2-DU)
47H
CO_TSDP10
80H ( = output on B1-DU)
48H
CO_TSDP11
81H ( = output on B2-DU)
49H
CO_TSDP20
81H ( = output on B2-DU)
4AH
CO_TSDP21
85H ( = output on IC2-DU)
4BH
TR_TSDP_B1
00H ( = output on B1-DD)
4CH
TR_TSDP_B2
01H ( = output on B2-DD)
4DH
RD/WR
(44H-4DH)
This register determines the time slots and the data ports on the IOM-2 Interface for the
data channels xy of the functional units XXX (Controller Data Access (CDA), Codec (CO)
and Transceiver (TR)).
DPS
... Data Port Selection
0: The data channel xy of the functional unit XXX is output on DD.
The data channel xy of the functional unit XXX is input from DU.
1: The data channel xy of the functional unit XXX is output on DU.
The data channel xy of the functional unit XXX is input from DD.
Note: For the CDA (controller data access) data the input is determined by the
CDA_CRx.SWAP bit. If SWAP = ’0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ’1’ the input from CDAx0 is vice versa
to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output
setting of CDAx0. See controller data access description in chapter 2.2.2.1
Data Sheet
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Detailed Register Description
TSS
... Timeslot Selection
Selects one of the 12 timeslots from 0...11 on the IOM-2 interface for the data channels.
7.3.3
CDAx_CR - Control Register Controller Data Access CH1x
Value after reset: See table below
7
0
CDAx_
CR
0
Register
Value after Reset
Register Address
CDA1_CR
00H
4EH
CDA2_CR
00H
4FH
EN_TBM
0
EN_
TBM
EN_I1 EN_I0 EN_O1 EN_O0 SWAP
RD/WR
(4EH-4FH)
... Enable TIC Bus Monitoring
0: The TIC bus monitoring is disabled
1: The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register
must be set to 08H for monitoring from DU or 88H for monitoring from DD respectively.
EN_I1, EN_I0
... Enable Input CDAx0, CDAx1
0: The input of the CDAx0, CDAx1 register is disabled
1: The input of the CDAx0, CDAx1 register is enabled
EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1
0: The output of the CDAx0, CDAx1 register is disabled
1: The output of the CDAx0, CDAx1 register is enabled
SWAP
... Swap Inputs
0: The time slot and data port for the input of the CDAxy register is defined by its own
TSDPxy register. The data port for the CDAxy input is vice versa to the output setting
for CDAxy.
1: The input (time slot and data port) of the CDAx0 is defined by the TSDP register of
CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data
port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port
for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition
for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to
CDAx0. The outputs are not affected by the SWAP bit.
Data Sheet
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Detailed Register Description
7.3.4
CO_CR - Control Register Codec Data
Value after reset: 00H
7
CO_CR
0
0
EN21
EN20
EN11
EN10
0
0
0
EN
21
EN
20
EN
11
EN
10
RD/WR (50H)
0
RD/WR (51H)
... Enable codec channel 21
... Enable codec channel 20
... Enable codec channel 11
... Enable codec channel 10
0: The codec data channel xy is disabled
1: The codec data channel xy is enabled
7.3.5
TR_CR - Control Register Transceiver Data
Value after reset: 3EH
7
TR_CR
EN_D
EN_B2R
EN_B1R
EN_B2X
EN_B1X
0
0
0
EN_
D
EN_
B2R
EN_
B1R
EN_
B2X
EN_
B1X
... Enable D-Channel Data
... Enable B2 Data received from IOM
... Enable B1 Data received from IOM
... Enable B2 Data to be transmitted to IOM
... Enable B1 Data to be transmitted to IOM
0: The transceiver data _xxx is disabled
1: The transceiver data _xxx is enabled
Data Sheet
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Detailed Register Description
7.3.6
HCI_CR - Control Register for HDLC and CI1 Data
Value after reset: A0H
7
HCI_CR
0
DPS_
CI1
DPS_CI1
EN_
CI1
EN_
D
EN_
B2H
EN_
B1H
0
0
0
RD/WR (52H)
... Data Port Selection CI1 Data
0: The CI1 data is output on DD and input from DU
1: The CI1 data is output on DU and input from DD
EN_CI1
EN_D
EN_B2H
EN_B1H
... Enable CI1 Data
... Enable D-Channel Data
... Enable HDLC B2 Data
... Enable HDLC B1 Data
0: The HDLC (D, B1, B2) and CI1 data is disabled
1: The HDLC (D, B1, B2) and CI1 data is enabled
7.3.7
MON_CR - Control Register Monitor Data
Value after reset: 40H
7
MON_CR
DPS
0
DPS
EN_
MON
0
0
0
0
MCS
RD/WR (53H)
... Data Port Selection
0: The Monitor data is output on DD and input from DU
1: The Monitor data is output on DU and input from DD
EN_MON
... Enable Output
0: The Monitor data input and output is disabled
1: The Monitor data input and output is enabled
MCS
... MONITOR Channel Selection
00: The MONITOR data is output on MON0
01: The MONITOR data is output on MON1
10: The MONITOR data is output on MON2
11: Not defined
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Detailed Register Description
7.3.8
SDSx_CR - Control Register Serial Data Strobe x
Value after reset: 00H
7
0
SDSx_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
0
TSS
Register
Value after Reset
Register Address
SDS1_CR
00H
54H
SDS2_CR
00H
55FH
RD/WR
(54H-55H)
Note: The SDS2_CR register is only applicable if a serial data strobe functionality is
selected (MODE1.RSS = ’01’) for the pin RSTO/SDS2
ENS_TSS
ENS_TSS+1
... Enable Serial Data Strobe of timeslot TS
... Enable Serial Data Strobe of timeslot TS+1
0: The serial data strobe or bit clock on SDSx for TS, TS+1 is disabled
1: The serial data strobe or bit clock on SDSx for TS, TS+1 is enabled
ENS_TSS+3
... Enable Serial Data Strobe of timeslot TS+3 (D-Channel)
0: The serial data strobe or bit clock on SDSx for the D-channel (bit7, 6) of TS+3 is
disabled
1: The serial data strobe or bit clock on SDSx for the D-channel (bit7, 6) of TS+3 is
enabled
TSS
... Timeslot Selection
Selects one of 12 timeslots on the IOM-2 interface (with respect to FSC) during which
SDSx is active. The data strobe signal allows standard data devices to access a
programmable channel.
Data Sheet
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Detailed Register Description
7.3.9
IOM_CR - Control Register IOM Data
Value after reset: 00H
7
IOM_CR
SPU
0
SPU
0
0
TIC_
DIS
EN_
BCL
CLKM DIS_
OD
DIS_ RD/WR (56H)
IOM
... Software Power UP
0: The DU line is normally used for transmitting data
1: Setting this bit to ’1’ will pull the DU line to low. This will enforce connected layer 1
devices to deliver IOM-clocking.
After a subsequent CIC-interrupt (C/I-code change; ISTA) and reception of the C/I-code
”PU” (Power Up indication in TE-mode) the microcontroller writes an AR or TIM
command as C/I-code in the CIX0-register, resets the SPU bit and wait for the following
CIC-interrupt.
TIC_DIS
... TIC Bus Disable
0: The last octet of the last IOM time slot (TS 11) is used as TIC bus
1: The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used
as every time slot.
EN_BCL
... Enable Bit Clock BCL
0: The BCL clock is disabled
1: The BCL clock is enabled
CLKM
... Clock Mode
If the transceiver is disabled (DIS_TR = ’1’) the DCL from the IOM-2 interface is an input.
With
0: A double clock per bit is expected
1: A single clock per bit is expected
DIS_OD
... Open Drain
0: IOM outputs are open drain driver
1: IOM outputs are push pull driver
Data Sheet
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Detailed Register Description
DIS_IOM
... Disable IOM
DIS_IOM should be set to ’1’ if external devices connected to the IOM interface should
be “disconnected“ e.g. for power saving purposes or for not disturbing the internal IOM
connection between layer 1 and layer 2. However, the SCOUT internal operation
between transceiver, B-channel and D-channel controller is independent of the DIS_IOM
bit.
0: The IOM interface is enabled
1: The IOM interface is disabled (high impedance)
7.3.10
MCDA - Monitoring CDA Bits
Value after reset: FFH
7
MCDA
0
MCDA21
Bit7
MCDAxy
Bit6
MCDA20
Bit7
MCDA11
Bit6
Bit7
Bit6
MCDA10
Bit7
RD (57H)
Bit6
... Monitoring CDAxy Bits
Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register.
This can be used for monitoring the D-channel bits on DU and DD and the ’Echo bits’ on
the TIC bus with the same register
Data Sheet
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Detailed Register Description
7.3.11
STI - Synchronous Transfer Interrupt
Value after reset: 00H
7
STI
0
STOV STOV STOV STOV
21
20
11
10
STI
21
STI
20
STI
11
STI
10
RD (58H)
For all interrupts in the STI register following logical states are applied:
0: Interrupt is not activated
1: Interrupt is activated
STOVxy
... Synchronous Transfer Overflow Interrupt
Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has
not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one
(for DPS=’0’) or zero (for DPS=’1’) BCL clocks before the time slot which is selected for
the STOV.
STIxy
... Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the Synchronous
Transfer Interrupt STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock
after the selected time slot (TSDPxy.TSS).
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
receive/transmit operations. One BCL clock is equivalent to two DCL clocks.
Data Sheet
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Detailed Register Description
7.3.12
ASTI - Acknowledge Synchronous Transfer Interrupt
Value after reset: 00H
7
ASTI
0
0
ACKxy
0
0
0
ACK
21
ACK
20
ACK
11
ACK
10
WR (58H)
... Acknowledge Synchronous Transfer Interrupt
After a STIxy interrupt the microcontroller has to acknowledge the interrupt by setting the
corresponding ACKxy bit.
0: No activity is initiated
1: Sets the acknowledge bit ACKxy for a STIxy interrupt
7.3.13
MSTI - Mask Synchronous Transfer Interrupt
Value after reset: FFH
7
MSTI
0
STOV STOV STOV STOV
21
20
11
10
STI
21
STI
20
STI
11
STI
10
RD/WR (59H)
For the MSTI register following logical states are applied:
0: Interrupt is not masked
1: Interrupt is masked
STOVxy
... Synchronous Transfer Overflow for STIxy
By masking the STOV bits the number and time of the STOV interrupts for a certain
enabled STIxy interrupt can be controlled. For an enabled STIxy the own STOVxy is
generated when the STOVxy is enabled (MSTI.STIxy and MSTI.STOVxy = ’0’).
Additionally all other STOV interrupts of which the corresponding STI is disabled
(MSTI.STI = ’1’ and MSTI.STOV = ’0’) are generated.
STIxy
... Synchronous Transfer Interrupt xy
The STIxy interrupts can be masked by setting the corresponding mask bit to ’1’. For a
masked STIxy no STOV interrupt is generated.
Data Sheet
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Detailed Register Description
7.3.14
SDS_CONF - Configuration Register for Serial Data Strobes
Value after reset: 00H
7
SDS_
CONF
0
0
SDSx_BCL
0
0
0
0
0
SDS2_ SDS1_ RD/WR (5AH)
BCL
BCL
... Enable IOM Bit Clock for SDSx
0: The serial data strobe is generated in the programmed timeslot (see chapter 7.3.8).
1: The IOM bit clock is generated in the programmed timeslot (see chapter 7.3.8 and
2.2.3).
7.3.15
MOR - MONITOR Receive Channel
Value after reset: 00H
7
0
RD (5CH)
MOR
Contains the MONITOR data received in the IOM-2 MONITOR channel according to the
MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by setting
the monitor channel select bit MON_CR.MCS.
7.3.16
MOX - MONITOR Transmit Channel
Value after reset: FFH
7
0
MOX
WR (5CH)
Contains the MONITOR data to be transmitted in IOM-2 MONITOR channel according
to the MONITOR channel protocol.The MONITOR channel (0,1,2) can be selected by
setting the monitor channel select bit MON_CR.MCS
Data Sheet
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Detailed Register Description
7.3.17
MOSR - MONITOR Interrupt Status Register
Value after reset: 00H
7
MOSR
0
MDR
MER
MDA
MAB
0
0
0
MDR
... MONITOR channel Data Received
MER
... MONITOR channel End of Reception
MDA
... MONITOR channel Data Acknowledged
0
RD (5DH)
The remote end has acknowledged the MONITOR byte being transmitted.
MAB
Data Sheet
... MONITOR channel Data Abort
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Detailed Register Description
7.3.18
MOCR - MONITOR Control Register
Value after reset: 00H
7
MOCR
MRE
0
MRE
MRC
MIE
MXC
0
0
0
0
RD/WR (5EH)
... MONITOR Receive Interrupt Enable
0: MONITOR interrupt status MDR generation is masked
1: MONITOR interrupt status MDR generation is enabled
MRC
... MR Bit Control:
Determines the value of the MR bit:
0: MR is always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of
a packet (if MRE = 1).
1: MR is internally controlled according to the MONITOR channel protocol. In addition,
the MDR interrupt is enabled for all received bytes according to the MONITOR
channel protocol (if MRE = 1).
MIE
... MONITOR Interrupt Enable
MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0).
MXC
... MX Bit Control
Determines the value of the MX bit:
0: The MX bit is always ’1’.
1: The MX bit is internally controlled according to the MONITOR channel
protocol.
Data Sheet
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Detailed Register Description
7.3.19
MSTA - MONITOR Status Register
Value after reset: 00H
7
MSTA
0
0
MAC
0
0
0
0
MAC
0
TOUT
RD (5FH)
... MONITOR Transmit Channel Active
The data transmission in the MONITOR channel is in progress
TOUT
... Time-Out
Read-back value of the TOUT bit
7.3.20
MCONF - MONITOR Configuration Register
Value after reset: 00H
7
MCONF
TOUT
0
0
0
0
0
0
0
0
TOUT
WR (5FH)
... Time-Out
0: The monitor time-out function is disabled
1: The monitor time-out function is enabled
Data Sheet
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Detailed Register Description
7.4
Codec Configuration Registers
7.4.1
General Configuration Register (GCR)
Value after reset: 00H
7
GCR
SP
0
SP
AGCX AGCR MGCR CME
PU
ATT2R ATT1R
RD/WR (60H)
... Speakerphone
0: Speakerphone support disabled
1: Speakerphone support enabled
AGCX
... Automatic Gain Control Transmit
0: Automatic gain control disabled
1: Automatic gain control enabled; only if speakerphone support is enabled (SP=1)
AGCR
... Automatic Gain Control Receive
0: Automatic gain control disabled
1: Automatic gain control enabled; only if speakerphone support is enabled (SP=1)
MGCR
... Modified Gain Control Receive
0: AGCR starts regulation up and down after speech was detected two times
1: AGCR starts regulation down of the attenuation immediately, regulation up is done
after speech was detected two times
0CME
... Controlled Monitoring Enable (GCR.SP =’1’)
0: Controlled monitoring disabled
1: Controlled monitoring enabled. ALS attenuation is fixed to the value determined by
the ATCR.CMAS setting
Note: If transmit speech is detected and LSC > -9.5 dB, the ALS programming is fixed
to -9.5 dB
PU
... Power Up
0: The codec is in standby mode (power-down); all registers and the coefficient RAM
contents are saved and all interface functions are available
1: The codec is in normal operation mode (power-up)
Data Sheet
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Detailed Register Description
ATT2R
ATT1R
... Attenuation of the Receive Channel related to Transmit Channel 2
... Attenuation of the Receive Channel related to Transmit Channel 1
0: Attenuation value for the conferences loop is 0 dB
1: Attenuation value for the conferences loop loaded from CRAM
7.4.2
Programmable Filter Configuration Register (PFCR)
Value after reset: 00H
7
PFCR
GX
GX
GR
0
GZ
FX
PGZ
FR
DHPR DHPX
RD/WR (61H)
... Transmit Gain
0: Gain set to 0 dB
1: Gain coefficients loaded from CRAM
GR
... Receive Gain
0: Gain set to 0 dB
1: Gain coefficients loaded from CRAM
GZ
... Sidetone Gain
0: Gain set to – ∞ dB
1: Gain coefficients loaded from CRAM
FX
... Transmit Frequency Correction Filter
0: Filter is bypassed
1: Filter coefficients loaded from CRAM
PGZ
... Position Sidetone Gain
0: Tap of the sidetone signal is before the AGC/GHX stage
1: Tap of the sidetone signal is after the AGC/GHX stage
FR
... Receive Frequency Correction Filter
0: Filter is bypassed
1: Filter coefficients loaded from CRAM
DHPR
... Disable High-Pass Receive (50/60 Hz filter)
0: Filter enabled
1: Filter disabled
Data Sheet
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Detailed Register Description
DHPX
... Disable High-Pass Transmit (50/60 Hz filter)
0: Filter enabled
1: Filter disabled
7.4.3
Tone Generator Configuration Register (TGCR)
Value after reset: 00H
7
TGCR
ET
ET
DT
0
ETF
PT
SEQ
TM
SM
SQTR
RD/WR (62H)
... Enable Tone Generator
0: Tone generator is disabled
1: Tone generator is enabled; frequency and gain coefficients loaded from CRAM
DT
... Dual Tone Mode
0: Dual tone mode is disabled
1: Dual tone mode is enabled; the output of signal generator FD is added to the tone
signal which is determined by TM and SEQ;
dual tone mode is only available if TGSR.DTMF =’0’
ETF
... Enable Tone Filter
0: Tone filter is by-passed
1: Tone filter is enabled; filter coefficients loaded from CRAM
PT
... Pulsed Tone
0: Pulsed tone is disabled
1: Pulsed tone is enabled; time coefficients loaded from CRAM
SEQ
... Sequence Generator
0: Sequence generator is disabled, a continuous tone signal is generated
1: Sequence generator is enabled; time coefficients loaded from CRAM
TM
... Tone Mode
0: Two-tone sequence is activated when sequence generator is enabled with SEQ =’1’
otherwise a continuous signal (F1, G1) is generated
1: Three-tone sequence is activated when sequence generator is enabled with SEQ =’1’
otherwise a continuous signal (F2, G2) is generated;
three-tone sequence is only available if TGSR.DTMF =’0’
Data Sheet
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Detailed Register Description
SM
... Stop Mode
0: Automatic stop mode is disabled
1: Automatic stop mode is enabled; two and three tone ring gets turned off after the
sequence is completed
SQTR
... Square/Trapezoid Waveform
0: Trapezoid shaped signal is enabled;
only available if tone ringing via loudspeaker is disabled with TGSR.TRL =’0’
1: Square-wave signal is enabled
7.4.4
Tone Generator Switch Register (TGSR)
Value after reset: 00H
7
TGSR
TRL
0
TRL
0
0
TRR DTMF TRX
0
0
RD/WR (63H)
... Tone Ringing via Loudspeaker
0: Ringing signal is not output directly to the loudspeaker pins
1: Ringing signal (square) is output directly to the loudspeaker pins LSP/LSN
TRR
... Tone Ringing Receive
0: Tone signal for receive direction is disabled
1: Tone signal for receive direction is enabled
DTMF
... DTMF Mode
0: DTMF mode is disabled
1: DTMF mode is enabled
TRX
... Tone Ringing Transmit
0: Tone generator for transmit direction is disabled
1: Tone generator for transmit direction is enabled
Data Sheet
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Detailed Register Description
7.4.5
AFE Configuration Register (ACR)
Value after reset: 00H
7
ACR
SEM
0
0
0
0
SEM DHOP DHON DLSP DLSN
RD/WR (64H)
... Single Ended Mode (only effective if DLSP and/or DLSN=’1’)
0: LSP and/or LSN amplifiers are in power down and grounded internally for single
ended mode
1: LSP and/or LSN amplifiers are in power down (high impedance)
DHOP
... Disable HOP Amplifier
0: HOP amplifier in normal mode
1: Disable HOP amplifier (power down, output high impedance)
DHON
... Disable HON Amplifier
0: HON amplifier in normal mode
1: Disable HON amplifier (power down, output high impedance)
DLSP
... Disable LSP Amplifier
0: LSP amplifier in normal mode
1: Disable LSP amplifier controlled by SEM setting
DLSN
... Disable LSN Amplifier
0: LSN amplifier in normal mode
1: Disable LSN amplifier controlled by SEM setting
Data Sheet
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Detailed Register Description
7.4.6
AFE Transmit Configuration Register (ATCR)
Value after reset: 00H
7
ATCR
0
MIC
MIC
0
CMAS
AIMX
RD/WR (65H)
... Microphone Amplifier (AMI) Control
Bit 7 6
5
4
Selected Mode
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AMI and PREFI is in power-down mode
0 dB
amplification
6 dB
amplification
12 dB amplification
18 dB amplification
24 dB amplification
30 dB amplification
36 dB amplification
42 dB amplification
bypass mode, reserved for internal tests
CMAS
0
0
0
0
1
1
1
1
0
1
... Controlled Monitoring Attenuation Select
0: In controlled monitoring mode (GCR.CME = ’1’)
the lower ALS setting is -9.5dB
1: In controlled monitoring mode (GCR.CME = ’1’)
the lower ALS setting is -21.5dB
AIMX
... Analog Input Multiplexer
Bit 1 0
0
0
1
1
Data Sheet
0
1
0
1
Selected Input
AMI is connected to the pins MIP1/MIN1 (differential input)
AMI is connected to the pins MIP2/MIN2 (differential input)
AMI is connected to the pin AXI (single-ended input)
not used
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Detailed Register Description
7.4.7
AFE Receive Configuration Register (ARCR)
Value after reset: 00H
7
ARCR
HOC
HOC
LSC
RD/WR (66H)
... Handset Output Amplifier (AHO) Control
Bit 3 2
1
0
Selected Mode
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
AHO is in power-down mode
2.5 dB amplification
– 0.5 dB amplification
– 3.5 dB amplification
– 6.5 dB amplification
– 9.5 dB amplification
– 12.5 dB amplification
– 15.5 dB amplification
– 18.5 dB amplification
– 21.5 dB amplification
bypass mode, reserved for internal tests only
LSC
0
0
0
0
1
1
1
1
0
0
1
... Loudspeaker Amplifier (ALS) Control
Bit 3 2
1
0
Selected Mode
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ALS is in power-down mode
11.5 dB amplification
8.5 dB amplification
5.5 dB amplification
2.5 dB amplification
– 0.5 dB amplification
– 3.5 dB amplification
– 6.5 dB amplification
– 9.5 dB amplification
– 12.5 dB amplification
– 15.5 dB amplification
– 18.5 dB amplification
– 21.5 dB amplification
– 24.5 dB amplification (only for TGSR.TRL = ’1’)
– 27.5 dB amplification (only for TGSR.TRL = ’1’)
bypass mode, reserved for internal tests only
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Data Sheet
0
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Detailed Register Description
7.4.8
Data Format Register (DFR)
Value after reset: 00H
7
DFR
DF2R
DFxR
0
DF2X
DF1R
DF1X
RD/WR (67H)
... Data Format CHx Receive (CHxR)
Bit
7,3
Bit Data Format CHxR Codec Voice Data Register
6,2
0
0
PCM A-Law
COx0R
0
1
PCM µ-Law
COx0R
1
0
8-bit linear mode
COx0R
(|sign 15...9| of the internal 16 bit word)
1
1
16-bit linear mode
COx0R (MSB)
(|sign 15...9| of the internal 16 bit word)
COx1R (LSB)
(|8...1| of the internal 16 bit word)
DFxX
... Data Format CHx Transmit (CHxX)
Bit
5,1
Bit Data Format CHxR Codec Data Register
4,0
0
0
PCM A-Law
COx0X
0
1
PCM µ-Law
COx0X
1
0
8-bit linear mode
COx0X
(|sign 15...9| of the internal 16 bit word)
1
1
16-bit linear mode
COx0X (MSB)
(|sign 15...9| of the internal 16 bit word)
COx1X (LSB)
(|8...1| of the internal 16 bit word)
The small letter ’x’ is a variable for channel 2 or 1.
Data Sheet
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Detailed Register Description
7.4.9
Data Source Selection Register (DSSR)
Value after reset: 00H
7
DSSR
0
DSSR
DSSR
ENX2 ENX1
DSS2X
DSS1X
RD/WR (68H)
... Data Source Selection Receive
Bit7 6
0
0
idle
0
1
CH1R
1
0
CH2R
1
1
CH1R+CH2R
ENX2
ENX1
... Enable Transmit CH2
... Enable Transmit CH1
0: Codec transmit data in CH2/CH1 disabled
1: Codec transmit data in CH2/CH1 enabled
DSS2X
... Data Source Selection CH2X
Bit3 2
0
0
idle code is transmitted
0
1
XDAT is transmitted
1
0
CH1R
1
1
XDAT+ CH1R is transmitted
DSS1X
... Data Source Selection CH1X
Bit1 0
Data Sheet
0
0
idle code is transmitted
0
1
XDAT is transmitted
1
0
CH2R
1
1
XDAT+ CH2R is transmitted
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Detailed Register Description
7.4.10
Extended Configuration (XCR) and Status (XSR) Register
Extended Status Register (XSR)
If MAAR in the XCR register is set to ’0’:
Value after reset: 00H
7
XSR
0
PGCR PGCX ERA
PGCR
0
0
0
SPST
RD (69H)
... Position of Gain Control Receive (see figure 73)
Read-back of the programmed value
PGCX
... Position of Gain Control Transmit (see figure 73)
Read-back of the programmed value
ERA
... Enhanced Reverse Attenuation
Read-back of the programmed value
SPST
... Speakerphone State
Bit 1 0
Description
0
0
Speakerphone is in receive mode
0
1
Speakerphone is in idle mode (reached via receive mode)
1
0
Speakerphone is in transmit mode
1
1
Speakerphone is in idle mode (reached via transmit mode)
If MAAR in the XCR register is set to ’1’:
Value after reset: 00H
7
XSR
0
RD (69H)
Value of the Momentary AGC Attenuation
Extended Configuration Register (XCR)
Value after reset: 00H
7
XCR
Data Sheet
PGCR PGCX ERA
0
0
0
232
0
0
MAAR
WR (69H)
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Detailed Register Description
PGCR
... Position of Gain Control Receive (see figure 73)
0: In front of the speech detector
1: Behind the speech detector
PGCX
... Position of Gain Control Transmit (see figure 73)
0: Behind the speech detector
1: In front of the speech detector
ERA
... Enhanced Reverse Attenuation
0: Standard reverse attenuation in receive direction
1: Enhanced reverse attenuation in receive direction
MAAR
... Monitoring AGC Attenuation Receive
0: The monitoring of the AGC attenuation receive in the XSR register is disabled. XSR
contains the read-back values of XCR register (bit 7:2) and the speakerphone states.
1: The monitoring of the AGC attenuation receive in the XSR register is enabled. The
momentary AGC attenuation can be accessed directly by the microcontroller via XSR
register.
Data Sheet
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Detailed Register Description
7.4.11
Mask Channel x Register (MASKxR)
Value after reset: 00H
7
0
MASKxR
MASKx
MPx
RD/WR
channel 1: 6AH
channel 2: 6BH
MASKx
... Mask Channel x
The codec data in channel 1 (CH1X, CH1R) or channel 2 (CH2X,CH2R) respectively is
masked with these 6 register bits. The position of this 6 bit mask on the 8 or 16 bit value
respectively is determined by the MPx bits. If a mask bit is set to ’1’ the data in the
corresponding bit position is masked and thus always a ’1’. With a ’0’ the data passes
unchanged.
MPx
Data Sheet
... Mask Position of Channel x
Bit 1 0
Description
0
0
Bit 5...0 of the codec data register CHx0 is masked with MASKx
0
1
Bit 7...2 of the codec data register CHx0 is masked with MASKx
1
0
Bit 5...0 of the codec data register CHx1 is masked with MASKx
1
1
Bit 7...2 of the codec data register CHx1 is masked with MASKx
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Detailed Register Description
7.4.12
Test Function Configuration Register (TFCR)
Value after reset: 00H
7
TFCR
0
ALTF
0
ALTF
DLTF
RD/WR (6CH)
... Analog Loop and Test Functions
Bit 5 4
3
Test Function
0
0
0
0
0
0
1
1
0
1
0
1
NOT:
ALF:
ALC:
ALN:
1
X
X
Reserved
DLTF
Data Sheet
0
No Test Mode
Analog Loop via Front End
Analog Loop via Converter
Analog Loop via Noise Shaper
... Digital Loop and Test Functions
Bit 2 1
0
Test Function
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
NOT:
IDR:
DLN:
DLS:
DLP1:
DLP2:
1
1
X
Reserved
No Test Mode
Initialize DRAM
Digital Loop via Noise Shaper
Digital Loop via Signal Processor
Digital Loop via codec part CH1
Digital Loop via codec part CH2
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Detailed Register Description
7.4.13
CRAM Control (CCR) and Status (CSR) Register
The programming of the CRAM Control Register (CCR) and the CRAM Status Register
(CSR) is intended for a back-up procedure for the direct access to individual CRAM
coefficients. A detailed description can be found in chapter 4.8.2.1.
CRAM Status Register (CSR)
Value after reset: 00H
7
CCR
0
0
DCA
0
DCA BSYB
CBADR
RD (6FH)
... DSP CRAM Access
Read-back of the programmed value
BSYB
... Busy Back-up Procedure
0: Momentary there is no transfer of CRAM data to the temporary area running. CRAM
access via microcontroller interface is possible
1: Transfer of the CRAM block <CBADR> is running. CRAM access via microcontroller
interface is not allowed
CBADR
... CRAM Block Address
Read-back of the programmed value
CRAM Control Register (CCR)
Value after reset: 00H
7
CCR
DCA
0
0
0
DCA
SBP
CBADR
WR (6FH)
... DSP CRAM Access
0: The normal CRAM area (80H to FFH) is accessed by the codec DSP
1: The temporary CRAM area (coefficient block with 8 bytes corresponding to the
COP_x sequences) is accessed by the codec DSP. The switching to the temporary
CRAM block happens as soon as the transfer of the block has completed (BSYB = ’0’)
SBP
... Start Back-up Procedure
0: No back-up is initiated
1: A transition to SBP = ’1’ starts the back-up of the CRAM block <CBADR> into the
temporary CRAM area
Data Sheet
236
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Detailed Register Description
CBADR
... CRAM Block Address
Address of a coefficient block with 8 bytes corresponding to the COP_x sequences
(x=0...F) of the codec programming sequences
7.4.14
CRAM (Coefficient RAM)
Address Mnemonic Description
80H
81H
82H
83H
84H
85H
86H
87H
T1
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
GTX
GTR
T2
90H
91H
92H
93H
94H
95H
96H
97H
FD
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
GE
A2
A1
K
-
Data Sheet
GD1
G1
F1
GD2
G2
F2
T3
GD3
G3
F3
Reserved
Reserved
Beat tone time lower byte
Beat tone time higher byte
Trapezoid generator amplitude
Tone generator amplitude
Tone generator frequency lower byte
Tone generator frequency higher byte
Level adjustment for transmit path
Level adjustment for receive path
Beat tone time span lower byte
Beat tone time span higher byte
Trapezoid generator amplitude
Tone generator amplitude
Tone generator frequency lower byte
Tone generator frequency higher byte
Dual tone frequency lower byte
Dual tone frequency higher byte
Beat tone time span lower byte
Beat tone time span higher byte
Trapezoid generator amplitude
Tone generator amplitude
Tone generator frequency lower byte
Tone generator frequency higher byte
Saturation amplification
Bandwidth
Center frequency
Attenuation of the stop-band
Reserved
Reserved
Reserved
Reserved
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Detailed Register Description
Address Mnemonic Description
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
TOFF
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
ATT2R
ATT1R
GR
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
GZ
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
FX
Transmit correction filter coefficients part 8
Transmit correction filter coefficients part 7
Transmit correction filter coefficients part 6
Transmit correction filter coefficients part 5
Transmit correction filter coefficients part 4
Transmit correction filter coefficients part 3
Transmit correction filter coefficients part 2
Transmit correction filter coefficients part 1
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
FR
Receive correction filter coefficients part 12
Receive correction filter coefficients part 11
Receive correction filter coefficients part 10
Receive correction filter coefficients part 9
Transmit correction filter coefficients part 12
Transmit correction filter coefficients part 11
Transmit correction filter coefficients part 10
Transmit correction filter coefficients part 9
Data Sheet
TON
-
GX
-
FX
Turn-off period of the tone generator lower byte
Turn-off period of the tone generator higher byte
Turn-on period of the tone generator lower byte
Turn-on period of the tone generator higher byte
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Conferencing attenuation CH2R
Conferencing attenuation CH1R
Receive gain lower byte
Receive gain higher byte
Transmit gain lower byte
Transmit gain higher byte
Reserved
Reserved
Sidetone gain lower byte
Sidetone gain higher byte
Reserved
Reserved
Reserved
Reserved
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Detailed Register Description
Address Mnemonic Description
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
FR
Receive correction filter coefficients 8
Receive correction filter coefficients 7
Receive correction filter coefficients 6
Receive correction filter coefficients 5
Receive correction filter coefficients 4
Receive correction filter coefficients 3
Receive correction filter coefficients 2
Receive correction filter coefficients 1
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
SW
DS
TW
ETLE
ETAE
ATT
GLE
GAE
Switching time
Decay speed
Wait time
Echo time (line side)
Echo time (acoustic side)
Attenuation programmed in GHR or GHX
Gain of line echo
Gain of acoustic echo
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
PDNLE
GDNLE
PDSLE
GDSLE
PDNAE
GDNAE
PDSAE
GDSAE
Peak decrement when noise is detected (line side)
Reserve when noise is detected (line side)
Peak decrement when speech is detected (line side)
Reserve when speech is detected (line side)
Peak decrement when noise is detected (acoustic side)
Reserve when noise is detected (acoustic side)
Peak decrement when speech is detected (acoustic side)
Reserve when speech is detected (acoustic side)
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
LP1R
LP1X
LP2LR
LP2LX
OFFR
OFFX
LIM
Reserved
Time constant LP1 (receive)
Time constant LP1 (transmit)
Limitation for LP2 (receive)
Limitation for LP2 (transmit)
Level offset up to detected noise (receive)
Level offset up to detected noise (transmit)
Starting level of the logarithmic amplifiers
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
LP2NR
LP2SR
PDNR
PDSR
LP2NX
LP2SX
PDNX
PDSX
Time constant LP2 for noise (receive)
Time constant LP2 for signal (receive)
Time constant PD for noise (receive)
Time constant PD for signal (receive)
Time constant LP2 for noise (transmit)
Time constant LP2 for signal (transmit)
Time constant PD for noise (transmit)
Time constant PD for signal (transmit)
Data Sheet
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Detailed Register Description
Address Mnemonic Description
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
AGIX
NOISX
TMLX
TMHX
AGX
AAX
COMX
LGAX
Initial AGC gain transmit
Threshold for AGC-reduction by background noise
Settling time constant for lower levels
Settling time constant for higher levels
Gain range of automatic control
Attenuation range of automatic control
Compare level rel. to max. PCM-value
Loudness gain adjustment
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
AGIR
NOISR
TMLR
TMHR
AGR
AAR
COMR
LGAR
Initial AGC attenuation/gain receive
Threshold for AGC-reduction by background noise
Settling time constant for lower levels
Settling time constant for higher lower levels
Gain range of automatic control
Attenuation range of automatic control
Compare level rel. to max. PCM-value
Loudness gain adjustment
Data Sheet
240
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Electrical Characteristics
8
Electrical Characteristics
8.1
Electrical Characteristics (general part)
8.1.1
Absolute Maximum Ratings
Parameter
Symbol
TSTG
VS
Storage temperature
Input/output voltage on any pin
with respect to ground
Maximum voltage on any pin
with respect to ground
Limit Values
Unit
min.
max.
– 65
150
°C
– 0.3
VDD + 0.3
V
7
V
Vmax
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
8.1.2
DC-Characteristics
VDD/VSS = 5 V ± 5 %; 3.3V ± 5 %; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
H-input level
(except pin XTAL1)
VIH
L-input level
(except pin XTAL1)
VIL
– 0.3
H-output level
(except pin XTAL2,
AD0...7)
VOH
2.4
L-output level
(except pin XTAL2, DU,
DD, AD0...7)
VOL
H-output level
(pins AD0...7)
VOH
L-output level
(pins AD0...7)
VOL
Data Sheet
typ.
max.
VDD +
2.0
Unit Test Condition
V
0.3
0.8
0.45
2.4
0.45
241
V
V
IO = -400 µA
V
IO = 2 mA
V
IO = -2 mA
V
IO = 2.5 mA
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Electrical Characteristics
8.1.2
DC-Characteristics (cont’d)
VDD/VSS = 5 V ± 5 %; 3.3V ± 5 %; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
L-output level
(pins DU,DD)
VOL
H-input level
(pin XTAL1)
VIH
L-input level
(pin XTAL1)
Input leakage current
Output leakage current
(all pins except
SX1,2,SR1,2,XTAL1,2
BGREF, Vref)
8.1.3
typ.
Unit Test Condition
max.
0.45
V
VDD-0.5
VDD
V
VIL
0
0.4
V
ILI
ILO
-1
-1
1
1
µA
µA
IO = 7mA
0V< VIN<VDD
0V< VOUT<VDD
Capacitances
TA = 25 °C, VDD = 5 V ± 5 %, 3.3V ± 5 % VSSA = 0 V, VSSD = 0 V, fc = 1 MHz, unmeasured
pins grounded.
Table 28
Parameter
Symbol
Limit Values Unit
min.
Remarks
max.
Input Capacitance
I/O Capacitance
CIN
CI/O
7
7
pF
pF
All pins except SX1,2 and
XTAL1,2
Output Capacitance
against VSS
COUT
10
pF
pins SX1,2
Load Capacitance
CL
40
pF
pins XTAL1,2
Data Sheet
242
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Electrical Characteristics
8.1.4
Oscillator Specification
Recommended Oscillator Circuits
33 pF
41
XTAL1
CL
External
Oscillator
Signal
41
XTAL1
7.68 MHz
33 pF
42
N.C.
XTAL2
42
XTAL2
CL
Crystal Oscillator Mode
Driving from External Source
ITS09659
Figure 93
Oscillator Circuits
Crystal Specification
Parameter
Symbol
Limit Values
Unit
Frequency
f
7.680
MHz
max. 100
ppm
max. 40
pF
Frequency calibration tolerance
Load capacitance
CL
Oscillator mode
Resistance
fundamental
R1
max. 50
Ω
Note: The load capacitance CL depends on the recommendation of the crystal
specification. Typical values for CL are 22 ... 33 pF resulting a turn-on time for the
IOM and MCLK clocks of approximately 0.2 to 4 ms.
Data Sheet
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Electrical Characteristics
XTAL1 Clock Characteristics (external oscillator input)
Parameter
Limit Values
Duty cycle
8.1.5
min.
max.
1:2
2:1
AC Characteristics
TA = 0 to 70 °C, VDD = 5 V ± 5%, VDD = 3.3 V ± 5%
Inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing
measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC
testing input/output waveforms are shown in figure 94.
2.4
2.0
2.0
Device
Under
Test
Test Points
0.8
0.8
C Load = 100 pF
0.45
ITS09660
Figure 94
Input/Output Waveform for AC Tests
Data Sheet
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Electrical Characteristics
8.1.6
IOM-2 Interface Timing
FSC (0)
tIIS
tFSD
DCL (0)
tIIH
DU/DD (I)
tIOD
DU/DD (0)
tSDD
SDS1/2
tBCD
tBCD
BCL (0)
ITD09663.vsd
Figure 95
IOM® Timing
Data Sheet
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Electrical Characteristics
Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
IOM output data delay
tIOD
100
ns
IOM input data setup
tIIS
20
ns
IOM input data hold
tIIH
20
ns
FSC strobe delay
tFSD
Strobe signal delay
tSDD
120
ns
BCL / DCL delay
tBCD
100
ns
Frame sync setup
tFSS
50
ns
Frame sync hold
tFSH
30
ns
Frame sync width
tFSW
40
ns
-130
ns
DCL Clock Characteristics
0.9 VDD
0.1 VDD
Figure 96
Definition of Clock Period and Width
Symbol
Limit Values
Unit
Test Condition
osc ± 100 ppm
min.
typ.
max.
tPO
585
651
717
ns
tWHO
260
325
391
ns
tWLO
260
325
391
ns
Data Sheet
246
osc ± 100 ppm
osc ± 100 ppm
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Electrical Characteristics
8.1.7
Microcontroller Interface Timing
8.1.7.1
Serial Control Interface (SCI) Timing
t1
t2
t4
t3
t5
CS
SCLK
t6
t7
t9
SDR
t8
SDX
t10
Figure 97
SCI Interface
Parameter
SCI Interface
Symbol
SCLK cycle time
t1
500
ns
SCLK high time
t2
100
ns
SCLK low time
t3
100
ns
CS setup time
t4
0
ns
CS hold time
t5
10
ns
SDR setup time
t6
40
ns
SDR hold time
t7
40
ns
SDX data out delay
t8
80
ns
CS high to SDX tristate
t9
40
ns
SCLK to SDX active
t10
80
ns
Data Sheet
Limit values
Min
247
Unit
Max
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Electrical Characteristics
8.1.7.2
Parallel Microcontroller Interface Timing
Siemens/Intel Bus Mode
Figure 98
Microprocessor Read Cycle
Figure 99
Microprocessor Write Cycle
Figure 100
Multiplexed Address Timing
Data Sheet
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Electrical Characteristics
WR x CS or
RD X CS
t AS
A0-A7
t AH
Address
ITT09661
Figure 101
Non-Multiplexed Address Timing
Motorola Bus Mode
Figure 102
Microprocessor Read Timing
R/W
t DSD
t RWD
t WW
t WI
CS x DS
t WD
t DW
D0 - D7
Data
ITT09679
Figure 103
Microprocessor Write Cycle
Data Sheet
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Electrical Characteristics
CS x DS
t AS
t AH
AD0 - AD7
ITT09662
Figure 104
Non-Multiplexed Address Timing
Microprocessor Interface Timing
Parameter
Symbol
Limit Values
min.
Unit
max.
ALE pulse width
tAA
50
ns
Address setup time to ALE
tAL
15
ns
Address hold time from ALE
tLA
10
ns
Address latch setup time to WR, RD
tALS
10
ns
Address setup time
tAS
25
ns
Address hold time
tAH
10
ns
ALE guard time
tAD
15
ns
DS delay after R/W setup
tDSD
20
ns
RD pulse width
tRR
110
ns
Data output delay from RD
tRD
95
ns
Data float from RD
tDF
25
ns
RD control interval
tRI
70
ns
W pulse width
tWW
60
ns
Data setup time to W x CS
tDW
35
ns
Data hold time W x CS
tWD
10
ns
W control interval
tWI
70
ns
R/W hold from CS x DS inactive
tRWD
30
ns
Data Sheet
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Electrical Characteristics
8.1.8
Reset
Table 29
Reset Signal Characteristics
Parameter
Symbol
Limit Values
Unit
Test Conditions
ms
Power On/Power Down
to Power Up (Standby)
min.
Length of active
low state
4
tRST
2 x DCL
clock cycles
8.2
During Power Up (Standby)
Electrical Characteristics (Transceiver Part)
DC Characteristics
VDD = 3.3 V ± 5 %, VSS = 0 V; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
Power supply currentpower-up (after reset)
IDUAR
4
mA
Power supply currentpower down
IDPD
1.1
mA
Power supply currentTranceiver active,
sending continous
pulses
IDTCP
12
mA
100 Ohms load on
the line
Power supply currentTranceiver active,
sending single pulses
IDTSP
10
mA
100 Ohms load on
the line
Power supply currentcodec powered up
IDCPU
6
mA
Power supply currenttone generation active
(single tone generated)
IDTG
18
mA
Data Sheet
251
-18.5 dB
amplification
50 Ohms load
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Electrical Characteristics
DC Characteristics
VDD = 5 V ± 5 % , VSS = 0 V; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
Power supply currentpower-up (after reset)
IDUAR
4.5
mA
Power supply currentpower down
IDPD
1.4
mA
Power supply currentTranceiver active,
sending continous
pulses
IDTCP
27.0
mA
100 Ohms load on
the line
Power supply currentTranceiver active,
sending single pulses
IDTSP
12.0
mA
100 Ohms load on
the line
Power supply currentcodec powered up
IDCPU
6.5
mA
Power supply currenttone generation active
(single tone generated)
IDTG
25.0
mA
-18.5 dB
amplification
50 Ohms load
DC Characteristics
VDD= 5V ± 5 %; 3.3V ± 5 %; VSS= 0V; TA = 0 to 70 °C
Parameter
Symbol Limit Values Unit Test Condition
min
Remarks
max
Transmitter output
impedance
ZX
10
0
kΩ
Ω
Inactive or during SX1,2
binary one
during binary zero
RL = 50 Ω
Receiver
input impedance
ZR
40
kΩ
SR1,2
single
ended
x
Data Sheet
252
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Electrical Characteristics
8.3
Electrical Characteristics (Codec Part)
8.3.1
DC Characteristics
VDD= 3.3V ± 5 %; VSS= 0V; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
Power supply current in
Emergency Ringing
Mode (AFE)
ITR
9
mA
Handset Mode (AFE)
IHS
10
mA
Speakerphone Mode
(AFE)
ISP
11
mA
Loudhearing Mode
(AFE)
ILH
13
mA
fTR = 400 Hz square
wave; ALS = -3.5dB
VDD= 5V ± 5 %; VSS= 0V; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
Power supply current in
Emergency Ringing
Mode (AFE)
ITR
12
mA
Handset Mode (AFE)
IHS
13
mA
Speakerphone Mode
(AFE)
ISP
14
mA
Loudhearing Mode
(AFE)
ILH
16
mA
fTR = 400 Hz square
wave; ALS = -3.5dB
Note: Operating power dissipation is measured with all analog outputs open.
All analog inputs are set to VREF.
The digital input signal (pin DD) is set to an idle code.
Data Sheet
253
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Electrical Characteristics
Transmission Characteristics
VDD= 5 V ± 5 %; VDD= 3.3 V ± 5 %; VSS = 0 V; TA = 0 to 70 °C
Parameter
Limit Values
min.
Overall programming range
(With specified transmission
characteristics)
Unit
Test Condition
max.
– 21.5
– 21.5
11.5
2.5
dB
dB
0
0
36
24
dB
dB
Receive:
loudspeaker
earpiece
Transmit:
differential inputs
single ended input
Programmable AFE gain
– 0.5
– 1.0
0.5
1.0
dB
dB
step accuracy
overall accuracy
Attenuation Distortion
@ 0 dBm0
0
– 0.25
– 0.25
– 0.25
– 0.25
0
dB
dB
dB
dB
dB
dB
< 200 Hz
200 – 300 Hz
300 – 2400 Hz
2400 – 3000 Hz
3000 – 3400 Hz
> 3400 Hz
0.25
0.45
0.9
Out-of-band signals
Group delay distortion
@ 0 dBm0 1)
dB
dB
– 45
– 65
dB
dB
– 35
– 40
dB
dB
µs
µs
µs
µs
TGSR.ERA=0
500 – 600 Hz
600 – 1000 Hz
1000 – 2600 Hz
2600 – 2800 Hz
dB
dB
dB
0 to – 30 dBm0
– 40 dBm0
– 45 dBm0
dB
dB
dB
3 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
750
380
130
750
Signal-to-total distortion
(method 2, sinewave 1kHz)
35
29
24
Gain tracking
(method 2)
@ – 10 dBm0
– 0.3
– 0.6
– 1.6
Data Sheet
– 35
– 45
receive (TGSR.ERA=0):
4.6 kHz
8.0 kHz
receive(TGSR.ERA=1):
4.6 kHz
8.0 kHz
transmit:
4.6 kHz
8.0 kHz
0.3
0.6
1.6
254
2001-03-12
PSB 21381/2
PSB 21383/4
Electrical Characteristics
Transmission Characteristics (cont’d)
VDD= 5 V ± 5 %; VDD= 3.3 V ± 5 %; VSS = 0 V; TA = 0 to 70 °C
Parameter
Limit Values
min.
Unit
Test Condition
max.
Idle-channel noise
– 75
– 66
dBm0
dBm0
receive (A-Law; Psoph.)
transmit (A-Law; Psoph.)
Cross-talk
– 66
dB
Reference: 0 dBm0
1)
Delay measurements include delays through the A/D and D/A with all features filters FX, GX, FR and GR
disabled.
Data Sheet
255
2001-03-12
PSB 21381/2
PSB 21383/4
Electrical Characteristics
8.3.2
Analog Front End Input Characteristics
VDD= 5V ± 5 %; 3.3V ± 5 %; VSS= 0V; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
Unit
Test Condition
kΩ
300 – 3400 Hz
mVp
mVp
36 dB; VDD=3.3V
36 dB; VDD=5V
Vp
Vp
differential;
0 dB; VDD=3.3V
0 dB; VDD=5V
Vp
Vp
single ended;
0 dB; VDD=3.3V
0 dB; VDD=5V
2
Ω
300 – 3400 Hz
2
Ω
300 – 3400 Hz
10
Ω
Load measured
from VREF to VSSA
2.25 2.4
2.55
V
IVREF = – 2 mA
200
400
kΩ
3.2
Vpk
Load (200Ω)
measured from
HOP to HON
3.2
Vpk
Load (50Ω)
measured from
LSP to LSN
min. typ
AMI-input impedance
AMI-input voltage swing
with specified transmission
characteristics
ZAMI
VAMI
max.
12.5 15
19
38
VAMI_dif
1.2
2.4
VAMI_single
0.75
1.67
8.3.3
Analog Front End Output Characteristics
VDD= 5V ± 5 %; 3.3V ± 5 %; TA = 0 to 70 °C
ZAHO
AHO-output impedance
ALS-output impedance
ZALS
VREF output impedance
ZVREF
7
VVREF
BGREF output impedance ZBGREF
VDD= 5V ± 5 %
AHO-output voltage swing VAHO
VREF output voltage
ALS-output voltage swing
Data Sheet
VALS
256
300
2001-03-12
PSB 21381/2
PSB 21383/4
Electrical Characteristics
Parameter
Symbol
Limit Values
min. typ
Unit
Test Condition
max.
VDD= 3.3V ± 5 %; TA = 0 to 70 °C
AHO-output voltage swing VAHO
1.6
Vpk
Load (200Ω)
measured from
HOP to HON
VALS
1.6
Vpk
Load (25Ω)
measured from
LSP to LSN
ALS-output voltage swing
The maximum output voltage swing corresponds to the maximum incoming PCM-code
(± 127)
Data Sheet
257
2001-03-12
PSB 21381/2
PSB 21383/4
Electrical Characteristics
9
Package Outlines
P-MQFP-44-1 (SMD)
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
258
2001-03-12
PSB 21381/2
PSB 21383/4
Electrical Characteristics
P-MQFP-64-1 (SMD)
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
259
2001-03-12
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Published by Infineon Technologies AG