INFINEON SAB-C161S-LM3V

D a t a S h e e t , V 1. 0 , N o v . 20 0 3
C161S
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er
M i c r o c o n t r o l l er s
N e v e r
s t o p
t h i n k i n g .
Edition 2003-11
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S h e e t , V 1. 0 , N o v . 20 0 3
C161S
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er
M i c r o c o n t r o l l er s
N e v e r
s t o p
t h i n k i n g .
C161S
Revision History:
2003-11
Previous Version:
none
Page
V1.0
Subjects (major changes since last revision)
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Template: mc_tmplt_a5.fm / 3 / 2003-09-01
16-Bit Single-Chip Microcontroller
C166 Family
C161S
C161S
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Summary of Features
High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
16-Priority-Level Interrupt System with 30 Sources, Sample-Rate down to 40 ns
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
On-Chip Memory Modules: 2 Kbytes On-Chip Internal RAM (IRAM)
On-Chip Peripheral Modules
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Sync./Asynchronous and High-Speed-Synchronous)
– On-Chip Real Time Clock
External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-bit or 16-bit
Data Bus Width
– Four Programmable Chip-Select Signals
– 4 Mbytes maximum address window size, results in a total external address space
of 16 Mbytes, when all chip-select signal (address windows) are active
Idle and Power Down Modes with Flexible Power Management
Programmable Watchdog Timer and Oscillator Watchdog
Up to 63 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
Power Supply: the C161S can operate from a 5 V or a 3 V power supply (see Table 1)
Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
On-Chip Bootstrap Loader
80-Pin MQFP Package
Data Sheet
1
V1.0, 2003-11
C161S
Summary of Features
This document describes several derivatives of the C161 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
Table 1
C161S Derivative Synopsis
Derivative
Max. Operating
Frequency
Operating Voltage
Ambient
Temperature
SAB-C161S-L25M
25 MHz
4.5 to 5.5 V (Standard)
0 to 70 °C
SAF-C161S-L25M
25 MHz
4.5 to 5.5 V (Standard)
-40 to 85 °C
SAB-C161S-LM3V
20 MHz
3.0 to 3.6 V (Reduced)
0 to 70 °C
SAF-C161S-LM3V
20 MHz
3.0 to 3.6 V (Reduced)
-40 to 85 °C
For simplicity all versions are referred to by the term C161S throughout this document.
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
•
•
the derivative itself, i.e. its function set, the temperature range, and the supply voltage
the package and the type of delivery.
For the available ordering codes for the C161S please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet
2
V1.0, 2003-11
C161S
General Device Information
2
General Device Information
2.1
Introduction
The C161S is a derivative of the Infineon C166 Family of full featured single-chip CMOS
microcontrollers. It combines high CPU performance (up to 12.5 million instructions per
second) with high peripheral functionality and enhanced IO-capabilities. It also provides
clock generation via PLL and power management features. The C161S is especially
suited for cost sensitive applications.
VDD
VSS
PORT0
16 bit
XTAL1
XTAL2
PORT1
16 bit
RSTIN
RSTOUT
NMI
Port 2
7 bit
C161S
EA
Port 3
12 bit
ALE
Port 4
6 bit
RD
WR/WRL
Port 5
2 bit
Port 6
4 bit
MCA05504
Figure 1
Data Sheet
Logic Symbol
3
V1.0, 2003-11
C161S
General Device Information
VDD
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
C161S
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.0/AD8
P0H.1/AD9
VSS
VDD
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8/MRST
P3.9/MTSR
P3.10/TxD0
P3.11/RxD0
P3.12/BHE/WRH
P3.13/SCLK
P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDD
VSS
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P4.4/A20
P4.5/A21
RD
WR/WRL
ALE
EA
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
XTAL1
XTAL2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
P1H.7/A15
P1H.6/A14
Pin Configuration and Definition
P5.15/T2EUD
P5.14/T4EUD
P2.15/EX7IN
P2.14/EX6IN
P2.13/EX5IN
P2.12/EX4IN
P2.11/EX3IN
P2.10/EX2IN
P2.9/EX1IN
P6.3/CS3
P6.2/CS2
P6.1/CS1
P6.0/CS0
NMI
RSTOUT
RSTIN
2.2
MCP05505
Figure 2
Data Sheet
Pin Configuration (top view)
4
V1.0, 2003-11
C161S
General Device Information
Table 2
Pin Definitions and Functions
Symbol Pin
No.
Input Function
Outp.
XTAL1
2
I
XTAL2
3
O
P3
IO
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
5
6
7
8
9
10
11
12
13
14
15
P3.13
16
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
Data Sheet
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
IO
17
18
19
20
23
24
O
O
O
O
O
O
XTAL1:
Input to the oscillator amplifier and input to the
internal clock generator
XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics (see Chapter 5.4) must be observed.
Port 3 is a 12-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as
push/pull or open drain drivers.
The following Port 3 pins also serve for alternate functions:
CAPIN GPT2 Register CAPREL Capture Input
T3OUT GPT1 Timer T3 Toggle Latch Output
T3EUD GPT1 Timer T3 External Up/Down Control Input
T4IN
GPT1 Timer T4 Count/Gate/Reload/Capture Inp.
T3IN
GPT1 Timer T3 Count/Gate Input
T2IN
GPT1 Timer T2 Count/Gate/Reload/Capture Inp.
MRST
SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR
SSC Master-Transmit/Slave-Receive Outp./Inp.
TxD0
ASC0 Clock/Data Output (Async./Sync.)
RxD0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
BHE
External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe
WRH
SCLK
SSC Master Clock Output / Slave Clock Input.
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state.
Port 4 can be used to output the segment address lines:
A16
Least Significant Segment Address Line
A17
Segment Address Line
A18
Segment Address Line
A19
Segment Address Line
A20
Segment Address Line
A21
Segment Address Line
5
V1.0, 2003-11
C161S
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input Function
Outp.
RD
25
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
WR/
WRL
26
O
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
ALE
27
O
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
EA
28
I
External Access Enable pin. A low level at this pin during and
after Reset forces the C161S to begin instruction execution
out of external memory. A high level forces execution out of
the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
IO
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 – D7
P0H.0 – P0H.7:
I/O
D8 – D15
Multiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
AD0 – AD7 AD0 – AD7
P0H.0 – P0H.7:
A8 – A15
AD8 – AD15
PORT0
P0L.0-7
29-36
P0H.0-7 39-46
Data Sheet
6
V1.0, 2003-11
C161S
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input Function
Outp.
PORT1
P1L.0-7
IO
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the
16-bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
I/O
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C161S. An
internal pull-up resistor permits power-on reset using only a
capacitor connected to VSS.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
47-54
P1H.0-7 55-62
RSTIN
65
Note: To let the reset configuration of PORT0 settle and to
let the PLL lock a reset duration of approx. 1 ms is
recommended.
RST
OUT
66
O
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI
67
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C161S to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Data Sheet
7
V1.0, 2003-11
C161S
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input Function
Outp.
P6
IO
P6.0
P6.1
P6.2
P6.3
68
69
70
71
IO
P2
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
O
O
O
O
72
73
74
75
76
77
78
P5
I
I
I
I
I
I
I
I
P5.14
P5.15
79
80
I
I
VDD
4, 22,
37, 64
–
Port 6 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as
push/pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
CS0
Chip Select 0 Output
Chip Select 1 Output
CS1
Chip Select 2 Output
CS2
CS3
Chip Select 3 Output
Port 2 is a 7-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as
push/pull or open drain drivers.
The following Port 2 pins also serve for alternate functions:
EX1IN
Fast External Interrupt 1 Input
EX2IN
Fast External Interrupt 2 Input
EX3IN
Fast External Interrupt 3 Input
EX4IN
Fast External Interrupt 4 Input
EX5IN
Fast External Interrupt 5 Input
EX6IN
Fast External Interrupt 6 Input
EX7IN
Fast External Interrupt 7 Input
Port 5 is a 2-bit input-only port with Schmitt-Trigger char.
The pins of Port 5 also serve as timer inputs:
T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Input
T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Input
Digital Supply Voltage:
+ 5 V during normal operation and idle mode.
+ 3.3 V during reduced supply operation and idle mode.
≥ 2.5 V during power down mode.
Note: Please refer to the Operating Conditions Parameters.
VSS
Data Sheet
1, 21,
38, 63
–
Digital Ground.
8
V1.0, 2003-11
C161S
General Device Information
Note: The following behavioural differences must be observed when the bidirectional
reset is active:
•
•
•
•
•
Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.
The reset indication flags always indicate a long hardware reset.
The PORT0 configuration is treated like on a hardware reset. Especially the
bootstrap loader may be activated when P0L.4 is low.
Pin RSTIN may only be connected to external reset devices with an open drain output
driver.
A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
9
V1.0, 2003-11
C161S
Functional Description
3
Functional Description
The architecture of the C161S combines advantages of both RISC and CISC processors
and of advanced peripheral subsystems in a very well-balanced way. In addition the onchip memory blocks allow the design of compact systems with maximum performance.
Figure 3 gives an overview of the different on-chip components and of the advanced,
high bandwidth internal bus structure of the C161S.
C166-Core
ProgMem
16
Data
32
Internal
ROM
Area
CPU
Instr. / Data
16
Data
16
IRAM
Internal
RAM
2 Kbytes
Osc / PLL
PEC
External Instr. / Data
Dual Port
Note: All time specifications refer to a CPU clock of 20 MHz
(see definition in the AC Characteristics section).
Interrupt Controller 16-Level
Priority
RTC
XTAL
WDT
Peripheral Data Bus
16
ASC0
SSC
(USART)
(SPI)
GPT
T2
EBC
T3
XBUS Control
External Bus
Control
T4
Port 0
16
Figure 3
Interrupt Bus
Port 2
4
Port 6
6
Port 4
On-Chip XBUS (16-Bit Demux)
16
T5
BRGen
Port 1
16
BRGen
Port 3
12
T6
7
Port 5
2
MCB04323_1S.vsd
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).
Data Sheet
10
V1.0, 2003-11
C161S
Functional Description
3.1
Memory Organization
The memory space of the C161S is configured in a von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 Mbytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.
The C161S is prepared to incorporate on-chip program memory (not in the ROM-less
derivatives, of course) for code or constant data. The internal ROM area can be mapped
either to segment 0 or segment 1.
2 Kbytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 16 Mbytes of external RAM and/or ROM can be connected to the
microcontroller. The maximum contiguous external address space is 4 Mbytes, i.e. this
is the maximum address window size. Using the chip-select lines (multiple windows) this
results in a maximum usable external address space of 16 Mbytes.
Data Sheet
11
V1.0, 2003-11
C161S
Functional Description
3.2
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:
•
•
•
•
16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed
16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is
input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both
addresses and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 4 external CS signals (3 windows plus default) can be generated in order to save
external glue logic. The C161S offers the possibility to switch the CS outputs to an
unlatched mode. In this mode the internal filter logic is switched off and the CS signals
are directly generated from the address. The unlatched CS mode is enabled by setting
CSCFG (SYSCON.6).
For applications which require less than 4 Mbytes of external memory space, this
address space can be restricted to 1 Mbyte, 256 Kbytes, or to 64 Kbytes. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if the full
address width is used.
Data Sheet
12
V1.0, 2003-11
C161S
Functional Description
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161S’s instructions can be executed
in just one machine cycle which requires 100 ns at 20 MHz CPU clock. For example,
shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a
16 × 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another
pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
CPU
Internal
RAM
SP
STKOV
STKUN
MDH
MDL
R15
Exec. Unit
Instr. Ptr.
Instr. Reg.
Mul/Div-HW
Bit-Mask Gen
General
4-Stage
Pipeline
R15
Purpose
ALU
32
ROM
16
(16-bit)
Barrel - Shifter
Registers
R0
PSW
SYSCON
Context Ptr.
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Page Ptr.
Code Seg. Ptr.
R0
16
MCB02147
Figure 4
CPU Block Diagram
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
Data Sheet
13
V1.0, 2003-11
C161S
Functional Description
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C161S instruction set which includes
the following instruction classes:
•
•
•
•
•
•
•
•
•
•
•
•
Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
14
V1.0, 2003-11
C161S
Functional Description
3.3.1
Interrupt System
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C161S is capable of reacting very fast to the occurrence
of non-deterministic events.
The architecture of the C161S supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicitly decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C161S has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 3 shows all of the possible C161S interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
Data Sheet
15
V1.0, 2003-11
C161S
Functional Description
Table 3
C161S Interrupt Nodes
Source of Interrupt or Request
PEC Service Request Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
Unassigned node
CC8IR
CC8IE
CC8INT
00’0060H
18H
External Interrupt 1
CC9IR
CC9IE
CC9INT
00’0064H
19H
External Interrupt 2
CC10IR
CC10IE
CC10INT
00’0068H
1AH
External Interrupt 3
CC11IR
CC11IE
CC11INT
00’006CH
1BH
External Interrupt 4
CC12IR
CC12IE
CC12INT
00’0070H
1CH
External Interrupt 5
CC13IR
CC13IE
CC13INT
00’0074H
1DH
External Interrupt 6
CC14IR
CC14IE
CC14INT
00’0078H
1EH
External Interrupt 7
CC15IR
CC15IE
CC15INT
00’007CH
1FH
GPT1 Timer 2
T2IR
T2IE
T2INT
00’0088H
22H
GPT1 Timer 3
T3IR
T3IE
T3INT
00’008CH
23H
GPT1 Timer 4
T4IR
T4IE
T4INT
00’0090H
24H
GPT2 Timer 5
T5IR
T5IE
T5INT
00’0094H
25H
GPT2 Timer 6
T6IR
T6IE
T6INT
00’0098H
26H
GPT2 CAPREL Reg.
CRIR
CRIE
CRINT
00’009CH
27H
Unassigned node
ADCIR
ADCIE
ADCINT
00’00A0H
28H
Unassigned node
ADEIR
ADEIE
ADEINT
00’00A4H
29H
ASC0 Transmit
S0TIR
S0TIE
S0TINT
00’00A8H
2AH
ASC0 Transmit Buffer
S0TBIR
S0TBIE
S0TBINT
00’011CH
47H
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACH
2BH
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0H
2CH
SSC Transmit
SCTIR
SCTIE
SCTINT
00’00B4H
2DH
SSC Receive
SCRIR
SCRIE
SCRINT
00’00B8H
2EH
SSC Error
SCEIR
SCEIE
SCEINT
00’00BCH
2FH
Unassigned node
XP0IR
XP0IE
XP0INT
00’0100H
40H
Unassigned node
XP1IR
XP1IE
XP1INT
00’0104H
41H
Unassigned node
XP2IR
XP2IE
XP2INT
00’0108H
42H
PLL/OWD and RTC
XP3IR
XP3IE
XP3INT
00’010CH
43H
Unassigned node
CC29IR
CC29IE
CC29INT
00’0110H
44H
Unassigned node
CC30IR
CC30IE
CC30INT
00’0114H
45H
Unassigned node
CC31IR
CC31IE
CC31INT
00’0118H
46H
Data Sheet
16
V1.0, 2003-11
C161S
Functional Description
The C161S also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during runtime:
Table 4
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008H
00’0010H
00’0018H
02H
04H
06H
II
II
II
UNDOPC
PRTFLT
BTRAP
BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
ILLOPA
BTRAP
00’0028H
0AH
I
ILLINA
BTRAP
00’0028H
0AH
I
ILLBUS
BTRAP
00’0028H
0AH
I
Reserved
–
–
[2CH –
3CH]
[0BH –
0FH]
–
Software Traps
• TRAP Instruction
–
–
Any
Any
[00’0000H – [00H –
00’01FCH] 7FH]
in steps of
4H
Reset Functions:
–
• Hardware Reset
• Software Reset
• W-dog Timer Overflow
Class A Hardware Traps:
• Non-Maskable
Interrupt
• Stack Overflow
• Stack Underflow
Class B Hardware Traps:
• Undefined Opcode
• Protected Instruction
Fault
• Illegal Word Operand
Access
• Illegal Instruction
Access
• Illegal External Bus
Access
Data Sheet
17
Current
CPU
Priority
V1.0, 2003-11
C161S
Functional Description
3.4
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components, or may be used internally to clock timers
T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet
18
V1.0, 2003-11
C161S
Functional Description
U/D
T2EUD
fCPU
2n : 1
T2IN
Interrupt
Request
GPT1 Timer T2
T2
Mode
Control
Reload
Capture
fCPU
Interrupt
Request
n
2 :1
Toggle FF
T3
Mode
Control
T3IN
GPT1 Timer T3
T3OTL
T3OUT
U/D
T3EUD
Other
Timers
Capture
Reload
T4IN
fCPU
2n : 1
T4
Mode
Control
GPT1 Timer T4
Interrupt
Request
U/D
T4EUD
MCT02141
n = 3 … 10
Figure 5
Block Diagram of GPT1
With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock. The count direction (up/down) for each timer is programmable by software.
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5. The overflows/underflows of timer
T6 can cause a reload from the CAPREL register. The CAPREL register may capture
the contents of timer T5 based on an external signal transition on the corresponding port
pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This
allows the C161S to measure absolute time differences or to perform pulse multiplication
without software overhead.
Data Sheet
19
V1.0, 2003-11
C161S
Functional Description
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
fSYS
2n : 1
Interrupt
Request
(T5IR)
GPT2 Timer T5
T5
Mode
Control
U/D
Clear
Capture
GPT2 CAPREL
T3IN/
Interrupt
Request
(CRIR)
MUX
CAPIN
Interrupt
Request
(T6IR)
CT3
Clear
fSYS
2n : 1
GPT2 Timer T6
T6
Mode
Control
Toggle FF
T6OTL
U/D
Mcb03999_x1s.vsd
n=2…9
Figure 6
Data Sheet
Block Diagram of GPT2
20
V1.0, 2003-11
C161S
Functional Description
3.5
Real Time Clock
The Real Time Clock (RTC) module of the C161S consists of a chain of 3 divider blocks,
a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible
via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip
oscillator frequency divided by 32 via a separate clock driver (fRTC = fOSC/32) and is
therefore independent from the selected clock generation mode of the C161S. All timers
count up.
The RTC module can be used for different purposes:
•
•
•
System clock to determine the current time and date
Cyclic time based interrupt
48-bit timer for long term measurements
T14REL
Reload
T14
8:1
f RTC
Interrupt
Request
RTCH
RTCL
MCD04432
Figure 7
RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to
maintain the correct system time even when intermediate resets are executed.
Data Sheet
21
V1.0, 2003-11
C161S
Functional Description
3.6
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 625 kbit/s and
half-duplex synchronous communication at up to 2.5 Mbit/s (@ 20 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake-up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 5 Mbit/s (@ 20 MHz
CPU clock). It may be configured so it interfaces with serially linked peripheral
components. A dedicated baud rate generator allows to set up all standard baud rates
without oscillator tuning. For transmission, reception, and error handling three separate
interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet
22
V1.0, 2003-11
C161S
Functional Description
3.7
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value
(stored in WDTREL) in order to allow further variation of the monitored time interval.
Each time it is serviced by the application software, the high byte of the Watchdog Timer
is reloaded. Thus, time intervals between 25 µs and 420 ms can be monitored
(@ 20 MHz).
The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz).
3.8
Parallel Ports
The C161S provides up to 63 I/O lines which are organized into six input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of three I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A21/19/17 … A16 in
systems where segmentation is enabled to access more than 64 Kbytes of memory.
Port 6 provides optional chip select signals.
Port 3 includes alternate functions of timers, serial interfaces, and the optional bus
control signal BHE.
Port 5 is used for timer control signals.
Data Sheet
23
V1.0, 2003-11
C161S
Functional Description
3.9
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (fCPU = 2 … 5 MHz).
In prescaler mode the PLL base frequency is divided by 2 (fCPU = 1 … 2.5 MHz).
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.
Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD line low upon a reset, similar to the standard reset configuration via
PORT0.
Data Sheet
24
V1.0, 2003-11
C161S
Functional Description
3.10
Power Management
The C161S provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):
•
•
•
Power Saving Modes switch the C161S into a special operating mode (control via
instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Power Down Mode stops all clock signals and all operation (RTC may optionally
continue running).
Clock Generation Management controls the distribution and the frequency of
internal and external clock signals (control via register SYSCON2).
Slow Down Mode lets the C161S run at a CPU clock frequency of fOSC / 1 … 32 (half
for prescaler operation) which drastically reduces the consumed power. The PLL can
be optionally disabled while operating in Slow Down Mode.
Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3).
Each peripheral can separately be disabled/enabled. A group control option disables
a major part of the peripheral set by setting one single bit.
The on-chip RTC supports intermittent operation of the C161S by generating cyclic
wake-up signals. This offers full performance to quickly react on action requests while
the intermittent sleep phases greatly reduce the average power consumption of the
system.
Data Sheet
25
V1.0, 2003-11
C161S
Functional Description
3.11
Instruction Set Summary
Table 5 lists the instructions of the C161S in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 5
Mnemonic
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR
BSET
BMOV(N)
BAND, BOR,
BXOR
BCMP
BFLDH/L
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
SHL / SHR
ROL / ROR
ASHR
Data Sheet
Instruction Set Summary
Description
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16- × 16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise XOR, (word/byte operands)
Clear direct bit
Set direct bit
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Bytes
2/4
2/4
2/4
2/4
2
2
2
2
2
2/4
2/4
2/4
2
2
4
4
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Shift left/right direct word GPR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
4
4
26
2/4
2/4
2/4
2
2
2
2
V1.0, 2003-11
C161S
Functional Description
Table 5
Instruction Set Summary (cont’d)
Mnemonic
MOV(B)
MOVBS
MOVBZ
JMPA, JMPI,
JMPR
JMPS
J(N)B
JBC
JNBS
CALLA, CALLI,
CALLR
CALLS
PCALL
TRAP
PUSH, POP
SCXT
RET
RETS
RETP
RETI
SRST
IDLE
PWRDN
SRVWDT
DISWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
Data Sheet
Description
Move word (byte) data
Move byte operand to word operand with sign extension
Move byte operand to word operand with zero extension
Jump absolute/indirect/relative if condition is met
Bytes
2/4
2/4
2/4
4
Jump absolute to a code segment
Jump relative if direct bit is (not) set
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
4
4
4
4
4
Call absolute subroutine in any code segment
Push direct word register onto system stack and call
absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack and update
register with word operand
Return from intra-segment subroutine
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct
word register from system stack
Return from interrupt service subroutine
Software Reset
Enter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
4
4
27
2
2
4
2
2
2
2
4
4
4
4
4
4
2
2
2/4
2/4
2
V1.0, 2003-11
C161S
Functional Description
3.12
Special Function Registers Overview
Table 6 lists all SFRs which are implemented in the C161S in alphabetical order. The
following markings assist in classifying the listed registers:
“b” in the “Name” column marks Bit-addressable SFRs.
“E” in the “Physical Address” column marks (E)SFRs in the Extended SFR-Space.
“X” in the “Physical Address” column marks registers within on-chip X-peripherals.
Table 6
Name
C161S Registers, Ordered by Name
8-Bit Description
Addr.
Reset
Value
b FF98H
CCH
Software Interrupt Control Register
0000H
ADDRSEL1
FE18H
0CH
Address Select Register 1
0000H
ADDRSEL2
FE1AH
0DH
Address Select Register 2
0000H
ADDRSEL3
FE1CH
0EH
Address Select Register 3
0000H
ADDRSEL4
FE1EH
0FH
Address Select Register 4
0000H
ADEIC
b FF9AH
CDH
Software Interrupt Control Register
0000H
BUSCON0
b FF0CH
86H
Bus Configuration Register 0
0XX0H
BUSCON1
b FF14H
8AH
Bus Configuration Register 1
0000H
BUSCON2
b FF16H
8BH
Bus Configuration Register 2
0000H
BUSCON3
b FF18H
8CH
Bus Configuration Register 3
0000H
BUSCON4
b FF1AH
8DH
Bus Configuration Register 4
0000H
FE4AH
25H
GPT2 Capture/Reload Register
0000H
CC10IC
b FF8CH
C6H
EX2IN Interrupt Control Register
0000H
CC11IC
b FF8EH
C7H
EX3IN Interrupt Control Register
0000H
CC12IC
b FF90H
C8H
EX4IN Interrupt Control Register
0000H
CC13IC
b FF92H
C9H
EX5IN Interrupt Control Register
0000H
CC14IC
b FF94H
CAH
EX6IN Interrupt Control Register
0000H
CC15IC
b FF96H
CBH
EX7IN Interrupt Control Register
0000H
CC29IC
b F184H
E C2H
Software Interrupt Control Register
0000H
CC30IC
b F18CH E C6H
Software Interrupt Control Register
0000H
CC31IC
b F194H
E CAH
Software Interrupt Control Register
0000H
CC8IC
b FF88H
C4H
Software Interrupt Control Register
0000H
CC9IC
b FF8AH
C5H
EX1IN Interrupt Control Register
0000H
ADCIC
CAPREL
Data Sheet
Physical
Address
28
V1.0, 2003-11
C161S
Functional Description
Table 6
C161S Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
Reset
Value
CP
FE10H
08H
CPU Context Pointer Register
FC00H
b FF6AH
B5H
GPT2 CAPREL Interrupt Ctrl. Reg.
0000H
FE08H
04H
CPU Code Seg. Pointer Reg. (read only)
0000H
DP0H
b F102H
E 81H
P0H Direction Control Register
00H
DP0L
b F100H
E 80H
P0L Direction Control Register
00H
DP1H
b F106H
E 83H
P1H Direction Control Register
00H
DP1L
b F104H
E 82H
P1L Direction Control Register
00H
DP2
b FFC2H
E1H
Port 2 Direction Control Register
0000H
DP3
b FFC6H
E3H
Port 3 Direction Control Register
0000H
DP4
b FFCAH
E5H
Port 4 Direction Control Register
00H
DP6
b FFCEH
E7H
Port 6 Direction Control Register
00H
DPP0
FE00H
00H
CPU Data Page Pointer 0 Reg. (10 bits)
0000H
DPP1
FE02H
01H
CPU Data Page Pointer 1 Reg. (10 bits)
0001H
DPP2
FE04H
02H
CPU Data Page Pointer 2 Reg. (10 bits)
0002H
DPP3
FE06H
03H
CPU Data Page Pointer 3 Reg. (10 bits)
0003H
External Interrupt Control Register
0000H
CRIC
CSP
EXICON
b F1C0H E E0H
IDCHIP
F07CH E 3EH
Identifier
05XXH
IDMANUF
F07EH
E 3FH
Identifier
1820H
IDMEM
F07AH
E 3DH
Identifier
0000H
IDMEM2
F076H
E 3BH
Identifier
0000H
IDPROG
F078H
E 3CH
Identifier
0000H
ISNC
b F1DEH E EFH
Interrupt Subnode Control Register
0000H
MDC
b FF0EH
87H
CPU Multiply Divide Control Register
0000H
MDH
FE0CH
06H
CPU Multiply Divide Reg. – High Word
0000H
MDL
FE0EH
07H
CPU Multiply Divide Reg. – Low Word
0000H
ODP2
b F1C2H E E1H
Port 2 Open Drain Control Register
0000H
ODP3
b F1C6H E E3H
Port 3 Open Drain Control Register
0000H
ODP6
b F1CEH E E7H
Port 6 Open Drain Control Register
00H
ONES
b FF1EH
8FH
Constant Value 1’s Register (read only)
FFFFH
P0H
b FF02H
81H
Port 0 High Reg. (Upper half of PORT0)
00H
Data Sheet
29
V1.0, 2003-11
C161S
Functional Description
Table 6
Name
C161S Registers, Ordered by Name (cont’d)
Physical
Address
8-Bit Description
Addr.
Reset
Value
P0L
b FF00H
80H
Port 0 Low Reg. (Lower half of PORT0)
00H
P1H
b FF06H
83H
Port 1 High Reg. (Upper half of PORT1)
00H
P1L
b FF04H
82H
Port 1 Low Reg.(Lower half of PORT1)
00H
P2
b FFC0H
E0H
Port 2 Register
0000H
P3
b FFC4H
E2H
Port 3 Register
0000H
P4
b FFC8H
E4H
Port 4 Register (8 bits)
P5
b FFA2H
D1H
Port 5 Register (read only)
P6
b FFCCH
E6H
Port 6 Register (8 bits)
PECC0
FEC0H
60H
PEC Channel 0 Control Register
0000H
PECC1
FEC2H
61H
PEC Channel 1 Control Register
0000H
PECC2
FEC4H
62H
PEC Channel 2 Control Register
0000H
PECC3
FEC6H
63H
PEC Channel 3 Control Register
0000H
PECC4
FEC8H
64H
PEC Channel 4 Control Register
0000H
PECC5
FECAH
65H
PEC Channel 5 Control Register
0000H
PECC6
FECCH
66H
PEC Channel 6 Control Register
0000H
PECC7
FECEH
67H
PEC Channel 7 Control Register
0000H
CPU Program Status Word
0000H
PSW
b FF10H
88H
RP0H
b F108H
E 84H
00H
XXXXH
00H
System Startup Config. Reg. (Rd. only)
XXH
RTCH
F0D6H E 6BH
RTC High Register
XXXXH
RTCL
F0D4H E 6AH
RTC Low Register
XXXXH
S0BG
FEB4H
5AH
Serial Channel 0 Baud Rate Generator
Reload Register
0000H
S0CON
b FFB0H
D8H
Serial Channel 0 Control Register
0000H
S0EIC
b FF70H
B8H
Serial Channel 0 Error Interrupt Ctrl. Reg
0000H
FEB2H
59H
Serial Channel 0 Receive Buffer Reg.
(read only)
S0RIC
b FF6EH
B7H
Serial Channel 0 Receive Interrupt
Control Register
0000H
S0TBIC
b F19CH E CEH
Serial Channel 0 Transmit Buffer
Interrupt Control Register
0000H
S0RBUF
Data Sheet
30
XXH
V1.0, 2003-11
C161S
Functional Description
Table 6
C161S Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
S0TBUF
FEB0H
58H
Serial Channel 0 Transmit Buffer
Register (write only)
b FF6CH
B6H
Serial Channel 0 Transmit Interrupt
Control Register
0000H
SP
FE12H
09H
CPU System Stack Pointer Register
FC00H
SSCBR
F0B4H
E 5AH
SSC Baudrate Register
0000H
SSCCON
b FFB2H
D9H
SSC Control Register
0000H
SSCEIC
b FF76H
BBH
SSC Error Interrupt Control Register
0000H
SSCRB
F0B2H
E 59H
SSCRIC
b FF74H
BAH
SSCTB
F0B0H
E 58H
SSCTIC
b FF72H
STKOV
STKUN
S0TIC
Reset
Value
00H
SSC Receive Buffer
XXXXH
SSC Receive Interrupt Control Register
0000H
SSC Transmit Buffer
0000H
B9H
SSC Transmit Interrupt Control Register
0000H
FE14H
0AH
CPU Stack Overflow Pointer Register
FA00H
FE16H
0BH
CPU Stack Underflow Pointer Register
FC00H
SYSCON
b FF12H
89H
CPU System Configuration Register
SYSCON2
b F1D0H E E8H
CPU System Configuration Register 2
0000H
SYSCON3
b F1D4H E EAH
CPU System Configuration Register 3
0000H
1)
0XX0H
T14
F0D2H E 69H
RTC Timer 14 Register
XXXXH
T14REL
F0D0H E 68H
RTC Timer 14 Reload Register
XXXXH
T2
FE40H
20H
GPT1 Timer 2 Register
0000H
T2CON
b FF40H
A0H
GPT1 Timer 2 Control Register
0000H
T2IC
b FF60H
B0H
GPT1 Timer 2 Interrupt Control Register
0000H
FE42H
21H
GPT1 Timer 3 Register
0000H
T3CON
b FF42H
A1H
GPT1 Timer 3 Control Register
0000H
T3IC
b FF62H
B1H
GPT1 Timer 3 Interrupt Control Register
0000H
FE44H
22H
GPT1 Timer 4 Register
0000H
T4CON
b FF44H
A2H
GPT1 Timer 4 Control Register
0000H
T4IC
b FF64H
B2H
GPT1 Timer 4 Interrupt Control Register
0000H
FE46H
23H
GPT2 Timer 5 Register
0000H
b FF46H
A3H
GPT2 Timer 5 Control Register
0000H
T3
T4
T5
T5CON
Data Sheet
31
V1.0, 2003-11
C161S
Functional Description
Table 6
Name
C161S Registers, Ordered by Name (cont’d)
8-Bit Description
Addr.
Reset
Value
b FF66H
B3H
GPT2 Timer 5 Interrupt Control Register
0000H
FE48H
24H
GPT2 Timer 6 Register
0000H
T6CON
b FF48H
A4H
GPT2 Timer 6 Control Register
0000H
T6IC
b FF68H
B4H
GPT2 Timer 6 Interrupt Control Register
0000H
TFR
b FFACH
D6H
Trap Flag Register
0000H
FEAEH
57H
Watchdog Timer Register (read only)
0000H
WDTCON
b FFAEH
D7H
Watchdog Timer Control Register
XP0IC
b F186H
E C3H
Software Interrupt Control Register
0000H
XP1IC
b F18EH
E C7H
Software Interrupt Control Register
0000H
XP2IC
b F196H
E CBH
Software Interrupt Control Register
0000H
XP3IC
b F19EH
E CFH
RTC/PLL Interrupt Control Register
0000H
ZEROS
b FF1CH
8EH
Constant Value 0’s Register (read only)
0000H
T5IC
T6
WDT
Physical
Address
2)
00XXH
1) The system configuration is selected during reset.
2) The reset value depends on the indicated reset source.
Data Sheet
32
V1.0, 2003-11
C161S
Electrical Parameters
4
Electrical Parameters
4.1
Absolute Maximum Ratings
Table 7
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
Min.
Max.
TST
TJ
VDD
-65
150
°C
–
-40
150
°C
under bias
-0.5
6.5
V
–
Voltage on any pin with
respect to ground (VSS)
VIN
-0.5
VDD + 0.5 V
–
Input current on any pin
during overload condition
IOV
-10
10
mA
–
Absolute sum of all input
currents during overload
condition
Σ|IOV|
–
100
mA
–
Power dissipation
PDISS
–
1.5
W
–
Storage temperature
Junction temperature
Voltage on VDD pins with
respect to ground (VSS)
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
33
V1.0, 2003-11
C161S
Electrical Parameters
4.2
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C161S. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noticed.
Table 8
Operating Condition Parameters
Parameter
Standard
digital supply voltage
Reduced
digital supply voltage
Symbol
VDD
VDD
VSS
IOV
Overload current
Absolute sum of overload Σ|IOV|
Digital ground voltage
Limit Values
Unit
Notes
Min.
Max.
4.5
5.5
V
Active mode,
fCPUmax = 25 MHz
2.51)
5.5
V
Power down mode
3.0
3.6
V
Active mode,
fCPUmax = 20 MHz
2.51)
3.6
V
Power down mode
V
Reference voltage
0
–
±5
mA
Per pin2)3)
–
50
mA
3)
currents
External Load
Capacitance
CL
–
100
pF
–
Ambient temperature
TA
0
70
°C
SAB-C161S …
-40
85
°C
SAF-C161S …
-40
125
°C
SAK-C161S …
1) Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.
2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
3) Not subject to production test, verified by design/characterization.
Data Sheet
34
V1.0, 2003-11
C161S
Electrical Parameters
4.3
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C161S
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C161S will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the C161S.
Data Sheet
35
V1.0, 2003-11
C161S
Electrical Parameters
4.4
Table 9
DC Parameters
DC Characteristics (Standard Supply Voltage Range)
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
Min.
Unit Test Condition
Max.
Input low voltage (TTL,
all except XTAL1)
VIL
0.2 VDD V
- 0.1
–
Input low voltage XTAL1
VIL2 SR -0.5
0.3 VDD V
VIH SR 0.2 VDD VDD + V
–
Input high voltage (TTL,
all except RSTIN and XTAL1)
SR -0.5
+ 0.9
–
0.5
Input high voltage RSTIN
(when operated as input)
VIH1 SR 0.6 VDD VDD +
Input high voltage XTAL1
VIH2 SR 0.7 VDD VDD +
V
–
V
–
0.5
0.5
Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT,
RSTIN2))
VOL
CC –
0.45
V
IOL = 2.4 mA
Output low voltage
(all other outputs)
VOL1 CC –
0.45
V
IOL = 1.6 mA
Output high voltage3)
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT)
VOH CC 2.4
–
V
0.9 VDD –
V
IOH = -2.4 mA
IOH = -0.5 mA
Output high voltage3)
(all other outputs)
VOH1 CC 2.4
IOZ1 CC
Input leakage current (all other) IOZ2 CC
RSTIN inactive current4)
IRSTH5)
RSTIN active current4)
IRSTL6)
RD/WR inactive current7)
IRWH5)
IRWL6)
RD/WR active current7)
ALE inactive current7)
IALEL5)
ALE active current7)
IALEH6)
IP6H5)
Port 6 inactive current7)
Input leakage current (Port 5)
Data Sheet
–
V
0.9 VDD –
V
–
±200
nA
–
±500
nA
–
-10
µA
-100
–
µA
–
-40
µA
-500
–
µA
–
40
µA
500
–
µA
–
-40
µA
36
IOH = -1.6 mA
IOH = -0.5 mA
0 V < VIN < VDD
0.45 V < VIN < VDD
VIN = VIH1
VIN = VIL
VOUT = 2.4 V
VOUT = VOLmax
VOUT = VOLmax
VOUT = 2.4 V
VOUT = 2.4 V
V1.0, 2003-11
C161S
Electrical Parameters
Table 9
DC Characteristics (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
Min.
7)
Port 6 active current
PORT0 configuration current7)
XTAL1 input current
Pin capacitance8)
(digital inputs/outputs)
6)
IP6L
-500
IP0H5)
–
IP0L6)
-100
IIL
CC –
CIO CC –
Unit Test Condition
Max.
–
µA
-10
µA
–
µA
±20
µA
10
pF
VOUT = VOL1max
VIN = VIHmin
VIN = VILmax
0 V < VIN < VDD
f = 1 MHz,
TA = 25 °C
1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2) Valid in bidirectional reset mode only.
3) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
4) These parameters describe the RSTIN pull-up, which equals a resistance of ca. 50 to 250 kΩ.
5) The maximum current may be drawn while the respective signal line remains inactive.
6) The minimum current must be drawn in order to drive the respective signal line active.
7) This specification is only valid during Reset and Adapt Mode.
8) Not subject to production test, verified by design/characterization.
Data Sheet
37
V1.0, 2003-11
C161S
Electrical Parameters
Table 10
DC Characteristics (Reduced Supply Voltage Range)
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
Min.
Input low voltage (TTL,
all except XTAL1)
VIL
Input low voltage XTAL1
VIL2 SR -0.5
VIH SR 1.8
Input high voltage (TTL,
all except RSTIN and XTAL1)
SR -0.5
Unit Test Condition
Max.
0.8
V
–
0.3 VDD V
–
VDD +
V
–
V
–
V
–
0.5
Input high voltage RSTIN
(when operated as input)
VIH1 SR 0.6 VDD VDD +
Input high voltage XTAL1
VIH2 SR 0.7 VDD VDD +
0.5
0.5
Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT,
RSTIN2))
VOL
CC –
0.45
V
IOL = 1.6 mA
Output low voltage
(all other outputs)
VOL1 CC –
0.45
V
IOL = 1.0 mA
Output high voltage3)
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT)
VOH CC 0.9 VDD –
V
IOH = -0.5 mA
Output high voltage3)
(all other outputs)
VOH1 CC 0.9 VDD –
V
IOH = -0.25 mA
IOZ1 CC
Input leakage current (all other) IOZ2 CC
RSTIN inactive current4)
IRSTH5)
RSTIN active current4)
IRSTL6)
RD/WR inactive current7)
IRWH5)
IRWL6)
RD/WR active current7)
ALE inactive current7)
IALEL5)
ALE active current7)
IALEH6)
IP6H5)
Port 6 inactive current7)
IP6L6)
Port 6 active current7)
Input leakage current (Port 5)
Data Sheet
–
±200
nA
0 V < VIN < VDD
–
±500
nA
0.45 V < VIN < VDD
–
-10
µA
-100
–
µA
–
-10
µA
-500
–
µA
–
20
µA
500
–
µA
–
-10
µA
-500
–
µA
VIN = VIH1
VIN = VIL
VOUT = 2.4 V
VOUT = VOLmax
VOUT = VOLmax
VOUT = 2.4 V
VOUT = 2.4 V
VOUT = VOL1max
38
V1.0, 2003-11
C161S
Electrical Parameters
Table 10
DC Characteristics (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
Min.
PORT0 configuration current
7)
XTAL1 input current
Pin capacitance8)
(digital inputs/outputs)
5)
IP0H
–
IP0L6)
-100
IIL
CC –
CIO CC –
Unit Test Condition
Max.
-5
µA
–
µA
±20
µA
10
pF
VIN = VIHmin
VIN = VILmax
0 V < VIN < VDD
f = 1 MHz,
TA = 25 °C
1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2) Valid in bidirectional reset mode only.
3) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
4) These parameters describe the RSTIN pull-up, which equals a resistance of ca. 50 to 250 kΩ.
5) The maximum current may be drawn while the respective signal line remains inactive.
6) The minimum current must be drawn in order to drive the respective signal line active.
7) This specification is only valid during Reset and Adapt Mode.
8) Not subject to production test, verified by design/characterization.
Data Sheet
39
V1.0, 2003-11
C161S
Electrical Parameters
Table 11
Power Consumption C161S (Standard Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Max.
Unit Test Condition
Power supply current (active)
with all peripherals active
IDD5
–
15 +
mA
1.8 × fCPU
RSTIN = VIL2
fCPU in [MHz]1)
Idle mode supply current
with all peripherals active
IIDX5
–
3+
mA
0.6 × fCPU
Idle mode supply current
with all peripherals deactivated,
PLL off, SDD factor = 32
IIDO52)
–
500 +
µA
50 × fOSC
RSTIN = VIH1
fCPU in [MHz]1)
RSTIN = VIH1
fOSC in [MHz]1)
Sleep and Power down mode
IPDR52)
supply current with RTC running
–
200 +
µA
25 × fOSC
Sleep and Power down mode
IPDO5
supply current with RTC disabled
–
50
µA
VDD = VDDmax
fOSC in [MHz]3)
VDD = VDDmax3)
1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 8.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2) This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current,
however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a
typical circuitry and may change in case of a not optimized external oscillator circuitry.
3) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
Data Sheet
40
V1.0, 2003-11
C161S
Electrical Parameters
Table 12
Power Consumption C161S (Reduced Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Max.
Unit Test Condition
Power supply current (active)
with all peripherals active
IDD3
–
7+
mA
1.2 × fCPU
RSTIN = VIL2
fCPU in [MHz]1)
Idle mode supply current
with all peripherals active
IIDX3
–
1+
mA
0.4 × fCPU
Idle mode supply current
with all peripherals deactivated,
PLL off, SDD factor = 32
IIDO32)
–
300 +
µA
30 × fOSC
RSTIN = VIH1
fCPU in [MHz]1)
RSTIN = VIH1
fOSC in [MHz]1)
Sleep and Power down mode
IPDR32)
supply current with RTC running
–
100 +
µA
10 × fOSC
Sleep and Power down mode
IPDO3
supply current with RTC disabled
–
30
µA
VDD = VDDmax
fOSC in [MHz]3)
VDD = VDDmax3)
1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 8.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2) This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current,
however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a
typical circuitry and may change in case of a not optimized external oscillator circuitry.
3) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
Data Sheet
41
V1.0, 2003-11
C161S
Electrical Parameters
I [mA]
IDD5max
100
IDD5typ
80
IDD3max
60
IDD3typ
40
IIDX5max
IIDX5typ
20
IIDX3max
IIDX3typ
10
Figure 8
Data Sheet
20
30
40
fCPU [MHz]
Supply and Idle Current as a Function of Operating Frequency
42
V1.0, 2003-11
C161S
Electrical Parameters
I [µA]
3000
IIDO5max
2500
IIDO5typ
IIDO3max
IIDO3typ
IPDR5max
1500
1000
IPDR3max
500
IPDOmax
10
Figure 9
Data Sheet
20
30
40
fOSC [MHz]
Sleep and Power Down Supply Current as a Function of Oscillator
Frequency
43
V1.0, 2003-11
C161S
Timing Characteristics
5
Timing Characteristics
5.1
Definition of Internal Timing
The internal operation of the C161S is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).
Phase Locked Loop Operation
fOSC
TCL
fCPU
TCL
Direct Clock Drive
fOSC
TCL
fCPU
TCL
Prescaler Operation
fOSC
TCL
fCPU
TCL
Figure 10
MCT04338
Generation Mechanisms for the CPU Clock
The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate fCPU. This influence must
be regarded when calculating the timings for the C161S.
Note: The example for PLL operation shown in Figure 10 refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
Data Sheet
44
V1.0, 2003-11
C161S
Timing Characteristics
levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 13 associates the combinations of these three bits with the respective clock
generation mode.
Table 13
C161S Clock Generation Modes
CLKCFG
(P0H.7-5)
CPU Frequency External Clock
fCPU = fOSC × F
Input Range1)
Notes
111
fOSC × 4
fOSC × 3
fOSC × 2
fOSC × 5
fOSC × 1
fOSC × 1.5
fOSC / 2
fOSC × 2.5
2.5 to 6.25 MHz
Default configuration
3.33 to 8.33 MHz
–
5 to 12.5 MHz
–
2 to 5 MHz
–
1 to 25 MHz
Direct drive2)
6.66 to 16.67 MHz
–
2 to 50 MHz
CPU clock via prescaler
4 to 10 MHz
–
110
101
100
011
010
001
000
1) The external clock input range refers to a CPU clock range of 10 … 25 MHz (PLL operation). If the on-chip
oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 16 MHz.
2) The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001B) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of fOSC for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see Table 13). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU
= fOSC × F). With every F’th transition of fOSC the PLL circuit synchronizes the CPU clock
to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency
does not change abruptly.
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so
it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the
duration of individual TCLs.
Data Sheet
45
V1.0, 2003-11
C161S
Timing Characteristics
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 11).
For a period of N × TCL the minimum value is computed using the corresponding
deviation DN:
(N × TCL)min = N × TCLNOM - DN, DN [ns] = ±(13.3 + N × 6.3) / fCPU [MHz]
(1)
where N = number of consecutive TCLs and 1 ≤ N ≤ 40.
So for a period of 3 TCLs @ 20 MHz (i.e. N = 3): D3 = (13.3 + 3 × 6.3) / 20 = 1.61 ns,
and (3TCL)min = 3TCLNOM - 1.61 ns = 73.39 ns (@ fCPU = 20 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 11).
Max. jitter DN
ns
±30
This approximated formula is valid for
1<
–N<
– 40 and 10 MHz <
– fCPU <
– 25 MHz.
10 MHz
±26.5
±20
16 MHz
20 MHz
25 MHz
±10
±1
1
10
20
30
40
N
MCD04455
Figure 11
Data Sheet
Approximated Maximum Accumulated PLL Jitter
46
V1.0, 2003-11
C161S
Timing Characteristics
Direct Drive
When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of fCPU directly follows the frequency of fOSC so the high and low time of
fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fOSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCLmin = 1/fOSC × DCmin (DC = duty cycle)
(2)
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated
so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin therefore has to be
used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/fOSC.
Data Sheet
47
V1.0, 2003-11
C161S
Timing Characteristics
5.2
External Clock Drive XTAL1
Table 14
Parameter
External Clock Drive XTAL1 (Operating Conditions apply)
Symbol
Direct Drive
1:1
Min.
Max.
Min.
Max.
–
20
–
601)
5001)
ns
SR 203)
–
5
–
10
–
ns
SR 203)
–
5
–
10
–
ns
SR –
8
–
5
–
10
ns
SR –
8
–
5
–
10
ns
High time2)
t1
t2
t3
t4
2)
Fall time
Unit
Min.
tOSC SR 40
Rise time2)
PLL
1:N
Max.
Oscillator
period
Low time2)
Prescaler
2:1
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock
generation mode. Please see respective table above.
2) The clock input signal must reach the defined levels VIL2 and VIH2.
3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in
direct drive mode depends on the duty cycle of the clock input signal.
t1
t3
t4
VIH2
0.5 VDD
VIL
t2
t OSC
MCT02534
Figure 12
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is verified by design
only (not tested in production).
Data Sheet
48
V1.0, 2003-11
C161S
Timing Characteristics
5.3
Testing Waveforms
2.4 V
1.8 V
1.8 V
Test Points
0.8 V
’
0.8 V
0.45 V
’
’
AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’.
Timing measurements are made at VIH min for a logic 1’ and VIL max for a logic 0’.
’
MCA04414
Figure 13
Input Output Waveforms
VLoad + 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA).
MCA00763
Figure 14
Data Sheet
Float Waveforms
49
V1.0, 2003-11
C161S
Timing Characteristics
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
Table 15 describes, how these variables are to be computed.
Table 15
Memory Cycle Variables
Description
Symbol
Values
ALE Extension
tA
tC
tF
TCL × <ALECTL>
Memory Cycle Time Waitstates
Memory Tristate Time
2TCL × (15 - <MCTC>)
2TCL × (1 - <MTTC>)
Note: Please respect the maximum operating frequency of the respective derivative.
5.4
AC Characteristics
Table 16
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
Min.
Max.
Min.
Max.
ALE high time
t5
CC 10 + tA
–
TCL - 10
+ tA
–
ns
Address setup to ALE
t6
CC 4 + tA
–
TCL - 16
+ tA
–
ns
Address hold after ALE
t7
CC 10 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 10 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA –
-10 + tA
–
ns
Address float after RD,
WR (with RW-delay)
t10
CC –
6
–
6
ns
Address float after RD,
WR (no RW-delay)
t11
CC –
26
–
TCL + 6
ns
Data Sheet
50
V1.0, 2003-11
C161S
Timing Characteristics
Table 16
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
Min.
Max.
Min.
Max.
RD, WR low time
(with RW-delay)
t12
CC 30 + tC
–
2TCL - 10 –
+ tC
ns
RD, WR low time
(no RW-delay)
t13
CC 50 + tC
–
3TCL - 10 –
+ tC
ns
RD to valid data in
(with RW-delay)
t14
SR –
20 + tC
–
2TCL - 20 ns
+ tC
RD to valid data in
(no RW-delay)
t15
SR –
40 + tC
–
3TCL - 20 ns
+ tC
ALE low to valid data in
t16
SR –
40 + tA
+ tC
–
3TCL - 20 ns
+ tA + tC
Address to valid data in
t17
SR –
50 + 2tA –
+ tC
4TCL - 30 ns
+ 2tA + tC
Data hold after RD
rising edge
t18
SR 0
–
0
–
Data float after RD
t19
SR –
26 + tF
–
2TCL - 14 ns
+ tF
Data valid to WR
t22
CC 20 + tC
–
2TCL - 20 –
+ tC
ns
Data hold after WR
t23
CC 26 + tF
–
2TCL - 14 –
+ tF
ns
ALE rising edge after RD, t25
WR
CC 26 + tF
–
2TCL - 14 –
+ tF
ns
t27
CC 26 + tF
–
2TCL - 14 –
+ tF
ns
CC -4 - tA
10 - tA
-4 - tA
10 - tA
ns
CS low to Valid Data In
t38
t39
SR –
40 + tC
+ 2tA
–
3TCL - 20 ns
+ tC + 2tA
CS hold after RD, WR1)
t40
CC 46 + tF
–
3TCL - 14 –
+ tF
Address hold after RD,
WR
ALE falling edge to CS1)
1)
Data Sheet
51
ns
ns
V1.0, 2003-11
C161S
Timing Characteristics
Table 16
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
Min.
Max.
Min.
Max.
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42
CC 16 + tA
–
TCL - 4
+ tA
–
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43
CC -4 + tA
–
-4
+ tA
–
ns
Address float after
RdCS, WrCS (with RW
delay)
t44
CC –
0
–
0
ns
Address float after
RdCS, WrCS (no RW
delay)
t45
CC –
20
–
TCL
ns
RdCS to Valid Data In
(with RW delay)
t46
SR –
16 + tC
–
2TCL - 24 ns
+ tC
RdCS to Valid Data In
(no RW delay)
t47
SR –
36 + tC
–
3TCL - 24 ns
+ tC
RdCS, WrCS Low Time
(with RW delay)
t48
CC 30 + tC
–
2TCL - 10 –
+ tC
ns
RdCS, WrCS Low Time
(no RW delay)
t49
CC 50 + tC
–
3TCL - 10 –
+ tC
ns
Data valid to WrCS
t50
CC 26 + tC
–
2TCL - 14 –
+ tC
ns
Data hold after RdCS
t51
t52
SR 0
–
0
–
ns
SR –
20 + tF
–
2TCL - 20 ns
+ tF
Address hold after
RdCS, WrCS
t54
CC 20 + tF
–
2TCL - 20 –
+ tF
ns
Data hold after WrCS
t56
CC 20 + tF
–
2TCL - 20 –
+ tF
ns
Data float after RdCS
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
52
V1.0, 2003-11
C161S
Timing Characteristics
Table 17
Multiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
Min.
Max.
Min.
Max.
ALE high time
t5
CC 11 + tA
–
TCL - 14
+ tA
–
ns
Address setup to ALE
t6
CC 5 + tA
–
TCL - 20
+ tA
–
ns
Address hold after ALE
t7
CC 15 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 15 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA –
-10 + tA
–
ns
Address float after RD,
WR (with RW-delay)
t10
CC –
6
–
6
ns
Address float after RD,
WR (no RW-delay)
t11
CC –
31
–
TCL + 6
ns
RD, WR low time
(with RW-delay)
t12
CC 34 + tC
–
2TCL - 16 –
+ tC
ns
RD, WR low time
(no RW-delay)
t13
CC 59 + tC
–
3TCL - 16 –
+ tC
ns
RD to valid data in
(with RW-delay)
t14
SR –
22 + tC
–
2TCL - 28 ns
+ tC
RD to valid data in
(no RW-delay)
t15
SR –
47 + tC
–
3TCL - 28 ns
+ tC
ALE low to valid data in
t16
SR –
45 + tA
+ tC
–
3TCL - 30 ns
+ tA + tC
Address to valid data in
t17
SR –
57 + 2tA –
+ tC
4TCL - 43 ns
+ 2tA + tC
Data hold after RD
rising edge
t18
SR 0
–
0
–
Data float after RD
t19
SR –
36 + tF
–
2TCL - 14 ns
+ tF
Data Sheet
53
ns
V1.0, 2003-11
C161S
Timing Characteristics
Table 17
Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
Min.
Max.
Min.
Max.
Data valid to WR
t22
CC 24 + tC
–
2TCL - 26 –
+ tC
ns
Data hold after WR
t23
CC 36 + tF
–
2TCL - 14 –
+ tF
ns
ALE rising edge after RD, t25
WR
CC 36 + tF
–
2TCL - 14 –
+ tF
ns
Address hold after RD,
WR
t27
CC 36 + tF
–
2TCL - 14 –
+ tF
ns
ALE falling edge to CS1)
CC -8 - tA
10 - tA
-8 - tA
10 - tA
ns
CS low to Valid Data In1)
t38
t39
SR –
47 + tC
+ 2tA
–
3TCL - 28 ns
+ tC + 2tA
CS hold after RD, WR1)
t40
CC 57 + tF
–
3TCL - 18 –
+ tF
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42
CC 19 + tA
–
TCL - 6
+ tA
–
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43
CC -6 + tA
–
-6
+ tA
–
ns
Address float after
RdCS, WrCS (with RW
delay)
t44
CC –
0
–
0
ns
Address float after
RdCS, WrCS (no RW
delay)
t45
CC –
25
–
TCL
ns
RdCS to Valid Data In
(with RW delay)
t46
SR –
20 + tC
–
2TCL - 30 ns
+ tC
RdCS to Valid Data In
(no RW delay)
t47
SR –
45 + tC
–
3TCL - 30 ns
+ tC
RdCS, WrCS Low Time
(with RW delay)
t48
CC 38 + tC
–
2TCL - 12 –
+ tC
ns
RdCS, WrCS Low Time
(no RW delay)
t49
CC 63 + tC
–
3TCL - 12 –
+ tC
ns
Data Sheet
54
V1.0, 2003-11
C161S
Timing Characteristics
Table 17
Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
Min.
Max.
Min.
Max.
Data valid to WrCS
t50
CC 28 + tC
–
2TCL - 22 –
+ tC
ns
Data hold after RdCS
t51
t52
SR 0
–
0
–
ns
SR –
30 + tF
–
2TCL - 20 ns
+ tF
Address hold after
RdCS, WrCS
t54
CC 30 + tF
–
2TCL - 20 –
+ tF
ns
Data hold after WrCS
t56
CC 30 + tF
–
2TCL - 20 –
+ tF
ns
Data float after RdCS
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
55
V1.0, 2003-11
C161S
Timing Characteristics
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
A23-A16
(A15-A8)
BHE, CSxE
t27
Address
t6
t7
t54
t19
Read Cycle
BUS
t18
Address
t8
Data In
t10
t14
RD
t42
t44
t12
t51
t52
t46
RdCSx
t48
Write Cycle
BUS
t23
Address
t8
WR,
WRL,
WRH
t42
Data Out
t56
t10
t22
t12
t44
t50
WrCSx
t48
Figure 15
Data Sheet
External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Normal ALE
56
V1.0, 2003-11
C161S
Timing Characteristics
t5
t16
t25
t39
t40
t17
t27
ALE
t38
CSxL
A23-A16
(A15-A8)
BHE, CSxE
Address
t6
t7
t54
t19
Read Cycle
BUS
t18
Address
Data In
t10
t8
t14
RD
t44
t42
t12
t51
t52
t46
RdCSx
t48
Write Cycle
BUS
t23
Address
Data Out
t8
WR,
WRL,
WRH
t56
t10
t44
t42
t22
t12
t50
WrCSx
t48
Figure 16
External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Extended ALE
Data Sheet
57
V1.0, 2003-11
C161S
Timing Characteristics
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
A23-A16
(A15-A8)
BHE, CSxE
t27
Address
t6
t7
t54
t19
Read Cycle
BUS
t18
Address
t9
Data In
t11
t15
RD
t43
t13
t45
t51
t52
t47
RdCSx
t49
Write Cycle
BUS
t23
Address
t9
WR,
WRL,
WRH
t43
Data Out
t56
t11
t22
t45
t13
t50
WrCSx
t49
Figure 17
Data Sheet
External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Normal ALE
58
V1.0, 2003-11
C161S
Timing Characteristics
t5
t16
t25
t39
t40
t17
t27
ALE
t38
CSxL
A23-A16
(A15-A8)
BHE, CSxE
Address
t6
t7
t54
t19
Read Cycle
BUS
t18
Address
Data In
t9
t11
RD
t15
t13
t43
t45
RdCSx
t51
t52
t47
t49
Write Cycle
BUS
t23
Address
Data Out
t56
t9
WR,
WRL,
WRH
t11
t22
t13
t43
t45
t50
WrCSx
t49
Figure 18
Data Sheet
External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Extended ALE
59
V1.0, 2003-11
C161S
Timing Characteristics
Table 18
Demultiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
Min.
Max.
Min.
Max.
ALE high time
t5
CC 10 + tA
–
TCL - 10
+ tA
–
ns
Address setup to ALE
t6
CC 4 + tA
–
TCL - 16
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 10 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA –
-10
+ tA
–
ns
RD, WR low time
(with RW-delay)
t12
CC 30 + tC
–
2TCL - 10 –
+ tC
ns
RD, WR low time
(no RW-delay)
t13
CC 50 + tC
–
3TCL - 10 –
+ tC
ns
RD to valid data in
(with RW-delay)
t14
SR –
20 + tC
–
2TCL - 20 ns
+ tC
RD to valid data in
(no RW-delay)
t15
SR –
40 + tC
–
3TCL - 20 ns
+ tC
ALE low to valid data in
t16
SR –
40 +
tA + t C
–
3TCL - 20 ns
+ tA + tC
Address to valid data in
t17
SR –
50 +
2 tA + tC
–
4TCL - 30 ns
+ 2tA + tC
Data hold after RD
rising edge
t18
SR 0
–
0
–
Data float after RD rising t20
edge (with RW-delay1))
SR –
26 +
–
1)
2 tA + tF
2TCL - 14 ns
+ 22tA
+ tF1)
Data float after RD rising t21
edge (no RW-delay1))
SR –
10 +
–
1)
2 tA + tF
TCL - 10
+ 22tA
+ tF1)
CC 20 + tC
–
Data valid to WR
Data Sheet
t22
60
2TCL - 20 –
+ tC
ns
ns
ns
V1.0, 2003-11
C161S
Timing Characteristics
Table 18
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
Min.
Data hold after WR
t24
CC 10 + tF
Max.
Min.
Max.
–
TCL - 10
+ tF
–
ns
ALE rising edge after RD, t26
WR
CC -10 + tF –
-10 + tF
–
ns
Address hold after WR2)
CC 0 + tF
–
0 + tF
–
ns
CC -4 - tA
10 - tA
-4 - tA
10 - tA
ns
CS low to Valid Data In3)
t28
t38
t39
SR –
40 +
tC + 2tA
–
3TCL - 20 ns
+ tC + 2tA
CS hold after RD, WR3)
t41
CC 6 + tF
–
TCL - 14
+ tF
–
ns
ALE falling edge to
RdCS, WrCS (with
RW-delay)
t42
CC 16 + tA
–
TCL - 4
+ tA
–
ns
ALE falling edge to
RdCS, WrCS (no
RW-delay)
t43
CC -4 + tA
–
-4
+ tA
–
ns
RdCS to Valid Data In
(with RW-delay)
t46
SR –
16 + tC
–
2TCL - 24 ns
+ tC
RdCS to Valid Data In
(no RW-delay)
t47
SR –
36 + tC
–
3TCL - 24 ns
+ tC
RdCS, WrCS Low Time
(with RW-delay)
t48
CC 30 + tC
–
2TCL - 10 –
+ tC
ns
RdCS, WrCS Low Time
(no RW-delay)
t49
CC 50 + tC
–
3TCL - 10 –
+ tC
ns
Data valid to WrCS
t50
CC 26 + tC
–
2TCL - 14 –
+ tC
ns
Data hold after RdCS
t51
t53
SR 0
–
0
–
ns
SR –
20 + tF
–
2TCL - 20 ns
+ 2tA + tF1)
ALE falling edge to CS3)
Data float after RdCS
(with RW-delay)1)
Data Sheet
61
V1.0, 2003-11
C161S
Timing Characteristics
Table 18
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
Min.
Max.
Min.
Max.
Data float after RdCS
(no RW-delay)1)
t68
SR –
0 + tF
–
TCL - 20
ns
1)
+ 2tA + tF
Address hold after
RdCS, WrCS
t55
CC -6 + tF
–
-6 + tF
–
ns
Data hold after WrCS
t57
CC 6 + tF
–
TCL - 14
+ tF
–
ns
1) RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
62
V1.0, 2003-11
C161S
Timing Characteristics
Table 19
Demultiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
Min.
Max.
Min.
Max.
ALE high time
t5
CC 11 + tA
–
TCL - 14
+ tA
–
ns
Address setup to ALE
t6
CC 5 + tA
–
TCL - 20
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 15 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA –
-10
+ tA
–
ns
RD, WR low time
(with RW-delay)
t12
CC 34 + tC
–
2TCL - 16 –
+ tC
ns
RD, WR low time
(no RW-delay)
t13
CC 59 + tC
–
3TCL - 16 –
+ tC
ns
RD to valid data in
(with RW-delay)
t14
SR –
22 + tC
–
2TCL - 28 ns
+ tC
RD to valid data in
(no RW-delay)
t15
SR –
47 + tC
–
3TCL - 28 ns
+ tC
ALE low to valid data in
t16
SR –
45 +
tA + t C
–
3TCL - 30 ns
+ tA + tC
Address to valid data in
t17
SR –
57 +
2 tA + tC
–
4TCL - 43 ns
+ 2tA + tC
Data hold after RD
rising edge
t18
SR 0
–
0
–
Data float after RD rising t20
edge (with RW-delay1))
SR –
36 +
–
1)
2 tA + tF
2TCL - 14 ns
+ 22tA
+ tF1)
Data float after RD rising t21
edge (no RW-delay1))
SR –
15 +
–
1)
2 tA + tF
TCL - 10
+ 22tA
+ tF1)
CC 24 + tC
–
Data valid to WR
Data Sheet
t22
63
2TCL - 26 –
+ tC
ns
ns
ns
V1.0, 2003-11
C161S
Timing Characteristics
Table 19
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
Min.
Data hold after WR
t24
CC 15 + tF
Max.
Min.
Max.
–
TCL - 10
+ tF
–
ns
ALE rising edge after RD, t26
WR
CC -12 + tF –
-12 + tF
–
ns
Address hold after WR2)
CC 0 + tF
–
0 + tF
–
ns
CC -8 - tA
10 - tA
-8 - tA
10 - tA
ns
CS low to Valid Data In3)
t28
t38
t39
SR –
47 +
tC + 2tA
–
3TCL - 28 ns
+ tC + 2tA
CS hold after RD, WR3)
t41
CC 9 + tF
–
TCL - 16
+ tF
–
ns
ALE falling edge to
RdCS, WrCS (with
RW-delay)
t42
CC 19 + tA
–
TCL - 6
+ tA
–
ns
ALE falling edge to
RdCS, WrCS (no
RW-delay)
t43
CC -6 + tA
–
-6
+ tA
–
ns
RdCS to Valid Data In
(with RW-delay)
t46
SR –
20 + tC
–
2TCL - 30 ns
+ tC
RdCS to Valid Data In
(no RW-delay)
t47
SR –
45 + tC
–
3TCL - 30 ns
+ tC
RdCS, WrCS Low Time
(with RW-delay)
t48
CC 38 + tC
–
2TCL - 12 –
+ tC
ns
RdCS, WrCS Low Time
(no RW-delay)
t49
CC 63 + tC
–
3TCL - 12 –
+ tC
ns
Data valid to WrCS
t50
CC 28 + tC
–
2TCL - 22 –
+ tC
ns
Data hold after RdCS
t51
t53
SR 0
–
0
–
ns
SR –
30 + tF
–
2TCL - 20 ns
+ 2tA + tF1)
ALE falling edge to CS3)
Data float after RdCS
(with RW-delay)1)
Data Sheet
64
V1.0, 2003-11
C161S
Timing Characteristics
Table 19
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
Min.
Max.
Min.
Max.
5 + tF
–
TCL - 20
ns
1)
+ 2tA + tF
Data float after RdCS
(no RW-delay)1)
t68
SR –
Address hold after
RdCS, WrCS
t55
CC -16 + tF –
-16 + tF
–
ns
Data hold after WrCS
t57
CC 9 + tF
TCL - 16
+ tF
–
ns
–
1) RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
65
V1.0, 2003-11
C161S
Timing Characteristics
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE, CSxE
t28
Address
t6
t55
t20
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t8
t14
RD
t12
t42
RdCSx
t51
t53
t46
t48
Write Cycle
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
t24
Data Out
t57
t8
t22
t12
t42
t50
WrCSx
t48
Figure 19
Data Sheet
External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Normal ALE
66
V1.0, 2003-11
C161S
Timing Characteristics
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE,
CSxE
t28
Address
t6
t55
t20
Read Cycle
BUS
(D15-D8)
D7-D0
t18
Data In
t8
t14
RD
t12
t42
t51
t53
t46
RdCSx
t48
Write Cycle
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
t24
Data Out
t57
t8
t22
t12
t42
t50
WrCSx
t48
Figure 20
Data Sheet
External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Extended ALE
67
V1.0, 2003-11
C161S
Timing Characteristics
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE, CSxE
t28
Address
t6
Read Cycle
BUS
(D15-D8)
D7-D0
t55
t21
t18
Data In
t9
t15
RD
t43
t13
t51
t68
t47
RdCSx
t49
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t9
t22
WR,
WRL,
WRH
t13
t50
t43
WrCSx
t49
Figure 21
External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Normal ALE
Data Sheet
68
V1.0, 2003-11
C161S
Timing Characteristics
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE, CSxE
t28
Address
t6
t55
t21
Read Cycle
BUS
(D15-D8)
D7-D0
t18
Data In
t9
t15
RD
t13
t43
t51
t68
t47
RdCSx
t49
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t9
t22
WR,
WRL, WRH
t13
t43
t50
WrCSx
t49
Figure 22
Data Sheet
External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Extended ALE
69
V1.0, 2003-11
C161S
Package Outlines
0.88 ±0.15
C
12.35
7˚ MAX.
H
0.65
0.3 ±0.08
0.15 +0.08
-0.02
2.45 MAX.
2 +0.1
-0.05
Package Outlines
0.25 MIN.
6
0.1
0.12 M A-B D C 80x
17.2
0.2 A-B D 4x
14 1)
0.2 A-B D H 4x
D
14 1)
17.2
B
A
80
Index Marking
1)
1
0.6 x 45˚
Does not include plastic or metal protrusion of 0.25 max. per side
GPM05249
Figure 23
P-MQFP-80-7 (Plastic Metric Quad Flat Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
70
V1.0, 2003-11
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG