FEATURES FUNCTIONAL BLOCK DIAGRAM For more information about the ADM1063 register map, refer to the AN-698 Application Note at www.analog.com. Rev. A REFIN REFOUT REFGND SDA SCL A1 D1P D1N D2P D2N TEMP SENSOR VREF INTERNAL DIODE MUX Complete supervisory and sequencing solution for up to 10 supplies Extended temperature range: −40°C to +105°C 10 supply fault detectors enable supervision of supplies to <0.5% accuracy at all voltages at 25°C <1.0% accuracy across all voltages and temperatures 5 selectable input attenuators allow supervision of supplies to 14.4 V on VH 6 V on VP1 to VP4 (VPx) 5 dual-function inputs, VX1 to VX5 (VXx) High impedance input to supply fault detector with thresholds between 0.573 V and 1.375 V General-purpose logic input 10 programmable driver outputs, PDO1 to PDO10 (PDOx) Open-collector with external pull-up Push/pull output, driven to VDDCAP or VPx Open collector with weak pull-up to VDDCAP or VPx Internally charge-pumped high drive for use with external N-FET (PDO1 to PDO6 only) Sequencing engine (SE) implements state machine control of PDOx outputs State changes conditional on input events Enables complex control of boards Power-up and power-down sequence control Fault event handling Interrupt generation on warnings Watchdog function can be integrated in SE Program software control of sequencing through SMBus Complete voltage margining solution for 6 voltage rails 12-bit ADC for readback of all supervised voltages 1 internal and 2 external temperature sensors Reference input (REFIN) has 2 input options Driven directly from 2.048 V (±0.25%) REFOUT pin More accurate external reference for improved ADC performance Device powered by the highest of VPx, VH for improved redundancy User EEPROM: 256 bytes Industry-standard, 2-wire bus interface (SMBus) Guaranteed PDO low with VH, VPx = 1.2 V Available in 40-lead, 6 mm × 6 mm LFCSP package A0 SMBus INTERFACE 12-BIT SAR ADC EEPROM CLOSED-LOOP MARGINING SYSTEM VX1 VX2 VX3 VX4 VX5 PDO1 DUALFUNCTION INPUTS CONFIGURABLE OUTPUT DRIVERS (LOGIC INPUTS OR SFDs) (HV CAPABLE OF DRIVING GATES OF N-FET) PDO6 CONFIGURABLE OUTPUT DRIVERS PDO8 (LV CAPABLE OF DRIVING LOGIC SIGNALS) PDO10 PDO2 PDO3 PDO4 PDO5 SEQUENCING ENGINE VP1 VP3 PROGRAMMABLE RESET GENERATORS VP4 (SFDs) VP2 VH PDO7 PDO9 PDOGND AGND VDD ARBITRATOR ADM1063-EP VCCP GND VDDCAP 09116-001 Data Sheet Multisupply Supervisor/Sequencer with ADC and Temperature Monitoring ADM1063-EP Figure 1. APPLICATIONS Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies GENERAL DESCRIPTION The ADM1063-EP is a configurable supervisory/sequencing device that offers a single-chip solution for supply monitoring and sequencing in multiple supply systems. In addition to these functions, the ADM1063-EP integrates a 12-bit ADC that can be used to accurately read back up to 12 separate voltages. The device also provides up to 10 programmable inputs for monitoring undervoltage faults, overvoltage faults, or out-ofwindow faults on up to 10 supplies. In addition, 10 programmable outputs can be used as logic enables. Six of these programmable outputs can provide up to a 12 V output for driving the gate of an N-FET that can be placed in the path of a supply. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADM1063-EP Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................7 Functional Block Diagram .............................................................. 1 ESD Caution...................................................................................7 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................8 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................9 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 12 Detailed Block Diagram .................................................................. 3 Ordering Guide .......................................................................... 12 Specifications..................................................................................... 4 Absolute Maximum Ratings ............................................................ 7 REVISION HISTORY 8/13—Rev. 0 to Rev. A Changes to Serial Bus Timing Parameters; Table 1 ...................... 6 Updated Outline Dimensions ....................................................... 12 5/10—Revision 0: Initial Version Rev. A | Page 2 of 12 Data Sheet ADM1063-EP Temperature measurement is possible with the ADM1063-EP. The device contains one internal temperature sensor and two pairs of differential inputs for remote thermal diodes. These are measured by the 12-bit ADC. The device is controlled via configuration data that can be programmed into an EEPROM. The entire configuration can be programmed using an intuitive GUI-based software package provided by Analog Devices, Inc. The logical core of the device is a sequencing engine. This statemachine-based construction provides up to 63 different states. This design enables very flexible sequencing of the outputs based on the condition of the inputs. Full details about this enhanced product are available in the ADM1063 data sheet, which should be consulted in conjunction with this data sheet. DETAILED BLOCK DIAGRAM REFIN REFOUT D1P D1N D2P D2N REFGND SDA SCL A1 A0 ADM1063-EP TEMP SENSOR INTERNAL DIODE VREF SMBus INTERFACE OSC 12-BIT SAR ADC DEVICE CONTROLLER EEPROM GPI SIGNAL CONDITIONING VX1 CONFIGURABLE OUTPUT DRIVER (HV) SFD PDO1 PDO2 PDO3 VX2 VX3 PDO4 VX4 PDO5 GPI SIGNAL CONDITIONING SEQUENCING ENGINE VX5 VP1 CONFIGURABLE OUTPUT DRIVER (HV) PDO6 CONFIGURABLE OUTPUT DRIVER (LV) PDO7 SFD SELECTABLE ATTENUATOR SFD VP2 VP3 PDO8 VP4 PDO9 VH SELECTABLE ATTENUATOR SFD PDO10 PDOGND AGND REG 5.25V CHARGE PUMP VDD ARBITRATOR GND VCCP 09116-002 VDDCAP CONFIGURABLE OUTPUT DRIVER (LV) Figure 2. Rev. A | Page 3 of 12 ADM1063-EP Data Sheet SPECIFICATIONS VH = 3.0 V to 14.4 V 1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +105°C, unless otherwise noted. Table 1. Parameter POWER SUPPLY ARBITRATION VH, VPx VPx VH VDDCAP CVDDCAP POWER SUPPLY Supply Current, IVH, IVPx Additional Currents All PDO FET Drivers On Min Typ Max Unit Test Conditions/Comments 4.75 6.0 14.4 5.4 V V V V µF Minimum supply required on one of VH, VPx Maximum VDDCAP = 5.1 V, typical VDDCAP = 4.75 V Regulated LDO output Minimum recommended decoupling capacitance 4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO10 off, ADC off mA 3.0 2.7 10 1 1 10 mA mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 µA each, PDO7 to PDO10 off Maximum additional load that can be drawn from all PDO pull-ups to VDDCAP Running round-robin loop 1 ms duration only, VDDCAP = 3 V 52 ±0.05 kΩ % Midrange and high range Current Available from VDDCAP ADC Supply Current EEPROM Erase Current SUPPLY FAULT DETECTORS VH Pin Input Impedance Input Attenuator Error Detection Ranges High Range Midrange VPx Pins Input Impedance Input Attenuator Error Detection Ranges Midrange Low Range Ultralow Range VXx Pins Input Impedance Detection Range Ultralow Range Absolute Accuracy Threshold Resolution Digital Glitch Filter 2 6 2.5 14.4 6 52 ±0.05 2.5 1.25 0.573 6 3 1.375 1 mA V V kΩ % Low range and midrange V V V No input attenuation error MΩ 0.573 1.375 ±1 8 0 100 V % Bits µs µs Rev. A | Page 4 of 12 No input attenuation error VREF error + DAC nonlinearity + comparator offset error + input attenuation error Minimum programmable filter length Maximum programmable filter length Data Sheet Parameter ANALOG-TO-DIGITAL CONVERTER Signal Range ADM1063-EP Min 0 Input Reference Voltage on REFIN Pin, VREFIN Resolution INL Gain Error Conversion Time Minimum Load Capacitance PSRR PROGRAMMABLE DRIVER OUTPUTS High Voltage (Charge Pump) Mode (PDO1 to PDO6) Output Impedance VOH IOUTAVG Standard (Digital Output) Mode (PDO1 to PDO10) VOH Max Unit Test Conditions/Comments VREFIN V The ADC can convert signals presented to the VH, VPx, and VXx pins; VPx and VH input signals are attenuated depending on the selected range; a signal at the pin corresponding to the selected range is from 0.573 V to 1.375 V at the ADC input 2.048 12 0.25 V Bits LSB % ms ms LSB LSB rms ±3 −1.7 ±3 −3 200 12 0 128 0.125 °C °C/V °C °C µA µA °C °C °C ±2.5 ±0.05 0.44 84 Offset Error Input Noise TEMPERATURE SENSOR 2 Local Sensor Accuracy Local Sensor Supply Voltage Coefficient Remote Sensor Accuracy Remote Sensor Supply Voltage Coefficient Remote Sensor Current Source Temperature for Code 0x800 Temperature for Code 0xC00 Temperature Resolution per Code REFERENCE OUTPUT Reference Output Voltage Load Regulation Typ ±2 2.043 2.048 −0.25 0.25 2.053 1 60 11 10.5 500 12.5 12 20 14 13.5 2.4 VOL IOL 3 ISINK3 RPULL-UP ISOURCE (VPx)3 Three-State Output Leakage Current Oscillator Frequency VPU − 0.3 0 19 20 90 100 VDDCAP = 4.75 V VDDCAP = 4.75 V High level Low level VDDCAP = 4.75 V VDDCAP = 4.75 V V mV mV µF dB No load Sourcing current, IDACxMAX = −100 µA Sinking current, IDACxMAX = 100 µA Capacitor required for decoupling, stability DC kΩ V V µA IOH = 0 µA IOH = 1 µA 2 V < VOH < 7 V 0.50 20 60 29 2 V V V V mA mA kΩ mA 10 110 µA kHz 4.5 Endpoint corrected, VREFIN = 2.048 V VREFIN = 2.048 V One conversion on one channel All 12 channels selected, 16× averaging enabled VREFIN = 2.048 V Direct input (no attenuator) Rev. A | Page 5 of 12 VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA VPU to VPx = 6.0 V, IOH = 0 mA VPU ≤ 2.7 V, IOH = 0.5 mA IOL = 20 mA Maximum sink current per PDOx pin Maximum total sink for all PDOx pins Internal pull-up Current load on any VPx pull-ups, that is, total source current available through any number of PDOx pull-up switches configured onto any one VPx pin VPDO = 14.4 V All on-chip time delays derived from this clock ADM1063-EP Parameter DIGITAL INPUTS (VXx, A0, A1) Input High Voltage, VIH Input Low Voltage, VIL Input High Current, IIH Input Low Current, IIL Input Capacitance Programmable Pull-Down Current, IPULL-DOWN SERIAL BUS DIGITAL INPUTS (SDA, SCL) Input High Voltage, VIH Input Low Voltage, VIL Output Low Voltage, VOL3 SERIAL BUS TIMING 4 Clock Frequency, fSCLK Bus Free Time, tBUF Start Setup Time, tSU;STA Stop Setup Time, tSU;STO Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT Input Low Current, IIL SEQUENCING ENGINE TIMING State Change Time Data Sheet Min Typ Max 2.0 0.8 −1 1 5 20 2.0 0.8 0.4 400 1.3 0.6 0.6 0.6 1.3 0.6 300 300 100 5 1 10 Unit Test Conditions/Comments V V µA µA pF µA Maximum VIN = 5.5 V Maximum VIN = 5.5 V VIN = 5.5 V VIN = 0 V VDDCAP = 4.75 V, TA = 25°C if known logic state is required V V V IOUT = −3.0 mA kHz µs µs µs µs µs µs ns ns ns ns µA VIN = 0 V µs At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP. All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured. Specification is not production tested but is supported by characterization data at initial product release. 4 Timing specifications are guaranteed by design and supported by characterization data. 1 2 3 Rev. A | Page 6 of 12 Data Sheet ADM1063-EP ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Voltage on VH Pin Voltage on VPx Pins Voltage on VXx Pins Voltage on A0, A1 Pins Voltage on REFIN, REFOUT Pins Voltage on VDDCAP, VCCP Pins Voltage on PDOx Pins Voltage on SDA, SCL Pins Voltage on GND, AGND, PDOGND, REFGND Pins Voltage on DxN, DxP Pins Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJ max) Storage Temperature Range Lead Temperature (Soldering Vapor Phase, 60 sec) Rating 16 V 7V −0.3 V to +6.5 V −0.3 V to +7 V 5V 6.5 V 16 V 7V −0.3 V to +0.3 V −0.3 V to +5 V ±5 mA ±20 mA 150°C −65°C to +150°C 215°C ESD Rating, All Pins 2000 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 40-Lead LFCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 7 of 12 θJA 26.5 Unit °C/W ADM1063-EP Data Sheet 34 33 32 31 VX1 1 PIN 1 INDICATOR VX2 2 30 PDO1 29 PDO2 VX3 3 28 PDO3 VX4 4 27 PDO4 VX5 5 ADM1063-EP VP1 6 TOP VIEW (Not to Scale) 21 PDO10 12 13 REFIN 11 14 15 16 17 18 19 20 NC PDO9 VH 10 NC 22 SCL PDO8 VP4 9 SDA PDO7 23 NC 24 VP3 8 NC VP2 7 REFOUT PDO6 AGND PDO5 25 REFGND 26 NC = NO CONNECT 09116-003 VCCP PDOGND 35 A1 36 A0 37 D2P 38 D2N 39 D1P 40 D1N GND VDDCAP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 to 5 6 to 9 10 11 12 13 14 15, 16, 19, 20 17 18 21 to 30 31 32 33 34 35 36 37 38 39 40 EPAD Mnemonic VX1 to VX5 (VXx) VP1 to VP4 (VPx) VH AGND (In a typical application, all ground pins are connected together.) REFGND (In a typical application, all ground pins are connected together.) REFIN REFOUT NC SCL SDA PDO10 to PDO1 PDOGND (In a typical application, all ground pins are connected together.) VCCP A0 A1 D2N D2P D1N D1P VDDCAP GND (In a typical application, all ground pins are connected together.) Exposed pad. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability. Rev. A | Page 8 of 12 Data Sheet ADM1063-EP TYPICAL PERFORMANCE CHARACTERISTICS 6 180 160 5 140 120 IVP1 (µA) VVDDCAP (V) 4 3 2 100 80 60 40 1 0 1 2 3 4 5 6 VVP1 (V) 0 09116-050 0 0 1 2 3 4 5 6 VVP1 (V) Figure 4. VVDDCAP vs. VVP1 09116-053 20 Figure 7. IVP1 vs. VVP1 (VP1 Not as Supply) 6 5.0 4.5 5 4.0 3.5 3.0 IVH (mA) VVDDCAP (V) 4 3 2 2.5 2.0 1.5 1.0 1 0 2 4 6 8 10 12 14 16 VVH (V) 0 09116-051 0 0 2 4 6 8 10 12 14 16 VVH (V) Figure 5. VVDDCAP vs. VVH 09116-054 0.5 Figure 8. IVH vs. VVH (VH as Supply) 350 5.0 4.5 300 4.0 250 IVH (µA) 3.0 2.5 2.0 1.5 200 150 100 1.0 50 0 0 1 2 3 4 VVP1 (V) 5 6 0 0 1 2 3 4 VVH (V) Figure 9. IVH vs. VVH (VH Not as Supply) Figure 6. IVP1 vs. VVP1 (VP1 as Supply) Rev. A | Page 9 of 12 5 6 09116-055 0.5 09116-052 IVP1 (mA) 3.5 ADM1063-EP Data Sheet 14 1.0 0.8 0.6 10 0.4 0.2 DNL (LSB) CHARGE-PUMPED V PDO1 (V) 12 8 6 0 –0.2 –0.4 4 –0.6 2 2.5 5.0 7.5 10.0 12.5 15.0 ILOAD (µA) –1.0 0 1000 4.5 0.8 4.0 0.6 3.5 0.4 INL (LSB) 3.0 VP1 = 5V 2.5 VP1 = 3V 2.0 0.2 0 –0.2 1.5 –0.4 1.0 –0.6 0.5 –0.8 0 3 4 5 6 ILOAD (mA) –1.0 09116-057 VPDO1 (V) 1.0 2 4000 Figure 13. DNL for ADC 5.0 1 3000 CODE Figure 10. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD 0 2000 1000 0 2000 3000 4000 CODE 09116-063 0 09116-056 0 09116-066 –0.8 Figure 14. INL for ADC Figure 11. VPDO1 (Strong Pull-Up to VPx) vs. ILOAD 12000 4.5 4.0 9894 10000 3.5 VP1 = 5V HITS PER CODE 2.5 VP1 = 3V 2.0 1.5 8000 6000 4000 1.0 2000 0.5 0 10 20 30 40 50 ILOAD (µA) 60 Figure 12. VPDO1 (Weak Pull-Up to VPx) vs. ILOAD 81 0 2047 2048 2049 CODE Figure 15. ADC Noise, Midcode Input, 10,000 Reads Rev. A | Page 10 of 12 09116-064 25 0 09116-058 VPDO1 (V) 3.0 Data Sheet ADM1063-EP 2.058 VP1 = 3.0V 2.048 VP1 = 4.75V 2.043 2.038 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 09116-061 REFOUT (V) 2.053 Figure 16. REFOUT vs. Temperature Rev. A | Page 11 of 12 ADM1063-EP Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 31 40 30 0.50 BSC 1 0.80 0.75 0.70 0.45 0.40 0.35 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.25 4.10 SQ 3.95 EXPOSED PAD 21 TOP VIEW PIN 1 INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 17. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADM1063BCPZ-EP-RL7 1 Temperature Range −40°C to +105°C Package Description 40-Lead LFCSP_WQ Z = RoHS Compliant Part. ©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09116-0-8/13(A) Rev. A | Page 12 of 12 Package Option CP-40-9