CoreMP7 Development Kit User's Guide

CoreMP7 Development Kit
User’s Guide
Actel Corporation, Mountain View, CA 94043
© 2006 Actel Corporation. All rights reserved.
Printed in the United States of America
Part Number: 50200075-0
Release: August 2006
No part of this document may be copied or reproduced in any form or by any means
without prior written consent of Actel.
Actel makes no warranties with respect to this documentation and disclaims any
implied warranties of merchantability or fitness for a particular purpose. Information
in this document is subject to change without notice. Actel assumes no responsibility
for any errors that may appear in this document.
This document contains confidential proprietary information that is not to be
disclosed to any unauthorized person without prior written consent of Actel
Corporation.
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All other products or brand names mentioned are trademarks or registered trademarks
of their respective holders.
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Document Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Document Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1
Contents and System Requirements . . . . . . . . . . . . . . . . 7
Development Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Hardware Components . . . . . . . . . . . . . . . . . . . . . . . 9
CoreMP7 Evaluation Board . . . . . . . . . . . . . . . . . . . . .
Detailed Board Description and Usage . . . . . . . . . . . . . . .
PLL Parts/Usage on M7A3P/E . . . . . . . . . . . . . . . . . . .
Programming the Development Kit with a FlashPro3 Programmer
3
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.9
.9
11
14
Setup and Self Test . . . . . . . . . . . . . . . . . . . . . . . . . 25
Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Hardware Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Programming the Test File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4
Actel CoreMP7 Design Flow . . . . . . . . . . . . . . . . . . . . 27
CoreMP7 System Creation . . . . . . . . . . . . .
FPGA Design Creation and Verification . . . . . .
FPGA Design Implementation . . . . . . . . . . .
FPGA Programming Software . . . . . . . . . . .
Microprocessor Design Creation and Programming
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27
29
30
31
31
Quickstart Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . 33
Actel CoreConsole 1.1 . . . . . . . . . . . . . . . . .
Actel Libero IDE v7.1 . . . . . . . . . . . . . . . . . .
ARM RealView Developer Kit – Actel Edition . . . . .
Running the Reversi Game via the On-Chip Debugger
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. 34
. 49
. 86
104
A M7A3PE600 and M7A3P1000 FG484 Package Connections . . 105
484-Pin FGBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
CoreMP7 Development Kit User’s Guide
3
Table of Contents
B Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 125
Top-Level View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
CoreMP7 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
C Signal Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
D Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Customer Service . . . . . . . . . . . . . . . . . .
Actel Customer Technical Support Center . . . . .
Actel Technical Support . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center
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147
147
147
147
148
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4
CoreMP7 Development Kit User’s Guide
Introduction
Thank you for purchasing the Actel CoreMP7 Development Kit.
This guide provides the information required to easily evaluate the CoreMP7 intellectual property
(IP) core and M7A3P/E devices.
The CoreMP7 Development Kit software includes a base set of common IP for use in your
embedded system. The CoreMP7 Evaluation Board also includes additional hardware to facilitate
your system development; however, additional purchases may be required to use certain hardware
found on the development board, such as the 10/100 Ethernet, USB 1.1, or CAN 2.0A/B interfaces.
Document Contents
Chapter 1 – Contents and System Requirements describes the contents of the CoreMP7
Development Kit.
Chapter 2 – Hardware Components describes the components of the CoreMP7 Evaluation Board.
Chapter 3 – Setup and Self Test describes how to set up the CoreMP7 Evaluation Board and how to
perform a self test.
Chapter 4 – Actel CoreMP7 Design Flow introduces the design flow for CoreMP7 using Actel
CoreConsole,® Actel Libero® Integrated Development Environment (IDE), and ARM® RealView
Developer Kit.
Chapter 5 – Quickstart Tutorial illustrates a sample Verilog design for the CoreMP7 Evaluation
Board.
Appendix A – M7A3PE600 and M7A3P1000 FG484 Package Connections provides a table listing
the board connections.
Appendix B – Board Schematics provides illustrations of the CoreMP7 Evaluation Board.
Appendix C – Signal Layers provides illustrations of the six signal layers of the CoreMP7
Evaluation Board.
Appendix D – Product Support describes Actel support services.
Document Assumptions
This user’s guide assumes the following:
• You intend to use Actel Libero IDE and ARM RealView Developer Kit.
• You have installed and are familiar with Actel Libero IDE v7.0 and ARM RealView Developer
Kit v2.2, or later versions of either suite.
• You are familiar with Verilog.
• You are familiar with PCs and the Windows operating system.
CoreMP7 Development Kit User’s Guide
5
1
Contents and System Requirements
This chapter details the contents of the CoreMP7 Development Kit and lists the power supply and
software system requirements.
Development Kit Contents
The CoreMP7 Development Kit includes the following:
• CoreMP7 Evaluation Board
• Actel Libero IDE Gold
• Actel CoreConsole IP Deployment Platform
• Actel SoftConsole GNU-based C compiler with basic debugger and FlashPro3 JTAG support
• CoreMP7 User’s Guide and Tutorial
• CD-ROM with design examples
• Universal 9 V DC power supply providing output up to 2 A
CUI, Inc. Part Number: DTS090220U-P5P-SZ
• Actel FlashPro3 Programmer (optional, depending on kit ordered)
For the CD-ROM contents, review the ReadMe.doc file at the top level of the CD-ROM.
System Requirements
The system requirements for Actel Libero IDE and ARM RealView Developer Kit are as follows:
• 1.0 GHz Pentium-class processor
• 750 MB hard disk space
• 256 MB RAM
• CD-ROM drive
• USB 1.1 (USB 2.0 recommended)
• Windows 2000 SP4 or Windows XP SP2
CoreMP7 Development Kit User’s Guide
7
2
Hardware Components
This chapter describes the hardware components of the CoreMP7 Evaluation Board.
CoreMP7 Evaluation Board
Figure 2-1 on page 10 shows a top-level view of the CoreMP7 Evaluation Board. The board consists
of the following:
• Wall-mount power supply connector with switch and LED indicator
• Switches to select from 1.5 V, 2.5 V, and 3.3 V VCCI (I/O Bank) voltages on banks 4–7 (for the
M7A3PE600) or banks 3–4 (for the M7A3P1000)
• 10-pin, 0.1"-pitch programming connector compatible with Altera connections
• 48 MHz oscillator and 32 kHz oscillator for real-time clock (RTC) calculations
• Eight LEDs driven by outputs from the device
• Jumpers allowing disconnection of all external circuitry from the FPGA
• One monostable pulse generator switch
• Eight switches providing input to the device
• Two RS-232 serial interfaces
• Two 10/100 Ethernet interfaces (only populated on boards with M7A3P1000)
• One Controller Area Network (CAN) 2.0B serial interface
• One USB 1.1 serial interface
For further information, refer to “M7A3PE600 and M7A3P1000 FG484 Package Connections” on
page 105 and “Board Schematics” on page 125.
Detailed Board Description and Usage
The CoreMP7 Evaluation Board has various advanced features that are covered in later sections of
this chapter. The Development Kit version can be identified as the one that has the FPGA soldered
directly to the board.
A block diagram of the CoreMP7 Evaluation Board is shown in Figure 2-1 on page 10 and will
facilitate understanding of the more detailed schematics shown in “Board Schematics” on page 125.
CoreMP7 Development Kit User’s Guide
9
Hardware Components
Figure 2-1. CoreMP7 Evaluation Board Top-Level View
10
CoreMP7 Development Kit User’s Guide
PLL Parts/Usage on M7A3P/E
Full schematics are available on the Development Kit tutorial CD-ROM supplied with the kit. The
schematics are also available for download from the Actel website. The dedicated electronic version
of the schematics can be enlarged to a far greater degree than can be shown in the printed version of
this manual; hence, the interested reader is referred to the dedicated schematics for the appropriate
level of detail.
PLL Parts/Usage on M7A3P/E
Instructions for PLL Activation on the CoreMP7 Evaluation Board
To use the PLLs on the CoreMP7 Evaluation Board, power must be applied to their respective
analog supply rails. For the west side middle PLL, known as PLF, the VCCPLF line must be
connected to VCC, which is held at 1.5 V. The same is true of VCCPLC for the PLL on the east
side, known as PLC. These voltages are not connected by default on the board for three reasons:
• The PLC analog voltage rails are not available on M7A3P devices, only in the M7A3PE family;
only the west side PLL, namely PLF, is available on M7A3P devices. On M7A3P devices, the
remaining pins are used as general purpose I/Os. The same board is used for M7A3PE and
M7A3P devices.
• The aim is to demonstrate the lowest possible power consumption for the part. Perpetually
powering the PLL lines would not achieve the lowest power.
• It is easy to connect the appropriate pins together when desired. This is why the pins are available
on the jumper-based headers.
A variety of valid connections is possible. Three examples are as follows:
• For PLF, connect pin M6 (VCCPLF) to VCC via jumper JP42.
• For PLC, connect pin M18 (VCCPLC) to VCC via jumper JP44.
• For PLA, connect pin F7 (VCCPLA) to VCC via jumper JP40
Note: PLA, PLB, PLD, and PLE are only available on M7A3PE devices.
To facilitate use, Actel supplies jumpers with selected production versions of the kit to allow users to
quickly connect and disconnect these voltage supply rails. If a user has lost the jumpers or has a kit
without jumpers, it is a simple matter of soldering short, insulated connecting wire to the
appropriate header pins on the corresponding PLL jumper block.
CoreMP7 Development Kit User’s Guide
11
Hardware Components
Power Supplies
A 9 V power supply is provided with the Development Kit (Figure 2-2). There are many power
supply components on the Evaluation Board to illustrate the many ways that differing voltage banks
may be used with M7A3P and M7A3PE technology. These voltage banks are not all required for
general use of the M7A3P silicon. They are provided for illustrative purposes only.
+9 V DC Supply
2 A Max.
D4
Red
2.5 V
Regulator
SW1
Off
On
3.3 V
Regulator
VPUMP
5.0 V
Regulator
1.5 V
Regulator
Core FPGA
Voltage
USB
Power
Figure 2-2. Power Supply Block Diagram
To use the CoreMP7 Evaluation Board with a wall-mount power supply, use the switching brick
power supply provided with the kit.
The external +9 V center-positive power supply provided to the board via connector J1 goes to a
voltage regulator chip, U1. As soon as the external voltage is connected to the board, the red “power
applied” LED, D4, illuminates to indicate that an external supply has been connected. As soon as
switch SW1 is moved to the ON position, the disabling ground signal is removed from pin 7 of U1,
and the regulator begins to provide power at its output.
The switching voltage regulator (U1) provides a dedicated 3.3 V supply at its output. The board’s
3.3 V supply is used to feed separate regulators that deliver 1.5 V (via U2) and 2.5 V (via U4). The
1.5 V supply is required for the core voltage of the M7A3P/E family, and the 2.5 V supply is
required for demonstrating LVDS extended I/O bank capability.
12
CoreMP7 Development Kit User’s Guide
PLL Parts/Usage on M7A3P/E
The presence of these voltages is indicated by the illumination of three green LEDs (D2, D3, and
D7) at the top middle of the board. Each LED is labeled with the voltage it represents and its
component identifier. All three voltages are selectable on I/O banks 4–7 on the M7A3PE device.
Note: Only M7 ProASIC3E devices have eight I/O banks. M7 ProASIC3 devices have four I/O
banks—one per side of the FG484 package.
The 3.3 V supply can also be used to provide the VPUMP programming voltage. VPUMP can be
provided to the chip during programming by applying a FlashPro3 programmer to the J10 interface
and selecting VPUMP from the FlashPro v4.0 (or later) programming software. The VPUMP voltage
can also be provided directly to the chip from the board. Leave the JP39 jumper in place to apply the
3.3 V supply to the VPUMP pin (U17 on the FG484 package).
Note: If both FlashPro3 and the board are selected to provide VPUMP, the connection on the board
will override, as FlashPro3 will detect that a voltage is available, issue an information message
in the programming software, and then tristate the VPUMP output pin, allowing the board to
provide all the power.
The board must be powered up during programming, as the chip needs its core voltages provided,
and VJTAG must be detected by the FlashPro3 programmer before it can set its JTAG signal voltages
to the correct level.
USB has its own dedicated 5 V power supply, all components of which (including the regulator U3)
are marked on the circuit board in a boxed area to indicate which components on the PCB are
associated with which tasks. A green LED (D5) representing 5 V supply availability is located at the
top middle of the board.
The external +9 V power supply is rated at 2 A maximum. In the first of the schematics shown in
“Board Schematics” on page 125, it can be seen that the 3.3 V supply is rated at 5 A maximum. The
derived power supplies of 1.5 V and 2.5 V are each rated at 2 A maximum, and the USB 5 V power
supply is rated at 500 mA, as shown in Figure B-3 on page 128. As such, the derived supplies cannot
all be working at their maximum current outputs simultaneously. The maximum ratings are given for
the individual regulator ICs and cannot be added together.
Both U1 (LM2678S-3.3) and U3 (LM2674M-5.0) are rated for an input voltage range of +8 V to
+40 V, so a wide range of power supplies can be used with the board with no concern about overvoltage conditions occurring from inadvertent usage of the wrong power supply. However, the user
should take care to ensure that the voltage provided is positive at the center pin of the J16 connector
and grounded on the outside.
Note: Greater heating of the regulator chips will be observed with higher voltages. It is therefore
recommended that only the included power supply or an equivalent substitute be used with
the Development Kit. The included power supply has been rated for this board, including any
Actel daughter cards that may be attached to the board.
CoreMP7 Development Kit User’s Guide
13
Hardware Components
Programming the Development Kit with a FlashPro3
Programmer
The same board is used for all CoreMP7 Development Kits. The COREMP7-E600-DEV-KIT
board is fitted with a M7A3PE600-FG484 device, and the COREMP7-1000-DEV-KIT board is
fitted with a M7A3P1000-FG484 device. Further, there are two additional variations of the
CoreMP7 Development Kit: COREMP7-E600-DEV-KIT-FP3 and COREMP7-1000-DEV-KIT-FP3.
The only difference between these two is the designator -FP3, which indicates that the kit includes
the FlashPro3 programmer.
Connecting the FlashPro3 Programmer to the Board
To connect the FlashPro3 programmer to the board:
1.
Connect the FlashPro3 programmer to your computer via the USB cable.
2.
Follow the instructions in the FlashPro User’s Guide (software v4.0 or later) for installing the
software and connecting to FlashPro3. The amber (yellow) power LED on the FlashPro3 should
be illuminated at this stage. If it is not, recheck the procedure given in the FlashPro User’s Guide
until you obtain steady illumination of the amber power LED.
3.
Make sure the board power switch SW1 is in the OFF position and only the red external power
LED is illuminated on the board.
4.
Connect the FlashPro3 programmer to the board via the 10-pin programming cable supplied
with the FlashPro3 programmer. The connector to use on the board is labeled FP3_JTAG ( J10)
and has a keyed header. The pin 1 location on the cable, indicated by the red ribbon running
along the side of the cable, will be on the left side as it enters the board.
After connecting the FlashPro3 programmer, you can verify communication by checking Device
Info in the FlashPro software. The M7A3P/E details will be shown in the software log window. If
you suspect a JTAG communication problem, try changing the VJTAG voltage. To overcome noise,
higher values usually work better, but all values should work with the supplied programming cable
(6" in length) connected to just one board.
Programming or Reprogramming the Example Design
On the Development Kit CD, you will find a Designer directory containing a STAPL file for
programming the target design. Select the TOP_M7A3PE6.STP file (for M7A3PE600 parts) or the
TOP_M7A3P1K.STP file (for M7A3P1000 parts) from the CD and use that as the STAPL file in
the FlashPro software. Selecting Program will erase, program, and verify the part.
14
CoreMP7 Development Kit User’s Guide
Programming the Development Kit with a FlashPro3 Programmer
Jumpers for Isolating Switches, LEDs, and Other Components from the
FPGA
Many jumpers are provided on the board to allow the user to disconnect various switch combinations
and LEDs from the FPGA I/O banks. All such jumpers are shown in the schematic in Figure B-8
on page 133 and are labeled on the top-layer silkscreen as JP*, where * is a number. All jumpers are
also labeled with the FPGA I/O pin number to which they are connected; e.g., JP29, for the TX0
connection of the RS-232 transmitter to the FPGA, is labeled “F18,” which indicates that it is
connected to pin F18. Similarly, SW4 has a jumper above it, JP3, that is labeled “T5,” indicating
that SW4 is connected to pin T5 of the FPGA when the jumper is in place.
Disconnecting jumpers JP2–JP9 causes the push button switches (SW3–SW10, respectively) to be
disconnected from the FPGA so that I/O pins T4, T5, R6, R5, U2, U3, P6, and P7 can be used for
other purposes. Disconnecting the eight jumpers, JP10–JP17, causes the eight LEDs (D9–D16) to
be disconnected from FPGA I/O pins R4, P5, R2, T2, P2, N2, N6, and N7, respectively.
The push-button switch SW2 (labeled RESET#), meant for applying a reset pulse, is connected to
pin W15, a chip-wide global. Again, all labeling is clearly shown on the silkscreen. This flexibility is
useful for experimentation with designs of your own choosing and in connecting other external
equipment to the board for development purposes.
CoreMP7 Development Kit User’s Guide
15
Hardware Components
LED Connections
Eight LEDs are connected to the device via jumpers. If the jumpers are in place, the device I/O can
drive the LEDs. The LEDs change based on the output as follows:
• A '1' on the output of the device lights the LED.
• A '0' on the output of the device switches off the LED.
• An unprogrammed or tristated output may show a faintly lit LED.
Note: If the I/O voltage of Bank 5 (on A3PE, set by J6) or Bank 2 (A3P, set by J6) is not at least
2.5 V, the LEDs will not illuminate. A setting of 1.8 V on the voltage bank will cause
extremely faint illumination.
Table 2-1 lists the jumper and device connection associated with each LED.
Table 2-1. LED Device Connections
LED Jumper Device Connection
D9
JP17
U9 pin N7
D10
JP16
U9 pin N6
D11
JP15
U9 pin N2
D12
JP14
U9 pin P2
D13
JP13
U9 pin T2
D14
JP12
U9 pin R2
D15
JP11
U9 pin P5
D16
JP10
U9 pin P4
To use the device I/O for other purposes, remove the jumpers.
16
CoreMP7 Development Kit User’s Guide
Programming the Development Kit with a FlashPro3 Programmer
Switch Connections
Eight switches are connected to the device via jumpers. If the jumpers are in place, the device I/O
can be driven by the switches listed in Table 2-2.
• Pressing a switch drives a '1' onto the associated device I/O pin. The '1' continues to be driven
while the switch is in place.
• Releasing a switch drives a zero onto the device I/O pin.
Table 2-2 lists the jumper and device connection associated with each switch.
Table 2-2. Switch Device Connections
Switch Jumper Device Connection
CoreMP7 Development Kit User’s Guide
SW3
JP2
U9 pin T4
SW4
JP3
U9 pin T5
SW5
JP4
U9 pin R6
SW6
JP5
U9 pin R5
SW7
JP6
U9 pin U2
SW8
JP7
U9 pin U3
SW9
JP8
U9 pin P6
SW10
JP9
U9 pin P7
17
Hardware Components
CoreUARTapb RS-232 Implementation
The CoreMP7 Development Kit includes two RS-232 ports that can be used for communication
between the embedded microprocessor and a common serial port, as found on a PC or other
RS-232–compatible device. To use either of the RS-232 ports, jumpers must be in place to connect
the FPGA to the on-board RS-232 transceiver. The jumpers used for the RS-232 connections can
be found in Table 2-3.
The primary RS-232 port (P2) has lines to support RTS/CTS flow control in addition to TXD and
RXD.
Note: Currently, CoreUARTapb does not support hardware RTS/CTS handshaking. If this
functionality is needed, it must be implemented in software. The default configuration has a
jumper shorting RTS0 and CTS0 together, disconnecting them from the FPGA I/Os and
creating a loopback connection, similar to the implementation found on the secondary
RS-232 port.
Table 2-3. RS-232 Connections
Signal Jumper Device Connection
18
TX0
JP29
U9 pin B11
RX0
JP32
U9 pin G21
RTS0
JP30
U9 pin K17
CTS0
JP33
U9 pin J19
TX1
JP31
U9 pin C11
RX1
JP34
U9 pin K18
CoreMP7 Development Kit User’s Guide
Programming the Development Kit with a FlashPro3 Programmer
Core10/100 Ethernet Implementation
Core10/100 is an Ethernet Media Access Controller (MAC) that connects Local Area Networks
(LANs) at data rates of 10 or 100 Mbps (see Figure 2-3). It has a Media Independent Interface
(MII) for physical connection and implements Carrier Sense Multiple Access with Collision
Detection (CSMA/CD) algorithms, per IEEE 802.3. Ethernet is a common standard used in
computer, communications, industrial, and other applications.
Shared
RAM
Data Interface Bus
CPU
(8-, 16-, or 32-Bit)
Transmit
RAM
Core10/100
PHY
MII
Interface
Control Interface Bus
Address
RAM
Receive
RAM
Figure 2-3. Overview of a Typical Core10/100 System
Detailed Core10/100 information is available in the Ethernet Media Access Controller Core10/100
datasheet at http://www.actel.com/ipdocs/Core10100_DS.pdf.
The MII interface to Core10/100 works with most Ethernet PHY chips. Due to the analog
requirements of an Ethernet PHY, such cannot be implemented in an Actel FPGA.
The CoreMP7 Evaluation Board supports dual Ethernet connections. An AM79C874VI from
Advanced Micro Devices (AMD) is used for each PHY (U19 and U20). See Table 2-4 on page 20
for details on the connections between the FPGA and each PHY via J26 and J27, which are
connection/disconnection points for PHY0 and PHY1, respectively.
Note: The dual Core10/100 Ethernet interfaces are only populated on boards based on the
M7A3P1000 device.
CoreMP7 Development Kit User’s Guide
19
Hardware Components
Table 2-4. 10/100 Ethernet Connections
PHY Signal
Jumper Device Connection ( J26/J27)
MDIO
1
U12/U12
MDC
3
T12/T12
TXD0
5
V10/V12
TXD1
7
U9/V11
TXD2
9
U10/R12
TXD3
11
T10/R11
TX_EN
13
AB7/AA9
TX_ER
15
AB6/AA10
EXT_IN_CLK_0 17
Y7/AA8
RXD0
19
Y6/AA7
RXD1
21
U9/AB9
RXD2
23
V8/AB8
RXD3
25
AA6/W9
RX_DV
27
AA5/W8
RX_ER
29
AB5/Y10
EXT_IN_CLK_1 31
AB4/W10
COL
33
AA4/U11
CRS
35
Y4/T11
RST#
37
W15/W15
N/C
39
N/C
USB
The CoreMP7 Evaluation Board includes a Fairchild Semiconductor USB1T11AM USB
transceiver. The USB standard specifies support for multiple device connections, allowing up to 127
unique devices. Further, the Fairchild transceiver supports the transmitting and receiving of serial
data at both full-speed (12 Mbps) and low-speed (1.5 Mbps) data rates. Implementation of the
Serial Interface Engine (SIE) is required to use the USB interface present on the Evaluation Board.
Information on the SIE can be found on the USB Implementers Forum at http://www.usb.org.
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CoreMP7 Development Kit User’s Guide
Programming the Development Kit with a FlashPro3 Programmer
CompanionCore CAN 2.0B Implementation
The CAN bus is a communication standard with multi-master capability, error detection and
correction, and broad industry acceptance. The CAN bus was designed for the automobile industry,
but CAN has recently been appearing in non-traditional applications. The CAN bus comprises two
signals to which all networked devices are connected, thus allowing communication between
multiple devices. The reliability and error detection is handled by a series of arbitrations, (not)
acknowledges, and CRC checks.
Table 2-5 details the connections between the M7A3P/E FPGA and the onboard CAN transceiver
(U18). The CoreMP7 Evaluation Board is also equipped with LEDs (D18 and D19) connected to
the TXD and RXD lines of the CAN bus. Therefore, when data is being transmitted or received,
the respective LED will blink.
If network termination is needed (typically for CAN baud rates greater than 100 kbps), shorting
JP38 (CAN_TERM) inserts a 120 Ω resistor between CAN-H and CAN-L.
Table 2-5. CAN Device Connections
CAN Signal Jumper Function / Device Connection
CAN_TXD
JP35
U9 pin K20
CAN_RXD
JP36
U9 pin J22
CAN_TERM JP37
Enables termination
CAN_SHLD
Enables shield ground
JP38
Clock Circuits
The CoreMP7 Evaluation Board has two clock circuits: a 48 MHz oscillator and a 32 kHz
oscillator.
48 MHz Oscillator
The 48 MHz oscillator on the board is a 30 ppm–stability crystal module that provides more than
adequate performance and can be connected to a general purpose I/O (pin W12) or a chip-wide
global (pin W17) using a jumper.
32 kHz Oscillator
The 32 kHz oscillator on the board is a 30 ppm–stability crystal module that will provide enough
accuracy to perform RTC calculations and is hardwired to a chip-wide global (pin V16).
CoreMP7 Development Kit User’s Guide
21
Hardware Components
Memory
Flash
The CoreMP7 Evaluation Board includes two STMicroelectronics M29W800DT Flash memory
chips, totaling 2 MB, which can be arranged in either a 1M × 16 or a 512K × 32 configuration. The
Flash memory is intended for use as executable program storage for the embedded microprocessor;
however, it can also be used as nonvolatile memory for the storage of system constants and
parameters.
SRAM
The CoreMP7 Evaluation Board includes two GSI Technology GS8001BT Synchronous SRAM
modules, totaling 2 MB, which can be arranged in either a 1M × 16 or a 512K × 32 configuration.
The SRAM memory is used for the embedded microprocessor stacks (both hardware and software)
and for dynamic system data.
Headers
There are three headers ( J11, J12, and J13) present on the CoreMP7 Evaluation Board intended for
use as general purpose I/O. These pins are tied to the various chip-wide global signals in the I/O
banks as well as dedicated general purpose I/Os. See the schematics in “Board Schematics” on page
125 for further information.
Test Points
All test points on the board are fitted with small test loops. These test points are labeled on the
silkscreen as TP1, TP2, etc. All such test points are also labeled on the silkscreen with the voltage
expected to be observed at that test point or the I/O pin to which the test point is connected. Each
voltage will be either 3.3 V, 2.5 V, 1.5 V, or GND. When measuring the voltage at a test point with
a DVM (digital voltage multimeter), the ground lead should be connected to a test point labeled
GND, and the voltage lead should be connected to the voltage to be tested. All voltage labels on the
board are relative to a 0 V ground reference (GND).
Board Layers
The complete board design and manufacturing files are included on the Development Kit CD. The
board file is in Allegro format, which will allow a user to create the appropriate Gerbers and other
board views as needed. Pictures of the board layers are also included in “Signal Layers” on page 139.
For your convenience, high-resolution PDFs of these layers are also provided on the Development
Kit CD.
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CoreMP7 Development Kit User’s Guide
Programming the Development Kit with a FlashPro3 Programmer
The board is fabricated with six copper layers. The layers are arranged as follows, from top to
bottom:
• Layer 1 – Top signal layer
• Layer 2 – Ground plane
• Layer 3 – Signal layer 3
• Layer 4 – Signal layer 4
• Layer 5 – Power plane
• Layer 6 – Bottom signal layer
Refer to the diagrams in “Signal Layers” on page 139.
CoreMP7 Development Kit User’s Guide
23
3
Setup and Self Test
This chapter outlines how to set up and test the CoreMP7 Evaluation Board.
Software Installation
The CoreMP7 Development Kit includes the Libero IDE software suite (version 7.0). For Libero
IDE software installation instructions, refer to the Actel Libero IDE / Designer Installation and
Licensing Guide for Software v6.1 at http://www.actel.com/documents/install_ug.pdf.
The CoreMP7 Development Kit also includes the Actel SoftConsole GNU-based C compiler and
debugger, which can be used to program and debug the CoreMP7 program memory through the
FlashPro3.
Hardware Installation
FlashPro3 is required to use the CoreMP7 Development Kit. For software and hardware installation
instructions, refer to the FlashPro v3.3 User’s Guide at http://www.actel.com/documents/
flashproUG.pdf. FlashPro3 is also used with SoftConsole to program and debug the Flash program
memory on the CoreMP7 Evaluation Board.
If you are using the ARM RealView Developer Kit, you will need to use the ARM RealView ICE
Micro Edition (RVI-ME) supplied with it to program and debug the Flash program memory on the
CoreMP7 Evaluation Board. For software and hardware installation instructions, refer to the
documentation included on the ARM RealView installation CDs.
Programming the Test File
To retest the evaluation board at any time, use the test program to reprogram the board. Use the
TEST_M7A3PE6.stp file with an M7A3PE600-FG484 fitted on the board. Use TEST_M7A3P1K.stp
with an M7A3P1000-FG484 fitted on the board.
The test design is currently implemented for the M7A3PE600 die size. It is possible to recompile
the design for other device sizes. For information about retargeting the device, refer to the Designer
User’s Guide at http://www.actel.com/documents/designerUG.pdf. The design files are available
under SelfTest on the Development Kit CD.
For instructions on programming the device using FlashPro3, refer to the FlashPro User’s Guide at
http://www.actel.com/documents/flashproUG.pdf.
The Flash memory on the board can be programmed using either FlashPro3 (if you are using
SoftConsole) or the RVI-ME (if you are using the RealView Developer Kit). For information on
programming the memory with RealView and the RVI-ME refer to ARM Application Note #110:
Flash Programming with RealView Debugger at http://www.arm.com/pdfs/AN110.zip.
CoreMP7 Development Kit User’s Guide
25
4
Actel CoreMP7 Design Flow
The CoreMP7 design flow consists of the two paths, shown in Figure 4-1 on page 28:
• FPGA development – the creation of the CoreMP7 system based on the Actel M7 FPGAs
• Executable code development – the creation of software programs that will execute on the
embedded microprocessor core
The CoreMP7 design flow has five main components:
• CoreMP7 system creation
• FPGA design creation and verification
• FPGA design implementation
• FPGA programming
• Microprocessor design creation and programming
CoreMP7 System Creation
CoreConsole is a system-level development tool and IP deployment platform that greatly simplifies
the task of assembling and connecting IP for implementation in Actel FPGAs. It enables you to
select IP components from a database supplied by Actel and graphically “stitch” them together to
build a processor-based System-Level Integration (SLI) design. When the design is complete, the
RTL (and other files needed to implement the design) can be generated and imported into the
familiar and proven design flow of the Actel Libero IDE software. CoreConsole also generates a
testbench for the SLI design that you can build to assist in verification.
Refer to the CoreConsole User’s Guide at http://www.actel.com/documents/CoreConsole_UG.pdf for
more information on using CoreConsole.
CoreMP7 Development Kit User’s Guide
27
CoreMP7 System Creation
Subsystem
RTL
CoreMP7
Testbench
System Editor
CoreMP7
Black-Box File
Design Creation/Verification
ACTgen
Core Generator
HDL Editor
WaveFormer
LiteTM
Testbench
Stimulus Generation
SynplifyR Synthesis
Synthesis
Libraries
Functional Simulation
Design Synthesis and
Optimization
ModelSimR
Simulator
PALACETM Physical
Synthesis
R
ViewDraw
Schematic Entry
User
Testbench
Performance Optimization
Timing Simulation
Design Implementation
MultiView Navigator
Compile
SmartTime
& Timer
I/O Assignments
Optimization and DRC
Static Timing Analysis and
Constraints Editor
ChipPlanner
Layout
SmartPower
Timing-Driven Place-and-Route
Power Analysis
Program File
Generation
Back-Annotated Timing
for Simulation
PinEditor
Floorplanning
I/O Attribute
Editor
Back-Annotate
Select I/O Standards
NetlistViewer
Design Schematic Viewer
Programming Software
ChainBuilder
(Flash Families)
Microprocessor Design
Creation/Verification
Source Code
Editor
FlashPro
(Flash Families)
Compiler
Simulator
Silicon Sculptor
(Antifuse/Flash Families)
JTAG
Emulation
Figure 4-1. Design Flow Paths
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CoreMP7 Development Kit User’s Guide
FPGA Design Creation and Verification
FPGA Design Creation and Verification
Design entry consists of writing HDL or capturing a schematic representation of the design and
performing functional simulations with a testbench.
Design Capture
For schematic capture, Libero IDE uses ViewDraw® for Actel, which includes a schematic editor.
The schematic editor provides a graphical entry method to capture designs. ViewDraw for Actel is
the Libero IDE integrated schematic entry vehicle, supporting mixed-mode entry, in which HDL
blocks and schematic symbols can be mixed.
The ViewDraw WIR file is automatically created after using the Save + Check command. This file
is used to create the structural HDL netlist.
For more information on using ViewDraw for Actel, refer to the Libero IDE User’s Guide for Software
v7.2 at http://www.actel.com/documents/libero_ug.pdf.
Adding SmartGen Macros
Use the SmartGen Macro Builder to instantly create customized macros, then use ViewDraw to add
these macros to a schematic. Alternatively, add the SmartGen macros in the HDL file.
Creating and Adding Symbols for HDL Files
Schematic users can encapsulate an HDL block within a block symbol.
To create a symbol:
1.
Right-click the block in the Design Hierarchy window of Libero IDE.
2.
Click Create Symbol. Libero IDE generates a symbol for the selected HDL block.
The macro is accessible from the components list in ViewDraw for Actel.
Testbench Generation
To run a simulation, it is necessary to create a testbench and associate it with a project. WaveFormer
Lite™ from SynaptiCAD™ is the Libero IDE integrated testbench generator. WaveFormer Lite
fits perfectly into Libero IDE, automatically extracting signal information from HDL design files
and producing HDL testbench code that can be used with any standard VHDL or Verilog
simulator.
WaveFormer Lite generates VHDL and Verilog testbenches from drawn waveforms.
CoreMP7 Development Kit User’s Guide
29
Actel CoreMP7 Design Flow
Pre-Synthesis Simulation
Functional simulation verifies that the logic of a design is functionally correct. Simulation is
performed using the Libero IDE integrated simulator, ModelSim® for Actel, which is a custom
edition of ModelSim PE integrated into Libero IDE.
ModelSim for Actel is an OEM edition of the Model Technology™ Incorporated (MTI) tools.
ModelSim for Actel supports VHDL or Verilog, but it can only simulate one language at a time. It
only works with Actel libraries and is supported by Actel.
Synthesis and Netlist Generation
After entering the design source, synthesize it to generate a netlist. Synthesis transforms the
behavioral HDL source into a gate-level netlist and optimizes the design for a target technology.
For more detailed information on the above topics, refer to the Libero IDE User’s Guide for Software
v7.2 at http://www.actel.com/documents/libero_ug.pdf.
FPGA Design Implementation
During design implementation, Actel Designer performs place-and-route on the design.
Place-and-Route
Start Designer from Libero IDE to place-and-route the design.
Timing Simulation
Perform timing simulation on the design after place-and-route in Designer. Timing simulation
requires information extracted and back-annotated from Designer.
Optional Tools
The tools listed in Table 4-1 provide optional functions that are not required in a basic design. Use
these tools to perform static timing analysis and power analysis, customize I/O placements and
attributes, and view the netlist. Perform the post-layout (timing) simulation after place-and-route.
Table 4-1. Designer User Tools
Designer User Tool
SmartTime
SmartPower
ChipEdit
PinEdit
Netlist Viewer
30
Function
Static timing analysis
Power analysis
Customize I/O and logic macro placement
Customize I/O placements and attributes
View your netlist and trace paths
CoreMP7 Development Kit User’s Guide
FPGA Programming Software
For more information on the tools described above, refer to the Designer User’s Guide for Software
v72.at http://www.actel.com/documents/designer_ug.pdf.
FPGA Programming Software
Program the device with programming software and hardware from Actel or with a supported thirdparty programming system. Refer to the Designer User’s Guide for Software v7.2, Silicon Sculptor User’s
Guide, and FlashPro User’s Guide for information about programming an Actel device.
These guides can be found at http://www.actel.com/techdocs/manuals/default.asp.
Microprocessor Design Creation and Programming
There are a large number of third party ARM7 program development tools that can be used with
CoreMP7 for the development of software programs that run on the processor. Actel offers several,
including the SoftConsole tools (included with the CoreMP7 Development Kit) and the RealView
Developer Kit (RVDK). SoftConsole is available for free, and the RVDK can be licensed from Actel
for an annual license fee. Although the RVDK has an annual license fee, the RealView C compiler
generates significantly more efficient code for CoreMP7 than the SoftConsole GCC compiler.
ARM RealView Developer Kit provides a fully integrated software solution with leading-edge tools
for creating efficient software to run on any ARM processor. Servicing all major market segments,
RealView Developer Kit provides flexible software tools to meet present and future requirements.
CoreMP7 Development Kit User’s Guide
31
5
Quickstart Tutorial
This tutorial illustrates a Verilog CoreMP7 design for the CoreMP7 Evaluation Board. This design
is created in Actel CoreConsole 1.1, Libero IDE v7.1, and ARM RealView Developer Kit. The
steps involved are as follows:
Actel CoreConsole 1.1
“Step 1 – Creating the Basic CoreConsole Project”
“Step 2 – Building the Subsystem within CoreConsole”
“Step 3 – Reviewing and Generating the CoreConsole Design”
Actel Libero IDE v7.1
“Step 1 – Create a New Project”
“Step 2 – Perform Pre-Synthesis Simulation”
“Step 3 – Synthesize the Design in Synplify”
“Step 4 – Perform Post-Synthesis Simulation”
“Step 5 – Implementing the Design with Actel Designer”
“Step 6 – Perform Timing Simulation with Back-Annotated Timing”
“Step 7 – Generating the Programming File”
“Step 8 – Programming the Device”
ARM RealView Developer Kit
“Step 1 – Creating a RealView Project”
“Step 2 – Compiling the Source Files”
“Step 3 – Debugging: Simulating/Executing the Compilation”
CoreMP7 Development Kit User’s Guide
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Quickstart Tutorial
Actel CoreConsole 1.1
This tutorial provides step-by-step instructions on how to create a CoreConsole project and generate
a CoreConsole design. The tutorial consists of three steps: “Step 1 – Creating the Basic
CoreConsole Project”, “Step 2 – Building the Subsystem within CoreConsole” on page 43, and
“Step 3 – Reviewing and Generating the CoreConsole Design” on page 46.
Note: Before you begin this tutorial, make sure the CoreConsole software is installed.
Step 1 – Creating the Basic CoreConsole Project
In Step 1, you learn the basic features of CoreConsole by creating a basic CoreConsole project. You
will use the Actel CoreConsole IP Deployment Platform tool to develop a skeleton CoreMP7
system. This system can be simulated and synthesized; however, it is too basic for practical use and
will be extended in “Step 2 – Building the Subsystem within CoreConsole”.
To create the CoreConsole project:
1.
Double-click the Actel CoreConsole 1.1 icon on your desktop to start the program, or select
Start > Programs > CoreConsole > Actel CoreConsole 1.1.
2.
From the File menu, select New. The New Design window displays, as shown in Figure 5-1.
3.
Enter your Design Name. For this tutorial, name your design “TutorialMP7”.
4.
Click OK to create your design project.
Figure 5-1. New Design Window in CoreConsole
To add components to your CoreConsole project:
34
1.
Under the Components tab, in the “Components available for selection" section, click
CoreMP7.
2.
Click the Add button in the "Selected Component's Details" section. The CoreMP7 component
appears in your design.
3.
In the "Components available for selection" section, click CoreMP7Bridge.
4.
Click the Add button in the "Selected Component's Details" section.
5.
Following the same process as in steps 4–5, add the component CoreAHB.
CoreMP7 Development Kit User’s Guide
Actel CoreConsole 1.1
6.
Once all three components have been added to the design, it should resemble Figure 5-2.
Note: Some of the components are overlapping. To arrange the components neatly, select Auto
Layout from the Actions menu.
Figure 5-2. CoreConsole Schematic Window before Auto Layout
7.
Following the process in steps 4–5, add the CoreMemCtrl component. When it appears in the
schematic window, you can drag it to the right of CoreMP7 for neater appearance.
CoreMP7 Development Kit User’s Guide
35
Quickstart Tutorial
To connect components within your CoreConsole project:
1.
From the Actions menu, select Auto Stitch. This displays the Auto Stitching window, as shown
in Figure 5-3.
Figure 5-3. CoreConsole Auto Stitching Window
Auto Stitching connects the critical components of the system together. However, you will still
need to connect most of the top-level signals manually. Manually connecting signals gives you
finite control over the microprocessor’s memory map.
2.
36
Confirm that stitching has been enabled for CoreMP7, CoreMP7Bridge, CoreAHB, and
CoreMemCtrl, as shown in Figure 5-3. Then click the Stitch button.
CoreMP7 Development Kit User’s Guide
Actel CoreConsole 1.1
3.
Once Auto Stitching is complete, your design should resemble Figure 5-4.
Figure 5-4. CoreConsole after Auto Stitching
The steps in the next section show you how to manually connect signals to the system’s top level.
The first set of instructions walks you through connecting the ARM7 JTAG interface to the top
level. The second set of instructions brings the memory bus (both data and address) to the top level
to interface with the Flash and SRAM modules.
4.
To make additional connections, float your mouse over one of the components, such as
CoreMP7Bridge. An options toolbar appears underneath the selected component, as shown in
Figure 5-5.
Figure 5-5. Component Options Toolbar
CoreMP7 Development Kit User’s Guide
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Quickstart Tutorial
5.
Click the Connect icon, the first icon from the left, which resembles a power plug. When you
have done this, the Configuring Connection dialog box appears, as shown in Figure 5-6.
Figure 5-6. CoreConsole Configuring Connection Dialog Box
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CoreMP7 Development Kit User’s Guide
Actel CoreConsole 1.1
6.
CoreMP7Bridge should automatically be selected in the From field. If it is not selected, select
it from the drop-down menu. Then select RV_ICE_If from the From Pin(s) drop-down menu,
as shown in Figure 5-7.
Figure 5-7. Selecting the CoreMP7Bridge RV_ICE_If Pins
7.
Select Top Level in the To drop-down menu.
8.
Enter the signal name “RV” for Connection Label and click Connect.
CoreMP7 Development Kit User’s Guide
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Quickstart Tutorial
9.
Click OK. Your schematic should resemble the one in Figure 5-8.
Figure 5-8. CoreConsole Schematic after Connecting ARM JTAG Interface
10. Click the Connect icon on the floating options menu for the CoreMemCtrl component.
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CoreMP7 Development Kit User’s Guide
Actel CoreConsole 1.1
11. From the Configuring Connection dialog box, select ExternalMemoryInterface in the From
Pin(s) drop-down menu, as shown in Figure 5-9.
Figure 5-9. Selecting the CoreMemCtrl ExternalMemoryInterface Pins
12. Select Top Level in the To drop-down menu.
13. Enter the signal name “Mem” for Connection Label and click Connect.
CoreMP7 Development Kit User’s Guide
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Quickstart Tutorial
14. Click OK. Your schematic should resemble the one in Figure 5-10.
Figure 5-10. CoreConsole Schematic after Connecting the External Memory Interface
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CoreMP7 Development Kit User’s Guide
Actel CoreConsole 1.1
Step 2 – Building the Subsystem within CoreConsole
Before you begin Step 2, you should know how to stitch components together, as taught in Step 1.
For more information on stitching components together, review the instructions in “Step 1 –
Creating the Basic CoreConsole Project” on page 34 or the CoreConsole User Guide.
Adding CoreUARTapb to the System
In this section, you will add a common CoreUARTapb component to the subsystem. CoreUARTapb
has an APB interface (as opposed to the high-speed AHB interface); therefore, a CoreAPB
component is required and will be implemented through a bridge.
1.
2.
Add the CoreAHB2APB, CoreAPB, and CoreUARTapb components. For neater appearance,
move CoreAHB2APB to the right of CoreMP7Bridge, with CoreAPB below the bridges and
CoreUARTapb below CoreAPB.
Connect the components as follows:
• Connect CoreAHB2APB through its AHBslave interface to CoreAHB via the
AHBmslave12 interface.
• Connect CoreUARTapb through its APBslave interface to CoreAPB via the APBmslave3
interface.
• Connect the CoreUARTapb TX signal to Top Level with the connection name UART_TX.
• Connect the CoreUARTapb RX signal to Top Level with the connection name UART_RX.
3.
Once completed, select Auto Stitch from the Actions menu. Confirm that Auto Stitching is
configured to operate on CoreAHB2APB and CoreUARTapb, then click the Stitch button.
CoreConsole will then connect the HCLK and nRESET pins to the components you added,
and connect CoreAHB2APB to CoreAPB as a master.
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Quickstart Tutorial
4.
Once completed, your CoreConsole schematic should look similar to Figure 5-11.
Figure 5-11. CoreConsole Schematic after Connecting CoreUARTapb
To add the I/O block and system control registers to the system:
1.
2.
Add the CoreGPIO and CoreRemap components. For neater appearance, move CoreGPIO
and CoreRemap to the right of CoreUARTapb.
Connect the components as follows:
• Connect CoreGPIO through its APBslave interface to CoreAPB via the APBmslave2
interface.
• Connect CoreRemap through its APBslave interface to CoreAPB via the APBmslave15
interface.
• Connect the CoreRemap CoreRemapDef pin to Top Level using the signal name
ReMapDef.
• Connect the CoreGPIO dataIn pin to Top Level using the signal name keyPadIn.
• Connect the CoreGPIO dataOut pin to Top Level using the signal name ledOut.
3.
44
Once completed, select Auto Stitch from the Actions menu.
CoreMP7 Development Kit User’s Guide
Actel CoreConsole 1.1
4.
Confirm that Auto Stitching is configured to operate on CoreGPIO and CoreRemap, then click
the Stitch button.
CoreConsole will then connect the HCLK and nRESET pins to the components you added.
5.
Once completed, your CoreConsole schematic should look similar Figure 5-12.
Figure 5-12. CoreConsole Schematic after Connecting CoreGPIO and CoreRemap
CoreMP7 Development Kit User’s Guide
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Quickstart Tutorial
Step 3 – Reviewing and Generating the CoreConsole Design
Even though you can manually view the design connections in a system of this size, this section
explores features in CoreConsole for reviewing your design connections.
To review the CoreConsole design connections:
1.
From the View menu, select Connections. The Connections dialog box appears.
2.
Examine the connections within the system for accuracy.
3.
Click a connection. The appropriate Connection dialog box displays. If necessary, you can make
modifications to the connection.
4.
Click OK to close the Connections window.
Displaying Linked Connections
Another useful tool is Show Linked Connections, which enables you to see all of your linked
connections at once. This feature is enabled by default, but you can change this from System
Options > Options.
In the schematic window, position your mouse cursor over HCLK on the Top Level bar and notice
all the highlighted linked connections. You can perform this action with all of the system signals.
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CoreMP7 Development Kit User’s Guide
Actel CoreConsole 1.1
Modifying Configuration Settings
Prior to generating the source code necessary for Actel Libero IDE, you must modify the
configuration settings.
1.
Position your mouse cursor over the CoreMP7 component and click the Configure button (the
second button from the left, with the binary digits).
The Configuring CoreMP7 dialog box displays, as shown in Figure 5-13.
Figure 5-13. Configuring CoreMP7 Dialog Box
2.
From the drop-down menu for Die, select M7A3PE600. This is the device populated on the
CoreMP7 Evaluation Board.
3.
Click OK.
Within the Configuring CoreMP7 dialog box, you can disable the JTAG debug interface, which
allows you to select the "fast" version of CoreMP7.
4.
Invoke the Configuration dialog boxes for the CoreMP7Bridge and CoreUARTapb
components.
5.
In the Device family field, select ProASIC3E from the drop-down menu and click OK.
6.
Select the Generate tab within the design manager.
7.
Select the HDL language preference. This tutorial is based on Verilog, so make sure Verilog is
selected.
8.
Click the Save & Generate button.
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Quickstart Tutorial
Before exiting CoreConsole, wait until both progress bars have reached 100% (Figure 5-14). This
process can take up to 45 seconds, depending on system complexity and PC resources.
Figure 5-14. CoreConsole Generate Tab
Once the generation phase has successfully completed, you can import your CoreConsole project
(i.e., HDL source files and the ARM7 black box) into Actel Libero IDE.
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CoreMP7 Development Kit User’s Guide
Actel Libero IDE v7.1
Actel Libero IDE v7.1
Step 1 – Create a New Project
This step uses the Libero IDE HDL Editor to enter an Actel CoreMP7 Verilog design.
To create the Libero IDE Verilog project:
1.
Double-click the Libero IDE icon on your desktop to start the program.
2.
From the File menu, select New Project. This displays the New Project Wizard, shown in
Figure 5-15.
Figure 5-15. New Project Wizard in Libero IDE
3.
Enter your Project name. For this tutorial, name your project “ReversiTutorial”.
4.
Select your HDL type. For this tutorial select Verilog.
5.
If necessary, in the Project location field, click Browse to navigate to C:\Actelprj. Click Next to
continue.
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Quickstart Tutorial
6.
Select your project Family, Die, and Package. For this tutorial, select ProASIC3E, the
M7A3PE600 die, and 484 FBGA for the package (Figure 5-16).
Figure 5-16. Select ProASIC3E, M7A3PE600, and 484 FBGA
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CoreMP7 Development Kit User’s Guide
Actel Libero IDE v7.1
7.
Click Next to select integrated tools in the New Project Wizard (Figure 5-17).
Figure 5-17. Selecting Integrated Tools in the Libero IDE New Project Wizard
8.
Click the Restore Defaults button to use the default tools included with Libero IDE.
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Quickstart Tutorial
9.
Click the Add button to add a different Synthesis, Simulation, or Stimulus tool. If you wish to
add a tool, Libero IDE opens the Add Profile dialog box (Figure 5-18).
Figure 5-18. Add Profile Dialog Box in Libero IDE
10. Name your profile, select a tool from the list of Libero IDE supported tools, and Browse to the
location of your tool. Click OK to return to the New Project Wizard.
11. After you have selected your tools, click Next to continue.
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CoreMP7 Development Kit User’s Guide
Actel Libero IDE v7.1
12. Click Add Files in the New Project Wizard to add existing project design files. Include any
ACTgen cores, CoreConsole Projects, Block Symbol, Schematic, Verilog Source,
Implementation, or Stimulus files (Figure 5-19).
Figure 5-19. Add Files in the Libero IDE New Project Wizard
13. Select the CoreConsole Project file type and click Add Files. Browse to your CoreConsole
Project created earlier (assuming default installation it will be located in the
C:\CoreConsole\Libero IDE Export\TutorialMP7\ directory) and select the TutorialMP7.ccp file,
then click Add.
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Quickstart Tutorial
The CoreConsole project will be displayed in the project wizard (Figure 5-20).You can add as
many files as you like this way. For this project, only the CoreConsole file will be imported with
this method.
Figure 5-20. CoreConsole Project Added to the New Libero IDE Project
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14. Review your project information. Click Finish to close the Wizard and create your new project
(Figure 5-21). Click Back to return to any step of the Wizard and correct information in your
project.
Figure 5-21. Summary in New Project Wizard
Your Libero IDE project exists, but you must add some top-level code or source to the project—such
as a schematic, SmartGen core, or Verilog module—before you can run synthesis.
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To add a Verilog top-level HDL file to the project:
1.
From the File menu, select Import Files. Navigate to the \Tutorial\FPGA directory on the
CD-ROM included with the CoreMP7 Development Kit and select the TutorialTop.v file.
Click Import.
2.
Click on the Design Hierarchy tab located at the bottom of the Libero IDE Design File
Manager, as shown in Figure 5-22.
Figure 5-22. Libero IDE Design File Manager
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3.
From the Design Hierarchy, right-click the TutorialTop.v file and select Set as Root (see Figure
5-23). This sets the project’s top-level file to the module contained in the source file just
imported.
4.
Click the File Manager tab to return to the Libero IDE Design File Manager.
Figure 5-23. Libero IDE Design Hierarchy Viewer
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Step 2 – Perform Pre-Synthesis Simulation
The next step is simulating the RTL description of the design. First, you must create a top-level
testbench to provide a stimulus for the design. Keep in mind you will not be able to simulate
CoreMP7 but will rely on the Bus Functional Model (BFM), which is a cycle-accurate model of the
embedded ARM7TDMI-S processor.
To create the top-level testbench:
1.
From the File menu, select File and then New. This opens the New dialog box, shown in Figure
5-24.
2.
Select Stimulus HDL File in the File Type field, enter “TutorialTop_tb” in the Name field, and
click OK. The HDL Editor opens. Enter the following text in a Verilog file, or if this document
is open in an electronic form, copy and paste it from here. Alternatively, this file is provided in
the \Tutorial\FPGA folder on the CD-ROM, and you can import the testbench as you did with
the top-level source file.
Figure 5-24. New File Dialog Box
‘timescale 1ns/100ps
module testbench();
parameter SYSCLK_PERIOD = 100; // 10MHz
reg SYSCLK;
reg NSYSRESET;
wire ICE_nSRST;
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pullup (weak1) p1 (ICE_nSRST);
initial
begin
SYSCLK = 1’b0;
NSYSRESET = 1’b0;
// Release system reset
#(SYSCLK_PERIOD * 4)
NSYSRESET = 1’b1;
#(SYSCLK_PERIOD * 100000);
$stop;
end
// SYSCLK signal
always @(SYSCLK)
#(SYSCLK_PERIOD / 2)
SYSCLK <= !SYSCLK;
// Instantiate module to test
TutorialTop TutorialTop_0 (
.SYSCLK(SYSCLK),
.NSYSRESET(NSYSRESET),
.RemapDefault(1’b0),
.HIGH(),
.LOW(),
.FLASH_BYTEN(),
.FLASH_CSN(),
.FLASH_OEN(),
.FLASH_RPN(),
.FLASH_WEN(),
.SRAM_ADSC(),
.SRAM_ADSP(),
.SRAM_ADV(),
.SRAM_BYTEN(),
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.SRAM_BYTE_WEN(),
.SRAM_CLK(),
.SRAM_CSN(),
.SRAM_GLOBAL_WEN(),
.SRAM_OEN(),
.SRAM_PWRDWN(),
.MEM_ADDR(),
.MEM_DATA(),
.SW(8’b0),
.LED(),
.RX0(1’b0),
.TX0(),
.ICE_nTRST(),
.ICE_TCK(1’b0),
.ICE_TDI(1’b0),
.ICE_TMS(1’b1),
.ICE_VTref(),
.ICE_TDO(),
.ICE_RTCK(),
.ICE_nSRST(ICE_nSRST),
.ICE_DBGACK(),
.ICE_DBGRQ()
);
endmodule
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3.
From the File menu, click Save. The testbench file now appears in the Libero IDE Design
Manager. Libero IDE lists TutorialTop_tb.v under Stimulus Files, as shown in Figure 5-25.
Figure 5-25. Libero IDE File Manger with Stimulus
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4.
Check the HDL in the file before you continue. Under the File Manager tab (Figure 5-26),
right-click TutorialTop_tb.v and select Check HDL. This checks the syntax of TutorialTop_tb.v.
Before moving to the next section, modify the code if you find any errors.
Figure 5-26. Check HDL Option from File Manager
To perform a pre-synthesis simulation:
1.
From the Design Hierarchy tab, right-click the TutorialTop.v file and select Organize
Stimulus, as shown in Figure 5-27.
Figure 5-27. Design Hierarchy Context Menu
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The Organize Stimulus dialog box appears, as shown in Figure 5-28.
Figure 5-28. Organize Stimulus Dialog Box
2.
Select TutorialTop_tb.v from the Stimulus files in the project list box and click Add to add the
file to the Associated files list.
3.
Click OK. Stimulus icons in the Design Flow window turn green to notify you that there is a
testbench file associated with the project.
4.
Right-click the Simulation icon in the Libero IDE Design Flow window and select Options,
as shown in Figure 5-29.
Figure 5-29. Simulation Context Menu
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The Project Settings: Simulation options window appears (Figure 5-30).
Figure 5-30. Simulation Project Settings
5.
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Change the Simulation run time from 1000ns to 5000ns, as shown in Figure 5-30, and click
OK. Changing the run time allows the default BFM test scripts to complete without having to
invoke additional run time from within the ModelSim simulator.
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6.
Click the Simulation icon in the Design Flow window, or right-click TutorialTop.v in the
Design Hierarchy and select Run Pre-Synthesis Simulation, as shown in Figure 5-31.
Figure 5-31. Running Pre-Synthesis Simulation from the TutorialTop.v Context Menu
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The ModelSim simulator opens and compiles the source files, as shown in Figure 5-32.
Figure 5-32. ModelSim Main Window
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Once the compilation completes, the simulator simulates for the default time period of 5000 ns, and
a wave window, shown in Figure 5-33, opens to display the simulation results. The default wave
window currently contains only the SYSCLK and NSYSRESET signals. You will expand this
shortly. The results of the default BFM scripts can also be viewed in the ModelSim log window (as
shown in Figure 5-32 on page 66). The successful reads and writes confirm that CoreMP7 is
connected properly from the top level down to the various busses.
Figure 5-33. ModelSim Wave Window
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7.
To add the CoreMP7 signals to the ModelSim Wave window, navigate to the CoreMP7E600D
instance in the ModelSim workspace, which can be found under the following hierarchy (shown
in Figure 5-34):
TutorialTop_0 > TutorialTop > CoreMP7E600D
Drag the CoreMP7E600D instantiation to the ModelSim wave window. The instantiation’s
signals will appear.
Figure 5-34. ModelSim Workspace Window
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8.
In the ModelSim Transcript (Log) window, type restart. This will bring up the Restart dialog
box (shown in Figure 5-35). Click the Restart button. This will reset the simulation to the
beginning so that logging of the CoreMP7 signals occurs.
Figure 5-35. ModelSim Restart Dialog Box
9.
Within the ModelSim Transcript window, type run–all. This will re-run the default testbench
and BFM scripts. The results should be the same as the previous run. Notice the ModelSim
Wave window—the CoreMP7 signals now have waveforms associated with them.
10. Undock the ModelSim Wave window and maximize it, then select Zoom Full from the
View > Zoom menu. Examining the ADDR, RDATA, WDATA, WRITE, SIZE, SYSCLK,
nRESET, and NSYSRESET signals allows the re-creation of the BFM scripts and validates the
results. The corresponding signals have been grouped together and are shown in Figure 5-36.
Figure 5-36. ModelSim Wave Window with CoreMP7 Signals
11. In the ModelSim window, select File then Quit to close the window.
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Step 3 – Synthesize the Design in Synplify
The next step is to generate an EDIF netlist by synthesizing the design in Synplify. For HDL
designs, Libero IDE launches and loads the Synplify Synplicity synthesizer with the appropriate
design files.
To create an EDIF netlist for the design using Synplify:
1.
In Libero IDE, click the Synplify Synthesis icon in the Design Flow window, or right-click the
TutorialTop.v file in the Design Hierarchy and select Synplify Synthesis. This launches the
Synplify synthesis tool with the appropriate design files, as shown in Figure 5-37.
Figure 5-37. Synplify Synthesis Main Window
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2.
From the Project menu, select Implementation Options. This displays the options for the
Implementation dialog box, as shown in Figure 5-38 for the M7A3PE600.
Figure 5-38. Implementation Options Dialog Box for the M7A3PE600
3.
Set (confirm) the following in the dialog box:
• Technology: Actel ProASIC3E (set automatically by Libero IDE)
• Part: M7A3PE600
• Fanout Guide: 12 (default)
• Hard limit to Fanout: Off (default)
4.
Accept the default values for each of the other tabs in the Options for Implementation dialog
box and click OK.
5.
In the Synplify main window, click Run. Synplify compiles and synthesizes the design into a
netlist called TutorialTop.edn. This netlist is then automatically translated by Libero IDE into a
Verilog netlist called TutorialTop.v.
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The resulting EDIF and Verilog files are displayed under Implementation Files in the Libero
IDE File Manager.
6.
If any errors appear after you click the Run button, edit the file using the Synplify editor. To edit
the file, double-click the file name in the Synplicity window. Any changes made here are saved
to the original design file in Libero IDE.
7.
Save and close Synplify. From the File menu, click Exit to close Synplify. Click Yes to save any
settings made to the TutorialTop_syn.prj file in Synplify.
Step 4 – Perform Post-Synthesis Simulation
The next step is simulating the Verilog netlist of the design using the Verilog testbench created in
“Step 2 – Perform Pre-Synthesis Simulation” on page 58.
1.
Click the Simulation icon in the Libero IDE Design Flow window, or right-click the
TutorialTop.v file in the Design Hierarchy tab and select Run Post-Synthesis Simulation. This
launches the ModelSim simulator, which compiles the source files and testbench.
Once the compilation completes, the simulator runs for 5000 ns and the Wave window displays
the simulation results. Verify that the read/write results of the executed BFM scripts are correct.
2.
Follow the same sequence as in “Step 2 – Perform Pre-Synthesis Simulation” on page 58,
beginning with step 7, to add and verify the internal CoreMP7 signals of the BFM.
3.
Scroll in the Wave window to verify that the CoreMP7 system works correctly. Use the zoom
buttons to zoom in and out as necessary.
Step 5 – Implementing the Design with Actel Designer
After creating and simulating the design, the next phase is implementing the design using the Actel
Designer software (performing place-and-route).
1.
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From the Libero IDE File menu, select Import Files. Navigate to the \Tutorial\FPGA directory
on the Development Kit CD-ROM and select the TutorialTop_PinConstraints.pdc file. It might
be necessary to change the file type to PDC to view this file. Click Import. The file will now be
listed under Constraint Files in the Libero IDE File Manager.
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2.
Click the Designer Place & Route button in the Libero IDE Design Flow window, or rightclick TutorialTop.v in the Design Hierarchy tab and select Run Designer. Designer reads in the
design file (Figure 5-39).
Figure 5-39. Actel Designer GUI
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The Device Selection Wizard opens (Figure 5-40).
Figure 5-40. Device Selection Wizard for M7A3PE600
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3.
Select M7A3PE600 in the Die field and 484 FBGA in the Package field. Accept the default
Speed grade and Die voltage and click Next.
4.
Use the default I/O settings and click Next.
5.
Use the default Junction Temperature and Voltage setup and click Finish.
6.
From the Designer File menu, select Import Source Files.
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This displays the Import Source Files dialog box (Figure 5-41). Click the Add button, navigate
to the Libero IDE project’s \constraint directory, and add the TutorialTop_PinConstraints.pdc file
(it may be necessary to change the file type to view the PDC file). Once the file has been added,
click OK.
Figure 5-41. Import Source Files Dialog Box in Designer
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7.
When the EDIF Import Options dialog box appears, as in Figure 5-42, click OK. This will reimport the source files (all three of them) into Designer.
Figure 5-42. EDIF Import Options Dialog in Designer
8.
Click the Compile icon. Leave the default Compile settings (Figure 5-43) and click OK.
Figure 5-43. Compile Options Window
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Designer compiles the design and shows the utilization of the selected device. Also, note that
the Compile icon in Designer turns green once the compile has successfully completed.
9.
Once the design compiles successfully, use the I/O Attribute Editor tool to verify the pin
assignments imported from the pin constraints file. Alternatively, the I/O Attribute Editor can
be used to create pin assignments. Click the I/O Attribute Editor to open the tool. It opens in
the MultiView Navigator user interface, as shown in Figure 5-44.
Figure 5-44. I/O Attribute Editor in MultiView Navigator
10. Verify that the correct pins have been assigned to all of the signals. If changes are made, select
Commit from the File menu and then close the I/O Attribute Editor.
Optional: After successfully compiling the design, use the Designer Tools to view the pre-layout
static timing analysis with SmartTime, set the timing constraints in SmartTime, analyze the
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static and dynamic power with SmartPower, and use the ChipPlanner to assign modules. Click
the appropriate icons to access these tools.
For more information on these functions, refer to the Designer or Libero IDE online help.
11. In Designer, click Layout. This opens the Layout Options dialog box, shown in Figure 5-45.
Figure 5-45. Layout Options Dialog Box
12. Click OK to accept the default layout options. This runs place-and-route on the design. The
Layout icon turns green to indicate that the layout has successfully completed.
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13. From Designer, click Back-Annotate in the Design Flow window. This opens the BackAnnotate dialog box, shown in Figure 5-46.
Figure 5-46. Back-Annotate Dialog Box
14. Accept the default settings and click OK. The Back-Annotate icon turns green.
15. Save and close Designer. From the File menu, click Exit. Click Yes to save the design before
closing Designer. Designer saves all the design information in an ADB file.
The file TutorialTop.adb appears under the Designer Files tab of the File Manager. To re-open
the file, right-click it and select Open in Designer.
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Step 6 – Perform Timing Simulation with Back-Annotated Timing
After completing place-and-route and back-annotation of the design, perform a timing simulation
with the ModelSim HDL simulator.
To perform a timing simulation:
1.
Click the Simulation icon in the Libero IDE Design Flow window, or right-click the
TutorialTop.v file under the Design Hierarchy tab and select Run Post-Layout Simulation.
2.
This launches the ModelSim Simulator, which compiles the back-annotated Verilog netlist file
and testbench.
Once the compilation completes, the simulator runs for 5000 ns and the Wave window displays
the simulation results. Verify that the read/write results of the executed BFM scripts are correct.
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3.
Follow the same sequence as in “Step 2 – Perform Pre-Synthesis Simulation” on page 58,
beginning with step 7, to add and verify the internal CoreMP7 signals of the BFM.
4.
Scroll in the Wave window to verify that the CoreMP7 system works correctly. Use the zoom
buttons to zoom in and out as necessary.
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Step 7 – Generating the Programming File
1.
Open the TutorialTop.adb file in Designer and click the Programming File button in the Design
Flow window, which opens the FlashPoint window (Figure 5-47).
2.
Click Finish. The programming file is generated and saved in the \designer\impl1 folder. The
Programming File icon in the Designer Design Flow window should now be green, indicating
that programming file generation has been successfully completed.
3.
Save and close Designer. From the File menu, click Exit. Click Yes to save the design before
closing Designer.
Figure 5-47. Flash Point Dialog Box
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Step 8 – Programming the Device
After generating the programming file, program the device using an Actel FlashPro3 programmer.
Before performing any action with the FlashPro3 programmer, it must be properly set up. Connect
the FlashPro3 USB cable to your PC USB port, connect the ribbon cable to the programming
header on the target board, and turn on the power switch on the board.
1.
Click the FlashPro Programming button in the Libero IDE Design Flow window, or rightclick TutorialTop.v under the Design Hierarchy tab and select Run FlashPro.
FlashPro opens (Figure 5-48).
Figure 5-48. FlashPro Desktop – Prior to Locating Programmer(s)
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FlashPro establishes a communication channel with the FlashPro3 programmer(s) attached to
the PC (Figure 5-49).
Figure 5-49. FlashPro Desktop – After Locating Programmer(s)
2.
When launching FlashPro from within Libero IDE, the project STAPL file is automatically
loaded and configured. To verify the STAPL file being used to program the device, click the
Configure STAPL File button.
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The STAPL Configuration window (Figure 5-50) appears.
Figure 5-50. STAPL Configuration Window
3.
Here the programming file may be changed by clicking the Browse button and navigating to the
new programming file. Various Actions may be performed using the drop-down selections. For
this tutorial, leave it set to PROGRAM (default).
For more information on these functions, refer to the FlashPro online help.
To return to the Programmer List window (Figure 5-51), click the View Programmers
button.
Figure 5-51. Programmers List Window
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4.
Verify that the attached programmer’s check box is selected under the Programmer Enabled
heading, then click the Program button.
5.
Programming will take approximately two and a half to three minutes to complete. Under the
Programming Status heading, a progress bar will appear. Alternatively, the log window may also
be viewed (Figure 5-52).
Figure 5-52. FlashPro Log Window
6.
Once programming has completed, select Exit from the File menu. Answer Yes when prompted
to save the project. This will return you to Libero IDE.
7.
From the Libero IDE File menu, select Exit. If prompted to save your project, answer Yes, as
this completes the Libero IDE FPGA portion of this tutorial.
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ARM RealView Developer Kit – Actel Edition
The RealView Developer Kit, available from Actel (separately from the CoreMP7 Development
Kit), contains an integrated project manager and file editor suitable for creating and developing
embedded projects. In this section, we’ll create the executable source code to be run on CoreMP7.
No coding will be required in this section, as we’ll use source code included with the CoreMP7
Development Kit.
Step 1 – Creating a RealView Project
To create a RealView project:
1.
Copy the contents from the \Tutorial\MPU directory on the CoreMP7 Development Kit
CD-ROM to the C:\CoreMP7\Tutorial\Source directory, which must be created.
2.
Launch the RealView Debugger 1.8 program located under Start > ARM > RealView
Developer Suite 2.2.
Prior to launching RealView Debugger, the RealView ICE Micro Edition must be connected
to the PC via the USB port. For information on installing and configuring the drivers for the
RealView ICE Micro Edition, see the RealView ICE – Micro Edition User's Guide on the
RealView Developer Kit – Actel Edition CD-ROM.
3.
From the Project menu, select New Project. This displays the Create New Project dialog box,
as shown in Figure 5-53.
Figure 5-53. RealView Create New Project Dialog Box
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4.
Click the Navigate button (the folder to the right of Project Base), select <Select Dir…> from
the context menu, and browse to the project directory: C:\CoreMP7\Tutorial. Click Select.
5.
Ensure the Standard Project radio button is selected, and enter “ReversiBasicEngine” in the
Project Name field. Click OK. This displays the Create Standard Project dialog box, shown in
Figure 5-54.
Figure 5-54. RealView Create Standard Project Dialog Box
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6.
Again, click the navigate button (to the right of Sources to build from) to open the Select
Source Files for Project dialog box (Figure 5-55).
7.
Navigate to the C:\CoreMP7\Tutorial\Source directory and press CTRL + A to select all the files
within the directory.
8.
Click Open.
Figure 5-55. RealView Select Source Files for Project Dialog
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9.
Click OK in the Create Standard Project dialog box. The Project Properties window now
appears (Figure 5-56).
Figure 5-56. RealView Project Properties
10. Click the CONFIGURATION entry in the left-hand window pane to view the available
project build variants.
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11. Right-click the Active config entry in the CONFIGURATION pane and select DebugRel
from the context menu, as shown in Figure 5-57.
Figure 5-57. RealView Project Properties Configuration Options
The Configuration settings enable you to build your application program in different ways. They
define the target configurations used in the build model. The most common target
configurations are a Debug build, with debug information and no code optimization, and a
Release build, with less debug information and high optimization.
This group can also be used to set up different optimization levels—for example, a DebugRel
configuration with higher optimization than Debug but lower than Release. Another example is
multiple variants of your application using different device drivers.
See the RealView documentation available at http://www.arm.com/documentation/
Trace_Debug/index.html or refer to online help for further information on this subject.
12. Expand the BUILD entry by clicking the plus sign to the left of its folder, and then select the
Link Advanced sub-menu component.
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13. Right-click the Scatter file entry in the Link Advanced pane and select Edit as Filename from
the context menu, as shown in Figure 5-58.
Figure 5-58. RealView Project Properties Build Options
14. Browse to the ..\CoreMP7\Tutorial\Source directory and select the CoreMP7DevKit.scf scatter
map description file.
The scatter file is used to tell the linker where to load files or objects residing in memory. For
detailed reference information on the linker and scatter-loading, refer to the ARM Developer
Suite Linker and Utilities Guide.
The benefit of using a scatter description file is that all the (target-specific) absolute addresses
chosen for your devices, code, and data are located in one file, making maintenance easy.
Furthermore, if you decide to change your memory map (e.g., if peripherals are moved), you do
not need to rebuild your entire project. You only need to re-link the existing objects.
15. Also within the Link Advanced menu, set the Entry point to Reset_Handler.
16. From the File menu, select Save and Close. This will return you to the RealView Debugger
desktop where you might see the compiler attempt to compile the source files with a makefile,
which fails due to missing files. Ignore this error/warning.
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Step 2 – Compiling the Source Files
Compiling Source Files
1.
From the Build menu, select Build. Select Yes if you are asked if you would like to Rebuild All.
The output of the Build pane appears with several messages generated as a result of the
attempted build, as shown in Figure 5-59. If errors were present in your source code, they would
be listed with the corresponding filename, line number, and a brief description of the error.
If an error is found, the Code pane of the RealView Debugger opens the relevant source file with
an arrow pointing to and highlighting the line of source code the first error message is
referencing. Correct the error, save the modified source file, and then rebuild the project, and
continue this process until no errors are present upon Compile.
Figure 5-59. RealView Debugger Build Pane
2.
If a project is already up-to-date, building will not occur when it is requested. If you wish to do
a forced rebuild of all source files, select Clean from the Build menu, which deletes the relevant
object files, and then select Rebuild All from the Build menu to rebuild the entire project.
Step 3 – Debugging: Simulating/Executing the Compilation
Simulator versus Emulator
A simulator attempts to model the entire behavior of a processor in software running on your
personal computer. No matter the speed of your PC, there is no simulator that can simulate the
microprocessor’s real-time behavior. Further, there is no external world communication between the
simulator and your target system. Stimulus files must be created and used to simulate external events.
On the other hand, emulators typically replace the processor on the target board and interface
directly with the external world. The emulator provides the user with all the features of simulation
plus the capabilities of interfacing with the external world and running at full system speed.
Emulators exist in two forms: Debug Modules and In-Circuit Emulation (ICE).
The Debug Module approach combines all of the emulator electronics and the actual emulation chip
into a single PCB, which connects to the target by ribbon cables, providing a connector that can plug
into an actual chip package of the target processor. All signals for the emulated microprocessor pass
through the ribbon cable that connects to the target system.
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The ICE approach is slightly different. The ICE interfaces directly to the On-Chip Debug system
within the actual processor. This provides an interface for complete control of the target processor—
typically JTAG, but sometimes a proprietary interface, already embedded into the target processor.
The exact electrical and timing characteristics of the target system are achieved when using the OnChip Debug system, whereas the Debug Module approach may provide additional features and
access to internals of the target. For that reason, simulators are best suited for the testing of
algorithms.
Configuring the Simulator / On-Chip Debugger
The frontend tools for performing emulation are exactly the same. The only differences between
simulation and emulation are the initial setup steps, specifically steps 3–6. The alternative steps for
performing emulation are discussed in “Alternative Steps for Using the On-Chip Debugger” on page
101.
1.
Click the Src tab in the RealView Debugger Debug window. The Code pane shows that there
is currently not a target connected to the debugger.
2.
Click the Connect to Target link to launch the Connection Control dialog.
3.
Expand the Server > localhost branches in the name tree, then right-click new_arm and select
Configure Device Info, as shown in Figure 5-60.
Figure 5-60. RealView Debugger Connection Control Dialog Box
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4.
The ARMulator Configuration dialog box appears. Select the ARM7TDMI-S processor, as
shown in Figure 5-61. Click OK to return to the Connection Control dialog box.
Figure 5-61. ARMulator Configuration Dialog Box
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5.
Select the new_arm check box under the name tree. A new simulation object, Simarm_1, will
be instantiated, as shown in Figure 5-62.
Figure 5-62. RealView Connection Control with Simulation Object
6.
The RealView Debugger is now connected to the ARM7TDMI-S Instruction Set Simulator
target. You may now close or minimize the Connection Control dialog box.
7.
The RealView Debugger Code pane prompts for the loading of the recently built image to the
target. Clink the Load link to load the image. If the Code pane is not prompting you to load an
image, click the Code tab at the bottom of the Code pane.
CoreMP7 Development Kit User’s Guide
95
Quickstart Tutorial
8.
The code is now loaded into the target. The current point of execution is identified by the red
box, as shown in Figure 5-63. The code currently being displayed is the basic initialization (or
bootloader) code, which is typically written in assembly language.
Figure 5-63. RealView Debugger Code Pane with Loaded Target
Debugging the Design
This section will touch on the basics of debugging from the simulation point of view. The primary
goal of this section is to learn the very basic features of the debugger, as their application in the
following example is rudimentary.
1.
Open the basicengine.cpp source file found in the ..\CoreMP7\Tutorial\Source directory using the
Open option under the File menu.
2.
Select Show Line Numbers from the Advanced sub-menu of the Edit menu to display line
numbers in the margins of the source code.
3.
Set a breakpoint on line 15, the “Reversi m reversi;” statement, by double-clicking to the left of
the line number. A red breakpoint marker will appear to the left of the line number, as shown in
Figure 5-64 on page 97.
A breakpoint is a user-defined stopping point in a program that is inserted for debugging
purposes. Breakpoints are a method embedded developers use to gain information about a
96
CoreMP7 Development Kit User’s Guide
ARM RealView Developer Kit – Actel Edition
program during its execution. During the break, the developer can examine the internal contents
of the processor, memory, registers, etc. to ensure proper operation.
Figure 5-64. RealView Code Pane with Breakpoint
4.
Select Run from the Debug menu (or use the F5 shortcut key). The cursor (red box) will now
be present on line 15 (where the breakpoint was set).
5.
Open the position.cpp source file and set a breakpoint on line 125, the “m_board[4][4] = White;”
statement.
CoreMP7 Development Kit User’s Guide
97
Quickstart Tutorial
6.
Right-click m_board and select Watch from the context menu. The m_board array will be
added to the watch window, as shown in Figure 5-65.
Figure 5-65. RealView Debugger Watch Window
A watch is a variable or expression that you require the debugger to display at every step or
breakpoint so that you can see how its value changes. The Watch pane is part of the RealView
Debugger Code window and displays the watches you have defined.
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CoreMP7 Development Kit User’s Guide
ARM RealView Developer Kit – Actel Edition
7.
Within the watch window, expand the m_board variable and then expand the [4] subcomponent (a dimension of the m_board array).
8.
Select Step Into from the Debug menu (or use the F11 shortcut key). The cursor (red box) will
now be present on line 126. Looking at the watch window, you can see that the m_board[4][4]
contents have changed from the default “nbColors” to the value “White.”
9.
Continuing to single-step (or Step Into) three more times, you will see changes in the [5][4],
[5][5], and [4][5] components of the m_board multi-dimensional array.
10. Select Registers from the View menu. The Register window is displayed; you may choose to
“dock” it into the RealView Debugger, as shown in Figure 5-66.
The Register window displays the contents of the internal processor registers at every step or
breakpoint so that you can see how its value changes. The register contents may also be modified
through this interface by simply double-clicking the value and modifying the field.
Figure 5-66. RealView Debugger Register Window
CoreMP7 Development Kit User’s Guide
99
Quickstart Tutorial
11. Right-click one of the <<NoAddr>> values in the RealView Debugger Memory window and
select Set Start Address. Enter the value 0xC2000000. The Memory window will now display
the memory segment contents beginning with the aforementioned address, as shown in Figure
5-67.
Figure 5-67. RealView Debugger Memory Window
The Memory window displays the contents of the memories (both Flash and SRAM), as well as
the memory-mapped peripheral configuration registers, at every step or breakpoint so that you
can see how its value changes. The memory contents may also be modified through this interface
by simply double-clicking the value and modifying the field.
12. If you are debugging with the emulator, you can modify the memory contents at 0xC2000000
and twiddle the LEDs on the CoreMP7 Evaluation Board, thus showing that you have direct
access to the on-chip peripherals.
13. If you wish to run the complete Reversi (also known as Othello) game on the CoreMP7
Development Kit, continue with “Running the Reversi Game via the On-Chip Debugger” on
page 104. Otherwise, end the debugging session by selecting Disconnect from the Target
menu.
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CoreMP7 Development Kit User’s Guide
ARM RealView Developer Kit – Actel Edition
Alternative Steps for Using the On-Chip Debugger
1.
Place a spare jumper on pin #37 and #39 of the J11 header (pins #AB15 and #AB17). Configure
the part to boot from the on-board synchronous SRAM.
2.
Connect the RVI-ME to the CoreMP7 Evaluation Board through the ARM_JTAG header and
power up the board.
3.
Expand the ARM-ARM-USB branch to reveal RVI-ME in the name tree. Right-click
RVI-ME and select Configure Device Info, as shown in Figure 5-68. This launches the
RVConfig utility.
Figure 5-68. RealView Debugger RVI-ME Configure Device
CoreMP7 Development Kit User’s Guide
101
Quickstart Tutorial
4.
Click the Auto Configure Scan Chain button in the RVConfig utility. After a few seconds, the
ARM7TDMI-S processor will be identified, as shown in Figure 5-69.
Figure 5-69. RealView Debugger RVConfig Dialog Box
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CoreMP7 Development Kit User’s Guide
ARM RealView Developer Kit – Actel Edition
5.
From the File menu, select Save. Then select File > Exit and return to the Configuration
Control dialog box.
6.
Select the ARM7TDMI-S check box under the Name tree. It may be necessary to expand the
RVI-ME branch first, as shown in Figure 5-70.
Figure 5-70. RealView Debugger Connection Control with On-Chip Debugger Target
7.
The RealView Debugger is now connected to the ARM7TDMI-S via the On-Chip Debugger.
You may now close or minimize the Connection Control dialog box.
8.
Continue with the Quickstart Tutorial with step 7 on page 95.
CoreMP7 Development Kit User’s Guide
103
Quickstart Tutorial
Running the Reversi Game via the On-Chip Debugger
1.
Reload the ReversiBasicEngine.axf file by selecting Reload Image to Target from the Debug
menu.
2.
Connect the RS-232 connector P2 to the COM1 port of your PC using a standard straightthrough serial cable.
3.
From the Debug menu, select Run (or use the F11 shortcut key). There will be an indicator in
the RealView Debugger status bar which indicates that the target is Running with a small
progress bar.
4.
Minimize the RealView Debugger tool.
5.
Navigate to the ..\Tutorial\Demo directory on the Tutorial CD-ROM and double-click the
ReversiGUI.exe executable.
6.
Pressing SW6, SW7, SW8, SW9, or SW10 will commence the game.
7.
To end the game, select Stop Execution from the Debug menu (or use the SHIFT + F5
shortcut key).
8.
Disconnect from the target by selecting Disconnect from the Target menu. It is now safe to
close the RealView Debugger.
Reversi Background
The object of the game is to own more pieces than your opponent when the game is over. The game
is over when neither player has a move. Usually, this means the board is full. On your turn, you place
one piece on the board with your color facing up. You must place the piece so that your opponent's
piece, or a row of your opponent's pieces, is flanked by your pieces. All of the opponent's pieces
between your pieces are then turned over to become your color.
Game Controls
SW6:
104
Moves the placement box up one unit
SW7:
Moves the placement box down one unit
SW8:
Places a piece
SW9:
Moves the placement box to the left one unit
SW10:
Moves the placement box to the right one unit
CoreMP7 Development Kit User’s Guide
A
M7A3PE600 and M7A3P1000 FG484
Package Connections
Due to the comprehensive and flexible nature of M7 ProASIC3/E device user I/Os, a naming
scheme is used to show the details of each I/O. The name identifies the I/O bank to which the I/O
belongs as well as the pairing and pin polarity for differential I/Os.
I/O nomenclature: Gmn or IOuxwBy
Gmn is only used for I/Os that also have CCC access, i.e., global pins.
G:
Global
m:
Global pin location associated with each CCC on the device: A (northwest corner), B
(northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F
(west middle)
n:
Global input MUX and pin number of the associated global location m: either A0, A1,
A2, B0, B1, B2, C0, C1, or C2
u:
I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding
in a clockwise direction
x:
P (positive) or N (negative) for differential pairs, or R (regular – single-ended) for I/Os
that support single-ended and voltage-referenced I/O standards only. U (positive-LVDS
only) or V (negative-LVDS only) restricts the I/O differential pair from being selected as
an LVPECL pair.
w:
D (differential pair), P (pair) or S (single-ended). D if both members of the pair are
bonded out to adjacent pins or are separated only by one GND or NC pin, P if both
members of the pair are bonded out but do not meet the adjacency requirement, or S if
the I/O pair is not bonded out. For differential pairs, adjacency for ball grid packages
means only vertical or horizontal. Diagonal adjacency does not meet the requirements for
a true differential pair.
B:
Bank
y:
Bank number [0..3] for M7 ProASIC3 and [0..7] for M7 ProASIC3E. The bank
number starts at 0 from the northwest I/O bank and proceeds in a clockwise direction.
Figure A-1 on page 106 and Table A-1 on page 107 are extracted from the ProASIC3 Flash Family
FPGAs with Optional Soft ARM Support and ProASIC3E Flash Family FPGAs with Optional Soft
ARM support datasheets and provide package connections for the M7A3PE600 and M7A3P1000
devices.
CoreMP7 Development Kit User’s Guide
105
M7A3PE600 and M7A3P1000 FG484 Package Connections
Pinouts for other devices in the FG484 family may be found on the Actel website:
ProASIC3 Flash Family FPGAs with Optional Soft ARM Support datasheet at www.actel.com/
documents/PA3_DS.pdf
ProASIC3E Flash Family FPGAs with Optional Soft ARM Support datasheet at www.actel.com/
documents/PA3E_DS.pdf
These datasheets are included on the CoreMP7 Development Kit CD. However, always refer to the
website for the most recent datasheet.
484-Pin FGBGA Package
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Figure A-1. 484-Pin FGBGA Package Layout
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CoreMP7 Development Kit User’s Guide
484-Pin FGBGA Package
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections
Pin Number
M7A3P1000 Function
M7A3PE600 Function
A1
GND
GND
A2
GND
GND
A3
VCCIB0
VCCIB0
A4
IO07RSB0
IO06NDB0V1
A5
IO09RSB0
IO06PDB0V1
A6
IO13RSB0
IO08NDB0V1
A7
IO18RSB0
IO08PDB0V1
A8
IO20RSB0
IO11PDB0V1
A9
IO26RSB0
IO17PDB0V2
A10
IO32RSB0
IO18NDB0V2
A11
IO40RSB0
IO18PDB0V2
A12
IO41RSB0
IO22PDB1V0
A13
IO53RSB0
IO26PDB1V0
A14
IO59RSB0
IO29NDB1V1
A15
IO64RSB0
IO29PDB1V1
A16
IO65RSB0
IO31NDB1V1
A17
IO67RSB0
IO31PDB1V1
A18
IO69RSB0
IO32NDB1V1
A19
NC
NC
A20
VCCIB0
VCCIB1
A21
GND
GND
A22
GND
GND
AA1
GND
GND
AA2
VCCIB3
VCCIB7
AA3
NC
NC
AA4
IO181RSB2
IO03NDB0V0
CoreMP7 Development Kit User’s Guide
107
M7A3PE600 and M7A3P1000 FG484 Package Connections
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
108
Pin Number
M7A3P1000 Function
M7A3PE600 Function
AA5
IO178RSB2
IO03PDB0V0
AA6
IO175RSB2
IO07NDB0V1
AA7
IO169RSB2
IO07PDB0V1
AA8
IO166RSB2
IO11NDB0V1
AA9
IO160RSB2
IO17NDB0V2
AA10
IO152RSB2
IO14PDB0V2
AA11
IO146RSB2
IO19PDB0V2
AA12
IO139RSB2
IO22NDB1V0
AA13
IO133RSB2
IO26NDB1V0
AA14
NC
NC
AA15
NC
NC
AA16
IO122RSB2
IO30NDB1V1
AA17
IO119RSB2
IO30PDB1V1
AA18
IO117RSB2
IO32PDB1V1
AA19
NC
NC
AA20
NC
NC
AA21
VCCIB1
VCCIB2
AA22
GND
GND
AB1
GND
VCCIB7
AB2
GND
NC
AB3
VCCIB2
NC
AB4
IO180RSB2
NC
AB5
IO176RSB2
GND
AB6
IO173RSB2
IO04NDB0V0
AB7
IO167RSB2
IO04PDB0V0
AB8
IO162RSB2
VCC
AB9
IO156RSB2
VCC
AB10
IO150RSB2
IO14NDB0V2
CoreMP7 Development Kit User’s Guide
484-Pin FGBGA Package
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
Pin Number
M7A3P1000 Function
M7A3PE600 Function
AB11
IO145RSB2
IO19NDB0V2
AB12
IO144RSB2
NC
AB13
IO132RSB2
NC
AB14
IO127RSB2
VCC
AB15
IO126RSB2
VCC
AB16
IO123RSB2
NC
AB17
IO121RSB2
NC
AB18
IO118RSB2
GND
AB19
NC
NC
AB20
VCCIB2
NC
AB21
GND
NC
AB22
GND
VCCIB2
B1
GND
NC
B2
VCCIB3
NC
B3
NC
NC
B4
IO06RSB0
GND
B5
IO08RSB0
GAA0/IO00NDB0V0
B6
IO12RSB0
GAA1/IO00PDB0V0
B7
IO15RSB0
GAB0/IO01NDB0V0
B8
IO19RSB0
IO05PDB0V0
B9
IO24RSB0
IO10PDB0V1
B10
IO31RSB0
IO12PDB0V2
B11
IO39RSB0
IO16NDB0V2
B12
IO48RSB0
IO23NDB1V0
B13
IO54RSB0
IO23PDB1V0
B14
IO58RSB0
IO28NDB1V1
B15
IO63RSB0
IO28PDB1V1
B16
IO66RSB0
GBB1/IO34PDB1V1
CoreMP7 Development Kit User’s Guide
109
M7A3PE600 and M7A3P1000 FG484 Package Connections
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
110
Pin Number
M7A3P1000 Function
M7A3PE600 Function
B17
IO68RSB0
GBA0/IO35NDB1V1
B18
IO70RSB0
GBA1/IO35PDB1V1
B19
NC
GND
B20
NC
NC
B21
VCCIB1
NC
B22
GND
NC
C1
VCCIB3
NC
C2
IO220PDB3
NC
C3
NC
GND
C4
NC
GAB2/IO133PDB7V1
C5
GND
GAA2/IO134PDB7V1
C6
IO10RSB0
GNDQ
C7
IO14RSB0
GAB1/IO01PDB0V0
C8
VCC
IO05NDB0V0
C9
VCC
IO10NDB0V1
C10
IO30RSB0
IO12NDB0V2
C11
IO37RSB0
IO16PDB0V2
C12
IO43RSB0
IO20NDB1V0
C13
NC
IO24NDB1V0
C14
VCC
IO24PDB1V0
C15
VCC
GBC1/IO33PDB1V1
C16
NC
GBB0/IO34NDB1V1
C17
NC
GNDQ
C18
GND
GBA2/IO36PDB2V0
C19
NC
IO42NDB2V0
C20
NC
GND
C21
NC
NC
C22
VCCIB1
NC
CoreMP7 Development Kit User’s Guide
484-Pin FGBGA Package
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
Pin Number
M7A3P1000 Function
M7A3PE600 Function
D1
IO219PDB3
NC
D2
IO220NDB3
IO131NDB7V1
D3
NC
IO131PDB7V1
D4
GND
IO133NDB7V1
D5
GAA0/IO00RSB0
IO134NDB7V1
D6
GAA1/IO01RSB0
VMV7
D7
GAB0/IO02RSB0
VCCPLA
D8
IO16RSB0
GAC0/IO02NDB0V0
D9
IO22RSB0
GAC1/IO02PDB0V0
D10
IO28RSB0
IO15NDB0V2
D11
IO35RSB0
IO15PDB0V2
D12
IO45RSB0
IO20PDB1V0
D13
IO50RSB0
IO25NDB1V0
D14
IO55RSB0
IO27PDB1V0
D15
IO61RSB0
GBC0/IO33NDB1V1
D16
GBB1/IO75RSB0
VCCPLB
D17
GBA0/IO76RSB0
VMV2
D18
GBA1/IO77RSB0
IO36NDB2V0
D19
GND
IO42PDB2V0
D20
NC
NC
D21
NC
NC
D22
NC
NC
E1
IO219NDB3
IO127NDB7V1
E2
NC
IO127PDB7V1
E3
GND
NC
E4
GAB2/IO224PDB3
IO128PDB7V1
E5
GAA2/IO225PDB3
IO129PDB7V1
E6
GNDQ
GAC2/IO132PDB7V1
CoreMP7 Development Kit User’s Guide
111
M7A3PE600 and M7A3P1000 FG484 Package Connections
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
112
Pin Number
M7A3P1000 Function
M7A3PE600 Function
E7
GAB1/IO03RSB0
VCOMPLA
E8
IO17RSB0
GNDQ
E9
IO21RSB0
IO09NDB0V1
E10
IO27RSB0
IO09PDB0V1
E11
IO34RSB0
IO13PDB0V2
E12
IO44RSB0
IO21PDB1V0
E13
IO51RSB0
IO25PDB1V0
E14
IO57RSB0
IO27NDB1V0
E15
GBC1/IO73RSB0
GNDQ
E16
GBB0/IO74RSB0
VCOMPLB
E17
IO71RSB0
GBB2/IO37PDB2V0
E18
GBA2/IO78PDB1
IO39PDB2V0
E19
IO81PDB1
IO39NDB2V0
E20
GND
IO43PDB2V0
E21
NC
IO43NDB2V0
E22
IO84PDB1
NC
F1
NC
NC
F2
IO215PDB3
NC
F3
IO215NDB3
VCC
F4
IO224NDB3
IO128NDB7V1
F5
IO225NDB3
IO129NDB7V1
F6
VMV3
IO132NDB7V1
F7
IO11RSB0
IO130PDB7V1
F8
GAC0/IO04RSB0
VMV0
F9
GAC1/IO05RSB0
VCCIB0
F10
IO25RSB0
VCCIB0
F11
IO36RSB0
IO13NDB0V2
F12
IO42RSB0
IO21NDB1V0
CoreMP7 Development Kit User’s Guide
484-Pin FGBGA Package
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
Pin Number
M7A3P1000 Function
M7A3PE600 Function
F13
IO49RSB0
VCCIB1
F14
IO56RSB0
VCCIB1
F15
GBC0/IO72RSB0
VMV1
F16
IO62RSB0
GBC2/IO38PDB2V0
F17
VMV0
IO37NDB2V0
F18
IO78NDB1
IO41NDB2V0
F19
IO81NDB1
IO41PDB2V0
F20
IO82PPB1
VCC
F21
NC
NC
F22
IO84NDB1
NC
G1
IO214NDB3
IO123NDB7V0
G2
IO214PDB3
IO123PDB7V0
G3
NC
NC
G4
IO222NDB3
IO124PDB7V0
G5
IO222PDB3
IO125PDB7V0
G6
GAC2/IO223PDB3
IO126PDB7V0
G7
IO223NDB3
IO130NDB7V1
G8
GNDQ
VCCIB7
G9
IO23RSB0
GND
G10
IO29RSB0
VCC
G11
IO33RSB0
VCC
G12
IO46RSB0
VCC
G13
IO52RSB0
VCC
G14
IO60RSB0
GND
G15
GNDQ
VCCIB2
G16
IO80NDB1
IO38NDB2V0
G17
GBB2/IO79PDB1
IO40NDB2V0
G18
IO79NDB1
IO40PDB2V0
CoreMP7 Development Kit User’s Guide
113
M7A3PE600 and M7A3P1000 FG484 Package Connections
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
114
Pin Number
M7A3P1000 Function
M7A3PE600 Function
G19
IO82NPB1
IO45PDB2V1
G20
IO85PDB1
NC
G21
IO85NDB1
IO48PDB2V1
G22
NC
IO46PDB2V1
H1
NC
IO121NDB7V0
H2
NC
IO121PDB7V0
H3
VCC
NC
H4
IO217PDB3
IO124NDB7V0
H5
IO218PDB3
IO125NDB7V0
H6
IO221NDB3
IO126NDB7V0
H7
IO221PDB3
GFC1/IO120PPB7V0
H8
VMV0
VCCIB7
H9
VCCIB0
VCC
H10
VCCIB0
GND
H11
IO38RSB0
GND
H12
IO47RSB0
GND
H13
VCCIB0
GND
H14
VCCIB0
VCC
H15
VMV1
VCCIB2
H16
GBC2/IO80PDB1
GCC1/IO50PPB2V1
H17
IO83PPB1
IO44NDB2V1
H18
IO86PPB1
IO44PDB2V1
H19
IO87PDB1
IO49NPB2V1
H20
VCC
IO45NDB2V1
H21
NC
IO48NDB2V1
H22
NC
IO46NDB2V1
J1
IO212NDB3
NC
J2
IO212PDB3
IO122PDB7V0
CoreMP7 Development Kit User’s Guide
484-Pin FGBGA Package
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
Pin Number
M7A3P1000 Function
M7A3PE600 Function
J3
NC
IO122NDB7V0
J4
IO217NDB3
GFB0/IO119NPB7V0
J5
IO218NDB3
GFA0/IO118NDB6V1
J6
IO216PDB3
GFB1/IO119PPB7V0
J7
IO216NDB3
VCOMPLF
J8
VCCIB3
GFC0/IO120NPB7V0
J9
GND
VCC
J10
VCC
GND
J11
VCC
GND
J12
VCC
GND
J13
VCC
GND
J14
GND
VCC
J15
VCCIB1
GCC0/IO50NPB2V1
J16
IO83NPB1
GCB1/IO51PPB2V1
J17
IO86NPB1
GCA0/IO52NPB3V0
J18
IO90PPB1
VCOMPLC
J19
IO87NDB1
GCB0/IO51NPB2V1
J20
NC
IO49PPB2V1
J21
IO89PDB1
IO47NDB2V1
J22
IO89NDB1
IO47PDB2V1
K1
IO211PDB3
NC
K2
IO211NDB3
IO114NDB6V1
K3
NC
IO117NDB6V1
K4
IO210PPB3
GFA2/IO117PDB6V1
K5
IO213NDB3
GFA1/IO118PDB6V1
K6
IO213PDB3
VCCPLF
K7
GFC1/IO209PPB3
IO116NDB6V1
K8
VCCIB3
GFB2/IO116PDB6V1
CoreMP7 Development Kit User’s Guide
115
M7A3PE600 and M7A3P1000 FG484 Package Connections
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
116
Pin Number
M7A3P1000 Function
M7A3PE600 Function
K9
VCC
VCC
K10
GND
GND
K11
GND
GND
K12
GND
GND
K13
GND
GND
K14
VCC
VCC
K15
VCCIB1
GCB2/IO54PPB3V0
K16
GCC1/IO91PPB1
GCA1/IO52PPB3V0
K17
IO90NPB1
GCC2/IO55PPB3V0
K18
IO88PDB1
VCCPLC
K19
IO88NDB1
GCA2/IO53PDB3V0
K20
IO94NPB1
IO53NDB3V0
K21
IO98NDB1
IO56PDB3V0
K22
IO98PDB1
NC
L1
NC
IO114PDB6V1
L2
IO200PDB3
IO111NDB6V1
L3
IO210NPB3
NC
L4
GFB0/IO208NPB3
GFC2/IO115PDB6V1
L5
GFA0/IO207NDB3
IO113PPB6V1
L6
GFB1/IO208PPB3
IO112PDB6V1
L7
VCOMPLF
IO112NDB6V1
L8
GFC0/IO209NPB3
VCCIB6
L9
VCC
VCC
L10
GND
GND
L11
GND
GND
L12
GND
GND
L13
GND
GND
L14
VCC
VCC
CoreMP7 Development Kit User’s Guide
484-Pin FGBGA Package
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
Pin Number
M7A3P1000 Function
M7A3PE600 Function
L15
GCC0/IO91NPB1
VCCIB3
L16
GCB1/IO92PPB1
IO54NPB3V0
L17
GCA0/IO93NPB1
IO57NPB3V0
L18
IO96NPB1
IO55NPB3V0
L19
GCB0/IO92NPB1
IO57PPB3V0
L20
IO97PDB1
NC
L21
IO97NDB1
IO56NDB3V0
L22
IO99NPB1
IO58PDB3V0
M1
NC
NC
M2
IO200NDB3
IO111PDB6V1
M3
IO206NDB3
IO115NDB6V1
M4
GFA2/IO206PDB3
IO113NPB6V1
M5
GFA1/IO207PDB3
IO109PPB6V0
M6
VCCPLF
IO108PDB6V0
M7
IO205NDB3
IO108NDB6V0
M8
GFB2/IO205PDB3
VCCIB6
M9
VCC
GND
M10
GND
VCC
M11
GND
VCC
M12
GND
VCC
M13
GND
VCC
M14
VCC
GND
M15
GCB2/IO95PPB1
VCCIB3
M16
GCA1/IO93PPB1
GDB0/IO66NPB3V1
M17
GCC2/IO96PPB1
IO60NDB3V1
M18
IO100PPB1
IO60PDB3V1
M19
GCA2/IO94PPB1
IO61PDB3V1
M20
IO101PPB1
NC
CoreMP7 Development Kit User’s Guide
117
M7A3PE600 and M7A3P1000 FG484 Package Connections
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
118
Pin Number
M7A3P1000 Function
M7A3PE600 Function
M21
IO99PPB1
IO59PDB3V0
M22
NC
IO58NDB3V0
N1
IO201NDB3
NC
N2
IO201PDB3
IO110PDB6V0
N3
NC
VCC
N4
GFC2/IO204PDB3
IO109NPB6V0
N5
IO204NDB3
IO106NDB6V0
N6
IO203NDB3
IO106PDB6V0
N7
IO203PDB3
GEC0/IO104NPB6V0
N8
VCCIB3
VMV5
N9
VCC
VCCIB5
N10
GND
VCCIB5
N11
GND
IO84NDB5V0
N12
GND
IO84PDB5V0
N13
GND
VCCIB4
N14
VCC
VCCIB4
N15
VCCIB1
VMV3
N16
IO95NPB1
VCCPLD
N17
IO100NPB1
GDB1/IO66PPB3V1
N18
IO102NDB1
GDC1/IO65PDB3V1
N19
IO102PDB1
IO61NDB3V1
N20
NC
VCC
N21
IO101NPB1
IO59NDB3V0
N22
IO103PDB1
IO62PDB3V1
P1
NC
NC
P2
IO199PDB3
IO110NDB6V0
P3
IO199NDB3
NC
P4
IO202NDB3
IO105PDB6V0
CoreMP7 Development Kit User’s Guide
484-Pin FGBGA Package
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
Pin Number
M7A3P1000 Function
M7A3PE600 Function
P5
IO202PDB3
IO105NDB6V0
P6
IO196PPB3
GEC1/IO104PPB6V0
P7
IO193PPB3
VCOMPLE
P8
VCCIB3
GNDQ
P9
GND
GEA2/IO101PPB5V2
P10
VCC
IO92NDB5V1
P11
VCC
IO90NDB5V1
P12
VCC
IO82NDB5V0
P13
VCC
IO74NDB4V1
P14
GND
IO74PDB4V1
P15
VCCIB1
GNDQ
P16
GDB0/IO112NPB1
VCOMPLD
P17
IO106NDB1
VJTAG
P18
IO106PDB1
GDC0/IO65NDB3V1
P19
IO107PDB1
GDA1/IO67PDB3V1
P20
NC
NC
P21
IO104PDB1
IO64PDB3V1
P22
IO103NDB1
IO62NDB3V1
R1
NC
NC
R2
IO197PPB3
IO107PDB6V0
R3
VCC
IO107NDB6V0
R4
IO197NPB3
GEB1/IO103PDB6V0
R5
IO196NPB3
GEB0/IO103NDB6V0
R6
IO193NPB3
VMV6
R7
GEC0/IO190NPB3
VCCPLE
R8
VMV3
IO101NPB5V2
R9
VCCIB2
IO95PPB5V1
R10
VCCIB2
IO92PDB5V1
CoreMP7 Development Kit User’s Guide
119
M7A3PE600 and M7A3P1000 FG484 Package Connections
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
120
Pin Number
M7A3P1000 Function
M7A3PE600 Function
R11
IO147RSB2
IO90PDB5V1
R12
IO136RSB2
IO82PDB5V0
R13
VCCIB2
IO76NDB4V1
R14
VCCIB2
IO76PDB4V1
R15
VMV2
VMV4
R16
IO110NDB1
TCK
R17
GDB1/IO112PPB1
VPUMP
R18
GDC1/IO111PDB1
TRST
R19
IO107NDB1
GDA0/IO67NDB3V1
R20
VCC
NC
R21
IO104NDB1
IO64NDB3V1
R22
IO105PDB1
IO63PDB3V1
T1
IO198PDB3
NC
T2
IO198NDB3
NC
T3
NC
GND
T4
IO194PPB3
GEA1/IO102PDB6V0
T5
IO192PPB3
GEA0/IO102NDB6V0
T6
GEC1/IO190PPB3
GNDQ
T7
IO192NPB3
GEC2/IO99PDB5V2
T8
GNDQ
IO95NPB5V1
T9
GEA2/IO187RSB2
IO91NDB5V1
T10
IO161RSB2
IO91PDB5V1
T11
IO155RSB2
IO83NDB5V0
T12
IO141RSB2
IO83PDB5V0
T13
IO129RSB2
IO77NDB4V1
T14
IO124RSB2
IO77PDB4V1
T15
GNDQ
IO69NDB4V0
T16
IO110PDB1
GDB2/IO69PDB4V0
CoreMP7 Development Kit User’s Guide
484-Pin FGBGA Package
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
Pin Number
M7A3P1000 Function
M7A3PE600 Function
T17
VJTAG
TDI
T18
GDC0/IO111NDB1
GNDQ
T19
GDA1/IO113PDB1
TDO
T20
NC
GND
T21
IO108PDB1
NC
T22
IO105NDB1
IO63NDB3V1
U1
IO195PDB3
NC
U2
IO195NDB3
NC
U3
IO194NPB3
NC
U4
GEB1/IO189PDB3
GND
U5
GEB0/IO189NDB3
IO100NDB5V2
U6
VMV2
GEB2/IO100PDB5V2
U7
IO179RSB2
IO99NDB5V2
U8
IO171RSB2
IO88NDB5V0
U9
IO165RSB2
IO88PDB5V0
U10
IO159RSB2
IO89NDB5V0
U11
IO151RSB2
IO80NDB4V1
U12
IO137RSB2
IO81NDB4V1
U13
IO134RSB2
IO81PDB4V1
U14
IO128RSB2
IO70NDB4V0
U15
VMV1
GDC2/IO70PDB4V0
U16
TCK
IO68NDB4V0
U17
VPUMP
GDA2/IO68PDB4V0
U18
TRST
TMS
U19
GDA0/IO113NDB1
GND
U20
NC
NC
U21
IO108NDB1
NC
U22
IO109PDB1
NC
CoreMP7 Development Kit User’s Guide
121
M7A3PE600 and M7A3P1000 FG484 Package Connections
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
122
Pin Number
M7A3P1000 Function
M7A3PE600 Function
V1
NC
VCCIB6
V2
NC
NC
V3
GND
NC
V4
GEA1/IO188PDB3
IO98NDB5V2
V5
GEA0/IO188NDB3
GND
V6
IO184RSB2
IO94NDB5V1
V7
GEC2/IO185RSB2
IO94PDB5V1
V8
IO168RSB2
VCC
V9
IO163RSB2
VCC
V10
IO157RSB2
IO89PDB5V0
V11
IO149RSB2
IO80PDB4V1
V12
IO143RSB2
IO78NPB4V1
V13
IO138RSB2
NC
V14
IO131RSB2
VCC
V15
IO125RSB2
VCC
V16
GDB2/IO115RSB2
NC
V17
TDI
NC
V18
GNDQ
GND
V19
TDO
NC
V20
GND
NC
V21
NC
NC
V22
IO109NDB1
VCCIB3
W1
NC
GND
W2
IO191PDB3
VCCIB6
W3
NC
NC
W4
GND
IO98PDB5V2
W5
IO183RSB2
IO96NDB5V2
W6
GEB2/IO186RSB2
IO96PDB5V2
CoreMP7 Development Kit User’s Guide
484-Pin FGBGA Package
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
Pin Number
M7A3P1000 Function
M7A3PE600 Function
W7
IO172RSB2
IO86NDB5V0
W8
IO170RSB2
IO86PDB5V0
W9
IO164RSB2
IO85PDB5V0
W10
IO158RSB2
IO85NDB5V0
W11
IO153RSB2
IO78PPB4V1
W12
IO142RSB2
IO79NDB4V1
W13
IO135RSB2
IO79PDB4V1
W14
IO130RSB2
NC
W15
GDC2/IO116RSB2
NC
W16
IO120RSB2
IO71NDB4V0
W17
GDA2/IO114RSB2
IO71PDB4V0
W18
TMS
NC
W19
GND
NC
W20
NC
NC
W21
NC
VCCIB3
W22
NC
GND
Y1
VCCIB3
GND
Y2
IO191NDB3
GND
Y3
NC
VCCIB5
Y4
IO182RSB2
IO97NDB5V2
Y5
GND
IO97PDB5V2
Y6
IO177RSB2
IO93NDB5V1
Y7
IO174RSB2
IO93PDB5V1
Y8
VCC
IO87NDB5V0
Y9
VCC
IO87PDB5V0
Y10
IO154RSB2
NC
Y11
IO148RSB2
NC
Y12
IO140RSB2
IO75NDB4V1
CoreMP7 Development Kit User’s Guide
123
M7A3PE600 and M7A3P1000 FG484 Package Connections
Table A-1. M7A3PE600 and M7A3P1000 FG484 Package Connections (Continued)
124
Pin Number
M7A3P1000 Function
M7A3PE600 Function
Y13
NC
IO75PDB4V1
Y14
VCC
IO72NDB4V0
Y15
VCC
IO72PDB4V0
Y16
NC
IO73NDB4V0
Y17
NC
IO73PDB4V0
Y18
GND
NC
Y19
NC
NC
Y20
NC
VCCIB4
Y21
NC
GND
Y22
VCCIB1
GND
CoreMP7 Development Kit User’s Guide
B
Board Schematics
This appendix provides illustrations of the CoreMP7 Evaluation Board.
Top-Level View
Figure B-1 on page 126 illustrates a top-level view of the CoreMP7 Evaluation Board. Figure B-2
on page 127 shows a bottom-level view of CoreMP7 Evaluation Board.
CoreMP7 Schematics
The rest of this appendix shows the following illustrations of the CoreMP7 Evaluation Board:
Figure B-3 on page 128: Main 1.5 V, 2.5 V, and 3.3 V Power Supplies
Figure B-4 on page 129: Flash and Synchronous SRAM Memories
Figure B-5 on page 130: M7A3PE600 FPGA – I/O Banks 0–2
Figure B-6 on page 131: M7A3PE600 FPGA – I/O Banks 3–5
Figure B-7 on page 132: M7A3PE600 FPGA – I/O Banks 6–7
Figure B-8 on page 133: LEDs and Push-Button Switches
Figure B-9 on page 134: FPGA I/O Expansion Headers
Figure B-10 on page 135: USB Interface
Figure B-11 on page 136: RS-232 and CAN Interfaces
Figure B-12 on page 137: Ethernet 0 Interface
Figure B-13 on page 138: Ethernet 1 Interface
CoreMP7 Development Kit User’s Guide
125
Figure B-1. Top-Level View of CoreMP7 Development Board
126
CoreMP7 Development Kit User’s Guide
Figure B-2. Bottom-Level View of CoreMP7 Development Board
CoreMP7 Development Kit User’s Guide
127
Figure B-3. Main 1.5 V, 2.5 V, and 3.3 V Power Supplies
A
B
C
D
3.3V
3.3V
0.1uF
C20
2.5V
C19
47UF/16V
2.5V
R9
4.99K
47UF/16V
C13
+
+
0.1uF
C21
0.1uF
DECOUPLING CAPACITORS
0.22UF/25V
C18
R4
4.99K
1
5
C22
1.5V
D17
1
TRANZORB
1
2
1
2
+ C2
10UF/35V
U2
NC
IN3
IN4
EN
SENSE
C23
0.1uF
2
3
4
5
7
NC
IN3
IN4
EN
SENSE
U4
19
18
16
15
14
13
12
9
8
6
1.5V
+ C3
10UF/35V
2.5V
TPS75225_QPWP
NC7
NC6
NC5
NC4
NC3
NC2
NC1
O/P9
O/P8
RESET
19
18
16
15
14
13
12
9
8
6
TPS75215_QPWP
NC7
NC6
NC5
NC4
NC3
NC2
NC1
O/P9
O/P8
RESET
2.5V Linear regulator with reset
2
3
4
5
7
1.5V Linear regulator with reset
+ C1
10UF/35V
1
2
JP1
2
1.5V
RESET25N
0.22UF/25V
C11
RESET15N
CONN_KLD_SMT
3
2
1
@
@
1
2A (Max)
4
TP1
+ C5
0.22UF/50V
5V_ON_OFF
+ C4
10UF/35V
2A (Max)
2
TO MEASURE CURRENT
1
2
J1
U1
4
6
3
1
5V
5
1
6
3
C16
0.01UF/16V
2
1
3
22UH
L1
C12
0.01UF/50V
3
C9
0.01UF/50V
C10
10UF/16V
4
3
2
1
GND
VIN
VSW
LM2674M-5.0
FB ON/OFF
NC2
NC1
CB
U3
5
6
7
8
5V Switching regulator / 5A
2
D6
CMSH5-40
D1
CMSH5-40
1
C6
0.01UF/50V
C17
100UF/10V
100uH
L2
5V@ 500mA (Max)
LM2678S-3.3
NC
GND VSW
VIN
FB
ON/OFF CB
GPI-152-3013
5
2
SW1
4
2
7
1
2
3.3V Switching regulator / 5A
1
2
4
1
2
VIN
1
2
9 VOLT
5
VIN
C15
100UF/16V
+ C8
100UF/10V
3.3V@ 5A (Max)
2
GREEN LED
D5
5V Pwr LED
R5
475E
5V
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
3.3V
Title:
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Approvals:
1
R10
2K
VIN
R8
2K
2
1.5V
VIN Pwr LED
D4
RED LED
R3
1K
1
Sanmina-SCI
POWER SUPPLY
CoreARM7 DEV KIT BOARD
Document No:
1
2061 Stierlin Ct
Mountain View, CA 94043
Actel Corp
1
GREEN LED
D3
R2
78.7
D7
GREEN LED
R6
274
3.3V
1.5V Pwr LED
MMBT2222
2.5V
2.5V Pwr LED
Q1
GREEN LED
D2
R1
200
3.3V Pwr LED
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
5V_ON_OFF
C14
0.22UF/50V
+ C7
100UF/10V
3.3V
1
2
2
GND
GND1
GND2
GND3
GND4
21
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
2
1
1
2
2
1
9V input power DC jack
1
2
1
2
1
2
2
1
1
2
2
1
3
2
1
10
11
17
20
21
GND
GND1
GND2
GND3
GND4
21
1
10
11
17
20
21
1
2
128
CoreMP7 Development Kit User’s Guide
Rev
2 of 12
1.7
Pg
A
B
C
D
Figure B-4. Flash and Synchronous SRAM Memories
A
3.3V
1
2
B
0.1uF
C24
1
2
0.1uF
C25
0.1uF
C26
5
0.1uF
C27
DECOUPLING CAPACITORS
MEM_ADDR[18:0]
1
2
C
1
2
D
1
2
MEM_ADDR[18:0]
0.1uF
C28
0.1uF
C29
3.3V
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
MEM_ADDR4
MEM_ADDR5
MEM_ADDR6
MEM_ADDR7
MEM_ADDR8
MEM_ADDR9
MEM_ADDR10
MEM_ADDR11
MEM_ADDR12
MEM_ADDR13
MEM_ADDR14
MEM_ADDR15
MEM_ADDR16
MEM_ADDR17
MEM_ADDR18
3.3V
37
9
10
13
14
46
27
12
15
26
47
28
11
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
MEM_DATA0
MEM_DATA1
MEM_DATA2
MEM_DATA3
MEM_DATA4
MEM_DATA5
MEM_DATA6
MEM_DATA7
MEM_DATA8
MEM_DATA9
MEM_DATA10
MEM_DATA11
MEM_DATA12
MEM_DATA13
MEM_DATA14
MEM_DATA15
VSS
VSS1
RP
RB
E
BYTE
G
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15A-1
M29W800DT
VCC
NC1
NC2
NC3
NC4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
U7
4
+ C154
10UF/10V
3.3V
FLASH_RPN
FLASH_CSN
FLASH_BYTEN
FLASH_READN
FLASH_WRITEN
0.1uF
C155
0.1uF
C146
FLASH_RPN
FLASH_RB
0.1uF
0.1uF
C156
3.3V
MEM_DATA[31:0]
10K
R122
MEM_DATA[31:0]
0.1uF
C157
0.1uF
C148
0.1uF
C158
0.1uF
C149
DECOUPLING CAPACITORS
C147
FLASH_CSN
FLASH_BYTEN
FLASH_READN
FLASH_WRITEN
MEM_DATA16
MEM_DATA17
MEM_DATA18
MEM_DATA19
MEM_DATA20
MEM_DATA21
MEM_DATA22
MEM_DATA23
MEM_DATA24
MEM_DATA25
MEM_DATA26
MEM_DATA27
MEM_DATA28
MEM_DATA29
MEM_DATA30
MEM_DATA31
+ C145
10UF/10V
3.3V
46
27
12
15
26
47
28
11
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
FLASH 512K * 16
VSS
VSS1
RP
RB
E
BYTE
G
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15A-1
M29W800DT
VCC
NC1
NC2
NC3
NC4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
U5
FLASH 512K * 16
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
37
9
10
13
14
MEM_ADDR0 25
MEM_ADDR1 24
MEM_ADDR2 23
MEM_ADDR3 22
MEM_ADDR4 21
MEM_ADDR5 20
MEM_ADDR6 19
MEM_ADDR7 18
MEM_ADDR8 8
MEM_ADDR9 7
MEM_ADDR10 6
MEM_ADDR11 5
MEM_ADDR12 4
MEM_ADDR13 3
MEM_ADDR14 2
MEM_ADDR15 1
MEM_ADDR16 48
MEM_ADDR17 17
MEM_ADDR18 16
1
2
1
2
1
2
1
2
1
4
1
2
1
2
1
2
1
2
1
2
0.1uF
C159
0.1uF
C150
3
3
0.1uF
C160
0.1uF
C151
SSRAM_CLK
SSRAM_BWRITEN
SSRAM_B0N
SSRAM_B1N
SSRAM_PWRDWN
SSRAM_GWRITEN
0.1uF
C161
0.1uF
0.1uF
C162
0.1uF
C153
SSRAM_BWRITEN
SSRAM_B2N
SSRAM_B3N
SSRAM_PWRDWN
SSRAM_GWRITEN
SSRAM_CLK
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
MEM_ADDR4
MEM_ADDR5
MEM_ADDR6
MEM_ADDR7
MEM_ADDR8
MEM_ADDR9
MEM_ADDR10
MEM_ADDR11
MEM_ADDR12
MEM_ADDR13
MEM_ADDR14
MEM_ADDR15
MEM_ADDR16
MEM_ADDR17
MEM_ADDR18
SSRAM 512K * 16
C152
U6
BW
BA
BB
ZZ
GW
CK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
GS88018
87
93
94
64
88
89
37
36
35
34
33
32
100
99
82
81
80
44
45
46
47
48
49
50
43
U8
GS88018
87
93
94
64
88
89
MEM_ADDR0
37
MEM_ADDR1
36
MEM_ADDR2
35
MEM_ADDR3
34
MEM_ADDR4
33
MEM_ADDR5
32
MEM_ADDR6 100
MEM_ADDR7
99
MEM_ADDR8
82
MEM_ADDR9
81
MEM_ADDR10 80
MEM_ADDR11 44
MEM_ADDR12 45
MEM_ADDR13 46
MEM_ADDR14 47
MEM_ADDR15 48
MEM_ADDR16 49
MEM_ADDR17 50
MEM_ADDR18 43
SSRAM 512K * 16
MEM_ADDR[18:0]
MEM_ADDR[18:0]
FLASH_RB
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
3.3V
4
11
20
27
54
61
70
77
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
3.3V
4
11
20
27
54
61
70
77
BW
BA
BB
ZZ
GW
CK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
2
42
51
52
53
56
57
66
75
78
79
95
96
LBO
FT
G
ADSP
ADSC
ADV
LBO
FT
G
ADSP
ADSC
ADV
PCB FAB:,REV.0X
2
E2
E1
E3
DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQPA
DQPB
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
E2
E1
E3
DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQPA
DQPB
SSRAM_CSN
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Title:
2061 Stierlin Ct
Mountain View, CA 94043
10K
R115
10K
R120
SSRAM_FT 2
10K
R119
3.3V
10K
R121
JP48
MEM_DATA[31:0]
1
Sanmina-SCI
MEMORY
1
10K
R116
JP47
SSRAM_LBO
10K
R117
10K
R114
3.3V
MEM_DATA[31:0]
CoreARM7 DEV KIT BOARD
Document No:
SSRAM_LBO
SSRAM_FT
SSRAM_READN
SSRAM_ADSP
SSRAM_ADSC
SSRAM_ADV
SSRAM_CSN
10K
R118
SSRAM_LBO
SSRAM_FT
MEM_DATA16
MEM_DATA17
MEM_DATA18
MEM_DATA19
MEM_DATA20
MEM_DATA21
MEM_DATA22
MEM_DATA23
MEM_DATA24
MEM_DATA25
MEM_DATA26
MEM_DATA27
MEM_DATA28
MEM_DATA29
MEM_DATA30
MEM_DATA31
Approvals:
10K
R113
SSRAM_READN
SSRAM_ADSP
SSRAM_ADSC
SSRAM_ADV
MEM_DATA0
MEM_DATA1
MEM_DATA2
MEM_DATA3
MEM_DATA4
MEM_DATA5
MEM_DATA6
MEM_DATA7
MEM_DATA8
MEM_DATA9
MEM_DATA10
MEM_DATA11
MEM_DATA12
MEM_DATA13
MEM_DATA14
MEM_DATA15
Actel Corp
31
14
86
84
85
83
97
98
92
58
59
62
63
68
69
72
73
8
9
12
13
18
19
22
23
74
24
31
14
86
84
85
83
97
98
92
58
59
62
63
68
69
72
73
8
9
12
13
18
19
22
23
74
24
1
3
5
1
15
41
65
91
VDD1
VDD2
VDD3
VDD4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
5
10
17
21
26
40
55
60
67
71
76
90
15
41
65
91
VDD1
VDD2
VDD3
VDD4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
5
10
17
21
26
40
55
60
67
71
76
90
2
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
1
2
3
6
7
16
25
28
29
30
38
39
42
51
52
53
56
57
66
75
78
79
95
96
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
1
2
3
6
7
16
25
28
29
30
38
39
CoreMP7 Development Kit User’s Guide
129
Rev
3 of 12
1.7
Pg
A
B
C
D
Figure B-5. M7A3PE600 FPGA – I/O Banks 0–2
A
B
C
1.5V
0.1uF
C43
VCC_IB1
0.1uF
C39
VCC_IB2
0.1uF
C36
0.1uF
C30
VCC_IB0
VCC_IB0
1.5V
5
TX0
TX1
MEM_DATA0
MEM_DATA1
MEM_DATA2
MEM_DATA3
MEM_DATA4
MEM_DATA5
MEM_DATA6
MEM_DATA7
MEM_DATA8
MEM_DATA9
MEM_DATA10
MEM_DATA11
MEM_DATA12
MEM_DATA13
MEM_DATA14
MEM_DATA15
MEM_DATA16
MEM_DATA17
MEM_DATA18
MEM_DATA19
MEM_DATA20
MEM_DATA21
MEM_DATA22
MEM_DATA23
MEM_DATA24
MEM_DATA25
MEM_DATA26
MEM_DATA27
MEM_DATA28
MEM_DATA29
MEM_DATA30
MEM_DATA31
0.1uF
C44
0.1uF
C40
0.1uF
C37
0.1uF
C31
5
0.1uF
C45
0.1uF
C41
0.1uF
C38
0.1uF
C32
0.1uF
C42
FPGA DECOUPLING CAPACITORS
B0 I/O0
B0 I/O1
B0 I/O2
B0 I/O3
B0 I/O4
B0 I/O5
MEM_DATA[31:0]
B0 I/O[0..5]
1
2
1
2
1
2
1
2
1
2
1
2
D
1
2
1
2
1
2
1
2
1
2
1
2
1
2
B5
B4
C7
C6
D8
E8
A5
A4
B7
B6
A7
A6
G10
G9
D9
E9
A8
B8
D10
E10
G11
H11
B10
C10
F11
F10
E11
D11
A9
B9
A11
A10
B11
C11
D5
D7
F8
E7
F9
D6
A3
H9
H10
C8
A1
FPGA BANK B0
A3PE600
4
1
NC
U10
1.5V
VCC_IB1
B1 I/O[0..5]
OUT
4
3
B1 I/O0
B1 I/O1
B1 I/O2
B1 I/O3
B1 I/O4
B1 I/O5
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
MEM_ADDR4
MEM_ADDR5
MEM_ADDR6
MEM_ADDR7
MEM_ADDR8
MEM_ADDR9
MEM_ADDR10
MEM_ADDR11
MEM_ADDR12
MEM_ADDR13
MEM_ADDR14
MEM_ADDR15
MEM_ADDR16
MEM_ADDR17
MEM_ADDR18
R14
1K
R11
1K
3.3V
2
JP49
1
3
FLASH_RPN
FLASH_BYTEN
FLASH_CSN
FLASH_WRITEN
FLASH_READN
FLASH_RB
SSRAM_PWRDWN
MEM_ADDR[18:0]
MEMORY INTERFACE
50MHZ OSCILLATOR
C33
0.1UF/50V
IO03PDB0V0
IO03NDB0V0
IO04PDB0V0
IO04NDB0V0
IO05PDB0V0
IO05NDB0V0
IO06PDB0V1
IO06NDB0V1
IO07PDB0V1
IO07NDB0V1
IO08PDB0V1
IO08NDB0V1
IO09PDB0V1
IO09NDB0V1
IO10PDB0V1
IO10NDB0V1
IO11PDB0V1
IO11NDB0V1
IO12PDB0V2
IO12NDB0V2
IO13PDB0V2
IO13NDB0V2
IO14PDB0V2
IO14NDB0V2
IO15PDB0V2
IO15NDB0V2
IO16PDB0V2
IO16NDB0V2
IO17PDB0V2
IO17NDB0V2
IO18PDB0V2
IO18NDB0V2
IO19PDB0V2
IO19NDB0V2
GAA0/IO00NDB0V0
GAB0/IO01NDB0V0
GAC0/IO02NDB0V0
GAB1/IO01PDB0V0
GAC1/IO02PDB0V0
GAA1/IO00PDB0V0
VCCIB0
VCCIB0_1
VCCIB0_2
VCC0
GND0
U9A
1
2
4
VCC
GND
2
1
2
1
2
B2 I/O[0..6]
F18
H17
J16
G18
G19
J18
J17
H19
H18
F19
E19
G20
G21
K18
K17
J19
K20
J22
K22
L22
L21
J21
K21
L20
K19
E18
G17
H16
L19
L16
L15
K16
B21
C22
J15
K15
H20
B22
A3PE600
CLOCKA_G
1
NC
3
32KHz OSCILLATOR
C34
0.1UF/50V
VCC_IB2
U11
1.5V
OUT
3
R15
1K
R12
1K
3.3V
CLOCKF
VCC_IB2
VCC_IB1
VCC_IB0
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
A3PE600
IO36NDB2V0
IO37NDB2V0
IO38NDB2V0
IO39PDB2V0
IO39NDB2V0
IO40PDB2V0
IO40NDB2V0
IO41PDB2V0
IO41NDB2V0
IO42PDB2V0
IO42NDB2V0
IO43PDB2V0
IO43NDB2V0
IO44PDB2V1
IO44NDB2V1
IO45PDB2V1
IO45NDB2V1
IO46PDB2V1
IO46NDB2V1
IO47PDB2V1
IO47NDB2V1
IO48PDB2V1
IO48NDB2V1
IO49PPB2V1
IO49NPB2V1
GBA2/IO36PDB2V0
GBB2/IO37PDB2V0
GBC2/IO38PDB2V0
GCB0/IO51NPB2V1
GCB1/IO51PPB2V1
GCC0/IO50NPB2V1
GCC1/IO50PPB2V1
VCCIB2
VCCIB2_1
VCCIB2_2
VCCIB2_3
VCC2
GND2
FPGA BANK B2
IO20PDB1V0
IO20NDB1V0
IO21PDB1V0
IO21NDB1V0
IO22PDB1V0
IO22NDB1V0
IO23PDB1V0
IO23NDB1V0
IO24PDB1V0
IO24NDB1V0
IO25PDB1V0
IO25NDB1V0
IO26PDB1V0
IO26NDB1V0
IO27PDB1V0
IO27NDB1V0
IO28PDB1V1
IO28NDB1V1
IO29PDB1V1
IO29NDB1V1
IO30PDB1V1
IO30NDB1V1
IO31PDB1V1
IO31NDB1V1
IO32PDB1V1
IO32NDB1V1
GBA0/IO35NDB1V1
GBA1/IO35PDB1V1
GBB0/IO34PDB1V1
GBB0/IO34NDB1V1
GBC0/IO33NDB1V1
GBC1/IO33PDB1V1
VCCIB1
VCCIB1_1
VCCIB1_2
VCC1
GND1
U9C
SSRAM_CLK
SSRAM_CSN
SSRAM_GWRITEN
SSRAM_READN
SSRAM_BWRITEN
SSRAM_B0N
SSRAM_B1N
SSRAM_B2N
SSRAM_B3N
SSRAM_ADSP
SSRAM_ADSC
SSRAM_ADV
RX0
RX1
RTS
CTS
CAN_TXD
CAN_RXD
USB_MODE
USB_OEN
USB_RCV
USB_VP
USB_VM
USB_SUSPND
USB_VMO/SEO
B2 I/O0
B2 I/O1
B2 I/O2
B2 I/O3
B2 I/O4
B2 I/O5
B2 I/O6
MISC INTERFACE
2
FPGA BANK B1
CLOCKA_GPIO
F12
E12
G12
H12
A12
B12
D13
D12
E14
E13
G13
F13
A13
B13
F14
G14
D15
D14
A15
A14
B17
B16
A17
A16
B18
A18
D17
D18
D16
E16
F15
E15
A20
H13
H14
C9
A21
3
U9B
1
2
4
VCC
GND
2
1
2
1
2
130
CoreMP7 Development Kit User’s Guide
Title:
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Approvals:
2061 Stierlin Ct
Mountain View, CA 94043
Actel Corp
3.3V
3.3V
3.3V
Document No:
1
Sanmina-SCI
FPGA_012
CoreARM7 DEV KIT BOARD
1
Rev
4 of 12
1.7
Pg
A
B
C
D
Figure B-6. M7A3PE600 FPGA – I/O Banks 3–5
A
B
C
D
1.5V
B3 I/O[0..11]
TP8
5
TP4
0.1uF
C46
0.1uF
C47
VCC_IB3
5
0.1uF
C48
0.1uF
C49
VCC_IB3
1.5V
B3 I/O0
B3 I/O1
B3 I/O2
B3 I/O3
B3 I/O4
B3 I/O5
B3 I/O6
B3 I/O7
B3 I/O8
B3 I/O9
B3 I/O10
B3 I/O11
0.1uF
C50
M20
N16
N18
M21
N21
N19
N17
N22
P22
P21
R21
P18
P17
P19
R19
R22
T22
U22
V22
T21
U21
R18
T18
R17
P16
T19
U19
M16
L17
M19
M15
M17
N15
P15
Y22
AA21
N14
N13
0.1uF
C51
0.1uF
C52
DECOUPLING CAPACITORS
USB_VPO
USB_SPEED
SW_EN
SW_FLG
RVI-ME_VTref
RVI-ME_nTRST
RVI-ME_TDI
RVI-ME_TMS
RVI-ME_TCK
RVI-ME_RTCK
RVI-ME_TDO
RVI-ME_nSRST
RVI-ME_DBGRQ
RVI-ME_DBGACK
T POINT B0
TP5
T POINT B0
TP6
T POINT B0
TP7
T POINT B0
T POINT B0
TP9
T POINT B0
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4
FPGA BANK B3
4
0.1uF
C53
VCC_IB4
A3PE600
0.1uF
C54
IO53NDB3V0
IO54NPB3V0
IO55NPB3V0
IO56PDB3V0
IO56NDB3V0
IO57PPB3V0
IO57NPB3V0
IO58PDB3V0
IO58NDB3V0
IO59PDB3V0
IO59NDB3V0
IO60PDB3V1
IO60NDB3V1
IO61PDB3V1
IO61NDB3V1
IO62PDB3V1
IO62NDB3V1
IO63PDB3V1
IO63NDB3V1
IO64PDB3V1
IO64NDB3V1
GDC1/IO65PDB3V1
GDC0/IO65NDB3V1
GDB1/IO66PPB3V1
GDB0/IO66NPB3V1
GDA1/IO67PDB3V1
GDA0/IO67NDB3V1
GCA1/IO52PPB3V0
GCA0/IO52NPB3V0
GCA2/IO53PDB3V0
GCB2/IO54PPB3V0
GCC2/IO55PPB3V0
VCCIB3
VCCIB3_1
VCCIB3_2
VCCIB3_3
VCC3
GND
U9D
1
2
1
2
0.1uF
C55
1.5V
B4 I/O0
B4 I/O1
B4 I/O2
B4 I/O3
B4 I/O4
B4 I/O5
B4 I/O6
B4 I/O7
B4 I/O8
B4 I/O9
B4 I/O10
B4 I/O11
B4 I/O12
B4 I/O13
B4 I/O14
B4 I/O15
B4 I/O16
B4 I/O17
B4 I/O18
B4 I/O19
B4 I/O20
B4 I/O21
B4 I/O22
B4 I/O23
3.3V
0.1uF
C57
CLOCKA_GPIO
CLOCKA_G
CLOCKF
RESET#
0.1uF
C56
B4 I/O[0..23]
VCC_IB4
1
2
1
2
1
2
1
2
0.1uF
C58
FPGA BANK B4
IO68NDB4V0
IO69NDB4V0
IO70NDB4V0
IO71PDB4V0
IO71NDB4V0
IO72PDB4V0
IO72NDB4V0
IO73PDB4V0
IO73NDB4V0
IO74PDB4V1
IO74NDB4V1
IO75PDB4V1
IO75NDB4V1
IO76PDB4V1
IO76NDB4V1
IO77PDB4V1
IO77NDB4V1
IO78PPB4V1
IO78NDB4V1
IO79PDB4V1
IO79NDB4V1
IO80PDB4V1
IO80NDB4V1
IO81PDB4V1
IO81NDB4V1
GDA2/IO68PDB4V0
GDB2/IO69PDB4V0
GDC2/IO70PDB4V0
VCCIB4
VCCIB4_1
VCCIB4_2
VCC4
GND4
U9E
3
3
0.1uF
C59
A3PE600
W16
V15
W14
AA17
AA16
AB15
AB14
AB17
AB16
T14
T13
AB13
AB12
U14
U13
V14
V13
AA11
Y12
AA13
AA12
Y11
W11
W13
W12
W17
V16
W15
R13
R14
AB20
R20
AB21
1
2
CoreMP7 Development Kit User’s Guide
131
1.5V
R93 0E 1
R94 0E 1
R95 0E 1
VCC_IB4
2
2
2
FPGA_MDIO
FPGA_MDC
FPGA_1TXD0
FPGA_1TXD1
FPGA_1TXD2
FPGA_1TXD3
FPGA_1TX_EN
FPGA_1TX_ER
FPGA_EXT_IN_CLK_2
FPGA_1RXD0
FPGA_1RXD1
FPGA_1RXD2
FPGA_1RXD3
FPGA_1RX_DV
FPGA_1RX_ER
FPGA_EXT_IN_CLK_3
FPGA_1COL
FPGA_1CRS
FPGA_0TXD0
FPGA_0TXD1
FPGA_0TXD2
FPGA_0TXD3
FPGA_0TX_EN
FPGA_0TX_ER
FPGA_EXT_IN_CLK_0
FPGA_0RXD0
FPGA_0RXD1
FPGA_0RXD2
FPGA_0RXD3
FPGA_0RX_DV
FPGA_0RX_ER
FPGA_EXT_IN_CLK_1
FPGA_0COL
FPGA_0CRS
B5 I/O0
B5 I/O1
B5 I/O2
B5 I/O3
B5 I/O4
B5 I/O5
U12
T12
V12
V11
R12
R11
AA9
AA10
AA8
AA7
AB9
AB8
W9
W8
Y10
W10
U11
T11
V10
V9
U10
T10
AB7
AB6
Y7
Y6
U9
V8
AA6
AA5
AB5
AB4
AA4
Y4
W7
W5
U8
T9
W6
V7
R9
R10
AB3
Y8
Y5
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
VCC_IB5
B5 I/O[0..5]
2
FPGA BANK B5
ETHERNET
Title:
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Approvals:
2061 Stierlin Ct
Mountain View, CA 94043
Actel Corp
A3PE600
IO82PDB5V0
IO82NDB5V0
IO83PDB5V0
IO83NDB5V0
IO84PDB5V0
IO84NDB5V0
IO85PDB5V0
IO85NDB5V0
IO86PDB5V0
IO86NDB5V0
IO87PDB5V0
IO87NDB5V0
IO88PDB5V0
IO88NDB5V0
IO89PDB5V0
IO89NDB5V0
IO90PDB5V1
IO90NDB5V1
IO91PDB5V1
IO91NDB5V1
IO92PDB5V1
IO92NDB5V1
IO93PDB5V1
IO93NDB5V1
IO94PDB5V1
IO94NDB5V1
IO95PPB5V1
IO95NPB5V1
IO96PDB5V2
IO96NDB5V2
IO97PDB5V2
IO97NDB5V2
IO98PDB5V2
IO98NDB5V2
IO99NDB5V2
IO100NDB5V2
IO101NPB5V2
GEA2/IO101PPB5V2
GEB2/IO100PDB5V2
GEC2/IO99PDB5V2
VCCIB5
VCCIB5_1
VCCIB5_2
VCC5
GND5
U9F
VCC_IB5
5
4
3
2
1
1.5V
1.5V
2.5V
2.5V
Document No:
1
Sanmina-SCI
FPGA_345
CoreARM7 DEV KIT BOARD
CON5
5
4
3
2
1
J7
VCC_IB4
5
4
3
2
1
CON5
5
4
3
2
1
J6
VCC_IB3
1
Pg
5 of 12
1.7
Rev
3.3V
3.3V
3.3V
A
B
C
D
Figure B-7. M7A3PE600 FPGA – I/O Banks 6–7
A
B
C
D
1.5V
3
1
3
1
3
1
3
1
3
1
3
1
1
1
R103
2
2
JP45
2
JP44
2
JP43
2
JP42
2
JP41
JP40
2
0E
0E
0E
0E
0E
0E
R105
R104
R106
R107
R108
R109
R110
1
1
5
1.5V
TRST
VCC_IB5
VCC_IB3
0E
2
VCC_IB1
2
0E
2
VCC_IB0
JP39
R101
R102
VCC_IB7
1
VCC_IB6
VCC_IB4
VCC_IB2
1
1
1
1
1
1
0E
2
0E
2
2
2
2
2
2
A2
A22
B1
C5
C18
D4
D19
E3
E20
J9
J14
K11
K12
K13
L10
L11
L12
L13
M11
M12
M13
N10
N11
N12
P9
P14
V3
F7
U7
M6
F16
M18
R16
G7
G16
L18
T16
T7
L7
E6
G8
E17
G15
V18
V6
T8
T15
L14
L9
C14
C15
H3
J10
J11
J12
J13
K14
M14
N9
P10
P11
P12
P13
R3
Y9
Y14
Y15
H8
F17
H15
U15
R15
U6
R8
F6
A3PE600
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
VCCPLA
VCCPLE
VCCPLF
VCCPLB
VCCPLC
VCCPLD
VCOMPLA
VCOMPLB
VCOMPLC
VCOMPLD
VCOMPLE
VCOMPLF
GNDQ_1
GNDQ_2
GNDQ_3
GNDQ_4
GNDQ_5
GNDQ_6
GNDQ_7
GNDQ_8
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VMV0
VMV2
VMV1
VMV4
VMV3
VMV6
VMV5
VMV7
TCK
TDI
TMS
TDO
VJTAG
TRST
VPUMP
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NC52
NC53
NC54
NC55
NC56
NC57
NC58
NC59
NC60
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72
NC73
NC74
NC75
NC76
NC77
NC78
NC79
GND43
GND42
GND41
GND40
GND39
GND38
GND37
GND36
GND35
A19
B3
B14
B15
B19
B20
C2
C3
C4
C12
C13
C16
C17
C19
C20
C21
D1
D2
D3
D20
D21
D22
E1
E2
E21
E22
F1
F20
F21
F22
G3
G22
H1
H2
H21
H22
J3
J20
K3
L1
M1
M22
N3
N20
P1
P20
R1
T1
T3
T20
U1
U20
V1
V2
V21
W1
W2
W3
W20
W21
W22
Y2
Y3
Y13
Y16
Y17
Y19
Y20
Y21
AA3
AA14
AA15
AA18
AA19
AA20
AB10
AB11
AB18
AB19
AB22
AB2
AB1
AA22
AA1
Y18
W19
W4
V20
4
VCC_IB6
B6 I/O[0..17]
1.5V
1
0.1uF
C85
0.1uF
C86
0.1uF
C62
0.1uF
C87
0.1uF
C63
100E
R18
SW_0
SW_1
SW_2
SW_3
SW_4
SW_5
SW_6
SW_7
LED_0
LED_1
LED_2
LED_3
LED_4
LED_5
LED_6
LED_7
TRST 1
1.5V
B6 I/O0
B6 I/O1
B6 I/O2
B6 I/O3
B6 I/O4
B6 I/O5
B6 I/O6
B6 I/O7
B6 I/O8
B6 I/O9
B6 I/O10
B6 I/O11
B6 I/O12
B6 I/O13
B6 I/O14
B6 I/O15
B6 I/O16
B6 I/O17
0.1uF
C61
VCC_IB6
2
1
2
1
2
1
2
2
1
2
1
2
1
2
0.1uF
C88
0.1uF
C64
3
U9G
FPGA BANK B6
1
2
SW
SW2
0.1uF
C66
0.1uF
C83
VCC_IB7
0.1uF
3
0.1uF
C84
0.1uF
C67
DECOUPLING CAPACITORS
A3PE600
IO105PDB6V0
IO105NDB6V0
IO106PDB6V0
IO106NDB6V0
IO107PDB6V0
IO107NDB6V0
IO108PDB6V0
IO108NDB6V0
IO109NPB6V0
IO109PPB6V0
IO110PDB6V0
IO110NDB6V0
IO111PDB6V1
IO111NDB6V1
IO112PDB6V1
IO112NDB6V1
IO113PPB6V1
IO113NDB6V1
IO114PDB6V1
IO114NDB6V1
IO115NDB6V1
IO116NDB6V1
IO117NDB6V1
GFA0/IO118NDB6V1
GFA1/IO118PDB6V1
GFA2/IO117PDB6V1
GFB2/IO116PDB6V1
GFC2/IO115PDB6V1
GEA0/IO102NDB6V0
GEA1/IO102PDB6V0
GEB1/IO103PDB6V0
GEB0/IO103NDB6V0
GEC0/IO104NPB6V0
GEC1/IO104PPB6V0
VCCIB6_1
VCCIB6_2
VCCIB6_3
VCCIB6
VCC6
GND6
C65
T4
T5
R6
R5
U2
U3
P6
P7
R4
P5
R2
T2
P2
N2
N6
N7
N5
P4
N1
M2
P3
M7
M3
L5
M5
M4
M8
N4
V5
V4
U4
U5
R7
T6
P8
Y1
AA2
N8
M9
M10
3
4
3.3V
0.1uF
C163
10K
R17
0.1uF
C164
3.3V
0.1uF
C69
C60
1uF
RESET#
0.1uF
C70
0.01uF
C93
2
2
2
2
RESET#
B7 I/O[0..31]
R96 0E 1
R97 0E 1
R98 0E 1
R99 0E 1
VCC_IB6
0.1uF
C68
SW2
1.5V
SWITCH AND LED INTERFACE
1
2
U16
V17
W18
V19
T17
TRST U18
U17
1
2
1
2
TCK
TDI
TMS
TDO
1
2
1
2
TCK
TDI
TMS
TDO
1
2
1
2
1
2
4
1
2
1
2
1
2
U9I
1
2
1
2
5
1
2
1
VCC_IB7
0.1uF
C71
0.1uF
C72
3.3V
0.1uF
C73
B7 I/O0
B7 I/O1
B7 I/O2
B7 I/O3
B7 I/O4
B7 I/O5
B7 I/O6
B7 I/O7
B7 I/O8
B7 I/O9
B7 I/O10
B7 I/O11
B7 I/O12
B7 I/O13
B7 I/O14
B7 I/O15
B7 I/O16
B7 I/O17
B7 I/O18
B7 I/O19
B7 I/O20
B7 I/O21
B7 I/O22
B7 I/O23
B7 I/O24
B7 I/O25
B7 I/O26
B7 I/O27
B7 I/O28
B7 I/O29
B7 I/O30
B7 I/O31
2
FPGA BANK B7
U9H
0.1uF
C74
TDI
9
7
5
3
TDO
TMS
1
0.1uF
C75
TDI
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
CON10
GND2
TRST
VJTAG
NC
GND1
0.1uF
C76
J10
JTAG
VPUMP
TMS
TDO
TCK
A3PE600
IO121PDB7V0
IO121NDB7V0
IO122PDB7V0
IO122NDB7V0
IO123PDB7V0
IO123NDB7V0
IO124PDB7V0
IO124NDB7V0
IO125PDB7V0
IO125NDB7V0
IO126PDB7V0
IO126NDB7V0
IO127PDB7V1
IO127NDB7V1
IO128PDB7V1
IO128NDB7V1
IO129PDB7V1
IO129NDB7V1
IO130PDB7V1
IO130NDB7V1
IO131PDB7V1
IO131NDB7V1
IO132NDB7V1
IO133NDB7V1
IO134NDB7V1
GFB0/IO119NPB7V0
GFB1/IO119PPB7V0
GFC0/IO120NPB7V0
GFC1/IO120PPB7V0
GAB2/IO133PDB7V1
GAA2/IO134PDB7V1
GAC2/IO132PDB7V1
VCCIB7
VCCIB7_1
VCCIB7_2
VCCIB7_3
VCC7
GND7
TCK
K2
K1
L2
L3
J2
J1
J4
K4
J5
K5
J6
K6
G2
G1
G4
H4
G5
H5
H7
J7
F3
F2
H6
F4
F5
L4
L6
L8
K7
E4
E5
G6
B2
C1
J8
K8
K9
K10
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
0.33uF/50V
C94
2
3.3V
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4
2
0.1uF
C78
TRST
Title:
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Approvals:
2061 Stierlin Ct
Mountain View, CA 94043
VCC_IB7
5
4
3
2
1
0.1uF
C80
1.5V
1.5V
2.5V
2.5V
0.1uF
C81
3.3V
3.3V
Document No:
1
Sanmina-SCI
FPGA_67_PLL
CoreARM7 DEV KIT BOARD
0.1uF
C79
3.3V
CON5
5
4
3
2
1
J9
1
VCC_IB6
5
4
3
2
1
CON5
5
4
3
2
1
J8
Actel Corp
0.1uF
C77
10
8
6
1
2
1
2
1
2
1
2
1
2
132
CoreMP7 Development Kit User’s Guide
Pg
6 of 12
1.7
Rev
0.1uF
C82
A
B
C
D
Figure B-8. LEDs and Push-Button Switches
A
B
C
D
1
D9
R35
274
1
D10
R36
274
1
D11
R37
274
5
1
D12
R38
274
5
1
D13
R39
274
1
D14
R40
274
D15
R41
274
1
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
1
2
D16
R42
274
1
1
1
1
1
1
1
1
JP17
JP16
JP15
JP14
JP13
JP12
JP11
JP10
2
2
2
2
2
2
2
2
VCC_IB6
1
1
1
1
332
R31
332
R27
332
R23
332
R19
2
2
2
2
4
3
2
1
SW5
4
3
2
1
SW7
4
3
SW9
4
3
TL1105SP_F100Q
2
1
TL1105SP_F100Q
LED_7
LED_6
LED_5
LED_4
LED_3
LED_2
LED_1
4
SW3
TL1105SP_F100Q
2
1
TL1105SP_F100Q
LED_0
4
1
2
1
2
1
2
1
2
C101
0.01UF/50V
C99
0.01UF/50V
C97
0.01UF/50V
C95
0.01UF/50V
1
2
1
2
1
2
1
2
R33
1K
R29
1K
R25
1K
R21
1K
1
1
1
1
JP8
JP6
JP4
JP2
2
2
2
2
3
3
SW_3
SW_2
SW_1
SW_0
VCC_IB6
1
1
1
1
2
2
2
2
SW4
4
3
SW6
4
3
SW8
4
3
SW10
4
3
TL1105SP_F100Q
2
1
TL1105SP_F100Q
2
1
TL1105SP_F100Q
2
1
TL1105SP_F100Q
2
1
C102
0.01UF/50V
C100
0.01UF/50V
C98
0.01UF/50V
C96
0.01UF/50V
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
332
R32
332
R28
332
R24
332
R20
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
CoreMP7 Development Kit User’s Guide
133
1
1
1
JP9
JP7
JP5
JP3
2
2
2
2
Title:
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Approvals:
2061 Stierlin Ct
Mountain View, CA 94043
Actel Corp
R34
1K
R30
1K
R26
1K
R22
1K
1
Document No:
1
Sanmina-SCI
SWITCHES & LEDS
CoreARM7 DEV KIT BOARD
SW_7
SW_6
SW_5
SW_4
1
Rev
7 of 12
1.7
Pg
A
B
C
D
Figure B-9. FPGA I/O Expansion Headers
A
B
C
D
1
D9
R35
274
1
D10
R36
274
1
D11
R37
274
5
1
D12
R38
274
5
1
D13
R39
274
1
D14
R40
274
D15
R41
274
1
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
1
2
D16
R42
274
1
1
1
1
1
1
1
1
JP17
JP16
JP15
JP14
JP13
JP12
JP11
JP10
2
2
2
2
2
2
2
2
VCC_IB6
1
1
1
1
332
R31
332
R27
332
R23
332
R19
2
2
2
2
4
3
2
1
SW5
4
3
2
1
SW7
4
3
SW9
4
3
TL1105SP_F100Q
2
1
TL1105SP_F100Q
LED_7
LED_6
LED_5
LED_4
LED_3
LED_2
LED_1
4
SW3
TL1105SP_F100Q
2
1
TL1105SP_F100Q
LED_0
4
1
2
1
2
1
2
1
2
C101
0.01UF/50V
C99
0.01UF/50V
C97
0.01UF/50V
C95
0.01UF/50V
1
2
1
2
1
2
1
2
R33
1K
R29
1K
R25
1K
R21
1K
1
1
1
1
JP8
JP6
JP4
JP2
2
2
2
2
3
3
SW_3
SW_2
SW_1
SW_0
VCC_IB6
1
1
1
1
2
2
2
2
SW4
4
3
SW6
4
3
SW8
4
3
SW10
4
3
TL1105SP_F100Q
2
1
TL1105SP_F100Q
2
1
TL1105SP_F100Q
2
1
TL1105SP_F100Q
2
1
C102
0.01UF/50V
C100
0.01UF/50V
C98
0.01UF/50V
C96
0.01UF/50V
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
332
R32
332
R28
332
R24
332
R20
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
134
CoreMP7 Development Kit User’s Guide
1
1
1
JP9
JP7
JP5
JP3
2
2
2
2
Title:
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Approvals:
2061 Stierlin Ct
Mountain View, CA 94043
Actel Corp
R34
1K
R30
1K
R26
1K
R22
1K
1
Document No:
1
Sanmina-SCI
SWITCHES & LEDS
CoreARM7 DEV KIT BOARD
SW_7
SW_6
SW_5
SW_4
1
Rev
7 of 12
1.7
Pg
A
B
C
D
Figure B-10. USB Interface
A
B
C
DE CAPS
SW_EN
1
1
JP23 2
JP24 2
3.3V
2
1
JP21 2
1
0.1uF
C107
5V
5
0.1uF
C108
JP27
1
1
JP19 2
JP26 2
1
JP18 2
SW_FLG_USB
USB_SUSPND
USB_VM
USB_VP
USB_RCV
USB_OEN
USB_MODE
7
11
14
4
74LCX04
10
74LCX04
U16E
3.3V
7
3
U16B
3.3V
14
4.7K
R43
7
6
5
4
3
2
1
7
13
D-
D+
VPO
12
74LCX04
U16F
6
NC
SPEED
74LCX04
3.3V
14
7
5
U16C
3.3V
14
VCC
VMO/SEO
USB1T11AM
GND
SUSPND
VM
VP
RCV
OE
MODE
U14
8
9
10
11
12
13
14
4
1
USB TRANSCEIVER
JP28
2
SW_EN_USB
JP251
D-
D+
JP201
3.3V
2
2
SW_FLG
USB_SPEED
2
USB_VMO/SEO
JP221
4.99K
R49
4.99K
R46
7
9
14
3
2
74LCX04
U16D
8
74LCX04
U16A
3.3V
7
1
14
3.3V
USB_VPO
3
SW_EN_USB
T POINT
TP15
T POINT
TP14
SW_FLG_USB
IN
OUT1
NC2
MIC2025
NC1
GND O U T 2
FLG
EN
U15
5
6
7
8
1
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
2
220uF/10V
+
C104
DD+
L2
L1
1
5
6
4
R44 2
R45 2
Title:
B
Size:
Date:
D+
D-
3
2
3.3V
1 15K
1 15K
5V
D+
D-
Document No:
1
Sanmina-SCI
USB
CoreARM7 DEV KIT BOARD
1 10K
1 10K
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
D+
D-
USB CONNECTOR
2061 Stierlin Ct
Mountain View, CA 94043
Eng Mgr:
1
USB Receptacle A-type
SHIELD1
SHIELD2
GND
VBUS
P1
Actel Corp
R47 2
R48 2
Approvals:
3
2
PSR05-PD10611
VCC
GND
C106
0.001uF/50V
4
1
U13
STEERING DIODE
BLM18PG121SN1
FB1
SW_EN_USB
SW_FLG_USB
0.1uF
C105
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
4
3
2
1
5V
USB POWER SWITCH
2
1
2
4
1
2
1
2
5
1
2
D
1
2
1
2
1
2
1
2
CoreMP7 Development Kit User’s Guide
135
Rev
9 of 12
1.7
Pg
A
B
C
D
A
B
C
TX0
1
1
JP32 2
JP33 2
3.3V
0.1uF
C115
0.1uF
C116
5
CAN_RXD
CAN_TXD
JP36 2
JP35 2
1
1
JP31 2
JP34 2
1
JP30 2
DECOUPLING CAPACITORS
RX1
CTS
RX0
TX1
RTS
1
JP29 2
5
1
1
C112
0.1uF
1
2
3.3V
+
3.3V
R85
182E
GREEN LED
D19
D18
RED LED
R84
432E
1
+
+
3.3V
2
C113
0.1uF
C109
0.1uF
1
2
R5IN
GND
INVALID
25
21
8
7
6
5
4
11
10
9
3
27
4
8
2
4
1
3
SHDN
CANL
CANH
MAX3051
RS
GND
RXD
TXD
VCC
U18
5
6
7
+
C110
0.1uF
C114
0.1uF
2
JP37
RX1_RS232
CTS_RS232
RX0_RS232
TX1_RS232
RTS_RS232
TX0_RS232
CAN TRANSCEIVER
MAX3243
VCC
FORCEOFF
R4IN
R3IN
R2IN
R1IN
T3OUT
T2OUT
T1OUT
V-
V+
TRANSCEIVER
FORCEON
R5OUT
R4OUT
R3OUT
R2OUT
R1OUT
R2OUTB
T3IN
T2IN
T1IN
C2-
C2+
C1-
C1+
3.3V
26
22
23
15
16
17
18
19
20
12
13
14
2
1
24
28
U17
RS-232
1
2
4
1
2
2
JP38
0.1uF
C111
R50
120E
1
D
1
2
1
2
1
2
2
1
1
2
2
1
1
2
1
2
136
+
Figure B-11. RS-232 and CAN Interfaces
CoreMP7 Development Kit User’s Guide
1
3
5
9
4
8
3
7
2
6
1
TX1_RS232
RX1_RS232
RTS_RS232
RX0_RS232
CTS_RS232
TX0_RS232
3
10
11
10
11
10
11
CONNECTOR DB9F
P3
CONNECTOR DB9F
P2
CONNECTOR DB9M
P4
5
9
4
8
3
7
2
6
1
5
9
4
8
3
7
2
6
1
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
2
Title:
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Approvals:
2061 Stierlin Ct
Mountain View, CA 94043
Actel Corp
Document No:
1
Sanmina-SCI
CAN_RS-232_TRANSCEIVER
CoreARM7 DEV KIT BOARD
1
Rev
1.7
Pg10 of 12
A
B
C
D
Figure B-12. Ethernet 0 Interface
A
B
C
D
PHY AD = 02h
EXT_IN_CLK_1
EXT_IN_CLK_0
1
5
2
C128
0.1uF
2
1
1
2
1
2
PHY_TX0-
2
2
2
2
2
2
1
PHY_TX0PHY_TX0+
PHY_RX0PHY_RX0+
TX-
CT1
LEDL2
LEDL1
NC
74
75
1
2
3
5
6
7
8
14
15
16
17
18
41
42
26
25
24
23
29
31
30
37
38
39
40
34
32
33
21
22
U19A
ETHERNET PHY
XTL-
XTL+
R65 1
R66 1
R67 1
R68 1
R63 1
R64 1
GND
LEDR2
LEDR1
4
3.3V
3.3V
LEDSPD0#
11
INTR
43
C130
0.1uF
PHY_RX0-
C129
0.1uF
20
GPIO[1]/TP125 19
GPIO[0]/10TXD--/7Wire
9
PWRDN
PHY_RX0+
AM79C874VI
PQT12x12_80H47
LED01
2 49.9E
2 49.9E
2 49.9E
2 49.9E
55
TECH_SEL[0]/LINK_BT
54
TECH_SEL[1]/SPDSEL 53
TECH_SEL[2]/DPX
48
LEDLNK#/LED_10LNK/LED_PCSBP_SD
47
LEDTX#/LEDBTB 46
LEDRX#/LEDSEL
45
LEDCOL#/SCRAM_EN#
44
LEDSPD[0]#/LEDBTA/FX_SEL#
12
8
6
5
3
2 330E
2 330E
J00-0065
RJ-45
RX-
CT2
RX+
PCSBP
ISODEF
ISO
REFCLK
CLK25
BURN_IN
RST#
64
63
77
78
66
TEST0/FXR67
TEST1/FXR+ 69
FXT+
70
FXT-
RX+
RX-
TX+
TX-
72
IBREF
68
TEST2
62
TEST3/SDI+
61
RPTR
58
LEDDPX#/LEDTXB 57
LEDSPD[1]#/LEDTXA/CLK25EN#
56
ANEGA
NetPHY-1LP
PHYAD[4]/10RXDPHYAD[3]/10RXD+
PHYAD[2]/10TXD++
PHYAD[1]/10TXD+
PHYAD[0]/10TXD-
COL/10COL
CRS/10CRS
RXD[0]/10RXD
RXD[1]
RXD[2]
RXD[3]
RX_DV
RX_ER/RXD[4]
RX_CLK/10RXCLK
TXD[0]/10TXD
TXD[1]
TXD[2]
TXD[3]
TX_EN/10TXEN
TX_ER/TXD[4]
TX_CLK/10TXCLK/PCSBP_CLK
MDIO
MDC
CON-RJ45
TX+
P5
LED01
LED00
10
LEDLNK0#
7
2
4
1
9
25Mhz
Y1
4.7K
4.7K
4.7K
4.7K
4.7K
2
LED00
C12722pF
2
C12622pF
R62 1K
PHY_TX0+
1
RST#
R57 1
R58 1
R59 1
R60 1
R61 1
0COL
0CRS
0RXD0
0RXD1
0RXD2
0RXD3
0RX_DV
0RX_ER
0TXD0
0TXD1
0TXD2
0TXD3
0TX_EN
0TX_ER
R53
1.5K
R52
1.5K
4
R56 10K
1
2
2
3
J16
PHY_RX0+
PHY_RX0-
PHY_TX0+
PHY_TX0-
1
1
2
3
J20
CON3
3
3
CON3
1
0PHYAD_3
2
3.3V
3
2
3
J18
CON3
1
0PHYAD_2
2
3.3V
3
1
0PHYAD_0
2
3.3V
LEDSPD0#
LEDLNK0#
1
3
1
1
2
3
J19
CON3
2
3
J17
3
CON3
1
0PHYAD_4
2
3.3V
3
1
0PHYAD_1
2
3.3V
3.3V
C125
0.1uF
65
60
59
51
C123
0.1uF
52
4
76
U19B
27
36
REFGND
REFVCC
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HEADER20X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J26
ETHERNET-1 JUMPER
71
73
28
DGND1
35
DGND2
VDD1
VDD2
AM79C874VI
PQT12x12_80H47
EQGND
13
49
12
OGND1
50
OGND2
OVDD1
OVDD2
NetPHY-1LP
EQVCC
ADPVCC
CRVGND
CRVVCC
TGND1
TGND2
TVCC1
TVCC2
PLLGND
PLLVCC
MDIO
1
MDC
3
0TXD0
5
0TXD1
7
0TXD2
9
0TXD3
11
0TX_EN
13
0TX_ER
15
EXT_IN_CLK_017
0RXD0
19
0RXD1
21
0RXD2
23
0RXD3
25
0RX_DV
27
0RX_ER
29
EXT_IN_CLK_131
0COL
33
0CRS
35
RST#
37
3.3V
C120
0.1uF
79
80
11
C117
0.1uF
10
PHY POWER SUPPLY
2
3.3V
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
3.3V
3.3V
1
3.3V
3.3V
0.1uF
C119
C121
0.1uF
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Title:
2061 Stierlin Ct
Mountain View, CA 94043
3.3V
1
Sanmina-SCI
ETHERNET-1
CoreARM7 DEV KIT BOARD
C122
0.1uF
Document No:
3.3V
Actel Corp
Approvals:
1
ALL THE DCAP SHOULD
BE PLACED WITHIN 3MM
OF THE CHIP
FPGA_MDIO
FPGA_MDC
FPGA_0TXD0
FPGA_0TXD1
FPGA_0TXD2
FPGA_0TXD3
FPGA_0TX_EN
FPGA_0TX_ER
FPGA_EXT_IN_CLK_0
FPGA_0RXD0
FPGA_0RXD1
FPGA_0RXD2
FPGA_0RXD3
FPGA_0RX_DV
FPGA_0RX_ER
FPGA_EXT_IN_CLK_1
FPGA_0COL
FPGA_0CRS
RESET#
C124
0.1uF
0.1uF
C118
3.3V
1
2
MDIO
MDC
0PHYAD_0
0PHYAD_1
0PHYAD_2
0PHYAD_3
0PHYAD_4
22.1E
R55
22.1E
R54
3.3V
1
1
2
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
5
13
14
13
14
1
2
1
2
CoreMP7 Development Kit User’s Guide
137
Rev
1.7
Pg 11of
12
A
B
C
D
Figure B-13. Ethernet 1 Interface
A
B
C
PHY AD = 04h
EXT_IN_CLK_3
EXT_IN_CLK_2
C142
0.1uF
2
2
2
2
2
2
4.7K
4.7K
4.7K
4.7K
4.7K
3.3V
5
2
C14122pF
2
C14022pF
PHY_TX1PHY_TX1+
PHY_RX1+
PHY_RX1-
LED11
LED10
LEDLNK1#
LED10
PHY_TX1-
PHY_TX1+
1
1
1
R77 1K
RST#
R72 1
R73 1
R74 1
R75 1
R76 1
R80 1
R81 1
R82 1
R83 1
25Mhz
Y2
1
P6
2
2
2
2
LEDL2
LEDL1
NC
TX-
CT1
R78 1
R79 1
10
9
7
2
4
TX+
U20A
ETHERNET PHY
XTL-
XTL+
2 330E
2 330E
J00-0065
11
12
8
6
5
3
3.3V
3.3V
LEDR2
LEDR1
GND
RX-
CT2
RX+
PCSBP
ISODEF
ISO
REFCLK
CLK25
BURN_IN
RST#
4
55
TECH_SEL[0]/LINK_BT
54
TECH_SEL[1]/SPDSEL
53
TECH_SEL[2]/DPX
43
LEDSPD1#
LED11
PHY_RX1-
PHY_RX1+
C143
0.1uF
20
GPIO[1]/TP125
19
GPIO[0]/10TXD--/7Wire
9
PWRDN
INTR
48
LEDLNK#/LED_10LNK/LED_PCSBP_SD
47
LEDTX#/LEDBTB
46
LEDRX#/LEDSEL
45
LEDCOL#/SCRAM_EN#
44
LEDSPD[0]#/LEDBTA/FX_SEL#
AM79C874VI
PQT12x12_80H47
C144
0.1uF
PHYAD[4]/10RXDPHYAD[3]/10RXD+
PHYAD[2]/10TXD++
PHYAD[1]/10TXD+
PHYAD[0]/10TXD-
COL/10COL
CRS/10CRS
64
63
77
78
66
TEST0/FXR67
TEST1/FXR+
69
FXT+
70
FXT-
RX+
RX-
TX+
TX-
72
IBREF
68
TEST2
62
TEST3/SDI+ 61
RPTR
58
LEDDPX#/LEDTXB
57
LEDSPD[1]#/LEDTXA/CLK25EN#
56
ANEGA
NetPHY-1LP
RXD[0]/10RXD
RXD[1]
RXD[2]
RXD[3]
RX_DV
RX_ER/RXD[4]
RX_CLK/10RXCLK
RJ-45
49.9E
49.9E
49.9E
49.9E
4
TXD[0]/10TXD
TXD[1]
TXD[2]
TXD[3]
TX_EN/10TXEN
TX_ER/TXD[4]
TX_CLK/10TXCLK/PCSBP_CLK
MDIO
MDC
CON-RJ45
74
75
1
2
3
5
6
7
8
14
15
16
17
18
41
42
R70 1
1COL
1CRS
1RXD0
1RXD1
1RXD2
1RXD3
1RX_DV
1RX_ER
2 22.1E
R69 1
1PHYAD_0
1PHYAD_1
1PHYAD_2
1PHYAD_3
1PHYAD_4
26
25
24
23
29
31
30
1TXD0
1TXD1
1TXD2
1TXD3
1TX_EN
1TX_ER
2 22.1E
1
2
D
21
22
37
38
39
40
34
32
33
2
1
1
1
1
3
1PHYAD_4 2
3.3V
3
1PHYAD_2 2
3.3V
3
3
10K
CON3
1
2
3
J25
CON3
1
2
3
J23
CON3
2
3
J21
LEDSPD1#
LEDLNK1#
2
PHY_RX1+
PHY_RX1-
PHY_TX1+
PHY_TX1-
1
1PHYAD_0
2
3.3V
R71 1
3
3.3V
1
1
3
1PHYAD_3 2
3.3V
3
1PHYAD_1 2
CON3
1
2
3
J24
CON3
1
2
3
J22
3.3V
3.3V
3.3V
1
MDIO
MDC
13
14
13
14
1
2
3.3V
2
65
U20B
27
36
REFGND
REFVCC
3.3V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HEADER20X2
39
MDIO
1
MDC
3
1TXD0
5
1TXD1
7
1TXD2
9
1TXD3
11
1TX_EN
13
1TX_ER
15
EXT_IN_CLK_217
1RXD0
19
1RXD1
21
1RXD2
23
1RXD3
25
1RX_DV
27
1RX_ER
29
EXT_IN_CLK_331
1COL
33
1CRS
35
RST#
37
ETHERNET-2 JUMPER
71
73
28
DGND1
35
DGND2
VDD1
VDD2
AM79C874VI
PQT12x12_80H47
EQGND
13
49
12
OGND1
50
OGND2
OVDD1
OVDD2
NetPHY-1LP
EQVCC
ADPVCC
CRVGND
CRVVCC
TGND1
TGND2
TVCC1
TVCC2
PLLGND
PLLVCC
3.3V
C138
0.1uF
C132
0.1uF
PCB FAB:,REV.0X
2
PCB ASSEMBLY:,REV.0X
BOARD INFORMATION
SCHEMATIC DIAGRAM NOTES
1.UNLESS STATED OTHERWISE:
A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.
B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.
C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V
C139
0.1uF
60
59
51
C137
0.1uF
52
4
76
79
80
11
C131
0.1uF
10
PHY POWER SUPPLY
C134
0.1uF
2
1
2
1
2
5
1
2
1
2
1
2
C135
0.1uF
3.3V
C136
0.1uF
Title:
B
Size:
Date:
DRAWN BY:
Thursday, December 01, 2005
Assembly
Doc Ctrl:
Engr:
Eng Mgr:
Approvals:
2061 Stierlin Ct
Mountain View, CA 94043
Actel Corp
FPGA_MDIO
FPGA_MDC
FPGA_1TXD0
FPGA_1TXD1
FPGA_1TXD2
FPGA_1TXD3
FPGA_1TX_EN
FPGA_1TX_ER
FPGA_EXT_IN_CLK_2
FPGA_1RXD0
FPGA_1RXD1
FPGA_1RXD2
FPGA_1RXD3
FPGA_1RX_DV
FPGA_1RX_ER
FPGA_EXT_IN_CLK_3
FPGA_1COL
FPGA_1CRS
RESET#
3.3V
C133
0.1uF
1
2
1
2
1
2
1
2
138
CoreMP7 Development Kit User’s Guide
1
Sanmina-SCI
ETHERNET-2
CoreARM7 DEV KIT BOARD
Document No:
3.3V
ALL THE DCAP SHOULD
BE PLACED WITHIN 3MM
OF THE CHIP
1
Rev
1.7
Pg12 of 12
A
B
C
D
C
Signal Layers
The CoreMP7 Evaluation Board is a six-layer board. The board has the following copper layers:
Figure C-1 on page 140: Layer 1 – Top Signal Layer
Figure C-2 on page 141: Layer 2 – Ground Plane
Figure C-3 on page 142: Layer 3 – Signal Layer 3
Figure C-4 on page 143: Layer 4 – Signal Layer 4
Figure C-5 on page 144: Layer 5 – Power Plane
Figure C-6 on page 145: Layer 6 – Bottom Signal Layer
CoreMP7 Development Kit User’s Guide
139
Figure C-1. Layer 1 – Top Signal Layer
140
CoreMP7 Development Kit User’s Guide
Figure C-2. Layer 2 – Ground Plane (Blank)
CoreMP7 Development Kit User’s Guide
141
Figure C-3. Layer 3 – Signal Layer 3
142
CoreMP7 Development Kit User’s Guide
Figure C-4. Layer 4 – Signal Layer 4
CoreMP7 Development Kit User’s Guide
143
Figure C-5. Layer 5 – Power Plane (Blank)
144
CoreMP7 Development Kit User’s Guide
Figure C-6. Layer 6 – Bottom Signal Layer
CoreMP7 Development Kit User’s Guide
145
D
Product Support
Actel backs its products with various support services including Customer Service, a Customer
Technical Support Center, a web site, an FTP site, electronic mail, and worldwide sales offices. This
appendix contains information about contacting Actel and using these support services.
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product
upgrades, update information, order status, and authorization.
From Northeast and North Central U.S.A., call 650.318.4480
From Southeast and Southwest U.S.A., call 650. 318.4480
From South Central U.S.A., call 650.318.4434
From Northwest U.S.A., call 650.318.4434
From Canada, call 650.318.4480
From Europe, call 650.318.4252 or +44 (0) 1276 401 500
From Japan, call 650.318.4743
From the rest of the world, call 650.318.4743
Fax, from anywhere in the world 650.318.8044
Actel Customer Technical Support Center
Actel staffs its Customer Technical Support Center with highly skilled engineers who can help
answer your hardware, software, and design questions. The Customer Technical Support Center
spends a great deal of time creating application notes and answers to FAQs. So, before you contact
us, please visit our online resources. It is very likely we have already answered your questions.
Actel Technical Support
Visit the Actel Customer Support website (www.actel.com/custsup/search.html) for more
information and support. Many answers available on the searchable web resource include diagrams,
illustrations, and links to other resources on the Actel web site.
Website
You can browse a variety of technical and non-technical information on Actel’s home page, at
www.actel.com.
CoreMP7 Development Kit User’s Guide
147
Product Support
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center from 7:00 A.M. to 6:00 P.M., Pacific
Time, Monday through Friday. Several ways of contacting the Center follow:
Email
You can communicate your technical questions to our email address and receive answers back by
email, fax, or phone. Also, if you have design problems, you can email your design files to receive
assistance. We constantly monitor the email account throughout the day. When sending your
request to us, please be sure to include your full name, company name, and your contact information
for efficient processing of your request.
The technical support email address is [email protected].
Phone
Our Technical Support Center answers all calls. The center retrieves information, such as your
name, company name, phone number and your question, and then issues a case number. The Center
then forwards the information to a queue where the first available application engineer receives the
data and returns your call. The phone hours are from 7:00 A.M. to 6:00 P.M., Pacific Time, Monday
through Friday. The Technical Support numbers are:
650.318.4460
800.262.1060
Customers needing assistance outside the US time zones can either contact technical support via
email ([email protected]) or contact a local sales office. Sales office listings can be found at
www.actel.com/contact/offices/index.html.
148
CoreMP7 Development Kit User’s Guide
Index
10/100 Ethernet 19
A
Actel
electronic mail 148
telephone 148
web-based technical support 147
website 147
assumptions 5
B
board
CAN 21
clocks 21
description 9
Ethernet 19
headers 22
jumpers 15
layers 22
LEDs 16
memory 22
PLLs 11
power supplies 12
block diagram 12
programming 14
RS-232 18
schematics 125
self test 25
programming 25
switches 17
test points 22
testing 25
programming 25
top-level view 10
usage 9
USB 20
CoreMP7 Development Kit User’s Guide
C
CAN 21
clocks 21
CompanionCore 21
contacting Actel
customer service 147
electronic mail 148
telephone 148
web-based technical support 147
Core10/100 19
CoreMP7 evaluation board 9
CoreUART 18
customer service 147
D
design flow 27
design creation 29
implementation 30
microprocessor 31
programming 31
system creation 27
verification 29
development kit contents 7
E
Ethernet 19
example design 14
F
FPGA package connections 105
H
hardware 9
description 9
installation 25
headers 22
149
Index
J
R
jumpers 15
RS-232 18
K
S
kit contents 7
schematics 125
self test 25
programming 25
setup 25
software
installation 25
switches 17
system requirements 7
L
LEDs 16
M
memory 22
P
PLLs 11
power supplies 12
block diagram 12
product support 147–148
customer service 147
electronic mail 148
technical support 147
telephone 148
website 147
programming 14
T
technical support 147
test points 22
testing 25
programming 25
U
USB 20
W
web-based technical support 147
150
CoreMP7 Development Kit User’s Guide
For more information about Actel’s products, visit our website at
http://www.actel.com
Actel Corporation • 2061 Stierlin Court • Mountain View, CA 94043 USA
Customer Service: 650.318.1010 • Customer Applications Center: 800.262.1060
Actel Europe Ltd. • Dunlop House, Riverside Way • Camberley, Surrey GU15 3YL • United Kingdom
Phone +44 (0) 1276 401 450 • Fax +44 (0) 1276 401 490
Actel Japan • EXOS Ebisu Bldg. 4F • 1-24-14 Ebisu Shibuya-ku • Tokyo 150 • Japan
Phone +81.03.3445.7671 • Fax +81.03.3445.7668 • www.jp.actel.com
Actel Hong Kong • Suite 2114, Two Pacific Place • 88 Queensway, Admiralty Hong Kong
Phone +852 2185 6460 • Fax +852 2185 6488 • www.actel.com.cn
50200075-0/8.06