6 5 4 3 2 1 REVISION RECORD LTR ECO NO: APPROVED: DATE: Analog Inputs D D Solder Link Connections: A: Buffered input (Default) B: Direct to ADC Input pins C: Route through 'Amplifier Mezzanine Card' for Alternative Amplifier Evaluation (Ch 5 ONLY) A4+ A0+ Default A SL0+ A0+ Place close to AINx +/- pins A0+_AMP AIN4+ 10r C77 C72 AIN0- 10r R146 AIN4- A1+_AMP 270pF 270pF SREWTERM-8_RA SREWTERM-8_RA J8 10r AI1- A5+_SURF A2+ AIN2+ Default A J9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SL5-1 AIN5- Default A SL23 A B C AI5- A5-_SURF 10r C88 Default A C38 270pF C41 680pF AIN510r A5-_SURFOUT A6+ AIN2+ AIN6+ C91 680pF AI6+ R74 Place close to AINx +/- pins AIN6+ B A 10r A6+_AMP Default A C42 270pF GND8 GND7 C33 680pF 270pF C43 A2- AIN2- GND AI2- 270pF Place close to AINx +/- pins 270pF C89 AIN2- C34 R87 A B C SL6+ A2+_AMP 270pF A6- R151 A2- B A AIN5+ 10r A5- A5-_AMP C Place close to AINx +/- pins A6+ R155 SL2- R84 A5+_SUFTOUT A2+ SL2+ B A Default A SL22 AIN1- AI2+ B A5+ A B C Default A R143 A1-_AMP AI5+ C85 680pF A1- Default A AIN5+ AIN1+ A5+_AMP A B C 10r C81 B A GND9 AIN410r Place close to AINx +/- pins A1- J13 C52 680pF AI4- SL5+1 AI1+ SL1- J14 270pF A1+ C86 AIN1- C30 R107 A4-_AMP A1+ B A 8 7 6 5 4 3 2 1 270pF AI0- C 8 7 6 5 4 3 2 1 C164 A4- B A A0-_AMP Default A SL1+ AIN1+ 10r A4- Default A SL4- AIN0- A0R134 AIN4+ A4+_AMP AI4+ C76 680pF A0- Default A SL0B A 270pF Place close to AINx +/- pins R102 AIN0+ 270pF AI0+ A4+ B A R139 B A AIN0+ Default A SL4+ AGND AGND SL6- 10r A2-_AMP Default A AIN6- AGND A3+ R79 A6- AIN6- B A 10r A6-_AMP Default A AI6- B A3+ To use optional header (Amplifier Mezzanine Card) solder link SL3+ & SL3- to C SL3+ R164 B A Place close to AINx +/- pins A7+ A7+ A3+_AMP AIN3+ 10r C90 270pF AIN3+ C93 680pF AI3+ C92 270pF A B AIN7+ R81 A7+_AMP AIN7+ 10r SL7+ AI7+ AIN3- A3- R163 A3-_AMP C44 270pF C48 270pF C35 680pF A7- SL3B A Place close to AINx +/- pins A7- SL7- 10r B A AIN3- AIN7- R80 AIN710r A7-_AMP AI7- AI3- Place between ch0 and ch4 SMA inputs AGND J15 1 2 3 J16 1 2 3 COMPANY: Analog Devices VCOM A A TITLE: DRAWN: EVAL-AD7768FMCZ DATED: Rob Finnerty CHECKED: DATED: Martin Madden QUALITY CONTROL: Place SL20,SL21 after amplifier and surfboard <QC By> DATED: <QC Date> CODE: SIZE: <Code> A2 DRAWING NO: REV: 02-0 A Close to RC input network RELEASED: <Released By> DATED: <Release Date>SCALE: <Scale> SHEET:1 OF 7 6 5 4 3 2 1 REVISION RECORD AMP+ AMPC70 C71 0.1uF 1nF 8 V+ C75 0r C74 U11-C LTR AMP+ Ch 0 0r 4 R148 C80 C79 0.1uF 1nF 8 V+ U12-C DNI DATE: C83 C84 0r 0r Ch 1 4 VR160 DNI ADA4896-2 DNI C147 D APPROVED: AMP- V- ADA4896-2 ECO NO: D C151 R238 DNI DNI R144 0r R240 R140 A0+_AMP R153 0r R149 C149 DNI DNI R145 2 0r R141 3 ADA4896-2 IN- R147 1 OUT R162 A1+_AMP 0r R135 A0+ IN+ 0r R236 0r R239 VCOM ADA4896-2 2 IN- 3 DNI 10k 10k 0r R154 0r R150 R158 R159 1 OUT A1+ IN+ 0r 0r U12-A DNI External Buffers (Default Gain = 1) External Buffers (Default Gain = 1) C150 C148 DNI R161 DNI C152 0r U11-A VCOM DNI 0r R118 DNI R132 DNI C139 DNI C143 R233 DNI DNI R127 R235 DNI R137 0r C R130 R152 0r A0-_AMP R119 DNI 6 C140 R128 0r 5 DNI R131 IN- R125 R126 7 OUT A0- IN+ C 0r 0r A1-_AMP ADA4896-2 R133 C142 0r 0r R138 DNI 0r DNI U11-B 0r R142 ADA4896-2 6 IN- 5 R157 R136 7 OUT A1- IN+ 0r 0r 0r U12-B 10k VCOM R237 10k C144 DNI C141 VCOM AMP+ AMPC97 C96 0.1uF 1nF 8 AMP+ AMP- C103 C102 V+ C98 0r 0r U14-C DNI R234 Ch 2 C104 C99 0.1uF 1nF C105 0r 0r 8 V+ Ch 3 U15-C 4 VR200 DNI ADA4896-2 4 B V- C162 B R203 DNI ADA4896-2 DNI C160 R251 DNI R195 DNI R250 0r A2+_AMP R194 R201 DNI 2 3 C106 R196 0r DNI R247 DNI ADA4896-2 IN- R199 1 OUT R179 R208 A3+_AMP 0r 0r A2+ IN+ 0r R204 DNI 0r 2 C107 3 U14-A R192 0r VCOM R197 0r DNI 10k VCOM External Buffers (Default Gain = 1) DNI R248 0r R198 0r R193 ADA4896-2 IN- OUT R202 1 R172 A3+ IN+ 0r 0r U15-A 10k External Buffers (Default Gain = 1) DNI R170 DNI C159 C161 R174 DNI C153 DNI C155 R241 DNI DNI R181 R242 DNI COMPANY: R165 A A2-_AMP 0r 0r R171 DNI 6 0r 5 C154 R182 DNI R189 R245 VCOM Analog Devices R184 0r R191 ADA4896-2 ININ+ OUT R180 7 A3-_AMP R169 A2- 0r TITLE: R175 C156 0r R185 DNI 0r U14-B R190 10k R246 VCOM DNI 0r 6 5 EVAL-AD7768FMCZ ADA4896-2 ININ+ OUT R183 7 0r R173 0r DRAWN: DATED: Rob Finnerty CHECKED: 0r U15-B 10k C157 DNI A A3- 0r DATED: Martin Madden QUALITY CONTROL: <QC By> DNI C158 24/11/2014 RELEASED: <Released By> 24/11/2014 DATED: <QC Date> CODE: SIZE: <Code> A2 DRAWING NO: REV: 02-0 A DATED: <Release Date>SCALE: <Scale> SHEET: 2OF 7 6 5 4 3 2 1 REVISION RECORD AMP+ AMP- C37 C36 0.1uF 1nF 8 V+ C39 C40 0r 0r AMP+ AMPC21 0.1uF C20 C25 C26 1nF 0r 0r Ch 4 U8-C 8 LTR APPROVED: DATE: V+ Ch 6 U5-C 4 ECO NO: VR105 DNI ADA4896-2 4 C135 D VR56 DNI ADA4896-2 D DNI C123 R232 DNI R100 R111 A4+_AMP DNI 0r R106 DNI C136 R110 R104 1 OUT 0r 0r C124 A4+ IN+ R101 0r R223 R52 IN- 3 DNI 0r DNI ADA4896-2 2 R60 A6+_AMP 0r DNI R57 DNI 2 0r 3 R231 10k R222 VCOM R53 0r R50 A6+ IN+ 0r 0r DNI U5-A C122 External Buffers (Default Gain = 1) C134 0r R59 R55 1 OUT 10k DNI VCOM U8-A R96 0r ADA4896-2 IN- External Buffers (Default Gain = 1) R72 DNI R27 DNI C129 DNI C119 R226 DNI DNI R76 R216 R26 0r A4-_AMP DNI 0r A6-_AMP 0r R34 C 0r R73 C128 DNI R77 DNI R83 IN- 5 0r C117 ADA4896-2 6 7 OUT R103 R75 DNI A4- IN+ 0r R28 0r 0r U8-B R230 R220 10k VCOM AMPC28 0.1uF 1nF 8 R35 0r R39 0r 5 ADA4896-2 IN- R51 R33 7 OUT A6- IN+ 0r 0r U5-B C120 AMP+ C29 10k DNI C130 VCOM 6 DNI DNI C R78 AMP+ AMP- C31 C32 C14 C13 C17 C18 0r 0r 0.1uF 1nF 0r 0r V+ Ch 5 U6-C 8 V+ Ch 7 U3-C 4 VR94 DNI ADA4896-2 4 B V- B R43 DNI ADA4896-2 C132 DNI C118 R229 A5+_AMP R99 DNI DNI 0r R85 0r R218 R47 A7+_AMP C133 DNI R95 R86 DNI 2 3 0r ADA4896-2 IN- OUT DNI 0r R70 R93 1 A5+ IN+ R37 0r 0r C121 R44 DNI 2 0r DNI R82 3 0r U6-A R228 10k R215 VCOM 10k DNI 0r R32 R63 DNI OUT R41 R42 1 A7+ IN+ 0r 0r U3-A External Buffers (Default Gain = 1) C116 External Buffers (Default Gain = 1) C131 DNI VCOM 0r R38 ADA4896-2 IN- R13 DNI C126 DNI R224 R62 DNI C114 0r A5-_AMP COMPANY: R213 A7-_AMP 0r A DNI R67 R6 Analog Devices DNI R20 0r 0r A C125 TITLE: DNI R64 DNI 6 5 0r R71 DNI VCOM ININ+ OUT R66 7 R61 C113 A5- 0r DNI R14 DNI 6 R21 0r 5 R25 0r 0r 0r U6-B 10k R214 VCOM 10k ADA4896-2 ININ+ U3-B C115 C127 R225 R68 ADA4896-2 OUT R19 7 0r R12 A7- DRAWN: Rob Finnerty 0r CHECKED: 24/11/2014 DATED: Martin Madden QUALITY CONTROL: <QC By> DNI EVAL-AD7768FMCZ DATED: RELEASED: <Released By> 24/11/2014 DATED: <QC Date> CODE: SIZE: <Code> A2 DRAWING NO: REV: 02-0 A DATED: <Release Date>SCALE: <Scale> SHEET: 3OF 7 6 5 4 3 2 1 REVISION RECORD DREGCAP SL18 links Over Drive DREGCAP for IOVDD<2.25V IOVDD IOVDD C82 SYNC_OUT C50 C51 D AIN0- 1uF C78 C53 0.1uF AIN0+ 1uF 1uF C63 1uF C49 C61 0.1uF 0.1uF 0.1uF 10uF C57 A B SL2 A B SL3 SYNCIN START SYNC_OUT SL5 R98 DNI 63 64 AIN0+ AIN0AIN1+ 2 3 AVDD1A 46 AVSS1A AVSS1B 45 AVDD1B 54 AVSS D RESET START 0.1uF 0.1uF 4 DATE: IOVDD R88 DNI SL5 links SYNC_IN to SYNC_OUT Default 0r in place C60 1uF APPROVED: IOVDD SYNC_IN C54 C62 ECO NO: R89 DNI IOVDD SL18 RCAPB AVDD2 AVDD1 LTR IOVDD Default Setting: ADC Data output on all 8 DOUTs FORMAT0 (SL2), FORMAT1(SL3) = B, A (0, 0) ADC DATA OUTPUT INTERFACE 53 AVDD2B 51 52 AVSS2B 33 35 REGCAP_B IOVDD 34 DGND 56 DREGCAP 55 FORMAT0 36 FORMAT1 37 38 SYNC_IN SYNC_OUT 30 START RESET DRDY DCLK AIN1+ 29 28 R113 0r R114 0r DRDY DRDY DCLK DCLK DO0 AIN1- 1 AIN2+ 8 AIN2- 7 AIN3+ 10 AIN1- DOUT0 DOUT1 AIN3- VCM R36 DOUT2 DOUT3 U9 AD7768BSTZ AIN3+ AIN3- DOUT5 C64 0.1uF C R120 DNI DOUT6 49 AIN4+ DOUT7 AIN4- 50 AIN5+ 47 AIN5- 48 42 AIN641 AIN6+ 26 R117 0r 25 R115 0r 24 R116 0r DOUT0 DO1 23 R123 0r 22 R124 0r 21 R122 0r 20 R129 0r DOUT1 DO2 DOUT2 DO3 DOUT3 DO4 DOUT4 DO5 DOUT5 59 49.9r AIN4+ 0r AIN2- VCM VCM_OUT R112 AIN2+ DOUT4 9 27 DO6 DOUT6 DO7 DOUT7 AIN4PDO/CS C 16 AIN5+ PD1/SCLK 17 AIN5DEC1/SDI 18 place close to DCLK, DRDY GND12 AIN6DEC0/SDO GND13 19 AIN6+ CS PD0 62 C69 61 REF2+ 43 REF20.1uF 44 REF15 REF1+ 0.1uF XTAL1 XTAL2/MCLK 31 32 58 6 C67 AIN7+ DNI 1uF AIN7- 0.1uF C66 0.1uF C138 1uF C146 A 1uF AVDD2 C137 12 MODE2 FILTER MODE3 SPI/PIN 11 B 57 GND14 GND15 SCLK FILTER R90 PD1 SCLK A IOVDD B MD3 1uF IOVDD place close to DOUT6/7 IOVDD C SL6 MODE3 RCAPA CS A FLTR R92 Default A C145 MODE1 DNI R91 C68 SL4A B MODE0 15 60 40 REGCAP_A 14 39 AVSS2A 13 AVDD2A DNI AIN7+ AIN7- CLK_SEL place close to SYNC_IN/SYNCOUT C SL7 Clock Termination GND16 GND17 MD2 MODE2 DEC1 MD1 SDI MD0 REF+ SDI A MODE1 place close to XTAL2 pin IOVDD B GND18 C SL8 MODE0 B B SDO DEC0 SDO A XT1 SL14 FILTER_0 IOVDD Connect to AD7768 Pin: R253 0r A B FILTER R254 MCLK Source Selection IOVDD B 0r C SL9 32MHZ C46 DNI 11 XT2 Y1 *FOR PIN CONTROL: SETTING TO B or C CONTROLS DEC RATE AND POWER DOWN FUNCTIONS C45 C DNI GND1 GND4 GND2 GND5 SL10 12 SL4 C SL1 IOVDD B SDP_MCLK A = SPI (Default) A: Crystal Oscillator (Default) B: External CMOS/LVDS Clock C: MCLK from Blackfin TMR_A A IOVDD MODE0 C B A B 1 A 4 3 2 MODE_0 SL11 MODE_1 A B IOVDD MODE1 13 IOVDD MODE2 14 C MCLK Y2 4 C59 0.1uF 1 0r R109 VCC ST OUT GND GND3 MODE3 15 GND6 SL4 SETS AD7768 FOR PIN OR SPI CONTROL DEFAULTED TO SPI CONTROL 3 COMPANY: Analog Devices 2 A TITLE: XTAL-EPSON-SG-210SERIES EVAL-AD7768FMCZ Crystal Oscillator A B IOVDD EXT CMOS IOVDD SL13 MODE_3 J7 & J6: USE FOR LVDS MCLK INPUT A B A J6 C SL12 MODE_2 B = PIN Config J7 DRAWN: DATED: Rob Finnerty 24/11/2014 C CHECKED: PIN Configuration: Mode and Filter Connections A = SDP GPIO Control B = GND: PIN CONFIG LOOKUP TABLE C = IOVDD: PIN CONFIG LOOKUP TABLE DATED: Martin Madden QUALITY CONTROL: <QC By> RELEASED: <Released By> 24/11/2014 DATED: <QC Date> CODE: SIZE: <Code> A2 DRAWING NO: REV: 02-0 A DATED: <Release Date>SCALE: <Scale> SHEET: 4 OF 7 6 5 4 3 2 1 REVISION RECORD 5V, 1.8V Regulators POWER SUPPLY : Jack or Bench Connection LTR ECO NO: APPROVED: DATE: J1 = Jack Connector A Ext 1.8-3.6V LK2 V+ Select Amplifier Rails EXT_IOVDD B A +12V LK1 D V+ GND V- B J1-4 J3 1 2 3 D1 11.1V GND19 J1-3 U16 ADP7118ARDZ-3.3 C4 10uF 7 VIN 8 VIN V+ J1-1 SMBJ10A-TR J1-2 IOVDD B A 1 VOUT 2 VOUT 2.2uf C8 D3 DNI SENSE/ADJ 5 DNI SS EP(GND) 9 VIOVDD_EN SMBJ10A-TR EN GND 4 C7 R15 2.2uf 5k1 3 D 6 V_AMP D5 Red C58 SL_AMP+ EXT_AVDD2 C22 0.1uF EXT_AVDD2 C6 10uF C11 AVDD2 Ext 5V or 2.5V 0.1uF B A EXT_AVDD1 AVDD1 AMP+ A B V+ Ext 5V or 2V External supply: Stand-Alone Operation J2-4 AMP- IOVDD 1nF AVDD2 B A SLP4 Default À C3 Star Point Ground SL_AMPV- EXT_AVDD1 J2-3 5V LINEAR U7 REGULATOR ADP7118ARDZ-5.0 V+ AVDD1 Default À C5 10uF C10 C15 7 VIN 8 VIN 0.1uF 2.2uf AVDD2 SLP2 Default A B A 1 VOUT 2 VOUT SLP1 F1 AVDD1 1K Ferrite Bead C27 SENSE/ADJ GND C GND J2-1 5 AVDD_EN J2-2 EN SS EP(GND) 9 0.1uF 3 C19 6 2.2uf GND 4 R4 5k1 C C55 1nF IOVDD D4 Red EXT_IOVDD J2-5 C1 10uF C2 0.1uF Power Sequence Control V+ V_5V1_DIODE R11 10k R2 R1 61R9 4k53 R3 86k6 U2 B Amplifer and Reference Supply R9 C Q2 B C9 U1 ADP7118ARDZ 7 VIN 8 VIN V+ BZT52 1 VOUT 2 VOUT 5 EN EP(GND) 9 R65 V_AMP_EN SS GND 4 10k2 DNI C65 40k2 VIN1 OUT1 VIN2 OUT2 VIN3 OUT3 VIN4 PWRGD 8 7 6 C23 0r R17 IOVDD_EN 0r R31 10k D6 GREEN R23 V_AMP_EN 0r R30 SI2304DDS-T1-GE3 Q1 0r R16 2.2uf B AVDD_EN 9 GND 1 3 6 5 R49 1K R24 10k R10 10 VDD ADM1185ARMZ 0r R40 10k2 C47 DNI R108 IOVDD 1nF R8 100K 100K R69 4 V_5V1_DIODE V_AMP R58 SENSE/ADJ R48 69k8 3 R5 E D2 C16 2.2uf 0r AVDD1 7V OUTPUT 2 R18 10k 100r R22 100K 0r C12 V_AMP R7 69k8 DNI R46 69k8 COMPANY: Analog Devices R29 A C24 DNI R45 10k2 A TITLE: 0r DRAWN: EVAL-AD7768FMCZ DATED: Rob Finnerty CHECKED: 24/11/2014 DATED: Martin Madden QUALITY CONTROL: <QC By> RELEASED: <Released By> 24/11/2014 DATED: <QC Date> CODE: SIZE: <Code> A2 DRAWING NO: REV: 02-0 A DATED: <Release Date>SCALE: <Scale> SHEET: 5OF 7 6 5 4 3 2 1 REVISION RECORD LTR Precision Voltage Reference ECO NO: APPROVED: DATE: REFERENCE BUFFER ADA4841-1 D D AMP+ 7 Default B C111 0.1uF 3 4 NC GND 6 U19 VOUT TP8 C109 8 3 TP1 TRIM Default B ADA4841-1YRJZ R54 SL17 6 V+ 1 C73 4 5 REF+ V- 0.1uF PD R178 R156 510r 0.1uF 1 1nF SL16 A 4.7uF U17 ADR444BRZ C165 0.1uF B C112 C95 A NC B +VIN + 2 AMP+ C167 3r3 2 5 0r C166 22uF 0.1uF C87 R168 0.1uF 42k2 R177 499r C C AUXR207 R187 0r 0r OPTIONAL HEADER CONNECTOR (Amplifier Mezzanine Card for Ch5) GND10 R188 0r GND11 2 3 AUX+ R176 U13-A + R205 1 OP2177 AUXOUT J11-1 J12-1 A5+_SURF J11-2 0r A5+_SUFTOUT AGND J12-2 AGND 0r J11-3 R186 0r J11-4 J11-5 0r R243 0r R244 0r R249 J12-3 AMP- J12-4 VCOM J12-5 AMP+ AGND J12-6 J11-6 AGND J11-7 B R206 J12-7 0r A5-_SURFOUT A5-_SURF B Creating VCOM - Common Mode for ADC Analog Inputs AMP+ C100 C101 0.1uF 1nF V+ V- U13-C 8 OP2177 Place close to analog input terminals 4 VCM_OUT C56 DNI R255 Default A A B R166 5 + R252 7 OP2177 0r Default A 0r SL15 VCOM R167 AVDD1 U13-B - A 6 SL19 DNI C94 0.1uF B VCM_OUT 0r VCM_OUT COMPANY: A Analog Devices A TITLE: DRAWN: EVAL-AD7768FMCZ DATED: Rob Finnerty CHECKED: 24/11/2014 DATED: Martin Madden QUALITY CONTROL: <QC By> RELEASED: <Released By> 24/11/2014 DATED: <QC Date> CODE: SIZE: <Code> A2 DRAWING NO: REV: 02-0 A DATED: <Release Date>SCALE: <Scale> SHEET: 6OF 7 6 5 4 3 2 1 REVISION RECORD LTR D RESET DOUT1 FILTER_0 MODE_0 12V GA0 +12V C 3P3VAUX U10 8 P1-A ASP-134604-01 C1 C2 C3 C4 C5 C6 C7 RESET C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 ECO NO: APPROVED: DATE: FMC-LPC Connector AK20 AK21 AJ24 AK25 AD21 AE21 AD27 AD28 AJ28 AJ29 GND No Connect No Connect GND GND No Connect No Connect GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND SCLK R97 SDP_MCLK 0r CS SYNC_OUT DOUT6 DOUT7 3P3VAUX GA1 P1-B ASP-134604-01 D1 D2 D3 D4 D5 D6 D7 D8 AE23 D9 AF23 D10 D11 AG22 D12 AH22 D13 D14 AK23 D15 AK24 D16 D17 AB24 D18 AC25 D19 D20 AB27 D21 AC27 D22 D23 AH26 D24 AH27 D25 D26 AK29 D27 AK30 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D PG_C2M GND GND No Connect No Connect GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V C VCC GA1 GA0 1 E0 2 E1 3 E2 6 7 SDA 5 I2C address set by controller board If Eval board does not use JTAG TDI and TDO then they must be shorted together (as shown) so as not to break JTAG chain SCL WP VSS 4 M24C02-WDW6TP DCLK EEPROM required in VITA standard I2C line pull-up resistors on FPGA board DRDY DOUT0 SDO START B DOUT4 DOUT5 P1-C ASP-134604-01 G1 G2 G3 G4 G5 G6 AD23 G7 AE24 G8 G9 AG20 G10 AH20 G11 G12 AJ22 G13 AJ23 G14 G15 AA20 G16 AB20 G17 G18 AC22 G19 AD22 G20 G21 AF26 G22 AF27 G23 G24 AJ27 G25 AK28 G26 G27 AC26 G28 AD26 G29 G30 AE28 G31 AF28 G32 G33 AD29 G34 AE29 G35 G36 AC29 G37 AC30 G38 G39 G40 GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND DOUT2 DOUT3 SYNC_IN SDI MODE_1 MODE_2 MODE_3 P1-D Board present pin ASP-134604-01 H1 No Connect H2 PRSNT_M2C_L H3 GND H4 AF22 CLK0_M2C_P H5 AG23 CLK0_M2C_N H6 GND H7 AF20 LA02_P H8 AF21 LA02_N H9 GND H10 AH21 LA04_P H11 AJ21 LA04_N H12 GND H13 AG25 LA07_P H14 AH25 LA07_N H15 GND H16 AE25 LA11_P H17 AF25 LA11_N H18 GND H19 AC24 LA15_P H20 AD24 LA15_N H21 GND H22 AJ26 LA19_P H23 AK26 LA19_N H24 GND H25 AG27 LA21_P H26 AG28 LA21_N H27 GND H28 AG30 LA24_P H29 AH30 LA24_N H30 GND H31 AE30 LA28_P H32 AF30 LA28_N H33 GND H34 AB29 LA30_P H35 AB30 LA30_N H36 GND H37 Y30 LA32_P H38 AA30 LA32_N H39 GND H40 VADJ B COMPANY: A Analog Devices A TITLE: DRAWN: EVAL-AD7768FMCZ DATED: Rob Finnerty CHECKED: 24/11/2014 DATED: Martin Madden QUALITY CONTROL: <QC By> RELEASED: <Released By> 24/11/2014 DATED: <QC Date> CODE: SIZE: <Code> A2 DRAWING NO: REV: 02-0 A DATED: <Release Date>SCALE: <Scale> SHEET: 7OF 7