INFINEON XC2000_1

U s e r ’ s Ma n u a l , V 1 . 0 , J u n e 2 0 0 7
XC2000 Derivatives
ar
y
1 6 / 3 2 - B i t S i n g l e -C h i p M i c r o c o n t r o l l e r w i t h
32-Bit Performance
P
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li
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V o l u m e 1 ( o f 2 ) : S y s t e m U n i ts
M i c r o c o n t r o l l e rs
Edition 2007-06
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
U s e r ’ s Ma n u a l , V 1 . 0 , J u n e 2 0 0 7
XC2000 Derivatives
ar
y
1 6 / 3 2 - B i t S i n g l e -C h i p M i c r o c o n t r o l l e r w i t h
32-Bit Performance
P
re
li
m
in
V o l u m e 1 ( o f 2 ) : S y s t e m U n i ts
M i c r o c o n t r o l l e rs
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
XC2xxx
Revision History: V1.0, 2007-06
Previous Version(s):
V0.1, 2007-03, Draft version
Page
Subjects (major changes since last revision)
1-2
More derivatives added to list
Description of SSC and CAN bootstrap loaders added
9-1ff
EBC chapter corrected
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User’s Manual
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Summary Of Chapters
Summary Of Chapters
This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For
a quick overview this table of chapters summarizes both volumes, so you immediately
can find the reference to the desired section in the corresponding document ([1] or [2]).
Summary Of Chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-1 [1]
Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-3 [1]
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]
2
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1]
3
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1]
4
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1]
5
Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1]
6
System Control Unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 [1]
7
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1]
8
Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1]
9
The External Bus Controller EBC . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]
10
Startup Configuration and Bootstrap Loading . . . . . . . . . . . . . . . 10-1 [1]
11
Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]
12
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1]
13
Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1]
14
The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [2]
15
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [2]
16
Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2]
17
Capture/Compare Unit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [2]
18
Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 [2]
19
Universal Serial Interface Channel . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2]
20
Controller Area Network (MultiCAN) Controller . . . . . . . . . . . . . . 20-1 [2]
Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]
Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 [2]
User’s Manual
L-1
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
User’s Manual
Summary Of Chapters
L-2
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table Of Contents
Table Of Contents
This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For
your convenience this table of contents (and also the keyword and register index) lists
both volumes, so you can immediately find the reference to the desired section in the
corresponding document ([1] or [2]).
Summary Of Chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-1 [1]
Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-3 [1]
1
1.1
1.2
1.3
1.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]
Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . 1-3 [1]
Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 [1]
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 [1]
Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 [1]
2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.2
2.3
2.4
2.5
2.6
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1]
Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . 2-2 [1]
High Instruction Bandwidth/Fast Execution . . . . . . . . . . . . . . . . . . . 2-4 [1]
Powerful Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 [1]
High Performance Branch-, Call-, and Loop-Processing . . . . . . . . . 2-6 [1]
Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . 2-7 [1]
Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . 2-8 [1]
Interfaces to System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 [1]
On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 [1]
On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 [1]
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1]
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 [1]
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 [1]
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.5
3.6
3.7
3.8
3.9
3.9.1
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1]
Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1]
Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1]
Data Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 [1]
Program Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 [1]
Program/Data SRAM (PSRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 [1]
Non-Volatile Program Memory (Flash) . . . . . . . . . . . . . . . . . . . . . 3-13 [1]
System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 [1]
IO Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 [1]
External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 [1]
Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 [1]
Embedded Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1]
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1]
User’s Manual
L-3
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table Of Contents
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.10
3.10.1
3.10.2
3.10.3
3.10.4
3.11
3.11.1
3.11.2
3.11.3
3.12
3.12.1
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Details of Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Handling Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Handling Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Program Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Startup, Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Reporting Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Retention Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stand-By RAM Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stand-By RAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marker Memory (MKMEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Parity Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.5.1
4.5.2
4.6
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1]
Components of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 [1]
Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . 4-5 [1]
Branch Detection and Branch Prediction Rules . . . . . . . . . . . . . . . . 4-7 [1]
Correctly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1]
Incorrectly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . 4-9 [1]
Instruction Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 [1]
Pipeline Conflicts Using General Purpose Registers . . . . . . . . . . . 4-13 [1]
Pipeline Conflicts Using Indirect Addressing Modes . . . . . . . . . . . 4-15 [1]
Pipeline Conflicts Due to Memory Bandwidth . . . . . . . . . . . . . . . . 4-17 [1]
Pipeline Conflicts Caused by CPU-SFR Updates . . . . . . . . . . . . . 4-20 [1]
CPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 [1]
Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 [1]
GPR Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 [1]
Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 [1]
Code Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 [1]
Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1]
Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1]
Long Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 [1]
Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 [1]
DSP Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46 [1]
The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 [1]
Standard Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56 [1]
User’s Manual
L-4
3-20 [1]
3-22 [1]
3-25 [1]
3-35 [1]
3-38 [1]
3-45 [1]
3-47 [1]
3-49 [1]
3-50 [1]
3-50 [1]
3-52 [1]
3-67 [1]
3-69 [1]
3-70 [1]
3-71 [1]
3-72 [1]
3-76 [1]
3-77 [1]
3-78 [1]
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table Of Contents
4.8.1
4.8.2
4.8.3
4.9
4.9.1
4.9.2
4.9.3
4.9.4
4.9.5
4.9.6
4.9.7
4.9.8
4.9.9
4.9.10
4.9.11
4.10
16-bit Adder/Subtracter, Barrel Shifter, and 16-bit Logic Unit . . . .
Bit Manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Data Processing (MAC Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAC Unit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representation of Numbers and Rounding . . . . . . . . . . . . . . . . . .
The 16-bit by 16-bit Signed/Unsigned Multiplier and Scaler . . . . .
Concatenation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
One-bit Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The 40-bit Adder/Subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Data Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The 40-bit Signed Accumulator Register . . . . . . . . . . . . . . . . . . . .
The MAC Unit Status Word MSW . . . . . . . . . . . . . . . . . . . . . . . . .
The Repeat Counter MRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Constant Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.5
5.6
5.7
5.8
5.9
5.10
5.11
Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1]
Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 [1]
Interrupt Arbitration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 [1]
Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 [1]
Operation of the Peripheral Event Controller Channels . . . . . . . . . . 5-19 [1]
The PECC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 [1]
The PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . 5-23 [1]
PEC Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 [1]
Channel Link Mode for Data Chaining . . . . . . . . . . . . . . . . . . . . . . 5-27 [1]
PEC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 [1]
Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . 5-30 [1]
Context Switching and Saving Status . . . . . . . . . . . . . . . . . . . . . . . . 5-32 [1]
Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 [1]
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 [1]
OCDS Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 [1]
Service Request Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 [1]
Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 [1]
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2
System Control Unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 [1]
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 [1]
Wake-Up Clock Circuit (OSC_WU) . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]
High Precision Oscillator Circuit (OSC_HP) . . . . . . . . . . . . . . . . . . 6-3 [1]
Phase-Locked Loop (PLL) Module . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 [1]
Clock Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 [1]
External Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 [1]
CGU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 [1]
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 [1]
User’s Manual
L-5
4-60 [1]
4-60 [1]
4-62 [1]
4-64 [1]
4-65 [1]
4-65 [1]
4-66 [1]
4-66 [1]
4-66 [1]
4-66 [1]
4-67 [1]
4-67 [1]
4-68 [1]
4-70 [1]
4-72 [1]
4-74 [1]
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.3
6.3.1
6.3.2
6.3.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.6
6.6.1
6.6.2
6.7
6.7.1
6.8
6.8.1
6.8.2
6.8.3
6.8.4
6.9
6.9.1
Table Of Contents
Reset Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 [1]
General Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 [1]
Coupling of Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 [1]
Debug Reset Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1]
Example1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1]
Example2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1]
Example3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1]
Reset Request Trigger Sources . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1]
Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 [1]
Reset Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 [1]
External Service Request (ESR) Pins . . . . . . . . . . . . . . . . . . . . . . . . 6-52 [1]
General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 [1]
ESR Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58 [1]
ESR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63 [1]
External Request Unit (ERU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64 [1]
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64 [1]
ERU Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 [1]
External Request Select Unit (ERSx; x = 0..3) . . . . . . . . . . . . . . . 6-72 [1]
Event Trigger Logic (ETLx; x = 0..3) . . . . . . . . . . . . . . . . . . . . . . . 6-74 [1]
Connecting Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 [1]
Output Gating Unit (OGUy; y = 0..3) . . . . . . . . . . . . . . . . . . . . . . . 6-77 [1]
ERU Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81 [1]
ERU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83 [1]
Power Supply and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-90 [1]
Supply Watchdog (SWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91 [1]
Monitoring the Voltage Level of a Core Domain . . . . . . . . . . . . . . 6-97 [1]
Controlling the Voltage Level of a Core Domain . . . . . . . . . . . . . 6-115 [1]
Handling the Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-126 [1]
Power State Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-128 [1]
Operating a Power Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-130 [1]
Power Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-134 [1]
Global State Controller (GSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-156 [1]
GSC Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-156 [1]
GSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-160 [1]
Temperature Compensation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 6-165 [1]
Temperature Compensation Registers . . . . . . . . . . . . . . . . . . . . 6-166 [1]
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-168 [1]
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-168 [1]
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-168 [1]
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-169 [1]
WDT Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-173 [1]
Wake-up Timer (WUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-176 [1]
Wake-Up Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-177 [1]
User’s Manual
L-6
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table Of Contents
6.9.2
6.10
6.10.1
6.10.2
6.10.3
6.11
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
6.11.6
6.11.7
6.12
6.13
WUT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous System Control Registers . . . . . . . . . . . . . . . . . .
SCU Interrupt and Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . .
SCU Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCU Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . .
SCU Trap Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCU Trap Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPM_M Interrupt and Trap Support . . . . . . . . . . . . . . . . . . . . . .
DPM_M Interrupt and Trap Registers . . . . . . . . . . . . . . . . . . . . .
Alternate Interrupt Assignment Register . . . . . . . . . . . . . . . . . . .
Identification Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCU Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.2.1
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.3.14
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1]
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1]
Basic Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1]
Input Stage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 [1]
Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 [1]
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 [1]
Description Scheme for the Port IO Functions . . . . . . . . . . . . . . . . 7-6 [1]
Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 [1]
Port Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 [1]
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 [1]
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 [1]
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 [1]
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 [1]
Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 [1]
Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 [1]
Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43 [1]
Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 [1]
Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 [1]
Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52 [1]
Port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-55 [1]
Port 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-62 [1]
Port 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65 [1]
8
Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1]
9
9.1
9.2
The External Bus Controller EBC . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]
External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 [1]
Timing Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]
User’s Manual
L-7
6-178 [1]
6-181 [1]
6-181 [1]
6-183 [1]
6-185 [1]
6-186 [1]
6-187 [1]
6-189 [1]
6-200 [1]
6-202 [1]
6-210 [1]
6-211 [1]
6-216 [1]
6-218 [1]
6-220 [1]
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table Of Contents
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10
9.4
9.5
Basic Bus Cycle Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]
Bus Cycle Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
Bus Cycle Examples: Fastest Access Cycles . . . . . . . . . . . . . . . . . 9-9 [1]
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 [1]
Configuration Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 [1]
The EBC Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 [1]
The EBC Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 [1]
The Timing Configuration Registers TCONCSx . . . . . . . . . . . . . . 9-16 [1]
The Function Configuration Registers FCONCSx . . . . . . . . . . . . . 9-19 [1]
The Address Window Selection Registers ADDRSELx . . . . . . . . . 9-22 [1]
Ready Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 [1]
Access Control to LXBus Modules . . . . . . . . . . . . . . . . . . . . . . . . 9-27 [1]
External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 [1]
Shutdown Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32 [1]
LXBus Access Control and Signal Generation . . . . . . . . . . . . . . . . . 9-33 [1]
EBC Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 [1]
10
10.1
10.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
Startup Configuration and Bootstrap Loading . . . . . . . . . . . . . . . 10-1 [1]
Start-Up Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 [1]
Internal Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]
External Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]
Bootstrap Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1]
General Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1]
Standard UART Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 [1]
Synchronous Serial Channel Bootstrap Loader . . . . . . . . . . . . . . 10-11 [1]
CAN Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 [1]
Summary of Bootstrap Loader Modes . . . . . . . . . . . . . . . . . . . . . 10-17 [1]
11
11.1
11.1.1
11.2
11.2.1
11.2.2
11.3
11.3.1
Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routing of Debug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cerberus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1]
13
Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1]
14
14.1
14.1.1
14.1.2
The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPT1 Core Timer T3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPT1 Core Timer T3 Operating Modes . . . . . . . . . . . . . . . . . . . . .
User’s Manual
L-8
11-1 [1]
11-2 [1]
11-3 [1]
11-5 [1]
11-7 [1]
11-8 [1]
11-9 [1]
11-9 [1]
14-1 [2]
14-2 [2]
14-4 [2]
14-8 [2]
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table Of Contents
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
14.2.7
14.2.8
14.2.9
14.3
GPT1 Auxiliary Timers T2/T4 Control . . . . . . . . . . . . . . . . . . . . .
GPT1 Auxiliary Timers T2/T4 Operating Modes . . . . . . . . . . . . .
GPT1 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPT1 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . .
Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPT2 Core Timer T6 Control . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPT2 Core Timer T6 Operating Modes . . . . . . . . . . . . . . . . . . . .
GPT2 Auxiliary Timer T5 Control . . . . . . . . . . . . . . . . . . . . . . . .
GPT2 Auxiliary Timer T5 Operating Modes . . . . . . . . . . . . . . . . .
GPT2 Register CAPREL Operating Modes . . . . . . . . . . . . . . . . .
GPT2 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPT2 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . .
KSCCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfaces of the GPT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [2]
Defining the RTC Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 [2]
RTC Run Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 [2]
RTC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 [2]
48-bit Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [2]
System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [2]
Cyclic Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 [2]
RTC Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 [2]
KSCCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 [2]
16
16.1
16.1.1
16.1.2
16.1.3
16.1.4
16.1.5
16.1.6
16.1.7
16.1.8
16.1.9
16.2
16.2.1
16.2.2
16.2.3
16.2.4
16.2.5
Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2]
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2]
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 [2]
Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2]
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 [2]
ADC Kernel Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 [2]
Conversion Request Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 [2]
Conversion Result Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 [2]
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 [2]
Electrical Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 [2]
Transfer Characteristics and Error Definitions . . . . . . . . . . . . . . . 16-14 [2]
Operating the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 [2]
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 [2]
Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 [2]
Module Activation and Power Saving Modes . . . . . . . . . . . . . . . 16-22 [2]
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 [2]
General ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 [2]
User’s Manual
L-9
14-15 [2]
14-18 [2]
14-27 [2]
14-30 [2]
14-31 [2]
14-32 [2]
14-34 [2]
14-38 [2]
14-41 [2]
14-44 [2]
14-48 [2]
14-53 [2]
14-56 [2]
14-57 [2]
14-58 [2]
14-60 [2]
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table Of Contents
16.2.6
16.2.7
16.2.8
16.2.9
16.2.10
16.2.11
16.2.12
16.2.13
16.2.14
16.2.15
16.2.16
16.2.17
16.2.18
16.3
16.3.1
16.3.2
16.3.3
16.3.4
Request Source Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33 [2]
Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-37 [2]
Scan Request Source Handling . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39 [2]
Scan Request Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . 16-43 [2]
Sequential Request Source Handling . . . . . . . . . . . . . . . . . . . . . 16-47 [2]
Sequential Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-52 [2]
Channel-Related Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-63 [2]
Channel-Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-68 [2]
Conversion Result Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-78 [2]
Conversion Result-Related Registers . . . . . . . . . . . . . . . . . . . . . 16-86 [2]
External Multiplexer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-96 [2]
Synchronized Conversions for Parallel Sampling . . . . . . . . . . . . 16-98 [2]
Additional Feature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-102 [2]
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-105 [2]
Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-105 [2]
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-105 [2]
Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-106 [2]
Digital Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-109 [2]
17
17.1
17.2
17.3
17.3.1
17.4
17.5
17.5.1
17.5.2
17.5.3
17.5.4
17.5.5
17.6
17.7
17.8
17.9
17.10
17.10.1
17.11
Capture/Compare Unit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [2]
The CAPCOM2 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [2]
CAPCOM2 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [2]
Capture/Compare Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 [2]
Capture/Compare Registers for the CAPCOM2 (CC31 … CC16) 17-11 [2]
Capture Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 [2]
Compare Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2]
Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 [2]
Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 [2]
Compare Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 [2]
Compare Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 [2]
Double-Register Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . 17-24 [2]
Compare Output Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . 17-27 [2]
Single Event Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 [2]
Staggered and Non-Staggered Operation . . . . . . . . . . . . . . . . . . . . 17-31 [2]
CAPCOM2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36 [2]
External Input Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . 17-38 [2]
KSCCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39 [2]
Interfaces of the CAPCOM Units . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41 [2]
18
18.1
18.1.1
18.1.2
18.1.3
Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User’s Manual
L-10
18-1 [2]
18-1 [2]
18-2 [2]
18-3 [2]
18-4 [2]
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table Of Contents
18.2
18.2.1
18.2.2
18.2.3
18.2.4
18.2.5
18.2.6
18.2.7
18.2.8
18.2.9
18.3
18.3.1
18.3.2
18.3.3
18.3.4
18.3.5
18.3.6
18.4
18.5
18.6
18.6.1
18.6.2
18.6.3
18.6.4
18.7
18.7.1
18.7.2
18.7.3
18.7.4
18.8
18.8.1
18.8.2
18.9
18.9.1
18.9.2
18.9.3
18.10
18.10.1
18.10.2
18.10.3
18.10.4
Operating Timer T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 [2]
T12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 [2]
T12 Counting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 [2]
T12 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 [2]
Compare Mode Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 [2]
T12 Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 [2]
T12 Shadow Register Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 18-31 [2]
Timer T12 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . 18-32 [2]
T12 related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33 [2]
Capture/Compare Control Registers . . . . . . . . . . . . . . . . . . . . . . 18-38 [2]
Operating Timer T13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50 [2]
T13 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50 [2]
T13 Counting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-53 [2]
T13 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-58 [2]
Compare Mode Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-60 [2]
T13 Shadow Register Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61 [2]
T13 related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-63 [2]
Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-66 [2]
Multi-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-68 [2]
Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-70 [2]
Hall Pattern Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-71 [2]
Hall Pattern Compare Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-73 [2]
Hall Mode Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-74 [2]
Hall Mode for Brushless DC-Motor Control . . . . . . . . . . . . . . . . . 18-76 [2]
Modulation Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-78 [2]
Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-78 [2]
Trap Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-80 [2]
Passive State Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-83 [2]
Multi-Channel Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 18-84 [2]
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-89 [2]
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-89 [2]
Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-91 [2]
General Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-103 [2]
Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-103 [2]
Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-106 [2]
General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-107 [2]
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-115 [2]
Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-115 [2]
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-116 [2]
Synchronous Start Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-117 [2]
Digital Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-118 [2]
19
Universal Serial Interface Channel . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2]
User’s Manual
L-11
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
19.1
19.1.1
19.1.2
19.1.3
19.1.4
19.1.5
19.1.6
19.1.7
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.2.5
19.2.6
19.2.7
19.2.8
19.2.9
19.2.10
19.2.11
19.2.12
19.2.13
19.2.14
19.3
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.4
19.4.1
19.4.2
19.4.3
19.4.4
19.4.5
19.4.6
19.5
19.5.1
19.5.2
19.5.3
19.5.4
19.5.5
19.6
Table Of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2]
Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 [2]
Channel Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 [2]
Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 [2]
Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 [2]
Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 [2]
Channel Events and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 [2]
Data Shifting and Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 [2]
Operating the USIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 [2]
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 [2]
Operating the USIC Communication Channel . . . . . . . . . . . . . . . 19-17 [2]
Channel Control and Configuration Registers . . . . . . . . . . . . . . . 19-28 [2]
Protocol Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37 [2]
Operating the Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40 [2]
Input Stage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-42 [2]
Operating the Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . 19-44 [2]
Baud Rate Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . 19-49 [2]
Operating the Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . 19-54 [2]
Operating the Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . 19-58 [2]
Transfer Control and Status Registers . . . . . . . . . . . . . . . . . . . . 19-60 [2]
Data Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-72 [2]
Operating the FIFO Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 19-82 [2]
FIFO Buffer and Bypass Registers . . . . . . . . . . . . . . . . . . . . . . . 19-91 [2]
Asynchronous Serial Channel (ASC = UART) . . . . . . . . . . . . . . . . 19-112 [2]
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-112 [2]
Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-113 [2]
Operating the ASC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-116 [2]
ASC Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-124 [2]
Hardware LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-129 [2]
Synchronous Serial Channel (SSC) . . . . . . . . . . . . . . . . . . . . . . . 19-130 [2]
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-130 [2]
Operating the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-138 [2]
Operating the SSC in Master Mode . . . . . . . . . . . . . . . . . . . . . . 19-141 [2]
Operating the SSC in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . 19-148 [2]
SSC Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-150 [2]
SSC Timing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-154 [2]
Inter-IC Bus Protocol (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-158 [2]
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-158 [2]
Operating the IIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-162 [2]
Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-168 [2]
Data Flow Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-171 [2]
IIC Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-176 [2]
IIS Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-181 [2]
User’s Manual
L-12
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table Of Contents
19.6.1
19.6.2
19.6.3
19.6.4
19.6.5
19.7
19.7.1
19.7.2
19.7.3
19.7.4
19.7.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating the IIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating the IIS in Master Mode . . . . . . . . . . . . . . . . . . . . . . .
Operating the IIS in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . .
IIS Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USIC Implementation in XC2000 . . . . . . . . . . . . . . . . . . . . . . . . . .
Implementation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19-181 [2]
19-185 [2]
19-190 [2]
19-194 [2]
19-195 [2]
19-199 [2]
19-199 [2]
19-200 [2]
19-200 [2]
19-201 [2]
19-203 [2]
20
20.1
20.1.1
20.1.2
20.2
20.2.1
20.2.2
20.2.3
20.2.4
20.2.5
20.2.6
20.2.7
20.2.8
20.2.9
20.2.10
20.2.11
20.2.12
20.3
20.3.1
20.3.2
20.3.3
20.3.4
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.4.6
20.4.7
Controller Area Network (MultiCAN) Controller . . . . . . . . . . . . . . 20-1 [2]
MultiCAN Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2]
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2]
CAN Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 [2]
CAN Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 [2]
Conventions and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 [2]
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 [2]
CAN Node Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 [2]
Message Object List Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 [2]
CAN Node Analysis Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 [2]
Message Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 [2]
Message Postprocessing Interface . . . . . . . . . . . . . . . . . . . . . . . 20-25 [2]
Message Object Data Handling . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29 [2]
Message Object Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-36 [2]
MultiCAN Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45 [2]
CAN Node Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-62 [2]
Message Object Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-79 [2]
General Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-102 [2]
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-102 [2]
Port Input Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-103 [2]
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-104 [2]
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-105 [2]
MultiCAN Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 20-106 [2]
Interfaces of the CAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . 20-106 [2]
Module Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-107 [2]
Mode Control Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-116 [2]
Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-117 [2]
Mode Control Register Description . . . . . . . . . . . . . . . . . . . . . . 20-119 [2]
Connection of External Signals . . . . . . . . . . . . . . . . . . . . . . . . . 20-122 [2]
MultiCAN Module Register Address Map . . . . . . . . . . . . . . . . . 20-125 [2]
Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]
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Table Of Contents
Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 [2]
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1
Introduction
Introduction
The rapidly growing area of embedded control applications is representing one of the
most time-critical operating environments for today’s microcontrollers. Complex control
algorithms have to be processed based on a large number of digital as well as analog
input signals, and the appropriate output signals must be generated within a defined
maximum response time. Embedded control applications also are often sensitive to
board space, power consumption, and overall system cost.
Embedded control applications therefore require microcontrollers, which:
• offer a high level of system integration
• eliminate the need for additional peripheral devices and the associated software
overhead
• provide system security and fail-safe mechanisms
• provide effective means to control (and reduce) the device’s power consumption
The increasing complexity of embedded control applications requires microcontrollers
for new high-end embedded control systems to possess a significant increase in CPU
performance and peripheral functionality over conventional 8-bit controllers. To achieve
this high performance goal Infineon has decided to develop its families of 16-bit CMOS
microcontrollers without the constraints of backward compatibility.
Nonetheless the architectures of the 16-bit microcontroller families pursue successful
hardware and software concepts, which have been established in Infineon’s popular
8-bit controller families.
This established functionality, which has been the basis for system solutions in a wide
range of application areas, is amended with flexible peripheral modules and effective
power control features. The sum of this provides the prerequisites for powerful, yet
efficient systems-on-chip.
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About this Manual
This manual describes the functionality of a number of 16-bit microcontrollers of the
Infineon XC2000 Family.
These microcontrollers provide identical functionality to a large extent, but each device
type has specific unique features as indicated here.
The descriptions in this manual cover a superset of the provided features and refer to the
following derivatives:
Table 1-1
XC2000 Derivative Synopsis
Derivative1)
Package
CCU6 Mod. ADC2) Chan.
Interfaces
XC2287-xxF66L
LQFP-144
0, 1, 2, 3
16 + 8
5 CAN Nodes,
6 Serial Channels
XC2286-xxF66L
LQFP-144
0, 1
16 + 8
3 CAN Nodes,
6 Serial Channels
XC2285-xxF66L
LQFP-144
0, 1
12
2 CAN Nodes,
4 Serial Channels
XC2267-xxF66L
LQFP-100
0, 1, 2, 3
8+8
5 CAN Nodes,
6 Serial Channels
XC2264-xxF66L
LQFP-100
0, 1
8
2 CAN Nodes,
4 Serial Channels
XC2387-xxF66L
LQFP-144
0, 1
16 + 8
3 CAN Nodes,
6 Serial Channels
XC2365-xxF66L
LQFP-100
0, 1
11 + 5
3 CAN Nodes,
6 Serial Channels
1)
The derivatives are available with various memory sizes. For details, please refer to the corresponding Data
Sheets.
2)
Analog input channels are listed for each Analog/Digital Converter module separately.
This manual is valid for these derivatives and describes all variations of the different
available temperature ranges and packages.
For simplicity, these various device types are referred to by the collective term XC2000
throughout this manual. The complete pro-electron conforming designations are listed in
the respective Data Sheets.
Some sections of this manual do not refer to all of the XC2000 derivatives which are
currently available or planned (such as devices with different types of on-chip memory
or peripherals). These sections contain respective notes wherever possible.
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1.1
Introduction
Members of the 16-bit Microcontroller Family
The microcontrollers in the Infineon 16-bit family have been designed to meet the high
performance requirements of real-time embedded control applications. The architecture
of this family has been optimized for high instruction throughput and minimized response
time to external stimuli (interrupts). Intelligent peripheral subsystems have been
integrated to reduce the need for CPU intervention to a minimum extent. This also
minimizes the need for communication via the external bus interface. The high flexibility
of this architecture allows to serve the diverse and varying needs of different application
areas such as automotive, industrial control, or data communications.
The core of the 16-bit family has been developed with a modular family concept in mind.
All family members execute an efficient control-optimized instruction set (additional
instructions for members of the second generation). This allows easy and quick
implementation of new family members with different internal memory sizes and
technologies, different sets of on-chip peripherals, and/or different numbers of IO pins.
The XBUS/LXBus concept (internal representation of the external bus interface)
provides a straightforward path for building application-specific derivatives by integrating
application-specific peripheral modules with the standard on-chip peripherals.
As programs for embedded control applications become larger, high level languages are
favored by programmers, because high level language programs are easier to write, to
debug and to maintain. The C166 Family supports this starting with its 2nd generation.
The 80C166-type microcontrollers were the first generation of the 16-bit controller
family. These devices established the C166 architecture.
The C165-type and C167-type devices are members of the second generation of this
family. This second generation is even more powerful due to additional instructions for
HLL support, an increased address space, increased internal RAM, and highly efficient
management of various resources on the external bus.
Enhanced derivatives of this second generation provide more features such as
additional internal high-speed RAM, an integrated CAN-Module, an on-chip PLL, etc.
The design of more efficient systems may require the integration of application-specific
peripherals to boost system performance while minimizing the part count. These efforts
are supported by the XBUS, defined for the Infineon 16-bit microcontrollers (second
generation). The XBUS is an internal representation of the external bus interface which
opens and simplifies the integration of peripherals by standardizing the required
interface. One representative taking advantage of this technology is the integrated CAN
module.
The C165-type devices are reduced functionality versions of the C167 because they do
not have the A/D converter, the CAPCOM units, and the PWM module. This results in a
smaller package, reduced power consumption, and design savings.
The C164-type devices, the C167CS derivatives, and some of the C161-type devices
are further enhanced by a flexible power management and form the third generation of
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the 16-bit controller family. This power management mechanism provides an effective
means to control the power that is consumed in a certain state of the controller and thus
minimizes the overall power consumption for a given application.
The XC16x derivatives represent the fourth generation of the 16-bit controller family.
The XC166 Family dramatically increases the performance of 16-bit microcontrollers by
several major improvements and additions. The MAC-unit adds DSP-functionality to
handle digital filter algorithms and greatly reduces the execution time of multiplications
and divisions. The 5-stage pipeline, single-cycle execution of most instructions, and
PEC-transfers within the complete addressing range increase system performance.
Debugging the target system is supported by integrated functions for On-Chip Debug
Support (OCDS).
The present XC2000 Family of microcontrollers builds the fifth generation of 16-bit
microcontrollers which provides 32-bit performance and takes users and applications a
considerable step towards industry’s target of systems on chip. Integrated memories and
peripherals allow compact systems, the integrated core power supply and control
reduces system requirements to one single voltage supply, the powerful combination of
CPU and MAC-unit is unleashed by optimized compilers. This leaves no performance
gap towards 32-bit systems.
A variety of different versions is provided which offer various kinds of on-chip program
memory1):
•
•
•
•
Mask-programmable ROM
Flash memory
OTP memory
ROMless without non-volatile memory.
Also there are devices with specific functional units.
The devices may be offered in different packages, temperature ranges and speed
classes.
Additional standard and application-specific derivatives are planned and are in
development.
Note: Not all derivatives will be offered in all temperature ranges, speed classes,
packages, or program memory variations.
Information about specific versions and derivatives will be made available with the
devices themselves. Contact your Infineon representative for up-to-date material or refer
to http://www.infineon.com/microcontrollers.
Note: As the architecture and the basic features, such as the CPU core and built-in
peripherals, are identical for most of the currently offered versions of the XC2000,
descriptions within this manual that refer to the “XC2000” also apply to the other
variations, unless otherwise noted.
1)
Not all derivatives are offered with all kinds of on-chip memory.
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1.2
Introduction
Summary of Basic Features
The XC2000 devices are enhanced members of the Infineon family of full featured 16-bit
single-chip CMOS microcontrollers. The XC2000 combines the extended functionality
and performance of the C166SV2 Core with powerful on-chip peripheral subsystems
and on-chip memory units and provides several means for power reduction.
The following key features contribute to the high performance of the XC2000:
High Performance 16-bit CPU with Five-Stage Pipeline and MAC Unit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single clock cycle instruction execution
1 cycle minimum instruction cycle time (most instructions)
1 cycle multiplication (16-bit × 16-bit
4 + 17 cycles division (32-bit / 16-bit), 4 cycles delay, 17 cycles background execution
1 cycle multiply and accumulate instruction (MAC) execution
Automatic saturation or rounding included
Multiple high bandwidth internal data buses
Register-based design with multiple, variable register banks
Two additional fast register banks
Fast context switching support
16 Mbytes of linear address space for code and data (von Neumann architecture)
System stack cache support with automatic stack overflow/underflow detection
High performance branch, call, and loop processing
Zero-cycle jump execution
Control Oriented Instruction Set with High Efficiency
• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral
control and user-defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data access
Power Management Features
• Two IO power domains fulfill system requirements from 3 V to 5 V
• Separately controllable core power domains support wake-up via external triggers or
on-chip timer while drastically reducing the power consumption
• Gated clock concept for improved power consumption and EMC
• Programmable system slowdown via clock generation unit
• Flexible management of peripherals, can be individually disabled
• Programmable frequency output
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Integrated On-Chip Memories
•
•
•
•
•
1 Kbyte on-chip Stand-By RAM (SBRAM) for data to preserved during power-saving
2 Kbytes Dual-Port RAM (DPRAM) for variables, register banks, and stacks
16 Kbytes on-chip high-speed Data SRAM (DSRAM) for variables and stacks
Up to 64 Kbytes on-chip high-speed Program/Data SRAM (PSRAM) for code and data
Up to 764 Kbytes on-chip Flash Program Memory for instruction code or constant data
Note: The system stack can be located in any memory area within the complete
addressing range.
16-Priority-Level Interrupt System
•
•
•
•
•
96 interrupt nodes with separate interrupt vectors on 15 priority levels (8 group levels)
7 cycles minimum interrupt latency in case of internal program execution
Fast external interrupts
Programmable external interrupt source selection
Programmable vector table (start location and step-width)
8-Channel Peripheral Event Controller (PEC
• Interrupt driven single cycle data transfer
• Programmable PEC interrupt request level, (15 down to 8)
• Transfer count option
(standard CPU interrupt after programmable number of PEC transfers)
• Separate interrupt level for PEC termination interrupts selectable
• Overhead from saving and restoring system state for interrupt requests eliminated
• Full 24-bit addresses for source and destination pointers, supporting transfers within
the total address space
Intelligent On-Chip Peripheral Subsystems
• Two synchronizable A/D Converters with programmable resolution (10-bit or 8-bit)
and conversion time (down to approx. 1 µs), up to 24 analog input channels, auto scan
modes, channel injection, data reduction features
• One Capture/Compare Unit with 2 independent time bases,
very flexible PWM unit/event recording unit with different operating modes,
includes two 16-bit timers/counters, maximum resolution fSYS
• Up to Four Capture/Compare Units for flexible PWM Signal Generation (CCU6)
(3/6 Capture/Compare Channels and 1 Compare Channel)
• Two Multifunctional General Purpose Timer Units:
– GPT1: three 16-bit timers/counters, maximum resolution fSYS/4
– GPT2: two 16-bit timers/counters, maximum resolution fSYS/2
• Six Serial Channels with baud rate generator, receive/transmit FIFOs, programmable
data length and shift direction, usable as UART, SPI-like, IIC, IIS, and LIN interface
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• Controller Area Network (MultiCAN) Module, Rev. 2.0B active,
up to five nodes operating independently or exchanging data via a gateway function,
Full-CAN/Basic-CAN
• Real Time Clock with alarm interrupt
• Watchdog Timer with programmable time intervals
• Bootstrap Loader for flexible system initialization
• Protection management for system configuration and control registers
On-Chip Debug Support
•
•
•
•
•
•
•
•
On-chip debug controller and related interface to JTAG controller
JTAG interface and break interface
Hardware, software and external pin breakpoints
Up to 4 instruction pointer breakpoints
Debug event control, e.g. with monitor call or CPU halt or trigger of data transfer
Dedicated DEBUG instructions with control via JTAG interface
Access to any internal register or memory location via JTAG interface
Single step support and watchpoints with MOV-injection
Up to 118 IO Lines With Individual Bit Addressability
•
•
•
•
Tri-stated in input mode
Push/pull or open drain output mode
Programmable port driver control
Two I/O power domains with a supply voltage range from 3.0 V to 5.5 V
(core-logic and oscillator input voltage is 1.5 V)
Various Temperature Ranges
• -40 to +85 °C
• -40 to +125 °C1)
Infineon CMOS Process
• Low power CMOS technology enables power saving Idle, Sleep, and Power Down
modes with flexible power management.
Green Plastic Low-Profile Quad Flat Pack (LQFP) Packages
• PG-LQFP-144, 20 × 20 mm body, 0.5 mm (19.7 mil) lead spacing,
surface mount technology
• PG-LQFP-100, 14 × 14 mm body, 0.5 mm (19.7 mil) lead spacing,
surface mount technology
1)
Not all derivatives are offered in all temperature ranges.
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Complete Development Support
For the development tool support of its microcontrollers, Infineon follows a clear third
party concept. Currently around 120 tool suppliers world-wide, ranging from local niche
manufacturers to multinational companies with broad product portfolios, offer powerful
development tools for the Infineon C500, C800, XC800, C166, XC166, and TriCore
microcontroller families, guaranteeing a remarkable variety of price-performance
classes as well as early availability of high quality key tools such as compilers,
assemblers, simulators, debuggers or in-circuit emulators.
Infineon incorporates its strategic tool partners very early into the product development
process, making sure embedded system developers get reliable, well-tuned tool
solutions, which help them unleash the power of Infineon microcontrollers in the most
effective way and with the shortest possible learning curve.
The tool environment for the Infineon 16-bit microcontrollers includes the following tools:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Compilers (C/C++)
Macro-assemblers, linkers, locators, library managers, format-converters
Architectural simulators
HLL debuggers
Real-time operating systems
VHDL chip models
In-circuit emulators (based on bondout or standard chips)
Plug-in emulators
Emulation and clip-over adapters, production sockets
Logic analyzer disassemblers
Starter kits
Evaluation boards with monitor programs
Industrial boards (also for CAN, FUZZY, PROFIBUS, FORTH applications)
Low level driver software (CAN, PROFIBUS, LIN)
Chip configuration code generation tool (DAvE)
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1.3
Introduction
Abbreviations
The following acronyms and terms are used within this document:
ADC
Analog Digital Converter
ALE
Address Latch Enable
ALU
Arithmetic and Logic Unit
ASC
Asynchronous/synchronous Serial Channel
CAN
Controller Area Network (License Bosch)
CAPCOM
CAPture and COMpare unit
CISC
Complex Instruction Set Computing
CMOS
Complementary Metal Oxide Silicon
CPU
Central Processing Unit
DMU
Data Management Unit
EBC
External Bus Controller
ESFR
Extended Special Function Register
EVVR
Embedded Validated Voltage Regulator
Flash
Non-volatile memory that may be electrically erased
GPR
General Purpose Register
GPT
General Purpose Timer unit
HLL
High Level Language
IIC
Inter Integrated Circuit (Bus)
IIS
Inter Integrated Circuit Sound (Bus)
IO
Input/Output
JTAG
Joint Test Access Group
LIN
Local Interconnect Network
LQFP
Low Profile Quad Flat Pack
LXBus
Internal representation of the external bus
MAC
Multiply/Accumulate (unit)
OCDS
On-Chip Debug Support
OTP
One-Time Programmable memory
PEC
Peripheral Event Controller
PLA
Programmable Logic Array
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PLL
Phase Locked Loop
PMU
Program Management Unit
PVC
Power Validation Circuit
PWM
Pulse Width Modulation
RAM
Random Access Memory
RISC
Reduced Instruction Set Computing
ROM
Read Only Memory
RTC
Real Time Clock
SFR
Special Function Register
SSC
Synchronous Serial Channel
SWD
Supply Watchdog
UART
Universal Asynchronous Receiver/Transmitter
USIC
Universal Serial Interface Channel
1.4
Naming Conventions
The manifold bitfields used for control functions and status indication and the registers
housing them are equipped with unique names wherever applicable. Thereby these
control structures can be referred to by their names rather than by their location. This
makes the descriptions by far more comprehensible.
To describe regular structures (such as ports) indices are used instead of a plethora of
similar bit names, so bit 3 of port 5 is referred to as P5.3.
Where it helps to clarify the relation between several named structures, the next higher
level is added to the respective name to make it unambiguous.
The term ADC0_GLOBCTR clearly identifies register GLOBCTR as part of module
ADC0, the term SYSCON0.CLKSEL clearly identifies bitfield CLKSEL as part of register
SYSCON0.
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2
Architectural Overview
Architectural Overview
The architecture of the XC2000 core combines the advantages of both RISC and CISC
processors in a very well-balanced way. This computing and controlling power is
completed by the DSP-functionality of the MAC-unit. The XC2000 integrates this
powerful CPU core with a set of powerful peripheral units into one chip and connects
them very efficiently. On-chip memory blocks with dedicated buses and control units
store code and data. This combination of features results in a high performance
microcontroller, which is the right choice not only for today’s applications, but also for
future engineering challenges. One of the buses used concurrently on the XC2000 is the
LXBus, an internal representation of the external bus interface. This bus provides a
standardized method for integrating additional application-specific peripherals into
derivatives of the standard XC2000.
DPRAM
2 Kbytes
DSRAM
16 Kbytes
OCDS
Debug Support
EBC
LXBus Control
External Bus
Control
CPU
DMU
Program Flash 1
256 Kbytes
PMU
IMB
Program Flash 0
256 Kbytes
C166SV2 - Core
XTAL
Program Flash 2
256 Kbytes
WDT
Oscillators/PLL, System Fct.
Clock, Reset, Power Control,
Stand-By RAM
Interrupt & PEC
RTC
LXBus
PSRAM
64 Kbytes
ADC
ADC
8-Bit/
8-Bit/
10-Bit 10-Bit
8 Ch. 16 Ch.
GPT
...
CC2
CCU63
CCU60
T7
T12
T12
T8
T13
T13
T2
T3
T4
Peripheral
Data Bus
Interrupt Bus
USIC2 USIC1 USIC0
2 Ch., 2 Ch., 2 Ch.,
64 x
64 x
64 x
Buffer Buffer Buffer
M ulti
CAN
RS232, RS232, RS232,
LIN,
LIN,
LIN,
5 ch.
SPI,
SPI,
SPI,
IIC, IIS IIC, IIS IIC, IIS
T5
T6
BRGen
P15
Port 5
P11
8
16
6
P10
16
P9
P8
8
P7 P6
7
5
P4
4
P3
8
P2
8
P1
13
8
P0
8
MC_XC2X_BLOCKDIAGRAM
Figure 2-1
XC2000 Functional Block Diagram
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2.1
Architectural Overview
Basic CPU Concepts and Optimizations
The main core of the CPU consists of a set of optimized functional units including the
instruction fetch/processing pipelines, a 16-bit Arithmetic and Logic Unit (ALU), a 40-bit
Multiply and Accumulate Unit (MAC), an Address and Data Unit (ADU), an Instruction
Fetch Unit (IFU), a Register File (RF), and dedicated Special Function Registers (SFRs).
Single clock cycle execution of instructions results in superior CPU performance, while
maintaining C166 code compatibility. Impressive DSP performance, concurrent access
to different kinds of memories and peripherals boost the overall system performance.
PSRAM
Flash/ROM
PMU
CPU
Prefetch
Unit
Branch
Unit
CSP
IP
VECSEG
CPUCON1
CPUCON2
Return
Stack
FIFO
IDX0
IDX1
QX0
QX1
QR0
QR1
+/-
+/-
Multiply
Unit
MRW
+/-
MCW
MSW
MAH
MAL
2-Stage
Prefetch
Pipeline
TFR
Injection/
Exception
Handler
5-Stage
Pipeline
IFU
DPP0
DPP1
DPP2
DPP3
DPRAM
IPIP
SPSEG
SP
STKOV
STKUN
ADU
Division Unit
Bit-Mask-Gen.
Multiply Unit
Barrel-Shifter
MDC
CP
R15
R15
R14
R15
R14
R14
R15
R14
GPRs
GPRs
GPRs
GPRs
R1
R1
R0
R0R1
R0
R1
R0
RF
PSW
+/-
MDH
MDL
ZEROS
ONES
MAC
Buffer
ALU
WB
DSRAM
EBC
Peripherals
DMU
mca04917_x.vsd
Figure 2-2
CPU Block Diagram
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Architectural Overview
Summary of CPU Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Opcode fully upward compatible with C166 Family
2-stage instruction fetch pipeline with FIFO for instruction pre-fetching
5-stage instruction execution pipeline
Pipeline forwarding controls data dependencies in hardware
Multiple high bandwidth buses for data and instructions
Linear address space for code and data (von Neumann architecture)
Nearly all instructions executed in one CPU clock cycle
Fast multiplication (16-bit × 16-bit) in one CPU clock cycle
Fast background execution of division (32-bit/16-bit) in 21 CPU clock cycles
Built-in advanced MAC (Multiply Accumulate) Unit:
– Single cycle MAC instruction with zero cycle latency including a 16 × 16 multiplier
– 40-bit barrel shifter and 40-bit accumulator to handle overflows
– Automatic saturation to 32 bits or rounding included with the MAC instruction
– Fractional numbers supported directly
– One Finite Impulse Response Filter (FIR) tap per cycle with no circular buffer
management
Enhanced boolean bit manipulation facilities
High performance branch-, call-, and loop-processing
Zero cycle jump execution
Register-based design with multiple variable register banks (byte or word operands)
Two additional fast register banks
Variable stack with automatic stack overflow/underflow detection
“Fast interrupt” and “Fast context switch” features
The high performance and flexibility of the CPU is achieved by a number of optimized
functional blocks (see Figure 2-2). Optimizations of the functional blocks are described
in detail in the following sections.
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2.1.1
Architectural Overview
High Instruction Bandwidth/Fast Execution
Based on the hardware provisions, most of the XC2000’s instructions can be executed
in just one clock cycle (1/fSYS). This includes arithmetic instructions, logic instructions,
and move instructions with most addressing modes.
Special instructions such as JMPS take more than one machine cycle. Divide
instructions are mainly executed in the background, so other instructions can be
executed in parallel. Due to the prediction mechanism (see Section 4.2), correctly
predicted branch instructions require only one cycle or can even be overlaid with another
instruction (zero-cycle jump).
The instruction cycle time is dramatically reduced through the use of instruction
pipelining. This technique allows the core CPU to process portions of multiple sequential
instruction stages in parallel. Up to seven stages can operate in parallel:
The two-stage instruction fetch pipeline fetches and preprocesses instructions from
the respective program memory:
PREFETCH: Instructions are prefetched from the PMU in the predicted order. The
instructions are preprocessed in the branch detection unit to detect branches. The
prediction logic determines if branches are assumed to be taken or not.
FETCH: The instruction pointer for the next instruction to be fetched is calculated
according to the branch prediction rules. The branch folding unit preprocesses detected
branches and combines them with the preceding instructions to enable zero-cycle
branch execution. Prefetched instructions are stored in the instruction FIFO, while stored
instructions are moved from the instruction FIFO to the instruction processing pipeline.
The five-stage instruction processing pipeline executes the respective instructions:
DECODE: The previously fetched instruction is decoded and the GPR used for indirect
addressing is read from the register file, if required.
ADDRESS: All operand addresses are calculated. For instructions implicitly accessing
the stack the stack pointer (SP) is decremented or incremented.
MEMORY: All required operands are fetched.
EXECUTE: The specified operation (ALU or MAC) is performed on the previously
fetched operands. The condition flags are updated. Explicit write operations to CPUSFRs are executed. GPRs used for indirect addressing are incremented or
decremented, if required.
WRITE BACK: The result operands are written to the specified locations. Operands
located in the DPRAM are stored via the write-back buffer.
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Architectural Overview
Powerful Execution Units
The 16-bit Arithmetic and Logic Unit (ALU) performs all standard (word) arithmetic
and logical operations. Additionally, for byte operations, signals are provided from bits 6
and 7 of the ALU result to set the condition flags correctly. Multiple precision arithmetic
is provided through a ‘CARRY-IN’ signal to the ALU from previously calculated portions
of the desired operation.
Most internal execution blocks have been optimized to perform operations on either 8-bit
or 16-bit quantities. Instructions have been provided as well to allow byte packing in
memory while providing sign extension of bytes for word wide arithmetic operations. The
internal bus structure also allows transfers of bytes or words to or from peripherals based
on the peripheral requirements.
A set of consistent flags is updated automatically in the PSW after each arithmetic,
logical, shift, or movement operation. These flags allow branching on specific conditions.
Support for both signed and unsigned arithmetic is provided through user-specifiable
branch tests. These flags are also preserved automatically by the CPU upon entry into
an interrupt or trap routine.
A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic
shifts are also supported.
The Multiply and Accumulate Unit (MAC) performs extended arithmetic operations
such as 32-bit addition, 32-bit subtraction, and single-cycle 16-bit × 16-bit multiplication.
The combined MAC operations (multiplication with cumulative addition/subtraction)
represent the major part of the DSP performance of the CPU.
The Address Data Unit (ADU) contains two independent arithmetic units to generate,
calculate, and update addresses for data accesses. The ADU performs the following
major tasks:
• The Standard Address Unit supports linear arithmetic for the short, long, and indirect
addressing modes. It also supports data paging and stack handling.
• The DSP Address Generation Unit contains an additional set of address pointers and
offset registers which are used in conjunction with the CoXXX instructions only.
The CPU provides a lot of powerful addressing modes for word, byte, and bit data
accesses (short, long, indirect). The different addressing modes use different formats
and have different scopes.
Dedicated bit processing instructions provide efficient control and testing of peripherals
while enhancing data manipulation. These instructions provide direct access to two
operands in the bit-addressable space without requiring them to be moved into
temporary flags. Logical instructions allow the user to compare and modify a control bit
for a peripheral in one instruction. Multiple bit shift instructions (single cycle execution)
avoid long instruction streams of single bit shift operations. Bitfield instructions allow the
modification of multiple bits from one operand in a single instruction.
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2.1.3
Architectural Overview
High Performance Branch-, Call-, and Loop-Processing
Pipelined execution delivers maximum performance with a stream of subsequent
instructions. Any disruption requires the pipeline to be refilled and the new instruction to
step through the pipeline stages. Due to the high percentage of branching in controller
applications, branch instructions have been optimized to require pipeline refilling only in
special cases. This is realized by detecting and preprocessing branch instructions in the
prefetch stage and by predicting the respective branch target address.
Prefetching then continues from the predicted target address. If the prediction was
correct subsequent instructions can be fed to the execution pipeline without a gap, even
if a branch is executed, i.e. the code execution is not linear. Branch target prediction (see
also Section 4.2.1) uses the following rules:
• Unconditional branches: Branch prediction is trivial in this case, as the branches will
always be taken and the target address is defined. This applies to implicitly
unconditional branches such as JMPS, CALLR, or RET as well as to branches with
condition code “unconditional” such as JMPI cc_UC.
• Fixed prediction: Branch instructions which are often used to realize loops are
assumed to be taken if they branch backward to a previous location (the begin of the
loop). This applies to conditional branches such as JMPR cc_XX or JNB.
• Variable prediction: In this case the respective prediction (taken or not taken) is
coded into the instruction and can, therefore, be selected for each individual branch
instruction. Thus, the software designer can optimize the instruction flow to the
specific code to be executed1). This applies to the branch instructions JMPA and
CALLA.
• Conditional indirect branches: These branches are always assumed to be not
taken. This applies to branch instructions JMPI cc_XX, [Rw] and CALLI cc_XX, [Rw].
The system state information is saved automatically on the internal system stack, thus
avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap
routines. Call instructions push the value of the IP on the system stack, and require the
same execution time as branch instructions. Additionally, instructions have been
provided to support indirect branch and call instructions. This feature supports
implementation of multiple CASE statement branching in assembler macros and high
level languages.
1)
The programming tools accept either dedicated mnemonics for each prediction leaving the choice up to
programmer, or they accept generic mnemonics and apply their own prediction rules.
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2.1.4
Architectural Overview
Consistent and Optimized Instruction Formats
To obtain optimum performance in a pipelined design, an instruction set has been
designed which incorporates concepts from Reduced Instruction Set Computing (RISC).
These concepts primarily allow fast decoding of the instructions and operands while
reducing pipeline holds. These concepts, however, do not preclude the use of complex
instructions required by microcontroller users. The instruction set was designed to meet
the following goals:
• Provide powerful instructions for frequently-performed operations which traditionally
have required sequences of instructions. Avoid transfer into and out of temporary
registers such as accumulators and carry bits. Perform tasks in parallel such as saving
state upon entry into interrupt routines or subroutines.
• Avoid complex encoding schemes by placing operands in consistent fields for each
instruction and avoid complex addressing modes which are not frequently used.
Consequently, the instruction decode time decreases and the development of
compilers and assemblers is simplified.
• Provide most frequently used instructions with one-word instruction formats. All other
instructions use two-word formats. This allows all instructions to be placed on word
boundaries: this alleviates the need for complex alignment hardware. It also has the
benefit of increasing the range for relative branching instructions.
The high performance of the CPU-hardware can be utilized efficiently by a programmer
by means of the highly functional XC2000 instruction set which includes the following
instruction classes:
•
•
•
•
•
•
•
•
•
•
•
•
•
Arithmetic Instructions
DSP Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
Possible operand types are bits, bytes, words, and doublewords. Specific instructions
support the conversion (extension) of bytes to words. Various direct, indirect, and
immediate addressing modes are provided to specify the required operands.
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2.1.5
Architectural Overview
Programmable Multiple Priority Interrupt System
The XC2000 provides 96 separate interrupt nodes that may be assigned to 16 priority
levels with 8 group priorities on each level. Most interrupt sources are connected to a
dedicated interrupt node. In some cases, multi-source interrupt nodes are incorporated
for efficient use of system resources. These nodes can be activated by several source
requests and are controlled via interrupt subnode control registers.
The following enhancements within the XC2000 allow processing of a large number of
interrupt sources:
• Peripheral Event Controller (PEC): This processor is used to off-load many interrupt
requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap
routines by performing single-cycle interrupt-driven byte or word data transfers
between any two locations with an optional increment of the PEC source pointer, the
destination pointer, or both. Only one cycle is ‘stolen’ from the current CPU activity to
perform a PEC service.
• Multiple Priority Interrupt Controller: This controller allows all interrupts to be assigned
any specified priority. Interrupts may also be grouped, which enables the user to
prevent similar priority tasks from interrupting each other. For each of the interrupt
nodes, there is a separate control register which contains an interrupt request flag, an
interrupt enable flag, and an interrupt priority bitfield. After being accepted by the CPU,
an interrupt service can be interrupted only by a higher prioritized service request. For
standard interrupt processing, each of the interrupt nodes has a dedicated vector
location.
• Multiple Register Banks: Two local register banks for immediate context switching add
to a relocatable global register bank. The user can specify several register banks
located anywhere in the internal DPRAM and made of up to sixteen general purpose
registers. A single instruction switches from one register bank to another (switching
banks flushes the pipeline, changing the global bank requires a validation sequence).
The XC2000 is capable of reacting very quickly to non-deterministic events because its
interrupt response time is within a very narrow range of typically 7 clock cycles (in the
case of internal program execution). Its fast external interrupt inputs are sampled every
clock cycle and allow even very short external signals to be recognized.
The XC2000 also provides an excellent mechanism to identify and process exceptions
or error conditions that arise during run-time, so called ‘Hardware Traps’. A hardware
trap causes an immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Unless another, higher prioritized, trap service is in progress, a hardware trap will
interrupt any current program execution. In turn, a hardware trap service can normally
not be interrupted by a standard or PEC interrupt.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
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2.1.6
Architectural Overview
Interfaces to System Resources
The CPU of the XC2000 interfaces to the system resources via several bus systems
which contribute to the overall performance by transferring data concurrently. This
avoids stalling the CPU because instructions or operands need to be transferred.
The Dual Port RAM (DPRAM) is directly coupled to the CPU because it houses the
global register banks. Transfers from/to these locations affect the performance and are,
therefore, carefully optimized.
The Program Management Unit (PMU) controls accesses to the on-chip program
memory blocks such as the ROM/Flash module and the Program/Data RAM (PSRAM)
and also fetches instructions from external memory.
The 64-bit interface between the PMU and the CPU delivers the instruction words, which
are requested by the CPU. The PMU decides whether the requested instruction word
has to be fetched from on-chip memory or from external memory.
The Data Management Unit (DMU) controls accesses to the on-chip Data RAM
(DSRAM), to the on-chip peripherals connected to the peripheral bus, and to resources
on the external bus. External accesses (including accesses to peripherals connected to
the on-chip LXBus) are executed by the External Bus Controller (EBC).
The 16-bit interface between the DMU and the CPU handles all data transfers
(operands). Data accesses by the CPU are distributed to the appropriate buses
according to the defined address map.
PMU and DMU are directly coupled to perform cross-over transfers with high speed.
Crossover transfers are executed in both directions:
• PMU via DMU: Code fetches from external locations are redirected via the DMU to
EBC. Thus, the XC2000 can execute code from external resources. No code can be
fetched from the Data RAM (DSRAM).
• DMU via PMU: Data accesses can also be executed to on-chip resources controlled
by the PMU. This includes the following types of transfers:
– Read a constant from the on-chip program ROM/Flash
– Read data from the on-chip PSRAM
– Write data to the on-chip PSRAM (required prior to executing out of it)
– Program/Erase the on-chip Flash memory
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Architectural Overview
On-Chip System Resources
The XC2000 controllers provide a number of powerful system resources designed
around the CPU. The combination of CPU and these resources results in the high
performance of the members of this controller family.
Peripheral Event Controller (PEC) and Interrupt Control
The Peripheral Event Controller enables response to an interrupt request with a single
data transfer (word or byte) which consumes only one instruction cycle and does not
require saving and restoring the machine status. Each interrupt source is prioritized for
every machine cycle in the interrupt control block. If PEC service is selected, a PEC
transfer is started. If CPU interrupt service is requested, the current CPU priority level
stored in the PSW register is tested to determine whether a higher priority interrupt is
currently being serviced. When an interrupt is acknowledged, the current state of the
machine is saved on the internal system stack and the CPU branches to the system
specific vector for the peripheral.
The PEC contains a set of SFRs which store the count value and control bits for eight
data transfer channels. In addition, the PEC uses a dedicated area of RAM which
contains the source and destination addresses. The PEC is controlled in a manner
similar to any other peripheral: through SFRs containing the desired configuration of
each channel.
An individual PEC transfer counter is implicitly decremented for each PEC service
except in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the vector location related to the corresponding source. PEC
services are very well suited, for example, to moving register contents to/from a memory
table. The XC2000 has eight PEC channels, each of which offers such fast interruptdriven data transfer capabilities.
Memory Areas
The memory space of the XC2000 is configured in a Von Neumann architecture. This
means that code memory, data memory, registers, and IO ports are organized within the
same linear address space which covers up to 16 Mbytes. The entire memory space can
be accessed bytewise or wordwise. Particular portions of the on-chip memory have been
made directly bit addressable as well.
Note: The actual memory sizes depend on the selected device type. This overview
describes the maximum block sizes.
768 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash
memory consists of 3 Flash modules, each organized as 64 4-Kbyte sectors. Each
sector can be separately write protected1), erased and programmed (in blocks of 128
bytes). The complete Flash area can be read-protected. A user-defined password
sequence temporarily unlocks protected areas. The Flash modules combine 128-bit
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read accesses with protected and efficient writing algorithms for programming and
erasing. Dynamic error correction provides extremely high read data security for all read
accesses. Accesses to different Flash modules can be executed in parallel.
Note: Program execution from on-chip program memory is the fastest of all possible
alternatives and results in maximum performance. The type of the on-chip
program memory depends on the chosen derivative. On-chip program memory
also includes the PSRAM.
64 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or
data. The PSRAM is accessed via the PMU and is, therefore, optimized for code fetches.
A section of the PSRAM with programmable size can be write-protected.
16 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user
data. The DSRAM is accessed via a separate interface and is, therefore, optimized for
data accesses.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, and in particular for general purpose register
banks. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide
(RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1 Kbyte of on-chip Stand-By SRAM (SBRAM) is provided as a storage for systemrelevant user data that must be preserved while the major part of the device is powered
down. The SBRAM is accessed via a specific interface and is powered via domain M.
The CPU has an actual register context of up to 16 wordwide and/or bytewide global
GPRs at its disposal, which are physically located within the on-chip RAM area. A
Context Pointer (CP) register determines the base address of the active global register
bank to be accessed by the CPU at a time. The number of register banks is restricted
only by the available internal RAM space. For easy parameter passing, a register bank
may overlap other register banks.
A system stack of up to 32 Kwords is provided as storage for temporary data. The system
stack can be located anywhere within the complete addressing range and it is accessed
by the CPU via the Stack Pointer (SP) register and the Stack Pointer Segment (SPSEG)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the
stack pointer value upon each stack access for the detection of a stack overflow or
underflow. This mechanism also supports the control of a bigger virtual stack. Maximum
performance for stack operations is achieved by allocating the system stack to internal
data RAM areas (DPRAM, DSRAM).
1)
To save control bits, sectors are clustered for protection purposes, they remain separate for programming/
erasing.
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Hardware detection of the selected memory space is placed at the internal memory
decoders and allows the user to specify any address directly or indirectly and obtain the
desired data without using temporary registers or special instructions.
For Special Function Registers three areas of the address space are reserved: The
standard Special Function Register area (SFR) uses 512 bytes, while the Extended
Special Function Register area (ESFR) uses the other 512 bytes. A range of 4 Kbytes is
provided for the internal IO area (XSFR). SFRs are wordwide registers which are used
for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC2000 Family with enhanced
functionality. Therefore, they should either not be accessed, or written with zeros, to
ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 2-1) of external RAM and/or ROM
can be connected to the microcontroller. The External Bus Interface also provides
access to external peripherals.
Table 2-1
XC2000 Memory Map
Address Area
Start Loc.
End Loc.
Area Size1)
Notes
IMB register space
FF’FF00H
FF’FFFFH
256 Bytes
–
Reserved (Access trap) F0’0000H
FF’FEFFH
<1 Mbyte
Minus IMB reg.
Reserved for EPSRAM E9’0000H
EF’FFFFH
448 Kbytes
Mirrors EPSRAM
Emulated PSRAM
E8’0000H
E8’FFFFH
64 Kbytes
Flash timing
Reserved for PSRAM
E1’0000H
E7’FFFFH
448 Kbytes
Mirrors PSRAM
Program SRAM
E0’0000H
E0’FFFFH
64 Kbytes
Maximum speed
Reserved for pr. mem.
CC’0000H
DF’FFFFH
<1.25 Mbytes –
Program Flash 2
C8’0000H
CB’FFFFH
256 Kbytes
–
Program Flash 1
C4’0000H
C7’FFFFH
256 Kbytes
–
Reserved Sector (PF0) C3’F000H
C3’FFFFH
4 Kbytes
Used internally
Program Flash 0
C0’0000H
C3’EFFFH
252 Kbytes
–
External memory area
40’0000H
BF’FFFFH
8 Mbytes
–
Available Ext. IO area2) 20’5800H
3F’FFFFH
< 2 Mbytes
Minus USIC/CAN
USIC registers
20’4000H
20’57FFH
6 Kbytes
Accessed via EBC
MultiCAN registers
20’0000H
20’3FFFH
16 Kbytes
Accessed via EBC
External memory area
01’0000H
1F’FFFFH
< 2 Mbytes
Minus segment 0
SFR area
00’FE00H
00’FFFFH
0.5 Kbyte
–
Dual-Port RAM
00’F600H
00’FDFFH
2 Kbytes
–
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Table 2-1
Architectural Overview
XC2000 Memory Map (cont’d)
Address Area
Start Loc.
End Loc.
Area Size1)
Notes
Reserved for DPRAM
00’F200H
00’F5FFH
1 Kbyte
–
ESFR area
00’F000H
00’F1FFH
0.5 Kbyte
–
XSFR area
00’E000H
00’EFFFH
4 Kbytes
–
Data SRAM
00’A000H
00’DFFFH
16 Kbytes
–
Reserved for DSRAM
00’8000H
00’9FFFH
8 Kbytes
–
External memory area
00’0000H
00’7FFFH
32 Kbytes
–
1)
The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
2)
Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Note: For an overview of the available memory sections for the different derivatives,
please refer to Table 1-1 "XC2000 Derivative Synopsis" on Page 1-2.
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External Bus Interface
To meet the needs of designs where more memory is required than is provided on chip,
up to 12 Mbytes of external RAM/ROM/Flash or peripherals can be connected to the
XC2000 microcontroller via its external bus interface.
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to an external bus mode with the following possible selections1):
• Address Bus Width with a range of 0 … 24-bit
• Data Bus Width 8-bit or 16-bit
• Bus Operation Multiplexed or Demultiplexed
In the demultiplexed bus modes, addresses are output on Port 0 and Port 1 and data is
input/output on Port 10 and Port 2. In the multiplexed bus modes both addresses and
data use Port 10 and Port 2 for input/output. The high order address (segment) lines use
Port 2. The number of active segment address lines is selectable, restricting the external
address space to 8 Mbytes … 64 Kbytes. This is required when interface lines are
assigned to Port 2.
For up to five address areas the bus mode (multiplexed/demultiplexed), the data bus
width (8-bit/16-bit) and even the length of a bus cycle (waitstates, signal delays) can be
selected independently. This allows access to a variety of memory and peripheral
components directly and with maximum efficiency.
Access to very slow memories or modules with varying access times is supported via a
particular ‘Ready’ function. The active level of the control input signal is selectable.
A HOLD/HLDA protocol is available for bus arbitration and allows the sharing of external
resources with other bus masters.
The external bus timing is related to the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.
For applications which require less than 64 Kbytes of address space, a non-segmented
memory model can be selected, where all locations can be addressed by 16 bits. Thus,
the upper Port 2 is not needed as an output for the upper address bits (Axx … A16), as
is the case when using the segmented memory model.
The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.
The MultiCAN module and the USIC modules are connected to and accessed via the
LXBus.
1)
Bus modes are switched dynamically if several address windows with different mode settings are used.
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Architectural Overview
On-Chip Peripheral Blocks
The XC2000 Family clearly separates peripherals from the core. This structure permits
the maximum number of operations to be performed in parallel and allows peripherals to
be added or deleted from family members without modifications to the core. Each
functional block processes data independently and communicates information over
common buses. Peripherals are controlled by data written to the respective Special
Function Registers (SFRs). These SFRs are located within either the standard SFR area
(00’FE00H … 00’FFFFH), the extended ESFR area (00’F000H … 00’F1FFH), or within
the internal IO area (00’E000H … 00’EFFFH).
These built-in peripherals either allow the CPU to interface with the external world or
provide functions on-chip that otherwise would need to be added externally in the
respective system.
The XC2000 generic peripherals are:
•
•
•
•
•
•
•
Two General Purpose Timer Blocks (GPT1 and GPT2)
A Watchdog Timer
A Capture/Compare unit (CAPCOM2)
Up to Four Enhanced Capture/Compare units (CCU60, CCU61, CCU62, CCU63)
Two 10-bit Analog/Digital Converters (ADC0, ADC1)
A Real Time Clock (RTC)
Thirteen I/O ports with a total of 118(75) I/O lines
Because the LXBus is the internal representation of the external bus, it does not support
bit-addressing. Accesses are executed by the EBC as if it were external accesses. The
LXBus connects on-chip peripherals to the CPU:
• MultiCAN module with up to 5 CAN nodes and gateway functionality
• Three Serial Interface Modules providing six serial channels
Each peripheral also contains a set of Special Function Registers (SFRs) which control
the functionality of the peripheral and temporarily store intermediate data results. Each
peripheral has an associated set of status flags. Individually selected clock signals are
generated for each peripheral from binary multiples of the master clock.
Note: For an overview of the available peripherals for the different derivatives, please
refer to Table 1-1 "XC2000 Derivative Synopsis" on Page 1-2.
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Peripheral Interfaces
The on-chip peripherals generally have two different types of interfaces: an interface to
the CPU and an interface to external hardware. Communication between the CPU and
peripherals is performed through Special Function Registers (SFRs) and interrupts. The
SFRs serve as control/status and data registers for the peripherals. Interrupt requests
are generated by the peripherals based on specific events which occur during their
operation, such as operation complete, error, etc.
To interface with external hardware, specific pins of the parallel ports are used, when an
input or output function has been selected for a peripheral. During this time, the port pins
are controlled either by the peripheral (when used as outputs) or by the external
hardware which controls the peripheral (when used as inputs). This is called the
‘alternate (input or output) function’ of a port pin, in contrast to its function as a general
purpose I/O pin.
Peripheral Timing
Internal operation of the CPU and peripherals is based on the master clock (fMC). The
clock generation unit uses the on-chip oscillator to derive the master clock from the
crystal or from the external clock signal. The clock signal gated to the peripherals is
independent from the clock signal that feeds the CPU. During Idle mode, the CPU’s clock
is stopped while the peripherals continue their operation. Peripheral SFRs may be
accessed by the CPU once per state. When an SFR is written to by software in the same
state where it is also to be modified by the peripheral, the software write operation has
priority. Further details on peripheral timing are included in the specific sections
describing each peripheral.
Programming Hints
• Access to SFRs: All SFRs reside in data page 3 of the memory space. The following
addressing mechanisms allow access to the SFRs:
– Indirect or direct addressing with 16-bit (mem) addresses must guarantee that the
used data page pointer (DPP0 … DPP3) selects data page 3.
– Accesses via the Peripheral Event Controller (PEC) use the SRCPx and DSTPx
pointers instead of the data page pointers.
– Short 8-bit (reg) addresses to the standard SFR area do not use the data page
pointers but directly access the registers within this 512-byte area.
– Short 8-bit (reg) addresses to the extended ESFR area require switching to the
512-byte Extended SFR area. This is done via the EXTension instructions EXTR,
EXTP(R), EXTS(R).
• Byte Write Operations to wordwide SFRs via indirect or direct 16-bit (mem)
addressing or byte transfers via the PEC force zeros in the non-addressed byte. Byte
write operations via short 8-bit (reg) addressing can access only the low byte of an
SFR and force zeros in the high byte. It is therefore recommended, to use the bitfield
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instructions (BFLDL and BFLDH) to write to any number of bits in either byte of an
SFR without disturbing the non-addressed byte and the unselected bits.
• Reserved Bits: Some of the bits which are contained in the XC2000’s SFRs are
marked as ‘Reserved’. User software should never write ‘1’s to reserved bits. These
bits are currently not implemented and may be used in future products to invoke new
functions. In that case, the active state for those new functions will be ‘1’, and the
inactive state will be ‘0’. Therefore writing only ‘0’s to reserved locations allows
portability of the current software to future devices. After read accesses, reserved bits
should be ignored or masked out.
Capture/Compare Unit (CAPCOM2)
The CAPCOM units support generation and control of timing sequences on up to
16 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse
and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
each capture/compare register.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timer T7 allow event scheduling for the capture/compare registers
relative to external events.
The capture/compare register array contains 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer T7 or T8
and programmed for capture or compare function.
All registers of each module have each one port pin associated with it which serves as
an input pin for triggering the capture function, or as an output pin to indicate the
occurrence of a compare event.
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Architectural Overview
Compare Modes (CAPCOM2)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
several compare events per timer period are possible
Mode 2
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin;
pin toggles on each compare match;
several compare events per timer period are possible
Single Event Mode
Generates single edges or pulses;
can be used with any compare mode
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
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Capture/Compare Units CCU6
The CCU6 units support generation and control of timing sequences on up to three 16bit capture/compare channels plus one independent 16-bit compare channel.
In compare mode, the CCU6 units provide two output signals per channel which have
inverted polarity and non-overlapping pulse transitions (deadtime control). The compare
channel can generate a single PWM output signal and is further used to modulate the
capture/compare output signals.
In capture mode the contents of compare timer T12 is stored in the capture registers
upon a signal transition at pins CCx.
The output signals can be generated in edge-aligned or center-aligned PWM mode.
They are generated continuously or in single-shot mode.
Compare timers T12 and T13 are free running timers which are clocked by the prescaled
system clock.
For motor control applications (brushless DC-drives) both subunits may generate
versatile multichannel PWM signals which are basically either controlled by compare
timer T12 or by a typical hall sensor pattern at the interrupt inputs (block commutation).
The latter mode provides noise filtering for the hall inputs and supports automatic
rotational speed measurement.
The trap function offers a fast emergency stop without CPU activity. Triggered by an
external signal (CTRAP) the outputs are switched to selectable logic levels which can be
adapted to the connected power stages.
Note: The number of available CCU6 units and channels depends on the selected
device type.
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General Purpose Timer (GPT12E) Unit
The GPT12E unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers which are organized in two separate
blocks, GPT1 and GPT2. Each timer in each block may operate independently in a
number of different modes, or may be concatenated with another timer of the same
block.
Each of the three timers T2, T3, T4 of block GPT1 can be configured individually for one
of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the system clock, divided by a programmable prescaler, while Counter Mode allows a
timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in block GPT1 is 4 system clock cycles.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
With its maximum resolution of 2 system clock cycles, the GPT2 block provides precise
event control and time measurement. It includes two timers (T5, T6) and a capture/
reload register (CAPREL). Both timers can be clocked with an input clock which is
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derived from the CPU clock via a programmable prescaler or with external signals. The
count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM1/2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
after the capture procedure. This allows the XC2000 to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
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Real Time Clock
The Real Time Clock (RTC) module of the XC2000 is directly clocked via a separate
clock driver either with the on-chip auxiliary oscillator frequency (fRTC = fOSCa) or with the
prescaled on-chip main oscillator frequency (fRTC = fOSCm/32). It is therefore
independent from the selected clock generation mode of the XC2000.
The RTC basically consists of a chain of divider blocks:
• Selectable 32:1 and 8:1 dividers (on - off)
• The reloadable 16-bit timer T14
• The 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of:
– a reloadable 10-bit timer
– a reloadable 6-bit timer
– a reloadable 6-bit timer
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.
Note: The registers associated with the RTC are not affected by a functional reset in
order to maintain the contents even when intermediate resets are executed.
The RTC module can be used for different purposes:
• System clock to determine the current time and date
• Cyclic time based interrupt, to provide a system time tick independent of CPU
frequency and other resources
• 48-bit timer for long term measurements
• Alarm interrupt for wake-up on a defined time
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A/D Converters
For analog signal measurement, two 10-bit A/D converters (ADC0, ADC1) with 16 (or 8)
multiplexed input channels including a sample and hold circuit have been integrated onchip. They use the method of successive approximation. The sample time (for loading
the capacitors) and the conversion time are programmable and can thus be adjusted to
the external circuitry. The A/D converters can also operate in 8-bit conversion mode,
where the conversion time is further reduced.
Several independent conversion result registers, selectable interrupt requests, and
highly flexible conversion sequences provide a high degree of programmability to fulfill
the requirements of the respective application. Both modules can be synchronized to
allow parallel sampling of two input channels.
For applications that require more analog input channels, external analog multiplexers
can be controlled automatically.
For applications that require less analog input channels, the remaining channel inputs
can be used as digital input port pins.
The A/D converters of the XC2000 support two types of request sources which can be
triggered by several internal and external events.
• Parallel requests are activated at the same time and then executed in a predefined
sequence.
• Queued requests are executed in a user-defined sequence.
In addition, the conversion of a specific channel can be inserted into a running sequence
without disturbing this sequence. All requests are arbitrated according to the priority level
that has been assigned to them.
Data reduction features, such as limit checking or result accumulation, reduce the
number of required CPU accesses and so allow the precise evaluation of analog inputs
(high conversion rate) even at low CPU speed.
The Peripheral Event Controller (PEC) may be used to control the A/D converters or to
automatically store conversion results into a table in memory for later evaluation, without
requiring the overhead of entering and exiting interrupt routines for each data transfer.
Therefore, each A/D converter contains 8 result registers which can be concatenated to
build a result FIFO. Wait-for-read mode can be enabled for each result register to
prevent loss of conversion data.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital input stages under
software control. This can be selected for each pin separately via registers P5_DIDIS
and P15_DIDIS (Port x Digital Input Disable).
The Auto-Power-Down feature of the A/D converters minimizes the power consumption
when no conversion is in progress.
Note: The number of available analog channels depends on the selected device type.
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Universal Serial Interface Channel Modules (USIC)
Each USIC channel can be individually configured to match the application needs, e.g.
the protocol can be selected or changed during run time without the need for a reset. The
following protocols are supported:
• UART (ASC, asynchronous serial channel)
- module capability: receiver/transmitter with max. baud rate fsys/4
- application target baud rate range: 1.2 kBaud to 3.5 MBaud
- number of data bits per data frame 1 to 63
- MSB or LSB first
• LIN Support by HW (low-cost network, baud rate up to 20 kBaud)
- data transfers based on ASC protocol
- baud rate detection possible by built-in capture event of baud rate generator
- checksum generation under SW control for higher flexibility
• SSC/SPI (synchronous serial channel with or without slave select lines)
- module capability: slave mode with max. baud rate fsys
- module capability: master mode with max. baud rate fsys /2
- application target baud rate range: 2 kBaud to 10 MBaud
- number of data bits per data frame 1 to 63, more with explicit stop condition
- MSB or LSB first
• IIC (Inter-IC Bus)
- application baud rate 100 kBaud to 400 kBaud
- 7-bit and 10-bit addressing supported
- full master and slave device capability
• IIS (infotainment audio bus)
- module capability: receiver with max. baud rate fSYS
- module capability: transmitter with max. baud rate fSYS /2
- application target baud rate range: up to 26 MBaud
In addition to the flexible choice of the communication protocol, the USIC structure has
been designed to reduce the system load (CPU load) allowing efficient data handling.
The following aspects have been considered:
• Data buffer capability
The standard buffer capability includes a double word buffer for receive data and a
single word buffer for transmit data. This allows longer CPU reaction times (e.g.
interrupt latency).
• Additional FIFO buffer capability
In addition to the standard buffer capability, the received data and the data to be
transmitted can be buffered in a FIFO buffer structure. The size of the receive and the
transmit FIFO buffer can be programmed independently. Depending on the
application needs, a total buffer capability of 64 data words can be assigned to the
receive and transmit FIFO buffers of a USIC module (the two channels of the USIC
module share the 64 data word buffer).
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•
•
•
•
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•
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In addition to the FIFO buffer, a bypass mechanism allows the introduction of highpriority data without flushing the FIFO buffer.
Transmit control information
For each data word to be transmitted, a 5-bit transmit control information has been
added to automatically control some transmission parameters, such as word length,
frame length, or the slave select control for the SPI protocol. The transmit control
information is generated automatically by analyzing the address where the user SW
has written the data word to be transmitted (32 input locations = 2^5 = 5 bit transmit
control information).
This feature allows individual handling of each data word, e.g. the transmit control
information associated to the data words stored in a transmit FIFO can automatically
modify the slave select outputs to select different communication targets (slave
devices) without CPU load. Alternatively, it can be used to control the frame length.
Flexible frame length control
The number of bits to be transferred within a data frame is independent of the data
word length and can be handled in two different ways. The first option allows
automatic generation of frames up to 63 bits with a known length. The second option
supports longer frames (even unlimited length) or frames with a dynamically controlled
length.
Interrupt capability
The events of each USIC channel can be individually routed to one of 4 service
request outputs, depending on the application needs. Furthermore, specific start and
end of frame indications are supported in addition to protocol-specific events.
Flexible interface routing
Each USIC channel offers the choice between several possible input and output pins
connections for the communications signals. This allows a flexible assignment of
USIC signals to pins that can be changed without resetting the device.
Input conditioning
Each input signal is handled by a programmable input conditioning stage with
programmable filtering and synchronization capability.
Baud rate generation
Each USIC channel contains an own baud rate generator. The baud rate generation
can be based either on the internal module clock or on an external frequency input.
This structure allows data transfers with a frequency that can not be generated
internally, e.g. to synchronize several communication partners.
Transfer trigger capability
In master mode, data transfers can be triggered events generated outside the USIC
module, e.g. at an input pin or a timer unit (transmit data validation). This feature
allows time base related data transmission.
Debugger support
The USIC offers specific addresses to read out received data without interaction with
the FIFO buffer mechanism. This feature allows debugger accesses without the risk
of a corrupted receive data sequence.
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To reach a desired baud rate, two criteria have to be respected, the module capability
and the application environment. The module capability is defined with respect to the
module’s input clock frequency fsys, being the base for the module operation. Although
the module’s capability being much higher (depending on the module clock and the
number of module clock cycles needed to represent a data bit), the reachable baud rate
is generally limited by the application environment. In most cases, the application
environment limits the maximum reachable baud rate due to driver delays, signal
propagation times, or due to EMI reasons.
Note: Depending on the selected additional functions (such as digital filters, input
synchronization stages, sample point adjustment, data structure, etc.), the
maximum reachable baud rate can be limited. Please also take care about
additional delays, such as (internal or external) propagation delays and driver
delays (e.g. for collision detection in ASC mode, for IIC, etc.).
to interrupt
registers
SRx
interrupt generation
pins
f sys
baud rate generator
data
shift
unit
baud rate generator 1
data
buff.
data
shift
unit
input
stages
PPP
(ASC,
SSC,…)
f sys
PPP
(ASC,
SSC,…)
optional: FIFO data buffer shared
between UxC0 and UxC1
Figure 2-3
UxC1
signal distribution
user interface
data
buff.
UxC0
input
stages
USIC
module x
USIC_channels
Channel Structure
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The USIC module contains two independent communication channels, with structure
shown in Figure 2-3.
The data shift unit and the data buffering of each channel support full-duplex data
transfers. The protocol-specific actions are handled by protocol pre-processors (PPP).
In order to simplify data handling, an additional FIFO data buffer is optionally available
for each USIC module to store transmit and receive data for each channel. This FIFO
data buffer is not necessarily available in all devices (please refer to USIC
implementation chapter for details).
Due to the independent channel control and baud rate generation, the communication
protocol, baud rate and the data format can be independently programmed for each
communication channel.
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MultiCAN Module
The MultiCAN module contains five independently operating CAN nodes with Full-CAN
functionality which are able to exchange Data and Remote Frames via a gateway
function. Transmission and reception of CAN frames is handled in accordance with CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
Note: The number of available CAN nodes depends on the selected device type.
All CAN nodes share a common set of 128 message objects. Each message object can
be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects can be combined to build
gateways between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to its own message object list, and it transmits only messages
belonging to this message object list. A powerful, command-driven list controller
performs all message object list operations.
MultiCAN Module Kernel
Clock
Control
CAN
Node 4
fCAN
Message
Object
Buffer
Address
Decoder
128
Objects
Linked
List
Control
.
.
.
CAN
Node 1
CAN
Node 0
Interrupt
Control
TXDC4
RXDC4
.
.
.
.
.
.
TXDC1
RXDC1
Port
Control
TXDC0
RXDC0
CAN Control
mc_mcan_block5.vsd
Figure 2-4
Block Diagram of MultiCAN Module
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MultiCAN Features
• CAN functionality conforms to CAN specification V2.0 B active for each CAN node
(compliant to ISO 11898)
• Up to Five independent CAN nodes
• Up to 128 independent message objects (shared by the CAN nodes)
• Dedicated control registers for each CAN node
• Data transfer rate up to 1 Mbit/s, individually programmable for each node
• Flexible and powerful message transfer control and error handling capabilities
• Full-CAN functionality for message objects:
– Can be assigned to one of the CAN nodes
– Configurable as transmit or receive objects, or as message buffer FIFO
– Handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering
– Remote Monitoring Mode, and frame counter for monitoring
• Automatic Gateway Mode support
• 16 individually programmable interrupt nodes
• Analyzer mode for CAN bus monitoring
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT. Thus, the
chip’s start-up procedure is always monitored. The software has to be designed to restart
the Watchdog Timer before it overflows. If, due to hardware or software related failures,
the software fails to do so, the Watchdog Timer overflows and generates an internal
hardware reset and pulls the RSTOUT pin low in order to allow external hardware
components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 16,384
or 256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) to allow further variation of the monitored time interval. Each
time it is serviced by the application software, the high byte of the Watchdog Timer is
reloaded and the low byte is cleared.
Thus, time intervals between 3.9 µs and 16.3 s can be monitored (@ 66 MHz).
The default Watchdog Timer interval after reset is 6.5 ms (@ 10 MHz).
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Parallel Ports
The XC2000 derivatives are available in two different packages:
• In LQFP-144, they provide up to 118 I/O lines which are organized into 11 input/output
ports and 2 input ports.
• In LQFP-100, they provide up to 75 I/O lines which are organized into 7 input/output
ports and 2 input ports.
All port lines are bit-addressable, and all input/output lines can be individually (bit-wise)
configured via port control registers. This configuration selects the direction (input/
output), push/pull or open-drain operation, activation of pull devices, and edge
characteristics (shape) and driver characteristics (output current) of the port drivers. The
I/O ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. During the internal reset, all port pins are configured as inputs
without pull devices active.
All port lines have programmable alternate input or output functions associated with
them. These alternate fucntions can be assigned to various port pins to support the
optimal utilization for a given application. For this reason, certain functions appear
several times in Table 2-3.
All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
Table 2-3
Summary of the XC2000’s Parallel Ports
Port
Width
1441)
Width
1001)
Alternate Functions
Port 0
8
8
Address lines,
Serial interface lines of USIC1, CAN0, and CAN1,
Input/Output lines for CCU61
Port 1
8
8
Address lines,
Serial interface lines of USIC1 and USIC2,
Input/Output lines for CCU62,
OCDS control, interrupts
Port 2
13
13
Address and/or data lines, bus control,
Serial interface lines of USIC0, CAN0, and CAN1,
Input/Output lines for CCU60, CCU63, and CAPCOM2,
Timer control signals,
JTAG, interrupts, system clock output
Port 3
8
---
Bus arbitration signals,
Serial interface lines of USIC0, USIC2, CAN3, and CAN4
User’s Manual
ArchitectureX2K, V1.0
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 2-3
Architectural Overview
Summary of the XC2000’s Parallel Ports (cont’d)
Port
Width
1441)
Width
1001)
Alternate Functions
Port 4
8
4
Chip select signals,
Serial interface lines of CAN2,
Input/Output lines for CAPCOM2,
Timer control signals
Port 5
16
11
Analog input channels to ADC0,
Input/Output lines for CCU6x,
Timer control signals,
JTAG, OCDS control, interrupts
Port 6
4
3
ADC control lines,
Serial interface lines of USIC1,
Timer control signals,
OCDS control
Port 7
5
5
ADC control lines,
Serial interface lines of USIC0 and CAN4,
Input/Output lines for CCU62,
Timer control signals,
JTAG, OCDS control,system clock output
Port 8
7
---
Input/Output lines for CCU60,
JTAG, OCDS control
Port 9
8
---
Serial interface lines of USIC2,
Input/Output lines for CCU60 and CCU63,
OCDS control
Port 10
16
16
Address and/or data lines, bus control,
Serial interface lines of USIC0, USIC1, CAN2, CAN3, and
CAN4,
Input/Output lines for CCU60,
JTAG, OCDS control
Port 11
6
---
Input/Output lines for CCU63
Port 15
8
5
Analog input channels to ADC1,
Timer control signals
1)
These columns describe the availability of port pins in the different packages.
User’s Manual
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
2.4
Architectural Overview
Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
to generate the clock signals for the XC2000 with high flexibility. The master clock fMC is
the reference clock signal, and is used for TwinCAN and is output to the external system.
The CPU clock fCPU and the system clock fSYS are derived from the master clock either
directly (1:1) or via a 2:1 prescaler (fSYS = fCPU = fMC/2).
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock/OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
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System Units (Vol. 1 of 2)
Preliminary
2.5
Architectural Overview
Power Management
The XC2000 provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):
• Supply Voltage Management allows the temporary reduction of the supply voltage
of major parts of the logic, or even the complete disconnection. This drastically
reduces the power consumed because of leakage current, in particular at high
temperature.
Several power reduction modes provide the optimal balance of power reduction and
wake-up time.
• Clock Generation Management controls the distribution and the frequency of
internal and external clock signals. While the clock signals for currently inactive parts
of logic are disabled automatically, the user can reduce the XC2000’s CPU clock
frequency which drastically reduces the consumed power.
External circuitry can be controlled via the programmable frequency output FOUT.
• Peripheral Management permits temporary disabling of peripheral modules. Each
peripheral can separately be disabled/enabled. Also the CPU can be switched off
while the peripherals can continue to operate.
Wake-up from power reduction modes can be triggered either externally by signals
generated by the external system, or internally by the on-chip wake-up timer, which
supports intermittent operation of the XC2000 by generating cyclic wake-up signals. This
offers full performance to quickly react on action requests while the intermittent sleep
phases greatly reduce the average power consumption of the system.
Note: When selecting the supply voltage and the clock source and generation method,
the required parameters must be carefully written to the respective bitfields, to
avoid unintended intermediate states. Recommended sequences are provided
which ensure the intended operation of power supply system and clock system.
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Preliminary
2.6
Architectural Overview
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system provides a broad range of debug and emulation
features built into the XC2000. The user software running on the XC2000 can thus be
debugged within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface,
consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger
controls the OCDS via a set of dedicated registers accessible via the JTAG interface.
Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.
An injection interface allows the execution of OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported as well as the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the
activation of an external signal.
The data transferred at a watchpoint (see above) can be obtained via the JTAG interface
or via the external bus interface for increased performance.
The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) to
communicate with external circuitry. These interface signals use dedicated pins.
Complete system emulation is supported by an emulation device. Via this full-featured
emulation interface (including internal buses, control, status, and pad signals) the
functions of the XC2000 chip can be emulated in an emulation system.
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System Units (Vol. 1 of 2)
Preliminary
3
Memory Organization
Memory Organization
The memory space of the XC2000 is configured in a “Von Neumann” architecture. This
means that code and data are accessed within the same linear address space. All of the
physically separated memory areas, including internal ROM and Flash, internal RAM,
the internal Special Function Register Areas (SFRs and ESFRs), the internal IO area,
and external memory are mapped into one common address space.
255...240
FF’FFFF
H
239...224
On-Chip
Program Memory
Areas
E0’0000
H
223...208
207...192
C0’0000H
175...160
A0’0000
H
~12 Mbytes
External Addressing Capability
159...144
143...128
External
Memory
Area
80’0000
H
127...112
111...96
60’0000H
95...80
16 Mbytes
Total Addressing Capability
191...176
79...64
40’0000
H
63...48
External
IO
Area
47...32
20’0000
External
Memory
Area
H
31...16
15...0
00’0000H
Total Address Space
16 Mbytes, Segments 255...0
mc_xc16x_mmap.vsd
Figure 3-1
Address Space Overview
User’s Manual
MemoryX2K, V1.1
3-1
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
The XC2000 provides a total addressable memory space of 16 Mbytes. This address
space is arranged as 256 segments of 64 Kbytes each, and each segment is again
subdivided into four data pages of 16 Kbytes each (see Figure 3-1).
Bytes are stored at even or odd byte addresses. Words are stored in ascending memory
locations with the low byte at an even byte address being followed by the high byte at
the next odd byte address (“little endian”). Double words (code only) are stored in
ascending memory locations as two subsequent words. Single bits are always stored in
the specified bit position at a word address. Bit position 0 is the least significant bit of the
byte at an even byte address, and bit position 15 is the most significant bit of the byte at
the next odd byte address. Bit addressing is supported for a part of the Special Function
Registers, a part of the internal RAM and for the General Purpose Registers.
xxxx’xxxAH
xxxx’xxx9H
7
6
… Bits ...
0
xxxx’xxx8H
Byte
xxxx’xxx7H
Byte
xxxx’xxx6H
Word (High Byte)
xxxx’xxx5H
Word (Low Byte)
xxxx’xxx4H
Double Word (High Byte)
xxxx’xxx3H
Double Word (Third Byte)
xxxx’xxx2H
Double Word (Second Byte)
xxxx’xxx1H
Double Word (Low Byte)
xxxx’xxx0H
xxxx’xxxFH
imb_endianess.vsd:byte_orga
Figure 3-2
Storage of Words, Bytes and Bits in a Byte Organized Memory
Note: Byte units forming a single word or a double word must always be stored within
the same physical (internal, external, ROM, RAM) and organizational (page,
segment) memory area.
User’s Manual
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
3.1
Memory Organization
Address Mapping
All the various memory areas and peripheral registers (see Table 3-1) are mapped into
one contiguous address space. All sections can be accessed in the same way. The
memory map of the XC2000 contains some reserved areas, so future derivatives can be
enhanced in an upward-compatible fashion.
Table 3-1
XC2000 Memory Map 1)
Area Size2)
Address Area
Start Loc. End Loc.
IMB register space
FF’FF00H FF’FFFFH 256 Bytes
Reserved (access trap)
F0’0000H
FF’FEFFH < 1 MByte
Reserved for EPSRAM
E9’0000H
EF’FFFFH 448 KBytes
EPSRAM
E8’0000H
E8’FFFFH 64 KBytes
Reserved for PSRAM
E1’0000H
E7’FFFFH 448 KBytes
PSRAM
E0’0000H
E0’FFFFH 64 KBytes
Reserved for Flash
CC’0000H DF’FFFFH <1.25 MBytes
Flash 2
C8’0000H
CB’FFFFH 256 KBytes
Flash 1
C4’0000H
C7’FFFFH 256 KBytes
Flash 0
C0’0000H
C3’FFFFH 252 KBytes3)
External memory area
40’0000H
BF’FFFFH 8 MBytes
External IO area4)
20’5800H
3F’FFFFH < 2 MBytes
Minus CAN/USIC
USIC registers
20’4000H
20’57FFH
6 KBytes
Accessed via EBC
MultiCAN registers
20’0000H
20’3FFFH
16 KBytes
Accessed via EBC
External memory area
01’0000H
1F’FFFFH < 2 MBytes
SFR area
00’FE00H
00’FFFFH 0.5 KBytes
Dual-port RAM
(DPRAM)
00’F600H
00’FDFFH 2 KBytes
Reserved for DPRAM
00’F200H
00’F5FFH
1 KBytes
ESFR area
00’F000H
00’F1FFH
0.5 KBytes
XSFR area
00’E000H
00’EFFFH 4 KBytes
Data SRAM (DSRAM)
00’A000H
00’DFFFH 16 KBytes
Reserved for DSRAM
00’8000H
00’9FFFH
8 KBytes
External memory area
00’0000H
00’7FFFH
32 KBytes
User’s Manual
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Notes
Minus IMB registers.
PSRAM with Flash
timing.
Program SRAM.
Minus res. seg.
Minus segment 0
V1.0, 2007-06
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Memory Organization
1)
Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
external bus accesses.
2)
The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3)
The 4 KB sector from C0’F000H to C0’FFFFH is not accessible to the software.
4)
Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
3.2
Special Function Register Areas
The Special Function Registers (SFRs) controlling the system and peripheral functions
of the XC2000 can be accessed via four dedicated address areas:
•
•
•
•
512-byte SFR area (located above the internal RAM: 00’FFFFH … 00’FE00H).
512-byte ESFR area (located below the internal RAM: 00’F1FFH … 00’F000H).
4-Kbytes XSFR area (located below the ESFR area: 00’EFFFH … 00’E000H).
256-byte IMB SFR area (located in: FF’FF00H … FF’FFFFH)1).
This arrangement provides upward compatibility with the derivatives of the C166 and
XC166 families.
1)
Attention: the IMB SFR area is not recognized by the CPU as special IO area (see Section 3.6).
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Memory Organization
SFR Area
Preliminary
SFRs
00'FE00 H
00'FC00 H
DPRAM
00'FA00 H
00'F800 H
00'F200 H
ESFRs
EBC
Interrupt/PEC
CC6
XSFR Area
00'F400 H
Ports
Reserved
Reserved
Reserved
00'F000 H
00'EE00 H
00'EC00 H
Upper Half of Data Page 3
Reserved for
DPRAM
8 KBytes
ESFR Area
00'F600 H
00'EA00 H
00'E800 H
00'E600 H
00'E400 H
00'E200 H
ADC
00'E000 H
x c 2000_regareas. v s d
Figure 3-3
Special Function Register Mapping
Note: The upper 256 bytes of SFR area, ESFR area, and internal RAM are bitaddressable (see hashed blocks in Figure 3-3).
Special Function Registers
The functions of the CPU, the bus interface, the IO ports, and the on-chip peripherals of
the XC2000 are controlled via a number of Special Function Registers (SFRs).
All Special Function Registers can be addressed via indirect and long 16-bit addressing
modes. The (word) SFRs and their respective low bytes in the SFR/ESFR areas can be
addressed using an 8-bit offset together with an implicit base address. However, this
does not work for the respective high bytes!
Note: Writing to any byte of an SFR causes the not addressed complementary byte to
be cleared.
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Memory Organization
The upper half of the SFR-area (00’FFFFH … 00’FF00H) and the ESFR-area (00’F1FFH
… 00’F100H) is bit-addressable, so the respective control/status bits can be modified
directly or checked using bit addressing.
When accessing registers in the ESFR area using 8-bit addresses or direct bit
addressing, an Extend Register (EXTR) instruction is required beforehand to switch the
short addressing mechanism from the standard SFR area to the Extended SFR area.
This is not required for 16-bit and indirect addresses. The GPRs R15 … R0 are
duplicated, i.e. they are accessible within both register blocks via short 2-, 4-, or 8-bit
addresses without switching.
ESFR_SWITCH_EXAMPLE:
EXTR #4
MOV
ODP9, #data16
BFLDL DP9, #mask, #data8
BSET DP1H.7
MOV
T8REL, R1
;---- ;--------------MOV
T8REL, R1
;Switch to ESFR area for next 4 instr.
;ODP9 uses 8-bit reg addressing
;Bit addressing for bitfields
;Bit addressing for single bits
;T8REL uses 16-bit mem address,
;R1 is duplicated into the ESFR space
;(EXTR is not required for this access)
;The scope of the EXTR #4 instruction …
;… ends here!
;T8REL uses 16-bit mem address,
;R1 is accessed via the SFR space
In order to minimize the use of the EXTR instructions the ESFR area mostly holds
registers which are mainly required for initialization and mode selection. Registers that
need to be accessed frequently are allocated to the standard SFR area, wherever
possible.
Note: The tools are equipped to monitor accesses to the ESFR area and will
automatically insert EXTR instructions, or issue a warning in case of missing or
excessive EXTR instructions.
Accesses to registers in the XSFR area use 16-bit addresses and require no specific
addressing modes or precautions.
General Purpose Registers
The General Purpose Registers (GPRs) use a block of 16 consecutive words either
within the global register bank or within one of the two local register banks. The bit-field
BANK in register PSW selects the currently active register bank. The global register bank
is mirrored to a section in the DPRAM, the Context Pointer (CP) register determines the
base address of the currently active global register bank section. This register bank may
consist of up to 16 Word-GPRs (R0, R1, … R15) and/or of up to 16 byte-GPRs
(RL0,RH0, … RL7, RH7). The sixteen byte-GPRs are mapped onto the first eight Word
GPRs (see Table 3-2).
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System Units (Vol. 1 of 2)
Preliminary
Memory Organization
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 bytes. The GPRs are accessed via short
2-, 4-, or 8-bit addressing modes using the Context Pointer (CP) register as base
address for the global bank (independent of the current DPP register contents).
Additionally, each bit in the currently active register bank can be accessed individually.
Table 3-2
Mapping of General Purpose Registers to DPRAM Addresses
DPRAM Address High Byte Registers Low Byte Registers Word Registers
<CP> + 1EH
–
–
R15
<CP> + 1CH
–
–
R14
<CP> + 1AH
–
–
R13
<CP> + 18H
–
–
R12
<CP> + 16H
–
–
R11
<CP> + 14H
–
–
R10
<CP> + 12H
–
–
R9
<CP> + 10H
–
–
R8
<CP> + 0EH
RH7
RL7
R7
<CP> + 0CH
RH6
RL6
R6
<CP> + 0AH
RH5
RL5
R5
<CP> + 08H
RH4
RL4
R4
<CP> + 06H
RH3
RL3
R3
<CP> + 04H
RH2
RL2
R2
<CP> + 02H
RH1
RL1
R1
<CP> + 00H
RH0
RL0
R0
The XC2000 supports fast register bank (context) switching. Multiple global register
banks can physically exist within the DPRAM at the same time. Only the global register
bank selected by the Context Pointer register (CP) is active at a given time, however.
Selecting a new active global register bank is simply done by updating the CP register.
A particular Switch Context (SCXT) instruction performs register bank switching by
automatically saving the previous context and loading the new context. The number of
implemented register banks (arbitrary sizes) is limited only by the size of the available
DPRAM.
Note: The local GPR banks are not memory mapped and the GPRs cannot be accessed
using a long or indirect memory address.
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Preliminary
Memory Organization
PEC Source and Destination Pointers
The source and destination address pointers for data transfers on the PEC channels are
located in the XSFR area.
Each channel uses a pair of pointers stored in two subsequent word locations with the
source pointer (SRCPx) on the lower and the destination pointer (DSTPx) on the higher
word address (x = 7 … 0). An additional segment register stores the associated source
and destination segments, so PEC transfers can move data from/to any location within
the complete addressing range.
Whenever a PEC data transfer is performed, the pair of source and destination pointers
(selected by the specified PEC channel number) accesses the locations referred to by
these pointers independently of the current DPP register contents.
If a PEC channel is not used, the corresponding pointer locations can be used for other
purposes.
For more details about the use of the source and destination pointers for PEC data
transfers see Section XXX in Interrupt And Trap “Operation of PEC Channels”.
Note: Writing to any byte of the PEC pointers causes the not addressed complementary
byte to be cleared.
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Preliminary
3.3
Memory Organization
Data Memory Areas
The XC2000 provides two on-chip RAM areas exclusively for data storage:
•
•
The Dual Port RAM (DPRAM) can be used for global register banks (GPRs), system
stack, storage of variables and other data, in particular for MAC operands.
The Data SRAM (DSRAM) can be used for system stack (recommended), storage
of variables and other data.
Note: Data can also be stored in the PSRAM (see Section 3.10). However, both data
memory areas provide the fastest access.
Two additional on-chip memory areas exist with the special purpose to retain data while
the system power domain is switched off:
•
•
The Stand-By RAM (SBRAM).
The Marker Memory (MKMEM).
Dual-Port RAM (DPRAM)
The XC2000 provides 2 Kbytes of DPRAM (00’F600H … 00’FDFFH). Any word or byte
data in the DPRAM can be accessed via indirect or long 16-bit addressing modes, if the
selected DPP register points to data page 3. Any word data access is made on an even
byte address. The highest possible word data storage location in the DPRAM is
00’FDFEH.
For PEC data transfers, the DPRAM can be accessed independent of the contents of the
DPP registers via the PEC source and destination pointers.
The upper 256 bytes of the DPRAM (00’FD00H through 00’FDFFH) are provided for
single bit storage, and thus they are bit addressable.
Note: Code cannot be executed out of the DPRAM.
An area of 3 Kbytes is dedicated to DPRAM (00’F200H … 00’FDFFH). The locations
without implemented DPRAM are reserved.
Data SRAM (DSRAM)
The XC2000 provides 16 Kbytes of DSRAM (00’A000H … 00’CFFFH). Any word or byte
data in the DSRAM can be accessed via indirect or long 16-bit addressing modes, if the
selected DPP register points to data page 3. Any word data access is made on an even
byte address. The highest possible word data storage location in the DSRAM is
00’CFFEH.
For PEC data transfers, the DSRAM can be accessed independent of the contents of the
DPP registers via the PEC source and destination pointers.
Note: Code cannot be executed out of the DSRAM.
An area of 20 Kbytes is dedicated to DSRAM (00’8000H … 00’CFFFH). The location
without implemented DSRAM are reserved.
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Preliminary
Memory Organization
Stand-By RAM (SBRAM)
The SBRAM provides 1 Kbyte of memory supplied by the wake-up power domain
(DMP_M). Its main purpose is to retain state while the system power domain (DMP_1)
is switched off.
Unlike the other memories the SBRAM is not mapped into the address range of the
processor. Reading and writing is done via two address and two data SFRs. Details of
the access mechanism are described in Section 3.11.
Note: Code cannot be executed out of the SBRAM.
Marker Memory (MKMEM)
The MKMEM provides 4 bytes of memory supplied by the wake-up power domain. Its
purpose is the same as the SBRAM.
The MKEM consists of 2 16-bit SFRs that are accessible as all other SFRs. Details are
described in Section 3.11.
Note: It goes without saying that code cannot be executed out of the MKMEM.
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Preliminary
3.4
Memory Organization
Program Memory Areas
The XC2000 provides two on-chip program memory areas for code/data storage:
•
•
The Program Flash/ROM stores code and constant data. Flash memory is (re-)
programmed by the application software or flash loaders, ROM is mask-programmed
in the factory.
The Program SRAM (PSRAM) stores temporary code sequences and other data.
For example higher level boot loader software can be written to the PSRAM and then
be executed to program the on-chip Flash memory.
IMB Reg.
FF'FFFF H
FF'FF00 H
FF'FFFF H
FF'FF00 H
Reserved
Reserved
F0'0000H
Reserved
PSRAM
Reserved
PSRAM
F0'0000H
E8'0000H
PSRAM (64 KB)
Flash Access
Timing
E9'0000H
E8'0000 H
E0'0000 H
E1'0000 H
Reserved
Flash Area
PSRAM (64 KB)
SRAM Timing
E0'0000 H
D0'0000 H
Flash 2 (256 KB)
C4'0000H
Flash 1 (256 KB)
Flash 0 (252 KB)
Flash 0 (192 KB)
C0'0000 H
Reserved (4 KB)
Flash 0 (60 KB)
C1'0000H
C0'F000H
No software access
to this Flash range.
C0'0000H
imb_memory_map.vsd
Figure 3-4
On-Chip Program Memory Mapping
User’s Manual
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
3.4.1
Memory Organization
Program/Data SRAM (PSRAM)
The XC2000 provides 64 Kbytes of PSRAM (E0’0000H … E0’FFFFH). The PSRAM
provides fast code execution without initial delays. Therefore, it supports non-sequential
code execution, for example via the interrupt vector table.
Any word or byte data in the PSRAM can be accessed via indirect or long 16-bit
addressing modes, if the selected DPP register points to one of its data page 896 – 899.
Any word data access is made on an even byte address. The highest possible word data
storage location in the PSRAM is E0’FFFEH.
For PEC data transfers, the PSRAM can be accessed independent of the contents of the
DPP registers via the PEC source and destination pointers.
Any data can be stored in the PSRAM. Because the PSRAM is optimized for code
fetches, however, data accesses to the data memories provide higher performance.
Note: The PSRAM is not bit-addressable.
An area of 512 Kbytes is dedicated to PSRAM (E0’0000H … F7’FFFFH). The locations
without implemented PSRAM are reserved.
Flash Emulation
During code development the PSRAM will often be used for storing code or data that the
production chip will later contain in the flash memory. In order to ensure similar execution
time the PSRAM supports a second access path in the range E8’0000H … EF’FFFFH
with timing parameters that correspond to Flash timing. The number of wait-cycles is
determined by the flash access timing configuration (see IMB_IMBCTRL.WSFLASH).
Writes are always performed without wait-cycles.
This flash access timing imitation is nearly cycle accurate because the same read logic
as for reading the flash memory is used1). Discrepancies might occur if the software uses
the PSRAM for flash emulation and directly as PSRAM. During emulation access
conflicts can cause a slightly different timing as in the product chip where these conflicts
do not occur.
Another source of timing differences can be access conflicts at the flash modules in the
product chip. Data reads and instruction fetches that target different flash modules can
be executed concurrently whereas if they target the same flash module they are
executed sequentially with the data access as first. In the flash emulation this type of
conflict can not occur. The data and the instruction access will both incur the defined
number of wait-cycles (as if they would target different flash modules) and if they collide
at the PSRAM interface the instruction fetch will see an additional wait-cycle.
1)
The dual use of the flash read logic might cause unexpected behavior: while the IMB Core is busy with
updating the protection configuration (after startup or after changing the security pages) read accesses to the
flash emulation range of the PSRAM are blocked because Flash data reads would be blocked also.
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Data Integrity
The PSRAM contains its own parity generation and comparison logic. It generates the
parity bits for every written byte. When reading data it checks the data integrity by
comparing the read parity bits with calculated parity bits.
If enabled parity errors can trigger a trap (see “Memory Parity Error Handling” on
Page 3-77).
Write Protection
As the PSRAM is often used to store timing critical code or constant data it is supplied
with a write protection. After storing critical data in the PSRAM the register field
IMB_IMBCTRH.PSPROT can be used to split the PSRAM into a read-only and a
writable part. Write accesses to the read-only part are blocked and a trap can be
activated.
3.4.2
Non-Volatile Program Memory (Flash)
The XC2000 provides 764 Kbytes of program Flash (C0’0000H … CB’FFFFH). Code and
data fetches are always 64-bit aligned, using byte select lines for word and byte data.
Any word or byte data in the program memory can be accessed via indirect or long 16bit addressing modes, if the selected DPP register points to one of the respective data
pages. Any word data access is made on an even byte address. The highest possible
word data storage location in the program memory is CB’FFFEH.
For PEC data transfers, the program memory can be accessed independent of the
contents of the DPP registers via the PEC source and destination pointers.
Note: The program memory is not bit-addressable.
An area of 2 Mbytes is dedicated to program memory (C0’0000H … DF’FFFFH). The
locations without implemented program memory are reserved.
A more detailed description can be found in “Embedded Flash Memory” on
Page 3-18.
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3.5
Memory Organization
System Stack
The system stack may be defined anywhere within the XC2000’s memory areas
(including external memory).
For all system stack operations the respective stack memory is accessed via a 24-bit
stack pointer. The Stack Pointer (SP) register provides the lower 16 bits of the stack
pointer (stack pointer offset), the Stack Pointer Segment (SPSEG) register adds the
upper 8 bits of the stack pointer (stack segment). The system stack grows downward
from higher towards lower locations as it is filled. Only word accesses are supported to
the system stack.
Register SP is decremented before data is pushed on the system stack, and
incremented after data has been pulled from the system stack. Only word accesses are
supported to the system stack.
By using register SP for stack operations, the size of the system stack is limited to
64 KBytes. The stack must be located in the segment defined by register SPSEG.
The stack pointer points to the latest system stack entry, rather than to the next available
system stack address.
A stack overflow (STKOV) register and a stack underflow (STKUN) register are provided
to control the lower and upper limits of the selected stack area. These two stack
boundary registers can be used both for protection against data corruption.
For best performance it is recommended to locate the stack to the DPRAM or to the
DSRAM. Using the DPRAM may conflict with register banks or MAC operands.
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3.6
Memory Organization
IO Areas
The following areas of the XC2000’s address space are marked as IO area:
•
•
The external IO area is provided for external peripherals (or memories) and also
comprises the on-chip LXBus-peripherals, such as the CAN or USIC modules. It is
located from 20’0000H to 3F’FFFFH (2 Mbytes).
The internal IO area provides access to the internal peripherals and is split into three
blocks:
– The SFR area, located from 00’FE00H to 00’FFFFH (512 bytes).
– The ESFR area, located from 00’F000H to 00’F1FFH (512 bytes).
– The XSFR area, located from 00’E000H to 00’EFFFH (4 Kbytes).
Note: The external IO area supports real byte accesses. The internal IO area does not
support real byte transfers, the complementary byte is cleared when writing to a
byte location.
The IO areas have special properties, because peripheral modules must be controlled
in a different way than memories:
•
•
•
Accesses are not buffered and cached, the write back buffers and caches are not
used to store IO read and write accesses.
Speculative reads are not executed, but delayed until all speculations are solved (e.g.
pre-fetching after conditional branches).
Data forwarding is disabled, an IO read access is delayed until all IO writes pending
in the pipeline are executed, because peripherals can change their internal state after
a write access.
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3.7
Memory Organization
External Memory Space
The XC2000 is capable of using an address space of up to 16 Mbytes. Only parts of this
address space are occupied by internal memory areas or are reserved. A total area of
approximately 12 Mbytes references external memory locations. This external memory
is accessed via the XC2000’s external bus interface.
Selectable memory bank sizes are supported: The maximum size of a bank in the
external memory space depends on the number of activated address bits. It can vary
from 64 Kbytes (with A15 … A0 activated) to 12 Mbytes (with A23 … A0 activated). The
logical size of a memory bank and its location in the address space is defined by
programming the respective address window. It can vary from 4 Kbytes to 12 Mbytes.
•
•
•
•
Non-segmented mode:
– 64 Kbytes with A15 … A0 on PORT0 or PORT1.
1-bit segmented mode:
– 128 Kbytes with A16 on Port 4
– and A15 … A0 on PORT0 or PORT1.
2-bit … 7-bit segmented mode:
– with Ax … A16 on Port 4
– and A15 … A0 on PORT0 or PORT1.
8-bit segmented mode:
– 12 Mbytes with A23 … A16 on Port 4
– and A15 … A0 on PORT0 or PORT1.
Each bank can be directly addressed via the address bus, while the programmable chip
select signals can be used to select various memory banks.
The XC2000 also supports four different bus types:
•
•
•
•
Multiplexed 16-bit Bus with address and data on PORT0 (default after Reset).
Multiplexed 8-bit Bus with address and data on PORT0/P0L.
Demultiplexed 16-bit Bus with address on PORT1 and data on PORT0.
Demultiplexed 8-bit Bus with address on PORT1 and data on P0L.
Memory model and bus mode are preselected during reset by pin EA and PORT0 pins.
For further details about the external bus configuration and control please refer to
Chapter XX (The External Bus Controller).
External word and byte data can only be accessed via indirect or long 16-bit addressing
modes using one of the four DPP registers. There is no short addressing mode for
external operands. Any word data access is made to an even byte address.
For PEC data transfers the external memory can be accessed independent of the
contents of the DPP registers via the PEC source and destination pointers.
Note: The external memory is not bit addressable.
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3.8
Memory Organization
Crossing Memory Boundaries
The address space of the XC2000 is implicitly divided into equally sized blocks of
different granularity and into logical memory areas. Crossing the boundaries between
these blocks (code or data) or areas requires special attention to ensure that the
controller executes the desired operations.
Memory Areas are partitions of the address space assigned to different kinds of
memory (if provided at all). These memory areas are the SFR areas, the on-chip
program or data RAM areas, the on-chip ROM/Flash (if available), the on-chip LXBusperipherals (if integrated), and the external memory.
Accessing subsequent data locations which belong to different memory areas is no
problem. However, when executing code, the different memory areas must be switched
explicitly via branch instructions. Sequential boundary crossing is not supported and
leads to erroneous results.
Note: Changing from the external memory area to the on-chip RAM area takes place
within segment 0.
Segments are contiguous blocks of 64 Kbytes each. They are referenced via the Code
Segment Pointer CSP for code fetches and via an explicit segment number for data
accesses overriding the standard DPP scheme.
During code fetching, segments are not changed automatically, but rather must be
switched explicitly. The instructions JMPS, CALLS and RETS will do this.
In larger sequential programs, make sure that the highest used code location of a
segment contains an unconditional branch instruction to the respective following
segment to prevent the pre-fetcher from trying to leave the current segment.
Data Pages are contiguous blocks of 16 Kbytes each. They are referenced via the data
page pointers DPP3 … DPP0 and via an explicit data page number for data accesses
overriding the standard DPP scheme. Each DPP register can select one of the possible
1024 data pages. The DPP register which is used for the current access is selected via
the two upper bits of the 16-bit data address. Therefore, subsequent 16-bit data
addresses which cross the 16-Kbytes data page boundaries will use different data page
pointers, while the physical locations need not be subsequent within memory.
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3.9
Memory Organization
Embedded Flash Memory
This chapter describes the embedded flash memory of the XC2000:
•
•
•
•
•
•
•
Section 3.9.1 defines the flash specific nomenclature and the structure of the flash
memory.
Section 3.9.2 describes the operating modes.
Section 3.9.3 contains all operations.
Section 3.9.4 gives the details of operating sequences.
The three sections Section 3.9.5, Section 3.9.6 and Section 3.9.7 look more into
depth of maintaining data integrity and protection issues.
Section 3.9.8 discusses Flash EEPROM emulation.
Section 3.9.9 describes interrupt generation by the flash memory.
The Chapter 3.10 describes how the flash memory is embedded into the memory
architecture of the XC2000 and lists all SFRs that affect its behavior.
3.9.1
Definitions
This section defines the nomenclature and some abbreviations as a base for the rest of
the document. The used flash memory is a non-volatile memory (“NVM”) based on a
floating gate one-transistor cell. It is called “non-volatile” because the memory content is
kept when the memory power supply is shut off.
Logical and Physical States
Flash memory content can not be changed directly as in SRAMs. Changing data is a
complicated process with a typically much longer duration than reading.
•
•
Erasing: The erased state of a cell is logical 0. Forcing an flash cell to this state is
called “erasing”. Erasing is possible with a minimum granularity of one page (see
below).
Programming: The programmed state of a cell is logical 1. Changing an erased cell
to this state is called “programming”. A page must only be programmed once and has
to be erased before it can be programmed again.
The above listed processes have certain limitations:
•
•
Retention: This is the time during which the data of a flash cell can be read reliably.
The retention time is a statistical figure that depends on the operating conditions of
the flash array (temperature profile) and the accesses to the flash array. With an
increasing number of program/erase cycles (see endurance) the retention is lowered.
Drain and gate disturbs decrease data retention as well.
Endurance: As described above the data retention is reduced with an increasing
number of program/erase cycles. A flash cell incurs one cycle whenever its page or
sector is erased. This number is called “endurance”. As said for the retention it is a
statistical figure that depends on operating conditions and the use of the flash cells
and not to forget on the required quality level.
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Drain Disturb: Because of using a so called “one-transistor” flash cell each program
access disturbs all pages of the same sector slightly. Over long these “drain disturbs”
make 0 and 1 values indistinguishable and thus provoke read errors. This effect is
again interrelated with the retention. A cell that incurred a high number of drain
disturbs will have a lower retention. The physical sectors of the flash array are
isolated from each other. So pages of a different sector do not incur a drain disturb.
This effect must be therefor considered when the page erase feature is used.
The durations of programming and erasing as well as the limits for endurance, retention
and drain disturbs are documented in the data sheet.
Attention: No means exist in the device that prevent the application from violating
these limitation.
Array Structure
The flash memory is hierarchically structured:
•
•
•
•
•
Block: A block consists of 128 user data bits (i.e. 16 bytes) and 9 ECC bits. One read
access delivers one block.
Page: A page consists of 8 blocks (i.e. 128 bytes). Programming changes always
complete pages.
Sector: A sector consists of 32 pages (i.e. 4096 bytes). The pages of one sector are
affected by drain disturb as described above. The pages of different sectors are
isolated from each other.
Array: Each array has in the XC2000 64 sectors1). Usually when referring to an
“array” this contains as well all accompanying logic as assembly buffer, high voltage
logic and the digital logic that allows to operate them in parallel.
Memory: The complete flash memory of the XC2000 consists of 3 flash arrays.
This structure is visualized in Figure 3-5.
1)
In the Flash0 one sector is reserved for device internal purposes. It is not accessible by software.
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256 KB
Array
Sect or
Num ber
63
Page
Num ber
Sector
Block
Num ber
31
Page
7
2
2
2
1
1
1
Sector
0
0
Page
0
Block
137 Bits
Combined flash memory byte address
Array
[ 1: 0]
Sect or
[ 5: 0]
Page
[4: 0]
Block
[2: 0]
Byte
[ 3: 0]
9 Bits ECC
128 Bits Data
[.. ][. . . . . .][. . . . .][. . .][. . . .]
flash_array_userview_diagram.vsd
Figure 3-5
3.9.2
Flash Structure
Operating Modes
The IMB and the flash memory and each flash module have certain modes of operation.
Some modes define clocking and power supply and the operating state of the analog
logic as oscillators and voltage pumps. Overall system modes (e.g. startup mode)
influence the behavior or the flash memory as well.
Other modes define the functional behavior. These will be discussed here.
3.9.2.1
Standard Read Mode
After reset and after performing a clean startup the flash memory with all its modules is
in “standard read mode”. In this mode it behaves as an on-chip ROM. This mode is
entered:
•
•
•
After reset when the complete start-up has been performed.
After completion of a longer lasting command like “erase” or “program” which is
acknowledged by clearing the “busy” flag.
Immediately after each other command execution.
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Memory Organization
In case of detecting an execution error like attempting to write to a write protected
range, sending a wrong password, after all sequence errors.
For the long lasting commands the read mode stays active until the last command of the
sequence is received and the operation is started.
3.9.2.2
Command Mode
After receiving the last command of a command sequence the addressed flash module
(not the whole flash memory!) is placed into command mode. For most commands this
will not be noticed by the user as the command executes immediately and afterwards the
flash module is placed again into read mode. For the long lasting commands the flash
module stays in command mode for several milliseconds. This is reported by setting the
corresponding “busy” flag. The data of a busy flash module cannot be read. New
command sequences are not accepted (even if they target different flash modules) and
cause a sequence error until the running operation has finished.
Read accesses to busy flash modules stall the CPU until the read mode is entered again.
A stalled CPU responds only to the reset. As no interrupts can be handled this state must
be avoided. Nevertheless this feature can be used to execute code from a flash module
that erases or programs data in the same flash module.
The IMB Core is limited to control only one running operation. Consequently when one
flash module is in command mode no other commands to either modules are accepted
but the other modules stay readable.
3.9.2.3
Page Mode
The page mode is entered with the “Enter Page Mode” command. Please find its
description below. A flash module that is in page mode can still be read (so it is
concurrently in “read mode”). At a time only one flash module can be in page mode.
When the flash memory is in page mode — i.e. one of the flash modules is in page mode
— some command sequences are not allowed. These are all erase sequences and the
“change read margin” sequence. These are ignored and a sequence error is reported.
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3.9.3
Memory Organization
Operations
The flash memory supports the following operations:
•
•
•
Instruction fetch.
Data read.
Command sequences to change data and control the protection.
3.9.3.1
Instruction Fetch from Flash Memory
Instructions are fetched by the PMU in groups of aligned 64 bits. These code requests
are forwarded to the flash memory. It needs a varying number of cycles (depending on
the system clock frequency) to perform the read access. The number of cycles must be
known to the IMB Core because the flash does not signal data availability. The number
of wait-cycles is therefore stored in the IMB_IMBCTRL register.
One read access to the flash memory delivers 128 data bits and a 9-bit ECC value. The
ECC value is used to detect and possibly correct errors. The addressed 64-bit part of the
128-bit chunk is sent to the PMU. The complete 128 data bits and the 9 ECC bits are
stored in the IMB Core with their address. If a succeeding fetch request matches this
address the data is delivered from the buffer without performing a read access in the
flash memory. The delivery from the buffer happens after one cycle. The flash read waitcycles are not waited.
The stored data are a kind of instruction cache. In order to support self-modifying code
(e.g. boot loaders) this cache is invalidated when the corresponding address is written
(i.e. erased or programmed).
In addition to this fetch buffer the IMB Core has an additional performance increasing
feature — the Linear Code Pre-Fetch. When this feature is enabled with
IMB_IMBCTRL.DLCPF = 0 the IMB Core fetches autonomously the following
instructions while the CPU executes from its own buffers or the fetch buffer. As this
feature is fetching only the linear successors (it does not analyze the code stream) it is
most effective for code with longer linear sequences. For code with a high density of
jumps and calls it can even cause a reduction of performance and should be switched
off.
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3.9.3.2
Memory Organization
Data Reads from Flash Memory
Data reads are issued by the DMU. Data is always requested in 16-bit words. The flash
memory delivers for every read request 128 bits plus ECC as described in “Instruction
Fetch from Flash Memory” on Page 3-22.
The IMB Core has to get all 128 bits to evaluate the ECC data. The requested 16 bits will
be delivered to the DMU. All data and ECC bits are kept in the data register and their
address is kept in the address register. For all following data reads the address is
compared with the address register and in case of a match the data is delivered after one
cycle from the data register. Every data read that is not delivered from this cache
invalidates the cache content. When the requested data arrives the cache contains again
valid data.
This small data cache is invalidated when a write (i.e. erase or program) access to this
address happens.
For data reads the IMB Core does not perform any autonomous pre-fetching.
3.9.3.3
Data Writes to Flash Memory
Flash memory content can not be changed by directly writing data to this memory.
Command sequences are used to execute all other operations in the flash except
reading. Command sequences consist of data writes with certain data to the flash
memory address range. All data moves targeting this range are interpreted as command
sequences. If they do not match a defined one or if the IMB Core is busy with executing
a sequence (i.e. it is in “command mode”) a sequence error is reported.
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3.9.3.4
Memory Organization
Command Sequences
As described before changing data in the flash memory is performed with command
sequences.
Table 3-3
Command Sequence Overview
Command Sequence
Description
Details on
Page
Reset to Read
Reset Flash into read mode and clear
error flags.
Page 3-26
Clear Status
Clear error and status flags.
Page 3-26
Change Read Margin
Change read margins.
Page 3-26
Enter Page Mode
Prepare page for programming.
Page 3-27
Enter Security Page Mode
Prepare security page for programming.
Page 3-28
Load Page Word
Load page with data.
Page 3-28
Program Page
Start page programming process.
Page 3-29
Erase Sector
Start sector erase process.
Page 3-30
Erase Page
Start page erase process.
Page 3-31
Erase Security Page
Start security page erase process.
Page 3-32
Disable Read Protection
Disable temporarily read protection with
password.
Page 3-32
Disable Write Protection
Disable temporarily write protection with
password.
Page 3-33
Re-Enable Read/Write
Protection
Re-enable protection.
Page 3-34
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3.9.4
Memory Organization
Details of Command Sequences
The description defines the command sequence with pseudo assembler code. It is
“pseudo” because all addresses are direct addresses which is generally not possible in
real assembler code.
The commands are called by a sequence of one to six data moves into the flash memory
range. The data moves must be of the “word” type, i.e. not byte move instructions. The
following sections describe each command. The following abbreviations for addresses
and data will be used:
•
•
•
•
•
•
•
•
PA: “Page Address”. This is the base address of the destination page. For example
the very first page has the address C0’0000H. The page 13 of the second array has
the PA = C0’0000H + 1·256·1024 (for the array) + 0·4·1024 (for the sector) + 13·128
(for the page) = C4’0680H.
SECPA: “Security Page Address”. This is the virtual address of a security page. It is
“virtual” because SECPA is just used as argument of the command sequence to
identify the security page but the physical storage of the security page is hidden.
Two security pages are defined:
SecP0: address C0’0000H.
SecP1: address C0’0080H.
WD: “Write Data”. This is a 16-bit data word that is written into the assembly buffer.
SA: “Sector Address”. This is the physical sector number as defined in Figure 3-6
based on the address of the flash module. Two examples as clarification:
1. Physical sector number 16 of the first array that is based on C0’0000H is addressed
with SA = C0’0000H + 16·4·1024 = C1’0000H.
2. The second 256 KB array has the base address C4’0000H (as shown in
Table 3-1). So its physical sector number 3 has the SA = C4’0000H + 3·4·1024 =
C4’3000H.
PWD: “Password”. This is a 64-bit password. It is transferred in 4 16-bit data words
PWD0 = PWD[15:0], PWD1 = PWD[31:16], PWD2 = PWD[47:32] and PWD3 =
PWD[63:48].
Address XX followed by two hexadecimal digits, for example “XXAAH”. If the
command targets a certain flash module the XX must be translated to its base
address. So “XXAAH” means C0’00AAH for all commands addressing flash 0,
C4’00AAH for flash 1 and C8’00AAH for flash 2. If a command (e.g. “Clear Status”)
addresses the complete flash memory the base address of flash module 0 must be
used.
Data XX followed by two hexadecimal digits, e.g. XXA5H. This is a “don’t care” data
word where only the low byte must match a certain pattern. So in this example all data
words like 12A5H or 79A5H can be used.
MR: “Margin”. This 8-bit number defines the read margin. MR can take the values 00H
(normal read), 01H (hard read 0), 02H (alternate hard read 0), 05H (hard read 1), 06H
(alternate hard read 1). All other values of MR are reserved.
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Reset to Read
Arguments: –
Definition:
MOV XXAAH, XXF0H
Timing: One cycle command that does not set any “BUSY” flags. But note that an
immediately following write access to the IMB Core is stalled for a few clock cycles during
which the IMB Core is busy with aborting a previous command.
Description: The internal command state machine is reset to initial state and returns to
read mode. An already started programming or erase operation is not affected and will
be continued (the “Reset to Read” command — i.e. all commands — will anyhow not be
accepted while the IMB Core is busy).
The “Reset to Read” command is a single cycle command. It can be used during a
command sequence to reset the command interpreter and return the IMB Core into its
initial state. It clears also all error flags in the Flash Status Register IMB_FSR and an
active page mode is aborted. Because all commands are rejected with a SQER while the
IMB Core is busy “Reset to Read” can not be used to abort an active command mode.
This command clears: PROER, PAGE, SQER, OPER, ISBER, IDBER, DSBER,
DDBER.
Clear Status
Arguments: –
Definition:
MOV XXAAH, XXF5H
Timing: 1-cycle command that does not set any busy flags.
Description: The flags OPER, SQER, PROER, ISBER, IDBER, DSBER, DDBER in
Flash status register are cleared. Additionally, the process status bits (PROG, ERASE,
POWER, MAR) are cleared.
Change Read Margin
Arguments: MR
Definition:
MOV XXAAH, XXB0H
MOV XX54H, XXMRH
Timing: 2-cycle command that sets “BUSY” for around 30 micro seconds.
Description: This command sequence changes the read margin of one flash module.
The address XX of the second move identifies the targeted flash module. The flash
module needs some time to change its read voltage. During this time BUSY is set and
this flash module cannot be accessed. The other flash modules stay readable.
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The argument “MR” defines the read margin:
•
•
•
•
•
•
00H: normal read margin.
01H: hard read 0 margin.
02H: alternate hard read 0 margin.
05H: hard read 1 margin.
06H: alternate hard read 1 margin.
Other values: reserved.
For understanding the read margins please refer to “Read Margins” on Page 3-35.
This command must not be issued when the flash memory is in page mode. In this case
it is ignored and a sequence error is reported.
Note: As noted in “Margin Control” on Page 3-60 the command sequences “Program
Page”, “Erase Sector”, “Erase Page” and “Erase Security Page” reset the read
margin back to 00H, i.e. to the normal read margin. The same happens in case of
a flash wake-up.
Enter Page Mode
Arguments: PA
Definition:
MOV XXAAH, XX50H
MOV PA, XXAAH
Timing: 2-cycle command that sets “BUSY” for around 100 clock cycles.
Description: The page mode is entered to prepare a page programming operation on
page address PA. (Write data are accepted only with the “Load Page Word” command.)
With this command, the IMB Core initializes the write pointer of its block assembly
register to zero so that it points to the first word. The page mode is indicated in the status
register IMB_FSR with the PAGE bit, separately for each flash module. The page mode
and the read mode are allowed in parallel at the same time and in the same flash module
so the flash module stays readable. When the addressed page PA is read the content of
the flash memory is delivered. The page mode can be aborted and the related PAGE bit
in IMB_FSR be cleared with the “Reset to Read” command. A new “Enter Page Mode”
command during page mode aborts the actual page mode, which is indicated with the
error flag SQER, and restarts a new page operation. So as mentioned above only one
of the flash modules can be in page mode at a time. If one of the erase commands or the
“Change Read Margin” command are received while in page mode it is ignored and a
sequence error is reported.
If write protection is installed for the sector to be programmed, the “Enter Page Mode”
command is only accepted when write protection has before been disabled using the
unlock command sequence “Disable Write Protection” with four passwords. If global
write protection is installed with read protection, also the command “Disable Read
Protection” can be used if no sector specific protection is installed. If write protection is
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not disabled when the “Enter Page Mode” command is received, the command is not
executed, and the protection error flag PROER is set in the IMB_FSR.
Enter Security Page Mode
Arguments: SECPA
Definition:
MOV XXAAH, XX55H
MOV SECPA, XXAAH
Timing: 2-cycle command that sets “BUSY” for around 100 clock cycles.
Description: This command is identical to the “Enter Page Mode” command (see
above), with the following exceptions: The addressed page (SECPA) belongs to the
security pages of the flash memory and not to the user flash range. This command can
only be executed after disabling of read protection and of sector write protection. Only if
protection is not installed (e.g. for the very first installation of keywords), read/write
protection need not be disabled. This command is not accepted and a protection error is
reported if any protection is installed and active.
The use of this command to install passwords and to disable them again is described in
“Protection Handling Details” on Page 3-38.
Load Page Word
Arguments: WD
Definition:
MOV XXF2H, WD
Timing: 1-cycle command that does not set any “BUSY” flags. But note that an
immediately following write access to the IMB Core or read from the flash memory is
stalled for a few clock cycles if it arrives while the IMB Core is busy with copying its block
assembly register content into the flash module assembly buffer. During this stall time
the CPU can not perform any action! So either the user software can accept this stall time
(which must be taken into account for the worst-case interrupt latency) or the software
must avoid the blocking accesses.
Description: Load the IMB Core block assembly register with a 16-bit word and
increment the write pointer. The 128 byte assembly buffer (i.e. a complete page) is filled
by a sequence of 64 “Load Page Word” commands. The word address is not determined
by the command but the “Enter Page Mode” command sets a write word pointer to zero
which is incremented after each “Load Page Word” command.
This (sequential) data write access to the block assembly register belongs to and is only
accepted in Page Mode. The command address of this single cycle command is always
the same (F2H). These low order address bits also identify the “Load Page Word”
command and the sequential write data to be loaded into the block assembly register.
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The high order bits XX should address the target page. The IMB Core takes always the
page address that was used by the last “Enter Page Mode” command.
When the 128-bit block assembly register of the IMB Core is filled completely after 8
“Load Page Word” commands the IMB Core calculates the 9 ECC bits and transfers the
block into the assembly buffer of the flash module. After that it sets the write pointer of
the block assembly register back to zero. The following 8 “Load Page Word” commands
fill again the block. After all 8 blocks are filled the “Program Page” command can be
used to trigger the program process that transfers the assembly buffer content into the
flash array.
While the IMB Core transfers the completed block assembly register to the flash module
it can not accept new data for a few cycles. A “Load Page Word” command arriving
during this time is stalled by the IMB Core.
If “Program Page” is called before all blocks of the assembly buffer have received new
data then the remaining bits are cleared.
If more than 8 times 8 commands are used the additional data is lost. The overflow
condition is indicated by the sequence error flag, but the execution of a following
“Program Page” command is not suppressed (the page mode is not aborted).
When a “Load Page Word” command is received and the flash is not in page mode, a
sequence error is reported in IMB_FSR with SQER flag. In case of a new “Enter Page
Mode” command or a “Reset to Read” command during page mode, or in case of an
Application Reset, the write data in the assembly buffer is lost. The current page mode
is aborted and in case of a new “Enter Page Mode” command entered again for the new
address.
Program Page
Arguments: –
Definition:
MOV XXAAH, XXA0H
MOV XX5AH, XXAAH
Timing: 2-cycle command that sets “BUSY” for the whole programming duration.
Description: The assembly buffer of the flash module is programmed into the flash array.
If the last block of data was not filled completely this command finalizes its ECC
calculation and copies its data into the assembly buffer before it starts the program
process. The selection of the flash module and the page to be programmed depends on
the page address used by the last “Enter Page Mode” command. The user software
should always address the targeted page.
The programming process is autonomously performed by the selected flash module. The
CPU is not occupied and can continue with its application.
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The “Program Page” command is only accepted if the addressed flash module is in
Page Mode (otherwise, a sequence error is reported instead of execution). With the
“Program Page” command, the page mode is terminated, indicated by resetting the
related PAGE flag and the command mode is entered and the PROG flag in the status
register IMB_FSR is activated and the BUSY flag for the addressed module is set in
IMB_FSR. While BUSY is set the IMB Core does not accept any further commands.
When the program process has finished BUSY is cleared but PROG stays set. It
indicates which operation has finished and will be cleared by a System Reset or by
“Clear Status”.
Read accesses to the busy flash module are not possible. Reading a busy flash module
stalls until the flash module becomes ready again.
If write protection is installed for the sector to be programmed, the “Program Page”
command is not accepted because the Flash is not in Page Mode (see description of the
“Enter Page Mode” command).
If the page to be programmed is a security page (accepted only in security page mode),
the new protection configuration (including keywords or protection confirmation code) is
valid directly after execution of this command.
While the IMB Core reads the new protection configuration all DMU accesses to any
flash module are stalled.
Erase Sector
Arguments: SA
Definition:
MOV XXAAH, XX80H
MOV XX54H, XXAAH
MOV SA, XX33H
Timing: 3-cycle command that sets BUSY for the whole erasing duration.
Description: The addressed physical sector in the flash array is erased. Following data
reads deliver all-zero data with correct ECC.
The erasing process is autonomously performed by the selected flash module. The CPU
is not occupied and can continue with its application.
The sector to be erased is addressed by SA (sector address) in the last command cycle.
With the last cycle of the “Erase Sector” command, the command mode is entered,
indicated by activation of the ERASE flag and after start of erase operation also by the
related busy flag in the status register IMB_FSR. The BUSY flag is cleared after finishing
the operation but ERASE stays set. It can be cleared by a System Reset or the “Clear
Status” command.
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Read accesses to the busy flash module are not possible. Read accesses to the not busy
flash module are especially supported. Reading a busy flash module stalls until the flash
module becomes ready again.
If write protection is installed for the sector to be erased, the Erase Sector command is
only accepted when write protection has before been disabled using the unlock
command sequence “Disable Write Protection”. If global write protection is installed
with read protection, also the command “Disable Read Protection” can be used if no
sector specific protection is installed. If write protection is not disabled when the “Erase
Sector” command is received, the command is not executed, and the protection error
flag PROER is set in the IMB_FSR.
This command must not be issued when the flash memory is in page mode. In this case
it is ignored and a sequence error is reported.
Erase Page
Arguments: PA
Definition:
MOV XXAAH, XX80H
MOV XX54H, XXAAH
MOV PA, XX03H
Timing: 3-cycle command that sets BUSY for the whole erasing duration.
Description: The addressed page is erased. Following data reads deliver all-zero data
with correct ECC.
With the last cycle of the “Erase Page” command, the command mode is entered,
indicated by activation of the ERASE flag and after start of erase operation also by the
related BUSY flag in the status register IMB_FSR. BUSY is cleared automatically after
finishing the operation but ERASE stays set. It is cleared by a System Reset or the
“Clear Status” command.
Read accesses to the busy flash array are not possible. Read accesses to the not busy
flash modules are especially supported. Reading a busy flash module stalls until the
flash module becomes ready again.
If the page to be erased belongs to a sector which is write protected, the command is
only executed when write protection has before been disabled (see “Erase Sector”
command).
In case of using the page erase care must be taken not to exceed the drain disturb limit
of the other pages of the same sector.
This command must not be issued when the flash memory is in page mode. In this case
it is ignored and a sequence error is reported.
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Erase Security Page
Arguments: SECPA
Definition:
MOV XXAAH, XX80H
MOV XX54H, XXA5H
MOV SECPA, XX53H
Timing: 3-cycle command that sets BUSY for the whole erasing duration.
Description: The addressed security page is erased.
This command is identical to the “Erase Page” command with the following exceptions:
The addressed page (SecP0 or SecP1) belongs not to the user visible flash memory
range. This command can only be executed after disabling of read protection and of
sector write protection.
See “Protection Handling Examples” on Page 3-45 for a detailed description of reprogramming security pages.
The structure of the two security pages (SecP0 and SecP1) is described in “Layout of
the Security Pages” on Page 3-43.
After erasing a security page the new protection configuration (including keywords or
protection confirmation code) is valid directly after execution of this command.
While the IMB Core reads the protection configuration all DMU accesses to any flash
module are stalled.
This command must not be issued when the flash memory is in page mode. In this case
it is ignored and a sequence error is reported.
Disable Read Protection
Arguments: PWD
Definition:
MOV
MOV
MOV
MOV
MOV
MOV
XX3CH,
XX54H,
XXAAH,
XX54H,
XXAAH,
XX5AH,
XXXXH
PWD0
PWD1
PWD2
PWD3
XX55H
Timing: 6-cycle command that does not set any busy flag.
Description: Disable temporarily Flash read protection and — if activated — global write
protection of the whole flash memory. The RPA bit in IMB_IMBCTR is reset.
This is a protected command sequence, using four user defined passwords to release
this command or to check the programmed keywords. For every password one
command cycle is required. If the second or fourth password represents the code of the
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“Reset to Read” command, it is interpreted as password and the reset is not executed.
The 16-bit passwords are internally compared with the keywords out of the “Security
Page 0”. If one or more passwords are not identical to their related keywords, the
protected sectors remain in the locked state and a protection error (PROER) is indicated
in the Flash status register. In this case, a new “Disable Read Protection” command or
a “Disable Write Protection” command is only accepted after the next Application
Reset.
Note: During execution of the “Disable Read” (or Write) Protection command a
password compare error is only indicated after all four passwords have been
compared with the related keywords.
Note: This command sequence is also used to check the correctness of keywords
before the protection is confirmed in the Security Page 1. A wrong keyword is
indicated by the IMB_FSR flag PROER.
After correct execution of this command, the whole flash memory is unlocked and the
read protection disable bit RPRODIS is set in the Flash Status Register (IMB_FSR).
Erase and program operations on all sectors are then possible, if the flash memory was
also globally write protected (WPA=1), and if they are not separately write protected. The
read protection (including global write protection, if so selected) remains disabled until
the command “Re-Enable Read/Write Protection” is executed, or until the next
Application Reset (including HW and SW reset).
Disable Write Protection
Arguments: PWD
Definition:
MOV
MOV
MOV
MOV
MOV
MOV
XX3CH,
XX54H,
XXAAH,
XX54H,
XXAAH,
XX5AH,
XXXXH
PWD0
PWD1
PWD2
PWD3
XX05H
Timing: 6-cycle command that does not set any busy flag.
Description: Disable temporarily the global flash write protection or/and the sector write
protection of all protected sectors. The WPA bit in IMB_IMBCTR is reset.
This is a protected command sequence, using four user defined passwords to release
this command (as described above for the “Disable Read Protection” command).
After correct execution of this command, all write-protected sectors are unlocked, which
is indicated in the Flash Status Register (IMB_FSR) with the WPRODIS bit. Erase and
program operations on all sectors are now possible, until
•
The command “Re-Enable Read/Write Protection” is executed, or
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The next Application Reset (including HW and SW reset) is received.
Re-Enable Read/Write Protection
Arguments: –
Definition:
MOV XX5EH, XXXXH
Timing: 1-cycle command that does not set any busy flags.
Description: Flash read and write protection is resumed.
This single-cycle command clears RPRODIS and WPRODIS. The IMB Core is triggered
to restore the protection states RPA and WPA from the content of the security page 0 as
defined in Table 3-4 ““Flash State” Determining RPA and WPA” on Page 3-40. So
in effect this command resumes all kinds of temporarily disabled protection installations.
This command is released immediately after execution.
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3.9.5
Memory Organization
Data Integrity
This section describes means for detecting and preventing the inadvertent modification
of data in the flash memory.
3.9.5.1
Error Correcting Codes (ECC)
With very low probability a flash cell can lose its data value faster than specified. In order
to reach the defined overall device reliability each 128-bit block of flash data is
accompanied with a 9-bit ECC value. This redundancy supplies SEC-DED capability,
meaning “single error correction and double error detection”. All single bit errors are
corrected (and the incident is detected), all double bit errors are detected and even most
triple bit errors are detected but some of these escape as valid data or corrected data.
A detected error is reported in the register IMB_FSR_PROT. Software can select which
type of error should trigger a trap by the means of register IMB_INTCTR. In the system
control further means exist to modify the handling of errors (see “SCU Trap Control
Registers” on Page 6-202). The enabled trap requests by the flash module are handled
there as “Flash Access Trap”. In case of a double-bit error the read data is always
replaced with a dummy data word.
3.9.5.2
Aborted Program/Erase Detection
Where the ECC should protect from intrinsic failures of the flash memory that affect
usually only single bits; an interruption of a running program or erase process might
cause massive data corruption:
•
•
The erase process programs first all cells to 1 before it erases them. So depending
on the time when it is interrupted the data might be in a different state. This can be
the old data, all-one, a random value, a weak all-zero or finally all-zero.
The program process programs all bits concurrently from 0 to 1. If it is interrupted not
all set bits might read as 1 or contain a weak 1.
The register IMB_FSR_OP contains the bits ERASE and PROG. These bits stay set until
the next “Clear Status” command or System Reset. So if an erase or program process
is interrupted by an Application Reset one of these bits is still set which allows to detect
the interruption. It lies in the responsibility of the software to send the “Clear Status”
command after a finalized program/erase process to enable this evaluation.
Another possible measure against aborted program/erase processes is to prevent resets
by configuring the SCU appropriately.
3.9.5.3
Read Margins
As explained above interrupting a program or erase process might leave cells in a
weakly erased or programmed state. This is particularly dangerous as following reads
might deliver the correct data with correct ECC but these cells do not have the defined
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retention, i.e. after a while they may toggle. This dangerous state can be detected with
“read margins”.
Reading with “hard read 0 margin” returns weak 0s as 1s and reading with “hard read 1
margin” returns weak 1s as 0s. Changing the read margin is done with the command
sequence “Change Read Margin” and is reported by the status register “IMB_MAR”.
In order to detect cells that will likely fail in the near future all used flash memory ranges
can be read with both hard reads regularly. If both read values are the same and no read
error occurs nothing has to be done. If this check fails there is still a good chance that
the normal read will return the correct value (or at least has only a correctable one-bit
error). After erasing the page this value can be programmed again to ensure long-term
readability of this data.
In case of using the page erase care must be taken not to exceed the drain disturb limit
of the other pages of the same sector.
3.9.5.4
Protection Overview
The flash memory supports read and write protection for the whole memory and
separate write protection for each logical sector. The logical sector structure is depicted
in Figure 3-6.
256 KB Array
Phys.
Sector
Number
Logical
Sector
Address
63
63
Logical
Sector
Number
9 = 64 KB
48
8 = 64 KB
Logical
Grouping
32
7 = 64 KB
16
12
15
Phys. Sector 15
Reserved in
Flash 0
0
8
4
0
6 = 12 KB/16 KB
5 = 16 KB
4 = 16 KB
0 - 3 = 4 * 4 KB
flash_array_logsectors_diagram.vsd
Figure 3-6
Logical Sectors
If read protection is installed and active, any flash read access is disabled in case of start
after reset from external memory or from internal RAM. Debug access is as well disabled
and thus the execution of injected OCDS instructions. In case of start after reset in
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internal flash, all flash access operations are controlled by the flash-internal user code
and are therefore allowed, as long as not especially disabled by the user, e.g. before
enabling the debug interface.
Per default, the read protection includes a full (global) flash memory write protection
covering all flash modules. This is necessary to eliminate the possibility to program a
dump routine into the Flash, which reads the whole Flash and writes it out via the
external bus or a serial interface. Program and erase accesses to the flash during active
read protection are only possible, if write protection is separately disabled. Flash write
and read protection can be temporarily disabled, if the user authorizes himself with
correct passwords.
The device also features a sector specific write protection. Software locking of flash
memory sectors is provided to protect code and data. This feature disables both program
and erase operations for all protected sectors. With write protection it is supported to
protect the flash memory or parts of it from unauthorized programming or erase
accesses and to provide virus-proof protection for all sectors.
Read and write protection is installed by specific security configuration words which are
programmed by the user directly into two “Security Pages” (SecP0/1). After any reset,
the security configuration is checked by the command state machine (IMB Core) and
installations are stored (and indicated) in related registers. If any protection is enabled
also the security pages are especially protected.
For authorization of short-term disabling of read protection or/and of write protection a
password checking feature is provided. Only with correct 64-bit password a temporary
unprotected state is taken and the protected command sequences are enabled. If not
finished by the command “Re-Enable Read/Write Protection”, the unprotected state is
terminated with the next reset. Password checking is based on four 16-bit keywords
(together 64 bits) which are programmed by the user directly into the “Security Page 0”
(SecP0).
Special support is provided to protect also the protection installation itself against any
stressing or beaming aggressors. The codes of configuration bits are selected, so that
in case of any violation in the flash array, on the read path or in registers the protected
state is taken per default. In registers and security pages, protection control bits are
coded always with two bits, having both codes, “00B” and “11B” as indication of illegal
and therefore protected state.
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3.9.6
Memory Organization
Protection Handling Details
As shortly described in “Protection Overview” on Page 3-36 the flash memory can be
in different protection states. The protection handling can be separated into different
layers that interact which each other (see Figure 3-7).
•
•
•
The lowest layer consists of the physical content of the security pages SecP0 and
SecP1. This information is used to initialize the protection system during startup.
The next layer consists of registers that report the state of the physical layer
(IMB_PROCONx) and the protection state (IMB_FSR). The protection state can be
temporarily changed with command sequences which is reflected in the IMB_FSR.
The highest layer is represented by 4 fields of the IMB_IMBCTR register. These fields
define the protection rights of the customer software (are read or write accesses
currently allowed or not).
The IMB Core controls the protection state of all connected flash modules centrally. In
this position it can supervise all accesses that are issued by the CPU.
Boot Mode
Upper Layer
IMB_CTRL
DDF
DCF
IMB_CTRH
RPA
WPA
Write to
DDF/DCF
Middle Layer
IMB_PROCONx
IMB_FSR
IMB_FSR
Disable/ ReEnable
Protection
PROCONs
WPRODIS
RPRO
RPRODIS
PROIN
PROINER
Physical Layer
Security Page 0
Passwords
Security Page 1
Lock Code
RPRO
PROCONs
Erase/
Program
Sec. Page
copied
influences
influences indirectly
flash_protection.vsd
Figure 3-7
Protection Layers
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3.9.6.1
Memory Organization
The Lower Layer “Physical State”
After reset the protection state of the device is restored from the following information:
•
•
The security page 1 contains a “lock code”. This consists of two words of data (32
bits). If it has the value AA55AA55H then security page 0 determines the protection
state. Otherwise (i.e. the lock code was not found) the device is in the “non-protected
state”. The content of the security page 0 is still copied into the registers as described
in “The Middle Layer “Flash State”” on Page 3-39 but their values are ignored in
the non-protected state.
The security page 0 contains the RPRO double bit, the write protection bits SnU and
4 passwords. If the field RPRO contains a valid 01B or 10B entry the page is valid and
the device is in the “protection installed state”. The page content determines the
security settings after startup. If SecP0 contains an invalid RPRO entry the device is
in the “errored protection” state.
To summarize: the content of the security pages determines if the device is in the “nonprotected state”, “protection installed state” or “errored protection state”. These states
are reflected in the register settings of the next layer.
The device is usually delivered in the “non-protected state”.
The exact layout of the security pages is described in “Layout of the Security Pages”
on Page 3-43.
3.9.6.2
The Middle Layer “Flash State”
The middle layer consists of the registers IMB_PROCONx and IMB_FSRx and
commands that manipulate them and the content of the security pages.
During startup the physical state is examined by the IMB Core and it is reflected in the
following bit settings:
•
•
•
“non-protected state”: IMB_FSR.PROIN = 0, IMB_FSR.PROINER = 0.
“protection installed state”: IMB_FSR.PROIN = 1, IMB_FSR.PROINER = 0.
“errored protection state”: IMB_FSR.PROIN = 0, IMB_FSR.PROINER = 1.
The fourth possible setting PROIN=1 and PROINER=1 is invalid and can not occur.
The IMB_PROCONx registers are initialized during startup with the content of the
security page 0. The bits DSBER and DDBER indicate if an ECC error occurred. The
customer software has thus the possibility to detect disturbed security pages and it can
refresh their content.
Commands
Other bits of the IMB_FSR: RPRODIS, WPRODIS, PROER can be manipulated with
command sequences and define together with the other bits the protection effective for
the next layer. All three bits are 0 after system startup.
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The command “Disable Read Protection” sets RPRODIS to 1 if the correct passwords
that are stored in SecP0 are supplied. If incorrect passwords are entered the bit PROER
is set and RPRODIS stays unchanged. As protection against “brute force attacks” that
search the correct password the password detection is locked. So after supplying the
first incorrect password all following passwords even the correct ones are rejected with
PROER. This state is only left by an Application Reset or by erasing SecP0.
The disabled protection can be enabled again by the Application Reset or by the
command “Re-Enable Read/Write Protection” which clears RPRODIS again.
The bit PROER can be reset by an Application Reset or by the commands “Reset to
Read” and “Clear Status”.
The command “Disable Write Protection” sets WPRODIS to 1 if the correct passwords
are supplied. It behaves analog to RPRODIS as described above.
The command “Re-Enable Read/Write Protection” clears RPRODIS and WPRODIS.
The commands “Enter Page Mode”, “Enter Security Page Mode”, “Erase Page”,
“Erase Security Page” and “Erase Sector” set PROER if the write access to the
addressed range is not allowed. If a write access is allowed or not is determined by the
next level.
Table 3-4 summarizes how the “Flash State” of protection determines the RPA and WPA
fields of IMB_IMBCTR. For the double bits a short notation is used here and in the
following sections: 1 means active, 0 means inactive, ‘#’ means invalid and ‘–’ means do
not care including invalid states. The symbol ‘|’ means logic or.
Table 3-4
“Flash State” Determining RPA and WPA
IMB_
FSR.
PROI
N
IMB_
FSR.
PROI
NER
IMB_
FSR.
RPR
O
IMB_
FSR.
RPR
ODIS
IMB_
FSR.
WPR
ODIS
Resulting Security Level in RPA and WPA
0
0
–
–
–
Non-protected state:
RPA = 0, WPA = 0.
1
0
Protection installed state (possibly disabled,
see below):
0
–
0
RPA = 0, WPA = 1.
0
0
1
RPA = 0, WPA = 0.
1|#
0
0
RPA = 1, WPA = 1.
–
1
1
RPA = 0, WPA = 0 (all disabled).
1|#
0
1
RPA = 1, WPA = 0.
1|#
1
0
RPA = 0, WPA = 1.
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Memory Organization
Table 3-4
“Flash State” Determining RPA and WPA (cont’d)
IMB_
FSR.
PROI
N
IMB_
FSR.
PROI
NER
0
1
3.9.6.3
IMB_
FSR.
RPR
O
IMB_
FSR.
RPR
ODIS
IMB_
FSR.
WPR
ODIS
Resulting Security Level in RPA and WPA
Errored protection state (see below):
–
0
0
RPA = 1, WPA = 1.
–
0
1
RPA = 1, WPA = 0.
–
1
0
RPA = 0, WPA = 1.
–
1
1
RPA = 0, WPA = 0.
The Upper Layer “Protection State”
This layer consists mainly of the 4 fields DCF, DDF, WPA and RPA of the IMB_IMBCTR
register. These determine the effective protection state together with registers of the
lower layers. Some of the above mentioned command sequences directly influence
these fields as well. In order to increase the resistance against beaming or power supply
manipulation all 4 fields are coded with 2 bits. Generally “01” means active, “10” inactive
and the two other states “00” and “11” are invalid and are recognized as “attacked” state.
Effective Security Level
The effective security level based on these 4 double-bits is summarized in Table 3-5 and
Table 3-6. For the double bits the same short notation is used as before: 1 means active,
0 means inactive, ‘#’ means invalid and ‘–’ means do not care including invalid states.
Table 3-5
Effective Read Security
RPA
DCF
DDF
Security Level
0
–
–
No read protection.
1|#
0
0
No read protection.
–
1|#
Data reads prohibited.
1|#
–
Code fetches prohibited.
Table 3-6
Effective Write Security
WPA
RPA
Security Level
0
–
No write protection
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Memory Organization
Table 3-6
Effective Write Security (cont’d)
WPA
RPA
Security Level
1|#
1|#
Global write protection.
1|#
0
Sector specific write protection depending on
IMB_PROCONx.
To summarize:
•
•
Read protection is always globally affecting the whole flash memory range. Code
fetches and data reads can be separately controlled.
Write protection can be global when the read protection is effective or it can be
specific for each logical sector.
The lower and the middle security layers determine how the 4 effective IMB_IMBCTR
fields are preset, changed and how software can access them. This is discussed in the
following paragraphs.
Initialization of the Effective Security Level
After Application Reset protection is activated so that RPA, WPA, DDF and DCF are set.
During startup the IMB Core determines the stored security level as described in “The
Lower Layer “Physical State”” on Page 3-39 and sets IMB_FSR.PROIN and
IMB_FSR.PROINER and IMB_PROCONx as described in “The Middle Layer “Flash
State”” on Page 3-39. The IMB Core further initializes the IMB_IMBCTR fields RPA and
WPA according to the rules of Table 3-4.
The bits DDF and DCF of the IMB_IMBCTR are not initialized by the IMB Core. During
system startup they are initialized depending on the startup condition. If code fetching
starts in the flash memory then they are set to the inactive state. In all other cases they
are activated to prevent read access to the flash memory without proving password
knowledge.
Changing the Effective Security Level
During run-time the effective security level can be changed. This can be done by directly
writing to the IMB_IMBCTR register or indirectly by changing the bits of the middle layer
by commands as “Disable Write Protection” or even double indirectly by changing the
content of the security pages which changes bits in the middle layer and influences the
effective security level.
Writing directly to IMB_IMBCTR:
•
DCF and DDF can be deactivated only if RPA is inactive. They can always be
activated.
Indirectly by using a command sequence:
•
A successful “Disable Read Protection” sets RPRODIS and clears RPA.
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•
•
Memory Organization
A successful “Disable Write Protection” sets WPRODIS and clears WPA.
“Re-Enable Read/Write Protection” clears RPRODIS and WPRODIS and sets RPA
and WPA according to Table 3-4 depending on PROIN, PROINER and RPRO.
Double indirect by changing security pages. After executing a command sequence that
changed the content of a security page the IMB Core immediately reads back the pages
and determines all resulting security data as described for system startup in
“Initialization of the Effective Security Level” on Page 3-42. The examples in
“Protection Handling Examples” on Page 3-45 will show how this can be used for
installing and removing protection or changing passwords.
3.9.6.4
Reaction on Protection Violation
If software tries to violate the protection rules the following happens:
•
•
•
Reading data when read protection is effective: The bit IMB_FSR.PROER is set and
the Flash access trap can be triggered via the SCU if IMB_INTCTR.DPROTRP is 0.
Default data is delivered.
Fetching code when read protection is effective: the trap code “TRAP 15D” is
delivered instead.
Programming or erasing memory ranges when they are write protected: PROER is
set.
3.9.6.5
Layout of the Security Pages
The previous sections just mentioned the content of the security pages. This section
depicts their exact layout. Figure 3-8 depicts symbolically the layout of the security
pages 0 and 1.
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Security Page 0
Block 1…7 unused
unused
unused
unused
FF'0010 H
FF'0008 H
4 PassWords
FF'0000 H
unused
P2
P1
P0
FF'0090 H
unused
unused
unused
unused
unused
unused
RPRO
PW3
PW2
PW1
PW0
Block 0
3 PROCON
Words
Block 1
unused
unused
unused
unused
FF'0080 H
CH
CL
Block 0
FF'0020 H
FF'00FF H
Block 2…7 unused
FF'007F H
Security Page 1
Lock Code
(2 Words)
flash_security_page_layout.vsd
Figure 3-8
Layout of Security Pages
Generally the 16-bit words are stored as always in the XC2000 in little endian format.
•
•
•
•
The PWx words contain the passwords.
The double bit RPRO is stored as in the related ISFR IMB_FSR_PROT in the bits 15
and 14. The other bits of this word are unused and should be kept all-zero.
The PROCON data is stored as defined in the IMB_PROCONx (x=0-2) ISFR.
The lock code consists of the two words CL and CH. Both contain “AA55H” to form
the correct lock code.
All bytes of the used blocks of the security pages (block 0 and 1 of SecP0 and block 0 of
SecP1) are to be considered as “reserved” and must be kept erased, i.e. with all-zero
content. The unused blocks of the security pages (blocks 2 to 7 of SecP0 and blocks 1
to 7 of SecP1) shall be programmed with all-one data.
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Preliminary
3.9.7
Memory Organization
Protection Handling Examples
Some examples on how to work with the protection system.
Delivery State
The device is delivered in the “non-protected state”.
Security page 1 is erased (so it does not contain the “lock code” AA55AA55H).
Security page 0 is erased and so “invalid” but because SecP1 is erased this data is
anyhow not evaluated. Only its content is copied into corresponding the registers.
During startup the bits DDF and DCF are set depending on the start mode but as RPA
and WPA are inactive all accesses to the flash memory are allowed.
The data sectors of the flash memory are delivered in the erased state as well. All sectors
can be programmed. After uploading the software the customer can install write and read
protection.
First Time Password Installation
In order to install a password generally the lock code in SecP1 has to be erased. In this
case the code is not present.
After that SecP0 must be erased with “Erase Security Page” in order to be able to
change RPRO. Erasing SecP0 clears RPRO to “00B” which is an invalid state. After
finishing the erase command the IMB Core restores the IMB_FSR and IMB_IMBCTR
fields from the flash data.
Because no lock code is present in SecP1 the invalid state of RPRO has no effect on the
user visible protection. Still all parts of the flash memory can be written.
The second step is to program the information of SecP0 with the required security
information. Again the IMB Core reads immediately back the stored data and initializes
the security system. As SecP1 still does not contain the lock code the device stays in the
“non-protected” mode.
The security pages cannot be read directly by customer software. The data programmed
into SecP0 can therefore only be verified indirectly. The data of the RPRO and SnU fields
can be checked by reading the IMB_PROCON and IMB_FSR registers. The passwords
can be verified with the command “Disable Read Protection”. If the password does not
match the bit PROER is set. But because of the erased SecP1 the flash memory stays
writable. So after erasing SecP0 the correct password can be programmed again.
After the SecP0 was verified successfully SecP1 gets programmed with the lock code
AA55AA55H which enables the security settings of SecP0.
Because the password validation left RPRODIS set the command “Re-Enable Read/
Write Protection” must be used to finally activate the new protection.
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Memory Organization
Changing Passwords or Security Settings
Changing the passwords is a delicate operation. The interrelation of the two security
pages must be kept in mind.
Usually in the protected state the SecP1 contains the lock code. First write protection
must be disabled with the correct passwords. Then the lock code in SecP1 is erased. If
this operation was successful PROIN will be cleared by the IMB Core. Now SecP0 can
be safely erased.
From this point on the security pages are in the factory delivery state and the new
passwords and security settings can be installed as described above.
Attention: The number of times a security page may be changed is noted in the
datasheet.
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Preliminary
3.9.8
Memory Organization
EEPROM Emulation
The flash memory of the XC2000 is used for three purposes:
1. Storage of program code. Updates happen usually very seldom. The main criteria to
be fulfilled is a retention of the life-time of the product.
2. Storage of constant data: this data is stored together with program code. So this data
is very seldom updated. Endurance is of no issue here but retention identical to the
code memory is required.
3. Data updated during run-time: this might be data with a very high frequency of
updates like a mileage counter or access keys for key-less entry. Other data might
be changed only in case of failures and other data might only be transferred from
RAM to non-volatile memory before the system is powered down.
Especially for the third type of data the non-volatile memory needs EEPROM like
characteristics:
•
•
•
Fine program/erase granularity which is in EEPROMs typically 1 byte.
Higher endurance than the intrinsic endurance of flash cells.
Short program and erase duration per byte. Especially for storing data in an
emergency (e.g. power failure) short latencies might be required.
A basic requirement for changing data during run-time is that code execution can still
resume, especially interrupt requests must still be serviced. This requirement is fulfilled
in the XC2000 because all three flash modules work independently. If one is busy with
program or erase then code can still be executed from the other two.
The other requirements are more difficult to fulfill because the XC2000 does not have an
EEPROM available but only the flash memory with the already frequently mentioned
limitations: big program/erase granularity, moderately long program/erase duration,
limited cell endurance with reduced retention at high number of program/erase cycles,
pages not isolated but affected by drain disturbs.
In order to alleviate these effects on run-time storage of data software is used to emulate
EEPROM. There is quite a number of algorithms for efficiently using flash memory as
EEPROM. The following section describes one (the most simple) of these algorithms.
It should be noted that the XC2000 does not offer the customer any hardware means for
EEPROM emulation. All of the following must be realized by software.
3.9.8.1
The Traditional EEPROM Emulation
This algorithm was already used in the Pegasus devices. The key point is to solve the
limited endurance by storing data in N different physical places. In XC2000 the algorithm
would use N sequential pages or groups of pages. If data is currently stored in the page
“x” then the next program happens to the page “(x+1) mod N”. The software typically
stores the current address in a table in RAM to avoid searching for the page at every
access.
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In order to find the current data after boot-up every entry must be marked. Either it
contains a counter (from 0 to 2*N-1) or the old entries are invalidated by erasing the page
after programming the new one.
After boot-up the emulation driver software must recover this mapping information1). The
same must happen in case of power-down modes that shut-down the main memory.
As all involved pages are re-used cyclically the endurance from customer perspective is
increased by the factor N. N must be chosen high enough to fulfill endurance and
retention requirements. Disturbs in the group of N pages are no issue because they incur
at most N-1 disturbs before they get written with new data. Care must be taken however
if one sector accommodates different groups of pages with different update behavior. In
this case the updates of one group of pages could exceed the disturb limits of the other
group. So generally one sector should be used only by one such EEPROM cyclic buffer.
The algorithm keeps the old data until the new data is verified so power failure during
programming can only destroy the last update but the older data is still available. There
are still some issues with power failure that need special treatment:
•
•
Power is cut during programming: the following boot-up might find an apparently
correctly programmed page. However the cells might be not fully programmed and
thus have a much lower retention. The algorithm must detect this situation and
finalize the programming, e.g. with margin reads.
Power is cut during erase: the same as above can happen. Data may appear as
erased but the retention is lowered.
The algorithm can be improved to cover these cases as well. The easiest solution is to
use margin reads to verify the program or erase steps.
The main deficiency of the described algorithm is that the software designer is required
to plan the use of the flash memory thoroughly. The user has to choose the correct value
of N. Then all data has to be allocated to pages. Data sharing one page should have a
similar or better identical update pattern (otherwise unchanged data is unnecessarily
written). If one set of data does not fill a complete sector the available pages must be
possibly left unused because they might incur too many drain disturbs.
There are other algorithms that try to alleviate these efforts by monitoring the flash usage
and adapt automatically the assignment of data to flash cells.
1)
This time must be taken into account for calculating the startup duration.
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3.9.9
Memory Organization
Interrupt Generation
Long lasting processes (these are mainly: program page, erase page, erase sector and
margin changes) set the IMB_FSR.BUSY flag of one flash module when accepting the
request and reset this flag after finishing the process. Software is required to poll the
busy flag in order to determine the end of the operation. In order to release the software
from this burden an interrupt can be generated. If the interrupt is enabled by
IMB_INTCTRL.IEN then all transitions from 1 to 0 of one of the 3 IMB_FSR.BUSY flags
send an interrupt request.
The “Enter Page Mode” command sets BUSY only for around 100 clock cycles. It is
usually not advisable to enable the interrupt for this command.
The register IMB_INTCTR contains fields for the interrupt status “ISR”, an enable for the
interrupt request “IEN” and fields for clearing the status flag “ICLR” or setting if “ISET”. It
should be noted that the interrupt request is only sent when ISR becomes 1 and IEN was
already 1. No interrupt is sent when IEN becomes 1 when ISR was already 1 or both are
set to 1 at the same time.
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3.10
Memory Organization
On-Chip Program Memory Control
The internal memory block “IMB” contains all memories of the so called “on-chip program
memory area” in the address range from C0’0000H to FF’FFFFH. Included are the
program SRAM, the embedded flash memories and central control logic called “IMB
Core”.
In the XC2000 device the IMB contains the following memories:
•
•
764 KB flash memory in three independent modules.
64 KB program SRAM (see Section 3.4.1).
The IMB connects these memories to the CPU data bus and the instruction fetch bus.
Each memory can contain instruction code, data or a mixture of both. The IMB manages
accesses to the memories and supports flash programming and erase.
3.10.1
Overview
The Figure 3-9 shows how the IMB and its memories are integrated into the device
architecture. Only the main data streams are included. The data buses are usually
accompanied by address and control signals and check-sum data like parity or ECC.
IMB
C166SV2
DMU
(Data access)
Data
IMB
Core
16
64
CPU
PMU
(Instr fetch)
PSRAM
(Program
SRA M)
Instructions
Flash Memory
64
Flash Module 0
128
Flash Module 1
128
Flash Module 2
128
imb_block_diagram.vsd
Figure 3-9
IMB Block Diagram
The CPU has two independent busses. The instruction fetch bus is controlled by the
program management unit “PMU” of the CPU. It fetches instructions in aligned groups of
64 bits. The instruction fetch unit of the CPU predicts the outcome of jumps and fetches
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instructions on the predicted branch in advance. In case of a misprediction this interface
can abort outstanding requests and continues fetching on the correct branch. As the
CPU can consume up to one 32-bit instruction per clock cycle the performance of this
interface determines the CPU performance.
The data bus is controlled by the data management unit “DMU” of the CPU. It reads data
in words of 16 bits. Write accesses address as well 16-bit words but additional byte
enables allow changing single bytes.
Because of the CPU’s “von Neumann” architecture data and instructions (and “special
function registers” to complete the list) share a common address range. When
instructions are used as data (e.g. when copying code from an IO interface to the
PSRAM) they are accessed via the data bus. The pipelined behavior of the CPU can
cause that code fetches and data accesses are requested simultaneously. The IMB
takes care that accesses can perform concurrently if they address different memories or
flash modules.
Additional connections of the IMB to central system control units exist. These are not
shown in the block diagram.
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3.10.2
Memory Organization
Register Interface
The “IMB Registers” on Page 3-52 describes the special function registers of the IMB.
In “System Control Registers” on Page 3-63 the special function registers that
influence the IMB but are not allocated to the IMB address range are described.
3.10.2.1 IMB Registers
The section describes all IMB special function registers.
Table 3-7
Registers Overview
Register Short
Name
Register Long Name
Offset
Address
Page Number
IMB_IMBCTRL
IMB Control Low
FF FF00H
Page 3-52
IMB_IMBCTRH
IMB Control High
FF FF02H
Page 3-54
IMB_INTCTR
Interrupt Control
FF FF04H
Page 3-55
IMB_FSR_BUSY
Flash State Busy
FF FF06H
Page 3-57
IMB_FSR_OP
Flash State Operations
FF FF08H
Page 3-57
IMB_FSR_PROT
Flash State Protection
FF FF0AH
Page 3-59
IMB_MAR
Margin
FF FF0CH
Page 3-61
IMB_PROCON0
Protection Configuration 0
FF FF10H
Page 3-62
IMB_PROCON1
Protection Configuration 1
FF FF12H
Page 3-62
IMB_PROCON2
Protection Configuration 2
FF FF14H
Page 3-62
IMB Control
Global IMB control.
Both IMB_IMBCTRL and IMB_IMBCTRH are reset by an Application Reset.
The write access to both registers is controlled by the register security mechanism as
defined in the SCU chapter “Register Control” on Page 6-181. Please note that the
register write-protection is not activated automatically again after an access to
IMB_IMBCTR because this happens only for SCU internal registers.
IMB_IMBCTRL
IMB Control Low
15
14
13
12
ISFR (FF FF00H)
Reset value: 558CH
11
10
9
8
7
6
5
4
3
2
1
0
DDF
DCF
-
-
-
-
-
-
-
-
DLC
PF
WSFLASH
rw
rw
-
-
-
-
-
-
-
-
rw
rw
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Memory Organization
Field
Bits
Typ Description
WSFLASH
[2:0]
rw
Wait States for Flash Access
Number of wait cycles after which the IMB expects
read data from the flash memory.
This field determines as well the read timing of the
PSRAM in the flash emulation address range. See
“Flash Emulation” on Page 3-12.
Note: WSFLASH must not be 0. This value is
forbidden!
DLCPF
3
rw
Disable Linear Code Pre-Fetch
0:
“High Speed Mode”: When the next read
request will be delivered from the buffer and so
the flash memory would be idle, the IMB Core
autonomously increments the last address
and reads the next 128-bit block from the flash
memory.
1:
“Low Power Mode”: This feature is disabled.
Usually for code with power minimization
requirements or for code with short linear code
sections this feature should be disabled (DLCPF =
1). Enabling this feature is only advantageous for
code section with longer linear sequences. With
lower values of WSFLASH the performance gain of
DLCPF=0 is reduced. In case of low WSFLASH
settings DLCPF=1 might even lead to better
performance than with linear code pre-fetch.
DCF
[13:12] rw
Disable Code Fetch from Flash Memory
“01”: Short notation DCF = 1. If RPA = 1 instructions
cannot be fetched from flash memory. If RPA
= 0 this field has no effect.
“10”: Short notation DCF = 0. Instructions can be
fetched independent of RPA.
“00” | “11”: Illegal state. Has the same effect as “01”.
This state can only be left by an Application
Reset.
During startup or test mode or when RPA = 0
software can change this field to any value.
Otherwise code fetch can only be disabled but not
enabled anymore until the next Application Reset.
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Field
Bits
Typ Description
DDF
[15:14] rw
Disable Data Read from Flash Memory
“01”: Short notation DDF = 1. If RPA = 1 data cannot
be read from flash memory. If RPA = 0 this
field has no effect.
“10”: Short notation DDF = 0. Data can be read
independent of RPA.
“00” | “11”: Illegal state. Has the same effect as “01”.
This state can only be left by an Application
Reset.
During startup or test mode or when RPA = 0
software can change this field to any value.
Otherwise data reads can only be disabled but not
enabled anymore until the next Application Reset.
IMB control high word. The WPA and RPA fields are described in “Protection Handling
Details” on Page 3-38.
IMB_IMBCTRH
IMB Control High
15
14
13
ISFR (FF FF02H)
12
11
10
9
8
7
6
5
4
PSPROT
–
–
–
–
RPA
WPA
rw
–
–
–
–
rh
rh
Field
Bits
Typ Description
WPA
[1:0]
rh
User’s Manual
MemoryX2K, V1.1
Reset value: 0005H
3
2
1
0
Write Protection Activated
“01”: Short notation WPA = 1. The write protection
of the flash memory is activated.
“10”: Short notation WPA = 0. The write protection
is not activated.
“00” | “11”: Illegal state. Same effect as “01”. The
illegal state can only be left by an Application
Reset.
This field is only changed by the IMB Core. Software
writes are ignored.
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Field
Bits
Typ Description
RPA
[3:2]
rh
Read Protection Activated
“01”: Short notation RPA = 1. The read protection of
the flash memory is activated.
“10”: Short notation RPA = 0. The read protection is
not activated.
“00” | “11”: Illegal state. Same effect as “01”. The
illegal state can only be left by an Application
Reset.
This field is only changed by the IMB Core. Software
writes are ignored.
PSPROT
[15:8]
rw
PSRAM Write Protection
This 8-bit field determines the address up to which
the PSRAM is write protected.
The start address of the writable range is E0’0000H
+ 1000H*PSPROT. The end address is determined
by the implemented memory. The equivalent range
in the PSRAM area with flash access timing is
protected as well. Here the writable range starts at
E8’0000H + 1000H*PSPROT and ends at E8’FFFFH
for XC2000.
So with PSPROT=00H the complete PSRAM is
writable. In case of XC2000 with PSPROT=10H or
bigger the complete implemented PSRAM is writeprotected.
Interrupt Control
Interrupt control and status.
Reset by Application Reset.
IMB_INTCTR
Interrupt Control
ISFR (FF FF04H)
15
14
13
12
11
ISR
PSE
R
–
–
–
rh
rh
–
–
–
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9
8
PSE
RCL ISET ICLR
R
w
w
w
3-55
Reset value: 0000H
7
6
5
4
–
–
–
–
–
–
–
–
3
2
1
0
DPR
DDD DIDT
OTR
IEN
TRP RP
P
rw
rw
rw
rw
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
Field
Bits
Typ Description
IEN
0
rw
Interrupt Enable
If set, the interrupt signal of the IMB gets activated
when ISR is set.
DIDTRP
1
rw
Disable Instruction Fetch Double Bit Error Trap
If set, a double bit ECC error does not cause the
replacement of the fetched data by a trap instruction.
DDDTRP
2
rw
Disable Data Read Double Bit Error Trap
If set, a double bit ECC error during data read does
not trigger the Flash access hardware trap.
DPROTRP
3
rw
Disable Protection Trap
If set, a read request from read protected flash
memory does not trigger the Flash access hardware
trap.
ICLR
8
w
Interrupt Clear
When written with 1 the ISR is cleared. Reading this
bit delivers always 0. Writing a 0 is ignored.
ISET
9
w
Interrupt Set
When written with 1 the ISR is set and if IEN is set
the interrupt signal is activated. Reading this bit
delivers always 0. Writing a 0 is ignored. When
writing ISET and ICLR to 1 concurrently ISET takes
priority so ISR is set.
PSERCLR
10
w
Clear PSRAM Error Flag
When written with 1 the PSER is cleared. Reading
this bit delivers always 0. Writing a 0 is ignored.
PSER
14
rh
PSRAM Error Flag
This flag is set when write requests to the write
protected or not implemented PSRAM range are
detected. This flag can be cleared by writing 1 to
PSERCLR.
ISR
15
rh
Interrupt Service Request
If set, it indicates that at least one IMB_FSR.BUSY
bit changed from 1 to 0. If IEN was set an interrupt
request is sent to the interrupt controller. After
servicing the interrupt the software handler clears
this flag by writing a 1 to ICLR.
User’s Manual
MemoryX2K, V1.1
3-56
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
Flash State
Flash state. Split into 3 registers IMB_FSR_BUSY, IMB_FSR_OP, and
IMB_FSR_PROT. The protection relevant fields or IMB_FSR_PROT are described in
“Protection Handling Details” on Page 3-38.
The registers are reset by the Application Reset with the exception of “ERASE”, “PROG”,
and “OPER”. These three fields are only reset by a System Reset.
IMB_FSR_BUSY
Flash State Busy
ISFR (FF FF06H)
15
14
13
12
11
–
–
–
–
–
–
–
–
–
–
10
9
8
Reset value: 0000H
7
6
5
4
3
2
1
PAGE
–
–
–
–
–
BUSY
rh
–
–
–
–
–
rh
0
Field
Bits
Typ Description
BUSY
[2:0]
rh
Busy
A flash module is busy with a task. Each bit position
corresponds to one of the 3 flash modules. The task
is indicated by the bits MAR, POWER, ERASE or
PROG of IMB_FSR_OP. BUSY is automatically
cleared when the task has finished. The
corresponding task indication is not cleared in order
to allow an interrupt handler to determine the
finished task.
PAGE
[10:8]
rh
Page Mode Indication
Set as long the corresponding flash module is in
page mode. Page mode is entered by the “Enter
Page Mode” commands and finished by a “Program
Page” command. The page mode can be also left by
a “Reset to Read” command. Also an Application
Reset clears this bit.
IMB_FSR_OP
Flash State Operations
ISFR (FF FF08H)
15
14
13
12
11
10
9
8
7
6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
User’s Manual
MemoryX2K, V1.1
3-57
Reset value: 0000H
5
4
3
2
1
0
OPE SQE
POW ERA PRO
MAR
R
R
ER SE
G
rh
rh
rh
rh
rh
rh
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
Field
Bits
Typ Description
PROG
0
rh
Program Task Indication
This bit is set when a program task is started. The
affected flash module is indicated by a BUSY bit.
The PROG bit is not automatically reset but must be
cleared by a “Clear Status” command. This bit is not
cleared by an Application Reset but only by a
System Reset.
ERASE
1
rh
Erase Task Indication
This bit is set when an erase task is started. The
affected flash module is indicated by a BUSY bit.
The ERASE bit is not automatically reset but must be
cleared by a “Clear Status” command. This bit is not
cleared by an Application Reset but only by a
System Reset.
POWER
2
rh
Power Change Indication
This bit indicates that a flash module is in its startup
phase or in a shutdown phase. The BUSY bits
indicate which flash module is busy. This bit is not
automatically reset but must be cleared by a “Clear
Status” command.
MAR
3
rh
Margin Change Indication
If a read margin modification is requested this bit is
set together with the corresponding BUSY bit. The
BUSY bit is cleared when the margin change is
effective and the flash module can be read again.
The MAR bit must be cleared by a “Clear Status”
command.
SQER
4
rh
Sequence Error
This bit is set by a errored command sequence or a
command that is not accepted. It is cleared by “Clear
Status” and “Reset to Read”.
User’s Manual
MemoryX2K, V1.1
3-58
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
Field
Bits
Typ Description
OPER
5
rh
IMB_FSR_PROT
Flash State Protection
15
14
13
12
RPRO
–
–
rh
–
–
11
Operation Error
The IMB Core maintains internal bits that are set
when starting a program or erase process. They are
cleared when this process finishes. These bits are
not reset by an Application Reset but only by a
System Reset. If one of these bits is set after
Application Reset the IMB Core sets OPER. So this
signals that a running erase or program process was
interrupted by an Application Reset.
The OPER is cleared by “Reset to Read”, “Clear
Status” or a System Reset.
ISFR (FF FF0AH)
10
9
8
DDB DSB IDBE ISBE
ER ER
R
R
rh
rh
rh
rh
Reset value: x000H
7
6
5
–
–
–
–
–
–
4
3
2
1
0
PRO WPR RPR PROI PROI
ER ODIS ODIS NER N
rh
rh
rh
rh
rh
Field
Bits
Typ Description
PROIN
0
rh
Flash Protection Installed
Modified by the IMB Core. Cleared by Application
Reset.
PROINER
1
rh
Flash Protection Installation Error
Modified by the IMB Core. Cleared by Application
Reset.
RPRODIS
2
rh
Read Protection Disabled
The read protection was temporarily disabled with
the “Disable Read Protection” command. Modified
by the IMB Core. Cleared by Application Reset.
WPRODIS
3
rh
Write Protection Disabled
The write protection was temporarily disabled with
the “Disable Write Protection” command. Modified
by the IMB Core. Cleared by Application Reset.
User’s Manual
MemoryX2K, V1.1
3-59
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
Field
Bits
Typ Description
PROER
4
rh
Protection Error
Set by a violation of the installed protection. Reset by
the “Clear Status” and “Reset to Read” commands
or an Application Reset.
ISBER
8
rh
Instruction Fetch Single Bit Error
Set if during instruction fetch a single-bit ECC error
was detected (and corrected). Reset by “Clear
Status” or “Reset to Read” commands or an
Application Reset.
IDBER
9
rh
Instruction Fetch Double Bit Error
Set if during instruction fetch a double-bit ECC error
was detected (and not corrected). Reset by “Clear
Status” or “Reset to Read” commands or an
Application Reset.
DSBER
10
rh
Data Read Single Bit Error
Same as ISBER for data reads.
DDBER
11
rh
Data Read Double Bit Error
Same as IDBER for data reads.
RPRO
[15:14] rh
Read Protection Configuration
This field is copied by the IMB Core from the
corresponding field in the security page 0. After
Application Reset read protection is activated.
Margin Control
Read margin control. Each field corresponds to one flash module. A hard read 0 detects
not completely erased cells. These are read as “1”. A hard read 1 detects not completely
programmed cells. These are read as “0”. Read margin changes are caused by the
command sequence “Change Read Margin”. The resulting read margin is reflected in
this status register.
The command sequences “Program Page”, “Erase Sector”, “Erase Page” and “Erase
Security Page” resets the read margin back to “normal”. The same happens in case of
a flash wake-up.
Reset by Application Reset.
User’s Manual
MemoryX2K, V1.1
3-60
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
IMB_MAR
Margin Control
ISFR (FF FF0CH)
8
7
6
Reset value: 0000H
15
14
13
12
11
10
9
5
4
3
2
1
–
–
–
–
–
–
–
HREAD2
HREAD1
HREAD0
–
–
–
–
–
–
–
rh
rh
rh
Field
Bits
Typ Description
HREAD0
[2:0]
rh
Hard Read 0
Active read margin of flash module 0.
“000”:Normal read.
“001”:Hard read 0.
“010”: Alternate hard read 0 (usually harder than
001).
“101”:Hard read 1.
“110”: Alternate hard read 1 (usually harder than
101).
other codes:Reserved.
HREAD1
[5:3]
rh
Hard Read 1
Same for flash module 1.
HREAD2
[8:6]
rh
Hard Read 2
Same for flash module 2.
0
Protection Configuration
Protection configuration register of each implemented flash module. In XC2000
PROCON0, PROCON1 and PROCON2 are implemented. PROCON0 is described
below. PROCON1 (at address FF’0012H) and PROCON2 (at address FF’F014H) have
the same functionality for the other two flash modules. The logical sector numbering is
depicted in Figure 3-6.
Each bit of the PROCONs is related to a logical sector. If it is cleared the write access to
the corresponding logical sector (this means to the range of physical sectors) is locked
under the conditions that are documented in “Protection Handling Details” on
Page 3-38. The PROCON registers are exclusively modified by the IMB Core.
Reset by Application Reset.
User’s Manual
MemoryX2K, V1.1
3-61
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
IMB_PROCONx (x=0-2)
Protection Configuration.
ISFR (FF FF10H+2*x)
15
14
13
12
11
10
–
–
–
–
–
–
–
–
–
–
–
–
9
8
7
5
4
3
2
1
0
S9U S8U S7U S6U S5U S4U S3U S2U S1U S0U
rh
rh
rh
Field
Bits
Typ Description
SsU (s=0-9)
s
rh
User’s Manual
MemoryX2K, V1.1
6
Reset value: 0000H
rh
rh
rh
rh
rh
rh
rh
Sector 0 to 9 Unlock
s:
Logical sector s of flash module 0 is writeprotected.
3-62
V1.0, 2007-06
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System Units (Vol. 1 of 2)
Preliminary
Memory Organization
3.10.2.2 System Control Registers
These registers are used to wakeup and shutdown parts of the memory sub-system.
Table 3-8
Registers Address Space
Module
Base Address
End Address
Note
SCU
0000H
0FFFH
SCU Module
Table 3-9
Registers Overview
Register Short
Name
Register Long Name
Offset
Address
Page Number
MEM_KSCCFG Memory Kernel Control
F012H
Page 3-63
FL_KSCCFG
FE22H
Page 3-64
Flash Kernel Control
Memory Kernel Configuration
This register controls the shutdown request of the processor sub-system units DMU,
PMU, IMB and EBC (see “Processor Sub-System Shutdown” on Page 3-67). The
layout of this register is identical to the other KSCCFGs but only the field COMCFG may
be used. Two values of this field might be used: 00B means that the “Clock-off Mode”
does not trigger a shutdown of the processor sub-system. This may be used only if the
system clock of DMP_1 is not disabled in the “Clock-off Mode”.
The second useful value is 10B. This value must be used in all cases when the “Clockoff Mode” is accompanied by disabling the system clock of the DMP_1. In this case the
sequence described in “Processor Sub-System Shutdown” on Page 3-67 must be
performed.
This register gets is reset by an Application Reset. Attention: the reset value of
COMCFG is 00B.
MEM_KSCCFG
Memory Kernel State Con
15
14
BP
COM
–
w
–
13
12
ESFR (F012H/06H)
11
10
COMCFG
–
–
rw
–
–
9
8
7
6
–
–
–
–
–
–
–
–
Field
Bits
Type
Description
1
0
rw
Has to be written to 1.
User’s Manual
MemoryX2K, V1.1
Reset Value: 0001H
3-63
5
4
3
2
1
0
–
–
1
–
–
rw
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
Field
Bits
Type
COMCFG
[13:12] rw
Clock Off Mode Configuration
This bit field defines if the shutdown request is
activated in clock-off mode.
If COMCFG[13] is 1 the shutdown request is
activated in clock-off mode (i.e. CR = 10).
COMCFG[12] has no functionality.
BPCOM
15
Bit Protection for COMCFG
This bit enables the write access to the bit field
COMCFG. It always reads 0. It is only active during
the write access cycle.
0
The bit field COMCFG is not changed.
1
The bit field COMCFG is updated with the
written value.
w
Description
Flash Kernel Configuration
This register controls the power-down request of the flash module. When configuring this
register care must be taken not to enable a powered-down flash module when the
operating voltage is not sufficient. In this case all CFG fields should contain 10B.
This register is reset by an Application Reset.
FL_KSCCFG
Flash Kernel State Con.
15
14
BP
COM
–
w
–
13
12
11
BP
COMCFG
SUM
rw
w
SFR (FE22H/11H)
10
–
–
9
8
7
BP
SUMCFG
NOM
rw
w
6
Reset Value: 0001H
5
4
3
2
–
NOMCFG
–
–
rw
–
1
BP
MOD
MOD
EN
EN
w
rw
Field
Bits
Type
Description
MODEN
0
rw
Module Enable
This bit can directly set the power-down request.
0
The power-down request is activated.
1
This field has no effect.
User’s Manual
MemoryX2K, V1.1
3-64
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
Field
Bits
Type
Description
BPMODEN
1
w
Bit Protection for MODEN
This bit enables the write access to the bit MODEN.
It always reads 0. It is only active during the write
access cycle.
0
The bit MODEN is not changed.
1
The bit MODEN is updated with the written
value.
NOMCFG
[5:4]
rw
Normal Operation Mode Configuration
This bit field defines if the power-down request is
activated in normal operation mode.
If NOMCFG[5] is 1 the power-down request is
activated in normal mode (i.e. CR = 00 or 11).
NOMCFG[4] has no functionality.
BPNOM
7
w
Bit Protection for NOMCFG
This bit enables the write access to the bit field
NOMCFG. It always reads 0. It is only active during
the write access cycle.
0
The bit field NOMCFG is not changed.
1
The bit field NOMCFG is updated with the
written value.
SUMCFG
[9:8]
rw
Suspend Mode Configuration
This bit field defines if the power-down request is
activated in suspend mode (which makes only sense
if it is activated in normal mode as well).
If SUMCFG[9] is 1 the power-down request is
activated in shutdown mode (i.e. CR = 01).
SUMCFG[8] has no functionality.
BPSUM
11
w
Bit Protection for SUMCFG
This bit enables the write access to the bit field
SUMCFG. It always reads 0. It is only active during
the write access cycle.
0
The bit field SUMCFG is not changed.
1
The bit field SUMCFG is updated with the
written value.
User’s Manual
MemoryX2K, V1.1
3-65
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
Field
Bits
COMCFG
[13:12] rw
Clock Off Mode Configuration
This bit field defines if the power-down request is
activated in clock-off mode.
If COMCFG[13] is 1 the power-down request is
activated in clock-off mode (i.e. CR = 10).
COMCFG[12] has no functionality.
BPCOM
15
Bit Protection for COMCFG
This bit enables the write access to the bit field
COMCFG. It always reads 0. It is only active during
the write access cycle.
0
The bit field COMCFG is not changed.
1
The bit field COMCFG is updated with the
written value.
User’s Manual
MemoryX2K, V1.1
Type
w
Description
3-66
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
3.10.3
Memory Organization
Startup, Shutdown
This section describes only shortly the shutdown and wake-up of the memory and
processor sub-system. The use of this functionality is delicate and should be done with
a software low-level driver according to Infineon recommendations.
3.10.3.1 Processor Sub-System Shutdown
The IMB with its memories PSRAM and the Flash memory is — from a programmers
point of view — part of the processor sub-system. This contains additionally the CPU
with its memories, the DMU, the PMU, and the EBC. All these modules must be active
(i.e. have a sufficient power supply and a running clock) to execute software.
Consequently, their shutdown is controlled by a common KSCCFG called
MEM_KSCCFG (see Page 3-63).
Before stopping the system clock or performing a power mode change the complete
processor sub-system must be shutdown cleanly. This requires the following steps:
•
•
•
•
The CPU executes the IDLE instruction. This instruction cleans up the processor
pipeline and the CPU stops fetching instructions. After that the idle state is reported
to the system control unit specifically the PSC (see “Power State Controller (PSC)”
on Page 6-128).
The PSC must be configured so that — triggered by the IDLE — it performs a
sequence A transition. The sequence A entry triggers the “Clock-off Mode” request
by the GSC.
The MEM_KSCCFG.COMCFG must be set to 10B so that the “Clock-off Mode”
request of the GSC activates the shutdown request of the processor sub-system
modules DMU, PMU, IMB and EBC. These acknowledge the request after finishing
all outstanding tasks.
The PSC can after that disable the system clock of DMP_1.
The system control unit must not be configured to disable the system clock without
performing this sequence. The danger is that the clock is switched off before the last
tasks of the processor sub-system have finished. Mainly affected are the following longer
lasting tasks:
•
•
•
Write accesses to the PSRAM: the last write access could be dropped.
Longer lasting processes in the Flash (e.g. erase sector, program page, …).
Write accesses via the EBC (e.g. to slow external memories): switching off the clock
while the external bus is active could even lead to timing violations at external
memories with loss of data.
The details of the registers MEM_KSCCFG and the FL_KSCCFG are described in
“System Control Registers” on Page 3-63.
User’s Manual
MemoryX2K, V1.1
3-67
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Memory Organization
3.10.3.2 Flash Module Power-Down
Before the power supply voltage of the IMB is reduced below 1.5 V the flash arrays must
be powered down. The SCU controls the flash power-down with a dedicated kernel state
control register, the FL_KSCCFG. The flash power-down is requested by the SCU when
FL_KSCCFG.MODEN is 0 (the flash is disabled) or in case of a global clock-off mode
when the field FL_KSCCFG.COMCFG contains “10” or “11”. If the MSB of the SUMCFG
or NOMCFG is 1 the flash power-down can also be requested in normal mode or
suspend mode.
A power-down request by the SCU is forwarded by the IMB Core to all flash modules.
The rest of the IMB is not affected by a flash power-down. So the device can continue
operation with the PSRAM. The IMB Core waits until all running processes have finished
in the flash modules before it acknowledges the power-down request. If the IMB Core
has received the beginning of a command sequence and is waiting for the rest when
receiving the power-down request it resets it command interpreter and performs a
“Reset to Read”. All accesses arriving after or with the power down request are ignored
(read accesses return default data as defined for not-implemented memory ranges —
see Table 3-10 “IMB Error Reporting” on Page 3-69). Accesses arriving after or with
a power down request should be considered as system control failure. Either the SCU
hardware or its low-level drivers must ensure that this case does not happen.
User’s Manual
MemoryX2K, V1.1
3-68
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
3.10.4
Memory Organization
Error Reporting Summary
The Table 3-10 summarizes the types of detected errors and the possible reactions.
Table 3-10
IMB Error Reporting
Error
Reaction
Data read from PSRAM with parity error.
If PECON.PEENPS:
HW trap (see Section 3.12).
Instruction fetch from PSRAM with parity
error.
If PECON.PEENPS:
HW trap (see Section 3.12).
Data read from flash memory with single bit Silently corrected. Bit IMB_FSR.DSBER
error.
set.
Data read from flash memory with double
bit error.
Bit IMB_FSR.DDBER set.
If IMB_INTCTR.DDDTRP = 0:
Flash access trap (see Section 6.11.4)
and default data is delivered.
Instruction fetch from flash memory with
single bit error.
Silently corrected. Bit IMB_FSR.ISBER
set.
Instruction fetch from flash memory with
double bit error.
Bit IMB_FSR.IDBER set.
If IMB_INTCTR.DIDTRP = 0:
“TRAP 15D” delivered instead of corrupted
data.
Data read from protected flash memory.
IMB_FSR.PROER set.
If IMB_INTCTR.DPROTRP = 0:
Flash access trap (see Section 6.11.4)
and default data is delivered.
Instruction fetch from protected flash
memory.
“TRAP 15D” delivered.
Program/erase request of write protected
flash range.
Only bit PROER in IMB_FSR set.
Data read or instruction fetch from busy
flash memory.
Read access stalled until end of busy
state.
Instruction fetch from ISFR addresses.
Default data (“TRAP 15D”) delivered.
Data read from not implemented ISFRs.
Default data delivered.
Data writes to not implemented ISFRs.
Silently ignored.
Data read from not implemented address
range.
Unpredictable. Mirrored data from other
memories might be returned or default
values.
User’s Manual
MemoryX2K, V1.1
3-69
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 3-10
Memory Organization
IMB Error Reporting (cont’d)
Error
Reaction
Instruction fetch from not implemented
address range.
Unpredictable. Mirrored data from other
memories might be returned or default
values.
Data written to not implemented PSRAM or Bit IMB_INTCTR.PSER set.
write protected PSRAM address range
Flash access trap (see Section 6.11.4)
(both determined by
and no data is changed in the PSRAM.
IMB_IMBCTR.PSPROT).
Program or erase command targeting not
implemented flash memory.
Unpredictable. Access is ignored or
mirrored into implemented flash
memory1).
Data read from powered-down flash
modules.
Considered as access to not-implemented
memory range. Default data or data from
implemented flash modules will be
returned.
Instruction fetch from powered-down flash
modules.
Considered as access to not-implemented
memory range. Default data (“TRAP 15D”)
will be returned or data from implemented
flash modules.
Program or erase command targeting
powered-down flash modules.
Silently ignored.
Shutdown or power-down request received The command interpreter is reset and a
while the command sequence interpreter is “Reset to Read” command sequence is
waiting for the last words of a command
executed.
sequence.
1)
The flash protection can not be by-passed by accessing the reserved memory ranges.
3.11
Data Retention Memories
This section describes the usage of the two special purpose data memories Stand-By
RAM (SBRAM) and Marker Memory (MKMEM). Both are supplied by the wake-up power
domain (DMP_M) and retain their data while the system power domain (DMP_1) is
switched off.
User’s Manual
MemoryX2K, V1.1
3-70
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
3.11.1
Memory Organization
Stand-By RAM Accesses
The SBRAM is not mapped into the address range of the processor. All accesses are
done via the 4 SFRs SBRAM_WADD, SBRAM_RADD, SBRAM_DATA0 and
SBRAM_DATA1. The following access options exist:
•
•
•
•
Write without automatic increment of the write address pointer:
The SW has to write the target address first to WADD and then the data to DATA0.
The data written to DATA0 is transferred to the indicated address in the SBRAM if (at
least) the lower byte of DATA0 is written. If DATA0 is written again the same address
in SBRAM is used for data storage. Bit WADD.MOD is cleared by a write access to
DATA0.
Write with automatic increment of the write address pointer:
The SW has to write the first target address to WADD and thereafter the data block
can be written word by word to DATA1. The data written to DATA1 is transferred to
the indicated address in the SBRAM if (at least) the lower byte of SRDR1 is written.
In parallel to the data storage in the SBRAM, the write address pointer WADD.WPTR
is automatically incremented by 1 (one word) for the next data to be stored. The
address pointer automatically does a wrap-around after reaching its maximum value
and in this case, bit WADD.WA is set. Bit WADD.MOD is set by a write access to
DATA1.
Read without automatic increment of the read address pointer:
The SW has to write the target address first to RADD and then can read the data from
DATA0. If DATA0 is read again the same address in SBRAM is read out. Bit
RADD.MOD is cleared by a read access to DATA0.
Read with automatic increment of the read address pointer:
The SW has to write the first target address to RADD and can then read the data
block word by word from DATA1. In parallel to the read action from SBRAM, the read
address pointer RADD.RPTR is automatically incremented by 1 (one word) for the
next data to be read. The address pointer automatically does a wrap-around after
reaching its maximum value and in this case, bit RADD.WA is set. Bit RADD.MOD is
set by a read access to DATA1.
The automatic increment accesses allow performing back-to-back data writes and
reads.
Note: Because read accesses to SBRAM_DATA0 and SBRAM_DATA1 return the value
that has been pre-read upon the most recent update of register SBRAM_RADD,
any data written to location @SBRAM_RADD can only be read back after
SBRAM_RADD has been updated with the very same address (either explicitly by
writing to it or implicitly via the auto-increment function). Generally when switching
from write to read accesses SBRAM_RADD should be written again before
reading SBRAM_DATAx.
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Preliminary
3.11.2
Memory Organization
Stand-By RAM Registers
This section describes the SBRAM register interface in detail.
3.11.2.1 SBRAM Read Address Register
This register defines the word location to be read.
Reset by Power-On Reset.
SBRAM_RADD
SBRAM Read Address Register SFR (FEDCH/6EH)
15
14
13
12
MOD WA
rwh
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
0
RPTR
0
r
rwh
r
rwh
Field
Bits
Type
Description
RPTR
[9:1]
rwh
Read Pointer
Selects the word address to be read from the
SBRAM. It is automatically incremented by 1 (i.e. to
the next word) when register DATA1 is read.
WA
14
rwh
Wrap Around
This bit indicates if a wrap-around of the read pointer
RPTR occurred due to the automatic address
increment.
0
An address wrap-around has not occurred.
1
An address wrap-around has been detected. It
has to be cleared by SW.
MOD
15
rwh
Modification
This bit indicates whether the last read access to
SBRAM data lead to an automatic increment of
RPTR.
0
The last data read access was done to DATA0
and RPTR was not modified automatically.
1
The last data read access was done to DATA1
and RPTR was automatically incremented by
1.
0
0,
r
[13:10]
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MemoryX2K, V1.1
Reserved
Read as 0; should be written with 0.
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Preliminary
Memory Organization
3.11.2.2 SBRAM Write Address Register
This register defines the word location to be written.
Reset by Power-On Reset.
SBRAM_WADD
SBRAM Write Address Register SFR (FEDEH/6FH)
15
14
13
12
MOD WA
rwh
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
0
WPTR
0
r
rwh
r
rwh
Field
Bits
Type
Description
WPTR
[9:1]
rwh
Write Pointer
Selects the write word address within the SBRAM.
It is automatically incremented by 1 if register DATA1
is written.
WA
14
rwh
Wrap-Around
This bit indicates if a wrap-around of the write pointer
WPTR occurred due to the automatic address
increment.
0
An address wrap-around has not occurred.
1
An address wrap-around has been detected. It
has to be cleared by SW.
MOD
15
rwh
Modification
This bit indicates whether the last write access to
SBRAM data lead to an automatic increment of
WPTR.
0
The last data write access was done to DATA0
and WPTR was not modified automatically.
1
The last data write access was done to DATA1
and WPTR was automatically incremented by
1.
0
0,
r
[13:10]
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MemoryX2K, V1.1
Reserved
Read as 0; should be written with 0.
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Preliminary
Memory Organization
3.11.2.3 SBRAM Data Register 0
This register delivers the read data and is the target for the write data without
modification of the respective address pointer.
Reset by Power-On Reset.
SBRAM_DATA0
SBRAM Data Register 0
15
14
13
12
11
SFR (FEE0H/70H)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
DATA
rwh
Field
Bits
Type
Description
DATA
[15:0]
rwh
SBRAM Data
This bit field contains the data read during the latest
SBRAM read access and is the target for the data to
be written to SBRAM.
A read access always delivers the data stored in the
SBRAM at the address indicated by the read pointer
RADD.RPTR.
A write access of (at least) the low byte leads to the
storage of the written data at the address indicated
by the write pointer WADD.WPTR.
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Preliminary
Memory Organization
3.11.2.4 SBRAM Data Register 1
This register delivers the read data and is the target for the write data with modification
of the respective pointer.
Reset by Power-On Reset.
SBRAM_DATA1
SBRAM Data Register 1
15
14
13
12
11
SFR (FEE2H/71H)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
DATA
rwh
Field
Bits
Type
Description
DATA
[15:0]
rwh
SBRAM Data
This bit field contains the data read during the latest
SBRAM read access and is the target for the data to
be written to SBRAM.
A write access of (at least) the low byte leads to the
storage of the written data at the address indicated
by the write pointer WADD.WPTR.
A read access always delivers the data stored in the
SBRAM at the address indicated by the read pointer
RADD.RPTR.
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Preliminary
3.11.3
Memory Organization
Marker Memory (MKMEM)
The marker memory simply consists of two SFRs located in the DMP_M power domain
for free usage of the SW.
3.11.3.1 Marker Memory SFR
Reset by Power-On Reset.
MKMEM0
Marker Memory 0 Register
MKMEM1
Marker Memory 1 Register
15
14
13
12
11
10
SFR (FED0H/68H)
Reset Value: 0000H
SFR (FED2H/69H)
Reset Value: 0000H
9
8
7
6
5
4
3
2
1
0
MARKER
rw
Field
Bits
Type
Description
MARKER
[15:0]
rw
Marker Content
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Preliminary
3.12
Memory Organization
Memory Parity Error Handling
The on-chip RAM modules check parity information during read accesses and generate
parity bits during write accesses. A parity error is noted in the register bits PECON.PEFx
separately for each implemented memory.
If enabled by the register bits PECON.PEENx the setting of a PECON.PEFx bit can
trigger a trap request. As documented in “SCU Trap Generation” on Page 6-200 by
default the requested trap is the ACER trap.
In order to handle the case that the ACER trap handler code itself incurrs a parity error
a reset can be triggered. If the bit TFR.ACER is set which indicates that the ACER trap
handler code is executed a parity error trap request triggers the reset action defined by
RSTCON1.MP.
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Preliminary
3.12.1
Memory Organization
Parity Control Registers
The register PECON controls the functional parity check mechanism.
This register is reset by a System Reset. An Application Reset clears only the enable bits
PEENx but not the error flags PEFx.
PECON
Parity Error Control Register
15
14
13
12
11
10
ESFR (F0C4H/41H)
9
8
PEF PEF PEF PEF PEF PEF PEF PEF
SB MC U2 U1 U0 PS DS DP
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Reset Value: 0000H
7
6
5
4
3
2
1
0
PE
EN
SB
rw
PE
EN
MC
rw
PE
EN
U2
rw
PE
EN
U1
rw
PE
EN
U0
rw
PE
EN
PS
rw
PE
EN
DS
rw
PE
EN
DP
rw
Field
Bits
Type
Description
PEENDP
0
rw
Parity Error Trap Enable for Dual Port Memory
0
No Parity trap is requested for dual port
memory parity errors
1
A Parity trap is requested for dual port memory
parity errors
PEENDS
1
rw
Parity Error Trap Enable for Data SRAM
0
No Parity trap is requested for data SRAM
parity errors
1
A Parity trap is requested for data SRAM parity
errors
PEENPS
2
rw
Parity Error Trap Enable for Program SRAM
0
No Parity trap is requested for program SRAM
parity errors
1
A Parity trap is requested for program SRAM
parity errors
PEENU0
3
rw
Parity Error Trap Enable for USIC0 Memory
0
No Parity trap is requested for USIC0 memory
parity errors
1
A Parity trap is requested for USIC0 memory
parity errors
PEENU1
4
rw
Parity Error Trap Enable for USIC1 Memory
0
No Parity trap is requested for USIC1 memory
parity errors
1
A Parity trap is requested for USIC1 memory
parity errors
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Preliminary
Memory Organization
Field
Bits
Type
Description
PEENU2
5
rw
Parity Error Trap Enable for USIC2 Memory
0
No Parity trap is requested for USIC2 memory
parity errors
1
A Parity trap is requested for USIC2 memory
parity errors
PEENMC
6
rw
Parity Error Trap Enable for MultiCAN Memory
0
No Parity trap is requested for MultiCAN
memory parity errors
1
A Parity trap is requested for MultiCAN
memory parity errors
PEENSB
7
rw
Parity Error Trap Enable for Standby Memory
0
No Parity trap is requested for Standby
memory parity errors
1
A Parity trap is requested for Standby memory
parity errors
PEFDP
8
rwh
Parity Error Flag for Dual Port Memory
0
No Parity errors have been detected for dual
port memory
1
A Parity error is indicated and can trigger a trap
request trigger, if enabled for dual port memory
The bit is only set by the enabled parity error from the
dual port memory. This bit can only be cleared via
SW.
Writing a zero to this bit does not change the content.
Writing a one to this bit does clear the bit.
PEFDS
9
rwh
Parity Error Flag for Data SRAM
0
No Parity errors have been detected for data
SRAM
1
A Parity error is indicated and can trigger a trap
request trigger, if enabled for data SRAM
The bit is only set by the enabled parity error from the
data SRAM. This bit can only be cleared via SW.
Writing a zero to this bit does not change the content.
Writing a one to this bit does clear the bit.
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Memory Organization
Field
Bits
Type
Description
PEFPS
10
rwh
Parity Error Flag for Program SRAM
0
No Parity errors have been detected for
program SRAM
1
A Parity error is indicated and can trigger a trap
request trigger, if enabled for program SRAM
The bit is only set by the enabled parity error from the
program SRAM. This bit can only be cleared via SW.
Writing a zero to this bit does not change the content.
Writing a one to this bit does clear the bit.
PEFU0
11
rwh
Parity Error Flag for USIC0 Memory
0
No Parity errors have been detected for USIC0
memory
1
A Parity error is indicated and can trigger a trap
request trigger, if enabled for USIC0 memory
The bit is only set by the enabled parity error from the
USIC0 memory. This bit can only be cleared via SW.
Writing a zero to this bit does not change the content.
Writing a one to this bit does clear the bit.
PEFU1
12
rwh
Parity Error Flag for USIC1 Memory
0
No Parity errors have been detected for USIC1
memory
1
A Parity error is indicated and can trigger a trap
request trigger, if enabled for USIC1 memory
The bit is only set by the enabled parity error from the
USIC1 memory. This bit can only be cleared via SW.
Writing a zero to this bit does not change the content.
Writing a one to this bit does clear the bit.
PEFU2
13
rwh
Parity Error Flag for USIC2 Memory
0
No Parity errors have been detected for USIC2
memory
1
A Parity error is indicated and can trigger a trap
request trigger, if enabled for USIC2 memory
The bit is only set by the enabled parity error from the
USIC2 memory. This bit can only be cleared via SW.
Writing a zero to this bit does not change the content.
Writing a one to this bit does clear the bit.
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Preliminary
Memory Organization
Field
Bits
Type
Description
PEFMC
14
rwh
Parity Error Flag for MultiCAN Memory
0
No Parity errors have been detected for
MultiCAN memory
1
A Parity error is indicated and can trigger a trap
request trigger, if enabled for MultiCAN
memory
The bit is only set by the enabled parity error from the
MultiCAN memory. This bit can only be cleared via
SW.
Writing a zero to this bit does not change the content.
Writing a one to this bit does clear the bit.
PEFSB
15
rwh
Parity Error Flag for Standby Memory
0
No Parity errors have been detected for
Standby memory
1
A Parity error is indicated and can trigger a trap
request trigger, if enabled for Standby memory
The bit is only set by the enabled parity error from the
Standby memory. This bit can only be cleared via
SW.
Writing a zero to this bit does not change the content.
Writing a one to this bit does clear the bit.
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Preliminary
User’s Manual
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Memory Organization
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System Units (Vol. 1 of 2)
Preliminary
4
Central Processing Unit (CPU)
Central Processing Unit (CPU)
Basic tasks of the Central Processing Unit (CPU) are to fetch and decode instructions,
to supply operands for the Arithmetic and Logic unit (ALU) and the Multiply and
Accumulate unit (MAC), to perform operations on these operands in the ALU and MAC,
and to store the previously calculated results. As the CPU is the main engine of the
XC2000 microcontroller, it is also affected by certain actions of the peripheral
subsystem.
Because a five-stage processing pipeline (plus 2-stage fetch pipeline) is implemented in
the XC2000, up to five instructions can be processed in parallel. Most instructions of the
XC2000 are executed in one single clock cycle due to this parallelism.
This chapter describes how the pipeline works for sequential and branch instructions in
general, and the hardware provisions which have been made to speed up execution of
jump instructions in particular. General instruction timing is described, including standard
timing, as well as exceptions.
While internal memory accesses are normally performed by the CPU itself, external
peripheral or memory accesses are performed by a particular on-chip External Bus
Controller (EBC) which is invoked automatically by the CPU whenever a code or data
address refers to the external address space.
Whenever possible, the CPU continues operating while an external memory access is in
progress. If external data are required but are not yet available, or if a new external
memory access is requested by the CPU before a previous access has been completed,
the CPU will be held by the EBC until the request can be satisfied. The EBC is described
in a separate chapter.
The on-chip peripheral units of the XC2000 work nearly independently of the CPU with
a separate clock generator. Data and control information are interchanged between the
CPU and these peripherals via Special Function Registers (SFRs).
Whenever peripherals need a non-deterministic CPU action, an on-chip Interrupt
Controller compares all pending peripheral service requests against each other and
prioritizes one of them. If the priority of the current CPU operation is lower than the
priority of the selected peripheral request, an interrupt will occur.
There are two basic types of interrupt processing:
•
•
Standard interrupt processing forces the CPU to save the current program status
and return address on the stack before branching to the interrupt vector jump table.
PEC interrupt processing steals only one machine cycle from the current CPU
activity to perform a single data transfer via the on-chip Peripheral Event Controller
(PEC).
System errors detected during program execution (hardware traps) and external nonmaskable interrupts are also processed as standard interrupts with a very high priority.
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Central Processing Unit (CPU)
In contrast to other on-chip peripherals, there is a closer conjunction between the
watchdog timer and the CPU. If enabled, the watchdog timer expects to be serviced by
the CPU within a programmable period of time, otherwise it will reset the chip. Thus, the
watchdog timer is able to prevent the CPU from going astray when executing erroneous
code. After reset, the watchdog timer starts counting automatically but, it can be disabled
via software, if desired.
In addition to its normal operation state, the CPU has the following particular states:
•
•
Reset state: Any reset (application or power) forces the CPU into a predefined active
state.
Idle state: The clock signal to the CPU itself is switched off, while the clocks for the
on-chip peripherals may keep running.
Transition to an active CPU state is forced by an interrupt (if in IDLE or SLEEP mode) or
by a reset (if in POWER DOWN mode).
The IDLE, SLEEP, POWER DOWN, and RESET states can be entered by specific
XC2000 system control instructions.
A set of Special Function Registers is dedicated to the CPU core (CSFRs):
•
•
•
•
•
•
•
•
•
•
CPU Status Indication and Control: PSW, CPUCON1, CPUCON2
Code Access Control: IP, CSP
Data Paging Control: DPP0, DPP1, DPP2, DPP3
Global GPRs Access Control: CP
System Stack Access Control: SP, SPSEG, STKUN, STKOV
Multiply and Divide Support: MDL, MDH, MDC
Indirect Addressing Offset: QR0, QR1, QX0, QX1
MAC Address Pointers: IDX0, IDX1
MAC Status Indication and Control: MCW, MSW, MAH, MAL, MRW
ALU Constants Support: ZEROS, ONES
The CPU also uses CSFRs to access the General Purpose Registers (GPRs). Since all
CSFRs can be controlled by any instruction capable of addressing the SFR/CSFR
memory space, there is no need for special system control instructions.
However, to ensure proper processor operation, certain restrictions on the user access
to some CSFRs must be imposed. For example, the instruction pointer (CSP, IP) cannot
be accessed directly at all. These registers can only be changed indirectly via branch
instructions. Registers PSW, SP, and MDC can be modified not only explicitly by the
programmer, but also implicitly by the CPU during normal instruction processing.
Note: Note that any explicit write request (via software) to an CSFR supersedes a
simultaneous modification by hardware of the same register.
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Central Processing Unit (CPU)
All CSFRs may be accessed wordwise, or bytewise (some of them even bitwise).
Reading bytes from word CSFRs is a non-critical operation. Any write operation to a
single byte of a CSFR clears the non-addressed complementary byte within the specified
CSFR.
Attention: Reserved CSFR bits must not be modified explicitly, and will always
supply a read value of 0. If a byte/word access is preferred by the
programmer or is the only possible access the reserved CSFR bits
must be written with 0 to provide compatibility with future versions.
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Preliminary
4.1
Central Processing Unit (CPU)
Components of the CPU
The high performance of the CPU results from the cooperation of several units which are
optimized for their respective tasks (see Figure 4-1). Prefetch Unit and Branch Unit
feed the pipeline minimizing CPU stalls due to instruction reads. The Address Unit
supports sophisticated addressing modes avoiding additional instructions needed
otherwise. Arithmetic and Logic Unit and Multiply and Accumulate Unit handle
differently sized data and execute complex operations. Three memory interfaces and
Write Buffer minimize CPU stalls due to data transfers.
PSRAM
Flash/ROM
PMU
CPU
Prefetch
Unit
CSP
IP
VECSEG
CPUCON1
CPUCON2
Branch
Unit
Return
Stack
FIFO
IDX0
IDX1
QX0
QX1
QR0
QR1
+/-
+/-
Multiply
Unit
MRW
+/-
MCW
MSW
MAH
MAL
2-Stage
Prefetch
Pipeline
TFR
Injection/
Exception
Handler
5-Stage
Pipeline
IFU
DPP0
DPP1
DPP2
DPP3
DPRAM
IPIP
SPSEG
SP
STKOV
STKUN
ADU
Division Unit
Bit-Mask-Gen.
Multiply Unit
Barrel-Shifter
MDC
CP
R15
R15
R14
R15
R14
R14
R15
R14
GPRs
GPRs
GPRs
GPRs
R1
R1
R0
R0R1
R0
R1
R0
RF
PSW
+/-
MDH
MDL
ZEROS
ONES
MAC
Buffer
ALU
WB
DSRAM
EBC
Peripherals
DMU
mca04917_x.vsd
Figure 4-1
CPU Block Diagram
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Preliminary
Central Processing Unit (CPU)
In general the instructions move through 7 pipeline stages, where each stage processes
its individual task (see Section 4.3 for a summary):
•
•
the 2-stage fetch pipeline prefetches instructions from program memory and stores
them into an instruction FIFO
the 5-stage processing pipeline executes each instruction stored in the instruction
FIFO
Because passing through one pipeline stage takes at least one clock cycle, any isolated
instruction takes at least five clock cycles to be completed. Pipelining, however, allows
parallel (i.e. simultaneous) processing of up to five instructions (with branches up to six
instructions). Therefore, most of the instructions appear to be processed during one
clock cycle as soon as the pipeline has been filled once after reset.
The pipelining increases the average instruction throughput considered over a certain
period of time.
4.2
Instruction Fetch and Program Flow Control
The Instruction Fetch Unit (IFU) prefetches and preprocesses instructions to provide a
continuous instruction flow. The IFU can fetch simultaneously at least two instructions
via a 64-bit wide bus from the Program Management Unit (PMU). The prefetched
instructions are stored in an instruction FIFO.
Preprocessing of branch instructions enables the instruction flow to be predicted. While
the CPU is in the process of executing an instruction fetched from the FIFO, the
prefetcher of the IFU starts to fetch a new instruction at a predicted target address from
the PMU. The latency time of this access is hidden by the execution of the instructions
which have already been buffered in the FIFO. Even for a non-sequential instruction
execution, the IFU can generally provide a continuous instruction flow. The IFU contains
two pipeline stages: the Prefetch Stage and the Fetch Stage.
During the prefetch stage, the Branch Detection and Prediction Logic analyzes up to
three prefetched instructions stored in the first Instruction Buffer (can hold up to six
instructions). If a branch is detected, then the IFU starts to fetch the next instructions
from the PMU according to the prediction rules. After having been analyzed, up to three
instructions are stored in the second Instruction Buffer (can hold up to three instructions)
which is the input register of the Fetch Stage.
In the case of an incorrectly predicted instruction flow, the instruction fetch pipeline is
bypassed to reduce the number of dead cycles.
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Central Processing Unit (CPU)
24-bit
Address
64-bit
Data
IFU Control
IFU Pipeline
Instruction Buffer (up to 6 Instr.)
CSP
+/-
IP
Branch Detection and Prediction Logic
Prefetch
Stage
Return Stack
CPUCON1
CPUCON2
Control Registers
Instruction
FIFO
Injection and Exception
Handler
VECSEG
TFR
Bypass Fetch to Decode
Branch Folding
Unit
Bypass Prefetch to Decode
Instruction Buffer (up to 3 Instr.)
Fetch
Stage
Instruction Buffer (up to 1 Instr.)
Decode
Stage
MCA05501
Figure 4-2
IFU Block Diagram
On the Fetch Stage, the prefetched instructions are stored in the instruction FIFO. The
Branch Folding Unit (BFU) allows processing of branch instructions in parallel with
preceding instructions. To achieve this the BFU preprocesses and reformats the branch
instruction. First, the BFU defines (calculates) the absolute target address. This address
— after being combined with branch condition and branch attribute bits — is stored in
the same FIFO step as the preceding instruction. The target address is also used to
prefetch the next instructions.
For the Processing Pipeline, both instructions are fetched from the FIFO again and are
executed in parallel. If the instruction flow was predicted incorrectly (or FIFO is empty),
the two stages of the IFU can be bypassed.
Note: Pipeline behavior in case of a incorrectly predicted instruction flow is described in
the following sections.
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Preliminary
4.2.1
Central Processing Unit (CPU)
Branch Detection and Branch Prediction Rules
The Branch Detection Unit preprocesses instructions and classifies detected branches.
Depending on the branch class, the Branch Prediction Unit predicts the program flow
using the following rules:
Table 4-1
Branch Classes and Prediction Rules
Branch Instruction Classes
Instructions
Prediction Rule (Assumption)
Inter-segment branch
instructions
JMPS seg, caddr
CALLS seg, caddr
The branch is always taken
Branch instructions with
user programmable branch
prediction
JMPA- xcc, caddr
JMPA+ xcc, caddr
CALLA- xcc, caddr
CALLA+ xcc, caddr
User-specified1) via bit 8 (‘a’) of
the instruction long word:
…+: branch ‘taken’ (a = 0)
…-: branch ‘not taken’ (a = 1)
Indirect branch instructions
JMPI cc, [Rw]
CALLI cc, [Rw]
Unconditional: branch ‘taken’
Conditional: ‘not taken’
Relative branch instructions
with condition code
JMPR cc, rel
Unconditional or backward:
branch ‘taken’
Conditional forward: ‘not taken’
Relative branch instructions
without condition code
CALLR rel
The branch is always taken
Branch instructions with bitcondition
JB(C) bitaddr, rel
JNB(S) bitaddr, rel
Backward: branch ‘taken’
Forward: ‘not taken’
Return instructions
RET, RETP
RETS, RETI
The branch is always taken
1) This bit can be also set/cleared automatically by the Assembler for generic JMPA and CALLA instructions
depending on the jump condition (condition is cc_Z: ‘not taken’, otherwise: ‘taken’).
4.2.2
Correctly Predicted Instruction Flow
Table 4-2 shows the continuous execution of instructions, assuming a 0-waitstate
program memory. In this example, most of the instructions are executed in one CPU
cycle while instruction In+6 takes two CPU cycles (general example for multicycle
instructions). The diagram shows the sequential instruction flow through the different
pipeline stages. Figure 4-3 shows the corresponding program memory section.
The instructions for the processing pipeline are fetched from the Instruction FIFO while
the IFU prefetches the next instructions to fill the FIFO. As long as the instruction flow is
correctly predicted by the IFU, both processes are independent.
In this example with a fast Internal Program Memory, the Prefetcher is able to fetch more
instructions than the processing pipeline can execute. In Tn+4, the FIFO and prefetch
buffer are filled and no further instructions can be prefetched. The PMU address stays
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stable (Tn+4) until a whole 64-bit double word can be buffered (Tn+7) in the 96-bit prefetch
buffer again.
Table 4-2
Correctly Predicted Instruction Flow (Sequential Execution)
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
Tn+6
Tn+7
Tn+8
Ia+16
Ia+24
Ia+32
Ia+40
Ia+40
Ia+40
Ia+40
Ia+48
Ia+48
PMU Data 64bit Id+1
Id+2
Id+3
Id+4
Id+5
Id+5
Id+5
Id+5
Id+7
PREFETCH
96-bit Buffer
In+6
…
In+9
In+9
…
In+11
In+12
In+13
In+14
In+15
In+15
…
In+19
In+15
…
In+19
In+16
…
In+19
In+17
…
In+19
In+18
…
In+21
FETCH
Instruction
Buffer
In+5
In+6
In+7
In+8
In+9
In+10
In+11
In+12
In+13
In+14
–
In+15
In+16
In+17
FIFO contents
In+3
…
In+5
In+4
…
In+8
In+5
…
In+11
In+6
…
In+13
In+7
…
In+14
In+7
…
In+14
In+8
…
In+15
In+9
…
In+16
In+10
…
In+17
Fetch from FIFO In+4
In+5
In+6
In+7
In+7
In+8
In+9
In+10
In+11
DECODE
In+3
In+4
In+5
In+6
In+6
In+7
In+8
In+9
In+10
ADDRESS
In+2
In+3
In+4
In+5
In+6
In+6
In+7
In+8
In+9
MEMORY
In+1
In+2
In+3
In+4
In+5
In+6
In+6
In+7
In+8
EXECUTE
In
In+1
In+2
In+3
In+4
In+5
In+6
In+6
In+7
WRITE BACK
–
In
In+1
In+2
In+3
In+4
In+5
In+6
In+6
PMU Address
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In+21
In+21
In+20
In+20
In+19
In+18
In+17
In+16
In+16
In+15
In+15
In+14
In+14
In+13
In+12
In+12
In+11
In+11
In+10
In+10
In+9
In+8
In+7
In+6
Ia+40
Ia+32
Ia+24
Ia+16
Ia+8
Ia
MCA04918
Figure 4-3
4.2.3
Program Memory Section for Correctly Predicted Flow
Incorrectly Predicted Instruction Flow
If the CPU detects that the IFU made an incorrect prediction of the instruction flow, then
the pipeline stages and the Instruction FIFO containing the wrong prefetched instructions
are canceled. The entire instruction fetch is restarted at the correct point of the program.
Table 4-3 shows the restarted execution of instructions, assuming a 0-waitstate program
memory. Figure 4-4 shows the corresponding program memory section.
During the cycle Tn, the CPU detects an incorrectly prediction case which leads to a
canceling of the pipeline. The new address is transferred to the PMU in Tn+1 which
delivers the first data in the next cycle Tn+2. But, the target instruction crosses the 64-bit
memory boundary and a second fetch in Tn+3 is required to get the entire 32-bit
instruction. In Tn+4, the Prefetch Buffer contains two 32-bit instructions while the first
instruction Im is directly forwarded to the Decode stage.
The prefetcher is now restarted and prefetches further instructions. In Tn+5, the
instruction Im+1 is forwarded from the Fetch Instruction Buffer directly to the Decode
stage as well. The Fetch row shows all instructions in the Fetch Instruction Buffer and
the instructions fetched from the Instruction FIFO. The instruction Im+3 is the first
instruction fetched from the FIFO during Tn+6. During the same cycle, instruction Im+2 was
still forwarded from the Fetch Instruction Buffer to the Decode stage.
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Table 4-3
Central Processing Unit (CPU)
Incorrectly Predicted Instruction Flow (Restarted Execution)
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
Tn+6
Tn+7
Tn+8
I…
Ia
Ia+8
Ia+16
Ia+24
I…
I…
I…
I…
PMU Data 64bit I…
–
Id
Id+1
Id+2
Id+3
I…
I…
I…
PREFETCH
96-bit Buffer
I…
–
–
–
Im
Im+1
Im+2
Im+3
Im+4
Im+5
I…
I…
FETCH
Instruction
Buffer
Inext+2
–
–
–
–
Im+1
Im+2
Im+3
Im+4
Im+5
I…
Fetch from FIFO –
–
–
–
–
–
Im+3
Im+4
Im+5
DECODE
Inext+1
–
–
–
Im
Im+1
Im+2
Im+3
Im+4
ADDRESS
Inext
–
–
–
–
Im
Im+1
Im+2
Im+3
MEMORY
Ibranch
–
–
–
–
–
Im
Im+1
Im+2
EXECUTE
In
Ibranch
–
–
–
–
–
Im
Im+1
WRITE BACK
–
In
Ibranch
–
–
–
–
–
Im
PMU Address
I...
I...
Im+5
Im+5
Im+4
Im+4
Im+3
Im+3
Im+2
Im+2
Im+1
Im+1
Im
Im
I...
I...
Ia+24
Ia+16
Ia+8
Ia
MCA04919
64-bit wide Program Memory with four 16 bit packages
Figure 4-4
Program Memory Section for Incorrectly Predicted Flow
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4.3
Central Processing Unit (CPU)
Instruction Processing Pipeline
The XC2000 uses five pipeline stages to execute an instruction. All instructions pass
through each of the five stages of the instruction processing pipeline. The pipeline stages
are listed here together with the 2 stages of the fetch pipeline:
1st -> PREFETCH: This stage prefetches instructions from the PMU in the predicted
order. The instructions are preprocessed in the branch detection unit to detect branches.
The prediction logic decides if the branches are assumed to be taken or not.
2nd -> FETCH: The instruction pointer of the next instruction to be fetched is calculated
according to the branch prediction rules. For zero-cycle branch execution, the Branch
Folding Unit preprocesses and combines detected branches with the preceding
instructions. Prefetched instructions are stored in the instruction FIFO. At the same time,
instructions are transported out of the instruction FIFO to be executed in the instruction
processing pipeline.
3rd -> DECODE: The instructions are decoded and, if required, the register file is
accessed to read the GPR used in indirect addressing modes.
4th -> ADDRESS: All the operand addresses are calculated. Register SP is
decremented or incremented for all instructions which implicitly access the system stack.
5th -> MEMORY: All the required operands are fetched.
6th -> EXECUTE: An ALU or MAC-Unit operation is performed on the previously fetched
operands. The condition flags are updated. All explicit write operations to CPU-SFRs
and all auto-increment/auto-decrement operations of GPRs used as indirect address
pointers are performed.
7th -> WRITE BACK: All external operands and the remaining operands within the
internal DPRAM space are written back. Operands located in the internal SRAM are
buffered in the Write Back Buffer.
Specific so-called injected instructions are generated internally to provide the time
needed to process instructions requiring more than one CPU cycle for processing. They
are automatically injected into the decode stage of the pipeline, then they pass through
the remaining stages like every standard instruction. Program interrupt, PEC transfer,
and OCE operations are also performed by means of injected instructions. Although
these internally injected instructions will not be noticed in reality, they help to explain the
operation of the pipeline.
The performance of the CPU (pipeline) is decreased by bandwidth limitations (same
resource is accessed by different stages) and data dependencies between instructions.
The XC2000’s CPU has dedicated hardware to detect and to resolve different kinds of
dependencies. Some of those dependencies are described in the following section.
Because up to five different instructions are processed simultaneously, additional
hardware has been dedicated to deal with dependencies which may exist between
instructions in different pipeline stages. This extra hardware supports ‘forwarding’ of the
operand read and write values and resolves most of the possible conflicts — such as
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multiple usage of buses — in a time optimized way without performance loss. This
makes the pipeline unnoticeable for the user in most cases. However, there are some
rare cases in which the pipeline requires attention by the programmer. In these cases,
the delays caused by the pipeline conflicts can be used for other instructions to optimize
performance.
Note: The XC2000 has a fully interlocked pipeline, which means that these conflicts do
not cause any malfunction. Instruction re-ordering is only required for performance
reasons.
The following examples describe the pipeline behavior in special cases and give
principle rules to improve the performance by re-ordering the execution of instructions.
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4.3.1
Central Processing Unit (CPU)
Pipeline Conflicts Using General Purpose Registers
The GPRs are the working registers of the CPU and there are a lot of possible
dependencies between instructions using GPRs. A high-speed five-port register file
prevents bandwidth conflicts. Dedicated hardware is implemented to detect and resolve
the data dependencies. Special forwarding busses are used to forward GPR values from
one pipeline stage to another. In most cases, this allows the execution of instructions
without any delay despite of data dependencies.
Conflict_GPRs_Resolved:
In
ADD R0,R1
;Compute new value for R0
In+1 ADD R3,R0
;Use R0 again
In+2 ADD R6,R0
;Use R0 again
In+3 ADD R6,R1
;Use R6 again
In+4 ...
Table 4-4
Resolved Pipeline Dependencies Using GPRs
Tn+2
Tn+31)
Tn+42)
Stage
Tn
Tn+1
DECODE
In = ADD
R0, R1
In+1 = ADD In+2 = ADD In+3 = ADD In+4
R3, R0
R6, R0
R6, R1
Tn+53)
In+5
ADDRESS In-1
In = ADD
R0, R1
In+1 = ADD In+2 = ADD In+3 = ADD In+4
R3, R0
R6, R0
R6, R1
MEMORY
In-2
In-1
In = ADD
R0, R1
In+1 = ADD In+2 = ADD In+3 = ADD
R3, R0
R6, R0
R6, R1
EXECUTE
In-3
In-2
In-1
In = ADD
R0, R1
In+1 = ADD In+2 = ADD
R3, R0
R6, R0
WR.BACK In-4
In-3
In-2
In-1
In = ADD
R0, R1
In+1 = ADD
R3, R0
1) R0 forwarded from EXECUTE to MEMORY.
2) R0 forwarded from WRITE BACK to MEMORY.
3) R6 forwarded from EXECUTE to MEMORY.
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However, if a GPR is used for indirect addressing the address pointer (i.e. the GPR) will
be required already in the DECODE stage. In this case the instruction is stalled in the
address stage until the operation in the ALU is executed and the result is forwarded to
the address stage.
Conflict_GPRs_Pointer_Stall:
In
ADD R0,R1
;Compute new value for R0
In+1 MOV R3,[R0]
;Use R0 as address pointer
In+2 ADD R6,R0
In+3 ADD R6,R1
In+4 ...
Table 4-5
Pipeline Dependencies Using GPRs as Pointers (Stall)
Tn+21)
Stage
Tn
Tn+1
DECODE
In = ADD
R0, R1
In+1 = MOV In+2
R3, [R0]
Tn+32)
Tn+4
Tn+5
In+2
In+2
In+3
ADDRESS In-1
In = ADD
R0, R1
In+1 = MOV In+1 = MOV In+1 = MOV In+2
R3, [R0]
R3, [R0]
R3, [R0]
MEMORY
In-2
In-1
In = ADD
R0, R1
–
–
In+1 = MOV
R3, [R0]
EXECUTE
In-3
In-2
In-1
In = ADD
R0, R1
–
–
WR.BACK In-4
In-3
In-2
In-1
In = ADD
R0, R1
–
1) New value of R0 not yet available.
2) R0 forwarded from EXECUTE to ADDRESS (next cycle).
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To avoid these stalls, one multicycle instruction or two single cycle instructions may be
inserted. These instructions must not update the GPR used for indirect addressing.
Conflict_GPRs_Pointer_NoStall:
In
ADD R0,R1
;Compute new value for R0
;R0 is not updated, just read
In+1 ADD R6,R0
In+2 ADD R6,R1
In+3 MOV R3,[R0]
;Use R0 as address pointer
In+4 ...
Table 4-6
Pipeline Dependencies Using GPRs as Pointers (No Stall)
Tn+2
Tn+31)
Stage
Tn
Tn+1
Tn+4
DECODE
In = ADD
R0, R1
In+1 = ADD In+2 = ADD In+3 = MOV In+4
R6, R0
R6, R1
R3, [R0]
Tn+5
In+5
ADDRESS In-1
In = ADD
R0, R1
In+1 = ADD In+2 = ADD In+3 = MOV In+4
R6, R0
R6, R1
R3, [R0]
MEMORY
In-2
In-1
In = ADD
R0, R1
In+1 = ADD In+2 = ADD In+3 = MOV
R6, R0
R6, R1
R3, [R0]
EXECUTE
In-3
In-2
In-1
In = ADD
R0, R1
In+1 = ADD In+2 = ADD
R6, R0
R6, R1
WR.BACK In-4
In-3
In-2
In-1
In = ADD
R0, R1
In+1 = ADD
R6, R0
1) R0 forwarded from EXECUTE to ADDRESS (next cycle).
4.3.2
Pipeline Conflicts Using Indirect Addressing Modes
In the case of read accesses using indirect addressing modes, the Address Generation
Unit uses a speculative addressing mechanism. The read data path to one of the
different memory areas (DPRAM, DSRAM, etc.) is selected according to a history table
before the address is decoded. This history table has one entry for each of the GPRs.
The entries store the information of the last accessed memory area using the
corresponding GPR. In the case of an incorrect prediction of the memory area, the read
access must be restarted.
It is recommended that the GPRs used for indirect addressing always point to the same
memory area. If an updated GPR points to a different memory area, the next read
operation will access the wrong memory area. The read access must be repeated, which
leads to pipeline stalls.
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Conflict_GPRs_Pointer_WrongHistory:
In
ADD R3,[R0]
;R0 points to DPRAM (e.g.)
In+1 MOV R0,R4
...
Ii
MOV DPPX, ...
;change DPPx
...
Im
ADD R6,[R0]
;R0 now points to SRAM (e.g.)
Im+1 MOV R6,R1
Im+2 ...
Table 4-7
Pipeline Dependencies with Pointers (Valid Speculation)
Stage
Tn
Tn+1
Tn+2
DECODE
In = ADD
R3, [R0]
In+1 = MOV In+2
R0, R4
Tn+3
Tn+4
Tn+5
In+3
In+4
In+5
In+3
In+4
In+3
ADDRESS In-1
In = ADD
R3, [R0]
In+1 = MOV In+2
R0, R4
MEMORY
In-2
In-1
In = ADD
R3, [R0]
In+1 = MOV In+2
R0, R4
EXECUTE
In-3
In-2
In-1
In = ADD
R3, [R0]
In+1 = MOV In+2
R0, R4
WR.BACK In-4
In-3
In-2
In-1
In = ADD
R3, [R0]
Table 4-8
In+1 = MOV
R0, R4
Pipeline Dependencies with Pointers (Invalid Speculation)
Tm+21)
Stage
Tm
DECODE
Im = ADD Im+1 = MOV Im+1 = MOV Im+2
R6, [R0] R6, R1
R6, R1
Tm+1
Tm+3
Tm+4
Tm+5
Im+3
Im+4
Im+3
ADDRESS Im-1
Im = ADD
R6, [R0]
Im = ADD
R6, [R0]
Im+1 = MOV Im+2
R6, R1
MEMORY
Im-2
Im-1
–
Im = ADD
R6, [R0]
Im+1 = MOV Im+2
R6, R1
EXECUTE
Im-3
Im-2
Im-1
–
Im = ADD
R6, [R0]
Im+1 = MOV
R6, R1
WR.BACK Im-4
Im-3
Im-2
Im-1
–
Im = ADD
R6, [R0]
1) Access to location [R0] must be repeated due to wrong history (target area was changed).
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4.3.3
Central Processing Unit (CPU)
Pipeline Conflicts Due to Memory Bandwidth
Memory bandwidth conflicts can occur if instructions in the pipeline access the same
memory area at the same time. Special access mechanisms are implemented to
minimize conflicts. The DPRAM of the CPU has two independent read/write ports; this
allows parallel read and write operation without delays. Write accesses to the DSRAM
can be buffered in a Write Back Buffer until read accesses are finished.
All instructions except the CoXXX instructions can read only one memory operand per
cycle. A conflict between the read and one write access cannot occur because the
DPRAM has two independent read/write ports. Only other pipeline stall conditions can
generate a DPRAM bandwidth conflict. The DPRAM is a synchronous pipelined
memory. The read access starts with the valid addresses on the address stage. The data
are delivered in the Memory stage. If a memory read access is stalled in the Memory
stage and the following instruction on the Address stage tries to start a memory read, the
new read access must be delayed as well. But, this conflict is hidden by an already
existing stall of the pipeline.
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The CoXXX instructions are the only instructions able to read two memory operands per
cycle. A conflict between the two read and one pending write access can occur if all three
operands are located in the DPRAM area. This is especially important for performance
in the case of executing a filter routine. One of the operands should be located in the
DSRAM to guarantee a single-cycle execution of the CoXXX instructions.
Conflict_DPRAM_Bandwidth:
In
ADD op1,R1
In+1 ADD R6,R0
In+2 CoMAC [IDX0],[R0]
In+3 MOV R3,[R0]
In+4 ...
Table 4-9
Pipeline Dependencies in Case of Memory Conflicts (DPRAM)
Tn+2
Tn+3
Tn+41)
Stage
Tn
Tn+1
DECODE
In = ADD
op1, R1
In+1 = ADD In+2 =
In+3 = MOV In+4
R6, R0
CoMAC … R3, [R0]
Tn+5
In+4
ADDRESS In-1
In = ADD
op1, R1
In+1 = ADD In+2 =
In+3 = MOV In+3 = MOV
R6, R0
CoMAC … R3, [R0]
R3, [R0]
MEMORY
In-2
In-1
In = ADD
op1, R1
In+1 = ADD In+2 =
In+2 =
R6, R0
CoMAC … CoMAC …
EXECUTE
In-3
In-2
In-1
In = ADD
op1, R1
In+1 = ADD –
R6, R0
WR.BACK In-4
In-3
In-2
In-1
In = ADD
op1, R1
In+1 = ADD
R6, R0
1) COMAC instruction stalls due to memory bandwidth conflict.
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The DSRAM is a single-port memory with one read/write port. To reduce the number of
bandwidth conflict cases, a Write Back Buffer is implemented. It has three data entries.
Only if the buffer is filled and a read access and a write access occur at the same time,
must the read access be stalled while one of the buffer entries is written back.
Conflict_DSRAM_Bandwidth:
In
ADD op1,R1
In+1 ADD R6,R0
In+2 ADD R6,op2
In+3 MOV R3,R2
In+4 ...
Table 4-10
Pipeline Dependencies in Case of Memory Conflicts (DSRAM)
Tn+41)
Stage
Tn
Tn+1
DECODE
In = ADD
op1, R1
In+1 = ADD In+2 = ADD In+3 = MOV In+4
R6, R0
R6, op2
R3, R2
Tn+2
Tn+3
Tn+5
In+4
ADDRESS In-1
In = ADD
op1, R1
In+1 = ADD In+2 = ADD In+3 = MOV In+3 = MOV
R6, R0
R6, op2
R3, R2
R3, R2
MEMORY
In-2
In-1
In = ADD
op1, R1
In+1 = ADD In+2 = ADD In+2 = ADD
R6, R0
R6, op2
R6, op2
EXECUTE
In-3
In-2
In-1
In = ADD
op1, R1
In+1 = ADD –
R6, R0
WR.BACK In-4
In-3
In-2
In-1
In = ADD
op1, R1
In+1 = ADD
R6, R0
WB.Buffer full
full
full
full
full
full
1) ADD R6, op2 instruction stalls due to memory bandwidth conflict.
User’s Manual
CPUSV2_X, V2.2
4-19
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.3.4
Central Processing Unit (CPU)
Pipeline Conflicts Caused by CPU-SFR Updates
CPU-SFRs control the CPU functionality and behavior. Changes and updates of CSFRs
influence the instruction flow in the pipeline. Therefore, special care is required to ensure
that instructions in the pipeline always work with the correct CSFR values. CSFRs are
updated late on the EXECUTE stage of the pipeline. Meanwhile, without conflict
detection, the instructions in the DECODE, ADDRESS, and MEMORY stages would still
work without updated register values. The CPU detects conflict cases and stalls the
pipeline to guarantee a correct execution. For performance reasons, the CPU
differentiates between different classes of CPU-SFRs. The flow of instructions through
the pipeline can be improved by following the given rules used for instruction re-ordering.
There are three classes of CPU-SFRs:
•
•
•
CSFRs not generating pipeline conflicts (ONES, ZEROS, MCW)
CSFR result registers updated late in the EXECUTE stage, causing one stall cycle
CSFRs affecting the whole CPU or the pipeline, causing canceling
CSFR Result Registers
The CSFR result registers MDH, MDL, MSW, MAH, MAL, and MRW of the ALU and
MAC-Unit are updated late in the EXECUTE stage of the pipeline. If an instruction
(except CoSTORE) accesses explicitly these registers in the memory stage, the value
cannot be forwarded. The instruction must be stalled for one cycle on the MEMORY
stage.
User’s Manual
CPUSV2_X, V2.2
4-20
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
Conflict_CSFR_Update_Stall:
In
MUL R0,R1
In+1 MOV R6,MDL
In+2 ADD R6,R1
In+3 MOV R3,[R0]
In+4 ...
Table 4-11
Pipeline Dependencies with Result CSFRs (Stall)
Tn+2
Tn+31)
Stage
Tn
Tn+1
Tn+4
Tn+5
DECODE
In = MUL
R0, R1
In+1 = MOV In+2 = ADD In+3 = MOV In+3 = MOV In+4
R6, MDL
R6, R1
R3, [R0]
R3, [R0]
ADDRESS In-1
In = MUL
R0, R1
In+1 = MOV In+2 = ADD In+2 = ADD In+3 = MOV
R6, MDL
R6, R1
R6, R1
R3, [R0]
MEMORY
In-2
In-1
In = MUL
R0, R1
In+1 = MOV In+1 = MOV In+2 = ADD
R6, MDL
R6, MDL
R6, R1
EXECUTE In-3
In-2
In-1
In = MUL
R0, R1
–
In+1 = MOV
R6, MDL
WR.BACK In-4
In-3
In-2
In-1
In = MUL
R0, R1
–
1) Cannot read MDL here.
User’s Manual
CPUSV2_X, V2.2
4-21
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
By reordering instructions, the bubble in the pipeline can be filled with an instruction not
using this resource.
Conflict_CSFR_Update_Resolved:
In
MUL R0,R1
In+1 MOV R3,[R0]
In+2 MOV R6,MDL
In+3 ADD R6,R1
In+4 ...
Table 4-12
Pipeline Dependencies with Result CSFRs (No Stall)
Tn+2
Tn+3
Tn+41)
Stage
Tn
Tn+1
DECODE
In = MUL
R0, R1
In+1 = MOV In+2 = MOV In+3 = ADD In+4
R3, [R0]
R6, MDL
R6, R1
Tn+5
In+5
ADDRESS In-1
In = MUL
R0, R1
In+1 = MOV In+2 = MOV In+3 = ADD In+4
R3, [R0]
R6, MDL
R6, R1
MEMORY
In-2
In-1
In = MUL
R0, R1
In+1 = MOV In+2 = MOV In+3 = ADD
R3, [R0]
R6, MDL
R6, R1
EXECUTE In-3
In-2
In-1
In = MUL
R0, R1
In+1 = MOV In+2 = MOV
R3, [R0]
R6, MDL
WR.BACK In-4
In-3
In-2
In-1
In = MUL
R0, R1
In+1 = MOV
R3, [R0]
1) MDL can be read now, no stall cycle necessary.
User’s Manual
CPUSV2_X, V2.2
4-22
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
CSFRs Affecting the Whole CPU
Some CSFRs affect the whole CPU or the pipeline before the Memory stage. The CPUSFRs CPUCON1, CP, SP, STKUN, STKOV, VECSEG, TFR, and PSW affect the overall
CPU function, while the CPU-SFRs IDX0, IDX1, QX1, QX0, DPP0, DPP1, DPP2, and
DPP3 only affect the DECODE, ADDRESS, and MEMORY stage when they are
modified explicitly. In this case the pipeline behavior depends on the instruction and
addressing mode used to modify the CSFR.
In the case of modification of these CSFRs by “POP CSFR” or by instructions using the
reg,#data16 addressing mode, a special mechanism is implemented to improve
performance during the initialization.
For further explanation, the instruction which modifies the CSFR can be called
“instruction_modify_CSFR”. This special case is detected in the DECODE stage when
the instruction_modify_CSFR enters the processing pipeline. Further on, instructions
described in the following list are held in the DECODE stage (all other instructions are
not held):
•
•
•
•
Instructions using long addressing mode (mem)
Instructions using indirect addressing modes ([Rw], [Rw+]…), except JMPI and CALLI
ENWDT, DISWDT, EINIT
All CoXXX instructions
If the CPUCON1, CP, SP, STKUN, STKOV, VECSEG, TFR, or the PSW are modified
and the instruction_modify_CSFR reaches the EXECUTE stage, the pipeline is
canceled. The modification affects the entire pipeline and the instruction prefetch. A
clean cancel and restart mechanism is required to guarantee a correct instruction flow.
In case of modification of IDX0, IDX1, QX1, QX0, DPP0, DPP1, DPP2, or DPP3 only the
DECODE, ADDRESS, and MEMORY stages are affected and the pipeline needs not to
be canceled. The modification does not affect the instructions in the ADDRESS,
MEMORY stage because they are not using this resource. Other kinds of instructions are
held in the DECODE stage until the CSFR is modified.
The following example shows a case in which the pipeline is stalled. The instruction
“MOV R6, R1” after the “MOV IDX1, #12” instruction which modifies the CSFR will be
held in DECODE Stage until the IDX1 register is updated. The next example shows an
optimized initialization routine.
User’s Manual
CPUSV2_X, V2.2
4-23
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
Conflict_Canceling:
In
MOV IDX1,#12
In+1 MOV R6,mem
In+2 ADD R6,R1
In+3 MOV R3,[R0]
Table 4-13
Pipeline Dependencies with Control CSFRs (Canceling)
Stage
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
DECODE
In = MOV
IDX1, #12
In+1 = MOV In+1 = MOV In+1 = MOV In+1 = MOV In+2 = ADD
R6, mem R6, mem R6, mem R6, mem R6, R1
ADDRESS In-1
In = MOV
IDX1, #12
–
–
–
In+1 = MOV
R6, mem
MEMORY
In-2
In-1
In = MOV
IDX1, #12
–
–
–
EXECUTE In-3
In-2
In-1
In = MOV
IDX1, #12
–
–
WR.BACK In-4
In-3
In-2
In-1
In = MOV
IDX1, #12
–
Conflict_Canceling_Optimized:
In
MOV IDX1,#12
In+1 MOV MAH,#23
In+2 MOV MAL,#25
In+3 MOV R3,#08
In+4 ...
Table 4-14
Pipeline Dependencies with Control CSFRs (Optimized)
Stage
Tn
Tn+1
DECODE
In = MOV
IDX1, #12
In+1 = MOV In+2 = MOV In+3 = MOV In+4
MAH, #23 MAL, #25 R3, #08
Tn+2
Tn+3
Tn+4
Tn+5
In+5
ADDRESS In-1
In = MOV
IDX1, #12
In+1 = MOV In+2 = MOV In+3 = MOV In+4
MAH, #23 MAL, #25 R3, #08
MEMORY
In-2
In-1
In = MOV
IDX1, #12
In+1 = MOV In+2 = MOV In+3 = MOV
MAH, #23 MAL, #25 R3, #08
EXECUTE In-3
In-2
In-1
In = MOV
IDX1, #12
In+1 = MOV In+2 = MOV
MAH, #23 MAL, #25
WR.BACK In-4
In-3
In-2
In-1
In = MOV
IDX1, #12
User’s Manual
CPUSV2_X, V2.2
4-24
In+1 = MOV
MAH, #23
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
For all the other instructions that modify this kind of CSFR, a simple stall and cancel
mechanism guarantees the correct instruction flow.
A possible explicit write-operation to this kind of CSFRs is detected on the MEMORY
stage of the pipeline. The following instructions on the ADDRESS and DECODE Stage
are stalled. If the instruction reaches the EXECUTE stage, the entire pipeline and the
Instruction FIFO of the IFU are canceled. The instruction flow is completely re-started.
Conflict_Canceling_Completely:
In
MOV PSW,R4
In+1 MOV R6,R1
In+2 ADD R6,R1
In+3 MOV R3,[R0]
In+4 ...
Table 4-15
Pipeline Dependencies with Control CSFRs (Cancel All)
Stage
Tn+1
DECODE
In+1 = MOV In+2 = ADD In+2 = ADD –
R6, R1
R6, R1
R6, R1
Tn+2
Tn+3
Tn+4
Tn+5
Tn+6
–
In+1 = MOV
R6, R1
ADDRESS In = MOV
PSW, R4
In+1 = MOV In+1 = MOV –
R6, R1
R6, R1
–
–
MEMORY
In = MOV
PSW, R4
–
–
–
–
EXECUTE In-2
In-1
In = MOV
PSW, R4
–
–
–
WR.BACK In-3
In-2
In-1
In = MOV
PSW, R4
–
–
In-1
User’s Manual
CPUSV2_X, V2.2
4-25
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.4
Central Processing Unit (CPU)
CPU Configuration Registers
The CPU configuration registers select a number of general features and behaviors of
the XC2000’s CPU core. In general, these registers must not be modified by application
software (exceptions will be documented, e.g. in an errata sheet).
Note: The CPU configuration registers are protected by the register security mechanism
after the EINIT instruction has been executed.
CPUCON1
CPU Control Register 1
SFR (FE18H/0CH)
Reset Value: 0007H
15
14
13
12
11
10
9
8
7
6
5
-
-
-
-
-
-
-
-
-
VECSC
-
-
-
-
-
-
-
-
-
rw
4
3
2
1
WDT SGT INTS
BP
CTL DIS CXT
rw
rw
rw
rw
0
ZCJ
Field
Bits
Type
Description
VECSC
[6:5]
rw
Scaling Factor of Vector Table
00
Space between two vectors is 2 words1)
01
Space between two vectors is 4 words
10
Space between two vectors is 8 words
11
Space between two vectors is 16 words
WDTCTL
4
rw
Configuration of Watchdog Timer
0
DISWDT executable only until End Of Init2)
1
DISWDT/ENWDT always executable
(enhanced WDT mode)
SGTDIS
3
rw
Segmentation Disable/Enable Control
0
Segmentation enabled
1
Segmentation disabled
INTSCXT
2
rw
Enable Interruptibility of Switch Context
0
Switch context is not interruptible
1
Switch context is interruptible
BP
1
rw
Enable Branch Prediction Unit
0
Branch prediction disabled
1
Branch prediction enabled
ZCJ
0
rw
Enable Zero Cycle Jump Function
0
Zero cycle jump function disabled
1
Zero cycle jump function enabled
rw
1) The default value (2 words) is compatible with the vector distance defined in the C166 Family architecture.
2) The DISWDT (executed after EINIT) and ENWDT instructions are internally converted in a NOP instruction.
User’s Manual
CPUSV2_X, V2.2
4-26
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
CPUCON2
CPU Control Register 2
15
14
13
12
SFR (FE1AH/0DH)
11
10
FIFODEPTH
FIFOFED
rw
rw
8
7
6
5
4
3
BYP BYP EIO STE
OV RET
LFIC
PF
F IAEN N
RUN ST
rw
rw
rw
rw
rw
rw
rw
2
-
1
0
DAID SL
rw
rw
Field
Bits
FIFODEPTH
[15:12] rw
FIFO Depth Configuration
0000 No FIFO (entries)
0001 One FIFO entry
…
…
1000 Eight FIFO entries
1001 reserved
…
…
1111 reserved
FIFOFED
[11:10] rw
FIFO Fed Configuration
00
FIFO disabled
01
FIFO filled with up to one instruction per cycle
10
FIFO filled with up to two instructions per cycle
11
FIFO filled with up to three instruction per cycle
BYPPF
9
rw
Prefetch Bypass Control
0
Bypass path from prefetch to decode disabled
1
Bypass path from prefetch to decode available
BYPF
8
rw
Fetch Bypass Control
0
Bypass path from fetch to decode disabled
1
Bypass path from fetch to decode available
EIOIAEN
7
rw
Early IO Injection Acknowledge Enable
0
Injection acknowledge by destructive read not
guaranteed
1
Injection acknowledge by destructive read
guaranteed
STEN
6
rw
Stall Instruction Enable (for debug purposes)
0
Stall Instruction disabled
1
Stall Instruction enabled (see example below)
LFIC
5
rw
Linear Follower Instruction Cache
0
Linear Follower Instruction Cache disabled
1
Linear Follower Instruction Cache enabled
User’s Manual
CPUSV2_X, V2.2
Type
9
Reset Value: 8FBBH
Description
4-27
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
Field
Bits
Type
Description
OVRUN
4
rw
Pipeline Control
0
Overrun of pipeline bubbles not allowed
1
Overrun of pipeline bubbles allowed
RETST
3
rw
Enable Return Stack
0
Return Stack is disabled
1
Return Stack is enabled
DAID
1
rw
Disable Atomic Injection Deny
0
Injection-requests are denied during Atomic
1
Injection-requests are not denied during
Atomic
SL
0
rw
Enables Short Loop Mode
0
Short loop mode disabled
1
Short loop mode enabled
Example for dedicated stall debug instructions:
STALLAM da,ha,dm,hm
STALLEW de,he,dw,hw
;Opcode: 44 dahadmhm
;Opcode: 45 dehedwhw
;Stalls the corresponding pipeline
;stage after “d” cycles for “h” cycles
;(“d” and “h” are 6-bit values)
Note: In general, these registers must not be modified by application software
(exceptions will be documented, e.g. in an errata sheet).
User’s Manual
CPUSV2_X, V2.2
4-28
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.5
Central Processing Unit (CPU)
Use of General Purpose Registers
The CPU uses several banks of sixteen dedicated registers R0, R1, R2, … R15, called
General Purpose Registers (GPRs), which can be accessed in one CPU cycle. The
GPRs are the working registers of the arithmetic and logic units and many also serve as
address pointers for indirect addressing modes.
The register banks are accessed via the 5-port register file providing the high access
speed required for the CPU’s performance. The register file is split into three
independent physical register banks. There are two types of register banks:
•
•
Two local register banks which are a part of the register file
A global register bank which is memory-mapped and cached in the register file
Core-RAM
Registerfile
Global
Local
AGU Write Port
ALU Write Port
Memory
mapped
GPR Bank
R15
R0
CP
R15
R15
R15
R14
R14
R13
R13
R12
R12
R11
R11
R10
R10
R9
R9
R8
R8
R7
R7
R6
R6
R5
R5
R4
R4
R3
R3
R2
R2
R1
R1
R0
R0
AGU Read Port
ALU Read Port 1
ALU Read Port 2
MCD04873
Figure 4-5
Register File
User’s Manual
CPUSV2_X, V2.2
4-29
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
Bitfield BANK in register PSW selects which of the three physical register banks is
activated. The selected bank can be changed explicitly by any instruction which writes
to the PSW, or implicitly by a RETI instruction, an interrupt or hardware trap. In case of
an interrupt, the selection of the register bank is configured via registers BNKSELx in the
Interrupt Controller ITC. Hardware traps always use the global register bank.
The local register banks are built of dedicated physical registers, while the global register
bank represents a cache. The banks of the memory-mapped GPRs (global bank) are
located in the internal DPRAM. One bank uses a block of 16 consecutive words. A
Context Pointer (CP) register determines the base address of the current selected bank.
To provide the required access speed, the GPRs located in the DPRAM are cached in
the 5-port register file (only one memory-mapped GPR bank can be cached at the time).
If the global register bank is activated, the cache will be validated before further
instructions are executed. After validation, all further accesses to the GPRs are
redirected to the global register bank.
Internal DPRAM
R15
(CP) + 30
R14
(CP) + 28
Register File
R13
R12
R11
15
0
16-Bit Context Pointer
R10
R15
R9
R8
R7
R0
R6
R5
R4
Global
R3
local
R2
R1
(CP) + 2
R0
(CP)
MCA04921
Figure 4-6
Register Bank Selection via Register CP
User’s Manual
CPUSV2_X, V2.2
4-30
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.5.1
Central Processing Unit (CPU)
GPR Addressing Modes
Because the GPRs are the working registers and are accessed frequently, there are
three possible ways to access a register bank:
•
•
•
Short GPR Address (mnemonic: Rw or Rb)
Short Register Address (mnemonic: reg or bitoff)
Long Memory Address (mnemonic: mem), for the global bank only
Short GPR Addresses specify the register offset within the current register bank
(selected via bitfield BANK). Short 4-bit GPR addresses can access all sixteen registers,
short 2-bit addresses (used by some instructions) can access the lower four registers.
Depending on whether a relative word (Rw) or byte (Rb) GPR address is specified, the
short GPR address is either multiplied by two (Rw) or not (Rb) before it is used to
physically access the register bank. Thus, both byte and word GPR accesses are
possible in this way.
Note: GPRs used as indirect address pointers are always accessed wordwise.
For the local register banks the resulting offset is used directly, for the global register
bank the resulting offset is logically added to the contents of register CP which points to
the memory location of the base of the current global register bank (see Figure 4-7).
Short 8-Bit Register Addresses within a range from F0H to FFH interpret the four least
significant bits as short 4-bit GPR addresses, while the four most significant bits are
ignored. The respective physical GPR address is calculated in the same way as for short
4-bit GPR addresses. For single bit GPR accesses, the GPR’s word address is
calculated in the same way. The accessed bit position within the word is specified by a
separate additional 4-bit value.
12-Bit Context Pointer
11
Specified by reg or bitoff
1 0
1 1 1 1
For byte
GPR
accesses
4-Bit GPR
Address
*1
*2
For word GPR
accesses
Internal
DRAM
Must be
within
the internal
DPRAM area
+
GPRs
MCA04922
Figure 4-7
Implicit CP Use by Logical Short GPR Addressing Modes
User’s Manual
CPUSV2_X, V2.2
4-31
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
24-Bit Memory Addresses can be directly used to access GPRs located in the DPRAM
(not applicable for local register banks). In case of a memory read access, a hit detection
logic checks if the accessed memory location is cached in the global register bank. In
case of a cache hit, an additional global register bank read access is initiated. The data
that is read from cache will be used and the data that is read from memory will be
discarded. This leads to a delay of one CPU cycle (MOV R4, mem
[CP ≤ mem ≤ CP + 31]). In case of a memory write access, the hit detection logic
determines a cache hit in advance. Nevertheless, the address conversion needs one
additional CPU cycle. The value is directly written into the global register bank without
further delay (MOV mem, R4).
Note: The 24-bit GPR addressing mode is not recommended because it requires an
extra cycle for the read and write access.
Table 4-16
Addressing Modes to Access GPRs
Word Registers1)
Short Address2)
Byte Registers
Name
Mem. Addr.3)
Name
Mem. Addr.3)
8-Bit
4-Bit
2-Bit
R0
(CP) + 0
RL0
(CP) + 0
F0H
0H
0H
R1
(CP) + 2
RH0
(CP) + 1
F1H
1H
1H
R2
(CP) + 4
RL1
(CP) + 2
F2H
2H
2H
R3
(CP) + 6
RH1
(CP) + 3
F3H
3H
3H
R4
(CP) + 8
RL2
(CP) + 4
F4H
4H
---
R5
(CP) + 10
RH2
(CP) + 5
F5H
5H
---
R6
(CP) + 12
RL3
(CP) + 6
F6H
6H
---
R7
(CP) + 14
RH3
(CP) + 7
F7H
7H
---
R8
(CP) + 16
RL4
(CP) + 8
F8H
8H
---
R9
(CP) + 18
RH4
(CP) + 9
F9H
9H
---
R10
(CP) + 20
RL5
(CP) + 10
FAH
AH
---
R11
(CP) + 22
RH5
(CP) + 11
FBH
BH
---
R12
(CP) + 24
RL6
(CP) + 12
FCH
CH
---
R13
(CP) + 26
RH6
(CP) + 13
FDH
DH
---
R14
(CP) + 28
RL7
(CP) + 14
FEH
EH
---
R15
(CP) + 30
RH7
(CP) + 15
FFH
FH
---
1) The first 8 GPRs (R7 … R0) may also be accessed bytewise. Writing to a GPR byte does not affect the other
byte of the respective GPR.
2) Short addressing modes are usable for all register banks.
3) Long addressing mode only usable for the memory mapped global GPR bank.
User’s Manual
CPUSV2_X, V2.2
4-32
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.5.2
Central Processing Unit (CPU)
Context Switching
When a task scheduler of an operating system activates a new task or an interrupt
service routine is called or terminated, the working context (i.e. the registers) of the left
task must be saved and the working context of the new task must be restored. The CPU
context can be changed in two ways:
•
•
Switching the selected register bank
Switching the context of the global register
Switching the Selected Physical Register Bank
By updating bitfield BANK in register PSW the active register bank is switched
immediately. It is possible to switch between the current memory-mapped GPR bank
cached in the global register bank (BANK = 00B), local register bank 1 (BANK = 10B),
and local register bank 2 (BANK = 11B).
In case of an interrupt service, the bank switch can be automatically executed by
updating bitfield BANK from registers BNKSELx in the interrupt controller. By executing
a RETI instruction, bitfield BANK will automatically be restored and the context will
switched to the original register bank.
The switch between the three physical register banks of the register file can also be
executed by writing to bitfield BANK. Because of pipeline dependencies an explicit
change of register PSW must cancel the pipeline.
Global Bank
Local Bank
Global Bank
Execution Task A
Execution Task B
ExecutionTask A
Interrupt of
Task B
recognized
Execution of
RETI
MCA04877
Figure 4-8
Context Switch by Changing the Physical Register Bank
After a switch to a local register bank, the new bank is immediately available. After
switching to the global register bank, the cached memory-mapped GPRs must be valid
before any further instructions can be executed. If the global register bank is not valid at
this time (in case if the context switch process has been interrupted), the cache
validation process is repeated automatically.
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Preliminary
Central Processing Unit (CPU)
Switching the Context of the Global Register Bank
The contents of the global register bank are switched by changing the base address of
the memory-mapped GPR bank. The base address is given by the contents of the
Context Pointer (CP).
After the CP has been updated, a state machine starts to store the old contents of the
global register bank and to load the new one. The store and load algorithm is executed
in nineteen CPU cycles: the execution of the cache validation process takes sixteen
cycles plus three cycles to stall an instruction execution to avoid pipeline conflicts upon
the completion of the validation process. The context switch process has two phases:
•
•
Store phase: The contents of the global register bank1) is stored back into the
DPRAM by executing eight injected STORE instructions. After the last STORE
instruction the contents of the global register bank are invalidated.
Load phase: The global register bank is loaded with the new context by executing
eight injected LOAD instructions. After the last LOAD instruction the contents of the
global register bank are validated.
The code execution is stopped until the global register bank is valid again. A hardware
interrupt can occur during the validation process. The way the validation process is
completed depends on the type of register bank selected for this interrupt:
•
•
If the interrupt also uses a global register bank the validation process is finished
before executing the service routine (see Figure 4-9).
If the interrupt uses a local register bank the validation process is interrupted and the
service routine is executed immediately (see Figure 4-10). After switching back to
the global register bank, the validation process is finished:
– If the interrupt occurred during the store phase, the entire validation process is
restarted from the very beginning.
– If the interrupt occurred during the load phase, only the load phase is repeated.
If a local-bank interrupt routine (Task B in Figure 4-11) is again interrupted by a globalbank interrupt (Task C), the suspended validation process must be finished before code
of Task C can be executed. This means that the validation process of Task A does not
affect the interrupt latency of Task B but the latency of Task C.
Note: If Task C would immediately interrupt Task A, the register bank validation process
of Task A would be finished first. The worst case interrupt latency is identical in
both cases (see Figure 4-9 and Figure 4-11).
1) During the store phase of the context switch the complete register bank is written to the DPRAM even if the
application only uses a part of this register bank. A register bank must not be located above FDE0H, otherwise
the store phase will overwrite SFRs (beginning at FE00H).
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Central Processing Unit (CPU)
Global Bank
Execution
Task A
Execution
Task B
Execution
Task B
Execution of
SCXT CP
Interrupt of
Task B
recognized
Execution of
SCXT CP
Register Bank
Validation
Process
Started
Finished
Figure 4-9
Global Bank
Global Bank
Execution
Task B
Execution
Task A
Execution of
POP CP
Execution of
RETI
Register Bank
Validation
Process
Started
Finished
Register Bank
Validation
Process
Started
Finished
MCA04874
Validation Process Interrupted by Global-Bank Interrupt
Global Bank
Global Bank
Local Bank
Execution
Task A
Execution
Task A
Execution Task B
Execution of
SCXT CP
Interrupt of
Task B
recognized
Execution of
RETI
Register Bank
Validation
Process
Started
Stopped
Register Bank
Validation
Process
Restarted Finished
MCA04875
Figure 4-10 Validation Process Interrupted by Local-Bank Interrupt
Local Bank
Global Bank
Execution
Task A
Global Bank
Execution
Task B
Interrupt of
Task C
recognized
Execution of
SCXT CP
Interrupt of
Task B
recognized
Local Bank
Global Bank
Execution
Task B
Execution
Task A
Execution
Task C
Execution of
RETI
Register Bank
Validation
Process
Restarted Finished
Register Bank
Validation
Process
Started
Stopped
Execution of
RETI
MCA04876
Figure 4-11 Validation Process Interrupted by Local- and Global-Bank Intr.
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Preliminary
4.5.2.1
Central Processing Unit (CPU)
The Context Pointer (CP)
This non-bit-addressable register selects the current global register bank context. It can
be updated via any instruction capable of modifying SFRs.
CP
Context Pointer
SFR (FE10H/08H)
11
10
9
8
7
6
Reset Value: FC00H
15
14
13
12
5
4
3
2
1
0
1
1
1
1
cp
0
r
r
r
r
rw
r
Field
Bits
Type
Description
cp
[11:1]
rw
Modifiable Portion of Register CP
Specifies the (word) base address of the current
global (memory-mapped) register bank.
When writing a value to register CP with bits CP[11:9]
= 000B, bits CP[11:10] are set to 11B by hardware.
Note: It is the user’s responsibility to ensure that the physical GPR address specified via
CP register plus short GPR address is always an internal DPRAM location. If this
condition is not met, unexpected results may occur. Do not set CP below the
internal DPRAM start address. Do not set CP above FDE0H, otherwise the store
phase will overwrite SFRs (beginning at FE00H).
The XC2000 switches the complete memory-mapped GPR bank with a single
instruction. After switching, the service routine executes within its own separate context.
The instruction “SCXT CP, #New_Bank” pushes the value of the current context pointer
(CP) into the system stack and loads CP with the immediate value “New_Bank”, which
selects a new register bank. The service routine may now use its “own registers”. This
memory register bank is preserved when the service routine terminates, i.e. its contents
are available on the next call.
Before returning from the service routine (RETI), the previous CP is simply popped from
the system stack which returns the registers to the original bank.
Note: Due to the internal instruction pipeline, a write operation to the CP register stalls
the instruction flow until the register file context switch is really executed. The
instruction immediately following the instruction that updates CP register can use
the new value of the changed CP.
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Preliminary
4.6
Central Processing Unit (CPU)
Code Addressing
The XC2000 provides a total addressable memory space of 16 Mbytes. This address
space is arranged as 256 segments of 64 Kbytes each. A dedicated 24-bit code address
pointer is used to access the memories for instruction fetches. This pointer has two parts:
an 8-bit code segment pointer CSP and a 16-bit offset pointer called Instruction Pointer
(IP). The concatenation of the CSP and IP results directly in a correct 24-bit physical
memory address.
Memory organized
in segments
15
87
CSP
0
15
IP
0
255
FF'0000H
254
FE'0000H
1
01'0000H
0
00'0000H
23
16 15
Segment
0
Offset
MCA04920
Figure 4-12 Addressing via the Code Segment and Instruction Pointer
tbd RAS
The Code Segment Pointer CSP selects the code segment being used at run-time to
access instructions. The lower 8 bits of register CSP select one of up 256 segments of
64 Kbytes each, while the higher 8 bits are reserved for future use. The reset value is
specified by the contents of the VECSEG register (Section 5.3).
Note: Register CSP can only be read but cannot be written by data operations.
In segmented memory mode (default after reset), register CSP is modified either
directly by JMPS and CALLS instructions, or indirectly via the stack by RETS and RETI
instructions.
In non-segmented memory mode (selected by setting bit SGTDIS in register
CPUCON1), CSP is fixed to the segment of the instruction that disabled segmentation.
Modification by inter-segment CALLs or RETurns is no longer possible.
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Central Processing Unit (CPU)
For processing an accepted interrupt or a TRAP, register CSP is automatically loaded
with the segment of the vector table (defined in register VECSEG).
Note: For the correct execution of interrupt tasks in non-segmented memory mode, the
contents of VECSEG must select the same segment as the current value of CSP,
i.e. the vector table must be located in the segment pointed to by the CSP.
CSP
Code Segment Pointer
SFR (FE08H/04H)
7
6
Reset Value: xxxxH
15
14
13
12
11
10
9
8
5
4
3
-
-
-
-
-
-
-
-
SEGNR
-
-
-
-
-
-
-
-
rh
2
1
0
Field
Bits
Type
Description
SEGNR
[7:0]
rh
Specifies the code segment from which the current
instruction is to be fetched.
Note: After a reset, register CSP is automatically loaded from register VECSEG.
The Instruction Pointer IP determines the 16-bit intra-segment address of the currently
fetched instruction within the code segment selected by the CSP register. Register IP is
not mapped into the XC2000’s address space; thus, it is not directly accessible by the
programmer. However, the IP can be modified indirectly via the stack by means of a
return instruction. IP is implicitly updated by the CPU for branch instructions and after
instruction fetch operations.
IP
Instruction Pointer
15
14
13
12
- - - (- - - -/- -)
11
10
9
8
7
Reset Value: 0000H
6
5
4
3
2
1
0
ip
0
(r)(w)h
r
Field
Bits
Type
Description
ip
[15:1]
h
Specifies the intra segment offset from which the
current instruction is to be fetched. IP refers to the
current segment <SEGNR>.
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4.7
Central Processing Unit (CPU)
Data Addressing
The Address Data Unit (ADU) contains two independent arithmetic units to generate,
calculate, and update addresses for data accesses, the Standard Address Generation
Unit (SAGU) and the DSP Address Generation Unit (DAGU). The ADU performs the
following major tasks:
•
•
•
•
Standard Address Generation (SAGU)
DSP Address Generation (DAGU)
Data Paging (SAGU)
Stack Handling (SAGU)
The SAGU supports linear arithmetic for the indirect addressing modes and also
generates the address in case of all other short and long addressing modes.
The DAGU contains an additional set of address pointers and offset registers which are
used in conjunction with the CoXXX instructions only.
The CPU provides a lot of powerful addressing modes (short, long, indirect) for word,
byte, and bit data accesses. The different addressing modes use different formats and
have different scopes.
4.7.1
Short Addressing Modes
Short addressing modes allow access to the GPR, SFR or bit-addressable memory
space. All of these addressing modes use an offset (8/4/2 bits) together with an implicit
base address to specify a 24-bit physical address:
Table 4-17
Short Addressing Modes
Mnemo- Base
nic
Address1)
Offset
Short Address Scope of Access
Range
Rw
(CP)
2 × Rw
0 … 15
GPRs (word)
Rb
(CP)
1 × Rb
0 … 15
GPRs (byte)
reg
00’FE00H
00’F000H
(CP)
(CP)
2 × reg
2 × reg
2 × (reg ∧ 0FH)
1 × (reg ∧ 0FH)
00H … EFH
00H … EFH
F0H … FFH
F0H … FFH
SFRs (word, low byte)
ESFRs (word, low byte)
GPRs (word)
GPRs (bytes)
bitoff
00’FD00H
00’FF00H
00’F100H
(CP)
2 × bitoff
2 × (bitoff ∧ 7FH)
2 × (bitoff ∧ 7FH)
2 × (bitoff ∧ 0FH)
00H … 7FH
80H … EFH
80H … EFH
F0H … FFH
RAM Bit word offset
SFR Bit word offset
ESFR Bit word offset
GPR Bit word offset
bitaddr
Bit word
see bitoff
Immediate bit
position
0 … 15
Any single bit
1) Accesses to general purpose registers (GPRs) may also access local register banks, instead of using CP.
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Central Processing Unit (CPU)
Physical Address = Base Address + ∆ × Short Address
Note: ∆ is 1 for byte GPRs, ∆ is 2 for word GPRs.
Rw, Rb: Specifies direct access to any GPR in the currently active context (global
register bank or local register bank). Both ‘Rw’ and ‘Rb’ require four bits in the instruction
format. The base address of the global register bank is determined by the contents of
register CP. ‘Rw’ specifies a 4-bit word GPR address, ‘Rb’ specifies a 4-bit byte GPR
address within a local register bank or relative to (CP).
reg: Specifies direct access to any (E)SFR or GPR in the currently active context (global
or local register bank). The ‘reg’ value requires eight bits in the instruction format. Short
‘reg’ addresses in the range from 00H to EFH always specify (E)SFRs. In that case, the
factor ‘∆’ equates 2 and the base address is 00’FE00H for the standard SFR area or
00’F000H for the extended ESFR area. The ‘reg’ accesses to the ESFR area require a
preceding EXT*R instruction to switch the base address. Depending on the opcode,
either the total word (for word operations) or the low byte (for byte operations) of an SFR
can be addressed via ‘reg’. Note that the high byte of an SFR cannot be accessed via
the ‘reg’ addressing mode. Short ‘reg’ addresses in the range from F0H to FFH always
specify GPRs. In that case, only the lower four bits of ‘reg’ are significant for physical
address generation and, therefore, it is identical to the address generation described for
the ‘Rb’ and ‘Rw’ addressing modes.
bitoff: Specifies direct access to any word in the bit addressable memory space. The
‘bitoff’ value requires eight bits in the instruction format. The specified ‘bitoff’ range
selects different base addresses to generate physical addresses (see Table 4-17). The
‘bitoff’ accesses to the ESFR area require a preceding EXT*R instruction to switch the
base address.
bitaddr: Any bit address is specified by a word address within the bit addressable
memory space (see ‘bitoff’) and a bit position (‘bitpos’) within that word. Therefore,
‘bitaddr’ requires twelve bits in the instruction format.
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4.7.2
Central Processing Unit (CPU)
Long Addressing Modes
Long addressing modes specify 24-bit addresses and, therefore, can access any word
or byte data within the entire address space. Long addresses can be specified in
different ways to generate the full 24-bit address:
•
•
•
Use one of the four Data Page Pointers (DPP registers): The used 16-bit pointer
selects a DPP with bits 15 … 14, bits 13 … 0 specify the 14-bit data page offset (see
Figure 4-13).
Select the used data page directly: The data page is selected by a preceeding
EXTP(R) instruction, bits 13 … 0 of the used 16-bit pointer specify the 14-bit data
page offset.
Select the used segment directly: The segment is selected by a preceeding
EXTS(R) instruction, the used 16-bit pointer specifies the 16-bit segment offset.
Note: Word accesses on odd byte addresses are not executed. A hardware trap will be
triggered.
16-Bit Data Address
Memory
15 14
0
255
FF'0000H
254
Selects DPP
9
DPP
0
FE'0000H
DPP3 - 11
DPP2 - 10
DPP1 - 01
X
DPP0 - 00
23
1
15 14
0
01'0000H
0
Page
Page Offset
Segment
Segment Offset
00'0000H
MCA04924
Figure 4-13 Data Page Pointer Addressing
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Preliminary
4.7.2.1
Central Processing Unit (CPU)
Data Page Pointers DPP0, DPP1, DPP2, DPP3
These four non-bit-addressable registers select up to four different data pages to be
active simultaneously at run-time. The lower 10 bits of each DPP register select one of
the 1024 possible 16-Kbyte data pages; the upper 6 bits are reserved for future use.
DPP0
Data Page Pointer 0
DPP1
Data Page Pointer 1
DPP2
Data Page Pointer 2
DPP3
Data Page Pointer 3
SFR (FE00H/00H)
Reset Value: 0000H
SFR (FE02H/01H)
Reset Value: 0001H
SFR (FE04H/02H)
Reset Value: 0002H
SFR (FE06H/03H)
Reset Value: 0003H
15
14
13
12
11
10
9
8
7
6
5
4
-
-
-
-
-
-
DPPxPN
-
-
-
-
-
-
rw
3
2
1
Field
Bits
Type
Description
DPPxPN
[9:0]
rw
Data Page Number of DPPx
Specifies the data page selected via DPPx.
0
The DPP registers allow access to the entire memory space in pages of 16 Kbytes each.
The DPP registers are implicitly used whenever data accesses to any memory location
are made via indirect or direct long 16-bit addressing modes (except for override
accesses via EXTended instructions and PEC data transfers). After reset, the Data Page
Pointers are initialized in such a way that all indirect or direct long 16-bit addresses result
in identical 18-bit addresses. This allows access to data pages 3 … 0 within segment 0
as shown in Figure 4-13. If the user does not want to use data paging, no further action
is required.
Data paging is performed by concatenating the lower 14 bits of an indirect or direct long
16-bit address with the contents of the DPP register selected by the upper two bits of the
16-bit address. The contents of the selected DPP register specify one of the 1024
possible data pages. This data page base address together with the 14-bit page offset
forms the physical 24-bit address (even if segmentation is disabled).
The selected number of segment address bits (via bitfield SALSEL) of the respective
DPP register is output on the respective segment address pins for all external data
accesses.
A DPP register can be updated via any instruction capable of modifying an SFR.
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Central Processing Unit (CPU)
Note: Due to the internal instruction pipeline, a write operation to the DPPx registers
could stall the instruction flow until the DPP is actually updated. The instruction
that immediately follows the instruction which updates the DPP register can use
the new value of the changed DPPx.
15 14 13
EXTP(R):
0
16-Bit Long Address
#pag
14-Bit Page Offset
24-Bit Physical Address
0
15
EXTS(R):
16-Bit Long Address
#seg
16-Bit Segment Offset
24-Bit Physical Address
MCA04925
Figure 4-14 Overriding the DPP Mechanism
Note: The overriding page or segment may be specified as a constant (#pag, #seg) or
via a word GPR (Rw).
Table 4-18
Long Addressing Modes
Mnemonic
Base Address1)
Offset
Scope of Access
mem
(DPPx)
mem ∧ 3FFFH
Any Word or Byte
mem
pag
mem ∧ 3FFFH
Any Word or Byte
mem
seg
mem
Any Word or Byte
1) Represents either a 10-bit data page number to be concatenated with a 14-bit offset, or an 8-bit segment
number to be concatenated with a 16-bit offset.
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4.7.3
Central Processing Unit (CPU)
Indirect Addressing Modes
Indirect addressing modes can be considered as a combination of short and long
addressing modes. This means that the “long” 16-bit pointer is provided indirectly by the
contents of a word GPR which itself is specified directly by a short 4-bit address
(‘Rw’ = 0 … 15).
There are indirect addressing modes, which add a constant value to the GPR contents
before the long 16-bit address is calculated. Other indirect addressing modes can
decrement or increment the indirect address pointers (GPR contents) by 2 or 1 (referring
to words or bytes) or by the contents of the offset registers QR0 or QR1.
Table 4-19
Generating Physical Addresses from Indirect Pointers
Step Executed Action
Calculation
Notes
1
Calculate the address of the GPR Address =
indirect pointer (word GPR) 2 × Short Addr.
from its short address
[+ (CP)]
see Table 4-17
2
Pre-decrement indirect
pointer (‘-Rw’) depending
on datatype (∆ = 1 or 2 for
byte or word operations)
(GPR Address) = Optional step, executed only if
(GPR Address)
required by addressing mode
-∆
3
Adjust the pointer by a
constant value
(‘Rw + const16’)
Pointer =
(GPR Address)
+ Constant
4
Calculate the physical 24-bit Physical Addr. = Uses DPPs or page/segment
address using the resulting Page/Segment + override mechanisms,
pointer
Pointer offset
see Table 4-18
5
Post-in/decrement indirect (GPR Address) = Optional step, executed only if
pointer (‘Rw±’) depending
(GPR Address)
required by addressing mode
on datatype (∆ = 1 or 2 for ± ∆
byte or word operations), or
depending on offset
registers (∆ = QRx)1)
Optional step, executed only if
required by addressing mode
1) Post-decrement and QRx-based modification is provided only for CoXXX instructions.
Note: Some instructions only use the lowest four word GPRs (R3 … R0) as indirect
address pointers, which are specified via short 2-bit addresses in that case.
The following indirect addressing modes are provided:
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Table 4-20
Central Processing Unit (CPU)
Indirect Addressing Modes
Mnemonic
Particularities
[Rw]
Most instructions accept any GPR (R15 … R0) as indirect address
pointer. Some instructions accept only the lower four GPRs (R3 … R0).
[Rw+]
The specified indirect address pointer is automatically post-incremented
by 2 or 1 (for word or byte data operations) after the access.
[-Rw]
The specified indirect address pointer is automatically pre-decremented
by 2 or 1 (for word or byte data operations) before the access.
[Rw +
#data16]
The specified 16-bit constant is added to the indirect address pointer,
before the long address is calculated.
[Rw-]
The specified indirect address pointer is automatically postdecremented by 2 (word data operations) after the access.
[Rw + QRx]
The specified indirect address pointer is automatically post-incremented
by QRx (word data operations) after the access.
[Rw - QRx]
The specified indirect address pointer is automatically postdecremented by QRX (word data operations) after the access.
4.7.3.1
Offset Registers QR0 and QR1
The non-bit-addressable offset registers QR0 and QR1 are used with CoXXX
instructions. For possible instruction flow stalls refer to Section 4.3.4.
QR0
Offset Register
QR1
Offset Register
15
14
13
12
11
10
ESFR (F004H/02H)
Reset Value: 0000H
ESFR (F006H/03H)
Reset Value: 0000H
9
8
7
6
5
4
3
2
1
0
QR
0
rw
r
Field
Bits
Type
Description
QR
[15:1]
rw
Modifiable Portion of Register QRx
Specifies the 16-bit word offset address for indirect
addressing modes (LSB always zero).
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4.7.4
Central Processing Unit (CPU)
DSP Addressing Modes
In addition to the Standard Address Generation Unit (SAGU), the DSP Address
Generation Unit (DAGU) provides an additional set of pointer registers (IDX0, IDX1) and
offset registers (QX0, QX1). The additional set of pointer registers IDX0 and IDX1 allows
the execution of DSP specific CoXXX instructions in one CPU cycle. An independent
arithmetic unit allows the update of these dedicated pointer registers in parallel with the
GPR-pointer modification of the SAGU. The DAGU only supports indirect addressing
modes that use the special pointer registers IDX0 and IDX1.
The address pointers can be used for arithmetic operations as well as for the special
CoMOV instruction. The generation of the 24-bit memory address is different:
•
For CoMOV instructions, the IDX pointers are concatenated with the DPPs or the
selected page/segment address, as described for long addressing modes (see
Figure 4-13 for a summary).
For arithmetic CoXXX instructions, the IDX pointers are automatically extended to
a 24-bit memory address pointing to the internal DPRAM area, as shown in
Figure 4-15.
•
IDX0
Address Pointer
IDX1
Address Pointer
15
14
13
12
11
10
SFR (FF08H/84H)
Reset Value: 0000H
SFR (FF0AH/85H)
Reset Value: 0000H
9
8
7
6
5
4
3
2
1
0
idx
0
rw
r
Field
Bits
Type
Description
idx
[15:1]
rw
Modifiable Portion of Register IDXx
Specifies the 16-bit word address pointer
Note: During the initialization of the IDX registers, instruction flow stalls are possible. For
the proper operation, refer to Section 4.3.4.
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Central Processing Unit (CPU)
There are indirect addressing modes which allow parallel data move operations before
the long 16-bit address is calculated (see Figure 4-16 for an example). Other indirect
addressing modes allow decrementing or incrementing the indirect address pointers
(IDXx contents) by 2 or by the contents of the offset registers QX0 and QX1 (used in
conjunction with the IDX pointers).
QX0
Offset Register
QX1
Offset Register
15
14
13
12
11
10
ESFR (F000H/00H)
Reset Value: 0000H
ESFR (F002H/01H)
Reset Value: 0000H
9
8
7
6
5
4
3
2
1
0
qx
0
rw
r
Field
Bits
Type
Description
qx
[15:1]
rw
Modifiable Portion of Register QXx
Specifies the 16-bit word offset for indirect
addressing modes
Note: During the initialization of the QX registers, instruction flow stalls are possible. For
the proper operation, refer to Section 4.3.4.
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Central Processing Unit (CPU)
15
Memory
16-Bit IDX Pointer
12 11
0
12 11
0
2
02'0000H
1
01'0000H
DPRAM in Data Page 3
0
23
00'0000H
15
000000001111
MCA04926
Figure 4-15 Arithmetic MAC Operations and Addressing via the IDX Pointers
Table 4-21
Generating Physical Addresses from Indirect Pointers (IDXx)
Step Executed Action
Calculation
Notes
1
Determine the used IDXx
pointer
---
–
2
Calculate an intermediate
Interm. Addr. =
long address for the parallel (IDXx Address)
data move operation and
±∆
in/decrement indirect
pointer (‘IDXx±’) by 2
(∆ = 2), or depending on
offset registers (∆ = QXx)
Optional step, executed only if
required by instruction
CoXXXM and addressing
mode
3
Calculate long 16-bit
address
–
4
Calculate the physical 24-bit Physical Addr. = Uses DPPs or page/segment
address using the resulting Page/Segment + override mechanisms, see
pointer
Pointer offset
Table 4-18 and Figure 4-15
5
Post-in/decrement indirect
pointer (‘IDXx±’) by 2
(∆ = 2), or depending on
offset registers (∆ = QXx)
User’s Manual
CPUSV2_X, V2.2
Long Address =
(IDXx Pointer)
(IDXx Pointer) =
(IDXx Pointer)
±∆
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Optional step, executed only if
required by addressing mode
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Central Processing Unit (CPU)
The following indirect addressing modes are provided:
Table 4-22
DSP Addressing Modes
Mnemonic
Particularities
[IDXx]
Most CoXXX instructions accept IDXx (IDX0, IDX1) as an indirect
address pointer.
[IDXx+]
The specified indirect address pointer is automatically post-incremented
by 2 after the access.
with parallel
data move
In case of a CoXXXM instruction, the address stored in the specified
indirect address pointer is automatically pre-decremented by 2 for the
parallel move operation. The pointer itself is not pre-decremented.
Then, the specified indirect address pointer is automatically postincremented by 2 after the access.
[IDXx-]
The specified indirect address pointer is automatically postdecremented by 2 after the access.
with parallel
data move
In case of a CoXXXM instruction, the address stored in the specified
indirect address pointer is automatically pre-incremented by 2 for the
parallel move operation. The pointer itself is not pre-incremented. Then,
the specified indirect address pointer is automatically post-decremented
by 2 after the access.
[IDXx + QXx]
The specified indirect address pointer is automatically post-incremented
by QXx after the access.
with parallel
data move
In case of a CoXXXM instruction, the address stored in the specified
indirect address pointer is automatically pre-decremented by QXx for
the parallel move operation. The pointer itself is not pre-decremented.
Then, the specified indirect address pointer is automatically postincremented by QXx after the access.
[IDXx - QXx]
The specified indirect address pointer is automatically postdecremented by QXx after the access.
with parallel
data move
In case of a CoXXXM instruction, the address stored in the specified
indirect address pointer is automatically pre-incremented by QXx for the
parallel move operation. The pointer itself is not pre-incremented. Then,
the specified indirect address pointer is automatically post-decremented
by QXx after the access.
Note: An example for parallel data move operations can be found in Figure 4-16.
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Central Processing Unit (CPU)
The CoREG Addressing Mode
The CoSTORE instruction utilizes the special CoREG addressing mode for immediate
storage of the MAC-Unit register after a MAC operation. The address of the MAC-Unit
register is coded in the CoSTORE instruction format as described in Table 4-23:
Table 4-23
Coding of the CoREG Addressing Mode
Mnemonic
Register
Coding of wwww:w bits [31:27]
MSW
MAC-Unit Status Word
00000
MAH
MAC-Unit Accumulator High Word
00001
MAS
Limited MAC-Unit Accumulator High 00010
Word
MAL
MAC-Unit Accumulator Low Word
00100
MCW
MAC-Unit Control Word
00101
MRW
MAC-Unit Repeat Word
00110
The example in Figure 4-16 shows the complex operation of CoXXXM instructions with
a parallel move operation based on the descriptions about addressing modes given in
Section 4.7.3 (Indirect Addressing Modes) and Section 4.7.4 (DSP Addressing
Modes).
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Central Processing Unit (CPU)
CoXXXMxx [IDX0+], [R2+]
Address Operations
1) Calculate Pointer Addresses
IDXx = IDX0
R2 Address = CP + 2 × 2
(Global Register Bank)
2) Intermediate Address of Write Pointer
for the Parallel Move Operation
Intermediate Address = (IDX0) - 2
3) Calculate Long 16-Bit Address
Long Address 1 = (IDX0)
Long Address 2 = (R2)
4) Calculate 24-Bit Physical Address
Physical Address 1 = Page 3 + Page Offset
Physical Address 2 = (DPPi) + Page Offset
5) Post Modify Address Pointer
(IDX0)new = (IDX0) + 2
(R2)new = (R2) + 2
Data Operations
1) Read Operands
op1 = (Physical Address 1)
op2 = (Physical Address 2)
1) Write Operand op1
(Intermediate Address) = op1
(IDX0)new (Updated Pointer)
(R2)new (Updated Pointer)
op1
op2
(IDX0) (Read Pointer)
Parallel
Move
(R2) (Read Pointer)
Intermediate Address
(Write Pointer for Parallel Move)
MCA04928
Figure 4-16 Arithmetic MAC Operations with Parallel Move
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Preliminary
4.7.5
Central Processing Unit (CPU)
The System Stack
The XC2000 supports a system stack of up to 64 Kbytes. The stack can be located
internally in one of the on-chip memories or externally. The 16-bit Stack Pointer register
(SP) addresses the stack within a 64-Kbyte segment selected by the Stack Pointer
Segment register (SPSG). A virtual stack (usually bigger than 64 Kbytes) can be
implemented by software. This mechanism is supported by the Stack Overflow register
STKOV and the Stack Underflow register STKUN (see descriptions below).
4.7.5.1
The Stack Pointer Registers SP and SPSEG
Register SPSEG (not bitaddressable) selects the segment being used at run-time to
access the system stack. The lower eight bits of register SPSEG select one of up
256 segments of 64 Kbytes each, while the higher 8 bits are reserved for future use.
The Stack Pointer SP (not bitaddressable) points to the top of the system stack (TOS).
SP is pre-decremented whenever data is pushed onto the stack, and it is postincremented whenever data is popped from the stack. Therefore, the system stack
grows from higher towards lower memory locations.
System stack addresses are generated by directly extending the 16-bit contents of
register SP by the contents of register SPSG, as shown in Figure 4-17.
The system stack cannot cross a 64-Kbyte segment boundary.
Stack Pointer
Segment
SPSEG
15
7 SPSEGNR 0
15
SP
0
255
FF'0000H
254
FE'0000H
1
01'0000H
0
00'0000H
23
16 15
0
MCA04929
Figure 4-17 Addressing via the Stack Pointer
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Central Processing Unit (CPU)
SP
Stack Pointer Register
15
14
13
12
SFR (FE12H/09H)
11
10
9
8
7
6
Reset Value: FC00H
5
4
3
1
0
sp
0
rwh
r
Field
Bits
Type
Description
sp
[15:1]
rwh
Modifiable Portion of Register SP
Specifies the top of the system stack.
SPSEG
Stack Pointer Segment
2
SFR (FF0CH/86H)
7
6
Reset Value: 0000H
15
14
13
12
11
10
9
8
5
4
3
-
-
-
-
-
-
-
-
SPSEGNR
-
-
-
-
-
-
-
-
rw
2
1
Field
Bits
Type
Description
SPSEGNR
[7:0]
rw
Stack Pointer Segment Number
Specifies the segment where the stack is located.
0
Note: SPSEG and SP can be updated via any instruction capable of modifying a 16-bit
SFR. Due to the internal instruction pipeline, a write operation to SPSG or SP
stalls the instruction flow until the register is really updated. The instruction
immediately following the instruction updating SPSG or SP can use the new value.
Extreme care should be taken when changing the contents of the stack pointer
registers. Improper changes may result in erroneous system behavior.
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4.7.5.2
Central Processing Unit (CPU)
The Stack Overflow/Underflow Pointers STKOV/STKUN
These limit registers (not bit-addressable) supervise the stack pointer. A trap is
generated when the stack pointer reaches its upper or lower limit. The Stack Pointer
Segment Register SPSG is not taken into account for the stack pointer comparison. The
system stack cannot cross a 64-Kbyte segment.
STKOV is compared with SP before each implicit write operation which decrements the
contents of SP (instructions CALLA, CALLI, CALLR, CALLS, PCALL, TRAP, SCXT, or
PUSH). If the contents of SP are equal to the contents of STKOV a stack overflow trap
is triggered.
STKUN is compared with SP before each implicit read operation which increments the
contents of SP (instructions RET, RETS, RETP, RETI, or POP). If the contents of SP are
equal to the contents of STKUN a stack underflow trap is triggered.
The Stack Overflow/Underflow Traps may be used in two different ways:
•
•
Fatal error indication treats the stack overflow as a system error and executes the
associated trap service routine.
In case of a stack overflow trap, data in the bottom of the stack may have been
overwritten by the status information stacked upon servicing the trap itself.
Virtual stack control allows the system stack to be used as a ‘Stack Cache’ for a
bigger external user stack: flush cache in case of an overflow, refill cache in case of
an underflow.
Scope of Stack Limit Control
The stack limit control implemented by the register pair STKOV and STKUN detects
cases in which the Stack Pointer (SP) crosses the defined stack area as a result of an
implicit change.
If the stack pointer was explicitly changed as a result of move or arithmetic instruction,
SP is not compared to the contents of STKOV and STKUN. In this case, a stack violation
will not be detected if the modified stack pointer is on or outside the defined limits, i.e.
below (STKOV) or above (STKUN). Stack overflow/underflow is detected only in case of
implicit SP modification.
SP may be operated outside the permitted SP range without triggering a trap. However,
if SP reaches the limit of the permitted SP range from outside the range as a result of an
implicit change (PUSH or POP, for example), the respective trap will be triggered.
Note: STKOV and STKUN can be updated via any instruction capable of modifying an
SFR. If a stack overflow or underflow event occurs in an ATOMIC/EXT sequence,
the stack operations that are part of the sequence are completed. The trap is
issued after the completion of the entire ATOMIC/EXT sequence.
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Central Processing Unit (CPU)
STKOV
Stack Overflow Reg.
15
14
13
12
SFR (FE14H/0AH)
11
10
9
8
7
6
Reset Value: FA00H
5
4
3
2
1
stkov
0
0
rw
Field
Bits
Type
Description
stkov
[15:1]
rw
Modifiable Portion of Register STKOV
Specifies the segment offset address of the lower
limit of the system stack.
STKUN
Stack Underflow Reg.
15
14
13
12
SFR (FE16H/0BH)
11
10
9
8
7
6
Reset Value: FC00H
5
4
3
2
1
stkun
0
rw
r
Field
Bits
Type
Description
stkun
[15:1]
rw
Modifiable Portion of Register STKUN
Specifies the segment offset address of the upper
limit of the system stack.
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4.8
Central Processing Unit (CPU)
Standard Data Processing
All standard arithmetic, shift-, and logical operations are performed in the 16-bit ALU. In
addition to the standard functions, the ALU of the XC2000 includes a bit-manipulation
unit and a multiply and divide unit. Most internal execution blocks have been optimized
to perform operations on either 8-bit or 16-bit numbers. After the pipeline has been filled,
most instructions are completed in one CPU cycle. The status flags are automatically
updated in register PSW after each ALU operation and reflect the current state of the
microcontroller. These flags allow branching upon specific conditions. Support of both
signed and unsigned arithmetic is provided by the user selectable branch test. The
status flags are also preserved automatically by the CPU upon entry into an interrupt or
trap routine. Another group of bits represents the current CPU interrupt status. Two
separate bits (USR0 and USR1) are provided as general purpose flags.
PSW
Processor Status Word
15
14
13
12
SFR
11
10
ILVL
IEN
HLD
EN
BANK
rwh
rw
rw
rwh
Type
9
8
7
Reset Value: 0000H
6
5
USR USR MUL
1
0
IP
rwh
rwh
r
4
3
2
1
0
E
Z
V
C
N
rwh
rwh
rwh
rwh
rwh
Field
Bits
Description
ILVL
[15:12] rwh
CPU Priority Level
0H Lowest Priority
…
…
FH Highest Priority
IEN
11
rw
Global Interrupt/PEC Enable Bit
0
Interrupt/PEC requests are disabled
1
Interrupt/PEC requests are enabled
HLDEN
10
rw
Hold Enable
0
External bus arbitration disabled
1
External bus arbitration enabled
Note: The selected arbitration mode is activated
when HLDEN is set for the first time.
BANK
User’s Manual
CPUSV2_X, V2.2
[9:8]
rwh
Reserved for Register File Bank Selection
00
Global register bank
01
Reserved
10
Local register bank 1
11
Local register bank 2
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Field
Bits
Type
Description
USR1
7
rwh
General Purpose Flag
May be used by application
USR0
6
rwh
General Purpose Flag
May be used by application
MULIP
5
r
Multiplication/Division in Progress
Note: Always set to 0 (MUL/DIV not interruptible),
for compatibility with existing software.
E
4
rwh
End of Table Flag
0
Source operand is neither 8000H nor 80H
1
Source operand is 8000H or 80H
Z
3
rwh
Zero Flag
0
ALU result is not zero
1
ALU result is zero
V
2
rwh
Overflow Flag
0
No Overflow produced
1
Overflow produced
C
1
rwh
Carry Flag
0
No carry/borrow bit produced
1
Carry/borrow bit produced
N
0
rwh
Negative Result
0
ALU result is not negative
1
ALU result is negative
ALU/MAC Status (N, C, V, Z, E, USR0, USR1)
The condition flags (N, C, V, Z, E) within the PSW indicate the ALU status after the most
recently performed ALU operation. They are set by most of the instructions according to
specific rules which depend on the ALU or data movement operation performed by an
instruction.
After execution of an instruction which explicitly updates the PSW register, the condition
flags cannot be interpreted as described below because any explicit write to the PSW
register supersedes the condition flag values which are implicitly generated by the CPU.
Explicitly reading the PSW register supplies a read value which represents the state of
the PSW register after execution of the immediately preceding instruction.
Note: After reset, all of the ALU status bits are cleared.
N-Flag: For most of the ALU operations, the N-flag is set to 1, if the most significant bit
of the result contains a 1; otherwise, it is cleared. In the case of integer operations, the
N-flag can be interpreted as the sign bit of the result (negative: N = 1, positive: N = 0).
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Negative numbers are always represented as the 2’s complement of the corresponding
positive number. The range of signed numbers extends from -8000H to +7FFFH for the
word data type, or from -80H to +7FH for the byte data type. For Boolean bit operations
with only one operand, the N-flag represents the previous state of the specified bit. For
Boolean bit operations with two operands, the N-flag represents the logical XORing of
the two specified bits.
C-Flag: After an addition, the C-flag indicates that a carry from the most significant bit of
the specified word or byte data type has been generated. After a subtraction or a
comparison, the C-flag indicates a borrow which represents the logical negation of a
carry for the addition.
This means that the C-flag is set to 1, if no carry from the most significant bit of the
specified word or byte data type has been generated during a subtraction, which is
performed internally by the ALU as a 2’s complement addition, and, the C-flag is cleared
when this complement addition caused a carry.
The C-flag is always cleared for logical, multiply and divide ALU operations, because
these operations cannot cause a carry.
For shift and rotate operations, the C-flag represents the value of the bit shifted out last.
If a shift count of zero is specified, the C-flag will be cleared. The C-flag is also cleared
for a prioritize ALU operation, because a 1 is never shifted out of the MSB during the
normalization of an operand.
For Boolean bit operations with only one operand, the C-flag is always cleared. For
Boolean bit operations with two operands, the C-flag represents the logical ANDing of
the two specified bits.
V-Flag: For addition, subtraction, and 2’s complementation, the V-flag is always set to 1
if the result exceeds the range of 16-bit signed numbers for word operations (-8000H to
+7FFFH), or 8-bit signed numbers for byte operations (-80H to +7FH). Otherwise, the
V-flag is cleared. Note that the result of an integer addition, integer subtraction, or 2’s
complement is not valid if the V-flag indicates an arithmetic overflow.
For multiplication and division, the V-flag is set to 1 if the result cannot be represented
in a word data type; otherwise, it is cleared. Note that a division by zero will always cause
an overflow. In contrast to the result of a division, the result of a multiplication is valid
whether or not the V-flag is set to 1.
Because logical ALU operations cannot produce an invalid result, the V-flag is cleared
by these operations.
The V-flag is also used as a ‘Sticky Bit’ for rotate right and shift right operations. With
only using the C-flag, a rounding error caused by a shift right operation can be estimated
up to a quantity of one half of the LSB of the result. In conjunction with the V-flag, the
C-flag allows evaluation of the rounding error with a finer resolution (see Table 4-24).
For Boolean bit operations with only one operand, the V-flag is always cleared. For
Boolean bit operations with two operands, the V-flag represents the logical ORing of the
two specified bits.
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Table 4-24
Central Processing Unit (CPU)
Shift Right Rounding Error Evaluation
C-Flag
V-Flag
Rounding Error Quantity
0
0
1
1
0
1
0
1
No rounding error
0 < Rounding error < 1/2 LSB
Rounding error = 1/2 LSB
Rounding error > 1/2 LSB
Z-Flag: The Z-flag is normally set to 1 if the result of an ALU operation equals zero,
otherwise it is cleared.
For the addition and subtraction with carry, the Z-flag is only set to 1, if the Z-flag already
contains a 1 and the result of the current ALU operation also equals zero. This
mechanism is provided to support multiple precision calculations.
For Boolean bit operations with only one operand, the Z-flag represents the logical
negation of the previous state of the specified bit. For Boolean bit operations with two
operands, the Z-flag represents the logical NORing of the two specified bits. For the
prioritize ALU operation, the Z-flag indicates whether the second operand was zero.
E-Flag: End of table flag. The E-flag can be altered by instructions which perform ALU
or data movement operations. The E-flag is cleared by those instructions which cannot
be reasonably used for table search operations. In all other cases, the E-flag value
depends on the value of the source operand to signify whether the end of a search table
is reached or not. If the value of the source operand of an instruction equals the lowest
negative number which is representable by the data format of the corresponding
instruction (8000H for the word data type, or 80H for the byte data type), the E-flag is set
to 1; otherwise, it is cleared.
General Control Functions (USR0, USR1, BANK, HLDEN)
A few bits in register PSW are dedicated to general control functions. Thus, they are
saved and restored automatically upon task switches and interrupts.
USR0/USR1-Flags: These bits can be set automatically during the execution of
repeated MAC instructions. These bits can also be used as general flags by an
application.
BANK: Bitfield BANK selects the currently active register bank (local or global). Bitfield
BANK is updated implicitly by hardware upon entering an interrupt service routine, and
by a RETI instruction. It can be also modified explicitly via software by any instruction
which can write to PSW.
HLDEN: Setting this bit for the first time activates the selected bus arbitration mode (see
Section 9.3.9). Bus arbitration can be disabled by temporarily clearing bit HLDEN. In this
case the bus is locked, while the bus arbitration mode remains selected.
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Central Processing Unit (CPU)
CPU Interrupt Status (IEN, ILVL)
IEN: The Interrupt Enable bit allows interrupts to be globally enabled (IEN = 1) or
disabled (IEN = 0).
ILVL: The four-bit Interrupt Level field (ILVL) specifies the priority of the current CPU
activity. The interrupt level is updated by hardware on entry into an interrupt service
routine, but it can also be modified via software to prevent other interrupts from being
acknowledged. If an interrupt level 15 has been assigned to the CPU, it has the highest
possible priority; thus, the current CPU operation cannot be interrupted except by
hardware traps or external non-maskable interrupts. For details refer to Chapter 5.
After reset, all interrupts are globally disabled, and the lowest priority (ILVL = 0) is
assigned to the initial CPU activity.
4.8.1
16-bit Adder/Subtracter, Barrel Shifter, and 16-bit Logic Unit
All standard arithmetic and logical operations are performed by the 16-bit ALU. In case
of byte operations, signals from bits 6 and 7 of the ALU result are used to control the
condition flags. Multiple precision arithmetic is supported by a “CARRY-IN” signal to the
ALU from previously calculated portions of the desired operation.
A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotations and
arithmetic shifts are also supported.
4.8.2
Bit Manipulation Unit
The XC2000 offers a large number of instructions for bit processing. These instructions
either manipulate software flags within the internal RAM, control on-chip peripherals via
control bits in their respective SFRs, or control IO functions via port pins.
Unlike other microcontrollers, the XC2000 features instructions that provide direct
access to two operands in the bit addressable space without requiring them to be moved
to temporary locations. Multiple bit shift instructions have been included to avoid long
instruction streams of single bit shift operations. These instructions require a single CPU
cycle.
The instructions BSET, BCLR, BAND, BOR, BXOR, BMOV, BMOVN explicitly set or
clear specific bits. The bitfield instructions BFLDL and BFLDH allow manipulation of up
to 8 bits of a specific byte at one time. The instructions JBC and JNBS implicitly clear or
set the specified bit when the jump is taken. The instructions JB and JNB (also
conditional jump instructions that refer to flags) evaluate the specified bit to determine if
the jump is to be taken.
Note: Bit operations on undefined bit locations will always read a bit value of ‘0’, while
the write access will not affect the respective bit location.
All instructions that manipulate single bits or bit groups internally use a read-modify-write
sequence that accesses the whole word containing the specified bit(s).
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Central Processing Unit (CPU)
This method has several consequences:
•
•
The read-modify-write approach may be critical with hardware-affected bits. In these
cases, the hardware may change specific bits while the read-modify-write operation
is in progress; thus, the writeback would overwrite the new bit value generated by the
hardware. The solution is provided by either the implemented hardware protection
(see below) or through special programming (see Section 4.3).
Bits can be modified only within the internal address areas (internal RAM and SFRs).
External locations cannot be used with bit instructions.
The upper 256 bytes of SFR area, ESFR area, and internal DPRAM are bit-addressable;
so, the register bits located within those respective sections can be manipulated directly
using bit instructions. The other SFRs must be accessed byte/word wise.
Note: All GPRs are bit-addressable independently from the allocation of the register
bank via the Context Pointer (CP). Even GPRs which are allocated to non-bitaddressable RAM locations provide this feature.
Protected bits are not changed during the read-modify-write sequence, such as when
hardware sets an interrupt request flag between the read and the write of the readmodify-write sequence. The hardware protection logic guarantees that only the intended
bit(s) is/are affected by the write-back operation.
Note: If a conflict occurs between a bit manipulation generated by hardware and an
intended software access, the software access has priority and determines the
final value of the respective bit.
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4.8.3
Central Processing Unit (CPU)
Multiply and Divide Unit
The XC2000’s multiply and divide unit has two separated parts. One is the fast 16 ×
16-bit multiplier that executes a multiplication in one CPU cycle. The other one is a
division sub-unit which performs the division algorithm in 18 … 21 CPU cycles
(depending on the data and division types). The divide instruction requires four CPU
cycles to be executed. For performance reasons, the rest of the division algorithm runs
in the background during the following seventeen CPU cycles, while further instructions
are executed in parallel. Interrupt tasks can also be started and executed immediately
without any delay. If an instruction (from the original instruction stream or from the
interrupt task) tries to use the unit while a division is still running, the execution of this
new instruction is stalled until the previous division is finished.
To avoid these stalls, the multiply and division unit should not be used during the first
fourteen CPU cycles of the interrupt tasks. For example, this requires up to fourteen onecycle instructions to be executed between the interrupt entry and the first instruction
which uses the multiply and divide unit again (worst case).
Multiplications and divisions implicitly use the 32-bit multiply/divide register MD
(represented by the concatenation of the two non-bit-addressable data registers MDH
and MDL) and the associated control register MDC. This bit-addressable 16-bit register
is implicitly used by the CPU when it performs a division or multiplication in the ALU.
After a multiplication, MD represents the 32-bit result. For long divisions, MD must be
loaded with the 32-bit dividend before the division is started. After any division, register
MDH represents the 16-bit remainder, register MDL represents the 16-bit quotient.
MDH
Multiply/Divide High Reg.
15
14
13
12
11
SFR (FE0CH/06H)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
mdh
rwh
Field
Bits
Type
Description
mdh
[15:0]
rwh
High Part of MD
The high order sixteen bits of the 32-bit multiply and
divide register MD.
User’s Manual
CPUSV2_X, V2.2
4-62
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
MDL
Multiply/Divide Low Reg.
15
14
13
12
11
SFR (FE0EH/07H)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
mdl
rwh
Field
Bits
Type
Description
mdl
[15:0]
rwh
Low Part of MD
The low order sixteen bits of the 32-bit multiply and
divide register MD.
Whenever MDH or MDL is updated via software, the Multiply/Divide Register In Use flag
(MDRIU) in the Multiply/Divide Control register (MDC) is set to ‘1’. The MDRIU flag is
cleared, whenever register MDL is read via software.
MDC
Multiply/Divide Control Reg.
SFR (FF0EH/87H)
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
MDR
IU
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
r(w)h
-
-
-
-
Field
Bits
Type
Description
MDRIU
4
rwh
Multiply/Divide Register In Use
0
Cleared when MDL is read via software.
1
Set when MDL or MDH is written via software,
or when a multiply or divide instruction is
executed.
Note: The MDRIU flag indicates the usage of register MD (MDL and MDH). In this case
MD must be saved prior to a new multiplication or division operation.
User’s Manual
CPUSV2_X, V2.2
4-63
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.9
Central Processing Unit (CPU)
DSP Data Processing (MAC Unit)
The new CoXXX arithmetic instructions are performed in the MAC unit. The MAC unit
provides single-instruction-cycle, non-pipelined, 32-bit additions; 32-bit subtraction; right
and left shifts; 16-bit by 16-bit multiplication; and multiplication with cumulative
subtraction/addition. The MAC unit includes the following major components, shown in
Figure 4-18:
•
•
•
•
•
•
•
•
16-bit by 16-bit signed/unsigned multiplier with signed result1)
Concatenation Unit
Scaler (one-bit left shifter) for fractional computing
40-bit Adder/Subtracter
40-bit Signed Accumulator
Data Limiter
Accumulator Shifter
Repeat Counter
16-Bit Input Operands
16
16
16
Repeat Counter
MCW Register
16
Signed/
Unsigned
Multiplier
Concatenation
Unit
32
32
32
Signed
Ext.
40-Bit Adder/Subtracter
40
Round + Saturation
ACCU-Shifter
40
40-Bit Signed
Accumulator
40
40
MSW Register
Limiter
MCA04930
Figure 4-18 Functional MAC Unit Block Diagram
1) The same hardware-multiplier is used in the ALU.
User’s Manual
CPUSV2_X, V2.2
4-64
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.9.1
Central Processing Unit (CPU)
MAC Unit Control
The working register of the MAC unit is a dedicated 40-bit accumulator register. A set of
consistent flags is automatically updated in status register MSW after each MAC
operation. These flags allow branching on specific conditions. Unlike the PSW flags,
these flags are not preserved automatically by the CPU upon entry into an interrupt or
trap routine. All dedicated MAC registers must be saved on the stack if the MAC unit is
shared between different tasks and interrupts. General properties of the MAC unit are
selected via the MAC control word MCW.
MCW
MAC Control Word
SFR (FFDCH/EEH)
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
MP
MS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
rw
rw
-
-
-
-
-
-
-
-
-
Field
Bits
Type
Description
MP
10
rw
One-Bit Scaler Control
0
Multiplier product shift disabled
1
Multiplier product shift enabled for signed
multiplications
MS
9
rw
Saturation Control
0
Saturation disabled
1
Saturation to 32-bit value enabled
4.9.2
Representation of Numbers and Rounding
The XC2000 supports the 2’s complement representation of binary numbers. In this
format, the sign bit is the MSB of the binary word. This is set to zero for positive numbers
and set to one for negative numbers. Unsigned numbers are supported only by
multiply/multiply-accumulate instructions which specify whether each operand is signed
or unsigned.
In 2’s complement fractional format, the N-bit operand is represented using the 1.[N-1]
format (1 signed bit, N-1 fractional bits). Such a format can represent numbers between
-1 and +1 - 2-[N-1]. This format is supported when bit MP of register MCW is set.
The XC2000 implements 2’s complement rounding. With this rounding type, one is
added to the bit to the right of the rounding point (bit 15 of MAL), before truncation (MAL
is cleared).
User’s Manual
CPUSV2_X, V2.2
4-65
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.9.3
Central Processing Unit (CPU)
The 16-bit by 16-bit Signed/Unsigned Multiplier and Scaler
The multiplier executes 16-bit by 16-bit parallel signed/unsigned fractional and integer
multiplication in one CPU-cycle. The multiplier allows the multiplication of unsigned and
signed operands. The result is always presented in a signed fractional or integer format.
The result of the multiplication feeds a one-bit scaler to allow compensation for the extra
sign bit gained in multiplying two 16-bit 2’s complement numbers.
4.9.4
Concatenation Unit
The concatenation unit enables the MAC unit to perform 32-bit arithmetic operations in
one CPU cycle. The concatenation unit concatenates two 16-bit operands to a 32-bit
operand before the 32-bit arithmetic operation is executed in the 40-bit adder/subtracter.
The second required operand is always the current accumulator contents. The
concatenation unit is also used to pre-load the accumulator with a 32-bit value.
4.9.5
One-bit Scaler
The one-bit scaler can shift the result of the concatenation unit or the output of the
multiplier one bit to the left. The scaler is controlled by the executed instruction for the
concatenation or by control bit MP in register MCW.
If bit MP is set the product is shifted one bit to the left to compensate for the extra sign
bit gained in multiplying two 16-bit 2’s-complement numbers. The enabled automatic
shift is performed only if both input operands are signed.
4.9.6
The 40-bit Adder/Subtracter
The 40-bit Adder/Subtracter allows intermediate overflows in a series of
multiply/accumulate operations. The Adder/Subtracter has two input ports. The 40-bit
port is the feedback of the accumulator output through the ACCU-Shifter to the
Adder/Subtracter. The 32-bit port is the input port for the operand coming from the onebit Scaler. The 32-bit operands are signed and extended to 40 bits before the
addition/subtraction is performed.
The output of the Adder/Subtracter goes to the accumulator. It is also possible to round
the result and to saturate it on a 32-bit value automatically after every accumulation. The
round operation is performed by adding 00’0000’8000H to the result. Automatic
saturation is enabled by setting the saturation control bit MS in register MCW.
When the accumulator is in the overflow saturation mode and an overflow occurs, the
accumulator is loaded with either the most positive or the most negative value
representable in a 32-bit value, depending on the direction of the overflow as well as on
the arithmetic used. The value of the accumulator upon saturation is either
00’7FFF’FFFFH (positive) or FF’8000’0000H (negative).
User’s Manual
CPUSV2_X, V2.2
4-66
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.9.7
Central Processing Unit (CPU)
The Data Limiter
Saturation arithmetic is also provided to selectively limit overflow when reading the
accumulator by means of a CoSTORE <destination>., MAS instruction. Limiting is
performed on the MAC-Unit accumulator. If the contents of the accumulator can be
represented in the destination operand size without overflow, then the data limiter is
disabled and the operand is not modified. If the contents of the accumulator cannot be
represented without overflow in the destination operand size, the limiter will substitute a
“limited” data as explained in Table 4-25:
Table 4-25
Limiter Output
ME-flag
MN-flag
Output of Limiter
0
x
unchanged
1
0
7FFFH
1
1
8000H
Note: In this particular case, both the accumulator and the status register are not
affected. MAS is readable by means of a CoSTORE instruction only.
4.9.8
The Accumulator Shifter
The accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The
source accumulator shifting operations are:
•
•
•
No shift (Unmodified)
Up to 16-bit Arithmetic Left Shift
Up to 16-bit Arithmetic Right Shift
Notice that bits ME, MSV, and MSL in register MSW are affected by left shifts; therefore,
if the saturation mechanism is enabled (MS) the behavior is similar to the one of the
Adder/Subtracter.
Note: Certain precautions are required in case of left shift with saturation enabled.
Generally, if MAE contains significant bits, then the 32-bit value in the accumulator
is to be saturated. However, it is possible that left shift may move some significant
bits out of the accumulator. The 40-bit result will be misinterpreted and will be
either not saturated or saturated incorrectly. There is a chance that the result of
left shift may produce a result which can saturate an original positive number to
the minimum negative value, or vice versa.
User’s Manual
CPUSV2_X, V2.2
4-67
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.9.9
Central Processing Unit (CPU)
The 40-bit Signed Accumulator Register
The 40-bit accumulator consists of three concatenated registers MAE, MAH, and MAL.
MAE is 8 bits wide, MAH and MAL are 16 bits wide. MAE is the Most Significant Byte of
the 40-bit accumulator. This byte performs a guarding function. MAE is accessed as the
lower byte of register MSW.
When MAH is written, the value in the accumulator is automatically adjusted to signed
extended 40-bit format. That means MAL is cleared and MAE will be automatically
loaded with zeros for a positive number (the most significant bit of MAH is 0), and with
ones for a negative number (the most significant bit of MAH is 1), representing the
extended 40-bit negative number in 2’s complement notation. One may see that the
extended 40-bit value is equal to the 32-bit value without extension. In other words, after
this extension, MAE does not contain significant bits. Generally, this condition is present
when the highest 9 bits of the 40-bit signed result are the same.
During the accumulator operations, an overflow may happen and the result may not fit
into 32 bits and MAE will change. The extension flag “E” in register MSW is set when the
signed result in the accumulator has exceeded the 32-bit boundary. This condition is
present when the highest 9 bits of the 40-bit signed result are not the same, i.e. MAE
contains significant bits.
Most CoXXX operations specify the 40-bit accumulator register as a source and/or a
destination operand.
MAL
Accumulator Low Word
15
14
13
12
11
SFR (FE5CH/2EH)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
MAL
rwh
Field
Bits
Type
Description
MAL
[15:0]
rwh
Low Part of Accumulator
The 40-bit accumulator is completed by the
accumulator high word (MAH) and bitfield MAE
User’s Manual
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4-68
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
MAH
Accumulator High Word
15
14
13
12
11
SFR (FE5EH/2FH)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
MAH
rwh
Field
Bits
Type
Description
MAH
[15:0]
rwh
High Part of Accumulator
The 40-bit accumulator is completed by the
accumulator low word (MAL) and bitfield MAE
User’s Manual
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4-69
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.9.10
Central Processing Unit (CPU)
The MAC Unit Status Word MSW
The upper byte of register MSW (bit-addressable) shows the current status of the MAC
Unit. The lower byte of register MSW represents the 8-bit MAC accumulator extension,
building the 40-bit accumulator together with registers MAH and MAL.
MSW
MAC Status Word
15
14
13
12
SFR (FFDEH/EFH)
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
-
MV MSL ME MSV MC
MZ
MN
MAE
-
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
2
1
0
Field
Bits
Type
Description
MV
14
rwh
Overflow Flag
0
No Overflow produced
1
Overflow produced
MSL
13
rwh
Sticky Limit Flag
0
Result was not saturated
1
Result was saturated
ME
12
rwh
MAC Extension Flag
0
MAE does not contain significant bits
1
MAE contains significant bits
MSV
11
rwh
Sticky Overflow Flag
0
No Overflow occurred
1
Overflow occurred
MC
10
rwh
Carry Flag
0
No carry/borrow produced
1
Carry/borrow produced
MZ
9
rwh
Zero Flag
0
MAC result is not zero
1
MAC result is zero
MN
8
rwh
Negative Result
0
MAC result is positive
1
MAC result is negative
MAE
[7:0]
rwh
MAC Accumulator Extension
The most significant bits of the 40-bit accumulator,
completing registers MAH and MAL
User’s Manual
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V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
MAC Unit Status (MV, MN, MZ, MC, MSV, ME, MSL)
These condition flags indicate the MAC status resulting from the most recently
performed MAC operation. These flags are controlled by the majority of MAC instructions
according to specific rules. Those rules depend on the instruction managing the MAC or
data movement operation.
After execution of an instruction which explicitly updates register MSW, the condition
flags may no longer represent an actual MAC status. An explicit write operation to
register MSW supersedes the condition flag values implicitly generated by the MAC unit.
An explicit read access returns the value of register MSW after execution of the
immediately preceding instruction. Register MSW can be accessed via any instruction
capable of accessing an SFR.
Note: After reset, all MAC status bits are cleared.
MN-Flag: For the majority of the MAC operations, the MN-flag is set to 1 if the most
significant bit of the result contains a 1; otherwise, it is cleared. In the case of integer
operations, the MN-flag can be interpreted as the sign bit of the result (negative: MN = 1,
positive: MN = 0). Negative numbers are always represented as the 2’s complement of
the corresponding positive number. The range of signed numbers extends from
80’0000’0000H to 7F’FFFF’FFFFH.
MZ-Flag: The MZ-flag is normally set to 1 if the result of a MAC operation equals zero;
otherwise, it is cleared.
MC-Flag: After a MAC addition, the MC-flag indicates that a “Carry” from the most
significant bit of the accumulator extension MAE has been generated. After a MAC
subtraction or a MAC comparison, the MC-flag indicates a “Borrow” representing the
logical negation of a “Carry” for the addition. This means that the MC-flag is set to 1 if no
“Carry” from the most significant bit of the accumulator has been generated during a
subtraction. Subtraction is performed by the MAC Unit as a 2’s complement addition and
the MC-flag is cleared when this complement addition caused a “Carry”.
For left-shift MAC operations, the MC-flag represents the value of the bit shifted out last.
Right-shift MAC operations always clear the MC-flag. The arithmetic right-shift MAC
operation can set the MC-flag if the enabled round operation generates a “Carry” from
the most significant bit of the accumulator extension MAE.
MSV-Flag: The addition, subtraction, 2’s complement, and round operations always set
the MSV-flag to 1 if the MAC result exceeds the maximum range of 40-bit signed
numbers. If the MSV-flag indicates an arithmetic overflow, the MAC result of an
operation is not valid.
The MSV-flag is a ‘Sticky Bit’. Once set, other MAC operations cannot affect the status
of the MSV-flag. Only a direct write operation can clear the MSV-flag.
ME-Flag: The ME-flag is set if the accumulator extension MAE contains significant bits,
that means if the nine highest accumulator bits are not all equal.
User’s Manual
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Central Processing Unit (CPU)
MSL-Flag: The MSL-flag is set if an automatic saturation of the accumulator has
happened. The automatic saturation is enabled if bit MS in register MCW is set. The
MSL-Flag can be also set by instructions which limit the contents of the accumulator. If
the accumulator has been limited, the MSL-Flag is set.
The MSL-Flag is a ‘Sticky Bit’. Once set, it cannot be affected by the other MAC
operations. Only a direct write operation can clear the MSL-flag.
MV-Flag: The addition, subtraction, and accumulation operations set the MV-flag to 1 if
the result exceeds the maximum range of signed numbers (80’0000’0000H to
7F’FFFF’FFFFH); otherwise, the MV-flag is cleared. Note that if the MV-flag indicates an
arithmetic overflow, the result of the integer addition, integer subtraction, or
accumulation is not valid.
4.9.11
The Repeat Counter MRW
The Repeat Counter MRW controls the number of repetitions a loop must be executed.
The register must be pre-loaded before it can be used with -USRx CoXXX operations.
MAC operations are able to decrement this counter. When a -USRx CoXXX instruction
is executed, MRW is checked for zero before being decremented. If MRW equals zero,
bit USRx is set and MRW is not further decremented. Register MRW can be accessed
via any instruction capable of accessing a SFR.
MRW
MAC Repeat Word
15
14
13
12
SFR (FFDAH/EDH)
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
REPEAT_COUNT
rwh
Field
Bits
Type
Description
REPEAT_
COUNT
[15:0]
rwh
16-bit loop counter
All CoXXX instructions have a 3-bit wide repeat control field ‘rrr’ (bit positions [31:29]) in
the operand field to control the MRW repeat counter. Table 4-26 lists the possible
encodings.
User’s Manual
CPUSV2_X, V2.2
4-72
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 4-26
Central Processing Unit (CPU)
Encoding of MAC Repeat Word Control
Code in ‘rrr’
Effect on Repeat Counter
000B
regular CoXXX instruction
001B
RESERVED
010B
‘-USR0 CoXXX’ instruction,
decrements repeat counter and sets bit USR0 if MRW is zero
011B
‘-USR1 CoXXX’ instruction,
decrements repeat counter and sets bit USR1 if MRW is zero
1XXB
RESERVED
Note: Bit USR0 has been a general purpose flag also in previous architectures. To
prevent collisions due to using this flag by programmer or compiler, use
‘-USR0 C0XXX’ instructions very carefully.
The following example shows a loop which is executed 20 times. Every time the
CoMACM instruction is executed, the MRW counter is decremented.
MOV
loop01:
-USR1
MRW, #19
;Pre-load loop counter
CoMACM [IDX0+], [R0+]
;Calculate and decrement MSW
ADD
R2,#0002H
JMPA
cc_nusr1, loop01 ;Repeat loop until USR1 is set
Note: Because correctly predicted JMPA is executed in 0-cycle, it offers the functionality
of a repeat instruction.
User’s Manual
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4-73
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
4.10
Central Processing Unit (CPU)
Constant Registers
All bits of these bit-addressable registers are fixed to 0 or 1 by hardware. These registers
can be read only. Register ZEROS/ONES can be used as a register-addressable
constant of all zeros or all ones, for example for bit manipulation or mask generation. The
constant registers can be accessed via any instruction capable of addressing an SFR.
ZEROS
Zeros Register
SFR (FF1CH/8EH)
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Field
Bits
Type Description
0
[15:0]
r
Constant Zero Bit
ONES
Ones Register
SFR (FF1EH/8FH)
Reset Value: FFFFH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Field
Bits
Type Description
1
[15:0]
r
User’s Manual
CPUSV2_X, V2.2
Constant One Bit
4-74
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
5
Interrupt and Trap Functions
Interrupt and Trap Functions
The architecture of the XC2000 supports several mechanisms for fast and flexible
response to service requests from various sources internal or external to the
microcontroller. Different kinds of exceptions are handled in a similar way:
•
•
•
Interrupts generated by the Interrupt Controller (ITC)
DMA transfers issued by the Peripheral Event Controller (PEC)
Traps caused by the TRAP instruction or issued by faults or specific system states
Normal Interrupt Processing
The CPU temporarily suspends current program execution and branches to an interrupt
service routine to service an interrupt requesting device. The current program status (IP,
PSW, also CSP in segmentation mode) is saved on the internal system stack. A
prioritization scheme with 16 priority levels allows the user to specify the order in which
multiple interrupt requests are to be handled.
Interrupt Processing via the Peripheral Event Controller (PEC)
A faster alternative to normal software controlled interrupt processing is servicing an
interrupt requesting device with the XC2000’s integrated Peripheral Event Controller
(PEC). Triggered by an interrupt request, the PEC performs a single word or byte data
transfer between any two locations through one of eight programmable PEC Service
Channels. During a PEC transfer, normal program execution of the CPU is halted. No
internal program status information needs to be saved. The same prioritization scheme
is used for PEC service as for normal interrupt processing.
Trap Functions
Trap functions are activated in response to special conditions that occur during the
execution of instructions. A trap can also be caused externally via the External Service
Request pins, ESRx. Several hardware trap functions are provided to handle erroneous
conditions and exceptions arising during instruction execution. Hardware traps always
have highest priority and cause immediate system reaction. The software trap function
is invoked by the TRAP instruction that generates a software interrupt for a specified
interrupt vector. For all types of traps, the current program status is saved on the system
stack.
External Interrupt Processing
Although the XC2000 does not provide dedicated interrupt pins, it allows connection of
external interrupt sources and provides several mechanisms to react to external events
including standard inputs, non-maskable interrupts, and fast external interrupts. Except
for the non-maskable interrupt and the reset input, these interrupt functions are alternate
port functions.
User’s Manual
ICU_X2K, V2.2
5-1
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
5.1
Interrupt and Trap Functions
Interrupt System Structure
The XC2000 provides 96 separate interrupt nodes assignable to 16 priority levels, with
8 sub-levels (group priority) on each level. In order to support modular and consistent
software design techniques, most sources of an interrupt or PEC request are supplied
with a separate interrupt control register and an interrupt vector. The control register
contains the interrupt request flag, the interrupt enable bit, and the interrupt priority of the
associated source. Each source request is then activated by one specific event,
determined by the selected operating mode of the respective device. For efficient
resource usage, multi-source interrupt nodes are also incorporated. These nodes can be
activated by several source requests, such as by different kinds of errors in the serial
interfaces. However, specific status flags which identify the type of error are
implemented in the serial channels’ control registers. Additional sharing of interrupt
nodes is supported via interrupt subnode control registers.
The XC2000 provides a vectored interrupt system. In this system specific vector
locations in the memory space are reserved for the reset, trap, and interrupt service
functions. Whenever a request occurs, the CPU branches to the location that is
associated with the respective interrupt source. This allows direct identification of the
source which caused the request. The Class B hardware traps all share the same
interrupt vector. The status flags in the Trap Flag Register (TFR) can then be used to
determine which exception caused the trap. For the special software TRAP instruction,
the vector address is specified by the operand field of the instruction, which is a seven
bit trap number.
The reserved vector locations build a jump table in the low end of a segment (selected
by register VECSEG) in the XC2000’s address space. The jump table consists of the
appropriate jump instructions which transfer control to the interrupt or trap service
routines and which may be located anywhere within the address space. The entries of
the jump table are located at the lowest addresses in the selected code segment. Each
entry occupies 2, 4, 8, or 16 words (selected by bitfield VECSC in register CPUCON1),
providing room for at least one doubleword instruction. The respective vector location
results from multiplying the trap number by the selected step width (2(VECSC+2)).
All pending interrupt requests are arbitrated. The arbitration winner is indicated to the
CPU together with its priority level and action request. The CPU triggers the
corresponding action based on the required functionality (normal interrupt, PEC, jump
table cache, etc.) of the arbitration winner.
An action request will be accepted by the CPU if the requesting source has a higher
priority than the current CPU priority level and interrupts are globally enabled. If the
requesting source has a lower (or equal) interrupt level priority than the current CPU
task, it remains pending.
User’s Manual
ICU_X2K, V2.2
5-2
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
Interrupt and Peripheral Event Controller
PEC Pointer
Interrupt
Request
Lines
SRCP0
DSTP0
PECSEG0
SRCP1
DSTP1
PECSEG1
SRCP7
DSTP7
PECSEG7
irq0
irq1
C166S V2
CPU
PEC Request
irq2
irq3
Arbitration
irq n-3
irq n-1
irq n-2 1)
Arbitr.
Winner
Peripheral
Event
Controller
(PEC)
EOP
INT 2)
Request
Control
Request
Control
Interrupt
Handler
Interrupt
Request
Arbitration
Control
PEC
Control
Interrupt
Handler Control
(Interrupt Control
Registers)
(PEC Control
Registers)
Fast Bank
Switching
Interrupt
Request
Injection
Control
(CPU Action
Request)
Injection
Interface
OCE/OCDS
OCE Injection
Request & Control
BNKSEL0
irq0IC
PECC0
irq1IC
PECC1
BNKSEL3
Interrupt Jump
Table Cache
irq126IC
PECC7
EOPIC
PECISNC
FINT0CSP
FINT0ADDR
FINT1CSP
FINT1ADDR
1)
2)
Number of interrupt nodes n (up to 128)
End of PEC Interrupt (EOPINT) is connected to Interrupt request line irq n-1.
Therefore, only n-1 interrupt lines (irq n-2 ... 0) are available for peripheral request handling.
Figure 5-1
User’s Manual
ICU_X2K, V2.2
MCB04915
Block Diagram of the Interrupt and PEC Controller
5-3
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
5.2
Interrupt and Trap Functions
Interrupt Arbitration and Control
The XC2000’s interrupt arbitration system handles interrupt requests from up to
80 sources. Interrupt requests may be triggered either by the on-chip peripherals or by
external inputs.
Interrupt processing is controlled globally by register PSW through a general interrupt
enable bit (IEN) and the CPU priority field (ILVL). Additionally, the different interrupt
sources are controlled individually by their specific interrupt control registers (… IC).
Thus, the acceptance of requests by the CPU is determined by both the individual
interrupt control registers and by the PSW. PEC services are controlled by the respective
PECCx register and by the source and destination pointers which specify the task of the
respective PEC service channel.
An interrupt request sets the associated interrupt request flag xxIR. If the requesting
interrupt node is enabled by the associated interrupt enable bit xxIE arbitration starts with
the next clock cycle, or after completion of an arbitration cycle that is already in progress.
All interrupt requests pending at the beginning of a new arbitration cycle are considered,
independently from when they were actually requested.
Figure 5-2 shows the three-stage interrupt prioritization scheme:
Hardware
Traps
OCDS
break
request
OCDS
or
OCE
Interrupt
Request
Lines
Request
Lines
Arbitration
xxxx
(ILVL)+
x.xx
(XGLVL)
PEC/
Interrupt
Handler
xxxxx
(OCDS
service
request
priority
level)
0xxxx
(ILVL
extended
with
0 in MSB)
CPU
CPU
Action
Control
xxxxx
(request
priority
level)
0xxxx
(ILVL.PSW
extended
with
0 in MSB)
CPU
Arbitration
PSW
Stage 1:
Compared 4-Bit ILVL+
2/3-Bit XGLVL
priority levels of
interrupt sources
(64/128 priority levels)
Stage 2:
4-Bit IRQ/PEC priority level
comparated with
5-Bit OCDS priority level
Stage 3:
5-Bit request priority level
comparated with
4-Bit PSW priority level
MCD04913
Figure 5-2
User’s Manual
ICU_X2K, V2.2
Interrupt Arbitration
5-4
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
The interrupt prioritization is done in three stages:
•
•
•
Select one of the active interrupt requests
Compare the priority levels of the selected request and an OCDS service request
Compare the priority level of the final request with the CPU priority level
The First Arbitration Stage
compares the priority levels of the active interrupt request lines. The interrupt priority
level of each requestor is defined by bitfield ILVL in the respective xxIC register. The
extended group priority level XGLVL (combined from bitfields GPX and GLVL) defines
up to eight sub-priorities within one interrupt level. The group priority level distinguishes
interrupt requests assigned to the same priority level, so one winner can be determined.
Note: All interrupt request sources that are enabled and programmed to the same
interrupt priority level (ILVL) must have different group priority levels. Otherwise,
an incorrect interrupt vector will be generated.
The Second Arbitration Stage
compares the priority of the first stage winner with the priority of OCDS service requests.
OCDS service requests bypass the first stage of arbitration and go directly to the CPU
Action Control Unit. The CPU Action Control Unit compares the winner’s 4-bit priority
level (disregarding the group level) with the 5-bit OCDS service request priority. The 4-bit
ILVL of the interrupt request is extended to a 5-bit value with MSB = 0. This means that
any OCDS request with MSB = 1 will always win the second stage arbitration. However,
if there is a conflict between an OCDS request and an interrupt request, the interrupt
request wins.
The Third Arbitration Stage
compares the priority level of the second stage winner with the priority of the current CPU
task. An action request will be accepted by the CPU only if the priority level of the request
is higher than the current CPU priority level (bitfield ILVL in register PSW) and if interrupt
and PEC requests are globally enabled by the global interrupt enable flag IEN in register
PSW. To compare with the 5-bit priority level of the second stage winner, the 4-bit CPU
priority level is extended to a 5-bit value with MSB = 0. This means that any request with
MSB = 1 will always interrupt the current CPU task. If the requestor has a priority level
lower than or equal to the current CPU task, the request remains pending.
Note: Priority level 0000B is the default level of the CPU. Therefore, a request on
interrupt priority level 0000B will be arbitrated, but the CPU will never accept an
action request on this level. However, every individually enabled interrupt request
(including all denied interrupt requests and priority level 0000B requests) triggers
a CPU wake-up from idle state independent of the global interrupt enable bit IEN.
User’s Manual
ICU_X2K, V2.2
5-5
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
Both the OCDS break requests and the hardware traps bypass the arbitration scheme
and go directly to the core (see also Figure 5-2).
The arbitration process starts with an enabled interrupt request and stays active as long
as an interrupt request is pending. If no interrupt request is pending the arbitration is
stopped to save power.
TBD Register Address Space
Interrupt Control Registers
The control functions for each interrupt node are grouped in a dedicated interrupt control
register (xxIC, where “xx” stands for a mnemonic for the respective node). All interrupt
control registers are organized identically. The lower 9 bits of an interrupt control register
contain the complete interrupt control and status information of the associated source
required during one round of prioritization (arbitration cycle); the upper 7 bits are
reserved for future use. All interrupt control registers are bit-addressable and all bits can
be read or written via software. Therefore, each interrupt source can be programmed or
modified with just one instruction.
xxIC
Interrupt Control Register
(E)SFR (yyyyH/zzH)
15
14
13
12
11
10
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8
7
6
Reset Value: - 000H
5
GPX xxIR xxIE
rw
rwh
rw
4
3
2
1
0
ILVL
GLVL
rw
rw
Field
Bits
Type
Description
GPX
8
rw
Group Priority Extension
Completes bitfield GLVL to the 3-bit group level
xxIR1)
7
rwh
Interrupt Request Flag
0
No request pending
1
This source has raised an interrupt request
xxIE
6
rw
Interrupt Enable Control Bit
(individually enables/disables a specific source)
0
Interrupt request is disabled
1
Interrupt request is enabled
ILVL
[5:2]
rw
Interrupt Priority Level
FH Highest priority level
…
…
0H Lowest priority level
User’s Manual
ICU_X2K, V2.2
5-6
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
Field
Bits
Type
Description
GLVL
[1:0]
rw
Group Priority Level
(Is completed by bit GPX to the 3-bit group level)
3H Highest priority level
…
…
0H Lowest priority level
1) Bit xxIR supports bit-protection.
When accessing interrupt control registers through instructions which operate on word
data types, their upper 7 bits (15 … 9) will return zeros when read, and will discard
written data. It is recommended to always write zeros to these bit positions. The layout
of the interrupt control registers shown below applies to each xxIC register, where “xx”
represents the mnemonic for the respective source.
The Interrupt Request Flag is set by hardware whenever a service request from its
respective source occurs. It is cleared automatically upon entry into the interrupt service
routine or upon a PEC service. In the case of PEC service, the Interrupt Request flag
remains set if the COUNT field in register PECCx of the selected PEC channel
decrements to zero and bit EOPINT is cleared. This allows a normal CPU interrupt to
respond to a completed PEC block transfer on the same priority level.
Note: Modifying the Interrupt Request flag via software causes the same effects as if it
had been set or cleared by hardware.
The Interrupt Enable Control Bit determines whether the respective interrupt node
takes part in the arbitration process (enabled) or not (disabled). The associated request
flag will be set upon a source request in any case. The occurrence of an interrupt request
can so be polled via xxIR even while the node is disabled.
Note: In this case the interrupt request flag xxIR is not cleared automatically but must be
cleared via software.
Interrupt Priority Level and Group Level
The four bits of bitfield ILVL specify the priority level of a service request for the
arbitration of simultaneous requests. The priority increases with the numerical value of
ILVL: so, 0000B is the lowest and 1111B is the highest priority level.
When more than one interrupt request on a specific level becomes active at the same
time, the values in the respective bitfields GPX and GLVL are used for second level
arbitration to select one request to be serviced. Again, the group priority increases with
the numerical value of the concatenation of bitfields GPX and GLVL, so 000B is the
lowest and 111B is the highest group priority.
Note: All interrupt request sources enabled and programmed to the same priority level
must always be programmed to different group priorities. Otherwise, an incorrect
interrupt vector will be generated.
User’s Manual
ICU_X2K, V2.2
5-7
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
Upon entry into the interrupt service routine, the priority level of the source that won the
arbitration and whose priority level is higher than the current CPU level, is copied into
bitfield ILVL of register PSW after pushing the old PSW contents onto the stack.
The interrupt system of the XC2000 allows nesting of up to 15 interrupt service routines
of different priority levels (level 0 cannot be arbitrated).
Interrupt requests programmed to priority levels 15 … 8 (i.e., ILVL = 1XXXB) can be
serviced by the PEC if the associated PEC channel is properly assigned and enabled
(please refer to Section 5.4). Interrupt requests programmed to priority levels 7 through
1 will always be serviced by normal interrupt processing.
Note: Priority level 0000B is the default level of the CPU. Therefore, a request on level 0
will never be serviced because it can never interrupt the CPU. However, an
individually enabled interrupt request (independent of bit IEN) on level 0000B will
terminate the XC2000’s Idle mode and reactivate the CPU.
General Interrupt Control Functions in Register PSW
The acceptance of an interrupt request depends on the current CPU priority level (bitfield
ILVL in register PSW) and the global interrupt enable control bit IEN in register PSW (see
Section 4.8).
CPU Priority ILVL defines the current level for the operation of the CPU. This bitfield
reflects the priority level of the routine currently executed. Upon entry into an interrupt
service routine, this bitfield is updated with the priority level of the request being serviced.
The PSW is saved on the system stack before the request is serviced. The CPU level
determines the minimum interrupt priority level which will be serviced. Any request on
the same or a lower level will not be acknowledged. The current CPU priority level may
be adjusted via software to control which interrupt request sources will be
acknowledged. PEC transfers do not really interrupt the CPU, but rather “steal” a single
cycle, so PEC services do not influence the ILVL field in the PSW.
Hardware traps switch the CPU level to maximum priority (i.e. 15) so no interrupt or PEC
requests will be acknowledged while an exception trap service routine is executed.
Note: The TRAP instruction does not change the CPU level, so software invoked trap
service routines may be interrupted by higher requests.
Interrupt Enable bit IEN globally enables or disables PEC operation and the
acceptance of interrupts by the CPU. When IEN is cleared, no new interrupt requests are
accepted by the CPU (see also Section 4.3.4). When IEN is set to 1, all interrupt
sources, which have been individually enabled by the interrupt enable bits in their
associated control registers, are globally enabled. Traps are non-maskable and are,
therefore, not affected by the IEN bit.
Note: To generate requests, interrupt sources must be also enabled by the interrupt
enable bits in their associated control register.
User’s Manual
ICU_X2K, V2.2
5-8
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
Register Bank Select bitfield BANK defines the currently used register bank for the
CPU operation. When the CPU enters an interrupt service routine, this bitfield is updated
to select the register bank associated with the serviced request:
•
•
•
•
Requests on priority levels 15 … 12 use the register bank pre-selected via the
respective bitfield GPRSELx in the corresponding BNKSEL register
Requests on priority levels 11 … 1 always use the global register bank,
i.e. BANK = 00B
Hardware traps always use the global register bank, i.e. BANK = 00B
The TRAP instruction does not change the current register bank
User’s Manual
ICU_X2K, V2.2
5-9
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
5.3
Interrupt and Trap Functions
Interrupt Vector Table
The XC2000 provides a vectored interrupt system. This system reserves a set of specific
memory locations, which are accessed automatically upon the respective trigger event.
Entries for the following events are provided:
•
•
•
Reset (hardware, software, watchdog)
Traps (hardware-generated by fault conditions or via TRAP instruction)
Interrupt service requests
Whenever a request is accepted, the CPU branches to the location associated with the
respective trigger source. This vector position directly identifies the source causing the
request, with two exceptions:
•
•
Class B hardware traps all share the same interrupt vector. The status flags in the
Trap Flag Register (TFR) are used to determine which exception caused the trap. For
details, see Section 5.11.
An interrupt node may be shared by several interrupt requests, e.g. within a module.
Additional flags identify the requesting source, so the software can handle each
request individually. For details, see Section 5.7.
The reserved vector locations build a vector table located in the address space of the
XC2000. The vector table usually contains the appropriate jump instructions that transfer
control to the interrupt or trap service routines. These routines may be located anywhere
within the address space. The location and organization of the vector table is
programmable.
The Vector Segment register VECSEG defines the segment of the Vector Table (can be
located in all segments, except for reserved areas).
Bitfield VECSC in register CPUCON1 defines the space between two adjacent vectors
(can be 2, 4, 8, or 16 words). For a summary of register CPUCON1, please refer to
Section 4.4.
Each vector location has an offset address to the segment base address of the vector
table (given by VECSEG). The offset can be easily calculated by multiplying the vector
number with the vector space programmed in bitfield VECSC.
Table 5-2 lists all sources capable of requesting interrupt or PEC service in the XC2000,
the associated interrupt vector locations, the associated vector numbers, and the
associated interrupt control registers.
Note: All interrupt nodes which are currently not used by their associated modules or are
not connected to a module in the actual derivative may be used to generate
software controlled interrupt requests by setting the respective IR flag.
User’s Manual
ICU_X2K, V2.2
5-10
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
VECSEG
Vector Segment Pointer
SFR (FF12H/89H)
7
6
Reset Value: Table 5-1
15
14
13
12
11
10
9
8
5
4
3
-
-
-
-
-
-
-
-
vecseg
-
-
-
-
-
-
-
-
rwh
Field
Bits
Type
Description
vecseg
[7:0]
rwh
Segment number of the Vector Table
2
1
0
The reset value of register VECSEG, that means the initial location of the vector table,
depends on the reset configuration. Table 5-1 lists the possible locations. This is
required because the vector table also provides the reset vector.
Table 5-1
Reset Values for Register VECSEG
Initial Value
Reset Configuration
0000H
Standard start from external memory
00C0H
Standard start from Internal Program Memory
00E0H
Execute bootstrap loader code
User’s Manual
ICU_X2K, V2.2
5-11
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 5-2
Interrupt and Trap Functions
XC2000 Interrupt Nodes
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
CAPCOM Register 16, or
ERU Request 0
CC2_CC16IC
xx’0040H
10H / 16D
CAPCOM Register 17, or
ERU Request 1
CC2_CC17IC
xx’0044H
11H / 17D
CAPCOM Register 18, or
ERU Request 2
CC2_CC18IC
xx’0048H
12H / 18D
CAPCOM Register 19, or
ERU Request 3
CC2_CC19IC
xx’004CH
13H / 19D
CAPCOM Register 20, or
USIC0 Request 6
CC2_CC20IC
xx’0050H
14H / 20D
CAPCOM Register 21, or
USIC0 Request 7
CC2_CC21IC
xx’0054H
15H / 21D
CAPCOM Register 22, or
USIC1 Request 6
CC2_CC22IC
xx’0058H
16H / 22D
CAPCOM Register 23, or
USIC1 Request 7
CC2_CC23IC
xx’005CH
17H / 23D
CAPCOM Register 24, or
ERU Request 0
CC2_CC24IC
xx’0060H
18H / 24D
CAPCOM Register 25, or
ERU Request 1
CC2_CC25IC
xx’0064H
19H / 25D
CAPCOM Register 26, or
ERU Request 2
CC2_CC26IC
xx’0068H
1AH / 26D
CAPCOM Register 27, or
ERU Request 3
CC2_CC27IC
xx’006CH
1BH / 27D
CAPCOM Register 28, or
USIC2 Request 6
CC2_CC28IC
xx’0070H
1CH / 28D
CAPCOM Register 29, or
USIC2 Request 7
CC2_CC29IC
xx’0074H
1DH / 29D
CAPCOM Register 30
CC2_CC30IC
xx’0078H
1EH / 30D
CAPCOM Register 31
CC2_CC31IC
xx’007CH
1FH / 31D
GPT1 Timer 2
GPT12E_T2IC
xx’0080H
20H / 32D
GPT1 Timer 3
GPT12E_T3IC
xx’0084H
21H / 33D
GPT1 Timer 4
GPT12E_T4IC
xx’0088H
22H / 34D
User’s Manual
ICU_X2K, V2.2
5-12
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 5-2
Interrupt and Trap Functions
XC2000 Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
GPT2 Timer 5
GPT12E_T5IC
xx’008CH
23H / 35D
GPT2 Timer 6
GPT12E_T6IC
xx’0090H
24H / 36D
GPT2 CAPREL Register
GPT12E_CRIC
xx’0094H
25H / 37D
CAPCOM Timer 7
CC2_T7IC
xx’0098H
26H / 38D
CAPCOM Timer 8
CC2_T8IC
xx’009CH
27H / 39D
A/D Converter Request 0
ADC_0IC
xx’00A0H
28H / 40D
A/D Converter Request 1
ADC_1IC
xx’00A4H
29H / 41D
A/D Converter Request 2
ADC_2IC
xx’00A8H
2AH / 42D
A/D Converter Request 3
ADC_3IC
xx’00ACH
2BH / 43D
A/D Converter Request 4
ADC_4IC
xx’00B0H
2CH / 44D
A/D Converter Request 5
ADC_5IC
xx’00B4H
2DH / 45D
A/D Converter Request 6
ADC_6IC
xx’00B8H
2EH / 46D
A/D Converter Request 7
ADC_7IC
xx’00BCH
2FH / 47D
CCU60 Request 0
CCU60_0IC
xx’00C0H
30H / 48D
CCU60 Request 1
CCU60_1IC
xx’00C4H
31H / 49D
CCU60 Request 2
CCU60_2IC
xx’00C8H
32H / 50D
CCU60 Request 3
CCU60_3IC
xx’00CCH
33H / 51D
CCU61 Request 0
CCU61_0IC
xx’00D0H
34H / 52D
CCU61 Request 1
CCU61_1IC
xx’00D4H
35H / 53D
CCU61 Request 2
CCU61_2IC
xx’00D8H
36H / 54D
CCU61 Request 3
CCU61_3IC
xx’00DCH
37H / 55D
CCU62 Request 0
CCU62_0IC
xx’00E0H
38H / 56D
CCU62 Request 1
CCU62_1IC
xx’00E4H
39H / 57D
CCU62 Request 2
CCU62_2IC
xx’00E8H
3AH / 58D
CCU62 Request 3
CCU62_3IC
xx’00ECH
3BH / 59D
CCU63 Request 0
CCU63_0IC
xx’00F0H
3CH / 60D
CCU63 Request 1
CCU63_1IC
xx’00F4H
3DH / 61D
CCU63 Request 2
CCU63_2IC
xx’00F8H
3EH / 62D
CCU63 Request 3
CCU63_3IC
xx’00FCH
3FH / 63D
CAN Request 0
CAN_0IC
xx’0100H
40H / 64D
User’s Manual
ICU_X2K, V2.2
5-13
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 5-2
Interrupt and Trap Functions
XC2000 Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
CAN Request 1
CAN_1IC
xx’0104H
41H / 65D
CAN Request 2
CAN_2IC
xx’0108H
42H / 66D
CAN Request 3
CAN_3IC
xx’010CH
43H / 67D
CAN Request 4
CAN_4IC
xx’0110H
44H / 68D
CAN Request 5
CAN_5IC
xx’0114H
45H / 69D
CAN Request 6
CAN_6IC
xx’0118H
46H / 70D
CAN Request 7
CAN_7IC
xx’011CH
47H / 71D
CAN Request 8
CAN_8IC
xx’0120H
48H / 72D
CAN Request 9
CAN_9IC
xx’0124H
49H / 73D
CAN Request 10
CAN_10IC
xx’0128H
4AH / 74D
CAN Request 11
CAN_11IC
xx’012CH
4BH / 75D
CAN Request 12
CAN_12IC
xx’0130H
4CH / 76D
CAN Request 13
CAN_13IC
xx’0134H
4DH / 77D
CAN Request 14
CAN_14IC
xx’0138H
4EH / 78D
CAN Request 15
CAN_15IC
xx’013CH
4FH / 79D
USIC0 Request 0
U0C0_0IC
xx’0140H
50H / 80D
USIC0 Request 1
U0C0_1IC
xx’0144H
51H / 81D
USIC0 Request 2
U0C0_2IC
xx’0148H
52H / 82D
USIC0 Request 3
U0C1_0IC
xx’014CH
53H / 83D
USIC0 Request 4
U0C1_1IC
xx’0150H
54H / 84D
USIC0 Request 5
U0C1_2IC
xx’0154H
55H / 85D
USIC1 Request 0
U1C0_0IC
xx’0158H
56H / 86D
USIC1 Request 1
U1C0_1IC
xx’015CH
57H / 87D
USIC1 Request 2
U1C0_2IC
xx’0160H
58H / 88D
USIC1 Request 3
U1C1_0IC
xx’0164H
59H / 89D
USIC1 Request 4
U1C1_1IC
xx’0168H
5AH / 90D
USIC1 Request 5
U1C1_2IC
xx’016CH
5BH / 91D
USIC2 Request 0
U2C0_0IC
xx’0170H
5CH / 92D
USIC2 Request 1
U2C0_1IC
xx’0174H
5DH / 93D
USIC2 Request 2
U2C0_2IC
xx’0178H
5EH / 94D
User’s Manual
ICU_X2K, V2.2
5-14
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 5-2
Interrupt and Trap Functions
XC2000 Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
USIC2 Request 3
U2C1_0IC
xx’017CH
5FH / 95D
USIC2 Request 4
U2C1_1IC
xx’0180H
60H / 96D
USIC2 Request 5
U2C1_2IC
xx’0184H
61H / 97D
Unassigned node
–
xx’0188H
62H / 98D
Unassigned node
–
xx’018CH
63H / 99D
Unassigned node
–
xx’0190H
64H / 100D
Unassigned node
–
xx’0194H
65H / 101D
Unassigned node
–
xx’0198H
66H / 102D
Unassigned node
–
xx’019CH
67H / 103D
Unassigned node
–
xx’01A0H
68H / 104D
Unassigned node
–
xx’01A4H
69H / 105D
Unassigned node
–
xx’01A8H
6AH / 106D
SCU Request 1
SCU_1IC
xx’01ACH
6BH / 107D
SCU Request 0
SCU_0IC
xx’01B0H
6CH / 108D
Program Flash Modules
PFM_IC
xx’01B4H
6DH / 109D
RTC
RTC_IC
xx’01B8H
6EH / 110D
End of PEC Subchannel
EOPIC
xx’01BCH
6FH / 111D
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
User’s Manual
ICU_X2K, V2.2
5-15
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
Table 5-3 lists the vector locations for hardware traps and the corresponding status flags
in register TFR. It also lists the priorities of trap service for those cases in which more
than one trap condition might be detected within the same instruction. After any reset
(hardware reset, software reset instruction SRST, or reset by watchdog timer overflow)
program execution starts at the reset vector at location xx’0000H. Reset conditions have
priority over every other system activity and, therefore, have the highest priority (trap
priority III).
Software traps may be initiated to any defined vector location. A service routine entered
via a software TRAP instruction is always executed on the current CPU priority level
which is indicated in bitfield ILVL in register PSW. This means that routines entered via
the software TRAP instruction can be interrupted by all hardware traps or higher level
interrupt requests.
Table 5-3
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Trap
Trap
1)
Location
Number Priority
Reset Functions
–
RESET
xx’0000H
00H
III
Class A Hardware Traps:
• System Request 0
• Stack Overflow
• Stack Underflow
• Software Break
SR0
STKOF
STKUF
SOFTBRK
SR0TRAP
STOTRAP
STUTRAP
SBRKTRAP
xx’0008H
xx’0010H
xx’0018H
xx’0020H
02H
04H
06H
08H
II
II
II
II
SR1
UNDOPC
ACER
PRTFLT
BTRAP
BTRAP
BTRAP
BTRAP
xx’0028H
xx’0028H
xx’0028H
xx’0028H
0AH
0AH
0AH
0AH
I
I
I
I
ILLOPA
BTRAP
xx’0028H
0AH
I
Reserved
–
–
[2CH - 3CH] [0BH 0FH]
–
Software Traps:
• TRAP Instruction
–
–
Any
Any
[xx’0000H - [00H xx’01FCH] 7FH]
in steps of
4H
Current
CPU
Priority
Class B Hardware Traps:
• System Request 1
• Undefined Opcode
• Memory Access Error
• Protected Instruction
Fault
• Illegal Word Operand
Access
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
User’s Manual
ICU_X2K, V2.2
5-16
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
Interrupt Jump Table Cache
Servicing an interrupt request via the vector table usually incurs two subsequent
branches: an implicit branch to the vector location and an explicit branch to the actual
service routine. The interrupt servicing time can be reduced by the Interrupt Jump Table
Cache (ITC, also called “fast interrupt”). This feature eliminates the second explicit
branch by directly providing the CPU with the service routine’s location.
The ITC provides two 24-bit pointers, so the CPU can directly branch to the respective
service routines. These fast interrupts can be selected for two interrupt sources on
priority levels 15 … 12.
The two pointers are each stored in a pair of interrupt jump table cache registers
(FINTxADDR, FINTxCSP), which store a pointer’s segment and offset along with the
priority level it shall be assigned to (select the same priority that is programmed for the
respective interrupt node).
FINT0ADDR
Fast Interrupt Address Reg. 0
FINT1ADDR
Fast Interrupt Address Reg. 1
15
14
13
12
11
10
XSFR (EC02H/--)
Reset Value: 0000H
XSFR (EC06H/--)
Reset Value: 0000H
9
8
7
6
5
4
3
2
1
0
ADDR
0
rw
r
Field
Bits
Type
Description
ADDR
[15:1]
rw
Address of Interrupt Service Routine
Specifies address bits 15 … 1 of the 24-bit pointer to
the interrupt service routine. This word offset is
concatenated with FINTxCSP.SEG.
FINT0CSP
Fast Interrupt Control Reg. 0
FINT1CSP
Fast Interrupt Control Reg. 1
10
Reset Value: 0000H
XSFR (EC04H/--)
Reset Value: 0000H
15
14
13
12
EN
-
-
GPX
ILVL
GLVL
SEG
rw
-
-
rw
rw
rw
rw
User’s Manual
ICU_X2K, V2.2
11
XSFR (EC00H/--)
9
8
7
5-17
6
5
4
3
2
1
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
Field
Bits
Type
Description
EN
15
rw
Fast Interrupt Enable
0
The interrupt jump table cache is not used
1
The interrupt jump table cache is enabled,
the vector table entry for the specified request
is bypassed, the cache pointer is used
GPX
12
rw
Group Priority Extension
Used together with bitfield GLVL
ILVL
[11:10] rw
Interrupt Priority Level
This selects the interrupt priority (15 … 12) of the
request this pointer shall be assigned to
00
Interrupt priority level 12 (1100B)
01
Interrupt priority level 13 (1101B)
10
Interrupt priority level 14 (1110B)
11
Interrupt priority level 15 (1111B)
GLVL
[9:8]
rw
Group Priority Level
Together with bit GPX this selects the group priority
of the request this pointer shall be assigned to
SEG
[7:0]
rw
Segment Number of Interrupt Service Routine
Specifies address bits 23 … 16 of the 24-bit pointer
to the interrupt service routine, is concatenated with
FINTxADDR.
User’s Manual
ICU_X2K, V2.2
5-18
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
5.4
Interrupt and Trap Functions
Operation of the Peripheral Event Controller Channels
The XC2000’s Peripheral Event Controller (PEC) provides 8 PEC service channels
which move a single byte or word between any two locations. A PEC transfer can be
triggered by an interrupt service request and is the fastest possible interrupt response.
In many cases a PEC transfer is sufficient to service the respective peripheral request
(for example, serial channels, etc.).
PEC transfers do not change the current context, but rather “steal” cycles from the CPU,
so the current program status and context needs not to be saved and restored as with
standard interrupts.
The PEC channels are controlled by a dedicated set of registers which are assigned to
dedicated PEC resources:
•
•
•
•
A 24-bit source pointer for each channel
A 24-bit destination pointer for each channel
A Channel Counter/Control register (PECCx) for each channel, selecting the
operating mode for the respective channel
Two interrupt control registers to control the operation of block transfers
5.4.1
The PECC Registers
The PECC registers control the action performed by the respective PEC channel.
Transfer Size (bit BWT) controls whether a byte or a word is moved during a PEC
service cycle. This selection controls the transferred data size and the increment step for
the pointer(s) to be modified.
Pointer Modification (bitfield INC) controls, which of the PEC pointers is incremented
after the PEC transfer. If the pointers are not modified (INC = 00B), the respective
channel will always move data from the same source to the same destination.
Transfer Control (bitfield COUNT) controls if the respective PEC channel remains
active after the transfer or not. Bitfield COUNT also generally enables a PEC channel
(COUNT > 00H).
The PECC registers also select the assignment of PEC channels to interrupt priority
levels (bitfield PLEV) and the interrupt behavior after PEC transfer completion (bit
EOPINT).
Note: All interrupt request sources that are enabled and programmed for PEC service
should use different channels. Otherwise, only one transfer will be performed for
all simultaneous requests. When COUNT is decremented to 00H, and the CPU is
to be interrupted, an incorrect interrupt vector will be generated.
PEC transfers are executed only if their priority level is higher than the CPU level.
User’s Manual
ICU_X2K, V2.2
5-19
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
PECCx
PEC Control Reg.
13
12
SFR (FECyH/6zH, Table 5-4)
11
10
9
8
7
6
Reset Value: 0000H
15
14
5
4
3
-
EOP
INT
PLEV
CL
INC
BWT
COUNT
-
rw
rw
rw
rw
rw
rwh
2
1
0
Field
Bits
Type
Description
EOPINT
14
rw
End of PEC Interrupt Selection
0
End of PEC interrupt on the same (PEC) level
1
End of PEC interrupt via separate node EOPIC
PLEV
[13:12] rw
PEC Level Selection
This bitfield controls the PEC channel assignment to
an arbitration priority level (see section below)
CL
11
rw
Channel Link Control
0
PEC channels work independently
1
Pairs of PEC channels are linked together1)
INC
[10:9]
rw
Increment Control (Pointer Modification)2)
00
Pointers are not modified
01
Increment DSTPx by 1 or 2 (BWT = 1 or 0)
10
Increment SRCPx by 1 or 2 (BWT = 1 or 0)
11
Increment both DSTPx and SRCPx by 1 or 2
BWT
8
rw
Byte/Word Transfer Selection
0
Transfer a word
1
Transfer a byte
COUNT
[7:0]
rwh
PEC Transfer Count
Counts PEC transfers and influences the channel’s
action (see Section 5.4.3)
1) For a functional description see “Channel Link Mode for Data Chaining”.
2) Pointers are incremented/decremented only within the current segment.
Table 5-4
PEC Control Register Addresses
Register
Address
PECC0
Register
Address
FEC0H / 60H SFR
PECC4
FEC8H / 64H SFR
PECC1
FEC2H / 61H SFR
PECC5
FECAH / 65H SFR
PECC2
FEC4H / 62H SFR
PECC6
FECCH / 66H SFR
PECC3
FEC6H / 63H SFR
PECC7
FECEH / 67H SFR
User’s Manual
ICU_X2K, V2.2
Reg. Space
5-20
Reg. Space
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
The PEC channel number is derived from the respective ILVL (LSB) and GLVL, where
the priority band (ILVL) is selected by the channel’s bitfield PLEV (see Table 5-5). So,
programming a source to priority level 15 (ILVL = 1111B) selects the PEC channel group
7 … 4 with PLEV = 00B; programming a source to priority level 14 (ILVL = 1110B) selects
the PEC channel group 3 … 0 with PLEV = 00B; programming a source to priority level
10 (ILVL = 1010B) selects the PEC channel group 3 … 0 with PLEV = 10B. The actual
PEC channel number is then determined by the group priority (levels 3 … 0, i.e.
GPX = 0).
Simultaneous requests for PEC channels are prioritized according to the PEC channel
number, where channel 0 has lowest and channel 7 has highest priority.
Note: All sources requesting PEC service must be programmed to different PEC
channels. Otherwise, an incorrect PEC channel may be activated.
Table 5-5
PEC Channel Assignment
Selected
PEC Channel
Group
Level
7
3
6
2
5
1
4
0
3
3
2
2
1
1
0
0
Used Interrupt Priorities Depending on Bitfield PLEV
PLEV = 00B
PLEV = 01B
PLEV = 10B
PLEV = 11B
15
13
11
9
14
12
10
8
Table 5-6 shows in a few examples which action is executed with a given programming
of an interrupt control register and a PEC channel.
User’s Manual
ICU_X2K, V2.2
5-21
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 5-6
Interrupt and Trap Functions
Interrupt Priority Examples
Priority Level
Type of Service
Interr. Group COUNT = 00H,
Level Level PLEV = XXB
COUNT ≠ 00H,
PLEV = 00B
COUNT ≠ 00H,
PLEV = 01B
1111 111
CPU interrupt,
level 15, group prio 7
CPU interrupt,
level 15, group prio 7
CPU interrupt,
level 15, group prio 7
1111 011
CPU interrupt,
level 15, group prio 3
PEC service,
channel 7
CPU interrupt,
level 15, group prio 3
1111 010
CPU interrupt,
level 15, group prio 2
PEC service,
channel 6
CPU interrupt,
level 15, group prio 2
1110 010
CPU interrupt,
level 14, group prio 2
PEC service,
channel 2
CPU interrupt,
level 14, group prio 2
1101 110
CPU interrupt,
level 13, group prio 6
CPU interrupt,
level 13, group prio 6
CPU interrupt,
level 13, group prio 6
1101 010
CPU interrupt,
level 13, group prio 2
CPU interrupt,
level 13, group prio 2
PEC service,
channel 6
0001 011
CPU interrupt,
level 1, group prio 3
CPU interrupt,
level 1, group prio 3
CPU interrupt,
level 1, group prio 3
0001 000
CPU interrupt,
level 1, group prio 0
CPU interrupt,
level 1, group prio 0
CPU interrupt,
level 1, group prio 0
0000 XXX
No service!
No service!
No service!
Note: PEC service is only achieved when bit GPX = 0 and COUNT ≠ 0.
Requests on levels 7 … 1 cannot initiate PEC transfers. They are always serviced
by an interrupt service routine: no PECC register is associated and no COUNT
field is checked.
User’s Manual
ICU_X2K, V2.2
5-22
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
5.4.2
Interrupt and Trap Functions
The PEC Source and Destination Pointers
The PEC channels’ source and destination pointers specify the locations between which
the data is to be moved. Both 24-bit pointers are built by concatenating the 16-bit offset
register (SRCPx or DSTPx) with the respective 8-bit segment bitfield (SRCSEGx or
DSTSEGx, combined in register PECSEGx).
PECSEGx
SRCSEGx
15
DSTSEGx
8 7
SRCPx
0
DSTPx
SRCPx
15
DSTPx
0
15
Source Pointer
23
16 15
Segment Address
Destination Pointer
0
Segment Offset
0
23
16 15
Segment Address
0
Segment Offset
Data Transfer
MCD04916
x = 7 … 0, depending on PEC channel number
Figure 5-3
PEC Data Pointers
When a PEC pointer is automatically incremented after a transfer, only the offset part is
incremented (SRCPx and/or DSTPx), while the respective segment part is not modified
by hardware. Thus, a pointer may be incremented within the current segment, but may
not cross the segment boundary. When a PEC pointer reaches the maximum offset
(FFFEH for word transfers, FFFFH for byte transfers), it is not incremented further, but
keeps its maximum offset value. This protects memory in adjacent segments from being
overwritten unintentionally.
No explicit error event is generated by the system in case of a pointer saturation;
therefore, it is the user’s responsibility to prevent this condition.
Note: PEC data transfers do not use the data page pointers DPP3 … DPP0.
Unused PEC pointers may be used for general data storage.
User’s Manual
ICU_X2K, V2.2
5-23
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
SRCPx
PEC Source Pointer
15
14
13
12
XSFR (ECyyH/--, Table 5-7)
11
10
9
8
7
6
5
Reset Value: 0000H
4
3
2
1
0
srcpx
rwh
Field
Bits
Type
Description
srcpx
[15:0]
rwh
Source Pointer Offset of Channel x
Source address bits 15 … 0
DSTPx
PEC Destination Pointer
15
14
13
12
11
XSFR (ECyyH/--, Table 5-7)
10
9
8
7
6
5
Reset Value: 0000H
4
3
2
1
0
dstpx
rwh
Field
Bits
Type
Description
dstpx
[15:0]
rwh
Destination Pointer Offset of Channel x
Destination address bits 15 … 0
PECSEGx
PEC Segment Pointer
15
14
13
12
XSFR (ECyyH/--, Table 5-7)
11
10
9
8
7
6
5
Reset Value: 0000H
4
3
srcsegx
dstsegx
rw
rw
2
1
Field
Bits
Type
Description
srcsegx
[15:8]
rw
Source Pointer Segment of Channel x
Source address bits 23 … 16
dstsegx
[7:0]
rw
Destination Pointer Segment of Channel x
Destination address bits 23 … 16
User’s Manual
ICU_X2K, V2.2
5-24
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 5-7
Interrupt and Trap Functions
PEC Data Pointer Register Addresses
Channel #
0
1
2
3
4
5
6
7
PECSEGx
EC80H
EC82H
EC84H
EC86H
EC88H
EC8AH EC8CH EC8EH
SRCPx
EC40H
EC44H
EC48H
EC4CH EC50H
EC54H
EC58H
DSTPx
EC42H
EC46H
EC4AH EC4EH EC52H
EC56H
EC5AH EC5EH
EC5CH
Note: If word data transfer is selected for a specific PEC channel (BWT = 0), the
respective source and destination pointers must both contain a valid word address
which points to an even byte boundary. Otherwise, the Illegal Word Access trap
will be invoked when this channel is used.
5.4.3
PEC Transfer Control
The PEC Transfer Count Field COUNT controls the behavior of the respective PEC
channel. The contents of bitfield COUNT select the action to be taken at the time the
request is activated. COUNT may allow a specified number of PEC transfers, unlimited
transfers, or no PEC service at all. Table 5-8 summarizes, how the COUNT field, the
interrupt requests flag IR, and the PEC channel action depend on the previous contents
of COUNT.
Table 5-8
Influence of Bitfield COUNT
Previous
COUNT
Modified
COUNT
IR after
Service
Action of PEC Channel and Comments
FFH
FFH
0
Move a Byte/Word
Continuous transfer mode, i.e. COUNT is not
modified
FEH … 02H
FDH … 01H
0
Move a Byte/Word and decrement COUNT
01H
00H
1
EOPINT = 0 (channel-specific interrupt)
Move a Byte/Word and leave request flag set,
which triggers another request
0
EOPINT = 1 (separate end-of-PEC interrupt)
Move a Byte/Word and clear request flag, set
the respective PEC subnode request flag CxIR
instead1)
–
No PEC action!
Activate interrupt service routine rather than
PEC channel
00H
00H
1) Setting a subnode request flag also sets flag EOPIR if the subnode request is enabled (CxIE = 1).
User’s Manual
ICU_X2K, V2.2
5-25
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
The PEC transfer counter allows service of a specified number of requests by the
respective PEC channel, and then (when COUNT reaches 00H) activation of an interrupt
service routine, either associated with the PEC channel’s priority level or with the general
end-of-PEC interrupt. After each PEC transfer, the COUNT field is decremented (except
for COUNT = FFH) and the request flag is cleared to indicate that the request has been
serviced.
When COUNT contains the value 00H, the respective PEC channel remains idle and the
associated interrupt service routine is activated instead. This allows servicing requests
on all priority levels by standard interrupt service routines.
Continuous transfers are selected by the value FFH in bitfield COUNT. In this case,
COUNT is not modified and the respective PEC channel services any request until it is
disabled again.
When COUNT is decremented from 01H to 00H after a transfer, a standard interrupt is
requested which can then handle the end of the PEC block transfer (channel-specific
interrupt or common end-of-PEC interrupt, see Table 5-8).
User’s Manual
ICU_X2K, V2.2
5-26
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
5.4.4
Interrupt and Trap Functions
Channel Link Mode for Data Chaining
In channel link mode, every two PEC channels build a pair (channels 0+1, 2+3, 4+5,
6+7), where the two channels of a pair are activated in turn. Requests for the even
channel trigger the currently active PEC channel (or the end-of-block interrupt), while
requests for the odd channel only trigger its associated interrupt node. When the transfer
count of one channel expires, control is switched to the other channel, and back. This
mode supports data chaining where independent blocks of data can be transferred to the
same destination (or vice versa), e.g. to build communication frames from several
blocks, such as preamble, data, etc.
Channel link mode for a pair of channels is enabled if at least one of the channel link
control bits (bit CL in register PECCx) of the respective pair is set. A linked channel pair
is controlled by the priority-settings (level, group) for its even channel. After enabling
channel link mode the even channel is active.
Channel linking is executed if the active channel’s link control bit CL is 1 at the time its
transfer count decrements from 1 to 0 (count > 0 before) and the transfer count of the
other channel is non-zero. In this case the active channel issues an EOP interrupt
request and the respective other channel of the pair is automatically selected.
Note: Channel linking always begins with the even channel.
Channel linking is terminated if the active channel’s link control bit CL is 0 at the time
its transfer count decrements from 1 to 0, or if the transfer count of the respective linked
channel is zero. In this case an interrupt is triggered as selected by bit EOPINT (channelspecific or general EOP interrupt).
A data-chaining sequence using PEC channel linking is programmed by setting bit CL
together with a transfer count value (> 0). This is repeated, triggered by the channel link
interrupts, for the complete sequence. For the last transfer, the interrupt routine should
clear the respective bit CL, so, at the end of the complete transfer, either a standard or
an END of PEC interrupt can be selected by bit EOPINT of the last channel.
Note: To enable linking, initially both channels must receive a non-zero transfer count.
For the rest of the sequence only the channel with the expired transfer count
needs to be reconfigured.
User’s Manual
ICU_X2K, V2.2
5-27
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
5.4.5
Interrupt and Trap Functions
PEC Interrupt Control
When the selected number of PEC transfers has been executed, the respective PEC
channel is disabled and a standard interrupt service routine is activated instead. Each
PEC channel can either activate the associated channel-specific interrupt node, or
activate its associated PEC subnode request flag in register PECISNC, which then
activates the common node request flag in register EOPIC (see Figure 5-4).
PECISNC
PEC Intr. Sub-Node Ctrl. Reg.
15
14
13
12
11
10
SFR (FFD8H/ECH)
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE
rwh
rw
rwh
rw
rwh
rw
rwh
rw
rwh
rw
rwh
rw
rwh
rw
rwh
rw
Field
Bits
Type
Description
CxIR
x=7…0
[2x+1]
rwh
Interrupt Request Flag of PEC Channel x
0
No request from PEC channel x pending
1
PEC channel x has raised an end-of-PEC
interrupt request
Note: These request flags must be cleared by SW.
CxIE
x=7…0
[2x]
rw
Interrupt Enable Control Bit of PEC Channel x
(individually enables/disables a specific source)
0
End-of-PEC request of channel x disabled
1
End-of-PEC request of channel x enabled1)
1) It is recommended to clear an interrupt request flag (CxIR) before setting the respective enable flag (CxIE).
Otherwise, former requests still pending cannot trigger a new interrupt request.
EOPIC
End-of-PEC Intr. Ctrl. Reg.
ESFR (F19EH/CFH)
15
14
13
12
11
10
9
8
7
-
-
-
-
-
-
-
GPX
-
-
-
-
-
-
-
rw
6
EOP EOP
IR
IE
rwh
rw
Reset Value: 0000H
5
4
3
2
1
0
ILVL
GLVL
rw
rw
Note: Please refer to the general Interrupt Control Register description for an
explanation of the control fields.
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Preliminary
Interrupt and Trap Functions
PECISNC
C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE
15
&
&
&
&
&
1
&
&
&
0
Interrupt Request
Pulse Generator
EOPIC
0
0
15
0
0
0
0
0
GPX
EOP EOP
IR
IE
87
ILVL
GLVL
0
MCD04914
Figure 5-4
End of PEC Interrupt Sub Node
Note: The interrupt service routine must service and clear all currently active requests
before terminating. Requests occurring later will set EOPIR again and the service
routine will be re-entered.
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Preliminary
5.5
Interrupt and Trap Functions
Prioritization of Interrupt and PEC Service Requests
Interrupt and PEC service requests from all sources can be enabled so they are
arbitrated and serviced (if they win), or they may be disabled, so their requests are
disregarded and not serviced.
Enabling and disabling interrupt requests may be done via three mechanisms:
•
•
•
Control Bits
Priority Level
ATOMIC and EXTended Instructions
Control Bits allow switching of each individual source “ON” or “OFF” so that it may
generate a request or not. The control bits (xxIE) are located in the respective interrupt
control registers. All interrupt requests may be enabled or disabled generally via bit IEN
in register PSW. This control bit is the “main switch” which selects if requests from any
source are accepted or not.
For a specific request to be arbitrated, the respective source’s enable bit and the global
enable bit must both be set.
The Priority Level automatically selects a certain group of interrupt requests to be
acknowledged and ignores all other requests. The priority level of the source that won
the arbitration is compared against the CPU’s current level and the source is serviced
only if its level is higher than the current CPU level. Changing the CPU level to a specific
value via software blocks all requests on the same or a lower level. An interrupt source
assigned to level 0 will be disabled and will never be serviced.
The ATOMIC and EXTend instructions automatically disable all interrupt requests for
the duration of the following 1 … 4 instructions. This is useful for semaphore handling,
for example, and does not require to re-enable the interrupt system after the inseparable
instruction sequence.
Interrupt Class Management
An interrupt class covers a set of interrupt sources with the same importance, i.e. the
same priority from the system’s viewpoint. Interrupts of the same class must not interrupt
each other. The XC2000 supports this function with two features:
Classes with up to eight members can be established by using the same interrupt priority
(ILVL) and assigning a dedicated group level to each member. This functionality is builtin and handled automatically by the interrupt controller.
Classes with more than eight members can be established by using a number of
adjacent interrupt priorities (ILVL) and the respective group levels (eight per ILVL). Each
interrupt service routine within this class sets the CPU level to the highest interrupt
priority within the class. All requests from the same or any lower level are blocked now,
i.e. no request of this class will be accepted.
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Interrupt and Trap Functions
The example shown below establishes 3 interrupt classes which cover 2 or 3 interrupt
priorities, depending on the number of members in a class. A level 6 interrupt disables
all other sources in class 2 by changing the current CPU level to 8, which is the highest
priority (ILVL) in class 2. Class 1 requests or PEC requests are still serviced, in this case.
In this way, the interrupt sources (excluding PEC requests) are assigned to 3 classes of
priority rather than to 7 different levels, as the hardware support would do.
Table 5-9
ILVL
(Priority)
Software Controlled Interrupt Classes (Example)
Group Level
7
15
Interpretation
6 5 4 3 2 1 0
PEC service on up to 8 channels
14
13
12
11
X X X X X X X X Interrupt Class 1
9 sources on 2 levels
X
10
9
8
7
X X X X X X X X Interrupt Class 2
X X X X X X X X 17 sources on 3 levels
6
X
5
X X X X X X X X Interrupt Class 3
9 sources on 2 levels
X
4
3
2
1
0
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Preliminary
5.6
Interrupt and Trap Functions
Context Switching and Saving Status
Before an interrupt request that has been arbitrated is actually serviced, the status of the
current task is automatically saved on the system stack. The CPU status (PSW) is saved
together with the location at which execution of the interrupted task is to be resumed after
returning from the service routine. This return location is specified through the Instruction
Pointer (IP) and, in the case of a segmented memory model, the Code Segment Pointer
(CSP). Bit SGTDIS in register CPUCON1 controls how the return location is stored.
The system stack receives the PSW first, followed by the IP (unsegmented), or followed
by CSP and then IP (segmented mode). This optimizes the usage of the system stack if
segmentation is disabled.
The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request
to be serviced, so the CPU now executes on the new level.
The register bank select field (BANK in PSW) is changed to select the register bank
associated with the interrupt request. The association between interrupt requests and
register banks are partly pre-defined and can partly be programmed.
The interrupt request flag of the source being serviced is cleared. IP and CSP are loaded
with the vector associated with the requesting source, and the first instruction of the
service routine is fetched from the vector location which is expected to branch to the
actual service routine (except when the interrupt jump table cache is used). All other
CPU resources, such as data page pointers and the context pointer, are not affected.
When the interrupt service routine is exited (RETI is executed), the status information is
popped from the system stack in the reverse order, taking into account the value of bit
SGTDIS.
High
Addresses
Status of
Interrupted
Task
SP
---
SP
--
PSW
PSW
IP
CSP
--
IP
SP
Low
Addresses
a) System Stack before
Interrupt Entry
b) System Stack after
Interrupt Entry
(Unsegmented)
b) System Stack after
Interrupt Entry
(Segmented)
MCD02226
Figure 5-5
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Interrupt and Trap Functions
Context Switching
An interrupt service routine usually saves all the registers it uses on the stack and
restores them before returning. The more registers a routine uses, the more time is spent
saving and restoring. The XC2000 allows switching the complete bank of CPU registers
(GPRs) either automatically or with a single instruction, so the service routine executes
within its own separate context (see also Section 4.5.2).
There are two ways to switch the context in the XC2000 core:
Switching Context of the Global Register Bank changes the complete global register
bank of CPU registers (GPRs) by changing the Context Pointer with a single instruction,
so the service routine executes within its own separate context. The instruction “SCXT
CP, #New_Bank” pushes the contents of the context pointer (CP) on the system stack
and loads CP with the immediate value “New_Bank”; this in turn, selects a new register
bank. The service routine may now use its “own registers”. This register bank is
preserved when the service routine terminates, i.e. its contents are available on the next
call. Before returning (RETI), the previous CP is simply POPped from the system stack,
which returns the registers to the original global bank.
Resources used by the interrupting program, such as the DPPs, must eventually be
saved and restored.
Note: There are certain timing restrictions during context switching that are associated
with pipeline behavior.
Switching Context by changing the selected register bank automatically updates
bitfield BANK to select one of the two local register banks or the current global register
bank, so the service routine may now use its “own registers” directly. This local register
bank is preserved when the service routine is terminated; thus, its contents are available
on the next call.
When switching to the global register bank, the service routine usually must also switch
the context of the global register bank to get a private set of GPRs, because the global
bank is likely to be used by several tasks.
For interrupt priority levels 15 … 12 the target register bank can be pre-selected and
then be switched automatically. The register bank selection registers BNKSELx provide
a 2-bit field for each possible arbitration priority level. The respective bitfield is then
copied to bitfield BANK in register PSW to select the register bank, as soon as the
respective interrupt request is accepted.
Table 5-10 identifies the arbitration priority level assignment to the respective bitfields
within the four register bank selection registers.
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Interrupt and Trap Functions
BNKSELx
Register Bank Select Reg. x
15
14
13
12
11
XSFR (Table 5-10)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
GPRSEL7 GPRSEL6 GPRSEL5 GPRSEL4 GPRSEL3 GPRSEL2 GPRSEL1 GPRSEL0
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
GPRSELy
(y = 7 … 0)
[2y+1
:2y]
rw
Register Bank Selection
00
Global register bank
01
Reserved
10
Local register bank 1
11
Local register bank 2
Table 5-10
rw
rw
Assignment of Register Bank Control Fields
Bank Select Control Register
Interrupt Node Priority
Notes
Register Name
Bitfields
Intr. Level
Group Levels
BNKSEL0
(EC20H/--)
GPRSEL0 … 3
12
0…3
13
0…3
14
0…3
15
0…3
12
4…7
13
4…7
14
4…7
15
4…7
BNKSEL1
(EC22H/--)
BNKSEL2
(EC24H/--)
BNKSEL3
(EC26H/--)
User’s Manual
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GPRSEL4 … 7
GPRSEL0 … 3
GPRSEL4 … 7
GPRSEL0 … 3
GPRSEL4 … 7
GPRSEL0 … 3
GPRSEL4 … 7
5-34
Lower
group
levels
Upper
group
levels
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5.7
Interrupt and Trap Functions
Interrupt Node Sharing
Interrupt nodes may be shared among several module requests if either the requests are
generated mutually exclusively or the requests are generated at a low rate. If more than
one source is enabled in this case, the interrupt handler will first need to determine the
requesting source. However, this overhead is not critical for low rate requests.
This node sharing is either controlled via interrupt sub-node control registers (ISNC)
which provide separate request flags and enable bits for each supported request source,
or via register ISSR, where each bit selects one of two interrupt sources. The interrupt
level used for arbitration is determined by the node control register (… IC).
The specific request flags within ISNC registers must be reset by software, contrary to
the node request bits which are cleared automatically.
Table 5-11
Sub-Node Control Bit Allocation
Interrupt Node
Interrupt Sources
Control
EOPIC
PEC channels 7 … 0
PECISNC
RTC_IC
RTC: overflow of T14, CNT0 … CNT3
RTC_ISNC
CC2_CC16IC
CAPCOM2 request, ERU request 0
ISSR
CC2_CC17IC
CAPCOM2 request, ERU request 1
ISSR
CC2_CC18IC
CAPCOM2 request, ERU request 2
ISSR
CC2_CC19IC
CAPCOM2 request, ERU request 3
ISSR
CC2_CC20IC
CAPCOM2 request, USIC0 request 6
ISSR
CC2_CC21IC
CAPCOM2 request, USIC0 request 7
ISSR
CC2_CC22IC
CAPCOM2 request, USIC1 request 6
ISSR
CC2_CC23IC
CAPCOM2 request, USIC1 request 7
ISSR
CC2_CC24IC
CAPCOM2 request, ERU request 0
ISSR
CC2_CC25IC
CAPCOM2 request, ERU request 1
ISSR
CC2_CC26IC
CAPCOM2 request, ERU request 2
ISSR
CC2_CC27IC
CAPCOM2 request, ERU request 3
ISSR
CC2_CC28IC
CAPCOM2 request, USIC2 request 6
ISSR
CC2_CC29IC
CAPCOM2 request, USIC2 request 7
ISSR
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5.8
Interrupt and Trap Functions
External Interrupts
Although the XC2000 has no dedicated INTR input pins, it supports many possibilities to
react to external asynchronous events. It does this by using a number of IO lines for
interrupt input. The interrupt function may be either combined with the pin’s main function
or used instead of it if the main pin function is not required.
The External Request Unit (see Section 6.4) provides flexible trigger signals with
selectable qualifiers, which can directly control peripherals (ADC, MultiCAN) or generate
additional interrupt/PEC requests from external input signals.
Table 5-12
Pins Usable as External Interrupt Inputs
Port Pin
Original Function
Control Register
P4.7-0/CC31-24IO
CAPCOM Register 31-24 Capture Input
1)
CC31-CC24
P2.10-3/CC23-16IO
CAPCOM Register 23-16 Capture Input
P4.2/T2IN
Auxiliary timer T2 input pin
T2CON
P4.6/T4IN
Auxiliary timer T4 input pin
T4CON
P2.10/CAPIN
GPT2 capture input pin1)
T5CON
CC23-CC16
1) Pin P2.10 overlays two possible input functions.
For each of these pins, either a positive, a negative, or both a positive and a negative
external transition can be selected to cause an interrupt or PEC service request. The
edge selection is performed in the control register of the peripheral device associated
with the respective port pin (separate control for ERU inputs). The peripheral must be
programmed to a specific operating mode to allow generation of an interrupt by the
external signal. The priority of the interrupt request is determined by the interrupt control
register of the respective peripheral interrupt source, and the interrupt vector of this
source will be used to service the external interrupt request.
Note: In order to use any of the listed pins as an external interrupt input, it must be
switched to input mode via its port control register.
When port pins CCxIO are to be used as external interrupt input pins, bitfield CCMODx
in the control register of the corresponding capture/compare register CCx must select
capture mode. When CCMODx is programmed to 001B, the interrupt request flag CCxIR
in register CCxIC will be set on a positive external transition at pin CCxIO. When
CCMODx is programmed to 010B, a negative external transition will set the interrupt
request flag. When CCMODx = 011B, both a positive and a negative transition will set
the request flag. In all three cases, the contents of the allocated CAPCOM timer will be
latched into capture register CCx, independent of whether or not the timer is running.
When the interrupt enable bit CCxIE is set, a PEC request or an interrupt request for
vector CCxINT will be generated.
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Pins T2IN or T4IN can be used as external interrupt input pins when the associated
auxiliary timer T2 or T4 in block GPT1 is configured for capture mode. This mode is
selected by programming the mode control fields T2M or T4M in control registers
T2CON or T4CON to 101B. The active edge of the external input signal is determined by
bitfields T2I or T4I. When these fields are programmed to X01B, interrupt request flags
T2IR or T4IR in registers T2IC or T4IC will be set on a positive external transition at pins
T2IN or T4IN, respectively. When T2I or T4I is programmed to X10B, then a negative
external transition will set the corresponding request flag. When T2I or T4I is
programmed to X11B, both a positive and a negative transition will set the request flag.
In all three cases, the contents of the core timer T3 will be captured into the auxiliary
timer registers T2 or T4 based on the transition at pins T2IN or T4IN. When the interrupt
enable bits T2IE or T4IE are set, a PEC request or an interrupt request for vector T2INT
or T4INT will be generated.
Pin CAPIN differs slightly from the timer input pins as it can be used as external interrupt
input pin without affecting peripheral functions. When the capture mode enable bit T5SC
in register T5CON is cleared to ‘0’, signal transitions on pin CAPIN will only set the
interrupt request flag CRIR in register CRIC, and the capture function of register
CAPREL is not activated.
So register CAPREL can still be used as reload register for GPT2 timer T5, while pin
CAPIN serves as external interrupt input. Bitfield CI in register T5CON selects the
effective transition of the external interrupt input signal. When CI is programmed to 01B,
a positive external transition will set the interrupt request flag. CI = 10B selects a negative
transition to set the interrupt request flag, and with CI = 11B, both a positive and a
negative transition will set the request flag. When the interrupt enable bit CRIE is set, an
interrupt request for vector CRINT or a PEC request will be generated.
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5.9
Interrupt and Trap Functions
OCDS Requests
The OCDS module issues high-priority break requests or standard service requests. The
break requests are routed directly to the CPU (like the hardware trap requests) and are
prioritized there. Therefore, break requests ignore the standard interrupt arbitration and
receive highest priority.
The standard OCDS service requests are routed to the CPU Action Control Unit together
with the arbitrated interrupt/PEC requests. The service request with the higher priority is
sent to the CPU to be serviced. If both the interrupt/PEC request and the OCDS request
have the same priority level, the interrupt/PEC request wins.
This approach ensures precise break control, while affecting the system behavior as little
as possible.
The CPU Action Control Unit also routes back request acknowledges and denials from
the core to the corresponding requestor.
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5.10
Interrupt and Trap Functions
Service Request Latency
The numerous service requests of the XC2000 (requests for interrupt or PEC service)
are generated asynchronously with respect to the execution of the instruction flow.
Therefore, these requests are arbitrated and are inserted into the current instruction
stream. This decouples the service request handling from the currently executed
instruction stream, but also leads to a certain latency.
The request latency is the time from activating a request signal at the interrupt controller
(ITC) until the corresponding instruction reaches the pipeline’s execution stage.
Table 5-13 lists the consecutive steps required for this process.
Table 5-13
Steps Contributing to Service Request Latency
Description of Step
Interrupt Response
PEC Response
Request arbitration in 3 stages,
leads to acceptance by the CPU
(see Section 5.2)
3 cycles
3 cycles
Injection of an internal instruction into
the pipeline’s instruction stream
4 cycles
4 cycles
The first instruction fetched from the
interrupt vector table reaches the
pipeline’s execution stage
4 cycles / 01)
---
Resulting minimum request latency
11/7 cycles
7 cycles
1) Can be saved by using the interrupt jump table cache (see Section 5.3).
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Interrupt and Trap Functions
Sources for Additional Delays
Because the service requests are inserted into the current instruction stream, the
properties of this instruction stream can influence the request latency.
Table 5-14
Additional Delays Caused by System Logic
Reason for Delay
Interrupt Response
PEC Response
Interrupt controller busy,
max. 7 cycles
because the previous interrupt request
is still in process
max. 7 cycles
Pipeline is stalled,
2 × TACCmax1)
because instructions preceding the
injected instruction in the pipeline need
to write/read data to/from a peripheral
or memory
2 × TACCmax
Pipeline cancelled,
because instructions preceding the
injected instruction in the pipeline
update core SFRs
4 cycles
4 cycles
Memory access for stack writes (if not
to DPRAM or DSRAM)
2/3 × TACC2)
---
Memory access for vector table read
(except for intr. jump table cache)
2 × TACC
---
1) This is the longest possible access time within the XC2000 system.
2) Depending on segmentation off/on.
The actual response to an interrupt request may be delayed further depending on
programming techniques used by the application. The following factors can contribute:
•
•
Actual interrupt service routine is only reached via a JUMP from the interrupt vector
table.
Time-critical instructions can be placed directly into the interrupt vector table,
followed by a branch to the remaining part of the interrupt service routine. The space
between two adjacent vectors can be selected via bitfield VECSC in register
CPUCON1.
Context switching is executed before the intended action takes place (see
Section 5.6)
Time-critical instructions can be programmed “non-destructive” and can be executed
before switching context for the remaining part of the interrupt service routine.
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5.11
Interrupt and Trap Functions
Trap Functions
Traps interrupt current execution in a manner similar to standard interrupts. However,
trap functions offer the possibility to bypass the interrupt system’s prioritization process
for cases in which immediate system reaction is required. Trap functions are not
maskable and always have priority over interrupt requests on any priority level.
The XC2000 provides two different kinds of trapping mechanisms: Hardware Traps are
triggered by events that occur during program execution (such as illegal access or
undefined opcode); Software Traps are initiated via an instruction within the current
execution flow.
Software Traps
The TRAP instruction causes a software call to an interrupt service routine. The vector
number specified in the operand field of the trap instruction determines which vector
location in the vector table will be branched to.
Executing a TRAP instruction causes an effect similar to the occurrence of an interrupt
at the same vector. PSW, CSP (in segmentation mode), and IP are pushed on the
internal system stack and a jump is taken to the specified vector location. When a trap
is executed, the CSP for the trap service routine is loaded from register VECSEG. No
Interrupt Request flags are affected by the TRAP instruction. The interrupt service
routine called by a TRAP instruction must be terminated with a RETI (return from
interrupt) instruction to ensure correct operation.
Note: The CPU priority level and the selected register bank in register PSW are not
modified by the TRAP instruction, so the service routine is executed on the same
priority level from which it was invoked. Therefore, the service routine entered by
the TRAP instruction uses the original register bank and can be interrupted by
other traps or higher priority interrupts, other than when triggered by a hardware
event.
Hardware Traps
Hardware traps are issued by faults or specific system states which occur during runtime
of a program (not identified at assembly time). A hardware trap may also be triggered
intentionally, for example: to emulate additional instructions by generating an Illegal
Opcode trap. The XC2000 distinguishes nine different hardware trap functions. When a
hardware trap condition has been detected, the CPU branches to the trap vector location
for the respective trap condition. The instruction which caused the trap is completed
before the trap handling routine is entered.
Hardware traps are non-maskable and always have priority over every other CPU
activity. If several hardware trap conditions are detected within the same instruction
cycle, the highest priority trap is serviced (see Table 5-3).
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Interrupt and Trap Functions
PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and
the CPU level in register PSW is set to the highest possible priority level (level 15),
disabling all interrupts. The global register bank is selected. Execution branches to the
respective trap vector in the vector table. A trap service routine must be terminated with
the RETI instruction.
The nine hardware trap functions of the XC2000 are divided into two classes:
Class A traps are:
•
•
•
•
System Request 0 (SR0)
Stack Overflow
Stack Underflow trap
Software Break
These traps share the same trap priority, but have individual vector addresses.
Class B traps are:
•
•
•
•
•
System Request 1 (SR1)
Undefined Opcode
Memory Access Error
Protection Fault
Illegal Word Operand Access
The Class B traps share the same trap priority and the same vector address.
The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the
kind of trap which caused the exception. Each trap function is indicated by a separate
request flag. When a hardware trap occurs, the corresponding request flag in register
TFR is set to ‘1’.
The reset functions may be regarded as a type of trap. Reset functions have the highest
system priority (trap priority III).
Class A traps have the second highest priority (trap priority II), on the 3rd rank are
Class B traps, so a Class A trap can interrupt a Class B trap. If more than one Class A
trap occur at a time, they are prioritized internally, with the SR0 trap at the highest and
the software break trap at the lowest priority.
In the case where e.g. an Undefined Opcode trap (class B) occurs simultaneously with
an SR0 trap (class A), both the SR0 and the UNDOPC flag is set, the IP of the instruction
with the undefined opcode is pushed onto the system stack, but the SR0 trap is
executed. After return from the SR0 service routine, the IP is popped from the stack and
immediately pushed again because of the pending UNDOPC trap.
Note: The trap service routine must clear the respective trap flag; otherwise, a new trap
will be requested after exiting the service routine. Setting a trap request flag by
software causes the same effects as if it had been set by hardware.
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Interrupt and Trap Functions
TFR
Trap Flag Register
15
14
12
11
Reset Value: 0000H
10
9
8
7
6
5
STK STK
SR0
OF UF
-
-
-
UND
OPC
-
-
rwh
-
-
-
rwh
-
-
rwh
13
SFR (FFACH/D6H)
SOF
T SR1
BRK
rwh rwh rwh
4
3
1
0
AC PRT ILL
ER FLT OPA
-
-
rwh
-
-
rwh
2
rwh
Field
Bits
Type
Description
SR0
15
rwh
System Request 0 Flag
0
No trigger detected
1
The selected condition has been detected
STKOF
14
rwh
Stack Overflow Flag
0
No stack overflow event detected
1
The current stack pointer value falls below the
contents of register STKOV
STKUF
13
rwh
Stack Underflow Flag
0
No stack underflow event detected
1
The current stack pointer value exceeds the
contents of register STKUN
SOFTBRK
12
rwh
Software Break
0
No software break event detected
1
Software break event detected
SR1
11
rwh
System Request 1 Flag
0
No trigger detected
1
The selected condition has been detected
UNDOPC
7
rwh
Undefined Opcode
0
No undefined opcode event detected
1
The currently decoded instruction has no valid
XC2000 opcode
ACER
4
rwh
Memory Access Error
0
No access error event detected
1
Illegal or erroneous access detected
PRTFLT
3
rwh
Protection Fault
0
No protection fault event detected
1
A protected instruction with an illegal format
has been detected
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Preliminary
Interrupt and Trap Functions
Field
Bits
Type
Description
ILLOPA
2
rwh
Illegal Word Operand Access
0
No illegal word operand access event detected
1
A word operand access (read or write) to an
odd address has been attempted
Class A Traps
Class A traps are generated by the high priority system request SR0 or by special CPU
events such as the software break, a stack overflow, or an underflow event. Class A
traps are not used to indicate hardware failures. After a Class A event, a dedicated
service routine is called to react on the events. Each Class A trap has its own vector
location in the vector table. Class A traps cannot interrupt atomic/extend sequences and
I/O accesses in progress, because after finishing the service routine, the instruction flow
must be further correctly executed. For example, an interrupted extend sequence cannot
be restarted. All Class A traps are generated in the pipeline during the execution of
instructions, except for SR0, which is an asynchronous external event. Class A trap
events can be generated only during the memory stage of execution, so traps cannot be
generated by two different instructions in the pipeline in the same CPU cycle. The
execution of instructions which caused a Class A trap event is always completed. In the
case of an atomic/extend sequence or I/O read access in progress, the complete
sequence is executed. Upon completion of the instruction or sequence, the pipeline is
canceled and the IP of the instruction following the last one executed is pushed on the
stack. Therefore, in the case of a Class A trap, the stack always contains the IP of the
first not-executed instruction in the instruction flow.
Note: The Branch Folding Unit allows the execution of a branch instruction in parallel
with the preceding instruction. The pre-processed branch instruction is combined
with the preceding instruction. The branch is executed together with the instruction
which caused the Class A trap. The IP of the first following not-executed
instruction in the instruction flow is then pushed on the stack.
If more than one Class A trap occur at the same time, they are prioritized internally. The
SR0 trap has the highest priority and the software break has the lowest.
Note: In the case of two different Class A traps occurring simultaneously, both trap flags
are set. The IP of the instruction following the last one executed is pushed on the
stack. The trap with the higher priority is executed. After return from the service
routine, the IP is popped from the stack and immediately pushed again because
of the other pending Class A trap (unless the trap related to the second trap flag
in TFR has been cleared by the first trap service routine).
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Preliminary
Interrupt and Trap Functions
Class B Traps
Class B traps are generated by unrecoverable hardware failures. In the case of a
hardware failure, the CPU must immediately start a failure service routine. Class B traps
can interrupt an atomic/extend sequence and an I/O read access. After finishing the
Class B service routine, a restoration of the interrupted instruction flow is not possible.
All Class B traps have the same priority (trap priority I). When several Class B traps
become active at the same time, the corresponding flags in the TFR register are set and
the trap service routine is entered. Because all Class B traps have the same vector, the
priority of service of simultaneously occurring Class B traps is determined by software in
the trap service routine.
The access error (ACER) and system request 1 (SR1) are asynchronous external (to the
CPU) events, while all other Class B traps are generated in the pipeline during the
execution of instructions. Class B trap events can be generated only during the memory
stage of execution, so traps cannot be generated by two different instructions in the
pipeline in the same CPU cycle. Instructions which caused a Class B trap event are
always executed, then the pipeline is canceled and the IP of the instruction following the
one which caused the trap is pushed on the stack. Therefore, the stack always contains
the IP of the first following not-executed instruction in the instruction flow.
Note: The Branch Folding Unit allows the execution of a branch instruction in parallel
with the preceding instruction. The pre-processed branch instruction is combined
with the preceding instruction. The branch is executed together with the instruction
causing the Class B trap. The IP of the first following not-executed instruction in
the instruction flow is pushed on the stack.
A Class A trap occurring during the execution of a Class B trap service routine will be
serviced immediately. During the execution of a Class A trap service routine, however,
any Class B trap occurring will not be serviced until the Class A trap service routine is
exited with a RETI instruction. In this case, the occurrence of the Class B trap condition
is stored in the TFR register, but the IP value of the instruction which caused this trap is
lost.
Note: If a Class A trap occurs simultaneously with a Class B trap, both trap flags are set.
The IP of the instruction following the one which caused the trap is pushed into the
stack, and the Class A trap is executed. If this occurs during execution of an
atomic/extend sequence or I/O read access in progress, then the presence of the
Class B trap breaks the protection of atomic/extend operations and the Class A
trap will be executed immediately without waiting for the sequence completion.
After return from the service routine, the IP is popped from the system stack and
immediately pushed again because of the other pending Class B trap. In this
situation, the restoration of the interrupted instruction flow is not possible.
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System Units (Vol. 1 of 2)
Preliminary
Interrupt and Trap Functions
System Request 0 Trap (A)
Whenever a high-to-low transition on the respective CPU-input is detected (i.e. the
defined condition has become true), the SR0 flag in register TFR is set and the CPU will
enter the SR0 trap routine.
Stack Overflow Trap (A)
Whenever the stack pointer is implicitly decremented and the stack pointer is equal to
the value in the stack overflow register STKOV, the STKOF flag in register TFR is set
and the CPU will enter the stack overflow trap routine.
For recovery from stack overflow, it must be ensured that there is enough excess space
on the stack to save the current system state twice (PSW, IP, in segmented mode also
CSP). Otherwise, a system reset should be generated.
Stack Underflow Trap (A)
Whenever the stack pointer is implicitly incremented and the stack pointer is equal to the
value in the stack underflow register STKUN, the STKUF flag is set in register TFR and
the CPU will enter the stack underflow trap routine.
Software Break Trap (A)
When the instruction currently being executed by the CPU is a SBRK instruction, the
SOFTBRK flag is set in register TFR and the CPU enters the software break debug
routine. The flag generation of the software break instruction can be disabled by the Onchip Emulation Module. In this case, the instruction only breaks the instruction flow and
signals this event to the debugger, the flag is not set and the trap will not be executed.
System Request 1 Trap (B)
Whenever a high-to-low transition on the respective CPU-input is detected (i.e. the
defined condition has become true), the SR1 flag in register TFR is set and the CPU will
enter the SR1 trap routine.
Undefined Opcode Trap (B)
When the instruction currently decoded by the CPU does not contain a valid XC2000
opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined
opcode trap routine. The instruction that causes the undefined opcode trap is executed
as a NOP.
This can be used to emulate unimplemented instructions. The trap service routine can
examine the faulting instruction to decode operands for unimplemented opcodes based
on the stacked IP. In order to resume processing, the stacked IP value must be
incremented by the size of the undefined instruction, which is determined by the user,
before a RETI instruction is executed.
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Preliminary
Interrupt and Trap Functions
Memory Access Error (B)
When a memory access error is detected, the ACER flag is set in register TFR and the
CPU enters the access error trap routine. The access error is reported in the following
cases:
•
•
•
•
•
access to Flash memory while it is disabled
access to Flash memory from outside while read-protection is active
double bit error detected when reading Flash memory
access to reserved locations (see memory map in Table 3-1)
parity error during an access to RAM
In case of an access error, additionally the soft-trap code 1E9BH is issued.
Protection Fault Trap (B)
Whenever one of the special protected instructions is executed where the opcode of that
instruction is not repeated twice in the second word of the instruction and the byte
following the opcode is not the complement of the opcode, the PRTFLT flag in register
TFR is set and the CPU enters the protection fault trap routine. The protected
instructions include DISWDT, EINIT, IDLE, PWRDN, SRST, ENWDT and SRVWDT.
The instruction that causes the protection fault trap is executed like a NOP.
Illegal Word Operand Access Trap (B)
Whenever a word operand read or write access is attempted to an odd byte address, the
ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access
trap routine.
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Preliminary
User’s Manual
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System Units (Vol. 1 of 2)
Preliminary
6
System Control Unit (SCU)
System Control Unit (SCU)
The System Control Unit (SCU) of the XC2000 handles all system control tasks beside
the debug related tasks which are controlled by the OCDS/Cerberus and the test related
tasks which are controlled by the TCU. All functions described in this chapter are tightly
coupled, thus, they are conveniently handled by one unit, the SCU.
The SCU contains the following functional sub-blocks:
•
•
•
•
•
•
•
•
•
•
Clock Generation (see Section 6.1 on Page 6-2)
Reset Operation (see Section 6.2 on Page 6-33)
Power Supply (see Section 6.5 on Page 6-90)
Global State Control (see Section 6.6 on Page 6-156)
Wake-up Timer (see Section 6.9 on Page 6-176)
Register Access Control (see Section 6.10.1 on Page 6-181)
Watchdog Timer (see Section 6.8 on Page 6-168)
External Interrupts (see Section 6.4 on Page 6-64)
Temperature Compensation (see Section 6.7 on Page 6-165)
SCU registers and Address map (see Section 6.13 on Page 6-220)
User’s Manual
SCU, V1.1
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.1
System Control Unit (SCU)
Clock Generation Unit
The Clock Generation Unit (CGU) allows a very flexible clock generation for XC2000.
During user program execution the frequency can be programmed for an optimal ratio
between performance and power consumption. Therefore the power consumption can
be adapted to the actual application state.
The CGU in the XC2000 consists of a clock generator block and a clock control unit
(CCU). The CGU can convert a low-frequency external clock to a high-speed internal
clock, or can create a high-speed internal clock without external input.
The system clock fSYS is generated out of four selectable clocks:
•
•
•
•
PLL clock fPLL
Wake-Up clock fWU
The Direct Clock fOSC, from pin XTAL1
Input DIRIN as Direct Clock Input fDIR
The RTC clock fRTC which is generated out of four selectable clocks:
•
•
•
•
PLL clock fPLL
The Direct Clock from pin XTAL1 fOSC
Input DIRIN as Direct Clock Input fDIR
Input DRTC as Direct Clock Input fDRTC
XTAL1
fOSC
XTAL2
Clock Generator
fPL L
f SYS
fWU
CCU
DIRIN
DRTC
fD IR IN
f SYS
to RTC
fR TC
fPD R TC
EXTCLK
to CC60
Clock Generation Unit (CGU)
CG U_Block_Diagram.vsd
Figure 6-1
User’s Manual
SCU, V1.1
Clock Generation Unit Block Diagram
6-2
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
The CGU is controlled by a number of registers, shown in Figure 6-2. The following
sections describe the different parts of the CGU.
Oscillator Control
PLL Control
System Control
Output Control
WUOSCCON
HPOSCCON
PLLCON0
SYSCON0
RTCCLKCON
PLLCON1
STATCLR0
EXTCON
PLLOSCCON
PLLCON2
STATCLR1
PLLCON3
PLLSTAT
WUOSCCON
Wake-up OSC Control Register
HPOSCCON
High Precision OSC Control Register
PLLOSCCON
PLLSTAT
PLL OSC Configuration Register
PLL Status Register
PLLCON0
PLL Configuration 0 Register
PLLCON1
PLLCON2
PLL Configuration 1 Register
PLL Configuration 2 Register
PLLCON3
PLL Configuration 3 Register
SYSCON0
STATCLR0
System Control 0 Register
Status Clear 0 Register
STATCLR1
Status Clear 1 Register
RTCCLKCON
EXTCON
RTC Clock Control Register
External Clock Control Register
CGU_Register_Overview.vsd
Figure 6-2
6.1.1
Clock Generation Unit Register Overview
Wake-Up Clock Circuit (OSC_WU)
The wake-up clock circuit provides fWU as output.
The clock frequency can be configured via bit field WUOSCCON.FREQSEL.
6.1.2
High Precision Oscillator Circuit (OSC_HP)
The high precision oscillator circuit, designed to work with both an external crystal
oscillator or an external stable clock source, consists of an inverting amplifier with XTAL1
as input, and XTAL2 as output.
Figure 6-3 shows the recommended external circuitries for both operating modes,
External Crystal Mode and External Input Clock Mode.
6.1.2.1
External Input Clock Mode
When supplying the clock directly, not using an external crystal and bypassing the highprecision oscillator, the input frequency needs to be equal or greater than 4 MHz if the
PLL VCO part is used.
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Preliminary
System Control Unit (SCU)
When using an external clock it must be connected to XTAL1. XTAL2 is left open
(unconnected).
6.1.2.2
External Crystal Mode
When using an external crystal, its frequency can be within the range of 4 MHz
to 25 MHz. An external oscillator load circuitry must be used, connected to both pins,
XTAL1 and XTAL2. It consists normally of the two load capacitances C1 and C2, for
some crystals a series damping resistor might be necessary. The exact values and
related operating range are dependent on the crystal and have to be determined and
optimized together with the crystal vendor using the negative resistance method. As
starting point for the evaluation, the following load cap values may be used:
Table 6-1
External CAP Capacitors
Fundamental Mode Crystal Frequency
(approx., MHz)
Load Caps C1, C2 (pF)
4
33
8
18
12
12
16
10
20
10
25
8
Fundamental Mode Crystal
4 to 25 MHz
XTAL1
fCRYST
OSC_HP
XTAL2
C1
fOSC
C2
VSS
CGU_OSC_HP_Crystal.vsd
Figure 6-3
User’s Manual
SCU, V1.1
XC2000 External Crystal Mode Circuitry for the High-Precision
Oscillator
6-4
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Preliminary
System Control Unit (SCU)
XTAL1
f EXT
External
Clock Signal
OSC_HP
XTAL2
fOSC
leave unconnected
VSS
CGU_OSC_HP_ExtIn.vsd
Figure 6-4
6.1.3
XC2000 External Clock Input Mode for the High-Precision Oscillator
Phase-Locked Loop (PLL) Module
This section describes the XC2000 PLL module.
The clock fPLL is generated in one of three selectable ways:
•
•
•
Prescaler Mode
Normal Mode
Free-Running Mode
6.1.3.1
Features
Here is a brief overview of the functions that are offered by the PLL.
•
•
•
•
•
•
•
•
•
•
•
•
Programmable clock generation PLL
VCO lock detection
High-Precision Oscillator Watchdog
4 bit input divider P: (divide by PDIV+1)
6 bit feedback divider N: (multiply by NDIV+1)
10 bit output divider K1 or K2: (divide by either by K1DIV+1 or K2DIV+1)
Prescaler Mode
Free-Running Mode
Normal Mode
VCO Power Down (Sleep Mode)
Glitchless switching between both K-Dividers
Glitchless switching between Normal Mode and Prescaler Mode
6.1.3.2
PLL Functional Description
The following figure shows the PLL block structure.
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Preliminary
System Control Unit (SCU)
PLLCON.O SCSEL
0
f OSC
1
f IOSC
M
U
X
fR
PLLSTAT.FINDIS
fP
PDivider
K1- fK1
Divider 1
fR EF
Lock
Detect.
Osc.
WDG
VCO
Core
fD IV
fVC O
0
K2Divider fK2
NDivider
M
U
X
fPL L
PLLCON.
VCOBY
PLL Block
PLL_Block_Diagram.vsd
Figure 6-5
PLL Block Diagram
The reference frequency fR can be selected to be either taken from the internal clock
(IOSC), generating fINT, or from an external clock source, fOSC.
The PLL uses up to three dividers to manipulate the reference frequency in a
configurable way. Each of the three dividers can be bypassed in defining the following
PLL operating modes.
•
•
•
Bypassing P, N and K2 dividers; this defines the Prescaler Mode
Bypassing K1 divider; this defines the Normal Mode
Bypassing K1 divider and ignoring the P divider; this defines the Free-Running Mode
Table 6-2 shows clock source options that can be selected.
Table 6-2
Clock Option Selection
VCOBY
FINDISC
Mode Selected
0
0
Normal Mode
1
x
Prescaler Mode
0
1
Free-Running Mode
Normal Mode
In Normal Mode, the reference frequency fR is divided down by a factor P, multiplied by
a factor N, and then divided down by a factor K2.
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System Control Unit (SCU)
PLLCON.O SCSEL
PLLSTAT.FINDIS
1
0
f OSC
f IOSC
1
M
U
X
fR
fP
PDivider
fR EF
VCO
Core
Lock
Detect.
Osc.
WDG
fD IV
fVC O
0
K2Divider fK2
NDivider
M
U
X
fPL L
PLLCON.
VCOBY
PLL Block
PLL_Normal_Mode.vsd
Figure 6-6
PLL Normal Mode Diagram
The output frequency is given by:
(6.1)
N
f PLL = ---------------- ⋅ f R
P ⋅ K2
The Normal Mode is selected by the following settings:
•
•
PLLCON0.VCOBY = 0
STATCLR1.CLRFINDIS = 1
The Normal Mode is entered when
•
•
•
•
PLLSTAT.FINDIS = 0
PLLSTAT.VCOBYST = 1
PLLSTAT.VCOLOCK = 1
HPOSCCON.PLLV = 1
Prescaler Mode
In Prescaler Mode, the reference frequency fR is only divided down by a factor K1.
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System Control Unit (SCU)
PLLCON.O SCSEL
0
f OSC
f IOSC
1
M
U
X
K1- fK1
Divider 1
fR
0
M
U
X
fPL L
PLLCON.
VCOBY
Osc.
WDG
PLL Block
PLL_Prescaler_Mode.vsd
Figure 6-7
PLL Prescaler Mode Diagram
The output frequency is given by:
(6.2)
fR
f PLL = ------K1
The Prescaler Mode is selected by the following settings:
•
PLLCON0.VCOBY = 1
The Prescaler Mode is entered when
•
•
PLLSTAT.VCOBYST = 0
HPOSCCON.PLLV = 1
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Preliminary
System Control Unit (SCU)
Free-Running Mode
In Freerunning Mode, the base frequency output fVCObase of the Voltage Controlled
Oscillator (VCO) is divided down by a factor K2.
PLLSTAT.FINDIS
1
'1'
fR EF
VCO
Core
Lock
Detect.
fD IV
fVC O
0
K2Divider fK2
NDivider
M
U
X
f PL L
PLLCON.
VCOBY
PLL Block
PLL_FreeRunning_Mode.vsd
Figure 6-8
PLL Free-Running Mode Diagram
The output frequency is given by:
(6.3)
f VCObase
f PLL = -----------------------------K2
The Free-Running Mode is selected by the following settings:
•
•
PLLCON0.VCOBY = 0
STATCLR1.SETFINDIS = 1
The Freerunning Mode is entered when
•
•
PLLCON1.FINDIS = 1
PLLSTAT.VCOBYST = 1
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
General Configuration Overview
All four divider values and all necessary other values can be configured via the PLL
configuration registers.
The following Figure 6-9 provides an overview of the PLL dividers and the frequency
ranges which are valid for each of the individual paths within the PLL block.
0..40 MHz
fEXT
fOSC
K1
0..40 MHz
4..40 MHz
fCRYST
fR
4..25 MHz
~ 5 MHz
fIOSC
P
4..16 MHz
fP
VCO
fN
IOSC
4..16 MHz
48..160 MHz
fVCO
K2
0..40 MHz
fK1
0..80 MHz
fK2
fPLL
0..80 MHz
N
PLL_Frequencies.vsd
Figure 6-9
Overview on Frequency Ranges for the PLL Block
The P-Divider generates the necessary input reference frequency fP for the VCO, which
is then compared to the divided output frequency fN of the VCO. Figure 6-10 gives a
graphical representation of the resulting frequency range for fP versus the input
frequency fOSC, respectively fR, for valid values of the P-Divider factor, while Table 6-3
provides some numerical examples.
[MHz]
fP
20
P= 1
P= 2
15
P= 3
P= 4
10
P= 5
P= 6
P= 7
5
P = 10
valid input range for f CRYST
fOSC
5
10
15
20
25
30
35
40 [MHz]
PLL_P-Factor_Frequencies.vsd
Figure 6-10 Possible P-Factor Values, fP versus fOSC
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System Units (Vol. 1 of 2)
Preliminary
Table 6-3
PDIV
System Control Unit (SCU)
P-Divider Factors
fP for fR =
P=
PDIV + 1
0
1
1
2
2
3
3
4
4
5
5
6
6+
7+
4 MHz
5 MHz
10 MHz
16 MHz
25 MHz
4
5
10
16
not allowed
5
8
12.5
5.33
8.33
4
6.25
not allowed
not allowed
5
not allowed
4.16
not allowed
Note: Of course, the whole range in between two fR columns in the table above is
allowed. E.g., for a range fR = 10 to 16 MHz, and P = 1, fP = 5 to 8 MHz.
Note: Higher values for fR are and can be achieved if fOSC is used and the high-precision
oscillator is bypassed. In this case, higher values for P are allowed and can be
even required.
The P-divider output frequency fP is fed to a VCO. The VCO is a part of the PLL, with a
feedback path. A divider in the feedback path (N-Divider) divides the VCO frequency.
The resulting frequency fN is compared to the VCO input frequency fP and must therefore
have the same frequency. The VCO is designed such that it can operate in two, partly
overlapping, frequency ranges. To achieve the desired output frequency of the VCO,
both, the N-factor and the VCO frequency range, must be programmed appropriately.
The N-divider output frequency fN is then compared with fP in the phase detector logic
within the VCO. The phase detector determines the difference between the two clocks,
and accordingly controls the output frequency fVCO.
Note: Due to this operation, the VCO clock of the PLL has a frequency which is a multiple
of fP. The factor for this is controlled through the value applied to the N-divider in
the feedback path. For this reason, this factor is often called a multiplier, although
it actually controls a division.
The output frequency fVCO of the VCO is divided by K2 to provide the final desired output
frequency fPLL.
6.1.3.3
High-Precision Oscillator Watchdog (OSC_WDG)
The OSC_WDG monitors the incoming clock fOSC to check whether it is above a lower
limit or not. The limit is defined in the data sheet
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System Control Unit (SCU)
The OSC_WDG uses the internal clock (IOSC) frequency fIOSC for its operation, thus, the
internal clock has to be enabled.
By setting bit HPOSCCON.OSCWDTRST, the detection can be restarted without a reset
of the complete PLL, e.g., in case of OSC loss-of-lock condition.
Note: After the OSC_WDG is reset, bit HPOSCCON.PLLV is not valid for some time
(544 * fOSCPLL).
6.1.3.4
PLL VCO Lock Detection
The PLL has a lock detection, which supervises the VCO part of the PLL in order to
differentiate between stable and instable VCO circuit behavior. The lock detector marks
the VCO output fVCO as instable, if the two inputs, fP and fR, differ too much. Changes in
one or both input frequencies below a certain deviation are not marked as a loss of lock,
since the VCO can handle such small changes without any problem for the system.
6.1.3.5
Internal Clock (OSC_PLL)
The PLL internal clock can be used for two different applications:
Operating the OSC_WDG
With this option, the input frequency for the PLL, either from OSC_HP or from XTAL1, is
supervised with OSC_PLL. For more information, please see Chapter 6.1.3.3.
Providing an input clock to the PLL
In case no external clock input is used via XTAL1, the clock frequency fIOSC of the internal
PLL clock, IOSC, can be used as input clock for all PLL modes. This is controlled and
configured via PLLCON1.OSCSEL.
6.1.3.6
Switching PLL Parameters
The following restrictions apply when changing PLL parameters via the PLLCON0
through PLLCON3 registers:
•
•
•
•
The VCO bypass switch may be used at any time, however, it has to be ensured that
the maximum operating frequency of the device (see data sheet) will not be
exceeded.
Before switching NDIV and PDIV, the Prescaler Mode has to be selected.
Before deselecting the Prescaler Mode, the RESLD bit has to be set and then the
VCOLOCK flag has to be checked. Only when the VCOLOCK flag is set again, the
Prescaler Mode may be deselected.
Before changing VCOSEL, the Prescaler Mode must be selected.
Note: PDIV and NDIV can also be switched in Normal Mode. When changing NDIV, it
must be regarded that the VCO clock fVCO may exceed the target frequency until
User’s Manual
SCU, V1.1
6-12
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
the PLL becomes locked. After changing PDIV or NDIV, one must wait for the PLL
lock condition. This procedure is typically used for increasing the VCO clock stepby-step.
6.1.4
Clock Control Unit
The Clock Control Unit (CCU) receives the output clock fPLL, which is created by the PLL,
the clock fWU from the wake-up clock, and the XTAL1/OSC_HP clock fOSC. In order to
obtain the system frequency, one of the three clock sources is selected.
Additionally, the control logic for the RTC asynchronous clock supply is located in the
Clock Control Unit.
OSCWDT
Emergency
Event
VCO LCK
Emergency
Event
SYSCO N0.CLKSEL
fWU
00
fOSC
01
fPL L
10
f D IR IN
11
M
U
X
Master
Clock
Multiplexer
(MCM)
10
SYSCON0.EMCLKSELEN
PLLCON1.EMCLKEN
HPOSCCON.EMCLKEN
0
1
00
01
System
Clock
Selection
M
U
X
Emergency
Clock
M
U
X
fSYS
to EXTCLK selection
11
SYSCON0.EMCLKSEL
CCU_SYSCLK.vsd
Figure 6-11 Clock Control Unit, SYSCLK Generation
User’s Manual
SCU, V1.1
6-13
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
RTCCLKCON.
RTCCLKSEL
fPL L
00
fOSC
01
fWU
10
f D R TC
11
RTCCLKCO N.
RTCCM
M
U
X
fR TC
0
1
M
U
X
to RTC block
fSYS
CCU_RTCCLK.vsd
Figure 6-12 Clock Control Unit, RTCCLK Generation
6.1.4.1
Emergency Clock Operation
There are two possible scenarios which can lead to a loss of the system clock, and
therefore to a dead-lock of the system. All three scenarios are based on the same rootcause: the system is clocked with a clock that is not longer suitable as clock source.
Oscillator Watchdog Event
For the unlikely case that the clock from the external source (or crystal) received from
OSC_HP drops below a value, for which the PLL VCO part is no longer able to generate
a stable system clock, an oscillator watchdog (OSCWDT) emergency event is
implemented.
The
mechanism
can
be
enabled / disabled
via
bit
HPOSCCON.EMCLKEN.
In case of an enabled OSCWDT event, the following actions are performed:
•
•
•
•
•
•
The oscillator watchdog trap flag (TRAPSTAT.OSCWDTT) is set, and a trap request
to the CPU is activated, if enabled (TRAPDIS.OSCWDTT = 0);
Bit HPOSCCON.PLLV is cleared;
Bit HPOSCCON.OSC2L1 is set;
Bit SYSCON0.EMSOSC is set if SYSCON0.EMCLKSELEN is set;
The system clock is switched to the clock source selected by
SYSCON0.EMCLKSEL, if enabled (SYSCON0.EMCLKSELEN = 1);
The PLL VCO clock input selection can be updated if HPOSCCON.EMFINDISEN is
set.
Emergency routines can be executed with the pre-configured clock. The current
occurrence of an OSCWDT emergency event is indicated by bit
SYSCON0.EMSOSC = 1. The occurrence of a previous OSCWDT emergency event is
indicated by bit HPOSCCON.OSC2L1 = 1.
User’s Manual
SCU, V1.1
6-14
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
An OSCWDT emergency event is terminated by setting bit STATCLR0.EMCOSC. Bit
HPOSCCON.OSC2L0 = 1 indicates that an OSCWDT emergency event condition is no
longer valid.
Note: The oscillator watchdog does not refer to the start-up process. Bit
HPOSCCON.PLLV has to be set first before the oscillator watchdog trap
generation mechanism is activated.
PLL VCO Loss of Lock Event
For the unlikely case that the PLL VCO part is no longer able to generate a stable system
clock, a PLL VCO loss of lock (VCOLCK) emergency event is implemented. The
mechanism can be enabled / disabled via bit PLLCON1.EMCLKEN.
In case of an enabled VCOLCK event, the following actions are performed:
•
•
•
•
•
•
The PLL VCO loss of lock trap flag (TRAPSTAT.VCOLCKT) is set, and a trap request
to the CPU is activated, if enabled (TRAPDIS.VCOLCKT = 0);
Bit PLLSTAT.VCOLOCK is cleared;
Bit PLLSTAT.VCOL0 is set;
Bit SYSCON0.EMSVCO is set if SYSCON0.EMCLKSELEN is set;
The system clock is switched to the clock source selected by
SYSCON0.EMCLKSEL, if enabled (SYSCON0.EMCLKSELEN = 1);
The PLL VCO clock input select can be updated if PLLCON1.EMFINDISEN is set.
Emergency routines can be executed with the pre-configured clock. The current
occurrence of a VCOLCK emergency event is indicated by bit SYSCON0.EMSVCO = 1.
The occurrence of a previous VCOLCK emergency event is indicated by bit
PLLSTAT.VCOL0 = 1.
A VCOLCK emergency event is terminated by setting bit STATCLR0.EMCVCO. Bit
PLLSTAT.VCOL1 = 1 indicates that a VCOLCK emergency event condition is no longer
valid.
6.1.5
External Clock Output
An external clock output is provided via pin EXTCLK. This external clock can be
enabled/disabled via bit EXTCON.EN. Each of the six clocks which defines a clock
domain can be individually be selected to be output at pin EXTCLK. This is configured
via bit field EXTCON.SEL. Changing the content of bit field EXTCON.SEL can lead to
spikes at pin EXTCLK.
Additionally, a connection to the CAPCOM60 module is implemented, to support the
start-up control of an external crystal for the system clock generation. The first time,
before the system clock is generated based on an external crystal, one should wait for
1000 cycles of the crystal clock before the clock control system is changed to External
Crystal Mode. The 1000 cycles can be counted with CC60, using fOSC as count input for
the counter.
User’s Manual
SCU, V1.1
6-15
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
EXTCO N.SEL
0000
fSYS
Reload fOU T
Counter
0001
fPL L
0010
fOSC
0011
fWU
0100
f D IR IN
0101
EXTCON.EN
reserved
0110
reserved
0111
reserved
1000
'0'
'0'
M
U
X
0
1
M
U
X
EXTCLK
to CC60
1001
...
1111
CCU_EXTCLK.vsd
Figure 6-13 Clock Control Unit, EXTCLK Generation
6.1.5.1
Programmable Frequency Output
The system clock output (EXTCLK) can be replaced by the programmable frequency
output fOUT. This output can be controlled via software, and so can be adapted to the
requirements of the connected external circuitry. The programmability also extends the
power management to a system level, as also circuitry (peripherals, etc.) outside the
XC2000 can be influenced, i.e. run at a scalable frequency, or can temporarily be
switched off completely.
Clock fOUT is generated via a reload counter, such that the output frequency can be
selected in small steps.
User’s Manual
SCU, V1.1
6-16
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
EXTCON.FORV
EXTCON.
FOEN
Ctrl.
Reload
1
fSYS
Counter
0
FOTL
M
U
X
fOUT
EXTCON.FOSS
EXTCON.FOTL
Reload Counter
CCU_EXTCLK_Counter.vsd
Figure 6-14 Programmable Frequency Output Generation
Output fOUT always provides complete output periods:
•
•
When fOUT is started (EXTCON.FOEN is set), counter FOCNT is loaded from
EXTCON.FORV
When the output clock generation is stopped (EXTCON.FOEN is cleared), counter
FOCNT is stopped when fOUT has reached (or is) ’0’.
Register EXTCON provides control over the output generation (frequency, waveform,
activation) as well as holds all status information (EXTCON.FOTL).
Note: The output (for EXTCON.FOSS= 1) is high for the duration of one fSYS cycle for all
reload values EXTCON.FORV > 0. For EXTCON.FORV = 0, the output
corresponds to fSYS.
User’s Manual
SCU, V1.1
6-17
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
6.1.6
CGU Registers
6.1.6.1
Wake-up Clock Register
This register controls the setting of the Wake-Up clock, OSC_WU.
WUOSCCON
Wake-up OSC Control Register ESFR (F1AEH/D7H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
0
DIS
PWSEL
FREQSEL
r
rw
rw
rw
Field
Bits
Type
Description
FREQSEL
[1:0]
rw
Clock Frequency Selection
The values for the different settings are listed in the
data sheet.
Note: This value should only be changed when the
wake-up clock is not used as source for the
system clock.
PWSEL
[3:2]
rw
Power Consumption Selection
The values for the different settings are listed in the
data sheet.
Note: This value should only be changed when the
wake-up clock is not used as source for the
system clock.
DIS
4
rw
Clock Disable
0B
The clock is enabled
1B
The clock is disabled
0
[15:5]
r
Reserved
Read as 0; should be written with 0.
6.1.6.2
High Precision Oscillator Register
This register controls the setting of the High-Precision Oscillator, OSC_HP.
User’s Manual
SCU, V1.1
6-18
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
HPOSCCON
High Precision OSC Control RegisterESFR (F1B4H/DAH)
15
14
13
0
r
12
11
10
EMFI
OSC OSC
NDIS
2L0 2L1
EN
rh
rh
rw
9
8
7
6
5
Reset Value: 053CH
4
EM
SHB X1D
CLK
X1D GAINSEL
Y
EN
EN
rw
rw
rw
rw
rh
3
2
MODE
rw
1
0
OSC
PLL
WDT
V
RST
w
rh
Field
Bits
Type
Description
PLLV
0
rh
Oscillator for PLL Valid Status Bit
This bit indicates whether the frequency output of
OSC_HP a limit or not. The limit is defined in the data
sheet.
This is checked by the Oscillator Watchdog of the
PLL.
0B
The OSC_HP frequency is not usable
1B
The OSC_HP frequency is usable
For more information see Chapter 6.1.3.3.
OSCWDTRST 1
w
Oscillator Watchdog Reset
0B
The Oscillator Watchdog of the PLL is not reset
and remains active
1B
The Oscillator Watchdog of the PLL is reset
and restarted
MODE
rw
Oscillator Mode
This bit field controls the operating mode and the
power-save options.
00B External Crystal Mode/External Input Clock
Mode. Power-Saving Mode is not entered.
01B OSC_HP disabled, Power-Saving Mode is not
entered.
10B External Input Clock Mode, Power-Saving
Mode is entered.
11B OSC_HP is disabled, Power-Saving Mode is
entered.
User’s Manual
SCU, V1.1
[3:2]
6-19
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
GAINSEL
[5:4]
rh
Oscillator Gain Selection
00B Gain configured for 4 to 8 MHz frequency
range
01B Gain configured for 4 to 16 MHz frequency
range
10B Gain configured for 4 to 20 MHz frequency
range
11B Gain configured for 4 to 25 MHz frequency
range
Values for the different settings are listed in the data
sheet.
X1D
6
rh
XTAL1 Data Value
This bit monitors the inverted value (level) of pin
XTAL1. If XTAL1 is not used as clock input, it can be
used as general purpose input (GPI) pin.
This bit is only updated if X1DEN is set.
X1DEN
7
rw
XTAL1 Data Enable
Bit X1D is not updated
0B
1B
Bit X1D reflects inverted level of XTAL1
SHBY
8
rw
Shaper Bypass
The shaper modulates an input to fit to the requested
shape. This is defined in the data sheet. If the input
has already the correct shape the shaper can be
bypassed.
0B
The shaper is not bypassed
1B
The shaper is bypassed
EMCLKEN
9
rw
OSCWDT Emergency System Clock Source
Select Enable
This bit defines whether the master clock multiplexer
(MCM) should be controlled by bit field
SYSCON0.EMCLKSEL in an OSCWDT emergency
case.
0B
MCM controlled by SYSCON0.CLKSEL
1B
MCM controlled by SYSCON0.EMCLKSEL in
an OSCWDT emergency case
Note: Bit SYSCON0.EMCLKSELEN has to be set in
order to enable use of SYSCON0.EMCLKSEL
User’s Manual
SCU, V1.1
6-20
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
EMFINDISEN
10
rw
Emergency Input Clock Disconnect Enable
This bit defines whether bit PLLSTAT.FINDIS is set
in an emergency case.
No update of PLLSTAT.FINDIS
0B
1B
PLLSTAT.FINDIS is set in an OSCWDT
emergency case
OSC2L1
11
rh
OSCWDT Reached Status
OSCWDT did not detect frequency below limit.
0B
1B
OSCWDT detected an input frequency below
the limit.
Note: Bit OSC2L1 can be cleared by setting bit
STATCLR1.OSC2L1CLR.
OSC2L0
12
rh
OSCWDT Left Status
OSCWDT did not detect frequency above limit.
0B
1B
OSCWDT detected an input frequency above
the limit.
Note: Bit OSC2L0 can be cleared by setting bit
STATCLR1.OSC2L0CLR.
0
[15:13] r
6.1.6.3
Reserved
Read as 0; should be written with 0.
PLL Clock Register
This register controls the settings of the internal PLL clock, OSC_PLL.
PLLOSCCON
PLL OSC Configuration RegisterESFR (F1B6H/DBH)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
0
OSC
PD
r
rw
rw
Field
Bits
Type
Description
OSCPD
0
rw
Internal Clock IOSC Power Saving Mode
0B
IOSC is active
1B
IOSC is no longer powered
User’s Manual
SCU, V1.1
0
6-21
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
0
[9:1]
rw
Reserved
Do not change the content of this bit field.
0
[15:10] r
6.1.6.4
Reserved
Read as 0; should be written with 0.
PLL Registers
These registers control the settings of the PLL.
PLLSTAT
PLL Status Register
15
14
13
0
r
12
ESFR (F0BCH/5EH)
11
10
9
REG
VCO VCO FIN
STA
L1
L0 DIS
T
rh
rh
rh
rh
8
7
0
K1
RDY
rh
rh
6
Reset Value: 0000H
5
4
0
rh
rh
rh
3
2
1
0
VCO OSC PWD VCO
LOC SEL STA BY
K
ST
T
ST
rh
rh
rh
rh
Field
Bits
Type
Description
VCOBYST
0
rh
VCO Bypass Status
0B
Prescaler Mode is entered
1B
Free-Running / Normal Mode is entered
PWDSTAT
1
rh
PLL Power-saving Mode Status
0B
PLL Power-saving Mode is inactive
1B
PLL Power-saving Mode is active
OSCSELST
2
rh
PLL Input Selection Status
0B
XTAL1/OSC_HP is used as clock source for
the VCO part
1B
Input clock is IOSC output
User’s Manual
SCU, V1.1
6-22
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
VCOLOCK
3
rh
PLL VCO Lock Status
0B
VCO not locked to target frequency. The
frequency difference of fP and fN is greater than
allowed.
VCO locked to target frequency. The
1B
frequency difference of fP and fN is small
enough to enable a stable VCO operation.
Note: In case of a loss of VCO lock, fVCO reaches the
upper boundary of the selected VCO band if
the reference clock input is greater than
expected. If the reference clock input is lower
than expected, fVCO reaches the lower
boundary of the selected VCO band.
K1RDY
7
rh
K1-Divider Ready Status
0B
A new K1DIV value has been written, but is not
used yet
1B
The K1-Divider operates with the value defined
in PLLCON2.K1DIV
This bit is cleared on a write to PLLCON2.K1DIV.
FINDIS
9
rh
Input Clock Disconnect Select Status
0B
VCO input clock connected
VCO input clock disconnected
1B
Note: FINDIS can be set
STATCLR1.SETFINDIS.
Note: FINDIS can be cleared
STATCLR1.CLRFINDIS.
VCOL0
10
rh
11
rh
bit
by
setting
bit
by
setting
bit
setting
bit
VCO Lock Detection Reached Status
0B
VCO lock was not acquired
1B
VCO lock was acquired
Note: VCOL1 can be cleared
STATCLR1.VCOL1CLR.
User’s Manual
SCU, V1.1
setting
VCO Lock Detection Lost Status
0B
VCO lock was not lost
1B
VCO lock was lost
Note: VCOL0 can be cleared
STATCLR1.VCPL0CLR.
VCOL1
by
6-23
by
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
REGSTAT
12
rh
PLL Power Regulator Status
The PLL has a separate internal power regulator,
providing the power supply of the PLL.
0B
PLL is not powered (no operation possible)
1B
PLL is powered (operation possible)
Note: REGSTAT can be set
PLLCON0.REGENSET.
by
setting
bit
Note: REGSTAT can be cleared by setting bit
PLLCON0.REGENCLR.
0
[6:4], 8 rh
Reserved
Should be written with 0.
0
[15:13] r
Reserved
Read as 0; should be written with 0.
PLLCON0
PLL Configuration 0 Register
15
14
13
12
11
10
ESFR (F1B8H/DCH)
9
8
7
6
0
0
NDIV
0
rw
r
rw
r
Reset Value: 1302H
5
4
REG REG
EN EN
SET CLR
w
w
3
0
r
2
1
0
VCO VCO VCO
SEL PWD BY
rw
rw
rw
Field
Bits
Type
Description
VCOBY
0
rw
VCO Bypass
0B
Normal operation, VCO is not bypassed
1B
Prescaler Mode; VCO is bypassed
VCOPWD
1
rw
VCO Power Saving Mode
0B
VCO is active
1B
VCO is inactive in power saving mode and can
not be used
VCOSEL
2
rw
VCO Range Select
See the data sheet.
REGENCLR
4
w
PLL Power Regulator Enable Clear
0B
PLL power regulator is not affected
1B
PLL is not powered (no operation possible)
User’s Manual
SCU, V1.1
6-24
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
REGENSET
5
w
PLL Power Regulator Enable Set
0B
PLL power regulator is not affected
1B
PLL is powered (operation possible)
NDIV
[13:8]
rw
N-Divider Value
The resulting factor N for the N-Divider is <NDIV>+1.
Only values between N = 16 and N = 40 are allowed.
Stable operation is not guaranteed outside of this
range.
0
15
rw
Reserved
Should be written with 0.
0
3,
[7:6],
14
r
Reserved
Read as 0; should be written with 0.
PLLCON1
PLL Configuration 1 Register ESFR (F1BAH/DDH)
15
14
13
12
11
10
9
8
7
0
0
PDIV
0
rw
r
rw
r
Reset Value: 000AH
6
5
EMFI
NDIS
EN
rw
EM
CLK
EN
rw
4
0
r
3
2
1
0
AOS
RES OSC PLL
CSE
LD SEL PWD
L
rw
w
rw
rw
Field
Bits
Type
Description
PLLPWD
0
rw
PLL Power Saving Mode
0B
Normal Mode
1B
Complete PLL block is inactive in power saving
mode and can not be used. Only the Bypass
Mode is active if previously selected.
OSCSEL
1
rw
Clock Input Selection
0B
PLL input clock is OSC_HP output
1B
PLL input clock is IOSC output
RESLD
2
w
Restart VCO Lock Detection
Setting bit RESLD will reset bit PLLSTAT.VCOLOCK
and restart the VCO lock detection.
Reading this bit returns always a zero.
User’s Manual
SCU, V1.1
6-25
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
AOSCSEL
3
rw
Asynchronous Clock Input Selection
0B
Configuration is controlled via bit OSCSEL
1B
PLL internal clock IOSC is selected
asynchronously
EMCLKEN
5
rw
VCOLCK Emergency System Clock Source
Select Enable
EMCLKEN defines whether the master clock
multiplexer (MCM) should be controlled by bit field
SYSCON0.EMCLKSEL in a VCOLCK emergency
case.
MCM controlled by SYSCON0.CLKSEL
0B
1B
MCM controlled by SYSCON0.EMCLKSEL in
a VCOLCK emergency case
Note: Bit SYSCON0.EMCLKSELEN has to be set in
order to enable use of SYSCON0.EMCLKSEL
EMFINDISEN
6
rw
Emergency Input Clock Disconnect Enable
EMFINDISEN defines whether bit PLLSTAT.FINDIS
is set in a VCOLCK emergency case.
0B
No update of PLLSTAT.FINDIS
PLLSTAT.FINDIS is set in a VCOLCK
1B
emergency case
PDIV
[11:8]
rw
P-Divider Value
The resulting factor P for the P-Divider is <PDIV>+1
0
15
rw
Reserved
Should be written with 0.
0
4, 7,
r
[14:12]
Reserved
Read as 0; should be written with 0.
PLLCON2
PLL Configuration 2 Register ESFR (F1BCH/DEH)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0001H
5
4
0
0
K1DIV
rw
r
rw
User’s Manual
SCU, V1.1
6-26
3
2
1
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
K1DIV
[9:0]
rw
K1-Divider Value
The resulting factor K1 for the K1-Divider is
<K1DIV>+1
K1ACK
15
rw
K1-Divider Ready Acknowledge
Setting this bit provides the acknowledge to
PLLSTAT.K1RDY.
0
[14:10] r
Reserved
Read as 0; should be written with 0.
PLLCON3
PLL Configuration 3 Register
15
14
13
12
11
10
ESFR (F1BEH/DFH)
9
8
7
6
Reset Value: 00CBH
5
4
3
2
1
0
0
K2DIV
rw
r
rw
Field
Bits
Type
Description
K2DIV
[9:0]
rw
K2-Divider Value
The resulting factor K2 for the K2-Divider is
<K2DIV>+1
0
15
rw
Reserved
Should be written with 0.
0
[14:10] r
6.1.6.5
0
Reserved
Read as 0; should be written with 0.
System Clock Control Registers
These registers control the system level clock behavior.
User’s Manual
SCU, V1.1
6-27
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
SYSCON0
System Control 0 Register
15
14
SEL
STA
T
0
rh
r
13
12
11
SFR (FF4AH/A5H)
10
EMS EMS
VCO OSC
rh
9
8
7
EM
CLK
SEL
EN
rw
0
rh
6
r
Reset Value: 0000H
5
4
3
2
1
0
0
EM
CLKSEL
0
CLKSEL
r
rw
r
rwh
Field
Bits
Type
Description
CLKSEL
[1:0]
rw
System Clock Select
CLKSEL selects the clock source used as system
clock fSYS for the system operation.
00B The WUT clock output fWU is used
01B The direct output from OSC_HP is used fOSC
10B The PLL clock output fPLL is used
11B Direct Input clock DIRIN fDIR is used
EMCLKSEL
[4:3]
rw
Emergency Clock Select
EMCLKSEL defines the clock source used as system
clock fSYS for the system operation in case of an
OSCWDT or VCOLCK emergency event.
00B The WUT clock output fWU is used
01B The direct output from OSC_HP is used fOSC
10B The PLL clock output fPLL is used
11B Direct Input clock DIRIN fDIR is used
EMCLKSELE
N
6
rw
Emergency Clock Select Enable
EMCLKSELEN enables the automatic asynchronous
switch to the emergency clock In case of an
OSCWDT or VCOLCK emergency event.
0B
Emergency clock switch is disabled
1B
Emergency clock switch is enabled
EMSOSC
12
rh
OSCWDT Emergency Event Source Status
0B
No OSCWDT emergency event occurred since
last clear of EMSOSC
1B
An OSCWDT emergency event has occurred
Note: This bit is only set if EMCLKSELEN is set.
User’s Manual
SCU, V1.1
6-28
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
EMSVCO
13
rh
VCOLCK Emergency Event Source Status
0B
No VCOLCK emergency event occurred since
last clear of EMSVCO
1B
A VCOLCK emergency event has occurred
Note: This bit is only set if EMCLKSELEN is set.
SELSTAT
15
rh
Clock Select Status
0B
Standard clock selection (CLKSEL) is active
1B
Emergency clock selection (EMCLKSEL) is
active
0
2, 5,
[11:7],
14
r
Reserved
Read as 0; should be written with 0.
STATCLR0
Status Clear 0 Register
15
14
0
13
12
ESFR (F0E0H/70H)
11
10
9
8
7
EMC EMC
VCO OSC
r
w
Reset Value: 0000H
6
5
4
3
1
0
0
w
r
Field
Bits
Type
Description
EMCOSC
12
w
EMSOSC Clear Trigger
0B
No action
Clear bit SYSCON0.EMSOSC
1B
EMCVCO
13
w
EMSVCO Clear Trigger
0B
No action
1B
Clear bit SYSCON0.EMSVCO
0
[11:0], r
[15:14]
User’s Manual
SCU, V1.1
2
Reserved
Read as 0; should be written with 0.
6-29
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
STATCLR1
Status Clear 1 Register
15
14
13
12
ESFR (F0E2H/71H)
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
CLR SET OSC OSC VCO VCO
FIN FIN 2L0 2L1 L1
L0
DIS DIS CLR CLR CLR CLR
w
w
w
w
w
w
0
r
Field
Bits
Type
Description
VCOL0CLR
0
w
VCOL0 Clear Trigger
No action
0B
1B
Bit PLLSTAT.VCOL0 is cleared
VCOL1CLR
1
w
VCOL1 Clear Trigger
0B
No action
Bit PLLSTAT.VCOL1 is cleared
1B
OSC2L1CLR
2
w
OSC2L1 Clear Trigger
0B
No action
1B
Bits HPOSCCON.OSC2L1 is cleared
OSC2L0CLR
3
w
OSC2L0 Clear Trigger
0B
No action
1B
Bit HPOSCCON.OSC2L0 is cleared
SETFINDIS
4
w
Set Status Bit PLLSTAT.FINDIS
0B
No action
1B
Set bit PLLSTAT.FINDIS. The VCO input clock
becomes disconnected (open).
Software should not set SETFINDIS if bit
SYSCON0.SELSTAT is set.
CLRFINDIS
5
w
Clear Status Bit PLLSTAT.FINDIS
0B
No action
1B
Clear bit PLLSTAT.FINDIS. The VCO input
clock becomes connected to the P-Divider.
Software should not set CLRFINDIS if bit
SYSCON0.SELSTAT is set.
0
[15:6]
r
Reserved
Read as 0; should be written with 0.
User’s Manual
SCU, V1.1
6-30
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
RTCCLKCON
RTC Clock Control Register
15
14
13
12
11
10
SFR (FF4EH/A7H)
9
8
7
6
Reset Value: 0006H
5
4
3
2
1
0
RTC RTCCLKS
CM
EL
0
r
rw
rw
Field
Bits
Type
Description
RTCCLKSEL
[1:0]
rw
RTC Clock Select
RTCCLKSEL defines the clock source used as
asynchronous clock for the RTC, when the RTC runs
in Asynchronous Mode.
00B The PLL clock output fPLL is used
01B The direct output from OSC_HP is used fOSC
10B The WUT clock output fWU is used
11B The input from port pin DRTC is used
RTCCM
2
rw
RTC Clocking Mode
0B
Asynchronous Mode:
The RTC operates with fRTC. No register
access is possible.
1B
Synchronous Mode:
The RTC operates with fSYS. Registers can be
read and written.
0
[15:3]
r
Reserved
Read as 0; should be written with 0.
6.1.6.6
External Clock Control Register
This register controls the settings for the external clock for pins 2.8 and 7.1.
EXTCON
External Clock Control Register SFR (FF5EH/AFH)
15
14
FO
EN
FO
SS
rw
rw
13
User’s Manual
SCU, V1.1
12
11
10
9
8
Reset Value: 0000H
7
6
5
FORV
0
FO
TL
0
SEL
EN
rw
r
rh
r
rw
rw
6-31
4
3
2
1
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
EN
0
rw
External Clock Enable
0B
No external clock is provided
1B
The configured external clock is provided
SEL
[4:1]
rw
External Clock Select
0000BfSYS is selected for the external clock
0001BfOUT is selected for the external clock
0010BfPLL is selected for the external clock
0011BfOSC is selected for the external clock
0100BfWU is selected for the external clock
0101BReserved, do not use this combination
0110BReserved, do not use this combination
0111BReserved, do not use this combination
1000BfRTC is selected for the external clock
1001BReserved, do not use this combination
…
1111BReserved, do not use this combination
FOTL
6
rh
Frequency Output Toggle Latch
FOTL is toggled upon each underflow of FOCNT.
FORV
[13:8]
rw
Frequency Output Reload Value
FORV is copied to FOCNT upon each underflow of
FOCNT.
FOSS
14
rw
Frequency Output Signal Select
0B
Output of the toggle latch selected for fOUT
1B
Output of the reload counter selected for fOUT.
The duty cycle depends on FORV
FOEN
15
rw
Frequency Output Enable
0B
Frequency output generation stops when fOUT
is/becomes low
1B
FOCNT is running, fOUT is gated to the pin.
First reload after 0-to-1 transition.
0
5, 7
r
Reserved
Read as 0; should be written with 0.
User’s Manual
SCU, V1.1
6-32
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.2
System Control Unit (SCU)
Reset Operation
All resets are generated by the Reset Control Block. It handles the control of the reset
triggers as well as the length of a reset and the reset timing. A reset leads the system,
or a part of the system depending on the reset, to a initialization into a defined state.
6.2.1
Reset Architecture
The XC2000 contains a very sophisticated reset architecture to offer the greatest amount
of flexibility for the support of different applications. The reset architecture supports the
different power domains:
If a power domain is deactivated all resets of the deactivated level and all resets of all
lower power domains are asserted.
Additionally the different types of resets supported for the complete system.
6.2.1.1
Reset Types
The following summery shows the different reset types.
•
•
•
•
•
Power-on Reset:
This reset leads to a initialization into a defined state of the complete system. This
reset is only generated on a real power-on event and can not be generated by any
no power related event.
System Reset:
This reset leads to a initialization into a defined state of the complete system without
the following parts: reset control, power control, clock control, stand-by RAM.
Debug Reset:
This reset leads to a initialization into a defined state of the complete debug system.
Internal Application Reset:
This reset leads to a initialization into a defined state of the complete application
system with the following parts: all peripherals (without the Ports and RTC), the CPU
and partially the SCU and the flash memory.
Application Reset:
This reset leads to a initialization into a defined state of the complete application
system with the following parts: all peripherals (without the RTC), the CPU and
partially the SCU and the flash memory.
6.2.2
General Reset Operation
A reset is generated if an enabled reset request trigger is asserted. Most reset request
trigger can configured for the reset type that should initiated by it. No action (disabled) is
one possible configuration and can be selected for a reset request trigger by setting the
adequate bit field in a Reset Configuration Register to 00B. The debug reset can only be
requested by dedicated reset request triggers and can not be selected via a Reset
User’s Manual
SCU, V1.1
6-33
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Configuration Register. For more information see also registers RSTCON0 and
RSTCON1.
The duration of a reset is defined by two independent counters. One counter for the
system and application reset types and one separate counter for the debug reset. A
separate counter for the debug reset was implemented to allow a non-intrusive
adaptation of the reset length to the debugger needs without modification of the
application setting.
6.2.2.1
Reset Counters (RSTCNTA and RSTCNTD)
RSTCNTA is the reset counter that controls the reset length for all application relevant
resets (system reset, internal application reset, and application reset). RSTCNTD is the
reset counter that controls the reset length for the debug reset.
The reset counters can be used for the following purposes:
•
•
First to control the length of the internal resets.
Second to configure the reset length in a way that the reset outputs via the ESRx pins
match with the reset input requirements of external blocks connected with the reset
outputs.
A reset counter RSTCNT is an 8-bit counter counting down from the reload value defined
by RSTCNTCON.RELx (x = A or D). The counter is started by the reset control block as
soon as a reset request trigger condition becomes active (for more information see
Table 6-4 and Table 6-5). Whether the counter has to be started or not depends on the
reset request trigger and whether the counter is already active or not. In case of that the
counter is inactive, not counting down, it is always started. While the counter is already
active it depends on the reset typ of the new reset request trigger that was asserted anew
if the counter is restarted or not. This behavior is summarized in Table 6-4 and
Table 6-5.
Table 6-4
Restart of RSTCNTA
Reset Active
New Reset
Power-On
System
Reset
Debug
Reset
Internal
Application
Application
Reset
Reset
System
Reset
Restart
No Restart
No Restart
No Restart
No Restart
Internal
Application
Reset
Restart
Restart
No Restart
No Restart
No Restart
Application
Reset
Restart
Restart
No Restart
Restart
No Restart
User’s Manual
SCU, V1.1
6-34
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 6-5
System Control Unit (SCU)
Restart of RSTCNTD
Reset Active
New Reset
Power-On
Debug Reset Restart
System
Reset
No Restart
Debug
Reset
No Restart
Internal
Application
Application
Reset
Reset
No Restart
No Restart
RSTCNTx ensures that a reset request trigger generates a reset of a minimum length
which is configurable. But if a reset request trigger is asserted continuously longer than
the counter needs for the complete count-down process the reset cannot be deasserted
before the reset request trigger is also deasserted. Anyway the counter is not started
again, instead the reset control block keeps the reset asserted until the reset request
trigger is deasserted.
6.2.2.2
De-assertion of a Reset
The reset of a dedicated typ is de-asserted when all of the following conditions are
fulfilled.
•
•
The reset counter has been expired (reached zero).
No reset request trigger that is configured to generate a reset of the dedicated typ is
currently asserted.
6.2.3
Coupling of Reset Types
The different reset types are coupled for a better usage:
•
•
•
The assertion of a Power-on Reset automatically asserts also the following reset
types:
– Debug Reset
– System Reset
– Internal Application Reset
– Application Reset
The assertion of a System Reset automatically asserts also the following reset types:
– Internal Application Reset
– Application Reset
The assertion of a Internal Application Reset automatically asserts also the following
reset type:
– Application Reset
User’s Manual
SCU, V1.1
6-35
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.2.4
System Control Unit (SCU)
Debug Reset Assertion
Unlike the other reset types a Debug Reset can only be asserted if the following two
conditions are valid:
•
•
A reset request trigger is asserted that request a debug reset
An Application Reset is active in the system
6.2.5
Example1:
Reset request trigger A is asserted and leads to an Application Reset. If the reset request
trigger is de-asserted before RSTCNTA reached zero the Application Reset is deasserted when RSTCNTA reaches zero. If the reset request trigger is de-asserted after
RSTCNTA reached zero the Application Reset is de-asserted when the reset request
trigger is de-asserted.
6.2.6
Example2:
Reset request trigger A is asserted and leads to an Application Reset. Reset request
trigger A is de-asserted before RSTCNTA reached zero. Reset request trigger B is
asserted after reset request trigger A but before RSTCNTA reaches zero. Reset request
trigger B is also configured to result in a Application Reset. If the reset request trigger B
is de-asserted before RSTCNTA reached zero the Application Reset is de-asserted
when RSTCNTA reaches zero. If the reset request trigger B is de-asserted after
RSTCNTA reached zero the Application Reset is de-asserted when the reset request
trigger B is de-asserted.
6.2.7
Example3:
Reset request trigger A is asserted and leads to a System Reset. Reset request trigger
A is de-asserted before RSTCNTA reached zero. Reset request trigger B is asserted
after reset request trigger A but before RSTCNTA reaches zero. Reset request trigger B
is configured to result in a Internal Application Reset. If the reset request trigger B is deasserted before RSTCNTA reached zero the System, Internal Application, and
Application Resets are de-asserted when RSTCNTA reaches zero. If the reset request
trigger B is de-asserted after RSTCNTA reached zero the Internal Application and
Application Resets are de-asserted when the reset request trigger B is de-asserted.
6.2.8
Reset Request Trigger Sources
The following overview summarizes the different reset request trigger sources within the
system.
User’s Manual
SCU, V1.1
6-36
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Power-On Reset Pin PORST
The PORST input pin requests asynchronously a Power-on Reset by driving the PORST
pin low.
Supply Watchdog (SWD)
If the power supply for I/O domain doesn’t reach the value required for proper
functionality, a non-synchronized reset request trigger is generated if the SWD reset
generation is enabled. This ensures a reproducible behavior in the case of power-fail.
This can also be used to restart the system without the usage of the PORST pin. As long
as the I/O power domain does not get the required voltage level the system is held in the
reset.
Core Power Validation (PVC_M and PVC_1)
If the core power supply doesn’t reach the value required for proper functionality of main
power domain (PVC_M), a reset request trigger can be forwarded to the system. The
generation of a Power-on Reset is configured by bit PVCMCON0.L1RSTEN = 1B. If the
bit PVCMCON0.L1RSTEN = 1B a request trigger is asserted for PVC_M1 upon a level
check match. If the bit PVCMCON0.L2RSTEN = 1B a request trigger is asserted for
PVC_M2 upon a level check match.
If the core power supply doesn’t reach the value required for proper functionality of
application power domain (PVC_1), a reset request trigger can be forwarded to the
system. The generation of a Power-on Reset for (Application Power Domain only) is
configured by bit PVC1CON0.L1RSTEN = 1B. If the bit PVC1CON0.L1RSTEN = 1B a
request trigger is asserted for PVC_11 upon a level check match. If the bit
PVC1CON0.L2RSTEN = 1B a request trigger is asserted for PVC_12 upon a level check
match.
For more information about the Power Validation Circuit see Chapter 6.5.2.
ESR0/ESR1/ESR2
An ESR0/ESR1/ESR2 reset request trigger leads to a configurable reset. The type of
reset can be configured via RSTCON1.ESRx.
The pins ESR0/ESR1/ESR2 can serve as an external reset input as well as a reset
output (open drain) for Internal Application and Application Resets. For the ESR1 and
ESR2 additionally several GPIO pad triggers that can be enabled additionally via register
ESREXCONx (x = 1 or 2) interfere with the ESR pin function. GPIO and ESR pin triggers
can be enabled/disabled individually and are combined for the reset trigger generation.
Note: The reset output is only asserted for the duration the reset counter RSTCNTA is
active. During a possible reset extension the reset output is not longer asserted.
User’s Manual
SCU, V1.1
6-37
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
If the pin ESR0/ESR1/ESR2 is enabled as reset output and the input level is low while
the output stage is disabled (indicating that it is still driven low externally), the reset
circuitry holds the chip in reset until a high level is detected on ESR0/ESR1/ESR2. The
internal output stage drives a low level during reset only while RSTCNTA is active. It
deactivates the output stage when the time defined by RSTCNTCON.RELA has passed.
Software
A software reset request trigger leads to a configurable reset. The type of reset can be
configured via RSTCON0.SW.
Watchdog Timer
A WDT reset request trigger leads to a configurable reset. The type of reset can be
configured via RSTCON1.WDT. A WDT reset is requested on a WDT overflow event.
For more information see Chapter 6.8.
CPU
A CPU reset request trigger leads to a configurable reset. The type of reset can be
configured via RSTCON0.CPU. A CPU reset is requested when instruction SRST is
executed.
Memory Parity
A MP reset request trigger leads to a configurable reset. The type of reset can be
configured via RSTCON1.MP. For more information see Section 3.12.
OCDS Block
The OCDS block has several options to request different reset types:
1. A Debug Reset either via the OCDS reset function or via bit CBS_OJCONF.RSTCL1
AND CBS_OJCONF.RSTCL3
2. A System Reset via bit CBS_OJCONF.RSTCL0
3. An Internal Application Reset via bit CBS_OJCONF.RSTCL2
4. An Application Reset via bit CBS_OJCONF.RSTCL3
User’s Manual
SCU, V1.1
6-38
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.2.8.1
System Control Unit (SCU)
Reset Sources Overview
The connection of the reset sources and the activated reset types are shown in
Table 6-6.
Table 6-6
Effects of Reset Types for Reset Activation
Reset Request
Trigger
Application
Reset
Internal
Application
Reset
Debug Reset
System Reset
PORST
Activated
Activated
Activated
Activated
SWD
Activated
Activated
Activated
Activated
PVC_M1
Activated
Activated
Activated
Activated
PVC_M2
Activated
Activated
Activated
Activated
PVC_11
Activated
Activated
Activated
Activated
PVC_12
Activated
Activated
Activated
Activated
ESR0
Configurable
Configurable
Not Activated
Configurable
ESR1
Configurable
Configurable
Not Activated
Configurable
ESR2
Configurable
Configurable
Not Activated
Configurable
WDT
Configurable
Configurable
Not Activated
Configurable
SW
Configurable
Configurable
Not Activated
Configurable
CPU
Configurable
Configurable
Not Activated
Configurable
MP
Configurable
Configurable
Not Activated
Configurable
OCDS Reset
Not Activated
Not Activated
Activated1)
Not Activated
CBS_OJCONF.RS Activated
TCL0
Activated
Not Activated
Activated
CBS_OJCONF.RS Not Activated
TCL1
Not Activated
Activated1)
Not Activated
CBS_OJCONF.RS Activated
TCL2
Activated
Not Activated
Not Activated
CBS_OJCONF.RS Activated
TCL3
Not Activated
Not Activated
Not Activated
1)
Only if an application reset is active or is requested in parallel.
User’s Manual
SCU, V1.1
6-39
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.2.9
System Control Unit (SCU)
Module Reset Behavior
Table 6-7 lists how the various functions of the XC2000 are affected through a reset
depending on the reset type. A “X” means that this block has at least some register/bits
that are affected by this reset type.
Table 6-7
Effect of Reset on Device Functions
Module / Function
Application
Reset
Internal
Application
Reset
Debug Reset
System
Reset
CPU Core
X
X
X
X
Peripherals
(except
SCU and
RTC)
X
X
X
X
SCU
X
Not affected
Not affected
X
RTC
Not affected
Not affected
X
X
DPRAM
Not affected,
reliable
Not affected,
reliable
Not affected,
reliable
Affected,
un-reliable
PSRAM
Not affected,
reliable
Not affected,
reliable
Not affected,
reliable
Affected,
un-reliable
DSRAM
Not affected,
reliable
Not affected,
reliable
Not affected,
reliable
Affected,
un-reliable
Flash
Memory
X
X
2)
Not affected,
reliable
X
2)
JTAG
Interface
Not affected
Not affected
Not affected
Not affected
OCDS
Not affected
Not affected
X
X
Oscillators,
PLL
Not affected
Not affected
Not affected
X
Port Pins
Not affected
X
Not affected
X
Pins ESRx
Not affected
X
Not affected
X
On-chip
Static
RAMs1)
1)
Reliable here means that also the redundancy is not affected by the reset.
2)
Parts of the flash memory block are only reset by a System Reset. For more detail see the flash chapter.
User’s Manual
SCU, V1.1
6-40
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.2.10
System Control Unit (SCU)
Reset Controller Registers
6.2.10.1 Status Registers
These registers contain the status of the reset request trigger for the last reset.
RSTSTAT0
Reset Status 0 Register
15
14
13
12
ESFR (F0B2H/59H)
11
10
9
8
7
Reset Value: 0000H
6
5
SW
CPU
0
rh
rh
r
3
2
1
0
Field
Bits
CPU
[13:12] rh
CPU Reset Type Status
00B The CPU reset trigger was not relevant for the
last reset
01B The CPU reset trigger was relevant for the last
reset. System, Internal Application, and
Application Resets where generated.
10B The CPU reset trigger was relevant for the last
reset. Internal Application and Application
Resets where generated.
11B The CPU reset trigger was relevant for the last
reset. Application Reset was generated.
SW
[15:14] rh
Software Reset Type Status
00B The Software reset trigger was not relevant for
the last reset
01B The Software reset trigger was relevant for the
last reset. System, Internal Application, and
Application Resets where generated.
10B The Software reset trigger was relevant for the
last reset. Internal Application and Application
Resets where generated.
11B The Software reset trigger was relevant for the
last reset. Application Reset was generated.
0
[11:0]
Reserved
Read as 0; should be written with 0.
User’s Manual
SCU, V1.1
Type
4
r
Description
6-41
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
RSTSTAT1
Reset Status 1 Register
15
14
13
12
ESFR (F0B4H/5AH)
11
10
9
8
7
6
Reset Value: F000H
5
4
3
2
1
0
ST1
STM
0
MP
WDT
ESR2
ESR1
ESR0
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type
Description
ESR0
[1:0]
rh
ESR0 Trigger Status
00B The Software reset trigger was not relevant for
the last reset
01B The Software reset trigger was relevant for the
last reset. System, Internal Application, and
Application Resets where generated.
10B The Software reset trigger was relevant for the
last reset. Internal Application and Application
Resets where generated.
11B The Software reset trigger was relevant for the
last reset. Application Reset was generated.
ESR1
[3:2]
rh
ESR1 Reset Typ Status
00B The ESR1 reset trigger was not relevant for the
last reset
01B The ESR1 reset trigger was relevant for the
last reset. System, Internal Application, and
Application Resets where generated.
10B The ESR1 reset trigger was relevant for the
last reset. Internal Application, and Application
Resets where generated.
11B The ESR1 reset trigger was relevant for the
last reset. Application Reset was generated.
User’s Manual
SCU, V1.1
6-42
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
ESR2
[5:4]
rh
ESR2 Reset Typ Status
00B The ESR2 reset trigger was not relevant for the
last reset
01B The ESR2 reset trigger was relevant for the
last reset. System, Internal Application, and
Application Resets where generated.
10B The ESR2 reset trigger was relevant for the
last reset. Internal Application, and Application
Resets where generated.
11B The ESR2 reset trigger was relevant for the
last reset. Application Reset was generated.
WDT
[7:6]
rh
WDT Reset Typ Status
00B The WDT reset trigger was not relevant for the
last reset
01B The WDT reset trigger was relevant for the last
reset. System, Internal Application, and
Application Resets where generated.
10B The WDT reset trigger was relevant for the last
reset. Internal Application, and Application
Resets where generated.
11B The WDT reset trigger was relevant for the last
reset. Application Reset was generated.
MP
[9:8]
rh
MP Reset Typ Status
00B The MP reset trigger was not relevant for the
last reset
01B The MP reset trigger was relevant for the last
reset. System, Internal Application, and
Application Resets where generated.
10B The MP reset trigger was relevant for the last
reset. Internal Application, and Application
Resets where generated.
11B The MP reset trigger was relevant for the last
reset. Application Reset was generated.
User’s Manual
SCU, V1.1
6-43
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
STM
[13:12] rh
Power-on for DMP_M Reset Status
00B The power-on reset for DMP_M reset trigger
was not relevant for the last reset
01B The power-on reset for DMP_M reset trigger
was not relevant for the last reset
10B The power-on reset for DMP_M reset trigger
was not relevant for the last reset
11B The power-on reset for DMP_M reset trigger
was relevant for the last reset
ST1
[15:14] rh
Power-on for DMP_1 Reset Status
00B The power-on reset for DMP_1 reset trigger
was not relevant for the last reset
01B The power-on reset for DMP_1 reset trigger
was not relevant for the last reset
10B The power-on reset for DMP_1 reset trigger
was not relevant for the last reset
11B The power-on reset for DMP_1 reset trigger
was relevant for the last reset
0
[11:10] r
Reserved
Read as 0; should be written with 0.
RSTSTAT2
Reset Status 2 Register
15
14
13
12
0
r
User’s Manual
SCU, V1.1
11
Description
ESFR (F0B6H/5BH)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
OJCONF3 OJCONF2 OJCONF1 OJCONF0
rh
rh
6-44
rh
rh
0
DB
rh
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
DB
[1:0]
rh
Debug Reset Typ Status
00B The DB reset trigger was not relevant for the
last reset
01B The DB reset trigger was not relevant for the
last reset
10B The DB reset trigger was not relevant for the
last reset
11B The DB reset trigger was relevant for the last
reset
OJCONF0
[3:2]
rh
OJCONF0 Reset Typ Status
00B The OFCONF0 reset trigger was not relevant
for the last reset
01B The OFCONF0 reset trigger was relevant for
the last reset. System, Internal Application,
and Application Resets where generated.
10B The OFCONF0 reset trigger was not relevant
for the last reset
11B The OFCONF0 reset trigger was not relevant
for the last reset
OJCONF1
[5:4]
rh
OJCONF1 Reset Typ Status
00B The OFCONF1 reset trigger was not relevant
for the last reset
01B The OFCONF1 reset trigger was not relevant
for the last reset
10B The OFCONF1 reset trigger was not relevant
for the last reset
11B The OFCONF1 reset trigger was relevant for
the last reset. Debug Reset was generated.
OJCONF2
[7:6]
rh
OJCONF2 Reset Typ Status
00B The OFCONF2 reset trigger was not relevant
for the last reset
01B The OFCONF2 reset trigger was not relevant
for the last reset
10B The OFCONF2 reset trigger was relevant for
the last reset. Internal Application, and
Application Resets where generated.
11B The OFCONF2 reset trigger was not relevant
for the last reset
User’s Manual
SCU, V1.1
6-45
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
OJCONF3
[9:8]
rw
OJCONF3 Reset Typ Status
00B The OFCONF3 reset trigger was not relevant
for the last reset
01B The OFCONF3 reset trigger was not relevant
for the last reset
10B The OFCONF3 reset trigger was not relevant
for the last reset
11B The OFCONF3 reset trigger was relevant for
the last reset. Application Reset was
generated.
0
[15:10] r
Reserved
Read as 0; should be written with 0.
STSTAT
Start-up Status Register
15
14
13
12
11
ESFR (F1E0H/F0H)
10
9
8
7
6
Reset Value: 8000H
5
4
3
MODE
0
HWCFG
rh
r
rh
2
1
0
Field
Bits
Type
Description
HWCFG
[7:0]
rh
HW Configuration Setting
This bitfield indicates the currently selected Start-Up
Mode (please refer to Section 10.1)
MODE
15
rh
Mode
This bit indicates if the correct Mode is entered or not.
0B
Reserved, the correct Mode is not entered
1B
Normal Mode is selected
0
[14:8]
r
Reserved
read as 0; should be written with 0.
User’s Manual
SCU, V1.1
6-46
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
6.2.10.2 Configuration Registers
These registers allow the behavioral configuration for the various reset trigger sources.
RSTCON0
Reset Configuration 0 Register ESFR (F0B8H/5CH)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
SW
CPU
PVC12
PVC11
0
rw
rw
rw
rw
rw
2
1
0
Field
Bits
Type
Description
PVC11
[9:8]
rw
PVC_1 Check Level 1 Reset Type Selection
This bit field defines which reset types are generated
by a PVC_1 check level 1 reset request trigger.
00B No reset is generated
01B System, Internal Application, and Application
Resets are generated
10B Internal Application, and Application Resets
are generated
11B Application Reset is generated
PVC12
[11:10] rw
PVC_1 Check Level 2 Reset Type Selection
This bit field defines which reset types are generated
by a PVC_1 check level 2 reset request trigger.
00B No reset is generated
01B System, Internal Application, and Application
Resets are generated
10B Internal Application, and Application Resets
are generated
11B Application Reset is generated
CPU
[13:12] rw
CPU Reset Type Selection
This bit field defines which reset types are generated
by a CPU reset request trigger.
00B No reset is generated
01B System, Internal Application, and Application
Resets are generated
10B Internal Application, and Application Resets
are generated
11B Application Reset is generated
User’s Manual
SCU, V1.1
6-47
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
SW
[15:14] rw
Software Reset Type Selection
This bit field defines which reset types are generated
by a software reset request trigger.
00B No reset is generated
01B System, Internal Application, and Application
Resets are generated
10B Internal Application, and Application Resets
are generated
11B Application Reset is generated
0
[0:7]
Reserved
Should be written with 0.
rw
Description
RSTCON1
Reset Configuration 1 Register ESFR (F0BAH/5DH)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0002H
5
4
3
2
1
0
0
MP
WDT
ESR2
ESR1
ESR0
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
ESR0
[1:0]
rw
ESR0 Reset Type Selection
This bit field defines which reset types are generated
by a ESR0 reset request trigger.
00B No reset is generated
01B System, Internal Application, and Application
Resets are generated
10B Internal Application, and Application Resets
are generated
11B Application Reset is generated
User’s Manual
SCU, V1.1
6-48
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
ESR1
[3:2]
rw
ESR1 Reset Type Selection
This bit field defines which reset types are generated
by a ESR1 reset request trigger.
00B No reset is generated
01B System, Internal Application, and Application
Resets are generated
10B Internal Application, and Application Resets
are generated
11B Application Reset is generated
ESR2
[5:4]
rw
ESR2 Reset Type Selection
This bit field defines which reset types are generated
by a ESR2 reset request trigger.
00B No reset is generated
01B System, Internal Application, and Application
Resets are generated
10B Internal Application, and Application Resets
are generated
11B Application Reset is generated
WDT
[7:6]
rw
WDT Reset Type Selection
This bit field defines which reset types are generated
by a WDT reset request trigger.
00B No reset is generated
01B System, Internal Application, and Application
Resets are generated
10B Internal Application, and Application Resets
are generated
11B Application Reset is generated
MP
[9:8]
rw
MP Reset Type Selection
This bit field defines which reset types are generated
by a MP reset request trigger.
00B No reset is generated
01B System, Internal Application, and Application
Resets are generated
10B Internal Application, and Application Resets
are generated
11B Application Reset is generated
0
[15:10] rw
User’s Manual
SCU, V1.1
Reserved
Should be written with 0.
6-49
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
RSTCNTCON
Reset Counter Control RegisterESFR (F1B2H/D9H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0A0AH
5
4
3
RELD
RELA
rw
rw
2
1
0
Field
Bits
Type
Description
RELA
[7:0]
rw
Application Reset Counter Reload Value
This bit field defines the reload value of RSTCNTA.
This value is always used when counter RSTCNTA is
started.
This counter value is used for System, Internal
Application, and Application Resets.
RELD
[15:8]
rw
Debug Reset Counter Reload Value
This bit field defines the reload value of RSTCNTD.
This value is always used when counter RSTCNTD
is started.
This counter value is used for the Debug Reset.
User’s Manual
SCU, V1.1
6-50
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Software Reset Control Register
This register controls the software reset operation.
SWRSTCON
Software Reset Control RegisterESFR (F0AEH/57H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0000H
5
4
SWCFG
0
rw
r
3
2
1
0
SW SW
RST BOO
REQ T
w
rw
Field
Bits
Type
Description
SWBOOT
0
rw
Software Boot Configuration Selection
0B
Bit field STSTAT.HWCFG is not changed
1B
Bit field STSTAT.HWCFG is updated with the
contents of SWCFG upon an Application Reset
SWRSTREQ
1
w
Software Reset Request
0B
No software reset is requested
1B
A software reset request trigger is generated
This bit is automatically cleared and read always as
zero.
SWCFG
[15:8]
rw
Software Boot Configuration
A software boot configuration different from the
external applied hardware configuration can be
specified with these bits.
The configuration encoding is equal to the HWCFG
encoding in register STSTAT.
0
[7:2]
r
Reserved
Read as 0; should be written with 0.
User’s Manual
SCU, V1.1
6-51
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.3
System Control Unit (SCU)
External Service Request (ESR) Pins
The ESR pins serve as multi-functional pins for an amount of different options:
•
•
•
•
•
•
•
•
Act as reset trigger input
Act as reset output
Act as trap input
Act as stop input for the CapCom60, CapCom61, CapCom62, and CapCom63
Act as wake-up trigger for a power saving mode
Act as trigger input for the GSC
Overlay with other product functions
Independent pad configuration
6.3.1
General Operation
Each ESR pin is equipped with an edge detection that allows the selection of the edges
used as triggers. One, both, or non edge can be selected via bit field
ESRCFGx.AEDCON if no clock is active in the application power domain and
ESRCFGx.SEDCON if a clock is active in the application power domain. Additionally
there a digital (3-stage median) filter (DF) to suppress from spikes. The ESR pin needs
to be asserted for a minimum of 2 fSYS clock cycles in order that a trigger is generated.
If in the application power domain no clock is active the filter is not taken into account.
The filter can be disable by clearing bit ESRCFGx.DFEN.
If an ESR trigger is generated please note that triggers for all purposes (reset, trap,
CCU6X stop, GSC, and PSC) are generated. If some of the actions resulting out of such
a trigger should not occur this has to be disabled by each feature for its own.
The following three figures shows the block diagrams of the three ESR functions.
User’s Manual
SCU, V1.1
6-52
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
ESRCFG0.
AEDCON
To PSC,
GSC and
OSC_WU
Edge
Detection
Edge
Detection
ESR0
DMPMIT.
ESR0T
To Trap
ESRCFG0.
SEDCON
DF
To PSC
and GSC
ESRCFG0.
DFEN
RSM
ESR0_block .
Figure 6-15 ESR0 Operation
User’s Manual
SCU, V1.1
6-53
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
ESREXCON1
Port 2.4
ESRCFG1.
AEDCON
Port 3.0
Port 10.0
Port 1.2
To PSC,
GSC and
OSC_WU
Edge
Detection
&
Edge
Detection
To Trap
ESRCFG1.
SEDCON
Port 1.0
DF
Port 2.1
ESR1
DMPMIT.
ESR1T
ESRCFG1.
DFEN
To PSC
and GSC
RSM
ESR1_block .
Figure 6-16 ESR1 Operation
User’s Manual
SCU, V1.1
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V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
ESREXCON2
Port 2.3
Port 7.0
ESRCFG2.
AEDCON
To PSC,
GSC and
OSC_WU
Port 10.14
Edge
Detection
Port 1.1
&
Edge
Detection
Port 1.3
Port 2.2
ESR2
DMPMIT.
ESR2T
To Trap
ESRCFG2.
SEDCON
DF
ESRCFG2.
DFEN
PSC, GSC,
CCU60,
CCU61,
CCU62
and CCU63
RSM
ESR2_block .
Figure 6-17 ESR2 Operation
6.3.1.1
ESR as Reset Input
The pins ESR0/ESR1/ESR2 can serve as an external reset input as well as a reset
output (open drain) for Internal Application and Application Resets. For the ESR1 and
ESR2 additionally several GPIO pad triggers that can be enabled additionally via register
ESREXCONx (x = 1 or 2) interfere with the ESR pin function. GPIO and ESR pin triggers
can be enabled/disabled individually and are combined for the reset trigger generation.
For more information about the reset system see Chapter 6.2.
Note: The reset output is only asserted for the duration the reset counter RSTCNTA is
active. During a possible reset extension the reset output is not longer asserted.
User’s Manual
SCU, V1.1
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System Units (Vol. 1 of 2)
Preliminary
6.3.1.2
System Control Unit (SCU)
ESR as Reset Output
If the pin ESR0/ESR1/ESR2 is enabled as reset output and the input level is low while
the output stage is disabled (indicating that it is still driven low externally), the reset
circuitry holds the chip in reset until a high level is detected on ESR0/ESR1/ESR2. The
internal output stage drives a low level during reset only while RSTCNTA is active. It
deactivates the output stage when the time defined by RSTCNTCON.RELA has passed.
For more information about the reset system see Chapter 6.2.
6.3.1.3
ESR as Trap Trigger
The ESR can request traps. The control mechanism if and which trap is requested is
located in the trap control logic. For more information see Chapter 6.11.3.
6.3.1.4
ESR as Stop Input
For more information see Section 18.10.4.
6.3.1.5
ESR as Wake-up Trigger for the PSC
When the device is currently in a power save state the ESR pin can be used a wake-up
trigger. For more information see Chapter 6.5.5.
6.3.1.6
ESR as Trigger Input for the GSC
The ESR can be used to request a change in the Control Mode. For more information
see Chapter 6.6.
6.3.1.7
Overlay with other Product Functions
For the pins ESR1 and ESR2 an overlay to other product functions are possible. For
these two ESR functions additionally other port inputs can be used to generate ESR
operations. This feature can be used for various applications:
•
•
•
Wake-up from a power saving mode on an external Interrupt or CCU6x trigger and
on a CAN or USIC operation
Wake-up from a Clock-off Mode on an external Interrupt or CCU6x trigger and on a
CAN or USIC operation
Request to enter a Clock-off Mode on an external Interrupt or CCU6x trigger and on
a CAN or USIC operation
For information which other peripheral input is on an ESR overlay pin see respective
Data Sheet.
For more information about the external interrupt trigger see Chapter 6.4.
For more information about the external CCU6x trigger see Section 18.10.4.
For more information about CAN operation see Section 20.4.6.
User’s Manual
SCU, V1.1
6-56
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
For more information about USIC operation see Section 19.7.5.
6.3.1.8
Pad Configuration for ESR Pads
The configuration is selected via bit field ESRCFGx.PC.
The pad functionality control can be configured independently for each pin, comprising:
•
•
•
A selection of the driver type (open-drain or push-pull)
An enable function for the output driver (input and/or output capability)
An enable function for the pull-up/down resistance
The following table defines the coding of the bit fields PC in registers ESRCFG0,
ESRCFG1, and ESRCFG2.
Note: The coding is the same as for the port register bit fields Pn_IOCRx.PC.
Table 6-8
PC Coding
PCx[3:0]
Selected Pull-up/Pull-down /
Selected Output Function
I/O
0000B
No pull device activated
0001B
Pull-down device activated
0010B
Pull-up device activated
Input is not inverted,
the input stage is
active in power-down
mode
0011B
No pull device activated
0100B
No pull device activated
0101B
Pull-down device activated
0110B
Pull-up device activated
0111B
No pull device activated
1000B
Output of ESRCFGx.OUT
1001B
Output of ESRCFGx.OUT
1010B
Output drives a 0 for an Internal
Application Reset, a 1 otherwise.
1011B
Output drives a 0 for an
Application Reset, a 1 otherwise.
1100B
Output of ESRCFGx.OUT
1101B
Output of ESRCFGx.OUT
1110B
Output drives a 0 for an Internal
Application Reset
1111B
Output drives a 0 for an
Application Reset
User’s Manual
SCU, V1.1
Output
Characteristics
Input is inverted,
the input stage is
active in power-down
mode
6-57
Output,
Push-pull
the input stage is not
inverted and active in
power-down mode
Open-drain,
a pull-up device
is activated
while the output
is not driving a 0
V1.0, 2007-06
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Preliminary
System Control Unit (SCU)
6.3.2
ESR Control Registers
6.3.2.1
Configuration Registers
ESR External Control Register
The ESR External Control registers contain enable/disable bits for the different inputs
that can lead to an ESR action. Only for ESR1 and ESR2 this option is available.
ESREXCON1
ESR1 External Control Register SFR (FF32H/99H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0001H
5
4
3
2
1
P21 P12 P10 P100 P30 P24 ESR
EN EN EN EN EN EN 1EN
0
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
ESR1EN
0
rw
ESR1 Pin Enable
This bit enables/disables the ESR1 pin for the
activation of all ESR1 related actions.
0B
The input from pin ESR1 is disabled
1B
The input from pin ESR1 is enabled
P24EN
1
rw
Port 2.4 Pin Enable
This bit enables/disables the Port 2.4 pin for the
activation of all ESR1 related actions.
0B
The input from port pin P2.4 is disabled
1B
The input from port pin P2.4 is enabled
P30EN
2
rw
Port 3.0 Pin Enable
This bit enables/disables the Port 3.0 pin for the
activation of all ESR1 related actions.
0B
The input from port pin P3.0 is disabled
1B
The input from port pin P3.0 is enabled
P100EN
3
rw
Port 10.0 Pin Enable
This bit enables/disables the Port 10.0 pin for the
activation of all ESR1 related actions.
0B
The input from port pin P10.0 is disabled
1B
The input from port pin P10.0 is enabled
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0
6-58
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
P10EN
4
rw
Port 1.0 Pin Enable
This bit enables/disables the Port 1.0 pin for the
activation of all ESR1 related actions.
The input from port pin P1.0 is disabled
0B
1B
The input from port pin P1.0 is enabled
P12EN
5
rw
Port 1.2 Pin Enable
This bit enables/disables the Port 1.2 pin for the
activation of all ESR1 related actions.
0B
The input from port pin P1.2 is disabled
The input from port pin P1.2 is enabled
1B
P21EN
6
rw
Port 2.1 Pin Enable
This bit enables/disables the Port 2.1 pin for the
activation of all ESR1 related actions.
0B
The input from port pin P2.1 is disabled
1B
The input from port pin P2.1 is enabled
0
[15:7]
rw
Reserved
Read as 0; should be written with 0.
ESREXCON2
ESR2 External Control Register SFR (FF34H/9AH)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0001H
5
4
3
2
1
P
P22 P13 P11
P70 P23 ESR
1014
EN EN EN
EN EN 2EN
EN
rw
rw
rw
rw
rw
rw
rw
0
rw
Field
Bits
Type
Description
ESR2EN
0
rw
ESR2 Pin Enable
This bit enables/disables the ESR2 pin for the
activation of all ESR2 related actions.
0B
The input from pin ESR2 is disabled
1B
The input from pin ESR2 is enabled
P23EN
1
rw
Port 2.3 Pin Enable
This bit enables/disables the Port 2.3 pin for the
activation of all ESR2 related actions.
0B
The input from port pin P2.3 is disabled
1B
The input from port pin P2.3 is enabled
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0
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
P70EN
2
rw
Port 7.0 Pin Enable
This bit enables/disables the Port 7.0 pin for the
activation of all ESR2 related actions.
The input from port pin P7.0 is disabled
0B
1B
The input from port pin P7.0 is enabled
P1014EN
3
rw
Port 10.14 Pin Enable
This bit enables/disables the Port 10.14 pin for the
activation of all ESR2 related actions.
0B
The input from port pin P10.14 is disabled
The input from port pin P10.14 is enabled
1B
P11EN
4
rw
Port 1.1 Pin Enable
This bit enables/disables the Port 1.1 pin for the
activation of all ESR2 related actions.
0B
The input from port pin P1.1 is disabled
1B
The input from port pin P1.1 is enabled
P13EN
5
rw
Port 1.3 Pin Enable
This bit enables/disables the Port 1.3 pin for the
activation of all ESR2 related actions.
0B
The input from port pin P1.3 is disabled
1B
The input from port pin P1.3 is enabled
P22EN
6
rw
Port 2.2 Pin Enable
This bit enables/disables the Port 2.2 pin for the
activation of all ESR2 related actions.
0B
The input from port pin P2.2 is disabled
1B
The input from port pin P2.2 is enabled
0
[15:7]
rw
Reserved
Read as 0; should be written with 0.
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Preliminary
System Control Unit (SCU)
ESR Configuration Register
The ESR configuration registers contains bits required for the behavioral control of the
ESR pins.
ESRCFG0
ESR0 Configuration Register
ESRCFG1
ESR1 Configuration Register
ESRCFG2
ESR2 Configuration Register
15
14
13
12
11
10
ESFR (F100H/80H)
Reset Value: 000EH
ESFR (F102H/81H)
Reset Value: 0002H
ESFR (F104H/82H)
Reset Value: 0002H
9
8
7
6
5
4
3
2
1
0
AEDCON
SEDCON
IN
OUT
DF
EN
PC
r
rw
rw
rh
rh
rw
rw
0
Field
Bits
Type
Description
PC
[3:0]
rw
Pin Control of ESRx
This bit field controls the behavior of the associated
ESRx pin.
The coding is described in Table 6-8.
DFEN
4
rw
Digital Filter Enable
This bit defines if the 3-stage median filter of the
ESRx is used or bypassed.
0B
The filter is bypassed
1B
The filter is used
OUT
5
rh
Data Output
This bit can be used as output value for the
associated ESRx pin.
0B
If selected, the output level is 0
1B
If selected, the output level is 1
IN
6
rh
Data Input
This bit monitors the input value at the associated
ESRx pin.
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Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
SEDCON
[8:7]
rw
Synchronous Edge Detection Control
This bit field defines the edges that lead to an ESRx
trigger of the synchronous path.
00B No trigger is generated
01B A trigger is generated upon a raising edge
10B A trigger is generated upon a falling edge
11B A trigger is generated upon a raising AND
falling edge
Other combinations than 00B are only allowed if bit
field AEDCON is configured to 00B.
AEDCON
[10:9]
rw
Asynchronous Edge Detection Control
This bit field defines the edges that lead to an ESRx
trigger of the asynchronous path.
00B No trigger is generated
01B A trigger is generated upon a raising edge
10B A trigger is generated upon a falling edge
11B A trigger is generated upon a raising AND
falling edge
Other combinations than 00B are only allowed if bit
field SEDCON is configured to 00B.
0
[15:11] r
User’s Manual
SCU, V1.1
Reserved
Read as 0; should be written with 0.
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Preliminary
System Control Unit (SCU)
6.3.3
ESR Data Register
6.3.3.1
ESRDAT
The ESR data register contains bits required if ESR0/ESR1/ESR2 are used as data
ports.
ESRDAT
ESR Data Register
15
14
13
12
ESFR (F106H/83H)
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
0
MOUT2
MOUT1
MOUT0
r
w
w
w
Field
Bits
Type
Description
MOUT0
[1:0]
w
Modification of ESRCFG0.OUT
Writing to this bit field can modify the content of bit
ESRCFG0.OUT for ESR0. It always reads 0.
00B Bit ESRCFG0.OUT is unchanged
01B Bit ESRCFG0.OUT is set
10B Bit ESRCFG0.OUT is cleared
11B Reserved, do not use this combination
MOUT1
[3:2]
w
Modification of ESRCFG1.OUT
Writing to this bit field can modify the content of bit
ESRCFG1.OUT for ESR1. It always reads 0.
00B Bit ESRCFG1.OUT is unchanged
01B Bit ESRCFG1.OUT is set
10B Bit ESRCFG1.OUT is cleared
11B Reserved, do not use this combination
MOUT2
[5:4]
w
Modification of ESRCFG2.OUT
Writing to this bit field can modify the content of bit
ESRCFG2.OUT for ESR2. It always reads 0.
00B Bit ESRCFG2.OUT is unchanged
01B Bit ESRCFG2.OUT is set
10B Bit ESRCFG2.OUT is cleared
11B Reserved, do not use this combination
0
[15:6]
w
Reserved
Read as 0; should be written with 0.
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System Units (Vol. 1 of 2)
Preliminary
6.4
System Control Unit (SCU)
External Request Unit (ERU)
The External Request Unit (ERU) is a versatile event and pattern detection unit. Its major
task is the generation of interrupts based on selectable trigger events at different
inputs, e.g. to generate external interrupt requests if an edge occurs at an input pin.
The detected events can also be used by other modules to trigger or to gate modulespecific actions, such as conversions of the ADC module.
6.4.1
Introduction
The ERU of the XC2000 can be split in three main functional parts:
•
•
•
4 independent Input Channels x for input selection and conditioning of trigger or
gating functions
Event distribution: A Connecting Matrix defines the events of the Input Channel x
that lead to a reaction of an Output Channel y.
4 independent Output Channels y for combination of events, definition of their
effects and distribution to the system (interrupt generation, ADC conversion triggers)
External Request Unit
from pins or
modules
4
External
Request Select
Units
Event Trigger
Logic Units
ERS0
ETL0
to interrupt
controller,
ADC
Output
Gating Units
ERU_PDOUT0
ERU_GOUT0
ERU_IOUT0
ERU_TOUT0
ERU_0A[3:0]
ERU_0B[3:0]
4
OGU0
Input Channel 0
Output Channel 0
4
4
ERS1
Connecting Matrix
ERU_1A[3:0]
ETL1
ERU_1B[3:0]
Input Channel 1
ERU_2A[3:0]
4
4
ERS2
ETL2
ERU_2B[3:0]
ERU_PDOUT1
ERU_GOUT1
ERU_IOUT1
ERU_TOUT1
OGU1
Output Channel 1
ERU_PDOUT2
ERU_GOUT2
ERU_IOUT2
ERU_TOUT2
OGU2
Output Channel 2
Input Channel 2
ERU_PDOUT3
ERU_GOUT3
ERU_IOUT3
ERU_TOUT3
4
ERU_3A[3:0]
ERU_3B[3:0]
4
ERS3
OGU3
ETL3
Input Channel 3
Output Channel 3
Peripheral Triggers
ERU_Block_Overview_.vsd
Figure 6-18 External Request Unit Overview
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Preliminary
System Control Unit (SCU)
These tasks are handled by the following building blocks:
•
•
•
•
An External Request Select Unit (ERSx) per Input Channel allows the selection of
one out of two or a logical combination of two inputs (ERU_xA, ERU_xB) to a
common trigger. For each of these two inputs, an input vector of 4 possible inputs is
available (e.g. the actual input ERU_xA can be selected from one of the ERU inputs
ERU_xA[3:0], similar for ERU_xB).
An Event Trigger Logic (ETLx) per Input Channel allows the definition of the
transition (edge selection, or by software) that lead to a trigger event and can also
store this status. Here, the input levels of the selected inputs are translated into
events (event detected = event flag becomes set, independent of the polarity of the
original inputs).
The Connecting Matrix distributes the events and status flags generated by the
Input Channels to the Output Channels. Additionally, some peripheral triggers from
other modules (e.g. CC2) are made available and can be combined with the triggers
generated by the Input Channels of the ERU.
An Output Gating Unit (OGUy) per Output Channel that combines the available
trigger events and status information from the Input Channels. An event of one Input
Channel can lead to reactions of several Output Channels, or also events of several
Input Channels can be combined to a reaction of one Output Channel (pattern
detection).
Different types of reactions are possible, e.g. interrupt generation (based on
ERU_IOUTy), triggering of ADC conversions (based on ERU_TOUTy), or gating of
ADC conversions (based on ERU_GOUTy).
The ERU is controlled by a number of registers, shown in Figure 6-19, and described in
Section 6.4.8.
Input Selection
Input & Trigger
Control
Output Control
EXISEL
EXICON0
EXOCON0
EXICON1
EXOCON1
EXICON2
EXOCON2
EXICON3
EXOCON3
EXISEL:
EXICON0..3:
EXOCON0..3:
Input Selection Register
Input and Trigger Control Registers
Output Control Registers
ERU_Register_Overview.vsd
Figure 6-19 ERU Registers Overview
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Preliminary
6.4.2
System Control Unit (SCU)
ERU Pin Connections
Figure 6-20 shows the ERU input connections, either directly with pins or via
communication modules, such as USIC or MultiCAN. These communication modules
provide their inputs (e.g. CAN receive input, or USIC data, clock, or control inputs) that
have been selected in these modules. With this structure, the number of possible input
pins is significantly increased, because not only the selection capability of the ERU is
used, but also the selection capability of the communication modules.
ERS0
ERS1
P2.1
ERU_0A0
P2.2
ERU_1A0
ESR1
ERU_0A1
ESR2
ERU_1A1
U0C0_DX0INS,
selected data input
ERU_0A2
U1C0_DX0INS,
selected data input
ERU_1A2
U0C0_DX2INS,
selected control input
ERU_0A3
U1C0_DX2INS,
selected control input
ERU_1A3
P1.1
P1.0
ERU_0B0
P5.13
ERU_0B1
MultiCAN_CAN4INS,
selected receive input CAN4
ERU_1B1
U0C1_DX0INS,
selected data input
ERU_0B2
U1C1_DX0INS,
selected data input
ERU_1B2
U0C1_DX2INS,
selected control input
ERU_0B3
U1C1_DX2INS,
selected control input
ERU_1B3
ERU_1B0
ERS2
P1.2
ERS3
P1.3
ERU_2A0
ERU_3A0
MultiCAN_CAN1INS,
selected receive input CAN1
MultiCAN_CAN3INS,
selected receive input CAN3
ERU_2A1
U2C0_DX0INS,
selected data input
ERU_2A2
reserved
ERU_3A2
U2C0_DX2INS,
selected control input
ERU_2A3
reserved
ERU_3A3
U2C0_DX1INS,
selected clock input
ERU_2B0
U1C0_DX1INS,
selected clock input
ERU_3B0
MultiCAN_CAN2INS,
selected receive input CAN2
ERU_2B1
MultiCAN_CAN0INS,
selected receive input CAN0
ERU_3B1
U2C1_DX0INS,
selected data input
ERU_2B2
reserved
ERU_3B2
U2C1_DX2INS,
selected control input
ERU_2B3
reserved
ERU_3B3
ERU_3A1
ERU_Inputs_Overview.vsd
Figure 6-20 ERU Inputs Overview
The inputs to the ERU can be selected from a large number of inputs. While some of the
inputs come directly from a pin, other inputs come from various peripheral modules, such
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Preliminary
System Control Unit (SCU)
as the USIC (inputs named with prefix UxCy to indicate which the communication
channel) and the MultiCAN modules. These inputs come from the pins that has been
selected as inputs for a USIC or MultiCAN function. The selection of the input is made
within the respective USIC or MultiCAN module.
Usually, such inputs would be selected for an ERU function when the input function to
the USIC or MultiCAN module is not used otherwise, or the module is not used at all.
However, it is also possible to select a input that is actually needed in a USIC or
MultiCAN module, and to use it also in the ERU to provide for certain trigger functions,
eventually combined with other inputs (e.g. to generate an interrupt in case a start of
frame is detected at a selected communication input).
Table 6-9 provides a complete overview of all pins as well as the ESRx inputs, that can
possibly be used as inputs to the ERU. Please note that there are also some other
peripheral inputs, that can be selected by the USIC or MultiCAN module via their
respective input multiplexers, and that can therefore be used as ERU inputs.
In total, external inputs from up to 51 pins (from which 7 are direct inputs to the ERU)
plus the ESRx pins can be chosen. For some of them, several choices exist in respect
to which module provides it and to which ERSx they are connected to).
Table 6-9
ERU External Pin Input Options
Port
Pin
Selectable via
ERU Input
P0
P0.0
U1C0 data input DX0A
ERS1, ERU_1A2
P0.1
U1C0 data input DX0B
U1C0 clock input DX1A
ERS1, ERU_1A2
ERS3, ERU_3B0
P0.2
U1C0 clock input DX1B
ERS3, ERU_3B0
P0.3
U1C0 control input DX2A
MultiCAN receive input RXDC0B
ERS1, ERU_1A3
ERS3, ERU_3B1
P0.4
U1C1 control input DX2A
MultiCan receive input RXDC1B
ERS1, ERU_1B3
ERS3, ERU_3A1
P0.5
U1C0 clock input DX1C
ERS3, ERU_3B0
P0.5
U1C1 data input DX0A
ERS1, ERU_1B2
P0.7
U1C1 data input DX0B
ERS1, ERU_1B2
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System Units (Vol. 1 of 2)
Preliminary
Table 6-9
System Control Unit (SCU)
ERU External Pin Input Options (cont’d)
Port
Pin
Selectable via
ERU Input
P1
P1.0
Direct ERU input
ERS0, ERU_0B0
P1.1
Direct ERU input
U2C1 data input DX0C
ERS1, ERU_1B0
ERS2, ERU_2B2
P1.2
Direct ERU input
U2C1 data input DX0D
ERS2, ERU_2A0
ERS2, ERU_2B2
P1.3
Direct ERU input
ERS3, ERU_3A0
P1.4
U2C0 control input DX2B
ERS2, ERU_2A3
P1.5
U2C0 data input DX0C
ERS2, ERU_2A2
P1.6
U2C0 data input DX0D
ERS2, ERU_2A2
P1.7
U2C0 clock input DX1C
ERS2, ERU_2B0
P2.0
MultiCAN receive input RXDC0C
ERS3, ERU_3B1
P2.1
Direct ERU input
ERS0, ERU_0A0
P2.2
Direct ERU input
ERS1, ERU_1A0
P2.3
U0C0 data input DX0E
MultiCAN receive input RXDC0A
ERS0, ERU_0A2
ERS3, ERU_3B1
P2.4
U0C0 data input DX0F
MultiCAN receive input RXDC1A
ESR0, ERU_0A2
ERS3, ERU_3A1
P2.6
U0C0 control input DX2D
MultiCAN receive input RXDC0D
ERS0, ERU_0A3
ERS3, ERU_3B1
P2.7
U0C1 control input DX2C
MultiCAN receive input RXDC1C
ERS0, ERU_0B3
ERS3, ERU_3A1
P2.10
U0C1 data input DX0E
ERS0, ERU_0B2
P3.0
U2C0 data input DX0A
U2C0 clock input DX1A
MultiCAN receive input RXDC3B
ERS2, ERU_2A2
ERS2, ERU_2B0
ERS2, ERU_2A1
P3.1
U2C0 data input DX0B
ERS2, ERU_2A2
P3.2
U2C0 control input DX2A
U2C0 clock input DX1B
ERS2, ERU_2A3
ERS2, ERU_2B0
P3.3
MultiCAN receive input RXDC3A
ERS2, ERU_2A1
P3.4
U2C1 control input DX2A
MultiCAN receive input RXDC4A
ERS2, ERU_2B3
ERS1, ERU_1B1
P3.6
U2C1 data input DX0A
ERS2, ERU_2B2
P3.7
U2C0 data input DX0B
ERS2, ERU_2B2
P2
P2
P3
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Preliminary
Table 6-9
System Control Unit (SCU)
ERU External Pin Input Options (cont’d)
Port
Pin
Selectable via
ERU Input
P4
P4.3
MultiCAN receive input RXDC2A
ERS2, ERU_2B1
P5
P5.13
Direct ERU input
ERS0, ERU_0B1
P6
P6.0
U1C1 data input DX0E
ERS1, ERU_1B2
P6.3
U1C1 control input DX2D
ERS1, ERU_1B3
P7.0
MultiCAN Node 4 receive input RXDC4B
ERS1, ERU_1B1
P7.3
U0C1 data input DX0F
ERS0, ERU_0B2
P7.4
U0C0 data input DX0D
ERS0, ERU_0A2
P9.5
U2C0 data input DX0D
ERS2, ERU_2A2
P9.7
U2C0 clock input DX1D
ERS2, ERU_2B0
P10.0
U0C0 data input DX0A
U0C1 data input DX0A
ERS0, ERU_0A2
ERS0, ERU_0B2
P10.1
U0C0 data input DX0B
ERS0, ERU_0A2
P10.3
U0C0 control input DX2A
U0C1 control input DX2A
ERS0, ERU_0A3
ERS0, ERU_0B3
P10.4
U0C0 control input DX2B
U0C1 control input DX2B
ERS0, ERU_0A3
ERS0, ERU_0B3
P10.6
U0C0 data input DX0C
U1C0 control input DX2D
ERS0, ERU_0A2
ERS1, ERU_1A3
P10.7
U0C1 data input DX0B
MultiCAN receive input RXDC4C
ERS0, ERU_0B2
ERS1, ERU_1B1
P7
P9
P10
P10
P10.10 U0C 0 control input DX2C
ERS0, ERU_0A3
P10.11 U1C0 clock input DX1D
MultiCAN receive input RXDC2B
ERS3, ERU_3B0
ERS2, ERU_2B1
P10.12 U1C0 data input DX0C
U1C0 clock input DX1D
ERS1, ERU_1A2
ERS3, ERU_3B0
P10.13 U1C0 data input DX0D
ERS1, ERU_1A2
P10.14 U0C1 data input DX0C
MultiCAN receive input RXDC3C
ERS0, ERU_0B2
ERS2, ERU_2A1
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Preliminary
Table 6-9
Port
System Control Unit (SCU)
ERU External Pin Input Options (cont’d)
Pin
Selectable via
ERU Input
ESR
ESR0
inputs
U1C0 data input DX0E
U1C0 control input DX2B
MultiCAN receive input RXDC2D
ERS1, ERU_1A2
ERS1, ERU_1A3
ERS2, ERU_2B1
ESR1
Direct ERU input
U1C0 data input DX0F
U1C0 control input DX2C
U1C1 data input DX0C
U1C1 control input DX2B
U2C0 data input DX0F
U2C1 control input DX2C
MultiCAN receive input RXDC0E
ERS0, ERU_0A1
ERS1, ERU_1A2
ERS1, ERU_1A3
ERS1, ERU_1B2
ERS1, ERU_1B3
ERS2, ERU_2B2
ERS2, ERU_2B3
ERS3, ERU_3B1
ESR2
Direct ERU input
U1C1 data input DX0D
U1C1 control input DX2C
U2C0 data input DX0E
U2C1 control input DX2B
MultiCAN receive input RXDC1E
ERS1, ERU_1A1
ERS1, ERU_1B2
ERS1, ERU_1B3
ERS2, ERU_2B2
ERS2, ERU_2B3
ERS3, ERU_3A1
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Preliminary
System Control Unit (SCU)
The following table describes the ERU input connections for the ERSx stages. The
selection is defined by the bit fields in register EXISEL.
Note: All functional inputs of the ERU are synchronized to fSYS before they can affect the
internal logic. The resulting delay of 2/fSYS and an uncertainty of 1/fSYS have to be
taken into account for precise timing calculation.
An edge of an input can only be correctly detected if both, the high phase and the
low phase of the input are each longer than 1/fSYS.
Table 6-10
ERSx Connections in XC2000
Input
from/to
Module
I/O to
ESRx
Can be used to/as
ERU_0A0
P2.1
I
ERS0 input A
ERU_0A1
ESR1
I
ERU_0A2
U0C0_DX0INS
I
ERU_0A3
U0C0_DX2INS
I
ERU_0B0
P1.0
I
ERU_0B1
P5.13
I
ERU_0B2
U0C1_DX0INS
I
ERU_0B3
U0C1_DX2INS
I
ERU_1A0
P2.2
I
ERU_1A1
ESR2
I
ERU_1A2
U1C0_DX0INS
I
ERU_1A3
U1C0_DX2INS
I
ERU_1B0
P1.1
I
ERU_1B1
MultiCAN_
CAN4INS
I
ERU_1B2
U1C1_DX0INS
I
ERU_1B3
U1C1_DX2INS
I
ERS0 Inputs
ERS0 input B
ERS1 Inputs
ERS1 input A
ERS1 input B
ERS2 Inputs
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System Control Unit (SCU)
Table 6-10
ERSx Connections in XC2000 (cont’d)
Input
from/to
Module
I/O to
ESRx
Can be used to/as
ERU_2A0
P1.2
I
ERS2 input A
ERU_2A1
MultiCAN_
CAN3INS
I
ERU_2A2
U2C0_DX0INS
I
ERU_2A3
U2C0_DX2INS
I
ERU_2B0
U2C0_DX1INS
I
ERU_2B1
MultiCAN_
CAN2INS
I
ERU_2B2
U2C1_DX0INS
I
ERU_2B3
U2C1_DX2INS
I
ERU_3A0
P1.3
I
ERU_3A1
MultiCAN_
CAN1INS
I
ERU_3A2
0
I
ERU_3A3
0
I
ERU_3B0
U1C0_DX1INS
I
ERU_3B1
MultiCAN_
CAN0INS
I
ERU_3B2
0
I
ERU_3B3
0
I
ERS2 input B
ERS3 Inputs
6.4.3
ERS3 input A
ERS3 input B
External Request Select Unit (ERSx; x = 0..3)
For each Input Channel x, an ERSx unit handles the input selection for the associated
ETLx unit. Each ERSx performs a logical combination of two inputs (Ax, Bx) to provide
one combined output ERSxO to the associated ETLx. Input Ax can be selected from 4
possibilities of the input vector ERU_xA[3:0] and can be optionally inverted. A similar
structure exists for input Bx (selection from ERU_xB[3:0]).
In addition to the direct choice of either input Ax or Bx or their inverted values, the
possible logical combinations for two selected inputs are a logical AND or a logical OR.
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Preliminary
System Control Unit (SCU)
EXISEL.
EXSxA
EXICONx.
NA
Select
Input
Ax
Select
Polarity
Ax
EXICONx.
SS
ERU_xA0
ERU_xA1
ERU_xA2
Ax
Bx
ERU_xA3
1
Ax OR Bx
ERU_xB0
ERU_xB1
ERU_xB2
Select
Input
Bx
Select
Polarity
Bx
EXISEL.
EXSxB
EXICONx.
NB
&
Ax AND Bx
Select
Source
for
ERSxO
ERSxO
ETLx
ERU_xB3
External Request
Select Unit x (ERSx)
ERU_ERS.vsd
Figure 6-21 External Request Select Unit Overview
The ERS units are controlled via register EXISEL (one register for all four ERSx units)
and registers EXICONx (one register for each ERSx and associated ETLx unit, e.g.
EXICON0 for Input Channel 0).
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6.4.4
System Control Unit (SCU)
Event Trigger Logic (ETLx; x = 0..3)
For each Input Channel x, an event trigger logic ETLx derives a trigger event and a status
from the input ERUxO delivered by the associated ERSx unit. Each ETLx is based on an
edge detection block, where the detection of a rising or a falling edge can be individually
enabled. Both edges lead to a trigger event if both enable bits are set (e.g. to handle a
toggling input).
Each of the four ETLx units has an associated EXICONx register, that controls all options
of an ETLx (the register also holds control bits for the associated ERSx unit, e.g.
EXICON0 to control ESR0 and ETL0).
EXICONx.
FE
EXICONx.
LD
Modify
Status
Flag
ERSx
ERSxO
Detect
Event
(edge)
Event Trigger
Logic x (ETLx)
set
clear
Status Flag
FL
EXICONx.FL
to all OGUy
edge event
TRx0 to
OGU0
Enable
Trigger
Pulse
trigger pulse
Select
Trigger
Output
TRx1 to
OGU1
TRx2 to
OGU2
TRx3 to
OGU3
EXICONx.
RE
EXICONx.
PE
EXICONx.
OCS
ERU_ETL.vsd
Figure 6-22 Event Trigger Logic Overview
When the selected event (edge) is detected, the status flag EXICONx.FL becomes set.
This flag can also be modified by software (set or clear). Two different operating modes
are supported by this status flag.
It can be used as “sticky” flag, that is set by hardware when the desired event has been
detected and has to be cleared by software. In this operating mode, it indicates that the
event has taken place, but without indicating the actual status of the input.
In the second operating mode, it is cleared automatically if the “opposite” event is
detected. For example, if only the falling edge detection is enabled to set the status flag,
it is cleared when the rising edge is detected. In this mode, it can be used for pattern
detection where the actual status of the input is important (enabling both edge detections
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is not useful in this mode).
The output of the status flag is connected to all following Output Gating Units (OGUy) in
parallel (see Figure 6-23) to provide pattern detection capability of all OGUy units
based on different or the same status flags.
In addition to the modification of the status flag, a trigger pulse output TRxy of ETLx can
be enabled (by bit EXICONx.PE) and selected to trigger actions in one of the OGUy
units. The target OGUy for the trigger is selected by bit field EXICON.OCS.
The trigger becomes active when the selected edge event is detected, independently
from the status flag EXICONx.FL.
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6.4.5
System Control Unit (SCU)
Connecting Matrix
The connecting matrix distributes the trigger (TRxy) and status (EXICONx.FL) outputs
from the different ETLx units between the OGUy units. In addition, it receives peripheral
triggers that can be OR-combined with the ETLx triggers in the OGUy units. Figure 6-23
provides a complete overview of the connections between the ETLx and the OGUy units.
EXICON0.FL
Pattern
Detection
Inputs
TR00
TR01
ETL0
OGU0
TR02
ERU_PDOUT0
ERU_GOUT0
ERU_IOUT0
ERU_TOUT0
TR03
Trigger
Inputs
TRx0
Peripheral
Triggers
EXICON1.FL
Pattern
Detection
Inputs
TR10
TR11
ETL1
OGU1
TR12
ERU_PDOUT1
ERU_GOUT1
ERU_IOUT1
ERU_TOUT1
Trigger
Inputs
TRx1
TR13
Peripheral
Triggers
EXICON2.FL
TR20
Pattern
Detection
Inputs
ERU_PDOUT2
OGU2
ERU_IOUT2
TR21
ETL2
TR22
ERU_GOUT2
ERU_TOUT2
TR23
Trigger
Inputs
TRx2
Peripheral
Triggers
Pattern
Detection
Inputs
ERU_PDOUT3
EXICON3.FL
TR30
TR31
ETL3
OGU3
TR32
ERU_GOUT3
ERU_IOUT3
ERU_TOUT3
TR33
Trigger
Inputs
TRx3
Peripheral
Triggers
ERU_ETL_OGU_Overview.vsd
Figure 6-23 Connecting Matrix between ETLx and OGUy
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6.4.6
System Control Unit (SCU)
Output Gating Unit (OGUy; y = 0..3)
Each OGUy unit combines the available trigger events and status flags from the Input
Channels and distributes the results to the system. Figure 6-24 illustrates the logic
blocks within an OGUy unit. All functions of an OGUy unit are controlled by its associated
EXOCONy register, e.g. EXOCON0 for OGU0. The function of an OGUy unit can be split
into two parts:
•
•
Trigger combination (see Section 6.4.6.1):
All triggers TRxy from the Input Channels that are enabled and directed to OGUy, a
selected peripheral-related trigger event, and a pattern change event (if enabled) are
logically OR-combined.
Pattern detection (see Section 6.4.6.2):
The status flags EXICONx.FL of the Input Channels can be enabled to take part in
the pattern detection. A pattern match is detected while all enabled status flags are
set.
Status Flags
EXICON0.FL
EXOCONy.
IPEN0
EXOCONy.
GEEN
EXICON1.FL
ERU_PDOUTy
EXOCONy.
IPEN1
EXICON2.FL
Detect
Pattern
EXOCONy.
PDR
EXOCONy.
IPEN2
Select
Gating
Scheme
EXICON3.FL
Triggers
from Input
Channels
EXOCONy.
GP
EXOCONy.
IPEN3
ERU_GOUTy
TR0y
Combine
OGU
Triggers
(OR)
TR1y
TR2y
TR3y
Interrupt
Gating
(AND)
ERU_IOUTy
ERU_TOUTy
ERU_OGUy1
Peripheral
Triggers
ERU_OGUy2
ERU_OGUy3
Select
Periph.
Triggers
EXOCONy.
ISS
Output Gating
Unit y (OGUy)
ERU_OGU.vsd
Figure 6-24 Output Gating Unit for Output Channel y
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Each OGUy units generates 4 outputs that are distributed to the system (not all of them
are necessarily used, please refer to Section 6.4.7):
•
•
•
•
ERU_PDOUTy to directly output the pattern match information for gating purposes
in other modules (pattern match = 1).
ERU_GOUTy to output the pattern match or pattern miss information (inverted
pattern match), or a permanent 0 or 1 under software control for gating purposes in
other modules.
ERU_TOUTy as combination of a peripheral trigger, a pattern detection result
change event, or the ETLx trigger outputs TRxy to trigger actions in other modules.
ERU_IOUTy as gated trigger output (ERU_GOUTy logical AND-combined with
ERU_TOUTy) to trigger interrupts (e.g. the interrupt generation can be gated to allow
interrupt activation during a certain time window).
6.4.6.1
Trigger Combination
The trigger combination logically OR-combines different trigger inputs to form a common
trigger ERU_TOUTy. Possible trigger inputs are:
•
•
•
In each ETLx unit of the Input Channels, the trigger output TRxy can be enabled and
the trigger event can be directed to one of the OGUy units.
One out of three peripheral triggers per OGUy can be selected as additional trigger
source. These peripheral triggers are generated by on-chip peripheral modules, such
as capture/compare or timer units. The selection is done by bit field EXOCONy.ISS.
In the case that at least one pattern detection input is enabled (EXOCONy.IPENx)
and a change of the pattern detection result from pattern match to pattern miss (or
vice-versa) is detected, a trigger event is generated to indicate a pattern detection
result event (if enabled by ECOCONy.GEEN).
The trigger combination offers the possibility to program different trigger criteria for
several inputs (independently for each Input Channel) or peripheral triggers, and to
combine their effects to a single output, e.g. to generate an interrupt or to start an ADC
conversion. This combination capability allows the generation of an interrupt per OGU
that can be triggered by several inputs (multitude of request sources -> one reaction).
The following table describes the peripheral trigger connections for the OGUy stages.
The selection is defined by the bit fields ISS in registers EXOCON0 (for OGU0),
EXOCON1 (for OGU1), EXOCON2 (for OGU2), or EXOCON3 (for OGU3).
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Table 6-11
OGUy Peripheral Trigger Connections in XC2000
Input
from/to
Module
I/O to
OGUy
Can be used to/as
ERU_
OGU01
CCU60_MCM_ST
I
peripheral triggers for OGU0
ERU_
OGU02
CCU60_T13_PM
I
ERU_
OGU03
CC2_31
I
ERU_
OGU11
CCU61_MCM_ST
I
ERU_
OGU12
CCU61_T13_PM
I
ERU_
OGU13
CC2_30
I
ERU_
OGU21
CCU62_MCM_ST
I
ERU_
OGU22
CCU62_T13_PM
I
ERU_
OGU23
CC2_29
I
ERU_
OGU31
CCU63_MCM_ST
I
ERU_
OGU32
CCU63_T13_PM
I
ERU_
OGU33
CC2_28
I
OGU0 Inputs
OGU1 Inputs
peripheral triggers for OGU1
OGU2 Inputs
peripheral triggers for OGU2
OGU3 Inputs
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peripheral triggers for OGU3
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6.4.6.2
System Control Unit (SCU)
Pattern Detection
The pattern detection logic allows the combination of the status flags of all ETLx units.
Each status flag can be individually included or excluded from the pattern detection for
each OGUy, via control bits EXOCONy.IPENx. The pattern detection block outputs the
following pattern detection results:
•
•
Pattern match (EXOCONy.PDR = 1 and ERU_PDOUTy = 1):
A pattern match is indicated while all status flags FL that are included in the pattern
detection are 1.
Pattern miss (EXOCONy.PDR = 0 and ERU_PDOUTy = 0):
A pattern miss is indicated while at least one of the status flags FL that are included
in the pattern detection is 0.
In addition, the pattern detection can deliver a trigger event if the pattern detection result
changes from match to miss or vice-versa (if enabled by EXOCONy.GEEN = 1). The
pattern result change event is logically OR-combined with the other enabled trigger
events to support interrupt generation or to trigger other module functions (e.g. in the
ADC). The event is indicated when the pattern detection result changes and
EXOCONy.PDR becomes updated.
The interrupt generation in the OGUy is based on the trigger ERU_TOUTy that can be
gated (masked) with the pattern detection result ERU_PDOUTy. This allows an
automatic and reproducible generation of interrupts during a certain time window, where
the request event is elaborated by the trigger combination block and the time window
information (gating) is given by the pattern detection. For example, interrupts can be
issued on a regular time base (peripheral trigger input from capture/compare unit is
selected) while a combination of inputs occurs (pattern detection based on ETLx status
bits).
A programmable gating scheme introduces flexibility to adapt to application
requirements and allows the generation of interrupt requests ERU_IOUTy under
different conditions:
•
•
•
•
Pattern match (EXOCONy.GP = 10B):
An interrupt request is issued when a trigger event occurs while the pattern detection
shows a pattern match.
Pattern miss (EXOCONy.GP = 11B):
An interrupt request is issued when the trigger event occurs while the pattern
detection shows a pattern miss.
Independent of pattern detection (EXOCONy.GP = 01B):
In this mode, each occurring trigger event leads to an interrupt request. The pattern
detection output can be used independently from the trigger combination for gating
purposes of other peripherals (independent use of ERU_TOUTy and ERU_PDOUTy
with interrupt requests on trigger events).
No interrupts (EXOCONy.GP = 00B, default setting)
In this mode, an occurring trigger event does not lead to an interrupt request. The
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pattern detection output can be used independently from the trigger combination for
gating purposes of other peripherals (independent use of ERU_TOUTy and
ERU_PDOUTy without interrupt requests on trigger events).
6.4.7
ERU Output Connections
This section describes the connections of the ERU outputs for gating or triggering other
module functions, as well as the connections to the interrupt control registers.
Table 6-12
ERU Output Connections in XC2000
Output
from/to
Module
I/O to
OGUy
Can be used to/as
OGU0 Outputs
ERU_
PDOUT0
not connected
O
pattern detection output
ERU_
GOUT0
ADC0 (REQGT0A)
ADC0 (REQGT1A)
ADC0 (REQGT2A)
ADC1 (REQGT0A)
ADC1 (REQGT1A)
ADC1 (REQGT2A)
O
gated pattern detection output
ERU_
TOUT0
not connected
O
trigger output
ERU_
IOUT0
ITC (CC2CC16IC)
O
interrupt output
OGU1 Outputs
ERU_
PDOUT1
not connected
O
pattern detection output
ERU_
GOUT1
ADC0 (REQGT0B)
ADC0 (REQGT1B)
ADC0 (REQGT1B)
ADC1 (REQGT0B)
ADC1 (REQGT1B)
ADC1 (REQGT1B)
O
gated pattern detection output
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System Control Unit (SCU)
Table 6-12
ERU Output Connections in XC2000 (cont’d)
Output
from/to
Module
I/O to
OGUy
Can be used to/as
ERU_
TOUT1
ADC0 (REQTR0A)
ADC0 (REQTR1A)
ADC0 (REQTR2A)
ADC1 (REQTR0A)
ADC1 (REQTR1A)
ADC1 (REQTR2A)
O
trigger output
ERU_
IOUT1
ITC (CC2CC17IC)
O
interrupt output
OGU2 Outputs
ERU_
PDOUT2
not connected
O
pattern detection output
ERU_
GOUT2
not connected
O
gated pattern detection output
ERU_
TOUT2
not connected
O
trigger output
ERU_
IOUT2
ITC (CC2CC18IC)
O
interrupt output
OGU3 Outputs
ERU_
PDOUT3
not connected
O
pattern detection output
ERU_
GOUT3
not connected
O
gated pattern detection output
ERU_
TOUT3
not connected
O
trigger output
ERU_
IOUT3
ITC (CC2CC19IC)
O
interrupt output
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6.4.8
ERU Registers
6.4.8.1
External Input Selection Register EXISEL
This register selects the A and B inputs for all four ERS units. The possible inputs are
given in Table 6-10.
EXISEL
External Input Select Register ESFR (F1A0H/D0H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
EXS3B
EXS3A
EXS2B
EXS2A
EXS1B
EXS1A
EXS0B
EXS0A
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
EXS0A [1:0]
rw
External Source Select for A0 (ERS0)
This bit field defines which input is selected for A0.
00B Input ERU_0A0 is selected
01B Input ERU_0A1 is selected
10B Input ERU_0A2 is selected
11B Input ERU_0A3 is selected
EXS0B [3:2]
rw
External Source Select for B0 (ERS0)
This bit field defines which input is selected for B0.
00B Input ERU_0B0 is selected
01B Input ERU_0B1 is selected
10B Input ERU_0B2 is selected
11B Input ERU_0B3 is selected
EXS1A [5:4]
rw
External Source Select for A1 (ERS1)
This bit field defines which input is selected for A1.
00B Input ERU_1A0 is selected
01B Input ERU_1A1 is selected
10B Input ERU_1A2 is selected
11B Input ERU_1A3 is selected
EXS1B [7:6]
rw
External Source Select for B1 (ERS1)
This bit field defines which input is selected for B1.
00B Input ERU_1B0 is selected
01B Input ERU_1B1 is selected
10B Input ERU_1B2 is selected
11B Input ERU_1B3 is selected
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Field
Bits
EXS2A [9:8]
System Control Unit (SCU)
Type Description
rw
External Source Select for A2 (ERS2)
This bit field defines which input is selected for A2.
00B Input ERU_2A0 is selected
01B Input ERU_2A1 is selected
10B Input ERU_2A2 is selected
11B Input ERU_2A3 is selected
EXS2B [11:10] rw
External Source Select for B2 (ERS2)
This bit field defines which input is selected for B2.
00B Input ERU_2B0 is selected
01B Input ERU_2B1 is selected
10B Input ERU_2B2 is selected
11B Input ERU_2B3 is selected
EXS3A [13:12] rw
External Source Select for A3 (ERS3)
This bit field defines which input is selected for A3.
00B Input ERU_3A0 is selected
01B Input ERU_3A1 is selected
10B Input ERU_3A2 is selected
11B Input ERU_3A3 is selected
EXS3B [15:14] rw
External Source Select for B3 (ERS3)
This bit field defines which input is selected for B3.
00B Input ERU_3B0 is selected
01B Input ERU_3B1 is selected
10B Input ERU_3B2 is selected
11B Input ERU_3B3 is selected
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6.4.8.2
System Control Unit (SCU)
External Input Control Registers EXICONx
These registers control the inputs of the ERSx unit and the trigger functions of the ETLx
units (x = 0..3).
EXICON0
External Input Control 0 Register
ESFR (F030H/18H)
EXICON1
External Input Control 1 Register
ESFR (F032H/19H)
EXICON2
External Input Control 2 Register
ESFR (F034H/1AH)
EXICON3
External Input Control 3 Register
ESFR (F036H/1CH)
15
14
13
12
11
10
9
8
7
0
NB
NA
SS
FL
r
rw
rw
rw
rwh
6
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
5
4
3
2
1
0
OCS
FE
RE
LD
PE
rw
rw
rw
rw
rw
Field
Bits
Type
Description
PE
0
rw
Output Trigger Pulse Enable for ETLx
This bit enables the generation of an output trigger
pulse at TRxy when the selected edge is detected
(set condition for the status flag FL).
0B
The trigger pulse generation is disabled
1B
The trigger pulse generation is enabled
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System Control Unit (SCU)
Field
Bits
Type
Description
LD
1
rw
Rebuild Level Detection for Status Flag for ETLx
This bit selects if the status flag FL is used as “sticky”
bit or if it rebuilds the result of a level detection.
0B
The status flag FL is not cleared by hardware
and is used as “sticky” bit. Once set, it is not
influenced by any edge until it becomes
cleared by software.
1B
The status flag FL rebuilds a level detection of
the desired event. It becomes automatically set
with a rising edge if RE = 1 or with a falling
edge if FE = 1. It becomes automatically
cleared with a rising edge if RE = 0 or with a
falling edge if FE = 0.
RE
2
rw
Rising Edge Detection Enable ETLx
This bit enables/disables the rising edge event as
edge event as set condition for the status flag FL or
as possible trigger pulse for TRxy.
A rising edge is not considered as edge event
0B
1B
A rising edge is considered as edge event
FE
3
rw
Falling Edge Detection Enable ETLx
This bit enables/disables the falling edge event as
edge event as set condition for the status flag FL or
as possible trigger pulse for TRxy.
0B
A falling edge is not considered as edge event
1B
A falling edge is considered as edge event
OCS
[6:4]
rw
Output Channel Select for ETLx Output Trigger
Pulse
This bit field defines which Output Channel OGUy is
targeted by an enabled trigger pulse TRxy.
000B Trigger pulses are sent to OGU0
001B Trigger pulses are sent to OGU1
010B Trigger pulses are sent to OGU2
011B Trigger pulses are sent to OGU3
1XXB Reserved, do not use this combination
FL
7
rwh
Status Flag for ETLx
This bit represents the status flag that becomes set
or cleared by the edge detection.
0B
The enabled edge event has not been
detected
1B
The enabled edge event has been detected
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System Control Unit (SCU)
Field
Bits
Type
Description
SS
[9:8]
rw
Input Source Select for ERSx
This bit field defines which logical combination is
taken into account as ESRxO.
00B Input A without additional combination
01B Input B without additional combination
10B Input A OR input B
11B Input A AND input B
NA
10
rw
Input A Negation Select for ERSx
This bit selects the polarity for the input A.
Input A is used directly
0B
1B
Input A is inverted
NB
11
rw
Input B Negation Select for ERSx
This bit selects the polarity for the input B.
0B
Input B is used directly
1B
Input B is inverted
0
[15:12] r
User’s Manual
SCU, V1.1
Reserved
Read as 0; should be written with 0.
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6.4.8.3
System Control Unit (SCU)
Output Control Registers EXOCONy
These registers control the outputs of the Output Gating Unit y (y = 0..3).
EXOCON0
External Output Trigger Control 0 Register
SFR (FE30H/18H)
EXOCON1
External Output Trigger Control 1 Register
SFR (FE32H/19H)
EXOCON2
External Output Trigger Control 2 Register
SFR (FE34H/1AH)
EXOCON3
External Output Trigger Control 3 Register
SFR (FE36H/1CH)
15
14
13
12
11
IPEN IPEN IPEN IPEN
3
2
1
0
rw
rw
rw
rw
10
9
8
7
6
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
5
4
3
2
1
0
0
GP
PDR
GE
EN
ISS
r
rw
rh
rw
rw
Field
Bits
Type
Description
ISS
[1:0]
rw
Internal Trigger Source Selection
This bit field defines which input is selected as
peripheral trigger input for OGUy. The possible inputs
are given in Table 6-11.
00B The peripheral trigger function is disabled
01B Input ERU_OGUy1 is selected
10B Input ERU_OGUy2 is selected
11B Input ERU_OGUy3 is selected
GEEN
2
rw
Gating Event Enable
Bit GEEN enables the generation of a trigger event
when the result of the pattern detection changes from
match to miss or vice-versa.
0B
The event detection is disabled
1B
The event detection is enabled
PDR
3
rh
Pattern Detection Result Flag
This bit represents the pattern detection result.
0B
A pattern miss is detected
1B
A pattern match is detected
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System Control Unit (SCU)
Field
Bits
Type
Description
GP
[5:4]
rw
Gating Selection for Pattern Detection Result
This bit field defines the gating scheme for the interrupt
generation (relation between the OGU output
ERU_PDOUTy and ERU_GOUTy).
00B ERU_GOUTy is always disabled and
ERU_IOUTy can not be activated
01B ERU_GOUTy is always enabled and ERU_IOUTy
becomes activated with each activation of
ERU_TOUTy
10B ERU_GOUTy is equal to ERU_PDOUTy and
ERU_IOUTy becomes activated with an activation
of ERU_TOUTy while the desired pattern is
detected (pattern match PDR = 1)
11B ERU_GOUTy is inverted to ERU_PDOUTy and
ERU_IOUTy becomes activated with an activation
of ERU_TOUTy while the desired pattern is not
detected (pattern miss PDR = 0)
IPENx
(x = 0-3)
12+x
rw
Pattern Detection Enable for ETLx Input
Bit IPENx defines whether the trigger event status flag
EXICONx.FL of ETLx takes part in the pattern detection
of OGUy.
Flag EXICONx.FL is excluded from the pattern
0B
detection
1B
Flag EXICONx.FL is included in the pattern
detection
0
[11:6]
r
Reserved
Read as 0; should be written with 0.
User’s Manual
SCU, V1.1
6-89
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.5
System Control Unit (SCU)
Power Supply and Control
The XC2000 can run from a single external power supply. The core supply voltages can
be generated by on-chip Embedded Voltage Regulators (EVRs) or can be fed in from an
external Voltage Regulator (VR). To significantly reduce the consumed leakage current
special power states directly considered for power saving are implemented. The major
part of the on-chip logic is located in an independent core power domain (DMP_1),
marked green and white in Figure 6-25. A second, smaller power domain (DMP_M),
marked grey, controls wake-up mechanism and other important device infrastructure
plus a Standby RAM (SB_RAM). Additionally the I/O part is divided in two parts
DMP_IO_0 and DMP_IO_1. DMP_IO_0 contains all ADC related I/Os and DMP_IO_1
the remaining system and communication I/Os. The DMP_M and/or DMP_1 can be
either switched off, i.e. disconnected from power by disabling the respective EVR1 or
lowered to 1.0 V.
The power supply and control is divided into two parts:
•
•
monitoring of the supply level
controlling and adjusting the supply level
The supply voltage of power domain DMP_IO_0 is monitored by a Supply WatchDog
(SWD, see Chapter 6.5.1).
The core voltage for each of the two core supply domains is supervised by a separate
Power Validation Circuit (PVC) that provides two monitoring levels. Each monitoring
level can request an interrupt (e.g. power-fail warning) or a reset in case of an invalid
voltage level. Device damage caused by power problems such as overcurrent due to an
external short-cut must be avoided. The PVCs are used to indicate such problems, so
together with some time-limit, the system can be protected from being damaged (see
Chapter 6.5.2).
By controlling the regulator, a core power domain can be switched off to save the
leakage current within this area (see Chapter 6.5.3.1).
Table 6-13
XC2000 Power Domains
Power Domain
Supply Source
Supply Voltage
[V]
Supply
Checked by
Pad IO domain
(DMP_IO_0)
External supply
see the data sheet
SWD
ADC IO domain
(DMP_IO_1)
External supply
see the data sheet
-
Wake-up domain
(DMP_M)
EVR_M
see the data sheet
PVC_M
System domain (DMP_1)
EVR_1
see the data sheet
PVC_1
User’s Manual
SCU, V1.1
6-90
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
GS C
Reset Power OS C_
Control Control WU
OSC_
HP
Clock Temp.
Control Comp.
SCU
PSRAM
64 Kbytes
P rogram Flash 0
256 Kbytes
CP U
WDT
P EC/
INT
IMB
E SR/
ERU
DP RAM
2 Kbytes
PMU
PLL
DS RAM
16 Kbytes
DMU
P rogram Flash 2
256 Kbytes
Stand-By RAM
1 Kbytes
LXB us
EBC
LXB us Control
External B us
Control
OCDS
Debug S upport
Peripheral
Data Bus
ADC
ADC
8-Bit/ 8-Bit/
10-Bit 10-Bit
8 Ch. 16 Ch.
P rogram Flash 1
256 Kbytes
GPT
LXBus
... CCU60
CC2
CCU63
T7
T12
T12
T8
T13
T13
USIC2 USIC1 USIC0
2 Ch., 2 Ch., 2 Ch.,
64 x
64 x
64 x
Buffer Buffer Buffer
T2
T3
T4
Multi
CAN
RTC
RS232, RS232, RS232,
LIN,
LIN,
LIN,
SPI,
SPI,
SPI,
IIC, IIS IIC, IIS IIC, IIS
T5
T6
BRGen
5 ch.
Ports
P 15
P ort 5
P 11
8
16
6
P10
16
P9
P8
8
7
P7 P 6
5
4
P4
P3
8
8
P2
13
P1
8
P0
8
MC_XC2X_BLOCKDIAGRAM_DK
Figure 6-25 XC2000 Power Domain Structure
6.5.1
Supply Watchdog (SWD)
The supply voltage of IO domain DMP_IO_0 is monitored to validate the overall power
supply. The external supply voltage is monitored for three purposes:
•
•
•
Detecting the ramp-up of the external supply voltage, so the device can be started
without requiring an external power-on reset (PORST).
Detecting the ramp-down of the external supply voltage, so the device can be brought
into a save state without requiring an external power-on reset (PORST).
Monitoring the external power supply allows the usage of a a low-cost regulator
without additional status inputs (standard 3-pin device).
User’s Manual
SCU, V1.1
6-91
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Feature list
The following list is a summery of the SWD functions.
•
•
•
•
•
Power-on reset, if supply is below VVAL
Two completely independent threshold levels and comparators
16 selectable threshold levels
Power Saving Mode (only VVAL detection active)
Spike filter for VDD noise suppression
Operating the SWD
VOP
VLEV2
VLEV1
VVAL
VSS
0V
start-up
reset
L2OK
L1OK
Power-Off
Power-On Operation
Operation
Operation
Fail
Warning
Power-Off
Figure 6-26 SWD Power Validation Example
User’s Manual
SCU, V1.1
6-92
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
The lower fix threshold VVAL defines the absolute minimum operation voltage for the IO
domain. If VVAL has not been reached the device is held in reset via the start-up reset.
When VDDP becomes greater as VVAL bit SWDCON1.PON is cleared.
Note: The physical value for VVAL can found in the XC2000 data sheet.
The SWD provides two adjustable threshold levels (LEV1 and LEV2) that can be
individually programmed, via SWDCON0.LEV1V and SWDCON0.LEV2V, and deliver a
compare value each. The two compare results can be monitored via bits
SWDCON0.L1OK and SWDCON0.L2OK. A reset or interrupt request can be generated
while the voltage level is below or equal/above the configured level of a threshold. If an
action and which action is triggered by each threshold can be configured via bit field
SWDCON0.LxACON and SWDCON0.LxALEV (x = 1,2).
Note: Both threshold compare levels should not be used as reset level at the same time.
Due to the wide operating range, the selectable threshold levels are distributed nonlinear to match application requirements with design constraints.
VDD [V]
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
Levels
Figure 6-27 Threshold Levels for Supply Voltage Supervision by SWD
The SWD control (programming of the threshold levels) is done by software only.
With these features, an external supply watchdog, e.g. integrated in some external VR,
can be replaced. It detects the minimum specified supply voltage level and can be
configured to monitor other voltage levels.
Note: If the PORST pin is used it has the same functionality as the SWD.
Power-Saving Mode of the SWD
The two configurable thresholds which its different functions can be disabled if not
needed. This is called the SWD Power Saving Mode. Please note that the minimum
operating voltage detection can never be disabled and it is always active. The SWD
Power Saving Mode is entered by setting bit SWDCON1.POWENSET and left by setting
bit SWDCON1.POWENCLR. If the SWD Power Saving Mode is active or not can be
monitored via bit SWDCON1.POWEN.
User’s Manual
SCU, V1.1
6-93
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.5.1.1
System Control Unit (SCU)
SWD Control Registers
The following registers are the software interface for the SWD.
SWDCON0
SWD Control 0 Register
15
14
11
ESFR (F080H/40H)
10
9
8
7
Reset Value: 0941H
13
12
6
5
4
3
2
1
L2A
LEV
L2ACON
L2
OK
LEV2V
L1A
LEV
L1ACON
L1
OK
LEV1V
rw
rw
rh
rw
rw
rw
rh
rw
0
Field
Bits
Type
Description
LEV1V
[3:0]
rw
Level Threshold 1 Voltage
This bit field defines the voltage level that is used as
threshold 1 check level.
The values of the level thresholds are listed in the
data sheet.
L1OK
4
rh
Level Threshold 1 Check Ok Status
0B
The supply voltage is below level threshold 1
The supply voltage is equal or higher than level
1B
threshold 1
L1ACON
[6:5]
rw
Level Threshold 1 Action Control
This bit field defines which action is requested if the
condition is violated (voltage is below the defined
level threshold 1).
00B No action is requested
01B An interrupt is requested
10B A reset request is generated
11B A reset and interrupt request is generated
L1ALEV
7
rw
Level threshold 1 Action Level
0B
The action configured by bit field L1ACON is
requested when the voltage is below LEV1V.
Otherwise no action is requested.
1B
The action configured by bit field L1ACON is
requested when the voltage is equal or above
LEV1V. Otherwise no action is requested.
User’s Manual
SCU, V1.1
6-94
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
LEV2V
[11:8]
rw
Level Threshold 2 Voltage
This bit field defines the voltage level that is used as
check level threshold 2.
The values of the level thresholds are listed in the
data sheet.
L2OK
12
rh
Level Threshold 2 Check Ok Status
0B
The supply voltage is below the selected level
threshold 2
1B
The supply voltage is equal or higher than the
selected level threshold 2
L2ACON
[14:13] rw
Level Threshold 2 Action Control
This bit field defines for which action is requested if
the condition is violated (voltage is below the defined
level threshold 2).
00B No action is requested
01B An interrupt is requested
10B A reset request is generated
11B A reset and interrupt request is generated
L2ALEV
15
Level Threshold 2 Action Level
0B
The action configured by bit field L2ACON is
requested when the voltage is below LEV2V.
Otherwise no action is requested.
1B
The action configured by bit field L2ACON is
requested when the voltage is equal or above
LEV2V. Otherwise no action is requested.
rw
SWDCON1
SWD Control 1 Register
15
14
13
12
11
ESFR (F082H/41H)
10
9
8
7
5
4
3
2
1
0
POW POW
CLR
POW
PON
EN EN
PON
EN
SET CLR
w
rh
rh
w
w
0
r
User’s Manual
SCU, V1.1
6
Reset Value: 0000H
6-95
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
POWENCLR
0
w
SWD Power Saving Mode Enable Clear
0B
Clearing this bit has no effect
1B
Setting this bit clears bit POWEN
Reading this bit returns always zero.
POWENSET
1
w
SWD Power Saving Mode Enable Set
Clearing this bit has no effect
0B
1B
Setting this bit set bit POWEN
Reading this bit returns always zero.
POWEN
2
rh
SWD Power Saving Mode Enable
0B
The SWD Power Saving Mode is disabled
1B
The SWD Power Saving Mode is enabled
PON
3
rh
Power-On Status Flag
0B
No power-on event occurred
A power-on event occurred
1B
CLRPON
4
w
Clear Power-On Status Flag
0B
Bit PON is not changed
1B
Bit PON is cleared
0
[15:5]
r
Reserved
Read as 0; should be written with 0.
User’s Manual
SCU, V1.1
6-96
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.5.2
System Control Unit (SCU)
Monitoring the Voltage Level of a Core Domain
The voltage of core domain DMP_M is monitored by the PVC_M. The core domain
DMP_M is marked in grey within Figure 6-25.
The voltage of core domain DMP_1 is monitored by the PVC_1. The core domain
DMP_1 is marked in green and white within Figure 6-25.
A Power Validation Circuit (PVC) monitors the internal core supply voltage of a core
domain. It can be configured to monitor two programmable independent voltage levels.
Feature list
The following list summarizes the features of a PVC.
•
•
•
•
Two completely independent comparators
Voltage levels selectable
Shut-off, which disables the complete module
Configurable level action selection
The PVC provides two adjustable threshold levels (LEV1 and LEV2) that can be
individually programmed, via PCVxCON0.LEV1V and PVCxCON0.LEV2V (x = M or 1),
and deliver a compare value each. The two compare results can be monitored via bits
PVCxCON0.L1OK and PVCxCON0.L2OK (x = M or 1). A reset or interrupt request can
be generated while the voltage level is below or equal / above the configured level of a
threshold. An interrupt is requested if bit PVCxCON0.L1INTEN and / or
PVCxCON0.L2INTEN (x = M or 1) is set. A reset is requested if bit
PVCxCON0.L1RSTEN and / or PVCxCON0.L2RSTEN (x = M or 1) is set. Additionally a
threshold can be used to generate an asynchronous trigger for the PSC (see
Chapter 6.5.2). An asynchronous trigger is generated if bit PVCxCON0.L1ASEN
and / or PVCxCON0.L2ASEN (x = M or 1) is set
Note: Both compare level should not be used as reset level at the same time.
Note: For a single threshold both interrupt and reset request generation should not be
enabled at the same time.
User’s Manual
SCU, V1.1
6-97
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.5.2.1
System Control Unit (SCU)
PVC Status and Control Registers
These registers are the software interface for the PVCs.
PVCMCON0
PVC_M Control Step 0 Register
ESFR (F1E4H)
15
14
13
12
11
10
L2R
L2A
L2IN L2A LEV
STE
SEN
TEN LEV 2OK
N
rwh rwh rwh rwh rh
9
LEV2V
rwh
8
7
Reset Value: 0544H
6
5
4
3
L1R
L1A
L1IN L1A LEV
STE
SEN
TEN LEV 1OK
N
rwh rwh rwh rwh rh
2
1
0
LEV1V
rwh
Field
Bits
Type
Description
LEV1V
[2:0]
rwh
Level Threshold 1 Voltage Configuration
This bit field defines the level of threshold 1 that is
compared with the DMP_M core voltage.
The values for the different configurations are listed
in the data sheet.
LEV1OK
3
rh
Level Threshold 1 Check Result
0B
The core voltage of the DMP_M is below the
configured level of threshold 1
1B
The core voltage of the DMP_M is equal or
above the configured level of threshold 1
L1ALEV
4
rwh
Level Threshold 1 Action Level
0B
The action configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the core voltage is below LEV1V. Otherwise no
action is requested.
1B
The actions configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the core voltage is equal or above LEV1V.
Otherwise no action is requested.
L1INTEN
5
rwh
Level Threshold 1 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison check was successful.
When a check is successful is defined via bit
L1ALEV.
0B
No interrupt is requested
1B
An interrupt is requested
User’s Manual
SCU, V1.1
6-98
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L1RSTEN
6
rwh
Level Threshold 1 Reset Request Enable
This bit defines if a reset request trigger is requested
if the comparison check was successful. When a
check is successful is defined via bit L1ALEV.
0B
No reset is requested
1B
An reset is requested
L1ASEN
7
rwh
Level Threshold 1 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison check was successful.
When a check is successful is defined via bit
L1ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
LEV2V
[10:8]
rwh
Level Threshold 2 Voltage Configuration
This bit field defines the level of threshold 2 that is
compared with the DMP_M core voltage.
The values for the different configurations are listed
in the data sheet.
LEV2OK
11
rh
Level Threshold 2 Check Result
0B
The core voltage of the DMP_M is below the
configured level of threshold 2
1B
The core voltage of the DMP_M is equal or
above the configured level of threshold 2
L2ALEV
12
rwh
Level Threshold 2 Action Level
0B
The action configured by bits L2INTEN,
L2RSTEN, and L2ASEN are requested when
the core voltage is below LEV2V. Otherwise no
action is requested.
The action configured by bits L2INTEN,
1B
L2RSTEN, and L2ASEN are requested when
the core voltage is equal or above LEV2V.
Otherwise no action is requested.
L2INTEN
13
rwh
Level Threshold 2 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison check was successful.
When a check is successful is defined via bit
L2ALEV.
No interrupt is requested
0B
1B
An interrupt is requested
User’s Manual
SCU, V1.1
6-99
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L2RSTEN
14
rwh
Level Threshold 2 Reset Request Enable
This bit defines if a reset request trigger is requested
if the comparison check was successful. When a
check is successful is defined via bit L2ALEV.
0B
No reset is requested
1B
An reset is requested
L2ASEN
15
rwh
Level Threshold 2 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison check was successful.
When a check is successful is defined via bit
L2ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
PVC1CON0
PVC_1 Control Step 0 Register
ESFR (F014H/0AH)
15
14
13
12
11
10
L2R
L2A
L2IN L2A LEV
STE
SEN
TEN LEV 2OK
N
rwh rwh rwh rwh rh
9
LEV2V
rwh
8
7
6
Reset Value: 0504H
5
4
3
L1R
L1A
L1IN L1A LEV
STE
SEN
TEN LEV 1OK
N
rwh rwh rwh rwh rh
2
1
0
LEV1V
rwh
Field
Bits
Type
Description
LEV1V
[2:0]
rwh
Level Threshold 1 Voltage Configuration
This bit field defines the level of threshold 1 that is
compared with the DMP_1 core voltage.
The values for the different configurations are listed
in the data sheet.
LEV1OK
3
rh
Level Threshold 1 Check Result
0B
The core voltage of the DMP_1 is below the
configured threshold level 1
1B
The core voltage of the DMP_1 is equal or
above the configured threshold level 1
User’s Manual
SCU, V1.1
6-100
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L1ALEV
4
rwh
Level Threshold 1 Action Level
0B
The action configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the core voltage is below LEV1V. Otherwise no
action is requested.
1B
The actions configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the core voltage is equal or above LEV1V.
Otherwise no action is requested.
L1INTEN
5
rwh
Level Threshold 1 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison check was successful.
When a check is successful is defined via bit
L1ALEV.
0B
No interrupt is requested
An interrupt is requested
1B
L1RSTEN
6
rwh
Level Threshold 1 Reset Request Enable
This bit defines if a reset request trigger is requested
if the comparison check was successful. When a
check is successful is defined via bit L1ALEV.
0B
No reset is requested
1B
An reset is requested
L1ASEN
7
rwh
Level Threshold 1 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison check was successful.
When a check is successful is defined via bit
L1ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
LEV2V
[10:8]
rwh
Level Threshold 2 Voltage Configuration
This bit field defines the level of threshold 2 that is
compared with the DMP_1 core voltage.
The values for the different configurations are listed
in the data sheet.
LEV2OK
11
rh
Level Threshold 2 Check Result
0B
The core supply voltage of the DMP_1 is below
the configured threshold level 2
1B
The core supply voltage of the DMP_1 is equal
or above the configured threshold level 2
User’s Manual
SCU, V1.1
6-101
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L2ALEV
12
rwh
Level Threshold 2 Action Level
0B
The action configured by bits L2INTEN,
L2RSTEN, and L2ASEN are requested when
the voltage is below LEV2V. Otherwise no
action is requested.
1B
The action configured by bits L2INTEN,
L2RSTEN, and L2ASEN are requested when
the voltage is equal or above LEV2V.
Otherwise no action is requested.
L2INTEN
13
rwh
Level Threshold 2 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison check was successful.
When a check is successful is defined via bit
L2ALEV.
0B
No interrupt is requested
An interrupt is requested
1B
L2RSTEN
14
rwh
Level Threshold 2 Reset Request Enable
This bit defines if a reset request trigger is requested
if the comparison check was successful. When a
check is successful is defined via bit L2ALEV.
0B
No reset is requested
1B
An reset is requested
L2ASEN
15
rwh
Level Threshold 2 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison check was successful.
When a check is successful is defined via bit
L2ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
User’s Manual
SCU, V1.1
6-102
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
PVCMCONA1
PVC_M Control for Step 1 Set A Register
ESFR (F1E6H)
PVCMCONA2
PVC_M Control for Step 2 Set A Register
ESFR (F1E8H)
PVCMCONA3
PVC_M Control for Step 3 Set A Register
ESFR (F1EAH)
PVCMCONA4
PVC_M Control for Step 4 Set A Register
ESFR (F1ECH)
PVCMCONA5
PVC_M Control for Step 5 Set A Register
ESFR (F1EEH)
PVCMCONA6
PVC_M Control for Step 6 Set A Register
ESFR (F1F0H)
15
14
13
12
L2R
L2A
L2IN L2A
STE
SEN
TEN LEV
N
rw
rw
rw
rw
11
10
9
0
LEV2V
r
rw
8
7
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
6
5
4
L1R
L1A
L1IN L1A
STE
SEN
TEN LEV
N
rw
rw
rw
rw
3
2
1
0
LEV1V
r
rw
0
Field
Bits
Type
Description
LEV1V
[2:0]
rw
Level Threshold 1 Voltage Configuration
This bit field defines the level of threshold 1 that is
compared with the DMP_M core voltage.
The values for the different configurations are listed
in the data sheet.
L1ALEV
4
rw
Level Threshold 1 Action Level
0B
The action configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the voltage is below LEV1V. Otherwise no
action is requested.
1B
The action configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the voltage is equal or above LEV1V.
Otherwise no action is requested.
User’s Manual
SCU, V1.1
6-103
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L1INTEN
5
rw
Level Threshold 1 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison check was successful.
When a check is successful is defined via bit
L1ALEV.
No interrupt is requested
0B
1B
An interrupt is requested
L1RSTEN
6
rw
Level Threshold 1 Reset Request Enable
This bit defines if a reset request trigger is requested
if the comparison check was successful. When a
check is successful is defined via bit L1ALEV.
0B
No reset is requested
1B
An reset is requested
L1ASEN
7
rw
Level Threshold 1 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison check was successful.
When a check is successful is defined via bit
L1ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
LEV2V
[10:8]
rw
Level Threshold 2 Voltage Configuration
This bit field defines the level of threshold 2 that is
compared with the DMP_M core voltage.
The values for the different configurations are listed
in the data sheet.
L2ALEV
12
rw
Level Threshold 2 Action Level
0B
The action configured by bits L2INTEN,
L2RSTEN, and L2ASEN are requested when
the voltage is below LEV2V. Otherwise no
action is requested.
1B
The action configured by bits L2INTEN,
L2RSTEN, and L2ASEN are requested when
the voltage is equal or above LEV2V.
Otherwise no action is requested.
User’s Manual
SCU, V1.1
6-104
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L2INTEN
13
rw
Level Threshold 2 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison check was successful.
When a check is successful is defined via bit
L2ALEV.
No interrupt is requested
0B
1B
An interrupt is requested
L2RSTEN
14
rw
Level Threshold 2 Reset Request Enable
This bit defines if a reset request trigger is requested
if the comparison check was successful. When a
check is successful is defined via bit L2ALEV.
0B
No reset is requested
1B
An reset is requested
L2ASEN
15
rw
Level Threshold 2 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison check was successful.
When a check is successful is defined via bit
L2ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
0
3, 11
rw
Reserved
Should be written with 0.
User’s Manual
SCU, V1.1
6-105
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
PVC1CONA1
PVC_1 Control for Step 1Set A Register
ESFR (F016H/0BH)
PVC1CONA2
PVC_1 Control for Step 2 Set A Register
ESFR (F018H/0CH)
PVC1CONA3
PVC_1 Control for Step 3 Set A Register
ESFR (F01AH/0DH)
PVC1CONA4
PVC_1 Control for Step 4 Set A Register
ESFR (F01CH/0EH)
PVC1CONA5
PVC_1 Control for Step 5 Set A Register
ESFR (F01EH/0FH)
PVC1CONA6
PVC_1 Control for Step 6 Set A Register
ESFR (F020H/10H)
15
14
13
12
L2R
L2A
L2IN L2A
STE
SEN
TEN LEV
N
rw
rw
rw
rw
11
10
9
0
LEV2V
r
rw
8
7
6
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
5
4
L1R
L1A
L1IN L1A
STE
SEN
TEN LEV
N
rw
rw
rw
rw
3
2
1
0
LEV1V
r
rw
0
Field
Bits
Type
Description
LEV1V
[2:0]
rw
Level Threshold 1 Voltage Configuration
This bit field defines the level of threshold 1 that is
compared with the DMP_1 core voltage.
The values for the different configurations are listed
in the data sheet.
L1ALEV
4
rw
Level Threshold 1 Action Level
0B
The action configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the voltage is below LEV1V. Otherwise no
action is requested.
1B
The action configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the voltage is equal or above LEV1V.
Otherwise no action is requested.
User’s Manual
SCU, V1.1
6-106
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L1INTEN
5
rw
Level Threshold 1 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison check was successful.
When a check is successful is defined via bit
L1ALEV.
No interrupt is requested
0B
1B
An interrupt is requested
L1RSTEN
6
rw
Level Threshold 1 Reset Request Enable
This bit defines if a reset request trigger is requested
if the comparison check was successful. When a
check is successful is defined via bit L1ALEV.
0B
No reset is requested
1B
An reset is requested
L1ASEN
7
rw
Level Threshold 1 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison check was successful.
When a check is successful is defined via bit
L1ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
LEV2V
[10:8]
rw
Level 2 Voltage Configuration
This bit field defines the level of threshold 2 that is
compared with the DMP_1 core voltage.
The values for the different configurations are listed
in the data sheet.
L2ALEV
12
rw
Level Threshold 2 Action Level
0B
The action configured by bits L2INTEN,
L2RSTEN, and L2ASEN are requested when
the voltage is below LEV2V. Otherwise no
action is requested.
1B
The action configured by bits L2INTEN,
L2RSTEN, and L2ASEN are requested when
the voltage is equal or above LEV2V.
Otherwise no action is requested.
User’s Manual
SCU, V1.1
6-107
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L2INTEN
13
rw
Level Threshold 2 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison check was successful.
When a check is successful is defined via bit
L2ALEV.
No interrupt is requested
0B
1B
An interrupt is requested
L2RSTEN
14
rw
Level Threshold 2 Reset Request Enable
This bit defines if a reset request trigger is requested
if the comparison check was successful. When a
check is successful is defined via bit L2ALEV.
0B
No reset is requested
1B
An reset is requested
L2ASEN
15
rw
Level Threshold 2 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison check was successful.
When a check is successful is defined via bit
L2ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
0
3, 11
rw
Reserved
Should be written with 0.
User’s Manual
SCU, V1.1
6-108
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
PVCMCONB1
PVC_M Control for Step 1 Set B Register
ESFR (F1F4H)
PVCMCONB2
PVC_M Control for Step 2 Set B Register
ESFR (F1F6H)
PVCMCONB3
PVC_M Control for Step 3 Set B Register
ESFR (F1F8H)
PVCMCONB4
PVC_M Control for Step 4 Set B Register
ESFR (F1FAH)
PVCMCONB5
PVC_M Control for Step 5 Set B Register
ESFR (F1FCH)
PVCMCONB6
PVC_M Control for Step 6 Set B Register
ESFR (F1FEH)
15
14
13
12
L2R
L2A
L2IN L2A
STE
SEN
TEN LEV
N
rw
rw
rw
rw
11
10
9
0
LEV2V
r
rw
8
7
Reset Value: 0544H
Reset Value: 0544H
Reset Value: 0544H
Reset Value: 0544H
Reset Value: 0544H
Reset Value: 0544H
6
5
4
L1R
L1A
L1IN L1A
STE
SEN
TEN LEV
N
rw
rw
rw
rw
3
2
1
0
LEV1V
r
rw
0
Field
Bits
Type
Description
LEV1V
[2:0]
rw
Level 1 Voltage Configuration
This bit field defines the level that is used by the
comparator 1 in the PVC.
The values for the different configurations are listed
in the data sheet.
L1ALEV
4
rw
Level 1 Action Level
0B
The action configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the voltage is below LEV1V. Otherwise no
action is requested.
1B
The actions configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the voltage is equal or above LEV1V.
Otherwise no action is requested.
User’s Manual
SCU, V1.1
6-109
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L1INTEN
5
rw
Level 1 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison level check was
successful. When a check is successful is defined via
bit L1ALEV.
No interrupt is requested
0B
1B
An interrupt is requested
L1RSTEN
6
rw
Level 1 Reset Request Enable
This bit defines if an reset request trigger is
requested if the comparison level check was
successful. When a check is successful is defined via
bit L1ALEV.
0B
No reset is requested
1B
An reset is requested
L1ASEN
7
rw
Level 1 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison level check was
successful. When a check is successful is defined via
bit L1ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
LEV2V
[10:8]
rw
Level 2 Voltage Configuration
This bit field defines the level that is used by the
comparator 2 in the PVC.
The values for the different configurations are listed
in the data sheet.
L2ALEV
12
rw
Level 2 Action Level
0B
The action configured by bits L2INTEN,
L2RSTEN, and L2ASEN are requested when
the voltage is below LEV2V. Otherwise no
action is requested.
The action configured by bits L2INTEN,
1B
L2RSTEN, and L2ASEN are requested when
the voltage is equal or above LEV2V.
Otherwise no action is requested.
User’s Manual
SCU, V1.1
6-110
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L2INTEN
13
rw
Level 2 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison level check was
successful. When a check is successful is defined via
bit L2ALEV.
No interrupt is requested
0B
1B
An interrupt is requested
L2RSTEN
14
rw
Level 2 Reset Request Enable
This bit defines if an reset request trigger is
requested if the comparison level check was
successful. When a check is successful is defined via
bit L2ALEV.
0B
No reset is requested
1B
An reset is requested
L2ASEN
15
rw
Level 2 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison level check was
successful. When a check is successful is defined via
bit L2ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
0
3, 11
rw
Reserved
Should be written with 0.
User’s Manual
SCU, V1.1
6-111
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
PVC1CONB1
PVC_1 Control for Step 1 Set B Register
ESFR (F024H/12H)
PVC1CONB2
PVC_1 Control for Step 2 Set B Register
ESFR (F026H/13H)
PVC1CONB3
PVC_1 Control for Step 3 Set B Register
ESFR (F028H/14H)
PVC1CONB4
PVC_1 Control for Step 4 Set B Register
ESFR (F02AH/15H)
PVC1CONB5
PVC_1 Control for Step 5 Set B Register
ESFR (F02CH/16H)
PVC1CONB6
PVC_1 Control for Step 6 Set B Register
ESFR (F02EH/17H)
15
14
13
12
L2R
L2A
L2IN L2A
STE
SEN
TEN LEV
N
rw
rw
rw
rw
11
10
9
0
LEV2V
r
rw
8
7
6
Reset Value: 9504H
Reset Value: 0544H
Reset Value: 0544H
Reset Value: 0544H
Reset Value: 0544H
Reset Value: 0544H
5
4
L1R
L1A
L1IN L1A
STE
SEN
TEN LEV
N
rw
rw
rw
rw
3
2
1
0
LEV1V
r
rw
0
Field
Bits
Type
Description
LEV1V
[2:0]
rw
Level 1 Voltage Configuration
This bit field defines the level that is used by the
comparator 1 in the PVC.
The values for the different configurations are listed
in the data sheet.
L1ALEV
4
rw
Level 1 Action Level
0B
The action configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the voltage is below LEV1V. Otherwise no
action is requested.
1B
The actions configured by bits L1INTEN,
L1RSTEN, and L1ASEN are requested when
the voltage is equal or above LEV1V.
Otherwise no action is requested.
User’s Manual
SCU, V1.1
6-112
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L1INTEN
5
rw
Level 1 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison level check was
successful. When a check is successful is defined via
bit L1ALEV.
No interrupt is requested
0B
1B
An interrupt is requested
L1RSTEN
6
rw
Level 1 Reset Request Enable
This bit defines if an reset request trigger is
requested if the comparison level check was
successful. When a check is successful is defined via
bit L1ALEV.
0B
No reset is requested
1B
An reset is requested
L1ASEN
7
rw
Level 1 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison level check was
successful. When a check is successful is defined via
bit L1ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
LEV2V
[10:8]
rw
Level 2 Voltage Configuration
This bit field defines the level that is used by the
comparator 2 in the PVC.
The values for the different configurations are listed
in the data sheet.
L2ALEV
12
rw
Level 2 Action Level
0B
The action configured by bits L2INTEN,
L2RSTEN, and L2ASEN are requested when
the voltage is below LEV2V. Otherwise no
action is requested.
The action configured by bits L2INTEN,
1B
L2RSTEN, and L2ASEN are requested when
the voltage is equal or above LEV2V.
Otherwise no action is requested.
User’s Manual
SCU, V1.1
6-113
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
L2INTEN
13
rw
Level 2 Interrupt Request Enable
This bit defines if an interrupt request trigger is
requested if the comparison level check was
successful. When a check is successful is defined via
bit L2ALEV.
No interrupt is requested
0B
1B
An interrupt is requested
L2RSTEN
14
rw
Level 2 Reset Request Enable
This bit defines if an reset request trigger is
requested if the comparison level check was
successful. When a check is successful is defined via
bit L2ALEV.
0B
No reset is requested
1B
An reset is requested
L2ASEN
15
rw
Level 2 Asynchronous Action Enable
This bit defines if asynchronous action can be
performed if the comparison level check was
successful. When a check is successful is defined via
bit L2ALEV.
0B
No asynchronous actions are performed
1B
Asynchronous actions can be performed
0
3, 11
rw
Reserved
Should be written with 0.
User’s Manual
SCU, V1.1
6-114
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.5.3
System Control Unit (SCU)
Controlling the Voltage Level of a Core Domain
The two core power domains DMP_M and DMP_1 can be controlled individually within
certain limits. The limits are defined by the supported Power States. The voltage level
of each core domain is controlled by an own Embedded Voltage Regulator (EVR).
The core power domain DMP_M is control by the EVR_M.
The core power domain DMP_1 is control by the EVR_1.
6.5.3.1
Power States
Based on the various operating states of the EVRs, several Power Modes are defined in
order to achieve easily a power reduction.
Table 6-14 summarizes the power states based on the respective voltage levels.
Table 6-14
Operating States Based on Supply Voltage
DMP_1
DMP_M
Off
Reduced Voltage
Full Voltage
Reduced
Voltage
Power State A
Power State B
Not Allowed
Full Voltage
Power State F
Power State G
Power State I
6.5.3.2
Embedded Voltage Regulator
An embedded voltage regulator (EVR) provides an stable core supply voltage
Feature list:
•
•
•
•
Regulation with external buffer capacitor
Selectable core voltage levels, including zero
Core voltage generation either based on a Low Power Reference or on a High
Precision Bandgap
External supply possible via capacitor-pin while EVR is off
When the EVR is disabled it tolerate an external supply voltage provided through the pin
VDDI that connects the external buffer capacitor.
The EVR configurations to select the desired voltage and reference pair are combined
within EVR settings EVRxSETyyV (x = M or 1 and yy = 10 or 15). Each setting contains
a bit field (VRSEL) to select the voltage level and reference and a bit field to fine-tune
the voltage level (VLEV). One out of the possible settings is used to control each of the
EVRs, but only in the allowed combinations for the two EVRs. The core voltage
generated by an EVR is derived either from the Low Power Reference (LPR) or from the
High Precision Bandgap (HP).
User’s Manual
SCU, V1.1
6-115
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
The core voltage of each setting can be adjusted to compensate application and
environmental influences. This is control via bit field EVRxSETyyV.VLEV.
Lower Power Reference (LPR)
The LPR of an EVR is used for two purposes:
•
•
Operation in a Power State other than Full Active
Special Power Saving in the Full Active Power State
The LPR can be enabled / disabled via the bit EVRxSETyyV.LPRDIS. If a setting use the
LPR or not is defined via the bit field EVRxSETyyV.VRSEL. Please note that even if bit
EVRxSETyyV.LPRDIS and the bit field EVRxSETyyV.VRVAL are writable this should
not be done, the reset value of the setting registers is already defined in the way the
different setting work.
As the core voltage depends on the LPR the LPR can be adjusted via bit field
EVRxCON0.LPRLEV for application specific fine tuning.
High Precision Bandgap (HP)
The HP bandgap of the system is used for two purposes:
•
•
Provide a very stable reference for the two EVRs when operating in Full Active
Provide a reference for the flash memory. For more information about this point see
the flash memory description.
Only one HP bandgap is implemented which is used by both EVRs. The HP bandgap
can be enabled / disable via the bit EVRMCON1.HPEN.
As the core voltage depends on the HP configuration, the HP bandgap can be adjusted
via bit field EVRMCON1.HPADJUST for application specific fine tuning.
User’s Manual
SCU, V1.1
6-116
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
EVR Status and Control Registers
EVRMCON0
EVR_M Control 0 Register
15
14
13
12
EVR
DIS
rh
11
ESFR (F084H/42H)
10
0
r
rh
rw
6
Reset Value: 0D20H
9
8
7
5
4
3
2
1
LPR
DIS
0
LPRTC
LPRLEV
0
rh
rw
rw
rw
r
0
Field
Bits
Type
Description
LPRLEV
[5:3]
rw
Low Power Reference Level
This bit field adjusts the core voltage generated by
the EVR for low power reference settings.
The values for the different configurations are listed
in the data sheet.
LPRTC
[7:6]
rw
Low Power Reference Temperature
Compensation
This bit field adjusts the core voltage generated by
the EVR for low power reference settings in order to
overcome temperature influences.
00B No temperature compensation selected
01B Positive temperature compensation selected:
+0.1 mV/°C
10B Negative temperature compensation selected:
-0.1 mV/°C
11B Reserved, do not use this combination
LPRCCDIS
8
rw
Low Power Reference Comparator Disable
0B
The LPR comparator is enabled
1B
The LPR comparator is disabled
LPRDIS
9
rh
Current Control Disable
0B
The current control is enabled
The current control is disabled
1B
This bit updates bit EVRMCON0.CCDIS.
EVRDIS
15
rh
EVR_M Disable
0B
The EVR_M is enabled
0B
The EVR_M is disabled
This bit is updated by bit EVRMSETy.EVRDIS.
0
8
rw
Reserved
Must be written with 1B.
User’s Manual
SCU, V1.1
6-117
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
0
[11:10] rw
Reserved
Should be written with 11B.
0
12
Reserved
Should be written with 0.
rh
EVR1CON0
EVR_1 Control 0 Register
15
14
13
12
EVR
DIS
rh
11
ESFR (F088H/44H)
10
0
rh
rw
rh
Description
rw
6
Reset Value: DF20H
9
8
7
5
4
3
2
1
LPR
DIS
0
LPRTC
LPRLEV
0
rh
rw
rw
rw
r
0
Field
Bits
Type
Description
LPRLEV
[5:3]
rw
Low Power Reference Level
This bit field adjusts the core voltage generated by
the EVR for low power reference settings.
The values for the different configurations are listed
in the data sheet.
LPRTC
[7:6]
rw
Low Power Reference Temperature
Compensation
This bit field adjusts the core voltage generated by
the EVR for low power reference settings in order to
overcome temperature influences.
00B No temperature compensation selected
01B Positive temperature compensation selected:
+0.1 mV/°C
10B Negative temperature compensation selected:
-0.1 mV/°C
11B Reserved, do not use this combination
LPRDIS
9
rh
Low Power Reference Disable
0B
The LPR is enabled
1B
The LPR is disabled
This bit is updated by bit EVR1SETy.LPRDIS.
EVRDIS
15
rh
EVR_1 Disable
0B
The EVR_1 is enabled
1B
The EVR_1 is disabled
This bit is updated by bit EVR1SETy.EVRDIS.
User’s Manual
SCU, V1.1
6-118
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
0
8
rw
Reserved
Must be written with 1B.
0
[11:10] rw
Reserved
Should be written with 11B.
0
12
rh
Reserved
Should be written with 0.
0
13
rw
Reserved
Must be written with 1B.
0
14
rh
Reserved
Should be written with 0.
0
[2:0]
r
Reserved
Read as 0; should be written with 0.
EVRMCON1
EVR_M Control 1 Register
15
14
13
12
11
ESFR (F086H/43H)
10
9
8
7
6
Reset Value: 0101H
5
4
3
0
HP
EN
0
r
rw
rw
Field
Bits
Type
Description
HPEN
8
rw
HP Bandgap Enable
0B
The HP bandgap is disabled
1B
The HP bandgap is enabled
0
[7:0]
rw
Reserved
Should not be changed.
0
[15:9]
r
Reserved
Read as 0; should be written with 0.
User’s Manual
SCU, V1.1
6-119
2
1
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
EVRMSET10V
EVR_M Setting for 1.0 V Register
ESFR (F090H/48H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 005BH
5
4
3
2
EVR
DIS
0
CC
DIS
0
LPR
DIS
0
VRSEL
VLEV
rw
rw
rw
rw
rw
rw
rw
rw
1
0
Field
Bits
Type
Description
VLEV
[5:0]
rw
Voltage Level Adjust
The values for the different configurations are listed
in the data sheet.
VRSEL
[7:6]
rw
Voltage Reference Selection
00B Full Voltage with high precision bandgap
selected
01B Reduced Voltage with low power reference
selected
10B Reserved, done not use this combination
11B Full Voltage with low power reference selected
Note: 01B should always be written to this bit field.
LPRDIS
9
rw
Low Power Reference Disable
0B
The LPR is enabled
1B
The LPR is disabled
This bit updates bit EVRMCON0.LPRDIS.
CCDIS
12
rw
Current Control Disable
0B
The current control is enabled
1B
The current control is disabled
This bit updates bit EVRMCON0.CCDIS.
EVRDIS
15
rw
EVR_M Disable
0B
The EVR_M is enabled
1B
The EVR_M is disabled
This bit updates bit EVRMCON0.EVRDIS.
0
8,
rw
[11:10]
[14:13]
User’s Manual
SCU, V1.1
Reserved
Should be written with 0.
6-120
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Preliminary
System Control Unit (SCU)
EVRMSET15VLP
EVR_M Setting for 1.5 V LP Register
ESFR (F094H/4AH)
15
14
13
12
11
10
9
8
7
6
Reset Value: 00DBH
5
4
3
2
EVR
DIS
0
CC
DIS
0
LPR
DIS
0
VRSEL
VLEV
rw
rw
rw
rw
rw
rw
rw
rw
1
0
Field
Bits
Type
Description
VLEV
[5:0]
rw
Voltage Level Adjust
The values for the different configurations are listed
in the data sheet.
VRSEL
[7:6]
rw
Voltage Reference Selection
00B Full Voltage with high precision bandgap
selected
01B Reduced Voltage with low power reference
selected
10B Reserved, done not use this combination
11B Full Voltage with low power reference selected
Note: 11B should always be written to this bit field.
LPRDIS
9
rw
Low Power Reference Disable
0B
The LPR is enabled
1B
The LPR is disabled
This bit updates bit EVRMCON0.LPRDIS.
CCDIS
12
rw
Current Control Disable
0B
The current control is enabled
1B
The current control is disabled
This bit updates bit EVRMCON0.CCDIS.
EVRDIS
15
rw
EVR_M Disable
0B
The EVR_M is enabled
1B
The EVR_M is disabled
This bit updates bit EVRMCON0.EVRDIS.
0
8,
rw
[11:10]
[14:13]
User’s Manual
SCU, V1.1
Reserved
Should be written with 0.
6-121
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Preliminary
System Control Unit (SCU)
EVRMSET15VHP
EVR_M Setting for 1.5 V HP Register
ESFR (F096H/4BH)
15
14
13
12
11
10
9
8
7
6
Reset Value: 001BH
5
4
3
2
EVR
DIS
0
CC
DIS
0
LPR
DIS
0
VRSEL
VLEV
rw
rw
rw
rw
rw
rw
rw
rw
1
0
Field
Bits
Type
Description
VLEV
[5:0]
rw
Voltage Level Adjust
The values for the different configurations are listed
in the data sheet.
VRSEL
[7:6]
rw
Voltage Reference Selection
00B Full Voltage with high precision bandgap
selected
01B Reduced Voltage with low power reference
selected
10B Reserved, done not use this combination
11B Full Voltage with low power reference selected
Note: 00B should always be written to this bit field.
LPRDIS
9
rw
Low Power Reference Disable
0B
The LPR is enabled
1B
The LPR is disabled
This bit updates bit EVRMCON0.LPRDIS.
CCDIS
12
rw
Current Control Disable
0B
The current control is enabled
1B
The current control is disabled
This bit updates bit EVRMCON0.CCDIS.
EVRDIS
15
rw
EVR_M Disable
0B
The EVR_M is enabled
1B
The EVR_M is disabled
This bit updates bit EVRMCON0.EVRDIS.
0
8,
rw
[11:10]
[14:13]
User’s Manual
SCU, V1.1
Reserved
Should be written with 0.
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Preliminary
System Control Unit (SCU)
EVR1SET10V
EVR_1 Setting for 1.0 V Register
ESFR (F098H/4CH)
15
14
13
12
0
CC
DIS
rw
rw
EVR CSM
DIS DDIS
rw
rw
11
10
6
Reset Value: 005BH
9
8
7
5
4
3
2
0
LPR
DIS
0
VRSEL
VLEV
rw
rw
rw
rw
rw
1
0
Field
Bits
Type
Description
VLEV
[5:0]
rw
Voltage Level Adjust
The values for the different configurations are listed
in the data sheet.
VRSEL
[7:6]
rw
Voltage Reference Selection
00B Full Voltage with high precision bandgap
selected
01B Reduced Voltage with low power reference
selected
10B Reserved, done not use this combination
11B Full Voltage with low power reference selected
Note: 01B should always be written to this bit field.
LPRDIS
9
rw
Low Power Reference Disable
0B
The LPR is enabled
1B
The LPR is disabled
This bit updates bit EVR1CON0.LPRDIS.
CCDIS
12
rw
Current Control Disable
0B
The current control is enabled
1B
The current control is disabled
This bit updates bit EVR1CON0.CCDIS.
CSMDDIS
14
rw
Core Supply Mode Detector Disable
0B
The core supply mode detector is enabled
1B
The core supply mode detector is disabled
This bit is updates bit EVR1CON0.CSMDDIS.
EVRDIS
15
rw
EVR_1 Disable
0B
The EVR_1 is enabled
1B
The EVR_1 is disabled
This bit updates bit EVR1CON0.EVRDIS.
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
0
8,
rw
[11:10]
13
Description
Reserved
Should be written with 0.
EVR1SET15VLP
EVR_1 Setting for 1.5 V LP Register
ESFR (F09CH/4EH)
15
14
13
12
0
CC
DIS
rw
rw
EVR CSM
DIS DDIS
rw
rw
11
10
6
Reset Value: 00DBH
9
8
7
5
4
3
2
0
LPR
DIS
0
VRSEL
VLEV
rw
rw
rw
rw
rw
1
0
Field
Bits
Type
Description
VLEV
[5:0]
rw
Voltage Level Adjust
The values for the different configurations are listed
in the data sheet.
VRSEL
[7:6]
rw
Voltage Reference Selection
00B Full Voltage with high precision bandgap
selected
01B Reduced Voltage with low power reference
selected
10B Reserved, done not use this combination
11B Full Voltage with low power reference selected
Note: 11B should always be written to this bit field.
LPRDIS
9
rw
Low Power Reference Disable
0B
The LPR is enabled
1B
The LPR is disabled
This bit updates bit EVR1CON0.LPRDIS.
CCDIS
12
rw
Current Control Disable
0B
The current control is enabled
1B
The current control is disabled
This bit updates bit EVR1CON0.CCDIS.
CSMDDIS
14
rw
Core Supply Mode Detector Disable
0B
The core supply mode detector is enabled
1B
The core supply mode detector is disabled
This bit is updates bit EVR1CON0.CSMDDIS.
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
EVRDIS
15
rw
EVR_1 Disable
0B
The EVR_1 is enabled
1B
The EVR_1 is disabled
This bit updates bit EVR1CON0.EVRDIS.
0
8,
rw
[11:10]
13
Reserved
Should be written with 0.
EVR1SET15VHP
EVR_1 Setting for 1.5 V HP Register
ESFR (F09EH/4FH)
15
14
13
12
0
CC
DIS
rw
rw
EVR CSM
DIS DDIS
rw
rw
11
10
6
Reset Value: 001BH
9
8
7
5
4
3
2
0
LPR
DIS
0
VRSEL
VLEV
rw
rw
rw
rw
rw
1
0
Field
Bits
Type
Description
VLEV
[5:0]
rw
Voltage Level Adjust
The values for the different configurations are listed
in the data sheet.
VRSEL
[7:6]
rw
Voltage Reference Selection
00B Full Voltage with high precision bandgap
selected
01B Reduced Voltage with low power reference
selected
10B Reserved, done not use this combination
11B Full Voltage with low power reference selected
Note: 00B should always be written to this bit field.
LPRDIS
9
rw
Low Power Reference Disable
0B
The LPR is enabled
1B
The LPR is disabled
This bit updates bit EVR1CON0.LPRDIS.
CCDIS
12
rw
Current Control Disable
0B
The current control is enabled
1B
The current control is disabled
This bit updates bit EVR1CON0.CCDIS.
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Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
CSMDDIS
14
rw
Core Supply Mode Detector Disable
The core supply mode detector is enabled
0B
1B
The core supply mode detector is disabled
This bit is updates bit EVR1CON0.CSMDDIS.
EVRDIS
15
rw
EVR_1 Disable
The EVR_1 is enabled
0B
1B
The EVR_1 is disabled
This bit updates bit EVR1CON0.EVRDIS.
0
8,
rw
[11:10]
13
6.5.4
Reserved
Should be written with 0.
Handling the Power System
Using the power system correctly is the key to save power. Depending on the application
different operating states can be defined in order to save the maximum about of power.
Several options and mechanisms are overed and supported by the XC2000. The
following mechanisms can be used to save power:
•
•
•
•
•
Reduction of the system performance
– the power consumption depends directly from the frequency of the system
– the system performance is control with the clock operation mechanism
Stopping single unused peripheral
– a peripheral not needed for an application can be disabled
– the module operation is controlled via register MOD_KSCCFG
Stopping multiple unused peripherals
– peripherals not needed for an application can be disabled
– system peripheral operation is controlled via the Global State Controller (GSC)
Stopping single unused analog parts
– an analog part not needed for an application can be stopped
– the operation is controlled via register either located in the SCU (PLL, OSCs,
PVCs, SWD, Temperature Compensation, HP bandgap, and LPR) or the ADC
Adapting the core voltage level to the application needs
– lowering the core voltage level for a complete domain gives an additional power
saving option that can and should be link with the previous options
– changes of the core voltage levels of the two core domains are controlled by the
Power State Controller (PSC)
– the Power States define all legal combination of the core voltage level for the two
core domains
The transition from one Power State to an other is called power transfer. All power
transfers can separated into one of two available basic power transfer:
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System Units (Vol. 1 of 2)
Preliminary
•
•
System Control Unit (SCU)
A Ramp-up Power Transfer
– this is defined as power transfer with at least one power domain voltage level
increasing
A Ramp-down Power Transfer
– this is defined as power transfer with at least one power domain voltage level
decreasing
Note: A power transfer where one power domain voltage level increase and the voltage
level of the other domain decrease is not defined and forbidden.
Each power transfer has to be requested by certain triggers. These triggers come from
various sources and lead to different transitions which are either pre-defined or userprogrammable.
The following triggers are available:
•
•
•
ESR Pin(s): a specific edge or level has occurred at the ESR pin(s)
WUT: the wake-up timer within DMP_M is expired
Software: the user program writes to the respective control registers in order to
initiate a state transition
Additionally there is one additional trigger that generates a power transfer:
•
Power-on Reset
In difference to the other triggers the power-on reset simply starts a power transfer based
on the reset value of the PSC registers. The power transition itself is also predefined and
fix by the reset values of the EVR and PSC registers and lead automatically to the Full
Active Mode with the LPR active. Power state I with the HP bandgap is thereafter
configured and entered automatically.
Note: Neither a system reset nor a application reset will trigger a power transfer.
The different triggers are separated into two different groups:
•
•
Ramp-down triggers that request the transition into a power saving mode that is not
power state I
– Only the software trigger can request a ramp-down
– The software trigger can be generated by the execution of the IDLE instruction if
bit SEQCON.IDLEEN is set
– The software trigger can be generated by setting bit SEQCON.SEQATRG
Ramp-up triggers that request the transition out of a power saving mode to Full Active
Mode
– An ESR trigger can request a ramp-up. Synchronous ESR triggers can be used to
request a ramp-up from power state F and power state G. Asynchronous ESR can
be used to generate triggers for all four power saving modes: power state B, power
state C, power state F, and power state G.
– An ESR trigger can be generated by an ESR event if bit SEQCON.ESRxEN is set
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Preliminary
System Control Unit (SCU)
– A wake-up timer event can generate a ramp-up trigger. A wake-up timer trigger
can request a ramp-up from the power saving states power state F and power
state G only.
– A wake-up timer trigger can be generated by an WUT event if bit
SEQCON.WUTEN is set
6.5.5
Power State Controller (PSC)
The Power State Controller (PSC) controls the operation of the EVRs and PVCs and
handles changes in the control different values.
6.5.5.1
General Overview
A power state transition implies a change of the core voltages in one or both core supply
domains. Each power state transition consists of several steps to de-couple the different
phases of the State Transition Sequence (STS). A state transition sequence defines how
EVRs and their associated PVCs are controlled and modified when a voltage change is
requested from the system.
•
•
Sequence A is used for ramp-down power transfers
Sequence B is used for ramp-up power transfers
Sequence A; it is invoked if instruction IDLE is executed or a software trigger bit
SEQBTRG in register SEQCON is set.
Sequence B; it is invoked if at least one valid wake-up trigger is asserted. If a wake-up
trigger is valid (can be recognized) depends on the currently entered power state. For
sequence B it is required to be pre-configured by the software when a power saving state
is entered where no software can be executed. Sequence B can only started after a
sequence A was performed. If no sequence A was performed the trigger for the
sequence B is treated as pending as long as a sequence A was performed.
Before a power transition is started all reset triggers that can request a reset have to be
disabled to ensure a correct power transition. Reset generation can be disabled by
setting RSTCON0 = 0x0000 and RSTCON1 = 0x0000. After the power transition the
reset can be enabled again as the application requires. Due to the fact that for the power
saving states no software can be executed the resets remain disabled until power state
Full Active is entered again. For real emergency reset request that will cause sever
system damage when lost, they should be redirected to the PORST pin. Other reset
triggers can either be redirected to a trap or the wake-up trigger of the power control
system via the ESR pins.
6.5.5.2
Sequence Configuration
Each of the two sequences is built of six configuration data sets defining up to six steps.
Each step of the sequence is controlled by its dedicated configuration data set.
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Preliminary
System Control Unit (SCU)
Step0 defines the current power state depending if the last transition was done with
sequence A or sequence B. Step0 defines the target power state depending on the
transition type. The sets 1 to 6 can be used as interim step configurations that are
needed for a transition.
At the end of each power state transition the values from the last enabled step are copied
to step 0.
6.5.5.3
Power State Transition Controlling
The PSC have to be pre-configured before the transition sequence is started. For a
power state transition sequence using sequence B the control registers SEQBSTEPx
and PVCyCONBx should be pre-configured for the wake-up transition before the first
power state transition is stated.
A transition sequence is started if either the IDLE instruction is executed or a ramp-up
trigger is asserted. A transition sequence is only started if no transition is currently
running. The transition sequence itself is the controlled by the sequence control registers
SEQzCONx.
Note: With the start of a sequence a trigger for the WUT is generated. Therefore the
WUT can be started if configured so (WUCR.AON = 1).
Skipping a Step
If a step is skipped the next not skipped step is executed without any time penalty. If a
step is skipped or not is configured via bit SEQzCONx.SEN.
Stopping the System Clock for a Power Domain
It is required to stop the system clock for each step that select a different core domain
voltage level than the previous step has for a power domain. If the core voltage levels
are unchanged the system clock can stay active. If the system clock has to be stopped
the PSC requests so and for the continuation the asynchronous event has to be
selected.
If the system clock is not stopped synchronous continuation is selected.
If the system clock is stopped asynchronous continuation is selected.
This configuration is ignored if the step is configured to be skipped.
The system clock is enabled again as soon as the selected trigger condition (bit field
TRGSEL in the associated register) is valid again. If no trigger was selected
(TRGSEL = 0000B) the system clock is not disabled at all.
This feature is controlled via bits SEQzCONx.CLKEN1 and SEQzCONx.CLKENM
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Preliminary
System Control Unit (SCU)
Connection to the GSC
In order to stop or activate the operation of peripherals within DMP_1 the GSC is used.
For this purpose the PSCx exit and PSCx entry GSC sources are used (x = sequence A
or B). If the system clock should be stopped for domain DMP_1 the PSCA entry is used
to bring all blocks in this domain into a state where the system clock can be stopped. If
the system clock should be active for domain DMP_1 the PSCB exit is used to reactivate
the clock system again. Unless disabled via bit SEQCON.GSCBY the entry request is
generated at the start of a sequence (before the first step is executed). Unless disabled
via bit SEQCON.GSCBY the exit request is generated at the end of a sequence (after
the last step is executed).
Asynchronous/Synchronous Continuation
An asynchronous continuation event is defined if both selected PVC OK outputs (from
PVC_M and PVC_1) match their configured action level.
A synchronous continuation event is defined by the system clock for DMP_M divided by
the value of bit field SEQzSTEPx.SYSDIV. Each time a step is started with the system
clock enabled for DMP_M a synchronous continuation trigger is generated after SYSDIV
system clock cycles.
Whenever the required continuation event occurs the next step is executed.
This configuration is ignored if the step is configured to be skipped.
6.5.5.4
Trigger Handling during a Power Transition
A power transition is an atomic operation. This means that it has to be finished before
any new active can be performed. Triggers that request an other power transition
occurring a currently performed power transition are stored automatically and trigger the
next power transition immediately after the currently one is finished.
6.5.6
Operating a Power Transfer
Performing a power transfer requires several steps that need to be executed involving
both hardware and software operation. The main operation of each power transfer are
the power transitions handled by the PSC. Each power transfer includes exactly two
power transitions, one ramp-down followed by one ramp-up.
Preparation
This phase includes different tasks that are required to prepare the system for the rampdown and the later ramp-up.
•
The sequence control register for both sequences A and B should be configured as
needed
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Preliminary
•
•
•
•
•
•
•
•
•
•
•
•
System Control Unit (SCU)
– The enable bits for the two power transitions should not be set before all
preparations are done in order to avoid a sequence start before the set-up is
finished
The GSC control register should be set up to stop the operations for the ramp-down
and restart of the operation with the ramp-up
The KSCCFG control register of each module should be set up to stop the operations
for the ramp-down and restart of the operation with the ramp-up
The reset generation should be disable by clearing the RSTCON registers
The global interrupt disable should be set to avoid interrupt operation
OSC_WU has to be active
The wake-up timer should be configured if this trigger is intended as ramp-up trigger
The ESRx function should be configured if this trigger is intended as ramp-up trigger
The ESRx pads should be configured if this trigger is intended as ramp-up trigger
Switch to LPR operation and disable the HP bandgap if required by the application
– Disabling the HP bandgap for a power saving mode reduces the overall power
consummation of this mode
– Disabling the HP bandgap also disables the flash, therefore all code that has to be
executed afterwards till the flash active again has to be copied first to the PSRAM
Switch off the VCO part of the PLL or the complete PLL
– Disabling the VCO part or the complete PLL for a power saving mode reduces the
overall power consummation of this mode
– Before disabling the VCO part or the complete PLL a clock source has to be
selected that still delivers a system clock after the VCO part or the complete PLL
is disabled
Enable both power sequences just before the IDLE instruction is executed
Execute the IDLE instruction
– The execution of the IDLE instruction starts the sequence A for the ramp-down
6.5.6.1
Generic Ramp-down Scenario
The following scenario shows the ramp-down flow for a better understanding.
Both thresholds are located below the current supply voltage. If the voltage falls below
the higher threshold of the PVC, a warning interrupt can be generated (undershoot
warning). If the voltage falls also below the lower threshold LEV1, a reset of this core
supply domain can be generated.
1. Stop the system operation of the peripherals via the GSC
2. Switch the power supply of the EVRs from the HP bandgap to the LPR if the HP
bandgap is currently used
3. Start sequence A: Both threshold levels are changed. The reset level is changed to
the new target value - 100 mV and the old interrupt level is changed to the new target
level + 200 mV.
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
4. Step two is performing the real voltage transition. The voltage levels of the power
domain is changed to the new value. Threshold level 2 is used as asynchronous
trigger to continue the sequence when the power is below the threshold level.
5. The core supply voltage reaches the new target level. The interrupt and reset
threshold levels are setup again.
1
2
3
4
5
LEV2
reset
activation
LEV1
LEV2
LEV1
Full Active
transition
Power Saving
Mode
P OWER_RAMP _DOWN
Figure 6-28 Ramp-down Example
6.5.6.2
Generic Ramp-up Scenario
Both thresholds are located below the current supply voltage. If the voltage falls below
the higher threshold of the PVC, a warning interrupt can be generated (undershoot
warning). If the voltage falls also below the lower threshold LEV1, a reset of this core
supply domain can be generated.
1. The higher threshold level (LEV2) is changed and therefore deactivated. It is
changed to the lower target threshold level for the new target core supply voltage.
The level should be selected in the range of - 100 mV of the target voltage.
2. Step two is performing the real voltage transition. The voltage levels of the power
domain is changed to the new value. Threshold level 2 is used as asynchronous
trigger to continue the sequence when the power is above the threshold level.
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Preliminary
System Control Unit (SCU)
3. The core supply voltage reaches the new target level. The new core supply voltage
has reached a level where the system clock can safely be activated again. The
interrupt and reset threshold levels are setup again.
4. The interrupt / trap resulting out of the ramp-up trigger reactivates the CPU from IDLE
Mode
5. The GSC reactivates the system operation of the peripherals
6. The power supply of the EVRs is switched back from the LPR to the HP bandgap and
the flash becomes active again
3
1
5
4
2
6
LEV2
LEV1
reset
activation
LEV2
LEV1
Power Saving
Mode
transition
Full Active
POWER_RAMP_UP
Figure 6-29 Ramp-up Example
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
6.5.7
Power Control Registers
6.5.7.1
PSC Status and Control Registers
SEQCON
Sequence Control Register
SFR (FEE4H/72H)
15
14
SEQ
GSC
BOS
BY
CDIS
rw
rw
13
12
SEQ
AOS
CDIS
rw
0
r
11
10
9
8
7
ESR ESR ESR
WUT
2
1
0
EN
EN EN EN
rw
rw
rw
rw
6
Reset Value: 8004H
5
4
0
IDLE
EN
r
rw
3
2
1
SEQ SEQ
B
A
EN EN
rwh rwh
0
r
0
SEQ
A
TRG
w
Field
Bits
Type
Description
SEQATRG
0
w
Sequence A Trigger
Setting this bit trigger a power transition defined by
sequence A
No action
0B
1B
Sequence A is started
Sequence A is only started if Sequence B is not
currently active.
This bit is automatically cleared and always read as
zero.
SEQAEN
2
rwh
Sequence A Enable
0B
Sequence A is never started
1B
Sequence A is started if requested
Sequence A is only started if Sequence B is not
currently active.
This bit is automatically cleared after the sequence
was started.
SEQBEN
3
rwh
Sequence B Enable
Sequence B is never started
0B
1B
Sequence B is started if requested
Sequence B is only started if Sequence A is not
currently active.
This bit is automatically cleared after the sequence
was started.
User’s Manual
SCU, V1.1
6-134
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
IDLEEN
4
rw
IDLE Trigger Enable
This bit defines if the IDLE instruction can trigger
sequence A or not.
0B
Sequence A is never triggered by the IDLE
instruction
1B
Sequence A is triggered by the IDLE
instruction
WUTEN
8
rw
WUT Trigger Enable
This bit defines if an WUT event can trigger
sequence B or not.
0B
Sequence B is never triggered by an WUT
event
1B
Sequence B is triggered by WUT event
ESR0EN
9
rw
ESR0 Trigger Enable
This bit defines if an ESR0 event can trigger
sequence B or not.
0B
Sequence B is never triggered by an ESR0
event
1B
Sequence B is triggered by ESR0 event
ESR1EN
10
rw
ESR1 Trigger Enable
This bit defines if an ESR1 event can trigger
sequence B or not.
0B
Sequence B is never triggered by an ESR1
event
1B
Sequence B is triggered by ESR1 event
ESR2EN
11
rw
ESR2 Trigger Enable
This bit defines if an ESR2 event can trigger
sequence B or not.
0B
Sequence B is never triggered by an ESR2
event
1B
Sequence B is triggered by ESR2 event
SEQAOSCEN
13
rw
Sequence A OSC_WU Enable
This bit defines if the OSC_WU is enabled with the
end of the sequence A.
0B
The enable setting for OSC_WU is left
unchanged
1B
OSC_WU is disabled
User’s Manual
SCU, V1.1
6-135
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
SEQBOSCEN
14
rw
Sequence B OSC_WU Enable
This bit defines if the OSC_WU is enabled with the
end of the sequence B.
0B
The enable setting for OSC_WU is left
unchanged
1B
OSC_WU is disabled
GSCBY
15
rw
GSC Bypass
This bit defines if an PSC event can trigger GSC
action or not.
The normal GSC action is requested
0B
1B
No GSC action is started
0
1,[7:5], r
12
Reserved
Read as 0; should be written with 0.
STEP0
Step 0 Register
15
14
13
SFR (FEF2H/79H)
12
PVC PVC
SYS
1
1
M
DIV
OFF OFF
rwh rwh rwh rwh
11
10
9
TRGSEL
rwh
8
7
6
Reset Value: C063H
5
4
3
2
1
CLK CLK
EN1 ENM
V1
VM
rwh
rwh
rwh
rwh
0
Field
Bits
Type
Description
VM
[2:0]
rwh
DMP_M Voltage Configuration
This bit defines the DMP_M core supply voltage that
is requested from EVR_M.
000B Full Voltage with HP bandgap selected
001B Reduced Voltage with LPR selected
010B Reserved, do not use this combination
011B Full Voltage with LPR selected
100B Off is configured
101B Off is configured
110B Off is configured
111B Off is configured
User’s Manual
SCU, V1.1
6-136
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
V1
[5:3]
rwh
DMP_1 Voltage Configuration
This bit defines the DMP_1 core supply voltage that
is requested from EVR_1.
000B Full Voltage with HP bandgap selected. If
DMP_1 was not powered before this is not
changed and only the EVR configuration is
changed.
001B Reduced Voltage with LPR selected. If DMP_1
was not powered before this is not changed
and only the EVR configuration is changed.
010B Reserved, do not use this combination
011B Full Voltage with LPR selected. If DMP_1 was
not powered before this is not changed and
only the EVR configuration is changed.
100B Off is configured, all clocks in the DMP_1 are
disabled and DMP_1 is not longer powered
101B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B but DMP_1 is powered with
EVR_1 configuration
110B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
enabled
111B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
disabled
CLKENM
6
rwh
System Clock Enable for DMP_M
This bit defines the system clock have to be stopped
for DMP_M.
System clock for DMP_M is stopped
0B
1B
System clock for DMP_M is running
CLKEN1
7
rwh
System Clock Enable for DMP_1
This bit defines the system clock have to be stopped
for DMP_1.
0B
System clock for DMP_1 is stopped
1B
System clock for DMP_1 is running
User’s Manual
SCU, V1.1
6-137
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
TRGSEL
[11:8]
rwh
Trigger Selection
This bit field defines the which of the four possible OK
outputs from both PVCs are used for validating the
power transition.
0000BNon of the outputs is used
0001BOK 1 from PVC_M is used
0010BOK 2 from PVC_M is used
0011BOK 1 from PVC_M AND OK 2 from PVC_M is
used
0100BOK 1 from PVC_1 is used
0101BOK 1 from PVC_M AND OK 1 from PVC_1 is
used
0110BOK 2 from PVC_M AND OK 1 from PVC_1 is
used
0111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 is used
1000BOK 2 from PVC_1 is used
1001BOK 1 from PVC_M AND OK 2 from PVC_1 is
used
1010BOK 2 from PVC_M AND OK 2 from PVC_1 is
used
1011BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 2 from PVC_1 is used
1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is
used
1101BOK 1 from PVC_M AND OK 1 from PVC_1
AND OK 2 from PVC_1 is used
1110BOK 2 from PVC_M AND OK 1 from PVC_1
AND OK2 from PVC_1 is used
1111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 AND OK2 from PVC_1
is used
SYSDIV
12
rwh
System Clock Divider
This bit defines the number of system clock cycles
fSYS before the sequence is continued.
0B
The sequence is continued after 1 fSYS cycles
1B
The sequence is continued after 64 fSYS cycles
User’s Manual
SCU, V1.1
6-138
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
PVCMOFF
13
rwh
PVC_M Disabled
This bit defines whether the PVC_M generates any
valid check results or not. The PVC_M can be
disabled in order to save power.
0B
The PVC_M is enabled and delivers valid
results
1B
The PVC_M is disabled and deliver no valid
results
PVC1OFF
14
rwh
PVC_1 Disabled
This bit defines whether the PVC_1 generates any
valid check results or not. The PVC_1 can be
disabled in order to save power.
0B
The PVC_1 is enabled and delivers valid
results
1B
The PVC_1 is disabled and deliver no valid
results
1
15
rwh
Reserved
Read as 1; should be written with 1.
This bit is updated by the SEN bit of the sequence
registers.
SEQASTEP1
Sequence Step 1 for Set A Register
SFR (FEE6H/73H)
15
SEN
rw
14
13
12
PVC PVC
SYS
1
M
DIV
OFF OFF
rw
rw
rw
User’s Manual
SCU, V1.1
11
10
9
TRGSEL
rw
8
7
6
CLK CLK
EN1 ENM
rw
6-139
rw
Reset Value: 0000H
5
4
3
2
1
V1
VM
rw
rw
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
VM
[2:0]
rw
DMP_M Voltage Configuration
This bit defines the DMP_M core supply voltage that
is requested with this step from EVR_M.
000B Full Voltage with HP bandgap selected
001B Reduced Voltage with LPR selected
010B Reserved, do not use this combination
011B Full Voltage with LPR selected
100B Off is configured
101B Off is configured
110B Off is configured
111B Off is configured
V1
[5:3]
rw
DMP_1 Voltage Configuration
This bit defines the DMP_1 core supply voltage that
is requested from EVR_1.
000B Full Voltage with HP bandgap selected. If
DMP_1 was not powered before this is not
changed and only the EVR configuration is
changed.
001B Reduced Voltage with LPR selected. If DMP_1
was not powered before this is not changed
and only the EVR configuration is changed.
010B Reserved, do not use this combination
011B Full Voltage with LPR selected. If DMP_1 was
not powered before this is not changed and
only the EVR configuration is changed.
100B Off is configured, all clocks in the DMP_1 are
disabled and DMP_1 is not longer powered
101B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B but DMP_1 is powered with
EVR_1 configuration
110B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
enabled
111B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
disabled
User’s Manual
SCU, V1.1
6-140
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
CLKENM
6
rw
System Clock Enable for DMP_M
This bit defines the system clock have to be stopped
till the next step or not for DMP_M.
0B
System clock for DMP_M is stopped
1B
System clock for DMP_M is running
CLKEN1
7
rw
System Clock Enable for DMP_1
This bit defines the system clock have to be stopped
till the next step or not for DMP_1.
0B
System clock for DMP_1 is stopped
System clock for DMP_1 is running
1B
User’s Manual
SCU, V1.1
6-141
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
TRGSEL
[11:8]
rw
Trigger Selection
This bit field defines the which of the four possible OK
outputs from both PVCs are used for validating the
power transition.
0000BNon of the outputs is used
0001BOK 1 from PVC_M is used
0010BOK 2 from PVC_M is used
0011BOK 1 from PVC_M AND OK 2 from PVC_M is
used
0100BOK 1 from PVC_1 is used
0101BOK 1 from PVC_M AND OK 1 from PVC_1 is
used
0110BOK 2 from PVC_M AND OK 1 from PVC_1 is
used
0111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 is used
1000BOK 2 from PVC_1 is used
1001BOK 1 from PVC_M AND OK 2 from PVC_1 is
used
1010BOK 2 from PVC_M AND OK 2 from PVC_1 is
used
1011BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 2 from PVC_1 is used
1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is
used
1101BOK 1 from PVC_M AND OK 1 from PVC_1
AND OK 2 from PVC_1 is used
1110BOK 2 from PVC_M AND OK 1 from PVC_1
AND OK2 from PVC_1 is used
1111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 AND OK2 from PVC_1
is used
SYSDIV
12
rw
System Clock Divider
This bit defines the number of system clock cycles
fSYS before the sequence is continued.
0B
The sequence is continued after 1 fSYS cycles
1B
The sequence is continued after 64 fSYS cycles
User’s Manual
SCU, V1.1
6-142
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
PVCMOFF
13
rw
PVC_M Disabled
This bit defines whether the PVC generates any valid
check results or not for this step. The PVC can be
disabled in order to save power.
0B
The PVC_M is enabled and delivers valid
results
1B
The PVC_M is disabled and deliver no valid
results
PVC1OFF
14
rw
PVC_1 Disabled
This bit defines whether the PVC generates any valid
check results or not for this step. The PVC can be
disabled in order to save power.
0B
The PVC_1 is enabled and delivers valid
results
1B
The PVC_1 is disabled and deliver no valid
results
SEN
15
rw
Step Enable
This bit defines the operation that is connected with
step n of the transition is skipped or not.
Step is skipped
0B
1B
Step is executed
User’s Manual
SCU, V1.1
6-143
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
SEQASTEP2
Sequence Step 2 for Set A Register
SFR (FEE8H/74H)
SEQASTEP3
Sequence Step 3 for Set A Register
SFR (FEEAH/75H)
SEQASTEP4
Sequence Step 4 for Set A Register
SFR (FEECH/76H)
SEQASTEP5
Sequence Step 5 for Set A Register
SFR (FEEEH/77H)
SEQASTEP6
Sequence Step 6 for Set A Register
SFR (FEF0H/78H)
15
SEN
rw
14
13
12
11
PVC PVC
SYS
1
M
DIV
OFF OFF
rw
rw
rw
10
9
TRGSEL
rw
8
7
6
CLK CLK
EN1 ENM
rw
rw
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
5
4
3
2
1
V1
VM
rw
rw
0
Field
Bits
Type
Description
VM
[2:0]
rw
DMP_M Voltage Configuration
This bit defines the DMP_M core supply voltage that
is requested with this step from EVR_M.
000B Full Voltage with HP bandgap selected
001B Reduced Voltage with LPR selected
010B Reserved, do not use this combination
011B Full Voltage with LPR selected
100B Off is configured
101B Off is configured
110B Off is configured
111B Off is configured
User’s Manual
SCU, V1.1
6-144
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
V1
[5:3]
rw
DMP_1 Voltage Configuration
This bit defines the DMP_1 core supply voltage that
is requested from EVR_1.
000B Full Voltage with HP bandgap selected. If
DMP_1 was not powered before this is not
changed and only the EVR configuration is
changed.
001B Reduced Voltage with LPR selected. If DMP_1
was not powered before this is not changed
and only the EVR configuration is changed.
010B Reserved, do not use this combination
011B Full Voltage with LPR selected. If DMP_1 was
not powered before this is not changed and
only the EVR configuration is changed.
100B Off is configured, all clocks in the DMP_1 are
disabled and DMP_1 is not longer powered
101B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B but DMP_1 is powered with
EVR_1 configuration
110B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
enabled
111B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
disabled
CLKENM
6
rw
System Clock Enable for DMP_M
This bit defines the system clock have to be stopped
till the next step or not for DMP_M.
System clock for DMP_M is stopped
0B
1B
System clock for DMP_M is running
CLKEN1
7
rw
System Clock Enable for DMP_1
This bit defines the system clock have to be stopped
till the next step or not for DMP_1.
0B
System clock for DMP_1 is stopped
1B
System clock for DMP_1 is running
User’s Manual
SCU, V1.1
6-145
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
TRGSEL
[11:8]
rw
Trigger Selection
This bit field defines the which of the four possible OK
outputs from both PVCs are used for validating the
power transition.
0000BNon of the outputs is used
0001BOK 1 from PVC_M is used
0010BOK 2 from PVC_M is used
0011BOK 1 from PVC_M AND OK 2 from PVC_M is
used
0100BOK 1 from PVC_1 is used
0101BOK 1 from PVC_M AND OK 1 from PVC_1 is
used
0110BOK 2 from PVC_M AND OK 1 from PVC_1 is
used
0111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 is used
1000BOK 2 from PVC_1 is used
1001BOK 1 from PVC_M AND OK 2 from PVC_1 is
used
1010BOK 2 from PVC_M AND OK 2 from PVC_1 is
used
1011BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 2 from PVC_1 is used
1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is
used
1101BOK 1 from PVC_M AND OK 1 from PVC_1
AND OK 2 from PVC_1 is used
1110BOK 2 from PVC_M AND OK 1 from PVC_1
AND OK2 from PVC_1 is used
1111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 AND OK2 from PVC_1
is used
SYSDIV
12
rw
System Clock Divider
This bit defines the number of system clock cycles
fSYS before the sequence is continued.
0B
The sequence is continued after 1 fSYS cycles
1B
The sequence is continued after 64 fSYS cycles
User’s Manual
SCU, V1.1
6-146
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
PVCMOFF
13
rw
PVC_M Disabled
This bit defines whether the PVC generates any valid
check results or not for this step. The PVC can be
disabled in order to save power.
0B
The PVC_M is enabled and delivers valid
results
1B
The PVC_M is disabled and deliver no valid
results
PVC1OFF
14
rw
PVC_1 Disabled
This bit defines whether the PVC generates any valid
check results or not for this step. The PVC can be
disabled in order to save power.
0B
The PVC_1 is enabled and delivers valid
results
1B
The PVC_1 is disabled and deliver no valid
results
SEN
15
rw
Step Enable
This bit defines the operation that is connected with
step n of the transition is skipped or not.
Step is skipped
0B
1B
Step is executed
SEQBSTEP1
Sequence Step 1 for Set B Register
SFR (FEF4H/7AH)
15
SEN
rw
14
13
12
PVC PVC
SYS
1
M
DIV
OFF OFF
rw
rw
rw
User’s Manual
SCU, V1.1
11
10
9
TRGSEL
rw
8
7
6
CLK CLK
EN1 ENM
rw
6-147
rw
Reset Value: 88DBH
5
4
3
2
1
V1
VM
rw
rw
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
VM
[2:0]
rw
DMP_M Voltage Configuration
This bit defines the DMP_M core supply voltage that
is requested with this step from EVR_M.
000B Full Voltage with HP bandgap selected
001B Reduced Voltage with LPR selected
010B Reserved, do not use this combination
011B Full Voltage with LPR selected
100B Off is configured
101B Off is configured
110B Off is configured
111B Off is configured
V1
[5:3]
rw
DMP_1 Voltage Configuration
This bit defines the DMP_1 core supply voltage that
is requested from EVR_1.
000B Full Voltage with HP bandgap selected. If
DMP_1 was not powered before this is not
changed and only the EVR configuration is
changed.
001B Reduced Voltage with LPR selected. If DMP_1
was not powered before this is not changed
and only the EVR configuration is changed.
010B Reserved, do not use this combination
011B Full Voltage with LPR selected. If DMP_1 was
not powered before this is not changed and
only the EVR configuration is changed.
100B Off is configured, all clocks in the DMP_1 are
disabled and DMP_1 is not longer powered
101B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B but DMP_1 is powered with
EVR_1 configuration
110B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
enabled
111B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
disabled
User’s Manual
SCU, V1.1
6-148
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
CLKENM
6
rw
System Clock Enable for DMP_M
This bit defines the system clock have to be stopped
till the next step or not for DMP_M.
0B
System clock for DMP_M is stopped
1B
System clock for DMP_M is running
CLKEN1
7
rw
System Clock Enable for DMP_1
This bit defines the system clock have to be stopped
till the next step or not for DMP_1.
0B
System clock for DMP_1 is stopped
System clock for DMP_1 is running
1B
User’s Manual
SCU, V1.1
6-149
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
TRGSEL
[11:8]
rw
Trigger Selection
This bit field defines the which of the four possible OK
outputs from both PVCs are used for validating the
power transition.
0000BNon of the outputs is used
0001BOK 1 from PVC_M is used
0010BOK 2 from PVC_M is used
0011BOK 1 from PVC_M AND OK 2 from PVC_M is
used
0100BOK 1 from PVC_1 is used
0101BOK 1 from PVC_M AND OK 1 from PVC_1 is
used
0110BOK 2 from PVC_M AND OK 1 from PVC_1 is
used
0111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 is used
1000BOK 2 from PVC_1 is used
1001BOK 1 from PVC_M AND OK 2 from PVC_1 is
used
1010BOK 2 from PVC_M AND OK 2 from PVC_1 is
used
1011BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 2 from PVC_1 is used
1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is
used
1101BOK 1 from PVC_M AND OK 1 from PVC_1
AND OK 2 from PVC_1 is used
1110BOK 2 from PVC_M AND OK 1 from PVC_1
AND OK2 from PVC_1 is used
1111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 AND OK2 from PVC_1
is used
SYSDIV
12
rw
System Clock Divider
This bit defines the number of system clock cycles
fSYS before the sequence is continued.
0B
The sequence is continued after 1 fSYS cycles
1B
The sequence is continued after 64 fSYS cycles
User’s Manual
SCU, V1.1
6-150
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
PVCMOFF
13
rw
PVC_M Disabled
This bit defines whether the PVC generates any valid
check results or not for this step. The PVC can be
disabled in order to save power.
0B
The PVC_M is enabled and delivers valid
results
1B
The PVC_M is disabled and deliver no valid
results
PVC1OFF
14
rw
PVC_1 Disabled
This bit defines whether the PVC generates any valid
check results or not for this step. The PVC can be
disabled in order to save power.
0B
The PVC_1 is enabled and delivers valid
results
1B
The PVC_1 is disabled and deliver no valid
results
SEN
15
rw
Step Enable
This bit defines the operation that is connected with
step n of the transition is skipped or not.
Step is skipped
0B
1B
Step is executed
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System Control Unit (SCU)
SEQBSTEP2
Sequence Step 2 for Set B Register
SFR (FEF6H/7BH)
SEQBSTEP3
Sequence Step 3 for Set B Register
SFR (FEF8H/7CH)
SEQBSTEP4
Sequence Step 4 for Set B Register
SFR (FEFAH/7DH)
SEQBSTEP5
Sequence Step 5 for Set B Register
SFR (FEFCH/7EH)
SEQBSTEP6
Sequence Step 6 for Set B Register
SFR (FEFEH/7FH)
15
SEN
rw
14
13
12
11
PVC PVC
SYS
1
M
DIV
OFF OFF
rw
rw
rw
10
9
TRGSEL
rw
8
7
6
CLK CLK
EN1 ENM
rw
rw
Reset Value: 80EBH
Reset Value: 80F3H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
5
4
3
2
1
V1
VM
rw
rw
0
Field
Bits
Type
Description
VM
[2:0]
rw
DMP_M Voltage Configuration
This bit defines the DMP_M core supply voltage that
is requested with this step from EVR_M.
000B Full Voltage with HP bandgap selected
001B Reduced Voltage with LPR selected
010B Reserved, do not use this combination
011B Full Voltage with LPR selected
100B Off is configured
101B Off is configured
110B Off is configured
111B Off is configured
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Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
V1
[5:3]
rw
DMP_1 Voltage Configuration
This bit defines the DMP_1 core supply voltage that
is requested from EVR_1.
000B Full Voltage with HP bandgap selected. If
DMP_1 was not powered before this is not
changed and only the EVR configuration is
changed.
001B Reduced Voltage with LPR selected. If DMP_1
was not powered before this is not changed
and only the EVR configuration is changed.
010B Reserved, do not use this combination
011B Full Voltage with LPR selected. If DMP_1 was
not powered before this is not changed and
only the EVR configuration is changed.
100B Off is configured, all clocks in the DMP_1 are
disabled and DMP_1 is not longer powered
101B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B but DMP_1 is powered with
EVR_1 configuration
110B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
enabled
111B Configuration is unchanged reading returns
last configured value out of 000B, 001B, 010B,
011B, or 100B, all clocks in the DMP_1 are
disabled
CLKENM
6
rw
System Clock Enable for DMP_M
This bit defines the system clock have to be stopped
till the next step or not for DMP_M.
System clock for DMP_M is stopped
0B
1B
System clock for DMP_M is running
CLKEN1
7
rw
System Clock Enable for DMP_1
This bit defines the system clock have to be stopped
till the next step or not for DMP_1.
0B
System clock for DMP_1 is stopped
1B
System clock for DMP_1 is running
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Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
TRGSEL
[11:8]
rw
Trigger Selection
This bit field defines the which of the four possible OK
outputs from both PVCs are used for validating the
power transition.
0000BNon of the outputs is used
0001BOK 1 from PVC_M is used
0010BOK 2 from PVC_M is used
0011BOK 1 from PVC_M AND OK 2 from PVC_M is
used
0100BOK 1 from PVC_1 is used
0101BOK 1 from PVC_M AND OK 1 from PVC_1 is
used
0110BOK 2 from PVC_M AND OK 1 from PVC_1 is
used
0111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 is used
1000BOK 2 from PVC_1 is used
1001BOK 1 from PVC_M AND OK 2 from PVC_1 is
used
1010BOK 2 from PVC_M AND OK 2 from PVC_1 is
used
1011BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 2 from PVC_1 is used
1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is
used
1101BOK 1 from PVC_M AND OK 1 from PVC_1
AND OK 2 from PVC_1 is used
1110BOK 2 from PVC_M AND OK 1 from PVC_1
AND OK2 from PVC_1 is used
1111BOK 1 from PVC_M AND OK 2 from PVC_M
AND OK 1 from PVC_1 AND OK2 from PVC_1
is used
SYSDIV
12
rw
System Clock Divider
This bit defines the number of system clock cycles
fSYS before the sequence is continued.
0B
The sequence is continued after 1 fSYS cycles
1B
The sequence is continued after 64 fSYS cycles
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Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
PVCMOFF
13
rw
PVC_M Disabled
This bit defines whether the PVC generates any valid
check results or not for this step. The PVC can be
disabled in order to save power.
0B
The PVC_M is enabled and delivers valid
results
1B
The PVC_M is disabled and deliver no valid
results
PVC1OFF
14
rw
PVC_1 Disabled
This bit defines whether the PVC generates any valid
check results or not for this step. The PVC can be
disabled in order to save power.
0B
The PVC_1 is enabled and delivers valid
results
1B
The PVC_1 is disabled and deliver no valid
results
SEN
15
rw
Step Enable
This bit defines the operation that is connected with
step n of the transition is skipped or not.
Step is skipped
0B
1B
Step is executed
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Preliminary
6.6
System Control Unit (SCU)
Global State Controller (GSC)
Beside power saving modes and the clock management Mode Control for the system
peripherals provides an additional opportunity for configuring the system to the
application needs.
Mode Control is described in detail in this chapter and is implemented by the GSC.
The GSC enables the user to configure one operating mode in a fast and easy way,
reacting fast and explicit to needs of an application.
Feature Overview
The following issues are handled by the GSC:
•
•
•
Control of peripheral clock operation
Suspend control for debugging
Arbitration between the different request sources
According to the requests coming from the OCDS, the SWD pre-warning detection or
other blocks, the GSC does an internal prioritization. The result is forwarded as
broadcast command request to all peripherals. The GSC internal prioritization scheme
for the implemented request sources is shown in Table 6-15.
6.6.1
GSC Control Flow
At least one request source asserts its request trigger in order to request a mode change
in the SoC. If several requests are pending there is an arbitration mechanism that treats
this issue. Request triggers are not stored by the GSC, therefore a trigger source has to
assert its trigger until the trigger is no longer valid or needed.
A request trigger is kept asserted as long as either the request is still pending or the
resulting command of the request was entered and acknowledged by the system. The
communication of the GSC and the peripherals is based on commands. Three different
commands are defined resulting in three modes:
•
•
•
Wake-up command
– This command defines the Normal Mode
Clock-off command
– This command defines the Stop Mode
Debug command
– This command defines the Suspend Mode
Each peripheral defines its specific behavior for these three modes via the module
register mod_KSCCFG.
6.6.1.1
Request Source Arbitration
The arbitration is a priority driven arbitration. The highest priority in this arbitration is
zero.
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Preliminary
System Control Unit (SCU)
Each cycle a new arbitration round is started. The winner of an arbitration round can
issue the next command towards the SoC. Please note that winning an arbitration does
not lead automatically to a new command raised. Only if currently no command is
broadcast in the SoC a new command can be generated and broadcast. If the winner of
the arbitration round is the same request trigger as in the previous round or if no winner
was detected no new command request is generated.
Table 6-15
Connection of the Request Sources
Request Source
Priority
PSCB exit
0
PSCB entry
1
PSCA exit
2
PSCA entry
3
OCDS exit
4
ESR0
5
ESR1
6
ESR2
7
WUT
8
ITC
9
SW1
11
SW2
12
OCDS entry
14
6.6.1.2
Generation of a New Command
When a new request trigger was detected and arbitrated a new command request is
generated if one of the following conditions is valid:
•
Currently no command request is broadcast that is not received by all slaves
Table 6-16
Request Source and Command Request Coupling
Request Source
Command Description
PSCB exit
Wake-up; Normal Mode
PSCB entry
Clock-off Mode
PSCA exit
Wake-up; Normal Mode
PSCA entry
Clock-off Mode
OCDS exit
Wake-up; Normal Mode
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Preliminary
Table 6-16
System Control Unit (SCU)
Request Source and Command Request Coupling
Request Source
Command Description
ESR0
Wake-up; Normal Mode
ESR1
Wake-up; Normal Mode
ESR2
Clock-off Mode
WUT
Wake-up; Normal Mode
ITC
Wake-up; Normal Mode
SW1
Wake-up; Normal Mode
SW2
Clock-off Mode
OCDS entry
Suspend Mode
6.6.1.3
Usage of Commands
The complete control mechanism for the different operation modes of the various slaves
are divided into two parts:
•
•
A central control and configuration part; the Global State Controller (GSC)
One local control part in each slave; the Kernel State Controller (KSC)
Via the GSC either different hardware sources (e.g. the WUT or the OCDS) or the
software can request the system to enter a specific mode. The parts that are affected by
the mode can be pre-defined locally for each part via the KSC. For each command a
specific reaction can be pre-configured in each KSC for each individual part.
6.6.1.4
Terminating a Request Trigger
A request trigger is no longer taken into account for the arbitration after the de-asserting
of the request trigger.
6.6.1.5
Suspend Control Flow
The suspend feature is controlled by the OCDS block. The GSC operates only as control
and communication interface towards the system. The suspend feature is composed out
of two requirements:
The mode that has to be entered when the Suspend Mode is requested.
The mode that has to be entered when the Suspend Mode is left.
The request to enter Suspend Mode is forwarded form the OCDS. When the Suspend
Mode is requested the system is expected to be stopped as soon as possible in an idle
state where no internal process is pending and in a way that this system state does not
lead to any damage internally or externally and can also be left without any damage.
Therefore all peripherals in the system are requested to enter a mode where the clock
can be stopped. This is done by sending a debug command.
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System Control Unit (SCU)
Leaving the Suspend Mode should serve the goal that debugging is a non-intrusive
operation. Therefore leaving the Suspend Mode can not lead to only one dedicated
system mode, instead it leads to the system mode the system left when it was requested
to exit the Suspend Mode. The system mode is stored when a Suspend Mode request
is detected by the GSC and is used as target system mode when a leave Suspend Mode
trigger is detected by the GSC.
6.6.1.6
Error Feedback for a Mode Transition
In case at least one peripheral reports an error the error flag in register GSCSTAT is set.
If no error is currently detected upon a new assertion of a system mode by the GSC the
error flag is cleared. To inform the system of this erroneous state an interrupt can be
generated.
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Preliminary
System Control Unit (SCU)
6.6.2
GSC Registers
6.6.2.1
GSC Control and Status Registers
The following register control and configure the behavior of the GSC.
GSCSWREQ
GSC Software Request Register
SFR (FF14H/8AH)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
SWT SWT
RG2 RG1
0
r
rwh
rwh
Field
Bits
Type
Description
SWTRG1
0
rwh
Software Trigger 1 (SW1)
0B
No SW1 request trigger is generated
1B
A SW1 request trigger is generated
This bit is automatically cleared if the SW1 request
trigger wins the arbitration and was broadcast to the
system.
SWTRG2
1
rwh
Software Trigger 2 (SW2)
0B
No SW2 request trigger is generated
A SW2 request trigger is generated
1B
This bit is automatically cleared if the SW2 request
trigger wins the arbitration and was broadcast to the
system.
0
[15:2]
r
Reserved
Read as 0; should be written with 0.
GSCEN
GSC Enable Register
15
0
r
14
OCD
SEN
EN
rw
13
1
rw
User’s Manual
SCU, V1.1
12
SFR (FF16H/8BH)
11
SW2 SW1
EN EN
rw
rw
10
1
rw
9
8
7
6
Reset Value: 7FFFH
5
4
3
2
1
0
OCD PSC PSC PSC PSC
ITC WUT ESR ESR ESR
SEX AEN AEX BEN BEX
EN EN 2EN 1EN 0EN
EN EN EN EN EN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
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System Control Unit (SCU)
Field
Bits
Type
Description
PSCBEXEN
0
rw
PSC Sequence B Exit Request Trigger Enable
0B
PSC sequence B exit request trigger is not
taken into account (disabled)
1B
PSC sequence B exit request trigger is taken
into account (enabled)
PSCBENEN
1
rw
PSC Sequence B Entry Request Trigger Enable
PSC sequence B entry request trigger is not
0B
taken into account (disabled)
1B
PSC sequence B entry request trigger is taken
into account (enabled)
PSCAEXEN
2
rw
PSC Sequence A Exit Request Trigger Enable
0B
PSC sequence A exit request trigger is not
taken into account (disabled)
1B
PSC sequence A exit request trigger is taken
into account (enabled)
PSCAENEN
3
rw
PSC Sequence A Entry Request Trigger Enable
0B
PSC sequence A entry request trigger is not
taken into account (disabled)
1B
PSC sequence A entry request trigger is taken
into account (enabled)
OCDSEXEN
4
rw
OCDS Exit Request Trigger Enable
0B
OCDS exit request trigger is not taken into
account (disabled)
1B
OCDS exit request trigger is taken into account
(enabled)
ESR0EN
5
rw
ESR0 Request Trigger Enable
ESR0 request trigger is not taken into account
0B
(disabled)
1B
ESR0 request trigger is taken into account
(enabled)
ESR1EN
6
rw
ESR1 Request Trigger Enable
0B
ESR1 request trigger is not taken into account
(disabled)
1B
ESR1 request trigger is taken into account
(enabled)
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Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
ESR2EN
7
rw
ESR2 Request Trigger Enable
0B
ESR2 request trigger is not taken into account
(disabled)
1B
ESR2 request trigger is taken into account
(enabled)
WUTEN
8
rw
WUT Request Trigger Enable
0B
WUT request trigger is not taken into account
(disabled)
1B
WUT request trigger is taken into account
(enabled)
ITCEN
9
rw
ITC Request Trigger Enable
ITC request trigger is not taken into account
0B
(disabled)
1B
ITC request trigger is taken into account
(enabled)
SW1EN
11
rw
Software 1 Request Trigger Enable
0B
SW1 request trigger is not taken into account
(disabled)
1B
SW1 request trigger is taken into account
(enabled)
SW2EN
12
rw
Software 2 Request Trigger Enable
0B
SW2 request trigger is not taken into account
(disabled)
1B
SW2 request trigger is taken into account
(enabled)
OCDSENEN
14
rw
OCDS Entry Request Trigger Enable
0B
OCDS entry request trigger is not taken into
account (disabled)
1B
OCDS entry request trigger is taken into
account (enabled)
OCDS entry is the request source belonging to the
according connector interface.
1
10, 13
rw
Reserved
Should be written with.
0
15
r
Reserved
Read as 0; should be written with 0.
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System Control Unit (SCU)
GSCSTAT
GSC Status Register
15
14
13
12
SFR (FF18H/8CH)
11
0
SOURCE
r
rh
10
9
8
7
PEN ERR
rh
rh
6
Reset Value: 3C00H
5
4
3
2
1
0
0
NEXT
0
CURRENT
r
rh
r
rh
Field
Bits
Type
Description
CURRENT
[1:0]
rh
Currently used Command
This bit field states the currently used system mode.
NEXT
[5:4]
rh
Next to use Command
This bit field states the next to be used system mode.
ERR
8
rh
Error Status Flag
This bit flags if with the last command that was
broadcast was acknowledge with at least one error.
This bit is automatically cleared when a new
command is broadcast.
PEN
9
rh
Command Pending Flag
This flag states if currently a command is pending or
not. A command is pending after the broadcast as
long as no all blocks acknowledge that they finished
the operation requested by the command.
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System Control Unit (SCU)
Field
Bits
SOURCE
[13:10] rh
Requesting Source Status
This bit field monitors the source that triggered the
last request.
0000B PSCB exit
0001B PSCB entry
0010B PSCA exit
0011B PSCA entry
0100B OCDS exit
0101B ESR0
0110B ESR1
0111B ESR2
1000B WU
1001B ITC
1010B Reserved, do not use this combination
1011B SW1
1100B SW2
1101B Reserved, do not use this combination
1110B OCDS entry
1111B Reserved, do not use this combination
0
[3:2],
r
[7:6],
[15:14]
Reserved
Read as 0; should be written with 0.
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Description
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6.7
System Control Unit (SCU)
Temperature Compensation Unit
The temperature compensation for the port drivers provides driver output characteristics
which are stable (within a certain band of parameter variation) over the specified
temperature range.
The temperature compensation sensor provides a reference clock signal which is
temperature-dependent. An enable trigger is used to define counting cycles where the
reference clock pulses are accumulated to build the sensor value TCLR.THCOUNT. The
enable trigger is derived from the system clock by a prescaler and a programmable
divider (see Figure 6-30). The value for the programmable divider must be written by the
user according to the selected system frequency.
After the count cycle, the resulting count value, i.e. the number of reference clock cycles,
is copied to bit field TCLR.THCOUNT. Thus, TCLR.THCOUNT is updated after every
count cycle while the temperature compensation is enabled.
Software can compare the temperature-related count value (TCLR.THCOUNT) to
several thresholds (temperature levels) in order to determine the control values
TCCR.TCC.
fREF
OSC_TC
fSYS
Figure 6-30
32:1
N:1
Prescaler
Programmable Divider
N = (TCDIV+1)
fEnable
Temperature Compensation Clock Generation
The clock divider is programmed via bit field TCCR.TCDIV. The value that should be
used for bit field TCCR.TCDIV can be calculated using the following formula
documented in the data sheet.
Generally, temperature compensation is a user-controlled feature. The Temperature
Compensation Control Register TCCR provides access to the actual compensation
value (generated by the sensor) and allows software control of the pads. During
operation the device (i.e. the pads) can be controlled by the value of the on-chip sensor,
or by externally provided compensation values. Register TCCR also provides the
programmable divider value.
Note: The relation between the counter value and the temperature can differ between
two devices and need to be evaluated for each device individually.
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System Control Unit (SCU)
6.7.1
Temperature Compensation Registers
6.7.1.1
TCCR
This register contains the control options.
TCCR
Temperature Compensation RegisterESFR (F1ACH/D6H)
15
14
13
12
11
10
9
8
7
6
5
Reset Value: 0003H
4
3
2
1
0
0
TCE
TCDIV
TCC
r
rw
rw
rw
Field
Bits
Type
Description
TCC
[1:0]
rw
Temperature Compensation Control
The value which controls the temperature
compensation inputs of the pads.
00B Maximum reduction = min. driver strength,
i.e. very low temperature
11B No reduction = max. driver strength,
i.e. very high temperature
TCDIV
[6:2]
rw
Temperature Compensation Clock Divider
This value adjusts the temperature compensation
logic to the selected operating frequency.
TCE
7
rw
Temperature Compensation Enable
0B
No action
1B
Enable counting to generate new temperature
values.
Clearing this bit also stops the temperature
compensation.
0
[15:8]
r
Reserved
Read as 0; should be written with 0.
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System Control Unit (SCU)
TCLR
Temperature Comp. Level RegisterESFR (F0ACH/56H)
15
14
13
12
11
10
9
8
7
6
5
Reset Value: 0000H
4
3
0
THCOUNT
r
rh
2
1
0
Field
Bits
Type
Description
THCOUNT
[7:0]
rh
Threshold Counter
Returns the result of the most recent count cycle of
the temperature sensor, to be compared with the
thresholds.
0
[15:8]
r
Reserved
Read as 0; should be written with 0.
Note: The threshold counter will not overflow but rather stop at count 255.
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6.8
System Control Unit (SCU)
Watchdog Timer
The following part describes the WDT and its functionality.
6.8.1
Introduction
The Watchdog Timer (WDT) is a secure mechanism to overcome life- and dead-locks.
An enabled WDT generates a reset for the system if not serviced in a configured time
frame.
Features
The following list is a summary of the WDT functions:
•
•
•
•
•
16-bit Watchdog Timer
Selectable operating frequency: fIN / 256 or fIN / 16384
Timer overflow error detection
Individual disable for timer functionality
Double Reset Detection
Figure 6-31 provides an overview on the registers of the Watchdog Timer.
W DT Control &
Status Register
W DT Reload
Register
W DT Timer
Register
WDTCS
WDTREL
WDTTIM
WDTCS WDT Control and Status Register
WDTREL WDT Reload Register
WDTTIM WDT Timer Register
WDT_Reg_Overview.vsd
Figure 6-31 Watchdog Timer Register Overview
6.8.2
Overview
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failure. The WDT helps to abort an accidental
malfunction of the XC2000 in a user-specified time period. When enabled, the WDT will
cause the XC2000 system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to
prevent the WDT from causing a WDT reset request trigger. Hence, regular service of
the WDT confirms that the system is functioning properly.
A further enhancement in the Watchdog Timer is its reset prewarning operation. Instead
of immediately resetting the device on the detection of an error, a prewarning output is
given to the system via an interrupt request. This makes it possible to bring the system
into a defined and predictable status, before the reset is finally issued.
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6.8.3
System Control Unit (SCU)
Functional Description
The following part describes all functions of the WDT.
6.8.3.1
Timer Operation
The timer is enabled when instruction ENWDT (Enable Watchdog Timer) is executed
correctly. The 16-bit counter implementing the timer functionality is clocked either with
fIN / 256 or fIN / 16384. The selection of the counting rate is done via bit WDTCS.IR. The
counter is reloaded and the prescaler is cleared when one of the following conditions
occurs:
•
•
•
•
A successful access to register WDTREL
The WDT is serviced
A WDT overflow condition (Prewarning Mode is entered)
The Disable Mode is entered
Determining WDT Periods
The WDT uses an input clock fIN, which is equal to the system clock fsys. A clock divider
in front of the WDT timer provides two output frequencies, fIN / 256 and fIN / 16384. Bit
WDTCS.IR selects between these two options.
The general formula to calculate a Watchdog period is:
period =
⎛ 2 16 – startvalue⎞ ⋅ 256 ⋅ 2 ( 1 – IR ) ⋅ 6
⎝
⎠
----------------------------------------------------------------------------------------------------------------------------------IN
f
(6.4)
The parameter <startvalue> represents either the fixed value FFFCH for the calculation
of the Time-out Period, or the user-programmable reload value RELV for the calculation
of the Normal Period.
6.8.3.2
Timer Modes
The Watchdog Timer can operate in one of three different Timer Modes:
•
•
•
Normal Mode
Disable Mode
Prewarning Mode
Figure 6-32 provides a state diagram of the different Timer Modes and the transition
possibilities. Please refer to the description of the conditions for changing from one mode
to the other.
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System Control Unit (SCU)
Application
Reset
Normal
Mode
DISWDT
Timer
overflow
ENWDT
Pre-Warning
Mode
Disable
Mode
WDT Reset Trigger
WDTCS.OE set
WDT_modes
Figure 6-32 State Diagram of the Timer Modes
Normal Mode
The Normal Mode is the default mode after an application reset. Normal Mode can be
entered from Disable Mode only when instruction ENWDT is executed. The timer is
loaded with RELV when the Normal Mode is entered, and it starts counting upwards.
After reset, the timer is loaded with FFFCH, and it starts counting upwards. It has to be
serviced before the counter overflows. Servicing is performed by the CPU via
instructions SRVWDT and/or ENWDT.
If the WDT is not serviced before the timer overflows, a system malfunction is assumed,
a WDT error is generated, and Prewarning Mode is entered. A reset of the XC2000 is
imminent and can no longer be stopped.
Table 6-17
Timer Periods in Normal Mode
IS
Reload Min. / Period
Value Max.
0
0000H
FFFEH
User’s Manual
SCU, V1.1
Example
@ fIN= 40 MHz
min.
65535 × 16384 / fIN = 1073725440 / fIN
26.8 s
max.
65536 × 16384 / fIN = 1073741824 / fIN
26.8 s
min.
1 × 16384 / fIN = 16384 / fIN
410 µs
max.
2 × 16384 / fIN = 32768 / fIN
819 µs
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Table 6-17
System Control Unit (SCU)
Timer Periods in Normal Mode
IS
Reload Min. / Period
Value Max.
1
0000H
FFFEH
Example
@ fIN= 40 MHz
min.
65535 × 256 / fIN = 16776960 / fIN
419 ms
max.
65536 × 256 / fIN = 16777216 / fIN
419 ms
min.
1 × 256 / fIN = 256 / fIN
6.4 µs
max.
2 × 256 / fIN = 512 / fIN
12.8 µs
Disable Mode
Disable Mode is provided for applications that do not require the Watchdog Timer
function. Disable Mode is entered when instruction DISWDT is executed, either before
End-of-Init, if CPUCON1.WDTCTL = 0, or at any time, if CPUCON1.WDTCTL = 1. The
timer is cleared in this mode. A transition from Disable Mode to Normal Mode is
performed when instruction ENWDT is executed while CPUCON1.WDTCTL = 1 The
timer is reloaded and the prescalers are cleared on this transition.
Prewarning Mode
Prewarning Mode is entered always when a Watchdog error is detected. This is an
overflow in Normal Mode. Instead of immediately requesting a reset of the device, the
WDT enables the system to enter a secure state by issuing the prewarning output before
the reset occurs. Receiving the prewarning, the CPU and the system are requested to
finish all pending transaction requests and to not generate new ones. The prewarning is
signalled via an interrupt. The CPU can recognize the WDT prewarning interrupt via
register INTSTAT. After finishing all pending transactions, the CPU should execute the
IDLE instruction to stop all further processing before the coming reset.
In Prewarning mode, the WDT starts counting from FFFFH upwards, and then requests
a WDT reset on the overflow. This reset request - and following reset generation - can
not be avoided in this mode; the WDT does not react anymore to accesses to its
registers, nor will it change its state until it is reset.
A feature of the WDT detects double errors and sets the whole system into a permanent
WDT reset. This feature prevents the XC2000 from executing random wrong code for
longer than the Time-out Period, and prevents the XC2000 from being repeatedly reset
by the WDT.
Double WDT errors are detected with the aid of the error-indication flag WDTCS.OE.
Servicing the WDT automatically clears this bit. However, this bit is not cleared when a
reset is caused by the WDT reset. Because the error bit is preserved across resets
requested by the WDT, the WDT can examine if an overflow occurs again. If bit
WDTCS.OE is still set when a new WDT overflow occurs, then there must have been a
preceding WDT reset without a software service of the WDT in the meantime. Hence,
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this is a double WDT error condition. In this case, the WDT will generate another reset
after the termination of the Prewarning Mode, but this time, the XC2000 will be held in
the reset state until a power-up reset is generated by external hardware.
Note: Double WDT errors can only occur if the WDT reset is not configured to generate
a system reset.
6.8.3.3
WDT during Power-Saving Modes
During Offline Mode, the WDT cannot be serviced. Excluding the case where the system
is running normally, a strategy for managing the WDT is needed for the Offline Mode.
There are two ways to handle the WDT in this case.
First, the WDT can be disabled before going into Offline Mode. This has the
disadvantage that the system will no longer be monitored during the Offline period.
Second, the time the system stays in the Offline Mode can be configured with the wakeup timer in a way that the system is switched back to Active Mode before the WDT needs
to be serviced. Then the CPU can service the WDT again and return to the Offline Mode.
Note: Before switching into a non-running power-management mode, software should
perform a Watchdog service sequence. The Watchdog reload value RELV in
register WDTREL should be programmed such that the wake-up occurs after a
period which best meets application requirements.
6.8.3.4
Suspend Mode Support
In an enabled and active debug session, the Watchdog functionality can lead to
unintended resets. Therefore, to avoid these resets, the OCDS can control whether the
WDT is enabled or disabled (default after reset). This is done via bit CBS_IOSR.DB.
Table 6-18
OCDS Behavior of WDT
WDTCS.DS
CBS_DBGSR.DBGEN
CBS_IOSR.DB
WDT Action
1
X
X
Stopped
0
0
X
Running
0
1
0
Stopped
0
1
1
Running
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6.8.4
WDT Kernel Registers
6.8.4.1
WDT Reload Register
This register defines the WDT reload value.
WDTREL
WDT Reload Register
15
14
13
12
ESFR (F0C8H/64H)
11
10
9
8
7
6
Reset Value: FFFCH
5
4
3
2
1
0
RELV
rw
Field
Bits
Type
Description
RELV
[15:0]
rw
Reload Value for the Watchdog Timer
This bit field defines the reload value for the WDT.
6.8.4.2
WDT Control and Status Register
The Control and Status Register can only be accessed in Secured Mode.
WDTCS
WDT Control and Status RegisterESFR (F0C6H/63H)
15
14
13
User’s Manual
SCU, V1.1
12
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
0
IR
0
PR
DS
OE
r
rw
r
rh
rh
rh
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Field
Bits
Type
Description
OE
0
rh
Overflow Error Status Flag
0B
No WDT overflow error
1B
A WDT overflow error has occurred.
This bit is set by hardware when the Watchdog Timer
overflows from FFFFH to 0000H.
This bit is only cleared through:
• a system reset
• a correctly executed SRVWDT or ENWDT
instruction
However, it is not possible to clear this bit in
Prewarning Mode with the SRVWDT or ENWDT
instruction.
DS
1
rh
Timer Enable/Disable Status Flag
0B
Timer is enabled (default after reset).
1B
Timer is disabled.
This bit is cleared when instruction ENWDT was
executed.
This bit is set when instruction DISWDT was
executed.
PR
2
rh
Prewarning Mode Flag
Normal Mode (default after reset)
0B
1B
Prewarning Mode
IR
8
rw
Input Frequency Request Bit
0B
Request to set input frequency to fIN / 16384
1B
Request to set input frequency to fIN / 256
An update of this bit is taken into account after the
next successful execution of instruction SRVWDT or
ENWDT, on a write to register WDTREL, and always
when the WDT is in Disable Mode.
0
[7:3],
[15:9]
r
Reserved
Read as 0; should be written with 0;
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6.8.4.3
System Control Unit (SCU)
WDT Timer Register
WDTTIM
WDT Timer Register
15
14
13
12
ESFR (F0CAH/65H)
11
10
9
8
7
6
Reset Value: FFFCH
5
4
3
2
1
0
TIM
rh
Field
Bits
Type
Description
TIM
[15:0]
rh
Timer Value
Reflects the current contents of the Watchdog Timer.
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6.9
System Control Unit (SCU)
Wake-up Timer (WUT)
The wake-up timer provides a very compact (and, therefore, power-saving) means of reactivating the system automatically from certain power saving modes after a specific
period of time. The master clock fSYS is prescaled and drives a simple counter. All
functions are controlled by register WUCR.
Note: For wake-up operation, the master clock fSYS is usually derived from the wake-up
clock (OSC_WU). The interval numbers in Figure 6-33 are based on this
assumption.
PSC
Control
OSC_WU
WUCR.
TTSTAT
150 to 560 kHz
fWU
Trim
Interrupt
Trigger
Sync.
fSYS
64:1
run
427 to
114 us
reset
27.9 to 7.5 s (max)
Run
Control
from PSC
WUCR.
AONCON
W ake-up
Interrupt
Trigger
WUCR.
WUTRG
WIC
WUCR.
RUNCON
W ake-up
Trigger
WUCR.
ASPCON
Wake-Up Timer
WUT_Block.vsd
Figure 6-33 Wake-up Timer Logic
The wake-up timer is controlled by two registers, illustrated in Figure 6-34.
W UT Control
Register
W UT Timer
Register
WUCR
WICR
WUCR:
WICR:
Wake-up Control Register
Wake-up Interval Count Register
WUT_Reg_Overview.vsd
Figure 6-34 Wake-up Timer Register Overview
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6.9.1
System Control Unit (SCU)
Wake-Up Timer Operation
The wake-up timer start and stop is controlled by the Run Control logic. The timer can
be started in the following ways:
•
•
bit WUCR.RUN is set
bit WUCR.AON is set AND the PSC generates a start trigger
When the timer is started, the prescaler is reset and the counter WIC starts to count
down.
The wake-up interval counter (WIC) is clocked with fSYS/64, and counts down until it
reaches zero. It then generates a wake-up trigger and sets bit WUCR.WUTRG.
The timer is stopped in the following ways:
•
•
bit WUCR.RUN is cleared
bit WUCR.ASP is set AND a wake-up trigger is generated
If the WIC is not stopped by its zero trigger, it continues counting down from FFFFH.
When the WIC is used to wake up the XC2000 after a predefined period, the clock
system usually is driven by the wake-up clock OSC_WU. This allows the power domain
DMP_1 to be switched off to save energy. As the power-down period is then defined in
units of 64 fOSC_WU cycles, it is mandatory that the WIC starts counting down only when
fSYS is really generated by OSC_WU. This is controlled by the auto-start feature, where
the state transition mechanism can automatically start the WIC after selecting the correct
clock source.
The actual frequency of OSC_WU can be measured prior to entering power-save mode
in order to adjust the number of clock cycles to be counted (value written to WIC), and
such, to define the time until wake-up. The period of OSC_WU can be measured by
evaluating its (synchronized) clock output, which can generate an interrupt request or
which can be monitored via bit WUCR.TTSTAT.
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6.9.2
WUT Registers
6.9.2.1
Register WICR
Via this register, the status and configuration of the WIC counter is done.
WICR
Wake-up Interval Count RegisterESFR (F0B0H/58H)
15
14
13
12
11
10
9
8
7
6
Reset Value: FFFFH
5
4
3
2
1
0
WIC
rwh
Field
Bits
Type
Description
WIC
[15:0]
rwh
Wake-up Interval Counter
This free-running 16-bit counter counts down and
issues a trigger when its count reaches zero.
6.9.2.2
Register WUCR
This register holds the status and control bits for the WUT.
WUCR
Wake-up Control Register
15
14
13
WU TTS
TRG TAT
rh
rh
12
11
0
ESFR (F1B0H/D8H)
10
9
8
ASP AON RUN
r
rh
rh
rh
Reset Value: 0000H
7
6
5
4
3
2
1
CLR
TRG
0
ASP
CON
AON
CON
RUN
CON
w
r
w
w
w
Field
Bits
Type
Description
RUNCON
[1:0]
w
Control Field for RUN
00B No action
01B Set bit RUN
10B Clear bit RUN
11B Reserved, do not use this combination
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Field
Bits
Type
Description
AONCON
[3:2]
w
Control Field for AON
00B No action
01B Set bit AON
10B Clear bit AON
11B Reserved, do not use this combination
ASPCON
[5:4]
w
Control Field for ASP
00B No action
01B Set bit ASP
10B Clear bit ASP
11B Reserved, do not use this combination
CLRTRG
7
w
Clear Bit WUTRG
0B
No action
1B
Clear bit WUTRG
RUN
8
rh
Run Indicator
0B
Wake-up counter is stopped
1B
Wake-up counter is counting down
Note: Clearing this bit via a write action to bit field
RUNCON stops the WUT after four cycles of
fWUT.
AON
9
rh
Auto-Start Indicator
0B
Wake-up counter is started by software only
1B
Wake-up counter can be started by the PSC
mechanism
ASP
10
rh
Auto-Stop Indicator
0B
Wake-up counter runs continuously
1B
Wake-up counter stops after generating a
trigger when reaching zero
TTSTAT
14
rh
Trim Trigger Status
0B
No trim trigger event is active. No trim interrupt
trigger is generated.
1B
A trim trigger event is active. A trim interrupt
trigger is generated.
Note: This bit is not valid if fSYS = fWU is configured in
register SYSCON0.
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Field
Bits
Type
Description
WUTRG
15
rh
WUT Trigger Indicator
0B
No trigger event has occurred since WUTRG
has been cleared last. No interrupt trigger is
generated.
1B
A wake-up trigger event has occurred. A wakeup interrupt trigger is generated.
0
[7:6],
r
[13:11]
Reserved
Read as 0; should be written with 0;
Note: The bits in the upper byte of register WUCR indicate the current status of the
wake-up counter logic. They are not influenced by a write access, but are
controlled by their associated control fields (lower byte) or by hardware.
The control bit(field)s in the lower byte of register WUCR determine the state of
the status bits (upper byte) of the wake-up counter logic. Setting bits by software
triggers the associated action, writing 0 has no effect.
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6.10
System Control Unit (SCU)
Register Control
This block handles the register accesses of the SCU, and the register access control for
all system register that use one of the following protection modes:
•
•
•
Write Protection Mode
Secured Mode
Start-up Protection
6.10.1
Register Access Control
There are some dedicated registers that control critical system functions and modes.
These registers are protected by a special register security mechanism, such that these
vital system functions cannot be changed inadvertently after the execution of the EINIT
instruction. However, as these registers control central system behavior, they need to be
accessed during operation. The system control software gets this access via a special
security state machine.
This security mechanism controls four different security levels. Three can be configured
via register SLC. If an access violation is detected, a trap trigger request RAT (see
Section 6.11) is generated.
•
•
•
•
Start-up Protected Mode
This mode is entered when bit STCON.STP is cleared. Registers that use the startup code protection mechanism are marked with ’St’ in the protection list. Protected
registers are locked against any write access. Write accesses have no effect on
these registers.
Write Protected Mode
This mode is entered automatically after the EINIT instruction is executed. Registers
protected in this mode are locked against any write access. Write accesses have no
effect on these registers.
Secured Mode
Registers protected by the Secure Mode can be written using a special command.
Access can be achieved by preceding the intended write access with writing
“Command 4” to register SLC. Writing “Command 4” to register SLC enables writes
to protected registers until the next write access is issued. Thereafter, “Command 4”
has to be written again in order to enable the next write to a protected register.
Registers that are protected by this mode are marked with ’Sec’ in Table 6-23.
Unprotected Mode
This mode is entered after an application reset. No protection is active, registers can
be written at any time.
In addition to normal access parameters (e.g. read only, bit type r or rh), all registers that
are equipped with one of the protection mechanism have the access limitations defined
by the selected security level. Independently of the security level, all protected registers
can also be read.
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6.10.1.1 Controlling the Security Level
Two registers, the Security Level Command register (SLC) and the Security Level Status
register (SLS), control the security level. The SLC register accepts the commands to
control the state machine modifying the security level, while the SLS register shows the
actual password, the actual security level, and the state of the state machine.
C o mma n d 3 o r a n y w rite a cce ss
Sta te 0
C o mma n d 2
o r a n y w rite a cce ss
C om man d 0
C o mma n d 4
Sta te 3
C om man d 2
C la ss 3 R e se t
C o mma n d 1
o r a n y w rite a cce ss
An y w rite a cce ss
Sta te 4
Sta te 1
C o mma n d 1
Sta te 2
MCA05336
Figure 6-35 State Machine for Security Level Controlling
The following mechanism is used to control the actual security level:
•
Changing the security level
can be done by executing the following command sequence:
“Command 0 - Command 1 - Command 2 - Command 3”.
This sequence establishes a new security level and/or a new password.
Table 6-19
Commands for Security Level Control
Command
Definition
Command 0
AAAAH
Command 1
5554H
Command 2
96H || <inverse password>
Command 3
000B || <new level> || 000B || <new password>
Command 4
8EH || <inverse password>
Note
Secured Mode only
Note: It is recommended to lock all command sequences with an atomic sequence.
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6.10.2
System Control Unit (SCU)
Register Protection Registers
6.10.2.1 Register SLC
This register is the interface for the protection commands.
SLC
Security Level Command RegisterESFR (F0C0H/60H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
COMMAND
rw
Field
Bits
Type
Description
COMMAND
[15:0]
rw
Security Level Control Command
The commands to control the security level must be
written to this register (see Table 6-19)
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6.10.2.2 Register SLS
This register reflects the status of the register protection.
SLS
Security Level Status Register ESFR (F0C2H/61H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
STATE
SL
0
PASSWORD
rh
rh
r
rh
2
1
0
Field
Bits
Type
Description
PASSWORD
[7:0]
rh
Current Security Control Password
Default after reset = 00H
SL
[12:11] rh
Security Level 1)
00B Unprotected Mode (default)
01B Secured Mode
10B Reserved, do not use this combination
11B Write Protected Mode
STATE
[15:13] rh
Current State of Switching State Machine
000B Awaiting command 0 or command 4 (default)
001B Awaiting command 1
010B Awaiting command 2
011B Awaiting new security level and password
100B Next access granted in Secured Mode
101B Reserved, do not use this combination
11XB Reserved, do not use this combination
0
[10:8]
Reserved
Read as 0; should be written with 0;
1)
r
While the security level is “unprotected” after reset, it changes to “write protected” after the execution of
instruction EINIT.
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6.10.3
System Control Unit (SCU)
Miscellaneous System Control Registers
6.10.3.1 System Control Registers
The following register serves for various system tasks.
SYSCON1
System Control 1 Register
15
14
13
12
11
SFR (FF4CH/A6H)
10
9
8
7
6
Reset Value: 0003H
5
4
3
2
1
GLC OCD
CST SEN
0
r
rw
rw
0
0
rw
Field
Bits
Type
Description
OCDSEN
2
rw
OCDS/Cerberus Enable
0B
OCDS and Cerberus are still in reset state
1B
ODCS and Cerberus are operable
GLCCST
3
rw
Global CAPCOM Start
Bit GLCCST starts all CAPCOM units synchronously,
if enabled.
0B
CAPCOM timer start is controlled locally in
each unit
1B
All CAPCOM timers are started synchronously
GLCCST is automatically cleared in the clock cycle
after it was set.
0
[1:0]
rw
Reserved
Should be written with 0.
0
[15:4]
r
Reserved
Read as 0; should be written with 0.
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6.11
System Control Unit (SCU)
SCU Interrupt and Trap Handling
The SCU handles a number of interrupts and traps. It contains appropriate logic and
registers to enable/disable the request sources, to hold the request flags, to set or clear
the flags, and to distribute the requests to a given interrupt or trap node.
The interrupt structure is detailed in Section 6.11.1, while the trap structure is explained
in Section 6.11.3.
In order to not loose interrupts or traps during a power-save mode, a number of interrupt
and trap requests are fed through a sticky flag register in the DMP_M domain, before
being connected to the SCU interrupt or trap handling structure. In this way, the
occurrence of an event is registered even when the DMP_1 domain is powered down.
Details about this structure can be found in Section 6.11.5.
An additional part of the SCU structure facilitates the mapping of the interrupt request
sources in the system to the sixteen interrupt nodes CC2_CCxIC. These interrupt nodes
are shared between the CC2 and other interrupt sources. Details can be found in
Section 6.11.7.
1
request
Figure 6-36 provides an overview on the SCU interrupt and trap handling, while
Figure 6-37 shows the registers involved.
Interrupt Status
Register
INTSTAT
request
Interrupt
Events
SCU_IRQ0
to ITC Node 6C H
SCU Interrupt
Structure
SCU_IRQ1
disable
9
to ITC Node 6B H
9
4
request
9
4
request
Trap
Events
Int. & Trap
Trigger Reg.
DMPMIT
DMP_M
Domain
4
4
request
disable
DMP_1
Domain
SCU_TRQ0
Trap Status
Register
TRAPSTAT
to TFR.ACER
SCU_TRQ1
SCU Trap
Structure
to TFR.SR1
CC2
Interrupt
Sources
16
USIC & ERU
Interrupt
Sources
10
request
SCU_TRQ2
to TFR.SR0
Alternate Interrupt
Assignment Register
ISSR
16
to 16 ITC Nodes
CC2_CC16IC
..
CC2_CC31IC
SCU_Trap_Int_Overview.vsd
Figure 6-36 SCU Interrupt and Trap Overview
User’s Manual
SCU, V1.1
6-186
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
SCU Interrupt
Registers
DMP_M
Registers
SCU Trap
Registers
Interrupt
Assignment
INTSTAT
DMPMIT
TRAPSTAT
ISSR
INTCLR
DMPMITCLR
TRAPCLR
INTSET
TRAPSET
INTDIS
TRAPDIS
INTNP0
TRAPNP
INTNP1
INTSTAT:
INTCLR:
INTSET:
INTDIS:
INTNP0/1:
TRAPSTAT:
TRAPCLR:
TRAPSET:
TRAPDIS:
TRAPNP:
DMPMIT:
DMPMITCLR:
ISSR:
Interrupt Status Register
Interrupt Status Clear Register
Interrupt Status Set Register
Interrupt Disable Register
Interrupt Node Pointer Registers 0/1
Trap Status Register
Trap Status Clear Register
Trap Status Set Register
Trap Disable Register
Trap Node Pointer Register
DMP_M Interrupt and Trap Trigger Register
DMP_M Interrupt and Trap Trigger Clear Register
Alternate Interrupt Assignment Register
SCU_Trap_Int_Reg_Overview.vsd
Figure 6-37 SCU Interrupt and Trap Register Overview
6.11.1
SCU Interrupt Handling
The SCU receives ten interrupt request lines, listed in Table 6-20. The basic interrupt
structure of the SCU is shown in Figure 6-38. If enabled by the corresponding bit in
register INTDIS, an interrupt is triggered either by the incoming interrupt request line, or
by a software set of the respective bit in register INTSET. The trigger sets the respective
flag in register INTSTAT and is gated to one of two interrupt nodes, selected by the node
pointer registers INTNP0 or INTNP1.
Nine of the ten interrupt requests are first fed through a sticky flag register in the DMP_M
domain. In this way, the occurrence of a request is registered even when the DMP_1
domain, including the SCU, is powered down. The registered event can then be
processed when the SCU is in normal power mode again. Please note that the disable
control of register INTDIS also influences the sticky bit in register DMPMIT (see
Section 6.11.5).
The interrupt flag in register INTSTAT can be cleared by software by writing to the
corresponding bit in register INTCLR.
If more than one interrupt source is connected to the same interrupt node pointer (via
register INTNP0/1), the requests are combined to one common line.
User’s Manual
SCU, V1.1
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Table 6-20
SCU Interrupt Overview
Source of Interrupt
Short Name
Sticky Flag Default Interrupt Node
in DMPMIT (Request Output)
SWD OK 1 Interrupt
SWD_1
yes
Node 6CH (SCU_IRQ0)
SWD OK 2 Interrupt
SWD_2
yes
Node 6BH (SCU_IRQ1)
PVC_M OK 1 Interrupt
PVC_M1
yes
Node 6CH (SCU_IRQ0)
PVC_M OK 2 Interrupt
PVC_M2
yes
Node 6BH (SCU_IRQ1)
PVC_1 OK 1 Interrupt
PVC_1_1
yes
Node 6CH (SCU_IRQ0)
PVC_1 OK 2 Interrupt
PVC_1_2
yes
Node 6BH (SCU_IRQ1)
Wake-up Timer Interrupt
WUT
yes
Node 6BH (SCU_IRQ1)
Wake-up Trim Interrupt
WU
yes
Node 6CH (SCU_IRQ0)
Watchdog Timer Interrupt
WDT
--
Node 6BH (SCU_IRQ1)
GSC Interrupt
GSC
yes
Node 6CH (SCU_IRQ0)
INTNPn.y
INTCLR.x
Interrupt
Event
Sticky Flag request
DMPMIT.x
clear
Interrupt Flag
INTSTAT.x
1
SCU_IRQ0
to ISS Block and
ITC Node 6C H
1
SCU_IRQ1
to ISS Block and
ITC Node 6B H
set
1
&
reserved
disable
INTSET.x
reserved
INTDIS.x
SCU Interrupt Structure
other interrupt sources
controlled by the same INTNPn
SCU_Int_Struct.vsd
Figure 6-38 SCU Interrupt Structure
The ten interrupt sources of the SCU module can be mapped to two interrupt nodes, by
programming the interrupt node pointer registers INTNP0 and INTNP1. The default
assignment of the interrupt sources to the nodes and their corresponding control register
are shown in Table 6-20. This table also lists which of the interrupt requests have a
sticky flag in register DMPMIT in the DMP_M domain.
User’s Manual
SCU, V1.1
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.11.2
System Control Unit (SCU)
SCU Interrupt Control Registers
6.11.2.1 Register INTSTAT
This register contains the interrupt request status flags for all interrupt request trigger
sources of the SCU. For setting and clearing of the bits in this register by software,
please see registers INTSET and INTCLR, respectively.
INTSTAT
Interrupt Status Register
15
14
13
12
11
SFR (FF00H/80H)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
GSC WDT WU WUT PVC PVC PVC PVC SWD SWD
I
I
I
I
1I2 1I1 MI2 MI1 I2
I1
0
r
rh
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
SWDI1
0
rh
SWD Interrupt Request Flag 1
This bit is set if bit DMPMIT.SWDI1 is set.
0B
No interrupt was requested since this bit was
cleared the last time
1B
An interrupt was requested since this bit was
cleared the last time
This bit can be cleared by bit INTCLR.SWDI1.
This bit can be set by bit INTSET.SWDI1.
SWDI2
1
rh
SWD Interrupt Request Flag 2
This bit is set if bit DMPMIT.SWDI2 is set.
0B
No interrupt was requested since this bit was
cleared the last time
1B
An interrupt was requested since this bit was
cleared the last time
This bit can be cleared by bit INTCLR.SWDI2.
This bit can be set by bit INTSET.SWDI2.
PVCMI1
2
rh
PVC_M Interrupt Request Flag 1
This bit is set if bit DMPMIT.PVCMI1 is set.
0B
No interrupt was requested since this bit was
cleared the last time
1B
An interrupt was requested since this bit was
cleared the last time
This bit can be cleared by bit INTCLR.PVCMI1.
This bit can be set by bit INTSET.PVCMI1.
User’s Manual
SCU, V1.1
0
6-189
rh
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
PVCMI2
3
rh
PVC_M Interrupt Request Flag 2
This bit is set if bit DMPMIT.PVCMI2 is set.
0B
No interrupt was requested since this bit was
cleared the last time
An interrupt was requested since this bit was
1B
cleared the last time
This bit can be cleared by bit INTCLR.PVCMI2.
This bit can be set by bit INTSETPVCMI2.
PVC1I1
4
rh
PVC_1 Interrupt Request Flag 1
This bit is set if bit DMPMIT.PVC1I1 is set.
0B
No interrupt was requested since this bit was
cleared the last time
1B
An interrupt was requested since this bit was
cleared the last time
This bit can be cleared by bit INTCLR.PVC1I1.
This bit can be set by bit INTSET.PVC1I1.
PVC1I2
5
rh
PVC_1 Interrupt Request Flag 2
This bit is set if bit DMPMIT.PVC1I2 is set.
0B
No interrupt was requested since this bit was
cleared the last time
1B
An interrupt was requested since this bit was
cleared the last time
This bit can be cleared by bit INTCLR.PVC1I2.
This bit can be set by bit INTSET.PVC1I2.
WUTI
6
rh
Wake-up Timer Trim Interrupt Request Flag
This bit is set if the WUT trim trigger event occur and bit
is INTDIS.WUTI = 0.
0B
No interrupt was requested since this bit was
cleared the last time
1B
An interrupt was requested since this bit was
cleared the last time
This bit can be cleared by bit INTCLR.WUTI.
This bit can be set by bit INTSET.WUTI.
User’s Manual
SCU, V1.1
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
WUI
7
rh
Wake-up Timer Interrupt Request Flag
This bit is set if the WU trigger event occur and bit is
INTDIS.WUI = 0.
0B
No interrupt was requested since this bit was
cleared the last time
1B
An interrupt was requested since this bit was
cleared the last time
This bit can be cleared by bit INTCLR.WUI.
This bit can be set by bit INTSET.WUI.
WDTI
8
rh
Watchdog Timer Interrupt Request Flag
This bit is set if the WDT Prewarning Mode is entered
and bit is INTDIS.WDTI = 0.
0B
No interrupt was requested since this bit was
cleared the last time
1B
An interrupt was requested since this bit was
cleared the last time
This bit can be cleared by bit INTCLR.WDTI.
This bit can be set by bit INTSET.WDTI.
GSCI
9
rh
GSC Interrupt Request Flag
This bit is set if the GSC error bit is set and bit is
INTDIS.GSCI = 0.
0B
No interrupt was requested since this bit was
cleared the last time
1B
An interrupt was requested since this bit was
cleared the last time
This bit can be cleared by bit INTCLR.GSCI.
This bit can be set by bit INTSET.GSCI.
0
[15:10] r
User’s Manual
SCU, V1.1
Reserved
Read as 0; should be written with 0.
6-191
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
6.11.2.2 Register INTCLR
This register contains the software clear control for all interrupt request status flags of all
SCU interrupt request trigger sources.
Clearing a bit in this register has no effect, reading a bit always returns zero.
INTCLR
Interrupt Clear Register
15
14
13
12
SFR (FE82H/41H)
11
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
GSC WDT WU WUT PVC PVC PVC PVC SWD SWD
I
I
I
I
1I2 1I1 MI2 MI1 I2
I1
0
r
w
w
w
w
w
w
w
w
w
Field
Bits
Type Description
SWDI1
0
w
Clear SWD Interrupt Request Flag 1
Setting this bit clears bit INTSTAT.SWDI1.
Clearing this bit has no effect.
Reading this bit returns always zero.
SWDI2
1
w
Clear SWD Interrupt Request Flag 2
Setting this bit clears bit INTSTAT.SWDI2.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVCMI1
2
w
Clear PVC_M Interrupt Request Flag 1
Setting this bit clears bit INTSTAT.PVCMI1.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVCMI2
3
w
Clear PVC_M Interrupt Request Flag 2
Setting this bit clears bit INTSTAT.PVCMI2.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVC1I1
4
w
Clear PVC_1 Interrupt Request Flag 1
Setting this bit clears bit INTSTAT.PVC1I1.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVC1I2
5
w
Clear PVC_1 Interrupt Request Flag 2
Setting this bit clears bit INTSTAT.PVC1I2.
Clearing this bit has no effect.
Reading this bit returns always zero.
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0
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w
V1.0, 2007-06
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
WUTI
6
w
Clear Wake-up Trim Interrupt Request Flag
Setting this bit clears bit INTSTAT.WUTI.
Clearing this bit has no effect.
Reading this bit returns always zero.
WUI
7
w
Clear Wake-up Interrupt Request Flag
Setting this bit clears bit INTSTAT.WUI.
Clearing this bit has no effect.
Reading this bit returns always zero.
WDTI
8
w
Clear Watchdog Timer Interrupt Request Flag
Setting this bit clears bit INTSTAT.WDTI.
Clearing this bit has no effect.
Reading this bit returns always zero.
GSCI
9
w
Clear GSC Interrupt Request Flag
Setting this bit clears bit INTSTAT.GSCI.
Clearing this bit has no effect.
Reading this bit returns always zero.
0
[15:10] r
Reserved
Read as 0; should be written with 0
6.11.2.3 Register INTSET
This register contains the software set option for all interrupt request status flags of all
SCU interrupt request trigger sources.
Clearing a bit in this register has no effect, reading a bit always returns zero
INTSET
Interrupt Set Register
15
14
13
12
SFR (FE80H/40H)
11
10
9
8
6
5
4
3
2
1
0
GSC WDT WU WUT PVC PVC PVC PVC SWD SWD
I
I
I
I
1I2 1I1 MI2 MI1 I2
I1
0
r
w
w
Field
Bits
Type Description
SWDI1
0
w
User’s Manual
SCU, V1.1
7
Reset Value: 0000H
w
w
w
w
w
w
w
w
Set SWD Interrupt Request Flag 1
Setting this bit sets bit INTSTAT.SWDI1.
Clearing this bit has no effect.
Reading this bit returns always zero.
6-193
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Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
SWDI2
1
w
Set SWD Interrupt Request Flag 2
Setting this bit sets bit INTSTAT.SWDI2.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVCMI1
2
w
Set PVC_M Interrupt Request Flag 1
Setting this bit sets bit INTSTAT.PVCMI1.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVCMI2
3
w
Set PVC_M Interrupt Request Flag 2
Setting this bit sets bit INTSTAT.PVCMI2.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVC1I1
4
w
Set PVC_1 Interrupt Request Flag 1
Setting this bit sets bit INTSTAT.PVC1I1.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVC1I2
5
w
Set PVC_1 Interrupt Request Flag 2
Setting this bit sets bit INTSTAT.PVC1I2.
Clearing this bit has no effect.
Reading this bit returns always zero.
WUTI
6
w
Set Wake-up Trim Interrupt Request Flag
Setting this bit sets bit INTSTAT.WUTI.
Clearing this bit has no effect.
Reading this bit returns always zero.
WUI
7
w
Set Wake-up Interrupt Request Flag
Setting this bit sets bit INTSTAT.WUI.
Clearing this bit has no effect.
Reading this bit returns always zero.
WDTI
8
w
Set Watchdog Timer Interrupt Request Flag
Setting this bit sets bit INTSTAT.WDTI.
Clearing this bit has no effect.
Reading this bit returns always zero.
GSCI
9
w
Set GSC Interrupt Request Flag
Setting this bit sets bit INTSTAT.GSCI.
Clearing this bit has no effect.
Reading this bit returns always zero.
0
[15:10] r
User’s Manual
SCU, V1.1
Reserved
Read as 0; should be written with 0
6-194
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
6.11.2.4 Register INTDIS
This register contains the software disable control for all interrupt request trigger sources
of the SCU.
INTDIS
Interrupt Disable Register
15
14
13
12
11
SFR (FE84H/42H)
10
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
GSC WDT WU WUT PVC PVC PVC PVC SWD SWD
I
I
I
I
1I2 1I1 MI2 MI1 I2
I1
0
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
SWDI1
0
rw
Disable SWD Interrupt Request 1
0B
An interrupt request can be generated for this
source
1B
No interrupt request can be generated for this
source
SWDI2
1
rw
Disable SWD Interrupt Request 2
0B
An interrupt request can be generated for this
source
1B
No interrupt request can be generated for this
source
PVCMI1
2
rw
Disable PVC_M Interrupt Request 1
0B
An interrupt request can be generated for this
source
1B
No interrupt request can be generated for this
source
PVCMI2
3
rw
Disable PVC_M Interrupt Request 2
0B
An interrupt request can be generated for this
source
1B
No interrupt request can be generated for this
source
PVC1I1
4
rw
Disable PVC_1 Interrupt Request 1
0B
An interrupt request can be generated for this
source
1B
No interrupt request can be generated for this
source
User’s Manual
SCU, V1.1
6-195
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
PVC1I2
5
rw
Disable PVC_1 Interrupt Request 2
0B
An interrupt request can be generated for this
source
1B
No interrupt request can be generated for this
source
WUTI
6
rw
Disable Wake-up Trim Interrupt Request
0B
An interrupt request can be generated for this
source
1B
No interrupt request can be generated for this
source
WUI
7
rw
Disable Wake-up Interrupt Request
An interrupt request can be generated for this
0B
source
1B
No interrupt request can be generated for this
source
WDTI
8
rw
Disable Watchdog Timer Interrupt Request
0B
An interrupt request can be generated for this
source
1B
No interrupt request can be generated for this
source
GSCI
9
rw
Disable GSC Interrupt Request
0B
An interrupt request can be generated for this
source
1B
No interrupt request can be generated for this
source
0
[15:10] r
Reserved
Read as 0; should be written with 0
6.11.2.5 Registers INTNP0 and INPNP1
These registers contain the control for the interrupt node pointers of all SCU interrupt
request trigger sources.
INTNP0
Interrupt Node Pointer 0 RegisterSFR (FE86H/43H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 4444H
5
4
3
2
1
0
WU
WUT
PVC12
PVC11
PVCM2
PVCM1
SWD2
SWD1
rw
rw
rw
rw
rw
rw
rw
rw
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SCU, V1.1
6-196
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
SWD1
[1:0]
rw
Interrupt Node Pointer for SWD 1 Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit
INTSTAT.SWDI1 (if enabled by bit INTDIS.SWDI1).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
SWD2
[3:2]
rw
Interrupt Node Pointer for SWD 2 Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit
INTSTAT.SWDI2 (if enabled by bit INTDIS.SWDI2).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
PVCM1
[5:4]
rw
Interrupt Node Pointer for PVC_M 1 Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit
INTSTAT.PCVMI1 (if enabled by bit INTDIS.PVCMI1).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
PVCM2
[7:6]
rw
Interrupt Node Pointer for PVC_M 2 Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit
INTSTAT.PCVMI2 (if enabled by bit INTDIS.PVCMI2).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
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SCU, V1.1
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
PVC11
[9:8]
rw
Interrupt Node Pointer for PVC_1 1 Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit
INTSTAT.PCV1I1 (if enabled by bit INTDIS.PVC1I1).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
PVC12
[11:10] rw
Interrupt Node Pointer for PVC_1 2 Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit
INTSTAT.PCV1I2 (if enabled by bit INTDIS.PVC1I2).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
WUT
[13:12] rw
Interrupt Node Pointer for WU Trim Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit
INTSTAT.WUTI (if enabled by bit INTDIS.WUTI).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
WU
[15:14] rw
Interrupt Node Pointer for WU Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit
INTSTAT.WUI (if enabled by bit INTDIS.WUI).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
INTNP1
Interrupt Node Pointer 1 RegisterSFR (FE88H/44H)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0001H
5
4
3
2
1
0
0
GSC
WDT
r
rw
rw
Field
Bits
Type Description
WDT
[1:0]
rw
Interrupt Node Pointer for WDT Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit INTSTAT.WDTI
(if enabled by bit INTDIS.WDTI).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
GSC
[3:2]
rw
Interrupt Node Pointer for GSC Interrupts
This bit field defines the interrupt node, which is
requested due to the set condition for bit INTSTAT.GSCI
(if enabled by bit INTDIS.GSCI).
00B Interrupt node 6CH is selected
01B Interrupt node 6BH is selected
10B Reserved, do not use this combination
11B Reserved, do not use this combination
0
[15:4] r
User’s Manual
SCU, V1.1
Reserved
Read as 0; should be written with 0
6-199
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Preliminary
6.11.3
System Control Unit (SCU)
SCU Trap Generation
The SCU receives eight trap lines, listed in Table 6-21. The basic trap structure of the
SCU is shown in Figure 6-39. If enabled by the corresponding bit in register TRAPDIS,
a trap is triggered either by a pulse on the incoming trap line, or by a software set of the
respective bit in register TRAPSET. The trigger sets the respective flag in register
TRAPSTAT and is gated to one of three trap nodes, selected by the node pointer register
TRAPNP.
Four of the eight trap requests are first fed through a sticky flag register in the DMP_M
domain. In this way, the occurrence of a request is registered even when the DMP_1
domain, including the SCU, is powered down. The registered event can then be
processed when the SCU is in normal power mode again. Please note that the disable
control of register TRAPDIS also influences the sticky bit in register DMPMIT (see
Section 6.11.5).
The trap flag in register TRAPSTAT can be cleared by software by writing to the
corresponding bit in register TRAPCLR.
If more than one trap source is connected to the same trap node pointer (via register
TRAPNP), the requests are combined to one common line.
Table 6-21
SCU Trap Request Overview
Source of Trap
Short Name
Sticky Flag
in DMPMIT
Default Trap Flag
Assignment in
Register TFR
Flash Access Traps
FA
---
TFR.ACER (SCU_TRQ0)
ESR0 Traps
ESR0
yes
TFR.SR1 (SCU_TRQ1)
ESR1 Traps
ESR1
yes
TFR.SR1 (SCU_TRQ1)
ESR2 Traps
ESR2
yes
TFR.SR1 (SCU_TRQ1)
PLL Traps
OSCWDT
---
TFR.SR1 (SCU_TRQ1)
Register Access Traps
RA
yes
TFR.ACER (SCU_TRQ0)
Parity Error Traps
PE
---
TFR.ACER (SCU_TRQ0)
VCO Lock Traps
VCOLCK
---
TFR.SR0 (SCU_TRQ2)
User’s Manual
SCU, V1.1
6-200
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
TRAPNP.y
TRAPCLR.x
Trap
Event
Sticky Flag request
DMPMIT.x
disable
clear
Trap Flag
TRAPSTAT.x
1
SCU_TRQ0
to TFR.ACER
set
1
1
&
SCU_TRQ1
to TFR.SR1
1
TRAPSET.x
SCU_TRQ2
to TFR.SR0
reserved
TRAPDIS.x
SCU Trap Structure
other trap sources controlled
by the same TRAPNP
SCU_Trap_Struct.vsd
Figure 6-39 SCU Trap Structure
The eight trap sources of the system can be mapped to three trap nodes by programming
the trap node pointer registers TRAPNP. The default assignment of the trap sources to
the nodes and their corresponding control register is listed in Table 6-21. This table also
lists which of the trap requests have a sticky flag in register DMPMIT in the DMP_M
domain.
User’s Manual
SCU, V1.1
6-201
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.11.4
System Control Unit (SCU)
SCU Trap Control Registers
6.11.4.1 Register TRAPSTAT
This register contains the status flags for all trap request trigger sources of the SCU.
For setting and clearing of these status bits by software, please see registers TRAPSET
and TRAPCLR, respectively.
TRAPSTAT
Trap Status Register
15
14
13
12
SFR (FF02H/81H)
11
10
9
8
7
6
VCO
PE
LCK
T
T
rh
rh
0
r
Reset Value: 0000H
5
4
3
2
1
OSC
RA
ESR ESR ESR
WDT
T
2T
1T
0T
T
rh
rh
rh
rh
rh
0
FA
T
rh
Field
Bits
Type Description
FAT
0
rh
Flash Access Trap Request Flag
TRAPSTAT.FAT is set when a flash access violation
occurs and TRAPDIS.FAT = 0.
No pending FAT trap request
0B
1B
An FAT trap request is pending
ESR0T
1
rh
ESR0 Trap Request Flag
TRAPSTAT.ESR0T is set when bit DMPMIT.ESR0T is
set and TRAPDIS.ESR0T = 0.
0B
No pending ESR0 trap request
1B
An ESR0 trap request is pending
ESR1T
2
rh
ESR1 Trap Request Flag
TRAPSTAT.ESR1T is set when bit DMPMIT.ESR1T is
set and TRAPDIS.ESR1T = 0.
0B
No pending ESR1 trap request
1B
An ESR1 trap request is pending
ESR2T
3
rh
ESR2 Trap Request Flag
TRAPSTAT.ESR2T is set when bit DMPMIT.ESR0T is
set and TRAPDIS.ESR2T = 0.
0B
No pending ESR2 trap request
An ESR2 trap request is pending
1B
User’s Manual
SCU, V1.1
6-202
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
OSCWDTT
4
rh
OSCWDT Trap Request Flag
TRAPSTAT.OSCWDTT is set when an OSCWDT
emergency event occurs and TRAPDIS.OSCWDTT = 0.
0B
No pending OSCWDT trap request
1B
An OSCWDT trap request is pending
RAT
5
rh
Register Access Trap Request Flag
TRAPSTAT.RAT is set when bit DMPMIT.RAT is set
and TRAPDIS.RAT = 0.
0B
No pending RAT trap request
An RAT trap request is pending
1B
PET
6
rh
Parity Error Trap Request Flag
TRAPSTAT.PET is set when a memory parity error
occurs and TRAPDIS.PET = 0.
0B
No pending PET trap request
1B
An PET trap request is pending
VCOLCKT
7
rh
VCOWDT Trap Request Flag
TRAPSTAT.VCOLCKT is set when a VCOLCK
emergency event occurs and TRAPDIS.VCOLCKT = 0.
0B
No pending VCOLCK trap request
1B
An VCOLCK trap request is pending
0
[15:8] r
User’s Manual
SCU, V1.1
Reserved
Read as 0; should be written with 0.
6-203
V1.0, 2007-06
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
6.11.4.2 Register TRAPCLR
This register contains the software clear control for the trap status flags in register
TRAPSTAT. Clearing a bit in this register has no effect, reading a bit always returns zero.
TRAPCLR
Trap Clear Register
15
14
13
SFR (FE8EH/47H)
12
11
10
9
8
7
6
VCO
PE
LCK
T
T
w
w
0
r
Reset Value: 0000H
5
4
3
2
1
OSC
RA
ESR ESR ESR
WDT
T
2
1
0
T
w
w
w
w
w
Field
Bits
Type Description
FAT
0
w
Clear Flash Access Trap Request Flag
0B
Flag TRAPSTAT.FAT is left unchanged
1B
Flag TRAPSTAT.FAT is cleared
ESR0T
1
w
Clear ESR0 Trap Request Flag
Flag TRAPSTAT.ESR0T is left unchanged
0B
1B
Flag TRAPSTAT.ESR0T is cleared
ESR1T
2
w
Clear ESR1 Trap Request Flag
0B
Flag TRAPSTAT.ESR1T is left unchanged
1B
Flag TRAPSTAT.ESR1T is cleared
ESR2T
3
w
Clear ESR2 Trap Request Flag
0B
Flag TRAPSTAT.ESR2T is left unchanged
1B
Flag TRAPSTAT.ESR2T is cleared
OSCWDTT
4
w
Clear OSCWDT Trap Request Flag
0B
Flag TRAPSTAT.OSCWDTT is left unchanged
1B
Flag TRAPSTAT.OSCWDTT is cleared
RAT
5
w
Clear Register Access Trap Request Flag
0B
Flag TRAPSTAT.RAT is left unchanged
1B
Flag TRAPSTAT.RAT is cleared
PET
6
w
Clear Parity Error Access Trap Request Flag
0B
Flag TRAPSTAT.PET is left unchanged
1B
Flag TRAPSTAT.PET is cleared
VCOLCKT
7
w
Clear VCOLCK Trap Request Flag
0B
Flag TRAPSTAT.VCOLCKT is left unchanged
1B
Flag TRAPSTAT.VCOLCKT is cleared
User’s Manual
SCU, V1.1
6-204
0
FA
T
w
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
0
[15:8] r
Reserved
Read as 0; should be written with 0
6.11.4.3 Register TRAPSET
This register contains the software set control for the trap status flags in register
TRAPSTAT. Clearing a bit in this register has no effect, reading a bit always returns zero.
TRAPSET
Trap Set Register
15
14
13
SFR (FE8CH/46H)
12
11
10
9
8
7
6
VCO
PE
LCK
T
T
w
w
0
r
Reset Value: 0000H
5
4
3
2
1
OSC
RA
ESR ESR ESR
WDT
T
2T
1T
0T
T
w
w
w
w
w
0
FA
T
w
Field
Bits
Type Description
FAT
0
w
Set Flash Access Trap Request Flag
0B
Flag TRAPSTAT.FAT is left unchanged
1B
Flag TRAPSTAT.FAT is set
ESR0T
1
w
Set ESR0 Trap Request Flag
0B
Flag TRAPSTAT.ESR0T is left unchanged
1B
Flag TRAPSTAT.ESR0T is set
ESR1T
2
w
Set ESR1 Trap Request Flag
0B
Flag TRAPSTAT.ESR1T is left unchanged
1B
Flag TRAPSTAT.ESR1T is set
ESR2T
3
w
Set ESR2 Trap Request Flag
0B
Flag TRAPSTAT.ESR2T is left unchanged
1B
Flag TRAPSTAT.ESR2T is set
OSCWDTT
4
w
Set OSCWDT Trap Request Flag
0B
Flag TRAPSTAT.OSCWDTT is left unchanged
1B
Flag TRAPSTAT.OSCWDTT is set
RAT
5
w
Set Register Access Trap Request Flag
Flag TRAPSTAT.RAT is left unchanged
0B
1B
Flag TRAPSTAT.RAT is set
User’s Manual
SCU, V1.1
6-205
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
PET
6
w
Set Parity Error Access Trap Request Flag
0B
Flag TRAPSTAT.PET is left unchanged
1B
Flag TRAPSTAT.PET is set
VCOLCKT
7
w
Set VCOLCK Trap Request Flag
Flag TRAPSTAT.VCOLCKT is left unchanged
0B
Flag TRAPSTAT.VCOLCKT is set
1B
0
[15:8] r
Reserved
Read as 0; should be written with 0.
6.11.4.4 Register TRAPDIS
This register contains the software disable control for all trap request trigger sources.
Note that the bits ESRxT and RAT in this register also disable the setting of the
respective flags in register DMPMIT (see Section 6.11.5).
TRAPDIS
Trap Disable Register
15
14
13
12
SFR (FE90H/48H)
11
10
9
8
7
6
VCO
PE
LCK
T
T
rw
rw
0
r
Reset Value: 009EH
5
4
3
Bits
Type
Description
FAT
0
rw
Disable Flash Access Trap Request
0B
FAT trap request enabled
1B
FAT trap request disabled
ESR0T
1
rw
Disable ESR0 Trap Request
0B
ESR0 trap request enabled
1B
ESR0 trap request disabled
ESR1T
2
rw
Disable ESR1 Trap Request
0B
ESR1 trap request enabled
1B
ESR1 trap request disabled
ESR2T
3
rw
Disable ESR2 Trap Request
0B
ESR2 trap request enabled
1B
ESR2 trap request disabled
6-206
1
OSC
RA
ESR ESR ESR
WDT
T
2
2
0
T
rw
rw
rw
rw
rw
Field
User’s Manual
SCU, V1.1
2
0
FA
T
rw
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type
Description
OSCWDTT
4
rw
Disable OSCWDT Trap Request
0B
OSCWDT trap request enabled
1B
OSCWDT trap request disabled
RAT
5
rw
Disable Register Access Trap Request
RAT trap request enabled
0B
RAT trap request disabled
1B
PET
6
rw
Disable Parity Error Trap Request
0B
PET trap request enabled
1B
PET trap request disabled
VCOLCKT
7
rw
Disable VCOLCK Trap Request
0B
VCOLCK trap request enabled
1B
VCOLCK trap request disabled
0
[15:8]
r
Reserved
Read as 0; should be written with 0.
6.11.4.5 Register TRAPNP
This register contains the control for the trap node pointers of all SCU trap request trigger
sources.
TRAPNP
Trap Node Pointer Register
15
14
13
12
11
10
SFR (FE92H/49H)
9
8
7
6
Reset Value: 8254H
5
4
3
2
1
0
VCOLCK
PE
RA
OSCWDT
ESR2
ESR1
ESR0
FA
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
FA
[1:0]
rw
User’s Manual
SCU, V1.1
Trap Node Pointer for Flash Access Traps
TRAPNP.FA selects the trap request output for an
enabled FAT trap request.
00B Select request output SCU_TRQ0 (TFR.ACER)
01B Select request output SCU_TRQ1 (TFR.SR1)
10B Select request output SCU_TRQ2 (TFR.SR0)
11B Reserved, do not use this combination
6-207
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
ESR0
[3:2]
rw
Trap Node Pointer for ESR0 Traps
TRAPNP.ESR0 selects the trap request output for an
enabled ESR0 trap request.
00B Select request output SCU_TRQ0 (TFR.ACER)
01B Select request output SCU_TRQ1 (TFR.SR1)
10B Select request output SCU_TRQ2 (TFR.SR0)
11B Reserved, do not use this combination
ESR1
[5:4]
rw
Trap Node Pointer for ESR1 Traps
TRAPNP.ESR1 selects the trap request output for an
enabled ESR1 trap request.
00B Select request output SCU_TRQ0 (TFR.ACER)
01B Select request output SCU_TRQ1 (TFR.SR1)
10B Select request output SCU_TRQ2 (TFR.SR0)
11B Reserved, do not use this combination
ESR2
[7:6]
rw
Trap Node Pointer for ESR2 Traps
TRAPNP.ESR2 selects the trap request output for an
enabled ESR2 trap request.
00B Select request output SCU_TRQ0 (TFR.ACER)
01B Select request output SCU_TRQ1 (TFR.SR1)
10B Select request output SCU_TRQ2 (TFR.SR0)
11B Reserved, do not use this combination
OSCWDT
[9:8]
rw
Trap Node Pointer for OSCWDT Traps
TRAPNP.OSCWDT selects the trap request output for
an enabled OSCWDT trap request.
00B Select request output SCU_TRQ0 (TFR.ACER)
01B Select request output SCU_TRQ1 (TFR.SR1)
10B Select request output SCU_TRQ2 (TFR.SR0)
11B Reserved, do not use this combination
RA
[11:10] rw
Trap Node Pointer for Register Access Traps
TRAPNP.RA selects the trap request output for an
enabled RAT trap request.
00B Select request output SCU_TRQ0 (TFR.ACER)
01B Select request output SCU_TRQ1 (TFR.SR1)
10B Select request output SCU_TRQ2 (TFR.SR0)
11B Reserved, do not use this combination
User’s Manual
SCU, V1.1
6-208
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
PE
[13:12] rw
Trap Node Pointer for Parity Error Traps
TRAPNP.PE selects the trap request output for an
enabled PET trap request.
00B Select request output SCU_TRQ0 (TFR.ACER)
01B Select request output SCU_TRQ1 (TFR.SR1)
10B Select request output SCU_TRQ2 (TFR.SR0)
11B Reserved, do not use this combination
VCOLCK
[15:14] rw
Trap Node Pointer for VCOLCK Traps
TRAPNP.VCOLCK selects the trap request output for
an enabled VCOLCK trap request.
00B Select request output SCU_TRQ0 (TFR.ACER)
01B Select request output SCU_TRQ1 (TFR.SR1)
10B Select request output SCU_TRQ2 (TFR.SR0)
11B Reserved, do not use this combination
User’s Manual
SCU, V1.1
Type Description
6-209
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.11.5
System Control Unit (SCU)
DPM_M Interrupt and Trap Support
For a number of SCU interrupt and trap requests, sticky status flags are implemented
additionally in the DMP_M. These flags are set with a trigger, and if set, trigger the
interrupt or trap generation in the DMP_1 SCU. In this way, no trap trigger is lost, even
when the DMP_1 is currently not powered. The flags are located in register DMPMIT.
Please note that the disable control bits in registers INTDIS and TRAPDIS also control
the setting of the respective DMPMIT.x flag, as illustrated in Figure 6-40.
DMPMITCLR.x
Interrupt
or Trap
Event
clear
Interrupt / Trap Trigger
Flag DMPMIT.x
request
to SCU
Interrupt/Trap
Structure
disable
INTDIS.x
TRAPDIS.x
set
&
DMP_M
SCU_DMPMIT_Struct.vsd
Figure 6-40 DPM_M Sticky Interrupt and Trap Flags
User’s Manual
SCU, V1.1
6-210
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.11.6
System Control Unit (SCU)
DPM_M Interrupt and Trap Registers
6.11.6.1 Register DMPMIT
This register holds the sticky interrupt and trap flags within the DMP_M power domain.
DMPMIT
DMP_M Int. and Trap Trigger RegisterSFR (FE96H/4BH)
15
14
RAT
0
rh
rh
13
12
11
ESR ESR ESR
2T
1T
0T
rh
rh
rh
10
9
0
rh
8
7
GSCI WUI
rh
rh
6
5
Reset Value: 0000H
4
3
2
1
0
WUT PVC PVC PVC PVC SWD SWD
I
1I2 1I1 MI2 MI1 I2
I1
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
SWDI1
0
rh
SWD Interrupt Request Flag 1
This bit is set if bit SWDCON0.L1OK is cleared and
SWDCON0.L1ACON = 01B and bit is INTDIS.SWDI1 = 0.
0B
No interrupt was requested since this bit was cleared the
last time
1B
An interrupt was requested since this bit was cleared the
last time
SWDI2
1
rh
SWD Interrupt Request Flag 2
This bit is set if bit SWDCON0.L2OK is cleared and
SWDCON0.L2ACON = 01B and bit is INTDIS.SWDI2 = 0.
0B
No interrupt was requested since this bit was cleared the
last time
1B
An interrupt was requested since this bit was cleared the
last time
PVCMI1 2
rh
PVC_M Interrupt Request Flag 1
This bit is set if bit PVCMCON0.L1OK is cleared and
PVCMCON0.L1INTEN = 1B and bit is INTDIS.PVCMI1 = 0.
0B
No interrupt was requested since this bit was cleared the
last time
1B
An interrupt was requested since this bit was cleared the
last time
User’s Manual
SCU, V1.1
6-211
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Field
Bits
System Control Unit (SCU)
Type Description
PVCMI2 3
rh
PVC_M Interrupt Request Flag 2
This bit is set if bit PVCMCON0.L2OK is cleared and
PVCMCON0.L2INTEN = 1B and bit is INTDIS.PVCMI2 = 0.
No interrupt was requested since this bit was cleared the
0B
last time
1B
An interrupt was requested since this bit was cleared the
last time
PVC1I1
4
rh
PVC_1 Interrupt Request Flag 1
This bit is set if bit PVC1CON0.L1OK is cleared and
PVC1CON0.L1INTEN = 1B and bit is INTDIS.PVC1I1 = 0.
0B
No interrupt was requested since this bit was cleared the
last time
1B
An interrupt was requested since this bit was cleared the
last time
PVC1I2
5
rh
PVC_1 Interrupt Request Flag 2
This bit is set if bit PVC1CON0.L2OK is cleared and
PVC1CON0.L2INTEN = 1B and bit is INTDIS.PVC1I2 = 0.
No interrupt was requested since this bit was cleared the
0B
last time
1B
An interrupt was requested since this bit was cleared the
last time
WUTI
6
rh
Wake-up Trim Interrupt Request Flag
This bit is set if a wake-up trim trigger occurs and bit is
INTDIS.WUTI = 0.
0B
No interrupt was requested since this bit was cleared the
last time
1B
An interrupt was requested since this bit was cleared the
last time
WUI
7
rh
Wake-up Interrupt Request Flag
This bit is set if a wake-up trigger occurs and bit is
INTDIS.WUI = 0.
No interrupt was requested since this bit was cleared the
0B
last time
1B
An interrupt was requested since this bit was cleared the
last time
User’s Manual
SCU, V1.1
6-212
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
GSCI
8
rh
GSC Interrupt Request Flag
This bit is set if a GSC trigger occurs and bit is
INTDIS.GSCI = 0.
0B
No interrupt was requested since this bit was cleared the
last time
1B
An interrupt was requested since this bit was cleared the
last time
ESR0T
11
rh
ESR0 Trap Request Flag
This bit is set if pin ESR0 is asserted.
No trap was requested since this bit was cleared the last
0B
time
1B
A trap was requested since this bit was cleared the last
time
ESR1T
12
rh
ESR1 Trap Request Flag
This bit is set if pin ESR1 is asserted.
0B
No trap was requested since this bit was cleared the last
time
1B
A trap was requested since this bit was cleared the last
time
ESR2T
13
rh
ESR2 Trap Request Flag
This bit is set if pin ESR2 is asserted.
0B
No trap was requested since this bit was cleared the last
time
1B
A trap was requested since this bit was cleared the last
time
RAT
15
rh
Register Access Trap Request Flag
This bit is set a protected register is written by an nonauthorized access.
No trap was requested since this bit was cleared the last
0B
time
1B
A trap was requested since this bit was cleared the last
time
0
[10:9] rh
14
User’s Manual
SCU, V1.1
Reserved
Read as 0; should be written with 0.
6-213
V1.0, 2007-06
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System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
6.11.6.2 Register DMPMITCLR
This register contains the software clear control for all status flags of all interrupt and trap
request trigger sources of the DMP_M power domain.
Clearing a bit in this register has no effect, reading a bit always returns zero.
DMPMITCLR
DMP_M Int. and Trap Clear RegisterSFR (FE98H/4CH)
15
14
RAT
0
w
r
13
12
11
ESR ESR ESR
2T
1T
0T
w
w
w
10
9
0
r
8
7
GSCI WUI
w
w
6
Reset Value: 0000H
5
4
3
w
w
w
w
Bits
Type Description
SWDI1
0
w
Clear SWD1 Interrupt Request Flag 1
Setting this bit clears bit DMPMIT.SWDI1.
Clearing this bit has no effect.
Reading this bit returns always zero.
SWDI2
1
w
Clear SWD Interrupt Request Flag 2
Setting this bit clears bit DMPMIT.SWDI2.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVCMI1
2
w
Clear PVC_M Interrupt Request Flag 1
Setting this bit clears bit DMPMIT.PVCM1I1.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVCMI2
3
w
Clear PVC_M Interrupt Request Flag 2
Setting this bit clears bit DMPMIT.PVCM1I2.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVC1I1
4
w
Clear PVC_1 Interrupt Request Flag 1
Setting this bit clears bit DMPMIT.PVC1I1.
Clearing this bit has no effect.
Reading this bit returns always zero.
PVC1I2
5
w
Clear PVC_1 Interrupt Request Flag 2
Setting this bit clears bit DMPMIT.PVC1I2.
Clearing this bit has no effect.
Reading this bit returns always zero.
6-214
1
0
WUT PVC PVC PVC PVC SWD SWD
I
1I2 1I1 MI2 MI1 I2
I1
Field
User’s Manual
SCU, V1.1
2
w
w
w
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits
Type Description
WUTI
6
w
Clear Wake-up Trim Interrupt Request Flag
Setting this bit clears bit DMPMIT.WUTI.
Clearing this bit has no effect.
Reading this bit returns always zero.
WUI
7
w
Clear Wake-up Interrupt Request Flag
Setting this bit clears bit DMPMIT.WUI.
Clearing this bit has no effect.
Reading this bit returns always zero.
GSCI
8
w
Clear GSC Interrupt Request Flag
Setting this bit clears bit DMPMIT.GSCI.
Clearing this bit has no effect.
Reading this bit returns always zero.
ESR0T
11
w
Clear ESR0 Trap Request Flag
Setting this bit clears bit DMPMIT.ESR0T.
Clearing this bit has no effect.
Reading this bit returns always zero.
ESR1T
12
w
Clear ESR1 Trap Request Flag
Setting this bit clears bit DMPMIT.ESR1T.
Clearing this bit has no effect.
Reading this bit returns always zero.
ESR2T
13
w
Clear ESR2 Trap Request Flag
Setting this bit clears bit DMPMIT.ESR2T.
Clearing this bit has no effect.
Reading this bit returns always zero.
RAT
15
w
Clear Register Access Trap Request Flag
Setting this bit clears bit DMPMIT.RAT.
Clearing this bit has no effect.
Reading this bit returns always zero.
0
[10:9] r
14
User’s Manual
SCU, V1.1
Reserved
Read as 0; should be written with 0.
6-215
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.11.7
System Control Unit (SCU)
Alternate Interrupt Assignment Register
6.11.7.1 Register ISSR
In order to map the interrupt request sources in the complete system to the available
interrupt nodes, 16 interrupt nodes are shared between the CC2 and other interrupt
sources.
ISSR
Interrupt Source Select RegisterSFR (FF2EH/97H)
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ISS
15
ISS
14
ISS
13
ISS
12
ISS
11
ISS
10
ISS
9
ISS
8
ISS
7
ISS
6
ISS
5
ISS
4
ISS
3
ISS
2
ISS
1
ISS
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits Type Description
ISS0
0
rw
Interrupt Source Select for CCU2_CC16IC
0B
CCU2 channel 16 is used as interrupt source
1B
External interrupt request ERU_IOUT0 is used
ISS1
1
rw
Interrupt Source Select for CCU2_CC17IC
0B
CCU2 channel 17 is used as interrupt source
1B
External interrupt request ERU_IOUT1 is used
ISS2
2
rw
Interrupt Source Select for CCU2_CC18IC
0B
CCU2 channel 18 is used as interrupt source
1B
External interrupt request ERU_IOUT2 is used
ISS3
3
rw
Interrupt Source Select for CCU2_CC19IC
0B
CCU2 channel 19 is used as interrupt source
1B
External interrupt request ERU_IOUT3 is used
ISS4
4
rw
Interrupt Source Select for CCU2_CC20IC
0B
CCU2 channel 20 is used as interrupt source
1B
USIC0 Interrupt Request 6 is used
ISS5
5
rw
Interrupt Source Select for CCU2_CC21IC
0B
CCU2 channel 21 is used as interrupt source
1B
USIC0 Interrupt Request 7 is used
ISS6
6
rw
Interrupt Source Select for CCU2_CC22IC
CCU2 channel 22 is used as interrupt source
0B
1B
USIC1 Interrupt Request 6 is used
User’s Manual
SCU, V1.1
6-216
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
Field
Bits Type Description
ISS7
7
rw
Interrupt Source Select for CCU2_CC23IC
0B
CCU2 channel 23 is used as interrupt source
1B
USIC1 Interrupt Request 7 is used
ISS8
8
rw
Interrupt Source Select for CCU2_CC24IC
CCU2 channel 24 is used as interrupt source
0B
External interrupt request ERU_IOUT0 is used
1B
ISS9
9
rw
Interrupt Source Select for CCU2_CC25IC
0B
CCU2 channel 25 is used as interrupt source
1B
External interrupt request ERU_IOUT1 is used
ISS10
10
rw
Interrupt Source Select for CCU2_CC26IC
0B
CCU2 channel 26 is used as interrupt source
1B
External interrupt request ERU_IOUT2 is used
ISS11
11
rw
Interrupt Source Select for CCU2_CC27IC
0B
CCU2 channel 27 is used as interrupt source
1B
External interrupt request ERU_IOUT3 is used
ISS12
12
rw
Interrupt Source Select for CCU2_CC28IC
0B
CCU2 channel 28 is used as interrupt source
1B
USIC2 Interrupt Request 6 is used
ISS13
13
rw
Interrupt Source Select for CCU2_CC29IC
0B
CCU2 channel 29 is used as interrupt source
USIC2 Interrupt Request 7 is used
1B
ISS14
14
rw
Interrupt Source Select for CCU2_CC30IC
0B
CCU2 channel 30 is used as interrupt source
1B
Select SCU Interrupt Request 0 (SCU_IRQ0)
ISS15
15
rw
Interrupt Source Select for CCU2_CC31IC
0B
CCU2 channel 31 is used as interrupt source
1B
Select SCU Interrupt Request 1(SCU_IRQ1)
User’s Manual
SCU, V1.1
6-217
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.12
System Control Unit (SCU)
Identification Block
For identification of the most important silicon parameters a set of identification registers
is defined that provide information on the chip manufacturer, the chip type and its
properties.
IDMANUF
Manufacturer Identif. Reg.
15
14
13
12
11
ESFR (F07EH/3FH)
10
9
8
7
6
Reset Value: 1820H
5
4
3
2
1
MANUF
MANSEC
r
r
0
Field
Bits
Type
Description
MANSEC
[4:0]
r
Section within Manufacturer
Indicates the department within Infineon.
00H Standard microcontroller
MANUF
[15:5]
r
Manufacturer
This is the JEDEC normalized manufacturer code.
0C1H Infineon Technologies AG
IDCHIP
Chip Identification Register
15
14
13
12
11
10
ESFR (F07CH/3EH)
9
8
7
6
Reset Value: XXXXH
5
4
3
CHIPID
Revision
rw
r
2
1
Field
Bits
Type
Description
Revision
[7:0]
r
Device Revision Code
Identifies the device step.
CHIPID
[15:8]
rw
Device Identification
Identifies the device name (reference via table).
User’s Manual
SCU, V1.1
6-218
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
System Control Unit (SCU)
IDMEM
Program Memory Identif. Reg. ESFR (F07AH/3DH)
15
14
13
12
11
10
9
8
7
Reset Value: 3XXXH
6
5
TYPE
SIZE
r
rw
4
3
2
1
Field
Bits
Type
Description
SIZE
[11:0]
rw
Size of on-chip Program Memory
The size of the implemented program memory in
terms of 4-Kbyte blocks,
i.e. memory size = <SIZE> × 4 Kbytes.
TYPE
[15:12] r
Type of on-chip Program Memory
Identifies the memory type on this silicon.
3H
Flash memory
IDPROG
Prog. Voltage Identif. Register ESFR (F078H/3CH)
15
14
13
12
11
0
10
9
8
7
6
Reset Value: 1313H
5
4
3
PROGVPP
PROGVDD
r
r
2
1
0
Field
Bits
Type
Description
PROGVDD
[7:0]
r
Programming VDD Voltage
The voltage of the standard power supply required to
program or erase (if applicable) the on-chip program
memory.
Formula: VDD = 20 × <PROGVDD> / 256 [V].
PROGVPP
[15:8]
r
Programming VPP Voltage
The voltage of the special programming power
supply (if existent) required to program or erase (if
applicable) the on-chip program memory.
Formula: VPP = 20 × <PROGVPP> / 256 [V]1).
1)
The XC2000 needs no special programming voltage and PROGVPP = PROGVDD.
User’s Manual
SCU, V1.1
6-219
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
6.13
System Control Unit (SCU)
SCU Register Addresses
The SCU registers are within the (E)SFR space of the XC2000. Therefore, their specified
addresses equal an offset from zero.
Table 6-22
Registers Address Space
Module
Base Address
End Address
SCU
00 0000H
00 FFFEH
Note
Kernel Register Overview
Table 6-23
Short Name
Register Overview of SCU
Register Long Name
WUOSCCON Wake-up OSC Control
Register
HPOSCCON
Offset
Addr.
Protection Reset
F1AEH Sec
High Precision Oscillator F1B4H
Configuration Register
Power
Domain
1)
Power-on
Reset
DMP_M
Sec
Power-on
Reset
DMP_M
Sec
Power-on
Reset
DMP_1
PLLOSCCON PLL Clock Control
Register
F1B6H
PLLSTAT
PLL Status Register
F1BCH -
Power-on
Reset
DMP_1
PLLCON0
PLL Configuration 0
Register
F1B8H
Sec
Power-on
Reset
DMP_1
PLLCON1
PLL Configuration 1
Register
F1BAH Sec
Power-on
Reset
DMP_1
PLLCON2
PLL Configuration 2
Register
F1BCH Sec
Power-on
Reset
DMP_1
PLLCON3
PLL Configuration 3
Register
F1BEH Sec
Power-on
Reset
DMP_1
SYSCON0
System Configuration 0
Register
FF4AH
Sec
Power-on
Reset
DMP_M
STATCLR0
Status Clear 0 Register
F0E0H
Sec
System
Reset
DMP_1
STATCLR1
Status Clear 1 Register
F0E2H
Sec
System
Reset
DMP_1
User’s Manual
SCU, V1.1
6-220
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 6-23
Short Name
System Control Unit (SCU)
Register Overview of SCU
Offset
Addr.
Protection Reset
RTCCLKCON RTC Clock Control
Register
FF4EH
Sec
System
Reset
DMP_1
EXTCON
External Clock Control
Register
FF5EH
Sec
System
Reset
DMP_1
WICR
Wake-up Interval Count
Register
F0B0H
Sec
Power-on
Reset
DMP_M
WUCR
Wake-up Control
Register
F1B0H
Sec
Power-on
Reset
DMP_M
RSTSTAT0
Reset Status 0 Register
F0B2H
-
Power-on
Reset
DMP_M
RSTSTAT1
Reset Status 1 Register
F0B4H
-
Power-on
Reset
DMP_M
RSTSTAT2
Reset Status 2 Register
F0B6H
-
Power-on
Reset
DMP_M
RSTCON0
Reset Configuration 0
Register
F0B8H
Sec
Power-on
Reset
DMP_M
RSTCON1
Reset Configuration 1
Register
F0BAH Sec
Power-on
Reset
DMP_M
RSTCNTCON Reset Counter
Configuration Register
F1B2H
Sec
Power-on
Reset
DMP_M
SWRSTCON
F0AEH Sec
Power-on
Reset
DMP_M
ESREXCON1 ESR 1 External Control
Register
FF32H
Sec
System
Reset
DMP_M
ESREXCON2 ESR 2 External Control
Register
FF34H
Sec
System
Reset
DMP_M
ESRCFG0
ESR 0 Configuration
Register
F100H
Sec
System
Reset
DMP_M
ESRCFG1
ESR 1 Configuration
Register
F102H
Sec
System
Reset
DMP_M
ESRCFG2
ESR 2 Configuration
Register
F104H
Sec
System
Reset
DMP_M
ESRDAT
ESR Data Register
F106H
Sec
System
Reset
DMP_M
User’s Manual
SCU, V1.1
Register Long Name
SW Reset Control
Register
6-221
Power
Domain
1)
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 6-23
Short Name
System Control Unit (SCU)
Register Overview of SCU
Register Long Name
Offset
Addr.
Protection Reset
Power
Domain
1)
SWDCON0
SWD Control 0 Register
F080H
Sec
Power-on
Reset
DMP_M
SWDCON1
SWD Control 1 Register
F082H
Sec
Power-on
Reset
DMP_M
PVCMCON0
PVC_M Control for Step
0 Register
F1E4H
Sec
Power-on
Reset
DMP_M
PVC1CON0
PVC_1 Control for Step 0 F014H
Register
Sec
Power-on
Reset
DMP_M
PVCMCONA
1
PVC_M Register for Step F1E6H
1 Sequence A
Sec
Power-on
Reset
DMP_M
PVCMCONA
2
PVC_M Register for Step F1E8H
2 Sequence A
Sec
Power-on
Reset
DMP_M
PVCMCONA
3
PVC_M Register for Step F1EAH Sec
3 Sequence A
Power-on
Reset
DMP_M
PVCMCONA
4
PVC_M Register for Step F1ECH Sec
4 Sequence A
Power-on
Reset
DMP_M
PVCMCONA
5
PVC_M Register for Step F1EEH Sec
5 Sequence A
Power-on
Reset
DMP_M
PVCMCONA
6
PVC_M Register for Step F1F0H
6 Sequence A
Sec
Power-on
Reset
DMP_M
PVC1CONA1 PVC_1 Register for Step F016H
1 Sequence A
Sec
Power-on
Reset
DMP_M
PVC1CONA2 PVC_1 Register for Step F018H
2 Sequence A
Sec
Power-on
Reset
DMP_M
PVC1CONA3 PVC_1 Register for Step F01AH
3 Sequence A
Sec
Power-on
Reset
DMP_M
PVC1CONA4 PVC_1 Register for Step F01CH
4 Sequence A
Sec
Power-on
Reset
DMP_M
PVC1CONA5 PVC_1 Register for Step F01EH
5 Sequence A
Sec
Power-on
Reset
DMP_M
PVC1CONA6 PVC_1 Register for Step F0F0H
6 Sequence A
Sec
Power-on
Reset
DMP_M
PVCMCONB
1
Sec
Power-on
Reset
DMP_M
User’s Manual
SCU, V1.1
PVC_M Register for Step F1F4H
1 Sequence B
6-222
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 6-23
Short Name
System Control Unit (SCU)
Register Overview of SCU
Register Long Name
Offset
Addr.
Protection Reset
Power
Domain
1)
PVCMCONB
2
PVC_M Register for Step F1F6H
2 Sequence B
Sec
Power-on
Reset
DMP_M
PVCMCONB
3
PVC_M Register for Step F1F8H
3 Sequence B
Sec
Power-on
Reset
DMP_M
PVCMCONB
4
PVC_M Register for Step F1FAH
4 Sequence B
Sec
Power-on
Reset
DMP_M
PVCMCONB
5
PVC_M Register for Step F1FCH Sec
5 Sequence B
Power-on
Reset
DMP_M
PVCMCONB
6
PVC_M Register for Step F1FEH
6 Sequence B
Sec
Power-on
Reset
DMP_M
PVC1CONB1 PVC_1 Register for Step F024H
1 Sequence B
Sec
Power-on
Reset
DMP_M
PVC1CONB2 PVC_1 Register for Step F026H
2 Sequence B
Sec
Power-on
Reset
DMP_M
PVC1CONB3 PVC_1 Register for Step F028H
3 Sequence B
Sec
Power-on
Reset
DMP_M
PVC1CONB4 PVC_1 Register for Step F02AH
4 Sequence B
Sec
Power-on
Reset
DMP_M
PVC1CONB5 PVC_1 Register for Step F02CH
5 Sequence B
Sec
Power-on
Reset
DMP_M
PVC1CONB6 PVC_1 Register for Step F02EH
6 Sequence B
Sec
Power-on
Reset
DMP_M
EVRMCON0
EVR_M Control 0
Register
F084H
Sec
Power-on
Reset
DMP_M
EVR1CON0
EVR_1 Control 0
Register
F088H
Sec
Power-on
Reset
DMP_M
EVRMCON1
EVR_M Control 1
Register
F086H
Sec
Power-on
Reset
DMP_M
EVRMSET10
V
EVR_M Setting for 1.0V
Register
F090H
Sec
Power-on
Reset
DMP_M
EVRMSET15
VLP
EVR_M Setting for 1.5V
LP Register
F094H
Sec
Power-on
Reset
DMP_M
EVRMSET15
VHP
EVR_M Setting for 1.5V
HP Register
F096H
Sec
Power-on
Reset
DMP_M
User’s Manual
SCU, V1.1
6-223
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 6-23
Short Name
System Control Unit (SCU)
Register Overview of SCU
Offset
Addr.
Protection Reset
EVR1SET10V EVR_1 Setting for 1.0V
Register
F098H
Sec
Power-on
Reset
DMP_M
EVR1SET15V EVR_1 Setting for 1.5V
LP
LP Register
F09CH
Sec
Power-on
Reset
DMP_M
EVR1SET15V EVR_1 Setting for 1.5V
HP
HP Register
F09EH
Sec
Power-on
Reset
DMP_M
SEQCON
Sequence Control
Register
FEE4H Sec
Power-on
Reset
DMP_M
STEP0
Step 0 Register
FEF2H
Sec
Power-on
Reset
DMP_M
SEQASTEP1
Sequence Step 1 for Set FEE6H Sec
A Register
Power-on
Reset
DMP_M
SEQASTEP2
Sequence Step 2 for Set FEE8H Sec
A Register
Power-on
Reset
DMP_M
SEQASTEP3
Sequence Step 3 for Set FEEAH Sec
A Register
Power-on
Reset
DMP_M
SEQASTEP4
Sequence Step 4 for Set FEECH Sec
A Register
Power-on
Reset
DMP_M
SEQASTEP5
Sequence Step 5 for Set FEEEH Sec
A Register
Power-on
Reset
DMP_M
SEQASTEP6
Sequence Step 6 for Set FEF0H
A Register
Sec
Power-on
Reset
DMP_M
SEQBSTEP1
Sequence Step 1 for Set FEF4H
B Register
Sec
Power-on
Reset
DMP_M
SEQBSTEP2
Sequence Step 2 for Set FEF6H
B Register
Sec
Power-on
Reset
DMP_M
SEQBSTEP3
Sequence Step 3 for Set FEF8H
B Register
Sec
Power-on
Reset
DMP_M
SEQBSTEP4
Sequence Step 4 for Set FEFAH Sec
B Register
Power-on
Reset
DMP_M
SEQBSTEP5
Sequence Step 5 for Set FEFCH Sec
B Register
Power-on
Reset
DMP_M
SEQBSTEP6
Sequence Step 6 for Set FEFEH Sec
B Register
Power-on
Reset
DMP_M
User’s Manual
SCU, V1.1
Register Long Name
6-224
Power
Domain
1)
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 6-23
Short Name
System Control Unit (SCU)
Register Overview of SCU
Register Long Name
Offset
Addr.
Protection Reset
1)
Power
Domain
GSCSWREQ
GSC SW Request
Register
FF14H
Sec
Application DMP_M
Reset
GSCEN
GSC Enable Register
FF16H
Sec
Application DMP_M
Reset
GSCSTAT
GSC Status Register
FF18H
-
Application DMP_M
Reset
EXISEL
External Interrupt Input
Select Register
F1A0H
Sec
Application DMP_1
Reset
EXICON0
External Interrupt Input
Trigger Control 0
Register
F030H
Sec
Application DMP_1
Reset
EXICON1
External Interrupt Input
Trigger Control 1
Register
F032H
Sec
Application DMP_1
Reset
EXICON2
External Interrupt Input
Trigger Control 2
Register
F034H
Sec
Application DMP_1
Reset
EXICON3
External Interrupt Input
Trigger Control 3
Register
F036H
Sec
Application DMP_1
Reset
EXOCON0
External Output Trigger
Control 0 Register
FE30H
Sec
Application DMP_1
Reset
EXOCON1
External Output Trigger
Control 1 Register
FE32H
Sec
Application DMP_1
Reset
EXOCON2
External Output Trigger
Control 2 Register
FE34H
Sec
Application DMP_1
Reset
EXOCON3
External Output Trigger
Control 3 Register
FE36H
Sec
Application DMP_1
Reset
INTSTAT
Interrupt Status Register
FF00H
-
Application DMP_1
Reset
INTCLR
Interrupt Clear Register
FE82H
Sec
Application DMP_1
Reset
INTSET
Interrupt Set Register
FE80H
Sec
Application DMP_1
Reset
User’s Manual
SCU, V1.1
6-225
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 6-23
Short Name
System Control Unit (SCU)
Register Overview of SCU
Register Long Name
Offset
Addr.
Protection Reset
1)
Power
Domain
INTDIS
Interrupt Disable
Register
FE84H
Sec
Application DMP_1
Reset
INTNP0
Interrupt Node Pointer 0
Register
FE86H
Sec
Application DMP_1
Reset
INTNP1
Interrupt Node Pointer 1
Register
FE88H
Sec
Application DMP_1
Reset
DMPMIT
DMP_M Interrupt and
Trap Trigger Register
FE96H
Sec
System
Reset
DMP_M
DMPMITCLR
DMP_M Interrupt and
Trap Clear Register
FE98H
Sec
System
Reset
DMP_M
ISSR
Interrupt Source Select
Register
FF2EH
Sec
Application DMP_1
Reset
TCCR
Temperature
Compensation Control
Register
F1ACH Sec
System
Reset
DMP_1
TCLR
Temperature
Compensation Level
Register
F0ACH Sec
System
Reset
DMP_1
WDTREL
WDT Reload Register
F0C8H
Sec
Application DMP_1
Reset
WDTCS
WDT Control and Status
Register
F0C6H
Sec
Application DMP_1
Reset
WDTTIM
WDT Timer Register
F0CAH Sec
Application DMP_1
Reset
TRAPSTAT
Trap Status Register
FF02H
System
Reset
DMP_1
TRAPCLR
Trap Clear Register
FE8EH Sec
System
Reset
DMP_1
TRAPSET
Trap Set Register
FE8CH Sec
System
Reset
DMP_1
TRAPDIS
Trap Disable Register
FE90H
Sec
System
Reset
DMP_1
TRAPNP
Trap Node Pointer
Register
FE92H
Sec
System
Reset
DMP_1
User’s Manual
SCU, V1.1
6-226
-
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 6-23
Short Name
System Control Unit (SCU)
Register Overview of SCU
Register Long Name
Offset
Addr.
Protection Reset
1)
Power
Domain
SLC
Security Level Command F0C0H
Register
-
Application DMP_1
Reset
SLS
Security Level Status
Register
F0C2H
-
Application DMP_1
Reset
SYSCON1
System Control 1
Register
FF4CH Sec
Application DMP_1
Reset
IDMANUF
Manufacturer
Identification Register
F07EH
-
System
Reset
DMP_1
IDCHIP
Chip Identification
Register
F07CH
-
System
Reset
DMP_1
IDMEM
Program Memory
Identification Register
F07AH
-
System
Reset
DMP_1
IDPROG
Programming Voltage
Identification Register
F078H
-
System
Reset
DMP_1
1)
Register write protection mechanism: “Sec” = register security mechanism, “St” = only accessible in startup
mode, “-” = always accessible (no protection), otherwise no access is possible.
User’s Manual
SCU, V1.1
6-227
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
User’s Manual
SCU, V1.1
System Control Unit (SCU)
6-228
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7
Parallel Ports
Parallel Ports
The XC2000 provides a set of General Purpose Input/Output (GPIO) ports that can be
controlled by the software and by the on-chip peripheral units. They are:
Table 7-1
Ports of the XC2000
Group
Width
I/O
Connected Modules
P0
8
I/O
EBC (A7...A0), CCU6, USIC, CAN
P1
8
I/O
EBC (A15...A8), CCU6
P2
13
I/O
EBC (READY, BHE, A23...A16, AD15...AD13, D15...D13),
CAN, CCU2, GPT12E, USIC, JTAG
P3
8
I/O
EBC arbitration (BREQ, HLDA, HOLD), CAN, USIC
P4
8
I/O
EBC (CS4...CS0), CCU2, CAN, GPT12E
P5
16
I
Analog Inputs, CCU6, JTAG, GPT12E, CAN
P6
4
I/O
ADC, GPT12E
P7
5
I/O
P7.0 J-LINK, CAN, GPT12E, SCU, JTAG, CCU6, ADC
P8
7
I/O
CCU6, JTAG
P9
8
I/O
CCU6, JTAG, CAN
P10
16
I/O
EBC(ALE, RD, WR, AD12...AD0, D12...D0), CCU6, USIC,
JTAG, CAN
P11
6
I/O
CCU6
P15
8
I
Analog Inputs, GPT12E, CCU6
Note: The availability of ports and port pins depends on the selected device type.
This chapter describes the maximum set of ports.
All registers are implemented up to the next full nibble. That means that P2 is
implemented as 16 bit port, P6 is 4 bit, P7, P8, P11 are 8 bit ports. The padding bits at
the end and inside the registers are standard read write bits, that can be used as storage
elements, but without functionality behind them.
The IOCR registers related to these bits are also implemented, but without functionality
behind them.
User’s Manual
Parallel Ports, V1.6D4
7-1
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.1
Parallel Ports
General Description
This chapter describes the architecture of the digital control circuit for a single port pin.
7.1.1
Basic Port Operation
There are three types of digital control circuits: with/without hardware override for digital
GPIOs, and for one for analog inputs. Each port pin contains one of them.
POCON.PPS
PWS
A
N
D
SCU_PERCFG.PGRx
Pn_OUT
Pn_IN
control
4
2
2
2
OD, DIR
ALTSEL0,1
Pn_OMR
pull
devices
1
1
FF
ALTIN
Alternate Data signals or other control
lines from Peripherals or SCU
control
4
ENABQ
Access to port registers
by PD Bus
Pn_IOCR
O
R
X
O
R
0
1
Input
stage
INV
ALT1
1
ALT2
1
ALT3
1
DQ1
ENDQ1
TC[1:0]
PD[2:0]
output
stage
pad
pin
1
1
2
3
Standard_port_structure_4.vsd
Figure 7-1
Structure of the Ports without Hardware Override Functionality
Note: INV signal is derived from Pn_IOCR.PC[3:2].
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Preliminary
Parallel Ports
POCON.PPS
PWS
A
N
D
O
R
SCU_PERCFG.PGRx
HW_DIR
Alternate Data signals or other
control lines from Peripherals
3
Pn_IN
1
1
FF
ALTIN
X
O
R
control
4
2 2
2
ALTSEL0,1
Pn_OMR
Pn_OUT
control
pull
devices
OD, DIR
4
ENABQ
Access to port registers
by PD Bus
Pn_IOCR
0
1
2
input
stage
HW_EN
msb
INV*
ALT1
1
ALT2
1
ALT3
1
HW_OUT
DQ1
ENDQ1
TC[1:0]
PD[2:0]
output
stage
pad
pin
1
1
1
2
3
Standard_EBCport_structure_5.vsd
Figure 7-2
Structure of the Ports with Hardware Override Functionality
Note: If HW_EN is activated, INV* signal is always zero.
Note: When HW_EN is disabled, the respective ports go to Power Save Mode as all
other ports. When HW_EN is active, then the user should set the
POCON.PPSx=0.
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7-3
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Access to port registers
by PD Bus
Preliminary
Parallel Ports
ENABQ
Pn_DIDIS
Pn_IN
Input
stage
Analog Input
pad
pin
Analog_port_digital_structure_2.vsd
Figure 7-3
Structure of Port 5 and Port 15
Note: There is always a standard digital input connected in parallel to each analog input.
User’s Manual
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7-4
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.1.2
Parallel Ports
Input Stage Control
An input stage consists of a Schmitt trigger, which can be enabled or disabled via
software, and an input multiplexer that by default selects the output of the input
Schmitt trigger.
A disabled input driver drives high logical level. During and after reset, all input stages
are enabled by default.
7.1.3
Output Driver Control
An output stage consists of an output driver, output multiplexer, and register bit fields for
their control.
7.1.3.1
Active Mode Behavior
Each output driver can be configured in a push-pull or an open-drain mode, or it can be
deactivated (three-stated). An output multiplexer in front of the output driver selects the
signal source, choosing either the appropriate bit of the Pn_OUT register, or one of
maximum three lines coming from a peripheral unit, see Figure 7-1. The selection is
done via the Pn_IOCR register. Software can set or clear the bit Pn_OUT.Px, which
drives the port pin in case it is selected by the output multiplexer.
An output driver with hardware override can select an additional output signal coming
from a peripheral. While the hardware override is activated, this signal has higher priority
than all other output signals and can not be deselected by the port. In this case, the
peripheral controls the direction of the pin.
7.1.3.2
Power Saving Mode Behavior
In Power Saving Mode (core and IO supply voltages available), the behavior of a pin
depends on the setting of the POCONx.PPSx bit. Basically, groups of four pins within a
port can be configured to react to Power Save Mode Request or to ignore it. In case a
pin group is configured to react to a Power Save Mode Request, each pin within a group
reacts according to its own configuration according to the Table 7-5.
7.1.3.3
Reset Behavior
During reset, all output stages of GPIO pins go to tri-state mode without any pull-up or
pull-down device.
7.1.3.4
Power-fail Behavior
When the core supply fails while the pad supply remains stable, the output stages go into
tri-state mode.
User’s Manual
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7-5
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.2
Parallel Ports
Pin Description
XC2000 contains multifunctional pins, grouped into ports. Each pin generally provides
connection to many modules. A pin can output one of up to three signals coming from
the peripherals. It can distribute in parallel its input signal to many peripherals. Optionally
a pin can be fully controlled by a peripheral, in case the peripheral is enabled (for
example EBC). These possibilities are listed in the “Port x Input/Output Functions” tables
further in this chapter. As an example see Table 7-7.
7.2.1
Description Scheme for the Port IO Functions
A general building block is used to describe each GPIO pin in the “Port x Input/Output
Functions” table. Each table consists of a number of such blocks, one block for each pin.
Table 7-2
Port x Input/Output Functions Building Block
Port I/O
Pin
Connected Signal(s)
From / to
Module
Register/Bit
Field
Px.y I
General-purpose input
Px_IN.Py
Px_IOCRy.PC 0XXXB
Signal(s)
module(s)
O
General-purpose output Px_OUT.Py
1X00B
ALT1 Signal
module
1X01B
ALT2 Signal
module
1X10B
ALT3 Signal
module
1X11B
module;
group En
HW_Out1)
HW_DIR HW_Out Signal
1)
•
•
•
Value
This row is optional.
HW_DIR:
The type Alternate Direction signal which is needed if HW_En is active:
– Out -always output
DIRx - the pins in one port having the same DIRx (x=0, 1, 2,...), are controlled as
a group by a dedicated HW_DIR signal.
SDIR- Single DIR- the pin is controlled by its own, dedicated, single HW_DIR
signal.
grouping indicates if the respective pin is controlled by hardware:
– ENx - the pins in one port having the same ENx (x=0, 1, 2,...), are controlled as a
group by a dedicated HW_EN signal.
– SEN - Single EN - the pin is controlled by its own, dedicated, single HW_EN signal
Digital port slices with HW_DIR defined are the ports described in Figure 7-2. Digital
port slices without HW_DIR are described in Figure 7-1.
User’s Manual
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XC2000 Derivatives
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Preliminary
7.3
Parallel Ports
Port Description
The bit positions in the port registers always start right-aligned. For example, a port
comprising only 8 pins only uses the bit positions [7:0] of the corresponding register. The
remaining bit positions are filled with 0 (r).
The pad driver mode registers may be different for each port. As a result, they are
described independently for each port in the corresponding chapter.
7.3.1
Port Register Description
7.3.1.1
Pad Driver Control
The pad structure used in this device offers the possibility to select the output driver
strength and the slew rate. These selections are independent from the output port
functionality, such as open-drain, push/pull or input only.
In order to minimize EMI problems, the driver strength can be adapted to the application
requirements by bit fields PDMx. The selection is done in groups of four pins.
The Port Output Control registers POCON provide the corresponding control bits. A
4-bit control field configures the driver strength and the edge shape. Word ports
consume four control nibbles each, byte ports consume two control nibbles each, where
each control nibble controls 4 pins of the respective port.
Note: P2_POCON register in the P11_MR contains an exception regarding the
additional strong output driver connected in parallel to the standard output driver
of the P2.8 pin. See port 2 section.
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Preliminary
Parallel Ports
Px_POCON (x=0-4)
Port x Output Control Register XSFR (E8A0H+2*x)
Px_POCON (x=6-11)
Port x Output Control Register XSFR (E8A0H+2*x)
15
14
13
12
11
10
9
8
7
Reset Value: 0000H
Reset Value: 0000H
6
5
4
3
2
1
PPS
3
PDM3
PPS
2
PDM2
PPS
1
PDM1
PPS
0
PDM0
rw
rwr
rw
rw
rw
rw
rw
rw
Field
Bit
Type Description
PDM0,
PDM1,
PDM2,
PDM3
[2:0],
[6:4],
[10:8],
[14:12]
rw
PPS0,
PPS1,
PPS2,
PPS3
3,
7,
11,
15
rw
Port Driver Mode x
Code Driver strength 1)
000 Strong driver
001 Strong driver
010 Strong driver
011 Weak driver
100 Medium driver
101 Medium driver
110 Medium driver
111 Weak driver
0
Edge Shape2)
Sharp edge mode
Medium edge mode
Soft edge mode
Pin Power Save
0
Pin behaves like in the Active Mode. Power
Save Management is ignored.
1
Behavior in the Power Save Mode described in
the Table 7-5.
1)
Defines the current the respective driver can deliver to the external circuitry.
2)
Defines the switching characteristics to the respective new output level. This also influences the peak currents
through the driver when producing an edge, i.e. when changing the output level.
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Preliminary
Parallel Ports
Mapping of the POCON Registers to Pins and Ports
The table below lists the defined POCON registers and the allocation of control bit fields
and port pins.
Table 7-3
Port Output Control Register Allocation
Controlled Pins (by POCONx.[y:z])1)
Control
Register
[15:12]
[11:8]
[7:4]
[3:0]
P0_POCON
---
---
P0.[7:4]
P0.[3:0]
8
P1_POCON
---
---
P1.[7:4]
P1.[3:0]
8
P2_POCON
CLOCKOUT P2.[11:8] +
driver at
P2.12
P2.8
P2.[7:4]
P2.[3:0]
13
P3_POCON
---
---
P3.[7:4]
P3.[3:0]
8
P4_POCON
---
---
P4.[7:4]
P4.[3:0]
8
P6_POCON
---
---
---
P6.[3:0]
4
P7_POCON
---
---
P7.4
P7.[3:0]
5
P8_POCON
---
---
P8.[6:4]
P8.[3:0]
7
P9_POCON
---
---
P9.[7:4]
P9.[3:0]
8
P10_POCON P10.[15:12]
P10.[11:8]
P10.[7:4]
P10.[3:0]
16
P11_POCON ---
---
P11.[5:4]
P11.[3:0]
6
1)
Port Length
x denotes the port number, while [y:z] represents the bit field range.
Note: When assigning functional signals to port pins, please consider the fact that the
driver strength is selected for pin groups. Assign functions with similar
requirements to pins within the same POCON control group.
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Preliminary
7.3.1.2
Parallel Ports
Port Output Register
The port output register defines the values of the output pins if the pin is used as GPIO
output.
Pn_OUT (n=0-4)
Port n Output Register
Pn_OUT (n=6-11)
Port n Output Register
15
14
6
5
4
3
2
1
0
P15 P14 P13 P12 P11 P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
10
Reset Value: 0000H
7
rwh
11
SFR (FFA2H+2*n)
8
rwh
12
Reset Value: 0000H
9
rwh
13
SFR (FFA2H+2*n)
rwh
Field
Bits
Type
Description
Px
(x = 0-15)
x
rwh
Port Output Bit x
This bit defines the level at the output pin of port Pn,
pin x if the output is selected as GPIO output.
0
The output level of Pn.x is 0.
1
The output level of Pn.x is 1.
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.1.3
Parallel Ports
Port Output Modification Register
The port output modification register contains the bits to individually set, clear, or toggle
the value of the port n output register.
P2_OMRH
Port 2 Output Modification Register HighXSFR (E9CAH)
P10_OMRH
Port 10 Output Modification Register HighXSFR (E9EAH)
Reset Value: 0000H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PC
15
PC
14
PC
13
PC
12
PC
11
PC
10
PC
9
PC
8
PS
15
PS
14
PS
13
PS
12
PS
11
PS
10
PS
9
PS
8
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Field
Bits
Type Description
PSx
(x = 8-15)
x-8
w
Port Set Bit x
Setting this bit sets or toggles the corresponding bit in
the port output register Pn_OUT (see Table 7-4).
On a read access, this bit returns 0.
PCx
(x = 8-15)
x
w
Port Clear Bit x
Setting this bit clears or toggles the corresponding bit
in the port output register Pn_OUT. (see Table 7-4).
On a read access, this bit returns 0.
Pn_OMRL (n=0-4)
Port n Output Modification Register LowXSFR (E9C0H+4*n)
Pn_OMRL (n=6-11)
Port n Output Modification Register LowXSFR (E9C0H+4*n)
Reset Value: 0000H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PC
7
PC
6
PC
5
PC
4
PC
3
PC
2
PC
1
PC
0
PS
7
PS
6
PS
5
PS
4
PS
3
PS
2
PS
1
PS
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Parallel Ports
Field
Bits
Type Description
PSx
(x = 0-7)
x
w
Port Set Bit x
Setting this bit sets or toggles the corresponding bit in
the port output register Pn_OUT (see Table 7-4).
On a read access, this bit returns 0.
PCx
(x = 0-7)
x+8
w
Port Clear Bit x
Setting this bit clears or toggles the corresponding bit
in the port output register Pn_OUT. (see Table 7-4).
On a read access, this bit returns 0.
Function of the PCx and PSx bit fields
Table 7-4
Function of the Bits PCx and PSx
PCx
PSx
Function
0 or no write access
0 or no write access
Bit Pn_OUT.Px is not changed.
0 or no write access
1
Bit Pn_OUT.Px is set.
1
0 or no write access
Bit Pn_OUT.Px is cleared.
1
1
Bit Pn_OUT.Px is toggled.
Note: If a bit position is not written (one out of two bytes not targeted by a byte write), the
corresponding value is considered as 0. Toggling a bit requires one 16-bit write.
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7-12
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XC2000 Derivatives
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Preliminary
7.3.1.4
Parallel Ports
Port Input Register
The port input register contains the values currently read at the input pins, also if a port
line is assigned as output.
Pn_IN (n=0-11)
Port n Input Register
P15_IN
Port 15 Input Register
15
14
13
12
11
10
P15 P14 P13 P12 P11 P10
rh
1)
rh
rh
rh
rh
rh
SFR (FF80H+2*n)
Reset Value: 0000H1)
SFR (FF9EH)
Reset Value: 0000H1)
9
8
7
6
5
4
3
2
1
0
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
rh
rh
rh
rh
rh
rh
rh
rh
rh
rh
Px bits for non implemented I/O lines are always read as 0.
Field
Bits
Type Description
Px
(x = 0-15)
x
rh
User’s Manual
Parallel Ports, V1.6D4
Port Input Bit x
This bit indicates the level at the input pin of port Pn,
pin x.
0
The input level of Pn.x is 0.
1
The input level of Pn.x is 1.
7-13
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Preliminary
7.3.1.5
Parallel Ports
Port Input/Output Control Registers
The port input/output control registers contain the bit fields to select the digital output and
input driver characteristics, such as pull-up/down devices, port direction (input/output),
open-drain and alternate output selections. The coding of the options is shown in
Table 7-5.
Depending on the port functionality not all of the input/output control registers may be
implemented. The structure with one control bit field for each port pin located in different
register offers the possibility to configure port pin functionality of a single pin without
accessing some other PCx in the same register by word-oriented writes.
P0_IOCRx (x=00-07)
Port 0 Input/Output Control Register x XSFR (E800H+2*x)
P1_IOCRx (x=00-07)
Port 1 Input/Output Control Register x XSFR (E820H+2*x)
P2_IOCRx (x=00-12)
Port 2 Input/Output Control Register x XSFR (E840H+2*x)
P3_IOCRx (x=00-07)
Port 3 Input/Output Control Register x XSFR (E860H+2*x)
P4_IOCRx (x=00-07)
Port 4 Input/Output Control Register x XSFR (E880H+2*x)
P6_IOCRx (x=00-03)
Port 6 Input/Output Control Register x XSFR (E8C0H+2*x)
P7_IOCRx (x=00-04)
Port 7 Input/Output Control Register x XSFR (E8E0H+2*x)
P8_IOCRx (x=00-06)
Port 8 Input/Output Control Register x XSFR (E900H+2*x)
P9_IOCRx (x=00-07)
Port 9 Input/Output Control Register x XSFR (E920H+2*x)
P10_IOCRx (x=00-15)
Port 10 Input/Output Control Register x XSFR (E940H+2*x)
P11_IOCRx (x=00-05)
Port 11 Input/Output Control Register x XSFR (E960H+2*x)
15
14
13
12
User’s Manual
Parallel Ports, V1.6D4
11
10
9
8
7
6
5
4
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
Reset Value: 0000H
3
2
1
0
PC
0
r
rw
r
7-14
0
V1.0, 2007-06
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Preliminary
Parallel Ports
Field
Bits
Type Description
PC
[7:4]
rw
Port Input/Output Control Bit
see Table 7-5
0
[3:0],
[15:8]
r
reserved
Coding of the PC bit field
The coding of the GPIO port behavior is done by the bit fields in the port control registers
Pn_IOCRx. There’s a control bit field PC for each port pin. The bit fields PC are located
in separate control registers in order to allow modifying a port pin (without influencing the
others) with simple move operations.
Note: When the pin direction is switched to output and the mode is test mode, the output
characteristic must be push-pull only.
Table 7-5
PC Coding
PC[3:0]
I/O
Selected Pull-up/down /
Selected Output Function
Behavior in Power Saving
Mode1)
0000B
Direct
Input
No pull device connected
Input value = Pn_OUT; no pull
0001B
Pull-down device connected Input value = 0; pull-down
0010B
Pull-up device connected
Input value = 1; pull-up
0011B
No pull device connected.
In this mode Pn_OUT
samples the pad input value
continuously.
Input value = Pn_OUT; Pn_OUT
always samples input value while
not in power save mode = freeze of
input value; no pull
0100B
0101B
Inverted No pull device connected
Input value = Pn_OUT; no pull
Input
Pull-down device connected Input value = 1; pull-down
0110B
Pull-up device connected
Input value = 0; pull-up
0111B
No pull device connected
In this mode Pn_OUT
samples the pad input value
continuously.
Input value = Pn_OUT; Pn_OUT
always samples input value while
not in power saving mode = freeze
of input value; no pull2)
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Preliminary
Table 7-5
Parallel Ports
PC Coding
PC[3:0]
I/O
Selected Pull-up/down /
Selected Output Function
Behavior in Power Saving
Mode1)
1000B
Output
(Direct
input)
Pushpull
General purpose Output
Output driver off.
Input Schmitt trigger off.
Pn_OUT delivered to the internal
logic; no pull
1001B
1010B
1011B
1100B
1101B
1110B
1111B
Output
(Direct
input)
Opendrain
Output function ALT1
Output function ALT2
Output function ALT3
General purpose Output
Output function ALT1
Output function ALT2
Output function ALT3
1)
In power saving mode, the input Schmitt trigger is always switched off. A defined input value is driven to the
internal circuitry instead of the level detected at the input pin.
2)
If the IOCR setting is “inverted input”, then an inverted signal Pn_OUT is driven internally. The Pn_OUT
register itself always contains the real, non-inverted input value of the pin. See Figure 7-1 and Figure 7-2.
User’s Manual
Parallel Ports, V1.6D4
7-16
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.1.6
Parallel Ports
Port Digital Input Disable Register
Ports 5 and 15 have, additionally to the analog input functionality, digital input
functionality too. In order to save switching of the internal Schmitt triggers of the digital
inputs, they can be disabled by means of Px_DIDIS Register. P5_DIDIS is a 16-bit
register, and P15_DIDIS is an 8-bit register.
P5_DIDIS
Port 5 Digital Input Disable RegisterSFR (FE8AH)
P15_DIDIS
Port 15 Digital Input Disable RegisterSFR (FE9EH)
15
14
13
12
11
10
P15 P14 P13 P12 P11 P10
rw
rw
rw
rw
rw
rw
Reset Value: 0000H
Reset Value: 0000H
9
8
7
6
5
4
3
2
1
0
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bit
Type
Description
Py
(y = 0-15)
y
rw
Port 5 Bit y Digital Input Control
0
Digital input stage (schmitt trigger) is
enabled.
1
Digital input stage (schmitt trigger) is
disabled, necessary if pin is used as
analog input.
User’s Manual
Parallel Ports, V1.6D4
7-17
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.2
Parallel Ports
Port 0
Port 0 is an 8-bit GPIO port.
7.3.2.1
Overview
The port registers of Port 0 are shown in Figure 7-4.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
Modification
Registers
P0_IOCR00
:
P0_IOCR07
P0_OMRL
Data
Registers
P0_OUT
P0_IN
P0_POCON
Port0_Regs.vsd
Figure 7-4
Port 0 Register Overview
Table 7-6
Port 0 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P0_OUT
Port 0 Output Register
FFA2H
0000H
P0_IN
Port 0 Input Register
FF80H
0000H
P0_OMRL
Port 0 Output Modification Register Low
E9C0H
0000H
P0_POCON
Port 0 Output Control Register
E8A0H
0000H
P0_IOCR00
Port 0 Input/Output Control Register 0
E800H
0000H
P0_IOCR01
Port 0 Input/Output Control Register 1
E802H
0000H
P0_IOCR02
Port 0 Input/Output Control Register 2
E804H
0000H
P0_IOCR03
Port 0 Input/Output Control Register 3
E806H
0000H
P0_IOCR04
Port 0 Input/Output Control Register 4
E808H
0000H
P0_IOCR05
Port 0 Input/Output Control Register 5
E80AH
0000H
P0_IOCR06
Port 0 Input/Output Control Register 6
E80CH
0000H
P0_IOCR07
Port 0 Input/Output Control Register 7
E80EH
0000H
User’s Manual
Parallel Ports, V1.6D4
7-18
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.2.2
Parallel Ports
Port 0 Functions
The following table describes the mapping between the pins of Port 0 and the related I/
O signals.
Table 7-7
Port 0 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field Value
P0.0
I
General-purpose input
P0_IN.P0
P0_IOCR00.PC
DX0A
U1C0
CC60INA
CCU61
General-purpose output
P0_OUT.P0
1X00B
DOUT
U1C0
1X01B
O
reserved
CC60
P0.1
1X10B
CCU61
1X11B
DIR1 A0
EBC; SEN
HW_Out
I
General-purpose input
P0_IN.P1
DX0B
U1C0
CC61INA
CCU61
DX1A
U1C0
General-purpose output
P0_OUT.P1
1X00B
DOUT
U1C0
1X01B
TXDC0
CAN0
1X10B
CC61
CCU61
1X11B
DIR1 A1
EBC; SEN
HW_Out
I
General-purpose input
P0_IN.P2
DX1B
U1C0
CC62INA
CCU61
General-purpose output
P0_OUT.P2
1X00B
SCLKOUT
U1C0
1X01B
TXDC0
CAN0
1X10B
CC62
CCU61
1X11B
EBC; SEN
HW_Out
O
P0.2
0XXXB
O
DIR1 A2
User’s Manual
Parallel Ports, V1.6D4
7-19
P0_IOCR01.PC
P0_IOCR02.PC
0XXXB
0XXXB
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-7
Parallel Ports
Port 0 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field Value
P0.3
I
General-purpose input
P0_IN.P3
P0_IOCR03.PC
DX2A
U1C0
RXDC0B
CAN0
General-purpose output
P0_OUT.P3
1X00B
SELO0
U1C0
1X01B
SELO1
U1C1
1X10B
COUT60
CCU61
1X11B
DIR1 A3
EBC; SEN
HW_Out
I
General-purpose input
P0_IN.P4
DX2A
U1C1
RXDC1B
CAN1
General-purpose output
P0_OUT.P4
1X00B
SELO0
U1C1
1X01B
SELO1
U1C0
1X10B
COUT61
CCU61
1X11B
DIR1 A4
EBC; SEN
HW_Out
I
General-purpose input
P0_IN.P5
DX1A
U1C1
DX1C
U1C0
General-purpose output
P0_OUT.P5
1X00B
SCLKOUT
U1C1
1X01B
SELO2
U1C0
1X10B
COUT62
CCU61
1X11B
EBC; SEN
HW_Out
O
P0.4
O
P0.5
O
DIR1 A5
User’s Manual
Parallel Ports, V1.6D4
7-20
P0_IOCR04.PC
P0_IOCR05.PC
0XXXB
0XXXB
0XXXB
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-7
Parallel Ports
Port 0 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field Value
P0.6
I
General-purpose input
P0_IN.P6
P0_IOCR06.PC
DX0A
U1C1
CTRAPA
CCU61
DX1B
U1C1
General-purpose output
P0_OUT.P6
1X00B
DOUT
U1C1
1X01B
TXDC1
CAN1
1X10B
COUT63
CCU61
1X11B
DIR1 A6
EBC; SEN
HW_Out
I
General-purpose input
P0_IN.P7
DX0B
U1C1
CTRAPB
CCU61
General-purpose output
P0_OUT.P7
1X00B
DOUT
U1C1
1X01B
SELO3
U1C0
1X10B
O
P0.7
O
reserved
DIR1 A7
User’s Manual
Parallel Ports, V1.6D4
P0_IOCR07.PC
0XXXB
0XXXB
1X11B
EBC; SEN
7-21
HW_Out
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.3
Parallel Ports
Port 1
Port 1 is an 8-bit GPIO port.
7.3.3.1
Overview
The port registers of Port 1 are shown in Figure 7-5.
Control
Registers
Modification
Registers
P1_IOCR00
:
P1_IOCR07
P1_OMRL
Data
Registers
P1_OUT
P1_IN
P1_POCON
Port1_Regs.vsd
Figure 7-5
Port 1 Register Overview
For this port, all pins can be read as GPIO, from the Port Input Register.
Table 7-8
Port 1 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P1_OUT
Port 1 Output Register
FFA4H
0000H
P1_IN
Port 1 Input Register
FF82H
0000H
P1_OMRL
Port 1 Output Modification Register Low
E9C4H
0000H
P1_POCON
Port 1 Output Control Register
E8A2H
0000H
P1_IOCR00
Port 1 Input/Output Control Register 0
E820H
0000H
P1_IOCR01
Port 1 Input/Output Control Register 1
E822H
0000H
P1_IOCR02
Port 1 Input/Output Control Register 2
E824H
0000H
P1_IOCR03
Port 1 Input/Output Control Register 3
E826H
0000H
P1_IOCR04
Port 1 Input/Output Control Register 4
E828H
0000H
P1_IOCR05
Port 1 Input/Output Control Register 5
E82AH
0000H
P1_IOCR06
Port 1 Input/Output Control Register 6
E82CH
0000H
P1_IOCR07
Port 1 Input/Output Control Register 7
E82EH
0000H
User’s Manual
Parallel Ports, V1.6D4
7-22
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.3.2
Parallel Ports
Port 1 Functions
The following table describes the mapping between the pins of Port 1 and the related I/
O signals.
Table 7-9
Port 1 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field Value
P1.0
I
General-purpose input
P1_IN.P0
P1_IOCR00.PC
ERU_0B0
SCU
CTRAPB
CCU62
O
General-purpose output P1_OUT.P0
1X00B
MCLKOUT
U1C0
1X01B
SELO4
U1C0
1X10B
reserved
P1.1
1X11B
DIR1 A8
EBC; SEN
I
General-purpose input
P1_IN.P1
ERU_1B0
SCU
DX0C
U2C1
O
0XXXB
HW_Out
P1_IOCR01.PC
0XXXB
General-purpose output P1_OUT.P1
1X00B
COUT62
CCU62
1X01B
SELO5
U1C0
1X10B
DOUT
U2C1
1X11B
EBC; SEN
HW_Out
DIR1 A9
User’s Manual
Parallel Ports, V1.6D4
7-23
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Parallel Ports
Table 7-9
Port 1 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field Value
P1.2
I
General-purpose input
P1_IN.P2
P1_IOCR02.PC
T12HRB
CCU61
ERU_2A0
SCU
CC62INA
CCU62
DX0D
U2C1
DX1C
U2C1
O
P1.3
General-purpose output P1_OUT.P2
1X00B
CC62
CCU62
1X01B
SELO6
U1C0
1X10B
SCLKOUT
U2C1
1X11B
DIR1 A10
EBC; SEN
HW_Out
I
General-purpose input
P1_IN.P3
T12HRB
CCU62
ERU_3A0
SCU
O
P1.4
0XXXB
P1_IOCR03.PC
0XXXB
General-purpose output P1_OUT.P3
1X00B
COUT63
CCU62
1X01B
SELO7
U1C0
1X10B
SELO4
U2C0
1X11B
DIR1 A11
EBC; SEN
HW_Out
I
General-purpose input
P1_IN.P4
DX2B
U2C0
O
P1_IOCR04.PC
0XXXB
General-purpose output P1_OUT.P4
1X00B
COUT61
CCU62
1X01B
SELO4
U1C1
1X10B
SELO5
U2C0
1X11B
EBC; SEN
HW_Out
DIR1 A12
User’s Manual
Parallel Ports, V1.6D4
7-24
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Parallel Ports
Table 7-9
Port 1 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field Value
P1.5
I
General-purpose input
P1_IN.P5
P1_IOCR05.PC
DX0C
U2C0
O
P1.6
General-purpose output P1_OUT.P5
1X00B
COUT60
CCU62
1X01B
SELO3
U1C1
1X10B
BRKOUT
OCDS
1X11B
DIR1 A13
EBC; SEN
HW_Out
I
General-purpose input
P1_IN.P6
DX0D
U2C0
CC61INA
CCU62
O
P1.7
0XXXB
P1_IOCR06.PC
0XXXB
General-purpose output P1_OUT.P6
1X00B
CC61
CCU62
1X01B
SELO2
U1C1
1X10B
DOUT
U2C0
1X11B
DIR1 A14
EBC; SEN
HW_Out
I
General-purpose input
P1_IN.P7
DX1C
U2C0
CC60INA
CCU62
O
P1_IOCR07.PC
0XXXB
General-purpose output P1_OUT.P7
1X00B
CC60
CCU62
1X01B
MCLKOUT
U1C1
1X10B
SCLKOUT
U2C0
1X11B
EBC; SEN
HW_Out
DIR1 A15
User’s Manual
Parallel Ports, V1.6D4
7-25
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.4
Parallel Ports
Port 2
Port 2 is an 13-bit GPIO port.
The CLKOUT pad P2.8
In order to drive high frequency clock signals, a strong driver is connected parallel to the
normal output driver of the pad P2.8. This strong driver shows the following behavior:
•
•
Only one fixed driver strength - strong driver sharp edge.
This means that the driver-strength settings of the standard port in the register
P2_POCON.PDM2 does not apply to this additional driver.
Does not have additional pull-ups and does not influence the standard behavior of
the pull devices of the standard output driver, but can be switched to input/output via
the P2_IOCR08 register
Mutually exclusive operation with the standard output driver
Which output is enabled and reacts to P2_IOCR08 settings at any moment is set by the
bit field P2_POCON.PDM3
The standard drivers of the pin group P2.8 to p2.12 is controlled by P2_POCON.PDM2
and PPS2 bitfields.
The pad is disabled during reset state, ENPS active state and by default after reset
7.3.4.1
Overview
The port registers of Port 2 are shown in Figure 7-6.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
P2_IOCR00
:
P2_IOCR12
Modification
Registers
Data
Registers
P2_OMRL
P2_OUT
P2_OMRH
P2_IN
P2_POCON
Port2_Regs.vsd
Figure 7-6
Port 2 Register Overview
User’s Manual
Parallel Ports, V1.6D4
7-26
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-10
Parallel Ports
Port 2 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P2_OUT
Port 2 Output Register
FFA6H
0000H
P2_IN
Port 2 Input Register
FF84H
0000H
P2_OMRL
Port 2 Output Modification Register Low
E9C8H
0000H
P2_OMRH
Port 2 Output Modification Register High
E9CAH
0000H
P2_POCON
Port 2 Output Control Register
E8A4H
0000H
P2_IOCR00
Port 2 Input/Output Control Register 0
E840H
0000H
P2_IOCR01
Port 2 Input/Output Control Register 1
E842H
0000H
P2_IOCR02
Port 2 Input/Output Control Register 2
E844H
0000H
P2_IOCR03
Port 2 Input/Output Control Register 3
E846H
0000H
P2_IOCR04
Port 2 Input/Output Control Register 4
E848H
0000H
P2_IOCR05
Port 2 Input/Output Control Register 5
E84AH
0000H
P2_IOCR06
Port 2 Input/Output Control Register 6
E84CH
0000H
P2_IOCR07
Port 2 Input/Output Control Register 7
E84EH
0000H
P2_IOCR08
Port 2 Input/Output Control Register 8
E850H
0000H
P2_IOCR09
Port 2 Input/Output Control Register 9
E852H
0000H
P2_IOCR10
Port 2 Input/Output Control Register 10
E854H
0000H
P2_IOCR11
Port 2 Input/Output Control Register 11
E856H
0000H
P2_IOCR12
Port 2 Input/Output Control Register 12
E858H
0000H
User’s Manual
Parallel Ports, V1.6D4
7-27
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.4.2
Parallel Ports
Port 2 Functions
The following table describes the mapping between the pins of Port 2 and the related I/
O signals.
Table 7-11
Port 2 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
Select
P2.0
I
General-purpose input
P2_IN.P0
P2_IOCR00.PC
0XXXB
D13
EBC
RxDC0C
CAN0
CC60INB
CCU63
O
General-purpose output P2_OUT.P0
1X00B
reserved
1X01B
CC60
CCU63
1X10B
reserved
P2.1
1X11B
DIR1 AD13
EBC; EN1
I
General-purpose input
P2_IN.P1
D14
EBC
ERU_0A0
SCU
CC61INB
CCU63
O
HW_Out
P2_IOCR01.PC
0XXXB
General-purpose output P2_OUT.P1
1X00B
TxDC0
CAN0
1X01B
CC61
CCU63
1X10B
reserved
DIR1 AD14
User’s Manual
Parallel Ports, V1.6D4
1X11B
EBC; EN1
7-28
HW_Out
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-11
Parallel Ports
Port 2 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
Select
P2.2
I
General-purpose input
P2_IN.P2
P2_IOCR02.PC
0XXXB
D15
EBC
ECTT1
CAN0 TTCAN
ERU_1A0
SCU
CC62INB
CCU63
O
General-purpose output P2_OUT.P2
1X00B
TxDC1
CAN1
1X01B
CC62
CCU63
1X10B
reserved
P2.3
DIR1 AD15
EBC; EN1
I
General-purpose input
P2_IN.P3
DX0E
U0C0
RXDC0A
CAN0
CC2_16
CAPCOM2
O
P2.4
1X11B
HW_Out
P2_IOCR03.PC
0XXXB
General-purpose output P2_OUT.P3
1X00B
DOUT
U0C0
1X01B
COUT63
CCU63
1X10B
CC2_16
CAPCOM2
1X11B
DIR2 A16
EBC; SEN
HW_Out
I
General-purpose input
P2_IN.P4
DX0F
U0C0
RXDC1A
CAN1
CC2_17
CAPCOM2
O
P2_IOCR04.PC
0XXXB
General-purpose output P2_OUT.P4
1X00B
reserved
1X01B
TXDC0
CAN0
1X10B
CC2_17
CAPCOM2
1X11B
EBC; SEN
HW_Out
DIR2 A17
User’s Manual
Parallel Ports, V1.6D4
7-29
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-11
Parallel Ports
Port 2 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
Select
P2.5
I
General-purpose input
P2_IN.P5
P2_IOCR05.PC
0XXXB
DX1D
U0C0
CC2_18
CAPCOM2
O
P2.6
General-purpose output P2_OUT.P5
1X00B
SCLKOUT
U0C0
1X01B
TXDC0
CAN0
1X10B
CC2_18
CAPCOM2
1X11B
DIR2 A18
EBC; SEN
HW_Out
I
General-purpose input
P2_IN.P6
DX2D
U0C0
CC2_19
CAPCOM2
RxDC0D
CAN0
O
P2.7
P2_IOCR06.PC
0XXXB
General-purpose output P2_OUT.P6
1X00B
SELO0
U0C0
1X01B
SELO1
U0C1
1X10B
CC2_19
CAPCOM2
1X11B
DIR2 A19
EBC; SEN
HW_Out
I
General-purpose input
P2_IN.P7
DX2C
U0C1
RxDC1C
CAN1
CC2_20
CAPCOM2
O
P2_IOCR07.PC
0XXXB
General-purpose output P2_OUT.P7
1X00B
SELO0
U0C1
1X01B
SELO1
U0C0
1X10B
CC2_20
CAPCOM2
1X11B
EBC; SEN
HW_Out
DIR2 A20
User’s Manual
Parallel Ports, V1.6D4
7-30
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-11
Parallel Ports
Port 2 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
Select
P2.8
I
General-purpose input
P2_IN.P8
P2_IOCR08.PC
0XXXB
DX1D
U0C1
CC2_21
CAPCOM2
O
P2.9
General-purpose output P2_OUT.P8
1X00B
SCLKOUT
U0C1
1X01B
FOUT
SCU
1X10B
CC2_21
CAPCOM2
1X11B
DIR2 A21
EBC; SEN
HW_Out
I
General-purpose input
P2_IN.P9
TCK_A
JTAG
CC2_22
CAPCOM2
O
O
0XXXB
General-purpose output P2_OUT.P9
1X00B
DOUT
U0C1
1X01B
TXDC1
CAN1
1X10B
CC2_22
CAPCOM2
1X11B
EBC; SEN
HW_Out
SDIR A22
P2.10 I
P2_IOCR09.PC
General-purpose input
P2_IN.P10
DX0E
U0C1
CC2_23
CAPCOM2
CAPIN
GPT12E
P2_IOCR10.PC
0XXXB
General-purpose output P2_OUT.P10
1X00B
DOUT
U0C1
1X01B
SELO3
U0C0
1X10B
CC2_23
CAPCOM2
1X11B
EBC; SEN
HW_Out
DIR2 A23
User’s Manual
Parallel Ports, V1.6D4
7-31
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-11
Port
Pin
I/O
P2.11 I
O
Parallel Ports
Port 2 Input/Output Functions (cont’d)
Connected Signal(s)
From / to
Module
Register/Bit
Field
Select
General-purpose input
P2_IN.P11
P2_IOCR11.PC
0XXXB
General-purpose output P2_OUT.P11
1X00B
SELO2
U0C0
1X01B
SELO2
U0C1
1X10B
reserved
SDIR BHE
P2.12 I
O
1X11B
EBC; SEN
General-purpose input
P2_IN.P12
READY
EBC
HW_Out
P2_IOCR12.PC
0XXXB
General-purpose output P2_OUT.P12
1X00B
SELO4
U0C0
1X01B
SELO3
U0C1
1X10B
reserved
SDIR READY
User’s Manual
Parallel Ports, V1.6D4
1X11B
EBC; SEN
7-32
HW_Out
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.5
Parallel Ports
Port 3
Port 3 is an 8-bit GPIO port.
7.3.5.1
Overview
The port registers of Port 3 are shown in Figure 7-7.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
Modification
Registers
P3_IOCR00
:
P3_IOCR07
P3_OMRL
Data
Registers
P3_OUT
P3_IN
P3_POCON
Port3_Regs.vsd
Figure 7-7
Port 3 Register Overview
Table 7-12
Port 3 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P3_OUT
Port 3 Output Register
FFA8H
0000H
P3_IN
Port 3 Input Register
FF86H
0000H
P3_OMRL
Port 3 Output Modification Register Low
E9CCH
0000H
P3_POCON
Port 3 Output Control Register
E8A6H
0000H
P3_IOCR00
Port 3 Input/Output Control Register 0
E860H
0000H
P3_IOCR01
Port 3 Input/Output Control Register 1
E862H
0000H
P3_IOCR02
Port 3 Input/Output Control Register 2
E864H
0000H
P3_IOCR03
Port 3 Input/Output Control Register 3
E866H
0000H
P3_IOCR04
Port 3 Input/Output Control Register 4
E868H
0000H
P3_IOCR05
Port 3 Input/Output Control Register 5
E86AH
0000H
P3_IOCR06
Port 3 Input/Output Control Register 6
E86CH
0000H
P3_IOCR07
Port 3 Input/Output Control Register 7
E86EH
0000H
User’s Manual
Parallel Ports, V1.6D4
7-33
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.5.2
Parallel Ports
Port 3 Functions
The following table describes the mapping between the pins of Port 3 and the related I/
O signals.
Table 7-13
Port 3 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
Select
P3.0
I
General-purpose input
P3_IN.P0
P3_IOCR00.PC
0XXXB
DX0A
U2C0
RxDC3B
CAN3
DX1A
U2C0
General-purpose output
P3_OUT.P0
1X00B
DOUT
U2C0
1X01B
O
P3.1
reserved
1X10B
reserved
1X11B
SDIR
BREQ
EBC; EN3
I
General-purpose input
P3_IN.P1
DX0B
U2C0
HLDA
EBC
General-purpose output
P3_OUT.P1
1X00B
DOUT
U2C0
1X01B
TXDC3
CAN3
1X10B
O
HW_Out
P3_IOCR01.PC
reserved
P3.2
0XXXB
1X11B
SDIR
HLDA
EBC; EN3
I
General-purpose input
P3_IN.P2
DX1B
U2C0
HOLD
EBC
General-purpose output
P3_OUT.P2
1X00B
SCLKOUT
U2C0
1X01B
TXDC3
CAN3
1X10B
O
reserved
User’s Manual
Parallel Ports, V1.6D4
HW_Out
P3_IOCR02.PC
0XXXB
1X11B
7-34
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-13
Parallel Ports
Port 3 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
Select
P3.3
I
General-purpose input
P3_IN.P3
P3_IOCR03.PC
0XXXB
DX2A
U2C0
RXDC3A
CAN3
General-purpose output
P3_OUT.P3
1X00B
SELO0
U2C0
1X01B
SELO1
U2C1
1X10B
O
reserved
P3.4
I
O
P3.5
I
O
P3.6
I
O
1X11B
General-purpose input
P3_IN.P4
DX2A
U2C1
RXDC4A
CAN4
General-purpose output
P3_OUT.P4
1X00B
SELO0
U2C1
1X01B
SELO1
U2C0
1X10B
SELO4
U0C0
1X11B
General-purpose input
P3_IN.P5
DX1A
U2C1
General-purpose output
P3_OUT.P5
1X00B
SCLKOUT
U2C1
1X01B
SELO2
U2C0
1X10B
SELO5
U0C0
1X11B
General-purpose input
P3_IN.P6
DX0A
U2C1
DX1B
U2C1
General-purpose output
P3_OUT.P6
1X00B
DOUT
U2C1
1X01B
TXDC4
CAN4
1X10B
SELO6
U0C0
1X11B
User’s Manual
Parallel Ports, V1.6D4
7-35
P3_IOCR04.PC
P3_IOCR05.PC
P3_IOCR06.PC
0XXXB
0XXXB
0XXXB
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-13
Parallel Ports
Port 3 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
Select
P3.7
I
General-purpose input
P3_IN.P7
P3_IOCR07.PC
0XXXB
DX0B
U2C1
General-purpose output
P3_OUT.P7
1X00B
DOUT
U2C1
1X01B
SELO3
U2C0
1X10B
SELO7
U0C0
1X11B
O
User’s Manual
Parallel Ports, V1.6D4
7-36
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.6
Parallel Ports
Port 4
Port 4 is an 8-bit GPIO port.
7.3.6.1
Overview
The port registers of Port 4 are shown in Figure 7-8.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
Modification
Registers
P4_IOCR00
:
P4_IOCR07
P4_OMRL
Data
Registers
P4_OUT
P4_IN
P4_POCON
Port4_Regs.vsd
Figure 7-8
Port 4 Register Overview
Table 7-14
Port 4 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P4_OUT
Port 4 Output Register
FFAAH
0000H
P4_IN
Port 4 Input Register
FF88H
0000H
P4_OMRL
Port 4 Output Modification Register Low
E9D0H
0000H
P4_POCON
Port 4 Output Control Register
E8A8H
0000H
P4_IOCR00
Port 4 Input/Output Control Register 0
E880H
0000H
P4_IOCR01
Port 4 Input/Output Control Register 1
E882H
0000H
P4_IOCR02
Port 4 Input/Output Control Register 2
E884H
0000H
P4_IOCR03
Port 4 Input/Output Control Register 3
E886H
0000H
P4_IOCR04
Port 4 Input/Output Control Register 4
E888H
0000H
P4_IOCR05
Port 4 Input/Output Control Register 5
E88AH
0000H
P4_IOCR06
Port 4 Input/Output Control Register 6
E88CH
0000H
P4_IOCR07
Port 4 Input/Output Control Register 7
E88EH
0000H
User’s Manual
Parallel Ports, V1.6D4
7-37
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.6.2
Parallel Ports
Port 4 Functions
The following table describes the mapping between the pins of Port 4 and the related I/
O signals.
Table 7-15
Port 4 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P4.0
I
General-purpose input
P4_IN.P0
P4_IOCR00.PC 0XXXB
CC2_24
CAPCOM2
General-purpose output
P4_OUT.P0
O
P4.1
1X00B
reserved
1X01B
reserved
1X10B
CC2_24
CAPCOM2
1X11B
DIR3
CS0
EBC; SEN
HW_Out
I
General-purpose input
P4_IN.P1
CC2_25
CAPCOM2
General-purpose output
P4_OUT.P1
O
reserved
P4.2
Select
P4_IOCR01.PC 0XXXB
1X00B
1X01B
TXDC2
CAN2
1X10B
CC2_25
CAPCOM2
1X11B
DIR3
CS1
EBC; SEN
HW_Out
I
General-purpose input
P4_IN.P2
CC2_26
CAPCOM2
T2IN
GPT12E
General-purpose output
P4_OUT.P2
O
reserved
DIR3
P4_IOCR02.PC 0XXXB
1X00B
1X01B
TXDC2
CAN2
1X10B
CC2_26
CAPCOM2
1X11B
CS2
EBC; SEN
HW_Out
User’s Manual
Parallel Ports, V1.6D4
7-38
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-15
Parallel Ports
Port 4 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P4.3
I
General-purpose input
P4_IN.P3
P4_IOCR03.PC 0XXXB
RXDC2A
CAN2
CC2_27
CAPCOM2
T2EUD
GPT12E
General-purpose output
P4_OUT.P3
O
P4.4
1X00B
reserved
1X01B
reserved
1X10B
CC2_27
CAPCOM2
1X11B
DIR3
CS3
EBC; SEN
HW_Out
I
General-purpose input
P4_IN.P4
CC2_28
CAPCOM2
COUNT
RTC
General-purpose output
P4_OUT.P4
O
P4.5
Select
P4_IOCR04.PC 0XXXB
1X00B
reserved
1X01B
reserved
1X10B
CC2_28
CAPCOM2
1X11B
DIR3
CS4
EBC; SEN
HW_Out
I
General-purpose input
P4_IN.P5
CC2_29
CAPCOM2
General-purpose output
P4_OUT.P5
O
P4_IOCR05.PC 0XXXB
1X00B
reserved
1X01B
reserved
1X10B
CC2_29
User’s Manual
Parallel Ports, V1.6D4
CAPCOM2
7-39
1X11B
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-15
Parallel Ports
Port 4 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P4.6
I
General-purpose input
P4_IN.P6
P4_IOCR06.PC 0XXXB
CC2_30
CAPCOM2
T4IN
GPT12E
General-purpose output
P4_OUT.P6
O
P4.7
I
O
Select
1X00B
reserved
1X01B
reserved
1X10B
CC2_30
CAPCOM2
General-purpose input
P4_IN.P7
CC2_31
CAPCOM2
T4EUD
GPT12E
General-purpose output
P4_OUT.P7
1X11B
P4_IOCR07.PC 0XXXB
1X00B
reserved
1X01B
reserved
1X10B
CC2_31
User’s Manual
Parallel Ports, V1.6D4
CAPCOM2
7-40
1X11B
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.7
Parallel Ports
Port 5
Port 5 is an 16-bit analog or digital input port.
To use the Port 5 as an analog input, the Schmitt trigger in the input stage must be
disabled. This is achieved by setting the corresponding bit in the register P5_DIDIS.
Data
Registers
Control
Registers
P5_DIDIS
P5_OUT
P5_IN
Port5_Regs.vsd
Figure 7-9
Port 5 Register Overview
Table 7-16
Port 5 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P5_IN
Port 5 Input Register
FF8AH
0000H
P5_DIDIS
Port 5 Digital Input Disable Register
FE8AH
0000H
User’s Manual
Parallel Ports, V1.6D4
7-41
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.7.1
Parallel Ports
Port 5 Functions
The following table describes the mapping between the pins of Port 5 and the related I/
O signals.
Table 7-17
Port 5 Input/Output Functions
Port
Pin
I/O
P5.0
I
P5.1
I
P5.2
I
TDI_A
JTAG
P5.3
I
T3IN
GPT12E
P5.4
I
T12HRB
CCU63
T3EUD
GPT12E
TMS_A
JTAG
T12HRB
CCU60
T12HRC
CCU60
T13HRC
CCU60
T12HRC
CCU61
T13HRC
CCU61
T12HRC
CCU62
T13HRC
CCU62
T12HRC
CCU63
T13HRC
CCU63
P5.5
I
P5.6
I
P5.7
I
P5.8
I
Select Connected Signal(s)
From / to Module
P5.9
I
CC2_T7IN
CAPCOM2
P5.10
I
BRKIN_A
JTAG
P5.11
I
P5.12
I
P5.13
I
ERU_0B1
SCU
P5.14
I
P5.15
I
ECTT3
CAN0 TTCAN
User’s Manual
Parallel Ports, V1.6D4
7-42
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.8
Parallel Ports
Port 6
Port 6 is an 4-bit GPIO port.
7.3.8.1
Overview
The port registers of Port 6 are shown in Figure 7-10.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
Modification
Registers
P6_IOCR00
:
P6_IOCR03
P6_OMRL
Data
Registers
P6_OUT
P6_IN
P6_POCON
Port6_Regs.vsd
Figure 7-10 Port 6 Register Overview
Table 7-18
Port 6 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P6_OUT
Port 6 Output Register
FFAEH
0000H
P6_IN
Port 6 Input Register
FF8CH
0000H
P6_OMRL
Port 6 Output Modification Register Low
E9D8H
0000H
P6_POCON
Port 6 Output Control Register
E8ACH
0000H
P6_IOCR00
Port 6 Input/Output Control Register 0
E8C0H
0000H
P6_IOCR01
Port 6 Input/Output Control Register 1
E8C2H
0000H
P6_IOCR02
Port 6 Input/Output Control Register 2
E8C4H
0000H
P6_IOCR03
Port 6 Input/Output Control Register 4
E8C6H
0000H
User’s Manual
Parallel Ports, V1.6D4
7-43
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.8.2
Parallel Ports
Port 6 Functions
The following table describes the mapping between the pins of Port 6 and the related I/
O signals.
Table 7-19
Port 6 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field Select
P6.0
I
General-purpose input
P6_IN.P0
P6_IOCR00.PC
REQGT0C
ADC0
REQGT1C
ADC0
REQGT2C
ADC0
REQGT0C
ADC1
REQGT1C
ADC1
REQGT2C
ADC1
DX0E
U1C1
General-purpose output
P6_OUT.P0
1X00B
EMUX0
ADC0
1X01B
DOUT
U1C1
1X10B
BRKOUT
P6_OUT.P
1X11B
General-purpose input
P6_IN.P1
REQTR0C
ADC0
REQTR1C
ADC0
REQTR2C
ADC0
REQTR0C
ADC1
REQTR1C
ADC1
REQTR2C
ADC1
General-purpose output
P6_OUT.P1
1X00B
EMUX1
ADC0
1X01B
T3OUT
GPT12E
1X10B
DOUT
U1C1
1X11B
O
P6.1
I
O
User’s Manual
Parallel Ports, V1.6D4
7-44
P6_IOCR01.PC
0XXXB
0XXXB
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Parallel Ports
Table 7-19
Port 6 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field Select
P6.2
I
General-purpose input
P6_IN.P2
P6_IOCR02.PC
DX1C
U1C1
General-purpose output
P6_OUT.P2
1X00B
EMUX2
ADC0
1X01B
T6OUT
GPT12E
1X10B
SCLK
U1C1
1X11B
General-purpose input
P6_IN.P3
DX2D
U1C1
REQTR0D
ADC0
REQTR1D
ADC0
REQTR2D
ADC0
REQTR0D
ADC1
REQTR1D
ADC1
REQTR2D
ADC1
General-purpose output
P6_OUT.P3
O
P6.3
I
O
reserved
P6_IOCR03.PC
0XXXB
0XXXB
1X00B
1X01B
T3OUT
GPT12E
1X10B
SEL0
U1C1
1X11B
User’s Manual
Parallel Ports, V1.6D4
7-45
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.9
Parallel Ports
Port 7
Port 7 is a 5-bit GPIO port.
7.3.9.1
Overview
The port registers of Port 7 are shown in Figure 7-11.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
Modification
Registers
P7_IOCR00
:
P7_IOCR04
P7_OMRL
Data
Registers
P7_OUT
P7_IN
P7_POCON
Port7_Regs.vsd
Figure 7-11 Port 7 Register Overview
Table 7-20
Port 7 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P7_OUT
Port 7 Output Register
FFB0H
0000H
P7_IN
Port 7 Input Register
FF8EH
0000H
P7_OMRL
Port 7 Output Modification Register Low
E9DCH
0000H
P7_POCON
Port 7 Output Control Register
E8AEH
0000H
P7_IOCR00
Port 7 Input/Output Control Register 0
E8E0H
0000H
P7_IOCR01
Port 7 Input/Output Control Register 1
E8E2H
0000H
P7_IOCR02
Port 7 Input/Output Control Register 2
E8E4H
0000H
P7_IOCR03
Port 7 Input/Output Control Register 3
E8E6H
0000H
P7_IOCR04
Port 7 Input/Output Control Register 4
E8E8H
0000H
User’s Manual
Parallel Ports, V1.6D4
7-46
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.9.2
Parallel Ports
Port 7 Functions
The following table describes the mapping between the pins of Port 7 and the related I/
O signals.
Table 7-21
Port 7 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P7.0
I
General-purpose input
P7_IN.P0
P7_IOCR00.PC 0XXXB
RXDC4B
CAN4
General-purpose output
P7_OUT.P0
1X00B
T3OUT
GPT12E
1X01B
T6OUT
GPT12E
1X10B
O
reserved
P7.1
1X11B
SDIR TDO
JTAG SEN
I
General-purpose input
P7_IN.P1
CTRAPA
CCU62
BRKIN_C
JTAG
General-purpose output
P7_OUT.P1
1X00B
FOUT
SCU
1X01B
TXDC4
CAN4
1X10B
O
reserved
P7.2
Select
I
O
HW_O
ut
P7_IOCR01.PC 0XXXB
1X11B
General-purpose input
P7_IN.P2
CCPOS0A
CCU62
TDI_C
JTAG
General-purpose output
P7_OUT.P2
1X00B
EMUX0
ADC1
1X01B
TXDC4
CAN4
1X10B
reserved
User’s Manual
Parallel Ports, V1.6D4
P7_IOCR02.PC 0XXXB
1X11B
7-47
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-21
Parallel Ports
Port 7 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P7.3
I
General-purpose input
P7_IN.P3
P7_IOCR03.PC 0XXXB
CCPOS1A
CCU62
TMS_C
JTAG
DX0F
U0C1
General-purpose output
P7_OUT.P3
1X00B
EMUX1
ADC1
1X01B
DOUT
U0C1
1X10B
DOUT
U0C0
1X11B
General-purpose input
P7_IN.P4
CCPOS2A
CCU62
TCK_C
JTAG
DX0D
U0C0
DX1E
U0C1
General-purpose output
P7_IN.P4
1X00B
EMUX2
ADC1
1X01B
DOUT
U0C1
1X10B
SCLK
U0C1
1X11B
O
P7.4
I
O
User’s Manual
Parallel Ports, V1.6D4
7-48
Select
P7_IOCR04.PC 0XXXB
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.10
Parallel Ports
Port 8
Port 8 is an 7-bit GPIO port.
7.3.10.1 Overview
The port registers of Port 8 are shown in Figure 7-12.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
Modification
Registers
P8_IOCR00
:
P8_IOCR06
P8_OMRL
Data
Registers
P8_OUT
P8_IN
P8_POCON
Port8_Regs.vsd
Figure 7-12 Port 8 Register Overview
Table 7-22
Port 8 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P8_OUT
Port 8 Output Register
FFB2H
0000H
P8_IN
Port 8 Input Register
FF90H
0000H
P8_OMRL
Port 8 Output Modification Register Low
E9E0H
0000H
P8_POCON
Port 8 Output Control Register
E8B0H
0000H
P8_IOCR00
Port 8 Input/Output Control Register 0
E900H
0000H
P8_IOCR01
Port 8 Input/Output Control Register 1
E902H
0000H
P8_IOCR02
Port 8 Input/Output Control Register 2
E904H
0000H
P8_IOCR03
Port 8 Input/Output Control Register 3
E906H
0000H
P8_IOCR04
Port 8 Input/Output Control Register 4
E908H
0000H
P8_IOCR05
Port 8 Input/Output Control Register 5
E90AH
0000H
P8_IOCR06
Port 8 Input/Output Control Register 6
E90CH
0000H
User’s Manual
Parallel Ports, V1.6D4
7-49
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Parallel Ports
7.3.10.2 Port 8 Functions
The following table describes the mapping between the pins of Port 8 and the related I/
O signals.
Table 7-23
Port 8 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P8.0
I
General-purpose input
P8_IN.P0
P8_IOCR00.PC 0XXXB
CC60INB
CCU60
General-purpose output
P8_OUT.P0
1X00B
CC60
CCU60
1X01B
O
P8.1
I
O
P8.2
I
O
P8.3
I
O
Select
reserved
1X10B
reserved
1X11B
General-purpose input
P8_IN.P1
P8_IOCR01.PC 0XXXB
CC61INB
CCU60
General-purpose output
P8_OUT.P1
1X00B
CC61
CCU60
1X01B
reserved
1X10B
reserved
1X11B
General-purpose input
P8_IN.P2
P8_IOCR02.PC 0XXXB
CC62INB
CCU60
General-purpose output
P8_OUT.P2
1X00B
CC62
CCU60
1X01B
reserved
1X10B
reserved
1X11B
General-purpose input
P8_IN.P3
P8_IOCR03.PC 0XXXB
TDI_D
JTAG
General-purpose output
P8_OUT.P3
1X00B
COUT60
CCU60
1X01B
reserved
1X10B
reserved
1X11B
User’s Manual
Parallel Ports, V1.6D4
7-50
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-23
Parallel Ports
Port 8 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P8.4
I
General-purpose input
P8_IN.P4
P8_IOCR04.PC 0XXXB
TMS_D
JTAG
General-purpose output
P8_OUT.P4
1X00B
COUT61
CCU60
1X01B
O
P8.5
I
O
P8.6
I
O
Select
reserved
1X10B
reserved
1X11B
General-purpose input
P8_IN.P5
P8_IOCR05.PC 0XXXB
TCK_D
JTAG
General-purpose output
P8_OUT.P5
1X00B
COUT62
CCU60
1X01B
reserved
1X10B
reserved
1X11B
General-purpose input
P8_IN.P6
P8_IOCR06.PC 0XXXB
CTRAPB
CCU60
BRKIN_D
JTAG
General-purpose output
P8_OUT.P6
1X00B
COUT63
CCU60
1X01B
reserved
1X10B
reserved
1X11B
User’s Manual
Parallel Ports, V1.6D4
7-51
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.11
Parallel Ports
Port 9
Port 9 is an 8-bit GPIO port.
7.3.11.1 Overview
The port registers of Port 9 are shown in Figure 7-13.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
Modification
Registers
P9_IOCR00
:
P9_IOCR07
P9_OMRL
Data
Registers
P9_OUT
P9_IN
P9_POCON
Port9_Regs.vsd
Figure 7-13 Port 9 Register Overview
Table 7-24
Port 9 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P9_OUT
Port 9 Output Register
FFB4H
0000H
P9_IN
Port 9 Input Register
FF92H
0000H
P9_OMRL
Port 9 Output Modification Register Low
E9E4H
0000H
P9_POCON
Port 9 Output Control Register
E8B2H
0000H
P9_IOCR00
Port 9 Input/Output Control Register 0
E920H
0000H
P9_IOCR01
Port 9 Input/Output Control Register 1
E922H
0000H
P9_IOCR02
Port 9 Input/Output Control Register 2
E924H
0000H
P9_IOCR03
Port 9 Input/Output Control Register 3
E926H
0000H
P9_IOCR04
Port 9 Input/Output Control Register 4
E928H
0000H
P9_IOCR05
Port 9 Input/Output Control Register 5
E92AH
0000H
P9_IOCR06
Port 9 Input/Output Control Register 6
E92CH
0000H
P9_IOCR07
Port 9 Input/Output Control Register 7
E92EH
0000H
User’s Manual
Parallel Ports, V1.6D4
7-52
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Parallel Ports
7.3.11.2 Port 9 Functions
The following table describes the mapping between the pins of Port 9 and the related I/
O signals.
Table 7-25
Port
Pin
I/O
P9.0 I
O
P9.1 I
O
P9.2 I
O
P9.3 I
O
Port 9 Input/Output Functions
Connected Signal(s)
From / to
Module
Register/Bit Field
Select
General-purpose input
P9_IN.P0
P9_IOCR00.PC
0XXXB
CC60INA
CCU63
General-purpose output
P9_OUT.P0
1X00B
CC60
CCU63
1X01B
reserved
1X10B
reserved
1X11B
General-purpose input
P9_IN.P1
P9_IOCR01.PC
0XXXB
CC61INA
CCU63
General-purpose output
P9_OUT.P1
1X00B
CC61
CCU63
1X01B
reserved
1X10B
reserved
1X11B
General-purpose input
P9_IN.P2
P9_IOCR02.PC
0XXXB
CC62INA
CCU63
General-purpose output
P9_OUT.P2
1X00B
CC62
CCU63
1X01B
reserved
1X10B
reserved
1X11B
General-purpose input
P9_IN.P3
General-purpose output
P9_OUT.P3
1X00B
COUT60
CCU63
1X01B
BRKOUT
JTAG
1X10B
reserved
User’s Manual
Parallel Ports, V1.6D4
P9_IOCR03.PC
0XXXB
1X11B
7-53
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-25
Port
Pin
I/O
P9.4 I
O
Parallel Ports
Port 9 Input/Output Functions (cont’d)
Connected Signal(s)
From / to
Module
Register/Bit Field
Select
General-purpose input
P9_IN.P4
P9_IOCR04.PC
0XXXB
General-purpose output
P9_OUT.P4
1X00B
COUT61
CCU63
1X01B
DOUT
U2C0
1X10B
reserved
P9.5 I
O
1X11B
General-purpose input
P9_IN.P5
P9_IOCR05.PC
DX0E
U2C0
CCPOS2B
CCU60
General-purpose output
P9_OUT.P5
1X00B
COUT62
CCU63
1X01B
DOUT
U2C0
1X10B
reserved
P9.6 I
O
1X11B
General-purpose input
P9_IN.P6
P9_IOCR06.PC
CTRAPA
CCU63
CCPOS1B
CCU60
General-purpose output
P9_OUT.P6
1X00B
COUT63
CCU63
1X01B
COUT62
CCU63
1X10B
reserved
P9.7 I
O
0XXXB
0XXXB
1X11B
General-purpose input
P9_IN.P7
ECTT2
CAN0 TTCAN
CTRAPB
CCU63
DX1D
U2C0
CCPOS0B
CCU60
General-purpose output
P9_OUT.P7
P9_IOCR07.PC
0XXXB
1X00B
reserved
1X01B
reserved
1X10B
reserved
1X11B
User’s Manual
Parallel Ports, V1.6D4
7-54
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.12
Parallel Ports
Port 10
Port 10 is a 16-bit GPIO port.
7.3.12.1 Overview
The port registers of Port 10 are shown in Figure 7-14.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
Modification
Registers
Data
Registers
P10_IOCR00
:
P10_IOCR15
P10_OMRL
P10_OUT
P10_OMRH
P10_IN
P10_POCON
Port10_Regs.vsd
Figure 7-14 Port 10 Register Overview
Table 7-26
Port 10 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P10_OUT
Port 10 Output Register
FFB6H
0000H
P10_IN
Port 10 Input Register
FF94H
0000H
P10_OMRL
Port 10 Output Modification Register Low
E9E8H
0000H
P10_OMRH
Port 10 Output Modification Register High
E9EAH
0000H
P10_POCON Port 10 Output Control Register
E8B4H
0000H
P10_IOCR00 Port 10 Input/Output Control Register 0
E940H
0000H
P10_IOCR01 Port 10 Input/Output Control Register 1
E942H
0000H
P10_IOCR02 Port 10 Input/Output Control Register 2
E944H
0000H
P10_IOCR03 Port 10 Input/Output Control Register 3
E946H
0000H
P10_IOCR04 Port 10 Input/Output Control Register 4
E948H
0000H
P10_IOCR05 Port 10 Input/Output Control Register 5
E94AH
0000H
P10_IOCR06 Port 10 Input/Output Control Register 6
E94CH
0000H
User’s Manual
Parallel Ports, V1.6D4
7-55
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-26
Register
Short Name
Parallel Ports
Port 10 Registers (cont’d)
Register Long Name
Address
Offset
Reset
Value
P10_IOCR07 Port 10 Input/Output Control Register 7
E94EH
0000H
P10_IOCR08 Port 10 Input/Output Control Register 8
E950H
0000H
P10_IOCR09 Port 10 Input/Output Control Register 9
E952H
0000H
P10_IOCR10 Port 10 Input/Output Control Register 10
E954H
0000H
P10_IOCR11 Port 10 Input/Output Control Register 11
E956H
0000H
P10_IOCR12 Port 10 Input/Output Control Register 12
E958H
0000H
P10_IOCR13 Port 10 Input/Output Control Register 13
E95AH
0000H
P10_IOCR14 Port 10 Input/Output Control Register 14
E95CH
0000H
P10_IOCR15 Port 10 Input/Output Control Register 15
E95EH
0000H
7.3.12.2 Port 10 Functions
The following table describes the mapping between the pins of Port 10 and the related
I/O signals.
Table 7-27
Port 10 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P10.0
I
General-purpose input
P10_IN.P0
P10_IOCR00.PC 0XXXB
D0
EBC
CC60INA
CCU60
DX0A
U0C0
DX0A
U0C1
O
Select
General-purpose output P10_OUT.P0
1X00B
DOUT
U0C1
1X01B
CC60
CCU60
1X10B
reserved
DIR1 AD0
User’s Manual
Parallel Ports, V1.6D4
1X11B
EBC; EN1
7-56
HW_Out
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-27
Parallel Ports
Port 10 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P10.1
I
General-purpose input
P10_IN.P1
P10_IOCR01.PC 0XXXB
D1
EBC
CC61INA
CCU60
DX0B
U0C0
DX1A
U0C0
O
General-purpose output P10_OUT.P1
1X00B
DOUT
U0C0
1X01B
CC61
CCU60
1X10B
reserved
P10.2
1X11B
DIR1 AD1
EBC; EN1
I
General-purpose input
P10_IN.P2
D2
EBC
CC62INA
CCU60
DX1B
U0C0
O
P10_IOCR02.PC 0XXXB
1X00B
SCLKOUT
U0C0
1X01B
CC62
CCU60
1X10B
1X11B
DIR1 AD2
EBC; EN1
I
General-purpose input
P10_IN.P3
D3
EBC
DX2A
U0C0
DX2A
U0C1
O
HW_Out
General-purpose output P10_OUT.P2
reserved
P10.3
Select
HW_Out
P10_IOCR03.PC 0XXXB
General-purpose output P10_OUT.P3
1X00B
reserved
1X01B
COUT60
CCU60
reserved
DIR1 AD3
User’s Manual
Parallel Ports, V1.6D4
1X10B
1X11B
EBC; EN1
7-57
HW_Out
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-27
Parallel Ports
Port 10 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P10.4
I
General-purpose input
P10_IN.P4
P10_IOCR04.PC 0XXXB
D4
EBC
DX2B
U0C0
DX2B
U0C1
O
General-purpose output P10_OUT.P4
1X00B
SELO3
U0C0
1X01B
COUT61
CCU60
1X10B
reserved
P10.5
1X11B
DIR1 AD4
EBC; EN1
I
General-purpose input
P10_IN.P5
D5
EBC
DX1B
U0C1
O
P10_IOCR05.PC 0XXXB
1X00B
SCLKOUT
U0C1
1X01B
COUT62
CCU60
1X10B
1X11B
DIR1 AD5
EBC; EN1
I
General-purpose input
P10_IN.P6
D6
EBC
DX0C
U0C0
DX2D
U1C0
CTRAPA
CCU60
O
HW_Out
General-purpose output P10_OUT.P5
reserved
P10.6
Select
HW_Out
P10_IOCR06.PC 0XXXB
General-purpose output P10_OUT.P6
1X00B
DOUT
U0C0
1X01B
TXDC4
CAN4
1X10B
SELO0
U1C0
1X11B
EBC; EN1
HW_Out
DIR1 AD6
User’s Manual
Parallel Ports, V1.6D4
7-58
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-27
Parallel Ports
Port 10 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit
Field
P10.7
I
General-purpose input
P10_IN.P7
P10_IOCR07.PC 0XXXB
D7
EBC
DX0B
U0C1
CCPOS0A
CCU60
RXDC4C
CAN4
O
General-purpose output P10_OUT.P7
1X00B
DOUT
U0C1
1X01B
COUT63
CCU60
1X10B
reserved
P10.8
1X11B
DIR1 AD7
EBC; EN1
I
General-purpose input
P10_IN.P8
D8
EBC
CCPOS1A
CCU60
DX1C
U0C0
BRKIN_B
JTAG
O
P10_IOCR08.PC 0XXXB
1X00B
MCLKOUT
U0C0
1X01B
SELO0
U0C1
1X10B
1X11B
DIR2 AD8
EBC; EN2
I
General-purpose input
P10_IN.P9
D9
EBC
CCPOS2A
CCU60
TCK_B
JTAG
O
HW_Out
General-purpose output P10_OUT.P8
reserved
P10.9
Select
HW_Out
P10_IOCR09.PC 0XXXB
General-purpose output P10_OUT.P9
1X00B
SELO4
U0C0
1X01B
MCLKOUT
U0C1
1X10B
reserved
DIR2 AD9
User’s Manual
Parallel Ports, V1.6D4
1X11B
EBC; EN2
7-59
HW_Out
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-27
Port
Pin
I/O
P10.10 I
O
Parallel Ports
Port 10 Input/Output Functions (cont’d)
Connected Signal(s)
From / to
Module
Register/Bit
Field
General-purpose input
P10_IN.P10
P10_IOCR10.PC 0XXXB
D10
EBC
DX2C
U0C0
TDI_B
JTAG
DX1A
U0C1
General-purpose output P10_OUT.P10
1X00B
SELO0
U0C0
1X01B
COUT63
CCU60
1X10B
reserved
DIR2 AD10
P10.11 I
O
1X11B
EBC; EN2
General-purpose input
P10_IN.P11
D11
EBC
DX1D
U1C0
RXDC2B
CAN2
TMS_B
JTAG
P10_IOCR11.PC 0XXXB
1X00B
SCLKOUT
U1C0
1X01B
BRKOUT
JTAG
1X10B
DIR2 AD11
O
HW_Out
General-purpose output P10_OUT.P11
reserved
P10.12 I
Select
1X11B
EBC; EN2
General-purpose input
P10_IN.P12
D12
EBC
DX0C
U1C0
DX1E
U1C0
HW_Out
P10_IOCR12.PC 0XXXB
General-purpose output P10_OUT.P12
1X00B
DOUT
U1C0
1X01B
TXDC2
CAN2
1X10B
TDO
JTAG
1X11B
EBC; EN2
HW_Out
DIR2 AD12
User’s Manual
Parallel Ports, V1.6D4
7-60
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 7-27
Port
Pin
I/O
P10.13 I
O
Parallel Ports
Port 10 Input/Output Functions (cont’d)
Connected Signal(s)
From / to
Module
Register/Bit
Field
General-purpose input
P10_IN.P13
P10_IOCR13.PC 0XXXB
DX0D
U1C0
General-purpose output P10_OUT.P13
1X00B
DOUT
U1C0
1X01B
TXDC3
CAN3
1X10B
SELO3
U1C0
1X11B
EBC; SEN
HW_Out
SDIR WR
P10.14 I
O
General-purpose input
P10_IN.P14
DX0C
U0C1
RXDC3C
CAN3
1X00B
SELO1
U1C0
1X01B
DOUT
U0C1
1X10B
SDIR RD
O
P10_IOCR14.PC 0XXXB
General-purpose output P10_OUT.P14
reserved
P10.15 I
Select
1X11B
EBC; SEN
General-purpose input
P10_IN.P15
DX1C
U0C1
HW_Out
P10_IOCR15.PC 0XXXB
General-purpose output P10_OUT.P15
1X00B
SELO2
U1C0
1X01B
DOUT
U0C1
1X10B
DOUT
U1C0
1X11B
EBC; SEN
HW_Out
SDIR ALE
User’s Manual
Parallel Ports, V1.6D4
7-61
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
7.3.13
Parallel Ports
Port 11
Port 11 is an 6-bit GPIO port.
7.3.13.1 Overview
The port registers of Port 11 are shown in Figure 7-15.
For this port, all pins can be read as GPIO, from the Port Input Register.
Control
Registers
Modification
Registers
P11_IOCR00
:
P11_IOCR05
P11_OMRL
Data
Registers
P11_OUT
P11_IN
P11_POCON
Port11_Regs.vsd
Figure 7-15 Port 11 Register Overview
Table 7-28
Port 11 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P11_OUT
Port 11 Output Register
FFB8H
0000H
P11_IN
Port 11 Input Register
FF96H
0000H
P11_OMRL
Port 11 Output Modification Register Low
E9ECH
0000H
P11_POCON Port 11 Output Control Register
E8B6H
0000H
P11_IOCR00 Port 11 Input/Output Control Register 0
E960H
0000H
P11_IOCR01 Port 11 Input/Output Control Register 1
E962H
0000H
P11_IOCR02 Port 11 Input/Output Control Register 2
E964H
0000H
P11_IOCR03 Port 11 Input/Output Control Register 3
E966H
0000H
P11_IOCR04 Port 11 Input/Output Control Register 4
E968H
0000H
P11_IOCR05 Port 11 Input/Output Control Register 5
E96AH
0000H
User’s Manual
Parallel Ports, V1.6D4
7-62
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Parallel Ports
7.3.13.2 Port 11 Functions
The following table describes the mapping between the pins of Port 11 and the related
I/O signals.
Table 7-29
Port 11 Input/Output Functions
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field
Select
P11.0
I
General-purpose input
P11_IN.P0
P11_IOCR00.PC
0XXXB
CCPOS0A
CCU63
General-purpose output
P11_OUT.P0
O
P11.1
I
O
P11.2
I
O
P11.3
1X00B
reserved
1X01B
reserved
1X10B
reserved
1X11B
General-purpose input
P11_IN.P1
CCPOS1A
CCU63
General-purpose output
P11_OUT.P1
P11_IOCR01.PC
0XXXB
1X00B
reserved
1X01B
reserved
1X10B
reserved
1X11B
General-purpose input
P11_IN.P2
CCPOS2A
CCU63
General-purpose output
P11_OUT.P2
P11_IOCR02.PC
0XXXB
1X00B
reserved
1X01B
reserved
1X10B
reserved
1X11B
I
General-purpose input
P11_IN.P3
O
General-purpose output
P11_OUT.P3
P11_IOCR03.PC
0XXXB
1X00B
reserved
1X01B
reserved
1X10B
reserved
1X11B
User’s Manual
Parallel Ports, V1.6D4
7-63
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Parallel Ports
Table 7-29
Port 11 Input/Output Functions (cont’d)
Port
Pin
I/O
Connected Signal(s)
From / to
Module
Register/Bit Field
Select
P11.4
I
General-purpose input
P11_IN.P4
P11_IOCR04.PC
0XXXB
O
General-purpose output
P11_OUT.P4
P11.5
1X00B
reserved
1X01B
reserved
1X10B
reserved
1X11B
I
General-purpose input
P11_IN.P5
O
General-purpose output
P11_OUT.P5
P11_IOCR05.PC
0XXXB
1X00B
reserved
1X01B
reserved
1X10B
reserved
1X11B
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Parallel Ports, V1.6D4
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System Units (Vol. 1 of 2)
Preliminary
7.3.14
Parallel Ports
Port 15
Port 15 is an 8-bit analog or digital input port.
7.3.14.1 Overview
To use the Port 15 as an analog input, the Schmitt trigger in the input stage must be
disabled. This is achieved by setting the corresponding bit in the register P15_DIDIS.
Control
Registers
Data
Registers
P15_DIDIS
P15_OUT
P15_IN
Port15_Regs.vsd
Figure 7-16 Port 15 Register Overview
Table 7-30
Port 15 Registers
Register
Short Name
Register Long Name
Address
Offset
Reset
Value
P15_IN
Port 15 Input Register
FF9EH
0000H
P15_DIDIS
Port 15 Digital Input Disable Register
FE9EH
0000H
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Parallel Ports, V1.6D4
7-65
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System Units (Vol. 1 of 2)
Preliminary
Parallel Ports
7.3.14.2 Port 15 Functions
The following table describes the mapping between the pins of Port 15 and the related
I/O signals.
Table 7-31
Port 15 Input/Output Functions
Port
Pin
I/O
Select Connected Signal(s)
P15.0
I
P15.1
I
P15.2
I
T5IN
GPT12E
P15.3
I
T5EUD
GPT12E
P15.4
I
T6IN
GPT12E
P15.5
I
T6EUD
GPT12E
P15.6
I
P15.7
I
User’s Manual
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7-66
From / to Module
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
8
Dedicated Pins
Dedicated Pins
Most of the input/output or control signals of the functional the XC2000 are realized as
alternate functions of pins of the parallel ports. There is, however, a number of signals
that use separate pins, including the oscillator, special control signals and, of course, the
power supply.
Table 8-1 summarizes the dedicated pins of the XC2000.
Table 8-1
XC2000 Dedicated Pins
Pin(s)
Function
PORST
Power-On Reset Input
ESR0
External Service Request Input 0
ESR1
External Service Request Input 1
ESR2
External Service Request Input 2
XTAL1, XTAL2
Oscillator Input/Output (main oscillator)
TESTM
Test Mode Enable
TRST
Test-System Reset Input
TRef
Control Pin for Core Voltage Generation
VAREFx, VAGND
VDDIM
VDDI1
VDDPA
VDDPB
VSS
Power Supply for the Analog/Digital Converter(s)
Digital Core Supply for Domain M (1 pin)
Digital Core Supply for Domain 1 (3 pins)
Digital Pad Supply for Domain A (1 pin)
Digital Pad Supply for Domain B (8 pins)
Digital Ground (4 pins)
The Power-On Reset Input PORST allows to put the XC2000 into the well defined reset
condition either at power-up or external events like a hardware failure or manual reset.
The External Service Request Inputs ESR0, ESR1, and ESR2 can be used for several
system-related functions:
• trigger interrupt or trap (Class A or Class B) requests via an external signal (e.g. a
power-fail signal)
• generate wake-up request signals
• generate hardware reset requests (ESR0 is bidirectional by default, ESR1 and ESR2
can optionally output a reset signal)
• data/control input for CCU6x, MultiCAN, and USIC (ESR1 or ESR2)
• software-controlled input/output signal
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DediPins_X7, V2.0
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V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Dedicated Pins
The Oscillator Input XTAL1 and Output XTAL2 connect the internal Main Oscillator
to the external crystal. The oscillator provides an inverter and a feedback element. The
standard external oscillator circuitry (see Section 6.1.2) comprises the crystal, two low
end capacitors and series resistor to limit the current through the crystal. The main
oscillator is intended for the generation of a high-precision operating clock signal for the
XC2000.
An external clock signal may be fed to the input XTAL1, leaving XTAL2 open. The current
logic state of input XTAL1 can be read via a status flag, so XTAL1 can be used as digital
input if neither the oscillator interface nor the clock input is required.
Note: Pin XTAL1 belongs to the core power domain DMP_M. All input signals, therefore,
must be within the core voltage range.
The Test Mode Input TESTM puts the XC2000 into a test mode, which is used during
the production tests of the device. In test mode, the XC2000 behaves different from
normal operation. Therefore, pin TESTM must be held HIGH (connect to VDDPB) for
normal operation in an application system.
The Test Reset Input TRST puts the XC2000’s debug system into reset state. During
normal operation this input should be held low. For debugging purposes the on-chip
debugging system can be enabled by driving pin TRST high at the rising edge of PORST.
The Control Pin for Core Voltage Generation TRef selects the generation method for
the core supply voltage VDDI. Connect TRef to VDDPB to use the on-chip EVRs, connect
TRef to VDDI1 for external core voltage supply (on-chip EVRs off).
The Analog Reference Voltage Supply pins VAREFx and VAGND provide separate
reference voltage for the on-chip Analog/Digital-Converter(s). This reduces the noise
that is coupled to the analog input signals from the digital logic sections and so improves
the stability of the conversion results, when VAREF and VAGND are properly discoupled
from VDD and VSS. Also, because conversion results are generated in relation to the
reference voltages, ratiometric conversions are easily achieved.
Note: Channel 0 of each module can be used as an alternate reference voltage input.
The Core Supply pins VDDIM/VDDI1 serve two purposes: While the on-chip EVVRs
provide the power for the core logic of the XC2000 these pins connect the EVVRs to their
external buffer capacitors. For external supply, the core voltage is applied to these pins.
The respective VDDI/VSS pairs should be decoupled as close to the pins as possible. Use
ceramic capacitors and observe their values recommended in the respective Data
Sheet.
The Power Supply pins VDDPA/VDDPB provide the power supply for all the digital logic of
the XC2000. Each power domain (DMP_A and DMP_B) can be supplied with an
arbitrary voltage within the specified supply voltage range (please refer to the
corresponding Data Sheets). These pins supply the output drivers as well as the on-chip
EVVRs, except for external core voltage supply. The respective VDDP/VSS pairs should
be decoupled as close to the pins as possible.
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DediPins_X7, V2.0
8-2
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Dedicated Pins
The Ground Reference pins VSS provide the ground reference voltage for the power
supplies as well as the reference voltage for the input signals.
Note: All VDDx pins and all VSS pins must be connected to the power supplies and
ground, respectively.
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DediPins_X7, V2.0
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Preliminary
User’s Manual
DediPins_X7, V2.0
Dedicated Pins
8-4
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9
The External Bus Controller EBC
The External Bus Controller EBC
All external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required at all, or dynamically (depending on the selected address range,
belonging to a chip-select signal) to one of four different external memory access modes,
which are as follows:
•
•
•
•
16/17/18/19 … 24-bit Addresses, 16-bit Data, Demultiplexed
16/17/18/19 … 24-bit Addresses, 16-bit Data, Multiplexed
16/17/18/19 … 24-bit Addresses, 8-bit Data, Multiplexed
16/17/18/19 … 24-bit Addresses, 8-bit Data, Demultiplexed
Note: The following description refers to the general EBC feature set. In packages
smaller than 144-pin, some features are not available, see Table 9-1.
In the multiplexed bus modes intra-segment address outputs and data input/outputs are
overlaid on 16 port pins. High order address (segment) lines are mapped to separate
port pins. In the demultiplexed bus modes, address outputs and data input/outputs are
not overlaid but mapped to the port pins separately. For applications which do not use
all address lines for external devices, the external address space can be restricted to
8 Mbytes, 4 Mbytes, 2 Mbytes, 1 Mbyte, 512 Kbytes, 256 Kbytes, 128 Kbytes or
64 Kbytes. In this case seven, six, five and so on, or no segment address lines are active.
Up to 5 external CS signals can be generated in order to save external glue logic. Access
to very slow memories is supported via a particular ‘Ready’ function. A HOLD/HLDA
protocol is available for bus arbitration.
The XC2000 External Bus Controller (EBC) allows access to external
peripherals/memories and to internal LXBus modules. The LXBus is an internal
representation of the ExtBus and it controls accesses to integrated peripherals and
modules in the same way as accesses to external components. Because some ExtBus
control signals are generally configurable, related additional control signals are
necessary for the internal LXBus to support its maybe different configuration.
The function of the EBC is controlled via a set of configuration registers. The basic and
general behaviour is programmed via the mode-selection registers EBCMOD0 and
EBCMOD1.
Additionally to the supported external bus chip-select channels, one LXBus chip select
channel is provided (both types together handled as ‘external’ chip select channels).
With one exception, each of these chip-select signals is programmable via a set of
registers. The Function CONtrol register for CSx (FCONCSx) register specifies the
external bus/LXBus cycles in terms of address (multiplexed/demultiplexed), data
(16-bit/8-bit), READY control, and chip-select enable. The timing of the bus access is
controlled by the Timing CONfiguration registers for CSx (TCONCSx), which specify the
timing of the bus cycle with the lengths of the different access phases. All these
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Preliminary
The External Bus Controller EBC
parameters are used for accesses within a specific address area that is defined via the
corresponding ADDRess SELect register ADDRSELx.
The five register sets (FCONCSx/TCONCSx/ADDRSELx) define five independent and
programmable “address windows”, whereas all external accesses outside these
windows are controlled via registers FCONCS0 and TCONCS0. Chip Select signals CS0
… CS4 belong to accesses on external bus, the additional Chip Select CS7 is used for
access to the internal MultiCAN and USIC module on LXBus.
The external bus timing is related to the reference CLocK OUTput (CLKOUT). All bus
signals are generated in relation to the rising edge of this clock. The external bus protocol
is compatible with those of the standard C166 Family. However, the external bus timing
is improved in terms of wait-state granularity and signal flexibility.
These improvements are configured via an enhanced register set (see above) in
comparison to C166 Family. The C16x registers SYSCON and BUSCONx are no longer
used. But because the configuration of the external bus controller is done during the
application initialization, only some initialization code has to be adapted for using the
new EBC module instead of the C16x external bus controller.
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EBC_X8, V1.0d1
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System Units (Vol. 1 of 2)
Preliminary
9.1
The External Bus Controller EBC
External Bus Signals
The EBC is using the following I/O signals:
Table 9-1
Signal
EBC Bus Signals
I/O
Port
Pins
Description
Signals available both in the 100-pin and 144-pin package
ALE
O
P10
Address Latch Enable; active high
RD
O
ReaD strobe: activated for every read access (active low)
WR, WRL
O
WRite/WRite Low byte strobe (active low)
WR-mode: activated for every write access.
WRL-mode: activated for low byte write accesses on a 16-bit
bus and for every data write access on an 8-bit bus.
BHE, WRH O
P2
Byte High Enable/WRite High byte strobe (active low)
BHE-mode: activated for every data access to the upper
byte of the 16-bit bus (handled as additional address bit)
WRH-mode: activated for high byte write accesses on a
16-bit bus.
READY/
READY
P2
READY; used for dynamic wait state insertion;
programmable active high or low
AD[12..0]
I/O
AD[15..13]
P10
P2
Address/Data bus; in multiplexed mode this bus is used for
both address and data, in demultiplexed mode it is data bus
only
A[7..0]
A[15..8]
A[23..16]
O
P0
P1
P2
Address bus
CS[3..0]
O
P4
Chip Select; active low;
CS7-used for internal LXBus access to MultiCAN and USICs
I
Signals available additionally in the 144-pin package
BREQ
O
HLDA
I/O
HoLD Accepted output (by the master); active low
Hold Accepted input (at the slave)
HOLD
I
HoLD request
CS4
O
User’s Manual
EBC_X8, V1.0d1
P3
P6
Bus REQuest; active low
Chip Select; active low;
CS7-used for internal LXBus access to MultiCAN and USICs
9-3
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 9-2
The External Bus Controller EBC
Write Configurations (see Chapter 9.3.2)
Written Byte
General Write Configuration
Low
High
WR
BHE
–
–
inactive
don’t care 0/1
write
–
active
inactive
–
write
active
write
write
active
9.2
Separated Byte Low/High Writes
ADDR[0] WRL
WRH
ADDR[0]
inactive
inactive
0/1
0
active
inactive
0/1
active
1
inactive
active
0/1
active
0
active
active
0/1
Timing Principles
The external bus timing is subdivided into six different timing phases (A-F).
9.2.1
Basic Bus Cycle Protocols
The phases A-F define all control signals needed for any access sequence to external
devices. At the beginning of a phase, the output signals may change within a given
output delay time. After the output delay time, the values of the control output signals are
stable within this phase. The output delay times are specified in the AC characteristics.
Each phase can occupy a programmable number of clock cycles. The number of clock
cycles is programmed in the TCONCSx register selected via the related address range
and CSx.
Access n
Phases
A
Address
BCDEF
Address n
FCONCSx
FCON of n
Access n + 1
A
BCDEF
Address n + 1
Access n + 2
A
BCDEF
Address n + 2
FCON of n + 1
Access n + 3
A
BCDEF
A
Address n + 3
FCON of n + 2
FCON of n + 3
MCA05373
Figure 9-1
Phases of a Sequence of Several Accesses
Phase A is used for tristating databus drivers from the previous cycle (tristate wait states
after CS switch). Phase A cycles are not inserted at every access cycle but only when
changing the CS. If an access using one CS (CSx) was finished and the next access with
a different CS (CSy) is started then Phase A cycle(s) are performed according to the
control bits as set in the first CS (CSx).
The A Phase cycles are inserted while the addresses and ALE of the next cycle are
already applied.
The following diagrams show the 6 timing phases for read and write accesses on the
demultiplexed bus and the multiplexed bus.
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EBC_X8, V1.0d1
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System Units (Vol. 1 of 2)
Preliminary
9.2.1.1
The External Bus Controller EBC
Demultiplexed Bus
During demultiplexed access, the address and data signals exists on the bus in parallel.
Phases
A
B
C
D
E
F
ALE
Valid
ADDR, CS
RD
Valid
Read DATA
Programmable
Clocks
0-3 1-2
0-3
0-1
1 - 32
0-3
MCT05374
Figure 9-2
Demultiplexed Bus Read
Phases
A
B
C
D
E
F
ALE
Valid
ADDR, CS
WR
Valid
Write DATA
Programmable
Clocks
0-3 1-2
0-3
0-1
1 - 32
0-3
MCT05375
Figure 9-3
•
•
•
•
•
•
Demultiplexed Bus Write
A phase: Addresses valid, ALE high, no command. CS switch tristate wait states
B phase: Addresses valid, ALE high, no command. ALE length
C phase: Addresses valid, ALE low, no command. R/W delay
D phase: Write data valid, ALE low, no command. Data valid for write cycles
E phase: Command (read or write) active. Access time
F phase: Command inactive, address hold. Read data tristate time, write data hold
time
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EBC_X8, V1.0d1
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9.2.1.2
The External Bus Controller EBC
Multiplexed Bus
During time multiplexed access, the address and data signals share the same external
lines.
Phases
A
B
C
D
E
F
ALE
Valid
ADDR, CS
RD
Address Valid
RD DATA
Programmable
Clocks
0-3 1-2
0-3
Data In
0-1
1 - 32
0-3
MCT05376
Figure 9-4
Multiplexed Bus Read
Phases
A
B
C
D
E
F
ALE
Valid
ADDR, CS
WR
WR DATA
Programmable
Clocks
Address Valid
0-3 1-2
0-3
Data Out
0-1
1 - 32
Next Address
0-3
MCT05377
Figure 9-5
•
•
•
•
•
•
Multiplexed Bus Write
A phase: addresses valid, ALE high, no command. CS switch tristate wait states
B phase: addresses valid, ALE high, no command. ALE length
C phase: addresses valid, ALE low, no command. Address hold, R/W delay
D phase: address tristate for read cycles, data valid for write cycles, ALE low, no
command
E phase: command (read or write) active. Access time
F phase: command inactive, address hold. Read data tristate time, write data hold
time
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V1.0, 2007-06
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System Units (Vol. 1 of 2)
Preliminary
9.2.2
The External Bus Controller EBC
Bus Cycle Phases
This chapter provides a detail description of each phase of an external memory bus
access cycle.
9.2.2.1
A Phase - CS Change Phase
The A phase can take 0-3 clocks. It is used for tristating databus drivers from the
previous cycle (tristate wait states after chip select switch).
A phase cycles are not inserted at every access cycle, but only when changing the CS.
If an access using one CS (CSx) ends and the next access with a different CS (CSy) is
started, then A phase cycles are performed according to the bits set in the first CS
(CSx). This feature is used to optimize wait states with devices having a long turn-off
delay at their databus drivers, such as EPROMs and flash memories.
The A phase cycles are inserted while the addresses and ALE of the next cycle are
already applied.
If there are some idle cycles between two accesses, these clocks are taken into account
and the A phase is shortened accordingly. For example, if there are three tristate cycles
programmed and two idle cycles occur, then the A phase takes only one clock.
9.2.2.2
B Phase - Address Setup/ALE Phase
The B phase can take 1-2 clocks. It is used for addressing devices before giving a
command, and defines the length of time that ALE is active. In multiplexed bus mode,
the address is applied for latching.
9.2.2.3
C Phase - Delay Phase
The C phase is similar to the A an B phases but ALE is already low. It can take 0-3 clocks.
In multiplexed bus mode, the address is held in order to be latched safely. Phase C
cycles can be used to delay the command signals (RW delay).
9.2.2.4
D Phase - Write Data Setup/MUX Tristate Phase
The D phase can take 0-1 clocks. It is used to tristate the address on the multiplexed bus
when a read cycle is performed. For all write cycles, it is used to ensure that the data are
valid on the bus before the command is applied.
9.2.2.5
E Phase - RD/WR Command Phase
The E phase is the command or access phase, and takes 1-32 clocks. Read data are
fetched, write data are put onto the bus, and the command signals are active. Read data
are registered with the terminating clock of this phase.
The READY function lengthens this phase, too. READY-controlled access cycles may
have an unlimited cycle time.
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Preliminary
9.2.2.6
The External Bus Controller EBC
F Phase - Address/Write Data Hold Phase
The F phase is at the end of an access. It can take 0-3 clocks.
Addresses and write data are held while the command is inactive. The number of wait
states inserted during the F phase is independently programmable for read and write
accesses. The F phase is used to program tristate wait states on the bidirectional data
bus in order to avoid bus conflicts.
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Preliminary
9.2.3
The External Bus Controller EBC
Bus Cycle Examples: Fastest Access Cycles
b
e
CLK
ALE
ADDR, CS
Valid
RD
DATA In
Valid
MCT05378
Figure 9-6
Fastest Read Cycle Demultiplexed Bus
b
e
CLK
ALE
ADDR, CS
Valid
WR
DATA Out
Valid
MCT05379
Figure 9-7
Fastest Write Cycle Demultiplexed Bus
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Preliminary
The External Bus Controller EBC
b
e
d
f
CLK
ALE
ADDR, CS
Valid
RD
Muxed
Address Out /
Data In
Addr. Valid
Data Valid
MCT05380
Figure 9-8
Fastest Read Cycle Multiplexed Bus
b
e
CLK
ALE
ADDR, CS
Valid
RD
Muxed
Address Out /
Data Out
Addr.
Valid
Valid
MCT05381
Figure 9-9
Fastest Write Cycle Multiplexed Bus
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System Units (Vol. 1 of 2)
Preliminary
9.3
The External Bus Controller EBC
Functional Description
The following section describes the EBC registers and their settings.
9.3.1
Configuration Register Overview
There are 3 groups of EBC registers:
•
•
•
EBC mode registers influencing the global functions.
Chip-select-related registers controlling the functionality linked to one CS.
MultiCAN and USIC related registers are used to control the access to the internal
LXBus.
CS0 is the default chip-select signal that is active whenever no other chip-select or
internal address space is addressed. Therefore, CS0 has no ADDRSEL register.
Note: All EBC registers are write-protected by the EINIT protection mechanism. Thus,
after execution of the EINIT instruction, these registers are not writable any more.
Table 9-3
EBC Configuration Register Overview
Name
CS1)
Description
Address
00EExxH
Start-up
Value
EBCMOD0
all
EBC MODe 0;
alternate function of EBC pins
00
5000H
EBCMOD1
all
EBC MODe 1;
alternate function of EBC pins
02
003FH
TCONCS0
0
Timing CONtrol for CS0
10
7C3DH
FCONCS0
0
Function CONtrol for CS0
12
0011H
TCONCS1-71)
1-61), Timing CONtrol for CS1 … CS71)
7
18, 20, 28,
0000H
30, 38, 40, 48
FCONCS1-71)
1-61), Function CONtrol for CS1 … CS71)
7
1A, 22, 2A,
0000H,
32, 3A, 42, 4A 0027H
ADDRSEL1-71) 1-61), ADDress window SELection
7
for CS1 … CS71)
1E, 26, 2E,
0000H,
36, 3E, 46, 4E 2003H
1) CS5 and CS6 register sets are not available (reserved for future LXBus peripherals).
A 128-byte address space is occupied/reserved by the EBC.
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The External Bus Controller EBC
00EE8E
ADDRSEL7
00EE4E
FCONCS7
00EE4A
TCONCS7
00EE48
ADDRSEL4
00EE36
FCONCS4
00EE32
CS7 Channel Control
CS4 Channel Control
TCONCS4
00EE30
ADDRSEL3
00EE2E
FCONCS3
00EE2A
TCONCS3
00EE28
ADDRSEL2
00EE26
FCONCS2
00EE22
TCONCS2
ADDRSEL1
00EE20
00EE1E
FCONCS1
TCONCS1
00EE1A
00EE18
FCONCS0
TCONCS0
00EE12
00EE10
EBCMO D1
00EE02
CS3 Channel Control
CS2 Channel Control
CS1 Channel Control
CS0 Channel Control
G eneral EBC Control
EBCMO D0
00EE00
MCA05382_XC
Figure 9-10 Mapping of EBC Registers into the XSFR Space
Note: CS5 and CS6 register sets are not available (reserved for future LXBus
peripherals).
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Preliminary
9.3.2
The External Bus Controller EBC
The EBC Mode Register 0
EBCMODe Register 0
EBCMOD0
EBC Mode Register 0
15
14
13
12
XSFR (EE00H/--)
11
10
9
8
7
RDY RDY ALE BYT WR EBC SLA ARB
POL DIS DIS DIS CFG DIS VE EN
rw
rw
rw
rw
rw
rw
rw
rw
Reset Value: 5000H
6
5
4
3
2
1
CSPEN
SAPEN
rw
rw
Field
Bits
Type
Description
RDYPOL
15
rw
READY Pin Polarity1)
0B
READY is active low
1
READY is active high
RDYDIS
14
rw
READY Pin Disable1)
0B
READY enabled
1B
READY disabled
ALEDIS
13
rw
ALE Pin Disable
0B
ALE enabled
1B
ALE disabled
BYTDIS
12
rw
BHE Pin Disable
0B
BHE enabled
1B
BHE disabled
WRCFG2)
11
rw
Configuration for Pins WR/WRL, BHE/WRH
0B
WR and BHE
1B
WRL and WRH
EBCDIS
10
rw
EBC Pins Disable
0B
EBC is using the pins for external bus
1B
EBC pins disabled
SLAVE
9
rw
SLAVE Mode Enable
0B
Bus arbiter acts in master mode
1B
Bus arbiter acts in slave mode
ARBEN
8
rw
BUS Arbitration Pins Enable
0B
HOLD, HLDA and BREQ pins are disabled
1B
Pins act as HOLD, HLDA, and BREQ
User’s Manual
EBC_X8, V1.0d1
9-13
0
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
The External Bus Controller EBC
Field
Bits
Type
Description
CSPEN
[7:4]
rw
CSx Pins Enable (only external CSx)
0000BAll external Chip Select pins disabled.
0001BCS0 pin enabled
0010BCS1 and CS0 pin enabled
…
…
0101BFive CSx pins enabled: CS4 - CS0
Else not supported (reserved)
SAPEN
[3:0]
rw
Segment Address Pins Enable
0000B All segment address pins disabled
0001B One: A[16] enabled
…
…
1000B Eight: A[23:16] enabled
Else not supported (reserved)
1) Not available in the 100-pin package.
2)
A change of the bit content is not valid before the next external bus access cycle.
Notes
1. Disabled pins are used for general purpose IO or for alternate functions (see port and
pin descriptions).
2. Bit field CSPEN controls the number of available CSx pins. The related address
windows and bus functions are enabled with the specific ENCSx bits in the
FCONCSx registers (see Page 9-20). There, an additional chip select (CS7) is
defined for internal access to the LXBus peripherals MultiCAN and USIC.
3. The external bus arbitration pins have a separate ARBitration ENable bit (ARBEN)
that has to be set in order to use the pins for arbitration and not for General Purpose
IO (GPIO). If ARBEN is cleared, the arbitration inputs HLDA and HOLD are fixed
internally to an inactive high state. Additionally, the master/slave setting of the arbiter
is done with a separate bit (SLAVE).
4. The reset value depends on the selected startup configuration.
User’s Manual
EBC_X8, V1.0d1
9-14
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9.3.3
The External Bus Controller EBC
The EBC Mode Register 1
EBC MODe register 1 controls the general use of port pins for external bus.
EBCMOD1
EBC Mode Register 1
XSFR (EE02H/--)
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
6
Reset Value: 003FH
5
4
WRP DHP ALP A0P
DIS DIS DIS DIS
rw
rw
rw
rw
3
2
1
0
APDIS
rw
Field
Bits
Type
Description
WRPDIS
7
rw
WR/WRL Pin Disable
0B
WR/WRL pin enabled
1B
WR/WRL pin disabled
DHPDIS
6
rw
Data High Port Pins Disable
0B
Address/Data bus pins 15-8 enabled
1B
Address/Data bus pins 15-8 disabled
ALPDIS
5
rw
Address Low Pins Disable
0B
Address bus pins 7-0 generally enabled
(depending on APDIS/A0PDIS)
1B
Address bus pins 7-0 disabled
A0PDIS
4
rw
Address Bit 0 Pin Disable
0B
Address bus pin 0 enabled
1B
Address bus pin 0 disabled
APDIS
[3:0]
rw
Address Port Pins Disable
0000B Address bus pins 15-1 enabled
0001B Pin A15 disabled, A14-A1 enabled
0010B Pins A15-A14 disabled, A13-A1 enabled
0011B Pins A15-A13 disabled, A12-A1 enabled
…
…
1110B Pins A15-A2 disabled, A1 enabled
1111B Address bus pins 15-1 disabled
Notes
1. Disabled bus pins may be used for general purpose IO or for alternate functions (see
port and pin descriptions).
2. After reset, the address and data bus pins are enabled, but in Idle state.
User’s Manual
EBC_X8, V1.0d1
9-15
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9.3.4
The External Bus Controller EBC
The Timing Configuration Registers TCONCSx
The timing control registers are used to program the described cycle timing for the
different access phases. The timing control registers may be reprogrammed during code
fetches from the affected address window. The new settings are first valid for the next
access.
TCONCS0
Timing Cfg. Reg. for CS0
15
14
13
12
11
XSFR (EE10H/--)
10
9
8
7
6
Reset Value: 7C3DH
5
4
3
2
1
0
-
WRPHF
RDPHF
PHE
PHD
PHC
PHB
PHA
-
rw
rw
rw
rw
rw
rw
rw
Field
Bits
WRPHF
[14:13] rw
Write Phase F
00B 0 clock cycles
…
…
11B 3 clock cycles (default)
RDPHF
[12:11] rw
Read Phase F
00B 0 clock cycles (default)
…
…
11B 3 clock cycles
PHE
[10:6]
rw
Phase E
00000B1 clock cycle
…
… (default: 9 clock cycles)
11111B32 clock cycles
PHD
5
rw
Phase D
0B
0 clock cycles (default)
1B
1 clock cycle
PHC
[4:3]
rw
Phase C
00B 0 clock cycles (default)
…
…
11B 3 clock cycles
PHB
2
rw
Phase B
0B
1 clock cycle (default)
2 clock cycles
1B
User’s Manual
EBC_X8, V1.0d1
Type
Description
9-16
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
The External Bus Controller EBC
Field
Bits
Type
Description
PHA
[1:0]
rw
Phase A
00B 0 clock cycles
…
…
11B 3 clock cycles (default)
TCONCSx (x = 1-4)
Timing Cfg. Reg. for CSx
TCONCS7
Timing Cfg. Reg. for CS7
15
14
13
12
11
10
XSFR (EE10H + x*8/--)
Reset Value: 0000H
XSFR (EE48H/--)
Reset Value: 0000H
9
8
7
6
5
4
3
2
1
0
-
WRPHF
RDPHF
PHE
PHD
PHC
PHB
PHA
-
rw
rw
rw
rw
rw
rw
rw
Field
Bits
WRPHF
[14:13] rw
Write Phase F
00B 0 clock cycles
…
…
11B 3 clock cycles (default)
RDPHF
[12:11] rw
Read Phase F
00B 0 clock cycles (default)
…
…
11B 3 clock cycles
PHE
[10:6]
rw
Phase E
00000B1 clock cycle
…
… (default: 9 clock cycles)
11111B32 clock cycles
PHD
5
rw
Phase D
0B 0 clock cycles (default)
1B 1 clock cycle
PHC
[4:3]
rw
Phase C
00B 0 clock cycles (default)
…
…
11B 3 clock cycles
PHB
2
rw
Phase B
0B 1 clock cycle (default)
1B 2 clock cycles
User’s Manual
EBC_X8, V1.0d1
Type
Description
9-17
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
The External Bus Controller EBC
Field
Bits
Type
Description
PHA
[1:0]
rw
Phase A
00B 0 clock cycles
…
…
11B 3 clock cycles (default)
Note: x = 7 belongs to the additional chip select (CS7) which is used and defined for
internal access to the LXBus peripherals MultiCAN and USIC. The register
TCONCS4 controls the chip select CS4, that is available only in the 144-pin
package.
User’s Manual
EBC_X8, V1.0d1
9-18
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9.3.5
The External Bus Controller EBC
The Function Configuration Registers FCONCSx
The Function Control registers are used to control the bus and READY functionality for
a selected address window. It can be distinguished between 8 and 16-bit bus and
multiplexed and demultiplexed accesses. Furthermore it can be defined whether the
address window (and its chip select signal CSx) is generally enabled or not.
FCONCS0
Function Cfg. Reg. for CS0
XSFR (EE12H/--)
15
14
13
12
11
10
9
8
7
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reset Value: 0011H
5
4
3
-
BTYP
-
-
rw
-
2
1
0
RDY RDY EN
MOD EN CS
rw
rw
rw
Field
Bits
Type
Description
BTYP
[5:4]
rw
Bus Type Selection
00B 8 bit Demultiplexed
01B 08 bit Multiplexed
10B 16 bit Demultiplexed
11B 16 bit Multiplexed
RDYMOD
2
rw
Ready Mode
0B
Asynchronous READY
1B
Synchronous READY
RDYEN
1
rw
Ready Enable
0B
Access time is controlled by bit field PHEx
1B
Access time is controlled by bit field PHEx and
READY signal
ENCS1)
0
rw
Enable Chip Select
0B
Disable
1B
Enable
1) Disabling a chip select not only effects the chip select output signal, it also deactivates the respective address
window of the disabled chip select. A disabled address window is also ignored by an address window
arbitration (see Chapter 9.3.6.3).
User’s Manual
EBC_X8, V1.0d1
9-19
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
The External Bus Controller EBC
FCONCSx (x = 1-4)
Function Cfg. Reg. for CSx
FCONCS7
Function Cfg. Reg. for CS7
XSFR (EE12H + x*8/--)
Reset Value: 0000H
XSFR (EE4AH/--)
Reset Value: 0027H
15
14
13
12
11
10
9
8
7
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
4
3
-
BTYP
-
-
rw
-
2
1
0
RDY RDY EN
MOD EN CS
rw
rw
rw
Field
Bits
Type
Description
BTYP
[5:4]
rw
Bus Type Selection
00B 8 bit Demultiplexed
01B 8 bit Multiplexed
10B 16 bit Demultiplexed
11B 16 bit Multiplexed
RDYMOD
2
rw
Ready Mode
0B
Asynchronous READY
Synchronous READY
1B
RDYEN
1
rw
Ready Enable
0B
Access time is controlled by bit field PHEx
1B
Access time is controlled by bit field PHEx and
READY signal
ENCS1)
0
rw
Enable Chip Select
0B
Disable
1B
Enable
1) Disabling a chip select not only effects the chip select output signal, it also deactivates the respective address
window of the disabled chip select. A disabled address window is also ignored by an address window
arbitration (see Chapter 9.3.6.3).
Notes
1. x = 7 belongs to the additional chip select (CS7) which is used and defined for internal
access to the LXBus peripherals MultiCAN and USIC. The register FCONCS4
controls the chip select CS4, that is available only in the 144-pin package.
2. The specific ENCSx bits in the FCONCSx registers enable the related address
windows and bus functions and the corresponding chip select signal CSx. But it
depends on the definition of bit field CSPEN in register EBCMOD0 how many CSx
pins are available and used for the external system. If an address window is enabled
User’s Manual
EBC_X8, V1.0d1
9-20
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
The External Bus Controller EBC
but no external pin is available for the CSx, the external bus cycle is executed without
chip select signal.
3. With ENCS7 the chip select CS7 and its related register set is enabled and defined
for internal access to the LXBus peripherals MultiCAN and USIC.
User’s Manual
EBC_X8, V1.0d1
9-21
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9.3.6
The External Bus Controller EBC
The Address Window Selection Registers ADDRSELx
Each chip select signal is associated with an ADDRSEL register.
9.3.6.1
Registers ADDRSELx
ADDRSELx (x = 1-4)
Address Range/Size for CSx XSFR (EE16H + x*8/--)
ADDRSEL7
Address Range/Size for CS7
XSFR (EE4EH/--)
15
14
13
12
11
10
9
8
7
6
Reset Value: 0000H
Reset Value: 0000H
5
4
3
2
1
RGSAD
RGSZ
rw
rw
Field
Bits
Type
Description
RGSAD
[15:4]
rw
Address Range Start Address Selection
RGSZ
[3:0]
rw
Address Range Size Selection (see Table 9-4)
0
Note: There is no register ADDRSEL0, as register set FCONCS0/TCONCS0 controls all
external accesses outside the address windows built by the enabled (by ENCS bit
in FCONCSx) address selects ADDRSELx. The register ADDRSEL4 controls the
chip select CS4, that is available only in the 144-pin package.
9.3.6.2
Definition of Address Areas
The enabled register sets FCONCSx/TCONCSx/ADDRSELx (x = 1 … 4, 7) define
separate address areas within the address space of the XC2000. Within each of these
address areas the conditions of external accesses and LXBus accesses (x = 7) can be
controlled separately, whereby the different address areas (windows) are defined by the
ADDRSELx registers. Each ADDRSELx register cuts out an address window, where the
corresponding parameters of the registers FCONCSx and TCONCSx are used to control
external accesses. The range start address of such a window defines the most
significant address bits of the selected window which are consequently not needed to
address the memory/module in this window (Table 9-4). The size of the window chosen
by ADDRSELx.RGSZ defines the relevant bits of ADDRSELx.RGSAD (marked with ‘R’)
which are used to select with the most significant bits of the request address the
corresponding window. The other bits of the request address are used to address the
memory locations inside this window. The lower bits of ADDRSELx.RGSAD (marked ‘x’)
are disregarded.
User’s Manual
EBC_X8, V1.0d1
9-22
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
The External Bus Controller EBC
The address area from 00’8000H to 00’FFFFH (32 Kbytes) is reserved for CPU internal
registers and data RAM, the area from BF’0000H to BF’7FFFH (32 Kbytes) for internal
startup memory and the area from C0’0000H to FF’FFFFH (4 Mbytes) is used by the
internal program memory. Therefore, these address areas cannot be used by external
resources connected to the external bus.
Table 9-4
Address Range and Size for ADDRSELx
ADDRSELx
Address Window
Range
Size
RGSZ
Relevant (R) Bits
of RGSAD
Selected
Address
Range
Range Start Address A[23:0]
Selected with R-bits of RGSAD
3…0
15 … 4
Size
A23 … A0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
11xx
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRx
RRxx
Rxxx
xxxx
4 Kbytes
8 Kbytes
16 Kbytes
32 Kbytes
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
1 Mbytes
2 Mbytes
4 Mbytes
8 Mbytes
reserved1)
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRR0
RR00
R000
----
RRRR
RRRR
RRRR
RRRR
RRRR
RRRx
RRxx
Rxxx
xxxx
xxxx
xxxx
xxxx
xxxx
RRRR
RRRx
RRxx
Rxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
RRRR
RRRR
RRRR
RRRR
RRRR
RRR0
RR00
R000
0000
0000
0000
0000
----
RRRR
RRR0
RR00
R000
0000
0000
0000
0000
0000
0000
0000
0000
----
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
----
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
----
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
----
1) The complete address space of 12 Mbytes can be selected by the default chip select CS0.
Note: The range start address can only be on boundaries specified by the selected
range size according to Table 9-4.
User’s Manual
EBC_X8, V1.0d1
9-23
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9.3.6.3
The External Bus Controller EBC
Address Window Arbitration
For each external access the EBC compares the current address with all address select
registers (programmable ADDRSELx and hard wired address select registers for startup
memory) of enabled windows. This comparison is done in four levels:
Priority 1:
Registers ADDRSELx [x = 2, 4] are evaluated first. A window match with one of these
registers directs the access to the respective external area using the corresponding set
of control registers FCONCSx/TCONCSx and ignoring registers ADDRSELy. An
overlapping of windows of this group will lead to an undefined behaviour.
Priority 2:
A match with registers ADDRSELy [y = 1, 3, 7] directs the access to the respective
external area using the corresponding set of control registers FCONCSy/TCONCSy. An
overlapping of windows of this group will lead to an undefined behaviour. Overlaps with
priority 2 ADDRSELx are only allowed for the (x, y) pairs (2, 1) and (4, 3).
Priority 3:
If there is no match with any address select register (neither the hardware ones nor the
programmable ADDRSEL) the access to the external bus uses the general set of control
registers FCONCS0/TCONCS0 if enabled.
User’s Manual
EBC_X8, V1.0d1
9-24
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9.3.7
The External Bus Controller EBC
Ready Controlled Bus Cycles
In cases, where the response (access) time of a peripheral is not constant, or where the
programmable wait states are not enough, the EBC provides external bus cycles that are
terminated via a READY input signal.
9.3.7.1
General
In such cases during phase E the EBC first counts a programmable number of clock
cycles (1 … 32) and then starts in the last wait cycle to monitor the internal READY line
(see Figure 9-11) to determine the actual end of the current bus cycle. The external
device drives READY active in order to indicate that data has been latched (write cycle)
or is available (read cycle).
The READY pin is generally enabled by setting the bit RDYDIS in EBCMOD0 to ‘0’ in
order to switch the corresponding port pin. Also the polarity of the READY is defined
inside the EBCMOD0 register on the RDYPOL bit.
For a specific address window the READY function is enabled via the RDYEN bit in the
FCONCSx register. With FCONCSx.RDYMOD the READY is handled either in
synchronous or in asynchronous mode (see also Figure 9-11).
When the READY function is enabled for a specific address window, each bus cycle
within this window must be terminated with an active READY signal. Otherwise the
controller hangs until the next reset. This is also the case for an enabled RDYEN but a
disabled READY port pin.
MUX
Async.
0
READY Ext
1
Sync.
1
EBCMOD0.RDYPOL
MUX
0
1
READY Int
FCONCSx.RDYMODx
MCA05383
Figure 9-11 External to Internal READY Conversion
User’s Manual
EBC_X8, V1.0d1
9-25
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9.3.7.2
The External Bus Controller EBC
The Synchronous/Asynchronous READY
The synchronous READY provides the fastest bus cycles, but requires setup and hold
times to be met. The CLKOUT signal should be enabled and may be used by the
peripheral logic to control the READY timing in this case.
The asynchronous READY is less restrictive, but requires one additional wait state
caused by the internal synchronization. As the asynchronous READY is sampled earlier
programmed wait states may be necessary to provide proper bus cycles.
A READY signal (especially asynchronous READY) that has been activated by an
external device may be deactivated in response to the trailing (rising) edge of the
respective command (RD or WR).
Bus Cycle with Active READY
Programmed
phase E
wait states
Bus Cycle Extended via READY
Programmed
phase E
wait states
ALE
RD / WR
Sync. READY
Async. READY
Sampling of READY Input
Not Interesting READY Cycles
MCT05384
Figure 9-12 READY Controlled Bus Cycles
9.3.7.3
Combining the READY Function with Predefined Wait States
Typically an external wait state or READY control logic takes a while to generate the
READY signal when a cycle was started. After a predefined number of clock cycles the
EBC will start checking its READY line to determine the end of the bus cycle.
When using the READY function with so-called ‘normally-ready’ peripherals, it may lead
to erroneous bus cycles, if the READY line is sampled too early. These peripherals pull
their READY output active, while they are idle. When they are accessed, they drive
READY inactive until the bus cycle is complete, then drive it active again. If, however,
the peripheral drives READY inactive a little late, after the first sample point of the
XC2000, the controller samples an active READY and terminates the current bus cycle
User’s Manual
EBC_X8, V1.0d1
9-26
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
The External Bus Controller EBC
too early. By inserting predefined wait states the first READY sample point can be shifted
to a time, where the peripheral has safely controlled the READY line.
9.3.8
Access Control to LXBus Modules
Access control to LXBus is required for accesses to the MultiCAN and USIC module. In
general, accesses to LXBus are not visible on external bus. During LXBus cycles, the
external bus is still enabled, but driven to inactive states (control signals) or switched into
the read mode (busses).
For accesses to MultiCAN and USICs, CS7 and its control registers ADDRSEL7,
TCONCS7, and FCONCS7 are used. The selection of LXBus is controlled with CS7. The
address range, defined in ADDRSEL7, is located in the ’External IO Range’ (range from
20’0000H to 3F’FFFFH). Only for the External IO Range of the total external address
range it is guaranteed, that a read access is executed after a preceding write access.
The value of the bus function control register FCONCS7 is selected according to the
requirements of the MultiCAN and USIC: 16-bit demultiplexed bus, access time
controlled with synchronous READY. This function control is represented by the default
value for FCONCS7 of ’0027H’.
The LXBus cycle timing as controlled with register TCONCS7 the shortest possible
timing using two clock cycles for one bus cycle. But this minimum timing will be
lengthened with waitstate(s) controlled by the MultiCAN/USIC itself with the READY
function. This timing control is controlled by the reset value of TCONCS7 (’0000H’).
User’s Manual
EBC_X8, V1.0d1
9-27
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
9.3.9
The External Bus Controller EBC
External Bus Arbitration
The XC2000 supports multi master systems on the external bus by its external bus
arbitration. This bus arbitration allows an external master to request the external bus.
The XC2000 will release the external bus and will float the data and address bus lines
and force the control signals via pull-ups/downs to their inactive state.
9.3.9.1
Initialization of Arbitration
During reset all arbitration pins are tristate, except pin BREQ which is pulled inactive.
After reset the XC2000 EBC always starts in ‘init mode’ where the external bus is
available but no arbitration is enabled. All arbitration pins are ignored in this state. Other
to the external bus connected XC2000 EBCs assume to have the bus also, so potential
bus conflicts are not resolved. For a multi master system the arbitration should be
initialized first before starting any bus access. The EBC can either be chosen as
arbitration master or as arbitration slave by programming the EBCMOD0 bit SLAVE. The
selected mode and the arbitration gets active by the first setting of the HLDEN bit inside
the CPUs PSW register. Afterwards a change of the slave/master mode is not possible
without resetting the device. Of course for arbitration the dedicated pins have to be
activated by setting EBCMOD0.ARBEN.
9.3.9.2
Arbitration Master Scheme
If the XC2000 EBC is configured as arbitration master, it is default owner of the external
bus, controls the arbitration protocol and drives the bus also during idle phases with no
bus requests. To perform the arbitration handshake a HOLD input allows the request of
the external bus from the arbitration master. When the arbitration master hands over the
bus to the requester this is signaled by driving the hold acknowledge pin HLDA low,
which remains at this level until the arbitration slave frees the bus by releasing its request
on the HOLD input. If the arbitration master is not the owner of the bus it treats the
external bus interface as follows:
•
•
•
•
Address and data bus(es) float to tristate
Command lines are pulled high by internal pull-up devices (RD, WR/WRL,
BHE/WRH)
Address latch control line ALE is pulled low by an internal pull-down device
CSx outputs are pulled high by internal pull-up devices.
In this state the arbitration slave can take over the bus.
If the arbitration master requires the bus again, it can request the bus via the bus request
signal BREQ. As soon as the arbitration master regains the bus it releases the BREQ
signal and drives HLDA to high.
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Preliminary
The External Bus Controller EBC
Not fixed number of cycles (0 … n)
HOLD
HLDA
Earliest Change
BREQ
CSx, WRH
Pull Up
WR/WRL, RD
Not Active Driven
ADD, DATA
High Impedance
BHE
MCT05385
Figure 9-13 Releasing the Bus by the Arbitration Master
Note: Figure 9-13 shows the first possibility for BREQ to get active. The XC2000 will
complete the currently running bus cycle before granting the external bus as
indicated by the broken lines.
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Preliminary
The External Bus Controller EBC
HOLD
HLDA
No BREQ Request
BREQ
Latest Possible Change
CSx, WRH
Pull Up
WR/WRL, RD
Not Active Driven
ADD, BHE
High Impedance
MCT05386
Figure 9-14 Regaining the Bus by the Arbitration Master
Note: The falling BREQ edge shows the last chance for BREQ to trigger the indicated
regain-sequence. Even if BREQ is activated earlier the regain-sequence is
initiated by HOLD going high. Please note that HOLD may also be deactivated
without the XC2000 requesting the bus.
9.3.9.3
Arbitration Slave Scheme
If the EBC is configured as arbitration slave it is by default not owner of the external bus
and has to request the bus first. As long as it has not finished all its queued requests and
the arbitration master is not requesting the bus the arbitration slave stays owner of the
bus. For the description of the signal handling of the handshake see Chapter 9.3.9.2.
For the arbitration slave the hold acknowledge pin HLDA is configured as input.
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Preliminary
9.3.9.4
The External Bus Controller EBC
Bus Lock Function
If an application in a multi master system requires a sequence of undisturbed bus access
it has the possibility (independently of being arbitration slave or master) to lock1) the bus
by setting the PSW bit HLDEN to ‘0’. In this case the locked EBC will not answer to HOLD
requests from other external bus master until HLDEN is set to ‘1’ again. Of course a
locked bus master not owning the bus can request the external bus. If a master and a
slave are requesting the external bus at the same time for several accesses, they toggle
the ownership after each access cycle if the bus is not locked.
9.3.9.5
Direct Master Slave Connection
If one XC2000 is configured as master and the other as slave and both are working on
the same external bus as bus master, they can be connected directly together for bus
arbitration as shown in Figure 9-15. As both EBCs assume after reset to own the
external bus, the ‘slave’ CPU has to be released from reset and initialized first, before
starting the ‘master’ CPU. The other way is to start both systems at the same time but
then both EBC must be configured from internal memory and the PSW.HLDEN bits set
before the first external bus request.
EBC in
Master Mode
EBC in
Slave Mode
HOLD
HOLD
HLDA
HLDA
BREQ
BREQ
MCA05387
Figure 9-15 Connecting two XC2000 Using Master/Slave Arbitration
When multiple (more than two) bus masters (XC2000 or other masters) shall share the
same external resources an additional external bus arbiter logic is required that
determines the currently active bus master and that controls the necessary signal
sequences.
1) It is not allowed to lock the bus by resetting the EBCMOD0.ARBEN bit, as this can lead to bus conflicts.
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Preliminary
9.3.10
The External Bus Controller EBC
Shutdown Control
In case of a shutdown request from the SCU it must be insured by the EBC that all the
different functions of the EBC are in a non-active state before the whole chip is switched
in a Idle, Powerdown, Sleep or Software Reset mode. A running bus cycle is finished,
still requested bus cycles are executed. Depending on the master/slave configuration of
EBC, the external bus arbiter is controlled for regaining the bus (master) before
performing the requested cycles, or the external bus must be released after complete
execution of still requested bus cycles (see Table 9-5). Only when this shutdown
sequence is terminated, the shutdown acknowledge is generated from EBC (and from
other modules, as described for SCU) and the chip can enter the requested mode.
Table 9-5 gives an overview of the shutdown control in EBC depending on the EBC
configuration.
Table 9-5
EBC Shutdown Control
Arbitration
Mode
Master Mode
Slave Mode
Bus Control With Control of Without
the Bus
Control of the
Bus
With Control of Without
the Bus
Control of the
Bus
–
Finish all
pending
requests.
Send shutdown
acknowledge
after leaving the
bus.
Finish all
pending cycle
requests.
Send shutdown
acknowledge
with the control
of the bus.
User’s Manual
EBC_X8, V1.0d1
Ask for the bus.
Finish all
pending cycle
requests.
Send shutdown
acknowledge
with the control
of the bus.
9-32
Ask for the bus if
needed and
finish all
requests.
Send shutdown
acknowledge
after leaving the
bus.
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Preliminary
9.4
The External Bus Controller EBC
LXBus Access Control and Signal Generation
To connect on-chip peripherals via the EBC, the local system bus LXBus is provided.
The LXBus is an internal (local) extension of the external bus. It is controlled by the
External Bus Controller EBC identically to the external bus, using the select and cycle
control functions as described for the external bus. The address range and chip select
control with ADDRSELn registers, the function control with FCONCSn registers and the
timing control with TCONCSn registers is identical to the external bus. Chip selects
CS5 … CS7 are reserved for LXBus peripherals. In XC2000, only one standard CSx, the
CS7 is used for the LXBus, necessary for the MultiCAN and USIC modules (see
Chapter 9.3.8). Per default, the address range of this peripheral is located within the socalled ‘External IO Range’ (from 20’0000H to 3F’0000H). Accesses to the IO range are
not buffered and not cached, and a read access is delayed until all IO writes pending in
the pipeline are executed.
Only internal accesses to LXBus peripherals are supported by the EBC. External
accesses are not supported in this C166SV2 derivative. Accesses to LXBus peripherals
and memories are not visible on external bus pads.
9.5
EBC Register Table
Table 9-6 lists all EBC Configuration Registers which are implemented in the XC2000
ordered by their physical address. The registers are all located in the XSFR space
(internal IO space).
Table 9-6
EBC Memory Table (ordered by physical address)
Name
Physical Description
Address
Reset
Value1)
EBCMOD0
EE00H
EBC Mode Register 0
5000H
EBCMOD1
EE02H
EBC Mode Register 1
003FH
TCONCS0
EE10H
CS0 Timing Configuration Register
7C3DH
FCONCS0
EE12H
CS0 Function Configuration Register
0011H
TCONCS1
EE18H
CS1 Timing Configuration Register
0000H
FCONCS1
EE1AH
CS1 Function Configuration Register
0000H
ADDRSEL1
EE1EH
CS1 Address Size and Range Register
0000H
TCONCS2
EE20H
CS2 Timing Configuration Register
0000H
FCONCS2
EE22H
CS2 Function Configuration Register
0000H
ADDRSEL2
EE26H
CS2 Address Size and Range Register
0000H
TCONCS3
EE28H
CS3 Timing Configuration Register
0000H
FCONCS3
EE2AH
CS3 Function Configuration Register
0000H
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Preliminary
Table 9-6
The External Bus Controller EBC
EBC Memory Table (ordered by physical address) (cont’d)
Name
Physical Description
Address
Reset
Value1)
ADDRSEL3
EE2EH
CS3 Address Size and Range Register
0000H
TCONCS4
EE30H
CS4 Timing Configuration Register
0000H
FCONCS4
EE32H
CS4 Function Configuration Register
0000H
ADDRSEL4
EE36H
CS4 Address Size and Range Register
0000H
TCONCS7
EE48H
CS7 Timing Configuration Register
0000H
FCONCS7
EE4AH
CS7 Function Configuration Register
0027H
ADDRSEL7
EE4EH
CS7 Address Size and Range Register
2003H
reserved
EE50H
EEFFH
reserved - do not use
–
1) NOTE: Reserved (and not listed) addresses are always read as FFFFH. However, for enabling future
enhancements without any compatibility problems, these addresses should neither be written nor be used as
read value by the software.
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Preliminary
10
Startup Configuration and Bootstrap Loading
Startup Configuration and Bootstrap Loading
After start-up, the XC2000 executes code out of an on-chip or off-chip program memory.
The initial code source can be selected via hardware configuration (i.e. defined levels on
specific pins):
•
•
•
Internal Start Mode: executes code out of the on-chip program Flash.
External Start Mode: executes code out of an off-chip memory connected to the
External Bus Interface.
Bootstrap Loading Modes: execute code out of the on-chip program SRAM
(PSRAM). This code is downloaded beforehand via a selectable serial interface.
10.1
Start-Up Mode Selection
After any device start-up the currently valid start-up configuration is indicated in bitfield
HWCFG of register SCU_STSTAT. Table 10-1 summarizes the defined start up modes.
A start-up configuration can be selected in two ways:
•
•
Via an externally applied hardware configuration upon a Power-on or Internal
Application reset
The hardware configuration is applied to Port 10 pins (P10.[3:0]).
The hardware that activates a startup configuration during reset may be simple pull
resistors for systems that use this feature upon every reset. You may want to use a
switchable solution (via jumpers or an external signal) for systems that only
temporarily use a hardware configuration.
By executing the following software sequence (using register SCU_SWRSTCON,
described in Section 6.2.10.2):
– Write respective configuration value (refer to Table 10-1) to bitfield SWCFG;
– Set Software Boot Configuration bit: SWBOOT = 1;
– Trigger a software reset by activating Software Reset Request: SWRSTREQ = 1.
Note: After an Application reset the hardware configuration from P10 will not be
evaluated, but the same configuration will be used as upon the previous reset.
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Preliminary
Table 10-1
Startup Configuration and Bootstrap Loading
XC2000 Start-Up Mode Configuration
Start-Up Mode
STSTAT.HWCFG
Value 1)
Configuration Pins
P10.[3:0] 2)
Internal Start from Flash
0000’0011B
x
x
1
1
Standard UART Bootloader mode
0000’0110B
x
1
1
0
CAN Bootloader mode
0000’0101B
x
1
0
1
SSC Bootloader mode
0000’1001B
1
0
0
1
External Start
0000’0000B
0
0
0
0
1) Bitfield HWCFG can be loaded from Port 10 or from bitfield SWCFG in register SWRSTCON.
2) x means that the level on the corresponding pin is irrelevant.
10.2
Internal Start
When internal start mode is configured, the XC2000 immediately begins executing code
out of the on-chip Flash memory (first instruction from location C0’0000H).
No additional configuration options are required, when selecting internal startup mode.
Note: Because internal start mode is expected to be the configuration used in most
cases, this mode can be selected by pulling high just 2 pins.
10.3
External Start
When external start mode is configured, the XC2000 begins executing code out of an
off-chip memory (first instruction from location 00’0000H), connected to the XC2000’s
external bus interface.
The External Bus Controller is adjusted to the employed external memory by evaluating
additional configuration pins.
Seven pins of P10 are used to select the EBC mode (P10.[10:8]), the address width
(P10.[12:11]), and the number of chip select lines (P10.[14:13]). The following tables
summarize the available options.
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Preliminary
Table 10-2
Startup Configuration and Bootstrap Loading
EBC Configuration: EBC Mode
EBC Startup Mode
Cfg. Pins
P10[10:8]
Pins Used by the EBC
8-Bit Data, Multiplexed
0
0
0
P2.0 … P2.2, P10.0 … P10.15
8-Bit Data, Demultiplexed
0
0
1
P0.0 … P0.7, P1.0 … P1.7, P2.0 … P2.2,
P10.0 … P10.7, P10.13, P10.14
16-Bit Data, MUX, BHE mode 0
1
0
P2.0 … P2.2, P2.11, P10.0 … P10.15
16-Bit Data, MUX, WRH mode 0
1
1
P2.0 … P2.2, P2.11, P10.0 … P10.15
16-Bit Data, DeMUX,
BHE mode, A0
1
0
0
P0.0 … P0.7, P1.0 … P1.7, P2.0 … P2.2,
P2.11, P10.0 … P10.14
16-Bit Data, DeMUX,
WRH mode, A0
1
0
1
P0.0 … P0.7, P1.0 … P1.7, P2.0 … P2.2,
P2.11, P10.0 … P10.14
16-Bit Data, DeMUX,
BHE mode, A1
1
1
0
P2.0 … P2.2,
P10.0 … P10.15
16-Bit Data, DeMUX,
WRH mode, A1
1
1
1
P0.0 … P0.7, P1.0 … P1.7, P2.0 … P2.2,
P10.0 … P10.7, P10.13, P10.14
Table 10-3
EBC Configuration: Address Width
Available Address Lines
Cfg. Pins Additional Address Pins
P10[12:11]
A15 … A0
0
0
None
A17 … A0
0
1
P2.3, P2.4
A19 … A0
1
0
P2.3 … P2.6
A23 … A0
1
1
P2.3 … P2.10
Table 10-4
EBC Configuration: Chip Select Lines
Available Chip Select Lines Cfg. Pins Used Pins
P10[14:13]
CS0 … CS4
0
0
P4.0 … P4.4
CS0
0
1
P4.0
CS0 … CS1
1
0
P4.0, P4.1
None
1
1
None
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Preliminary
10.4
Startup Configuration and Bootstrap Loading
Bootstrap Loading
Bootstrap Loading is the technique of transferring code to the XC2000 via a certain
interface (usually serial) before the regular code execution out of non-volatile program
memory commences. Instead, the XC2000 executes the previously received code.
This boot-code may be complete (e.g. temporary software for testing or calibration),
amend existing code in non-volatile program memory (e.g. with product-specific data or
routines), or load additional code (e.g. using higher or more secure protocols). A possible
application for bootstrap loading is the programming of virgin Flash memory at the end
of a production line, with no external memory or internal Flash required for the
initialization code.
The BSL mechanism may be used for standard system startup as well as only for special
occasions like system maintenance (firmware update) or end-of-line programming or
testing.
The XC2000 supports bootstrap loading using several protocols/modes:
•
•
•
Standard UART protocol, loading 32 bytes (see Section 10.4.2)
Synchronous serial protocol (see Section 10.4.3)
CAN protocol (see Section 10.4.4)
For a summary of these modes, see also Table 10-10
10.4.1
General Functionality
Even though each bootstrap loader has its particular functionality, the general handling
is the same for all of them.
Entering a Bootstrap Loader
Bootstrap loaders are enabled by selecting a specific start-up configuration (see
Section 10.1).
The required configuration patterns are described in Table 10-10 for the bootstrap
loaders, and are summarized in Table 10-1.
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Preliminary
Startup Configuration and Bootstrap Loading
Loading the Startup Code
After establishing communication, the BSL enters a loop to receive the respective
number of bytes. These bytes are stored sequentially into the on-chip PSRAM, starting
at location E0’0000H. To execute the loaded code the BSL then points register VECSEG
to location E0’0000H, i.e. the first loaded instruction, and then jumps to this instruction.
The loaded code may be the final application code or another, more sophisticated,
loader routine that adds a transmission protocol to enhance the integrity of the loaded
code or data. It may also contain a code sequence to change the system configuration
and enable the bus interface to store the received data into external memory.
This process may go through several iterations or may directly execute the final
application.
Note: Data fetches from a protected Flash will not be executed.
Exiting Bootstrap Loader Mode
After the bootstrap loader has been activated, the watchdog timer and the debug system
are disabled. Watchdog timer and debug system are released automatically when the
BSL terminates after having received the last byte from the host.
If 2nd level loaders are used, the loader routine should deactivate the watchdog timer via
instruction DISWDT to allow for an extended download period.
After a non-BSL reset the XC2000 will start executing out of user memory as externally
configured.
Interface to the Host
The bootstrap loader communicates with the external host over a predefined set of
interface pins. These interface pins are automatically enabled and controlled by the
bootstrap loader. The host must connect to these predefined interface pins.
Table 10-10 indicates the interface pins that are used in each bootstrap loader mode.
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10.4.2
Startup Configuration and Bootstrap Loading
Standard UART Bootstrap Loader
The standard UART bootstrap loader transfers program code/data via channel 0 of
USIC0 (U0C0) into the PSRAM. The U0C0 receiver is only enabled after the
identification byte has been transmitted. A half duplex connection to the host is,
therefore, sufficient to feed the BSL.
Data is transferred from the external host to the XC2000 using asynchronous eight-bit
data frames without parity (1 start bit, 1 stop bit). The number of data bytes to be received
in standard UART boot mode is fixed to 32 bytes, which allows for up to 16 two-byte
instructions.
Reset
CONFIG.
PINS
RxD
TxD
CSP:IP
Internal BSL-Routine
32 bytes
User Software
mc_bsl_x2k.vsd
Figure 10-1 Bootstrap Loader Sequence
After entering UART BSL mode and the respective initialization the XC2000 scans the
RxD line to receive a zero byte, i.e. one start bit, eight 0 data bits and one stop bit. From
the duration of this zero byte it calculates the corresponding baudrate factor with respect
to the current CPU clock, initializes the serial interface U0C0 accordingly and switches
pin TxD to output. Using this baudrate, an identification byte (D5H) is returned to the host
that provides the loaded data.
After sending the identification byte the BSL enters a loop to receive 32 Bytes via U0C0.
These bytes are stored sequentially into locations E0’0000H through E0’001FH of the
internal PSRAM and then executed.
Note: For loading more code, e.g. via a 2nd-level loader, see also Section 10.4.2.2.
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Preliminary
Startup Configuration and Bootstrap Loading
10.4.2.1 Specific Settings
When the XC2000 has entered the Standard UART BSL mode, the following
configuration is automatically set:
Table 10-5
UART BSL-Specific State
Item
Value
Comments
U0C0_CCR
0002H
ASC mode selected for USIC0 Channel 0
U0C0_PCRL
0401H
1 stop bit, three RxD-samples at point 4
U0C0_SCTRL
0002H
Passive data level = 1
U0C0_SCTRH
0707H
8 data bits
U0C0_PDIV
XXXXH
Measured value (zero-byte)
U0C0_FDRL
43FFH
Normal divider mode 1:1 selected
U0C0_BRGL
1C00H
Normal mode, FDIV, 8 clocks/bit
U0C0_DX0CR
0003H
Data input selection
P7_IOCR03
00B0H
P7.3 is push/pull output (TxD)
P7_IOCR04
0020H
P7.4 is input with pull-up (RxD)
DPP1
0081H
Points to USIC0 base address 1)
R0
4044H
Pointer to U0C0_PSR 1)
R1
4048H
Pointer to U0C0_PSCR 1)
R2
405CH
Pointer to U0C0_RBUF 1)
R3
4000H
Mask to clear RIF 1)
1) This register setting is provided for a 2nd-level loader routine (see Section 10.4.2.2).
The identification byte identifies the device to be booted. The following codes are
defined:
55H: 8xC166.
A5H: Previous versions of the C167 (obsolete).
B5H: Previous versions of the C165.
C5H: C167 derivatives.
D5H: All devices equipped with identification registers (including the XC2000).
Note: The identification byte D5H does not directly identify a specific derivative. This
information can, in this case, be obtained from the identification registers.
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Preliminary
Startup Configuration and Bootstrap Loading
10.4.2.2 Second Level Bootloader
Most probably the initially loaded routine will load additional code or data, as an average
application is likely to require substantially more instructions than could fit into 32 Bytes.
This second receive loop may directly use the pre-initialized interface U0C0 to receive
data and store it to arbitrary user-defined locations.
The example code below shows how to fit such a 2nd-level loader into the available 32
bytes. This is possible due to the pre-initialized serial channel and the pre-set registers
(see Table 10-5).
;Example for Secondary UART Bootstrap Loader Routine
;--------------------------------------------------------------TargetStart LIT ’0E00020H’
;Definition of target area:
TargetEnd
LIT ’0E001FFH’
;480 bytes in this example
StartOfCode LIT ’0E00100H’
;Continue executing here...
;...after download
Level2Loader:
DISWDT
;No WDT for further download
MOV
DPP0,#(PAG TargetStart)
MOV
R10, #(DPP0:TargetStart);Set pointer to target area
Level2MainLoop:
MOV
[R1],R3
;Clear RIF for new byte
Level2RecLoop:
MOV
R4, [R0]
;Access PSR
JNB
R4.14,Level2RecLoop
;Wait for RIF
MOVB [R10],[R2]
;Copy new byte to target
CMPI1 R10, #POF (TargetEnd);All bytes received??
JMPR cc_NE,Level2MainLoop ;Repeat for complete area
Level2Terminate:
JMPS
SEG StartOfCode, SOF StartOfCode
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Preliminary
Startup Configuration and Bootstrap Loading
10.4.2.3 Choosing the Baudrate for the BSL
The calculation of the serial baudrate for U0C0 from the length of the first zero byte that
is received, allows the operation of the bootstrap loader of the XC2000 with a wide range
of baudrates. However, the upper and lower limits have to be kept, in order to ensure
proper data transfer.
The XC2000 uses bitfield PDIV to measure the length of the initial zero byte. The
quantization uncertainty of this measurement implies the deviation from the real
baudrate.
For a correct data transfer from the host to the XC2000 the maximum deviation between
the internal initialized baudrate for U0C0 and the real baudrate of the host should be
below 2.5%. The deviation (FB, in percent) between host baudrate and XC2000 baudrate
can be calculated via Equation (10.1):
B Contr – B Host
F B = ------------------------------------ × 100%
B Contr
F B ≤ 2.5%
(10.1)
Note: Function (FB) does not consider the tolerances of oscillators and other devices
supporting the serial communication.
This baudrate deviation is a nonlinear function depending on the system clock and the
baudrate of the host. The maxima of the function (FB) increase with the host baudrate
due to the smaller baudrate prescaler factors and the implied higher quantization error
(see Figure 10-2).
Ι
FB
2.5%
B Low
B High
B Host
ΙΙ
MCA02260
Figure 10-2 Baudrate Deviation between Host and XC2000
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Startup Configuration and Bootstrap Loading
The minimum baudrate (BLow in Figure 10-2) is determined by the maximum count
capacity of bitfield PDIV, when measuring the zero byte, i.e. it depends on the system
clock. The minimum baudrate is obtained by using the maximum PDIV count 210 in the
baudrate formula. Baudrates below BLow would cause PDIV to overflow. In this case
U0C0 cannot be initialized properly and the communication with the external host is likely
to fail.
The maximum baudrate (BHigh in Figure 10-2) is the highest baudrate where the
deviation still does not exceed the limit, i.e. all baudrates between BLow and BHigh are
below the deviation limit. BHigh marks the baudrate up to which communication with the
external host will work properly without additional tests or investigations.
Higher baudrates, however, may be used as long as the actual deviation does not
exceed the indicated limit. A certain baudrate (marked I) in Figure 10-2) may e.g. violate
the deviation limit, while an even higher baudrate (marked II) in Figure 10-2) stays very
well below it. Any baudrate can be used for the bootstrap loader provided that the
following three prerequisites are fulfilled:
•
•
•
the baudrate is within the specified operating range for U0C0
the external host is able to use this baudrate
the computed deviation error is below the limit.
Note: When the bootstrap loader mode is entered after a power reset, the bootstrap
loader will begin to operate with fSYS = fIOSC × 2 (approximately 10 MHz) which will
limit the maximum baudrate for U0C0.
Higher levels of the bootstrapping sequence can then switch the clock generation
mode in order to achieve higher baudrates for the download.
User’s Manual
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V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
10.4.3
Startup Configuration and Bootstrap Loading
Synchronous Serial Channel Bootstrap Loader
The Synchronous Serial Channel (SSC) bootstrap loader transfers program code/data
from an external serial EEPROM via channel 0 of USIC0 (U0C0) into the PSRAM. The
XC2000 is the master, so no additional elements (except for the EEPROM) are required.
Data is transferred from the external EEPROM to the XC2000 using synchronous eightbit data frames with MSB first. The number of data bytes to be received in SSC boot
mode is user-selectable. The serial clock rate is set to fSYS/10, which results in 1 MHz
after a power reset.
After entering SSC BSL mode and the respective initialization, the XC2000 first reads
the header from the first addresses (00...0) of the target EEPROM.
This header consists of two items:
•
•
The memory identification Byte: D5H
The data size field: 1 byte or 2 bytes, depending on the EEPROM’s addressing mode
(8-bit or 16-bit, see Section 10.4.3.1)
If both items are valid the BSL enters a loop to read the number of bytes defined by the
data size field (maximum is FFH or FF00H, depending on the EEPROM) via U0C0.
These bytes are stored sequentially into PSRAM starting at location E0’0000H and are
then executed. Therefore, the size of the PSRAM in the respective derivative determines
the real maximum block size to be downloaded.
An invalid header (identification byte ≠ D5H, data size field = 0 or greater than
65280/FF00H) is indicated by toggling the CS line low 3 times. This helps debugging
during the system setup phase.
User’s Manual
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V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Startup Configuration and Bootstrap Loading
10.4.3.1 Supported EEPROM Types
The XC2000’s SSC bootstrap loader assumes an SPI-compatible EEPROM (25xxx
series). It supports devices with 8-bit addressing as well as with 16-bit addressing. The
connected EEPROM type is determined by examining the received header bytes, as
indicated in Table 10-6.
Table 10-6
Determining the EEPROM Type
SSC Frame
Number
Meaning of
Transmitted Data
Received Data from
8-bit Addr. Device
Received Data from
16-bit Addr. Device
1
03H: Read command
XXH (default level)
XXH (default level)
2
00H: Address byte
(high for 16-bit addr.)
XXH (default level)
XXH (default level)
3
00H: Address byte low
Identification Byte
XXH (default level)
4
00H: Dummy byte
Size field
Identification Byte
5
00H: Dummy byte
Data byte 1
Size field, high Byte
6
00H: Dummy byte
Data byte 2
Size field, low Byte
7
00H: Dummy byte
Data byte 3
Data byte 1
…
00H: Dummy byte
Data byte 4 … n
Data byte 2 … n
Note: The value of the returned default bytes (indicated as XXH) depends on the
employed EEPROM type.
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Startup Configuration and Bootstrap Loading
10.4.3.2 Specific Settings
When the XC2000 has entered the SSC BSL mode, the following configuration is
automatically set:
Table 10-7
SSC BSL-Specific State
Item
Value
Comments
U0C0_CCR
0001H
SSC mode selected for USIC0 Channel 0
U0C0_PCRL
0011H
SSC master mode, frequency from fPPP
U0C0_PCRH
8000H
MCLK generation is enabled
U0C0_SCTRL
0103H
MSB first, passive data level=1
U0C0_SCTRH
073FH
8 data bits, infinite frame
U0C0_DX0CR
0015H
Data input selection
U0C0_FDRL
43FFH
Normal divider mode 1:1 selected
U0C0_BRGL
0000H
Normal mode, FDIV - default value after reset
U0C0_BRGH
8004H
Passive levels MCLK/SCLK=0, PDIV=4
P2_IOCR03
00D0H
P2.3 is open-drain output (MTSR)
P2_IOCR04
0020H
P2.4 is input with pull-up (MRST)
P2_IOCR05
00D0H
P2.5 is open-drain output (SCLK)
P2_IOCR06
00C0H
P2.6 is open-drain output (SLS)
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XC2000 Derivatives
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Preliminary
10.4.4
Startup Configuration and Bootstrap Loading
CAN Bootstrap Loader
The CAN bootstrap loader transfers program code/data via node 0 of the MultiCAN
module into the PSRAM. Data is transferred from the external host to the XC2000 using
eight-byte data frames. The number of data frames to be received is programmable and
determined by the 16-bit data message count value DMSGC.
The communication between XC2000 and external host is based on the following three
CAN standard frames:
•
•
•
Initialization frame - sent by the external host to the XC2000
Acknowledge frame - sent by the XC2000 to the external host
Data frame(s) - sent by the external host to the XC2000
The initialization frame is used in the XC2000 for baud rate detection. After a successful
baud rate detection is reported to the external host by sending the acknowledge frame,
data is transmitted using data frames. Table 10-8 shows the parameters and settings for
the three utilized CAN standard frames.
Note: The CAN bootstrap loader requires a point-to-point connection with the host, i.e.
the XC2000 must be only CAN node connected to the network. A crystal with at
least 4 MHz is required for CAN bootstrap loader operation.
Initialization Phase
The first task is to determine the CAN baud rate at which the external host is
communicating. This task requires the external host to send initialization frames
continuously to the XC2000. The first two data bytes of the initialization frame include a
2-byte baud rate detection pattern (5555H), an 11-bit (2-byte) identifier ACKID1) for the
acknowledge frame, a 16-bit data message count value DMSGC, and an 11-bit (2-byte)
identifier DMSGID1) to be used by the data frame(s).
The CAN baud rate is determined by analyzing the received baud rate detection pattern
(5555H) and the baud rate registers of the MultiCAN module are set accordingly. The
XC2000 is now ready to receive CAN frames with the baud rate of the external host.
Acknowledge Phase
In the acknowledge phase, the bootstrap loader waits until it receives the next correctly
recognized initialization frame from the external host, and acknowledges this frame by
generating a dominant bit in its ACK slot. Afterwards, the bootstrap loader transmits an
acknowledge frame back to the external host, indicating that it is now ready to receive
data frames. The acknowledge frame uses the message identifier ACKID that has been
received with the initialization frame.
1) The CAN bootstrap loader copies the two identifier bytes received in the initialization frame directly to register
MOAR. Therefore, the respective fields in the initialization frame must contain the intended identifier padded
with two dummy bits at the lower end and extended with bitfields IDE (=0B) and PRI (=01B) at the upper end.
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System Units (Vol. 1 of 2)
Preliminary
Startup Configuration and Bootstrap Loading
Data Transmission Phase
In the data transmission phase, data frames are sent by the external host and received
by the XC2000. The data frames use the 11-bit data message identifier DMSGID that
has been sent with the initialization frame. Eight data bytes are transmitted with each
data frame. The first data byte is stored in PSRAM at E0’0000H. Consecutive data bytes
are stored at incrementing addresses.
Both communication partners evaluate the data message count DMSGC until the
requested number of CAN data frames has been transmitted. After the reception of the
last CAN data frame, the bootstrap loader finishes and executes the loaded code.
Timing Parameters
There are no general restrictions for CAN timings of the external host. During the
initialization phase the external host transmits initialization frames. If no acknowledge
frame is sent back within a certain time as defined in the external host (e.g. after a
dedicated number of initialization frame transmissions), the external host can decide that
the XC2000 is not able to establish the CAN boot communication link.
Table 10-8
CAN Bootstrap Loader Frames
Frame Type
Parameter
Description
Initialization
Frame
Identifier
11-bit, don’t care
DLC = 8
Data length code, 8 bytes within CAN frame
Data bytes 0/1
Baud rate detection pattern (5555H)
Data bytes 2/3
Acknowledge message identifier ACKID
(complete register contents)
Data bytes 4/5
Data message count DMSGC, 16-bit
Data bytes 6/7
Data message identifier DMSGID
(complete register contents)
Acknowledge Identifier
Frame
Acknowledge message identifier ACKID as received
by data bytes [3:2] of the initialization frame
DLC = 4
Data length code, 4 bytes within CAN frame
Data bytes 0/1
Contents of bit-timing register
Data bytes 2/3
Copy of acknowledge identifier from initialization frame
Data frame
Identifier
Data message identifier DMSGID as sent by data
bytes [7:6] of the initialization frame
DLC = 8
Data length code, 8 bytes within CAN frame
Data bytes
0 to 7
Data bytes, assigned to increasing destination
(PSRAM) addresses
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Startup Configuration and Bootstrap Loading
10.4.4.1 Specific Settings
When the XC2000 has entered the CAN BSL mode, the following configuration is
automatically set:
Table 10-9
CAN BSL-Specific State
Item
Value
Comments
P2_IOCR05
00A0H
P2.5 is push/pull output (TxD)
P2_IOCR06
0020H
P2.6 is input with pull-up (RxD)
SCU_HPOSCCON
0030H
OSC_HP enabled, External Crystal/Clock mode
SCU_SYSCON0
0001H
OSC_HP selected as system clock
CAN_MOCTR0L
0008H
Message Object 0 Control, low
CAN_MOCTR0H
00A0H
Message Object 0 Control, high
CAN_MOCTR1L
0000H
Message Object 1 Control, low
CAN_MOCTR1H
0F28H
Message Object 1 Control, high
CAN_MOFCR1H
0400H
Message Object Function Control, high
CAN_MOAMR0H
1FFFH
Message Object 0 - Acceptance Mask bit set
CAN_NPCR0
0003H
Data input selection
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
10.4.5
Startup Configuration and Bootstrap Loading
Summary of Bootstrap Loader Modes
This table summarizes the external hardware provisions that are required to activate a
bootstrap loader in a system.
Table 10-10 Configuration Data for Bootstrap Loader Modes
Bootstrap Loader Configuration Receive Line
on P10.3-01)
Mode
from Host
Transmit Line
to Host
Transferred
Data
Standard UART
x110B
RxD = P7.4
TxD = P7.3
32 Bytes
Sync. Serial
1001B
MRST = P2.4
MTSR = P2.3
SCLK = P2.5
SLS = P2.6
n Bytes;
1 … 65,280
MultiCAN
x101B
RxDC0 = P2.6
TxDC0 = P2.5
8 × n Bytes
1) x means that the level on the corresponding pin is irrelevant.
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Preliminary
User’s Manual
SCFG/BSL, V1.0
Startup Configuration and Bootstrap Loading
10-18
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
11
Debug System
Debug System
The XC2000 includes an On-Chip Debug Support (OCDS) system, which provides
convenient debugging, controlled directly by an external device via debug interface pins.
On-Chip Debug Support (OCDS)
The OCDS system supports a broad range of debug features including setting up
breakpoints and tracing memory locations. Typical application of OCDS is to debug the
user software running on the XC2000 in the customer’s system environment.
The OCDS system is controlled by an external debugging device via the Debug
Interface, including an independent JTAG interface and a break interface (Figure 11-1).
The debugger manages the debugging tasks through a set of OCDS registers accessible
via the JTAG interface, and through a set of special debug IO instructions. Additionally,
the OCDS system can be controlled by the CPU, e.g. by the monitor program. The
OCDS system interacts with the core through an injection interface to allow execution of
Cerberus-generated instructions, and through a break port.
OCDS System
Trace Interface
Break Interface
break_in
OCDS
Module
break_out
CPU
Debugger
JTAG Interface
Debug
Interface
JTAG
Module
Cerberus
(IO Module)
Injection Interface
CPU Status
Controller
Other
Resources
MCA05388
Figure 11-1 OCDS Overall Structure
The OCDS system functions are represented and controlled by the Debug Interface, the
OCDS Module and by the debug IO control module (Cerberus) which provides all the
functionality necessary to interact between the debug interface (the external debugger)
and the internal system.
User’s Manual
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XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Debug System
The OCDS system provides the following basic features:
•
•
•
•
•
•
•
•
Hardware, software and external pin breakpoints
Reaction on break with CPU-Halt, monitor call, data transfer and external signal
Read/write access to the whole address space
Single stepping
Debug Interface pins for JTAG interface and break interface
Injection of arbitrary instructions
Fast memory tracing through transfer to external bus
Analysis and status registers
11.1
Debug Interface
The Debug Interface is a channel to access XC2000 On-Chip Debug Support (OCDS)
resources. Through it data can be transferred to/from all on- and off-chip (if any)
memories and control registers.
Features and Functions
•
•
•
•
•
Independent interface for On-Chip Debug Support (OCDS)
JTAG port based on the IEEE 1149 JTAG standard
Break interface for external trigger and indication of breaks
Generic memory access functionality
Independent data transfer channel for e.g. programming of on-chip non volatile
memory
The Debug Interface is represented by:
• Standard JTAG Interface
• Two additional XC2000 specific signals - OCDS Break-Interface
JTAG Interface
The JTAG interface is a standardized and dedicated port usually used for boundary scan
and for chip internal tests. Because both of these applications are not enabled during
normal operation of the device in a system, the JTAG port is an ideal interface for
debugging tasks.
This interface holds the JTAG IEEE.1149-standard signals:
•
•
•
•
•
TDI - Serial data input
TDO - Serial data output
TCK - JTAG clock
TMS - State machine control signal
TRST - Reset/Module enable
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XC2000 Derivatives
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Preliminary
Debug System
OCDS Break-Interface
Two additional signals are used to implement a direct asynchronous-break channel
between the Debugger and XC2000 OCDS Module:
• BRKIN (BReaK IN request) allows the Debugger asynchronously to interrupt the CPU
and force it to a predefined status/action.
• BRKOUT (BReaK OUT signal) can be activated by OCDS to notify the external world
that some predefined debug event has happened, while not interrupting the CPU and
using its pin(s).
11.1.1
Routing of Debug Signals
The signals used to connect an external debugger via the JTAG interface and the break
interface usually conflict with the requirements of the application, which needs as many
IOs as possible. In the XC2000, these signals are only provided as alternate functions
(no dedicated pins). To minimize the impact caused by the debug interface pins, these
signals can be mapped to several pins. Thus, each application can select the variant with
the least impact. This is controlled via the Debug Pin Routing Register DBGPRR. Pin
BRKOUT can be assigned to pins P6.0, P10.11, P1.5, or P9.3 as a standard alternate
output signal via the respective IOC register.
11.1.1.1 Register DBGPRR
This register controls the pin mapping of the JTAG pins.
DBGPRR
Debug Pin Routing Register
15
14
13
12
11
10
ESFR (F06EH/37H)
9
8
7
6
Reset Value: 0000H
5
4
3
2
1
0
TRS
TL
0
DPR
BRKIN
DPR
TCK
DPR
TMS
DPR
TDI
DPR
TDO
rh
r
rw
rw
rw
rw
rw
Field
Bits
Type
Description
DPRTDO
[1:0]
rw
Debug Pin Routing for TDO
00
P7.0
01
P10.12
10
Reserved, do not use
11
Reserved, do not use
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Preliminary
Debug System
Field
Bits
Type
Description
DPRTDI
[3:2]
rw
Debug Pin Routing for TDI
00
P5.2
01
P10.10
10
P7.2
11
P8.3
DPRTMS
[5:4]
rw
Debug Pin Routing for TMS
00
P5.4
01
P10.11
10
P7.3
11
P8.4
DPRTCK
[7:6]
rw
Debug Pin Routing for TCK
00
P2.9
01
P10.9
10
P7.4
11
P8.5
DPRBRKIN
[9:8]
rw
Debug Pin Routing for BRKIN
00
P5.10
01
P10.8
10
P7.1
11
P8.6
TRSTL
15
rh
TRST Pin Start-up Value
This bit indicates if the Debug Mode can be entered
or not.
0
A debugger can not be connected
1
A debugger can be connected
0
[14:10] r
User’s Manual
OCDS_X8, V2.2
Reserved
read as 0; should be written with 0.
11-4
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System Units (Vol. 1 of 2)
Preliminary
11.2
Debug System
OCDS Module
The application of OCDS Module is to debug the user software running on the CPU in
the customer’s system. This is done with an external debugger, that controls the OCDS
Module via the independent Debug Interface.
Features
•
•
•
•
•
•
•
Hardware, software and external pin breakpoints
Up to 4 instruction pointer breakpoints
Masked comparisons for hardware breakpoints
The OCDS can also be configured by a monitor
Support of multi CPU/master system
Single stepping with monitor or CPU halt
PC is visible in halt mode (IO_READ_IP instruction injection via Cerberus)
Basic Concept
The on chip debug concept is split up into two parts. The first part covers the generation
of debug events and the second part defines what actions are taken when a debug event
is generated.
• Debug events:
– Hardware Breakpoints
– Decoding of a SBRK Instruction
– Break Pin Input activated
• Debug event actions:
– Halt Mode of the CPU
– Call a Monitor
– Trigger Transfer
– Activate External Pin Output
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System Units (Vol. 1 of 2)
Preliminary
Debug System
Debug Event Sources
Hardware
Triggers
Debug Actions
HALT the CPU
Programmable
Combination
Debug
Event
Processing
CALL a Monitor
SBRK Instruction
Transfer Triggered
Break_In Pin Activated
Break_Out Pin Activated
MCB05389
Figure 11-2 OCDS Concept: Block Diagram
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System Units (Vol. 1 of 2)
Preliminary
11.2.1
Debug System
Debug Events
The Debug Events can come from a few different sources.
Hardware Breakpoints
The Hardware Breakpoint is a debug-event, raised when a single or a combination of
multiple trigger-signals are matching with the programmed conditions.
The following hardware trigger sources can be used:
Table 11-1
Hardware Triggers
Trigger Source
Size
Task Identifier
16 bits
Instruction Pointer
24 bits
Data address of reads (two busses monitored)
2 × 24 bits
Data address of writes
24 bits
Data value (reads or writes)
16 bits
SBRK Instruction
This is a mechanism through which the software can explicitly generate a debug event.
It can be used for instance by a debugger to temporarily patch code held in RAM in order
to implement Software Breakpoints.
A special SBRK (Software BReaK) instruction is defined with opcode 0x8C00. When this
instruction has been decoded and it reaches the Execute stage, the whole pipeline is
canceled including the SBRK itself. Hence in fact the SBRK instruction is never
“executed” by itself.
The further behavior is dependent on how OCDS has been programmed:
• if the OCDS is enabled and the software breakpoints are also enabled, then the CPU
goes into Halt Mode
• if the OCDS is disabled or the software breakpoints are disabled, then the Software
Break Trap (SBRKTRAP) is executed-Class A Trap, number 08H
Break Pin Input
An external debug break pin (BRKIN) is provided to allow the debugger to
asynchronously interrupt the processor.
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Preliminary
11.2.2
Debug System
Debug Actions
When the OCDS is enabled and a debug event is generated, one of the following actions
is taken:
Trigger Transfer
One of the actions that can be specified to occur on a debug event being raised is to
trigger the Cerberus:
• to execute a Data Transfer - this can be used in critical routines where the system
cannot be interrupted to transfer a memory location
• to inject an instruction to the Core - using this mechanism, an arbitrary instruction can
be injected into the XC2000 pipeline
Halt Mode
Upon this Action the OCDS Module sends a Break-Request to the Core.
The Core accepts this request, if the OCDS Break Level is higher than current CPU
priority level. In case a Break-Request is accepted, the system suspends execution with
halting the instruction flow.
The Halt Mode can be still interrupted by higher priority user interrupts. It then relies on
the external debugger system to interrogate the target purely through reading and
updating via the debug interface.
Call a Monitor
One of the possible actions to be taken when a debug event is raised is to call a Monitor
Program.
This short entry to a Monitor allows a flexible debug environment to be defined which is
capable of satisfying many of the requirements for efficient debugging of a real time
system. In the common case the Monitor has the highest priority and can not be
interrupted from any other requesting source.
It is also possible to have an Interruptible Monitor Program. In such a case safety critical
code can be still served while the Monitor (Debugger) is active, which gives a maximum
flexibility to the user.
Activate External Pin
This action activates the external pin BRKOUT of the OCDS Break-Interface. It can be
used in critical routines where the system cannot be interrupted to signal to the external
world that a particular event has happened. The feature could also be useful to
synchronize the internal and external debug hardware.
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Preliminary
11.3
Debug System
Cerberus
Cerberus is the module which provides and controls all the operations necessary to
interact between the external debugger (via the Debug Interface), the OCDS Module
and the internal system of XC2000.
Features
• JTAG interface is used as control and data channel
• Generic memory read/write functionality (RW mode) with access to the whole address
space
• Reading and writing of general-purpose registers (GPRs)
• Injection of arbitrary instructions
• External host controls all transactions
• All transactions are available at normal run time and in halt mode
• Priority of transactions can be configured
• Full support for communication between the monitor and an external host (debugger)
• Optional error protection
• Tracing memory locations through transferring values to the external bus
• Analysis Register for internal bus locking situations
The target application of Cerberus is to use the JTAG interface as an independent port
for On Chip Debug Support. The external debugger can access the OCDS registers and
arbitrary memory locations with the injection mechanism.
11.3.1
Functional Overview
Cerberus is operated by an external debugger across the JTAG Interface. The
Debugger supplies Cerberus IO Instructions and performs bidirectional data-transfers.
The Cerberus distinguishes between two main modes of operation:
Read/Write Mode of Operation
Read/Write (RW) Mode is the most typical way to operate Cerberus. This mode is used
to read and write memory locations or to inject instructions. The injection interface to the
core is actively used in this mode.
In this mode an external Debugger (host), using JTAG Interface, can:
• read and write memory locations from the target system (data-transfer);
• inject arbitrary instructions to be executed by the Core.
All Cerberus IO Instructions can be used in RW mode. The dedicated IO_READ_IP
instruction is provided in RW mode to read the IP of the CPU while in Break.
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Debug System
The access to any memory location is performed with injected instructions, as PEC
transfer. The following Cerberus IO Instructions can be used in their generic meaning:
• IO_READ_WORD, IO_WRITE_WORD
• IO_READ_BLOCK, IO_WRITE_BLOCK
• IO_WRITE_BYTE
Within these instructions, the host writes/reads data to/from a dedicated
register/memory, while the Cerberus itself takes care of the rest: to perform a PEC
transfer by injection of the appropriate instructions to the Core.
Communication Mode of Operation
In this mode the external host (debugger) communicates with a program (Monitor)
running on the CPU. The data-transfers are made via a PDBus+ register. The external
host is master of all transactions, requesting the monitor to write or read a value.
The difference to Read/Write Mode of Operation is that the read or write request now
is not actively executed by the Cerberus, but it sets request bits in a CPU accessible
register to signal the Monitor, that the host wants to send (IO_WRITE_WORD) or receive
(IO_READ_WORD) a value. The Monitor has to poll this status register and perform
respectively the proper actions
Communication Mode is the default mode after reset. Only the IO_WRITE_WORD and
IO_READ_WORD Instructions are effectively used in Communication Mode.
The Host and the Monitor exchange data directly with the dedicated data-register. For a
synchronization of Host (Debugger) and Monitor accesses, there are associated control
bits in a Cerberus status register.
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Preliminary
12
Instruction Set Summary
Instruction Set Summary
This chapter briefly summarizes the XC2000’s instructions ordered by instruction
classes. This provides a basic understanding of the XC2000’s instruction set, the power
and versatility of the instructions and their general usage.
A detailed description of each single instruction, including its operand data type,
condition flag settings, addressing modes, length (number of bytes) and object code
format is provided in the “Instruction Set Manual” for the XC2000 Family. This manual
also provides tables ordering the instructions according to various criteria, to allow quick
references.
Summary of Instruction Classes
Grouping the various instruction into classes aids in identifying similar instructions (e.g.
SHR, ROR) and variations of certain instructions (e.g. ADD, ADDB). This provides an
easy access to the possibilities and the power of the instructions of the XC2000.
Note: The used mnemonics refer to the detailed description.
Table 12-1
Arithmetic Instructions
Addition of two words or bytes:
ADD
ADDB
Addition with Carry of two words or bytes:
ADDC
ADDCB
Subtraction of two words or bytes:
SUB
SUBB
Subtraction with Carry of two words or bytes:
SUBC
SUBCB
16 × 16 bit signed or unsigned multiplication:
MUL
MULU
16/16 bit signed or unsigned division:
DIV
DIVU
32/16 bit signed or unsigned division:
DIVL
DIVLU
1’s complement of a word or byte:
CPL
CPLB
2’s complement (negation) of a word or byte:
NEG
NEGB
Bitwise ANDing of two words or bytes:
AND
ANDB
Bitwise ORing of two words or bytes:
OR
ORB
Bitwise XORing of two words or bytes:
XOR
XORB
Table 12-2
Logical Instructions
User’s Manual
InstrSummary_X, V2.0
12-1
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 12-3
Instruction Set Summary
Compare and Loop Control Instructions
Comparison of two words or bytes:
CMP
CMPB
Comparison of two words with post-increment by
either 1 or 2:
CMPI1
CMPI2
Comparison of two words with post-decrement by
either 1 or 2:
CMPD1
CMPD2
Manipulation of a maskable bit field in either the high
or the low byte of a word:
BFLDH
BFLDL
Setting a single bit (to ‘1’):
BSET
–
Clearing a single bit (to ‘0’):
BCLR
–
Movement of a single bit:
BMOV
–
Movement of a negated bit:
BMOVN
–
ANDing of two bits:
BAND
–
ORing of two bits:
BOR
–
XORing of two bits:
BXOR
–
Comparison of two bits:
BCMP
–
Shifting right of a word:
SHR
–
Shifting left of a word:
SHL
–
Rotating right of a word:
ROR
–
Rotating left of a word:
ROL
–
Arithmetic shifting right of a word (sign bit shifting):
ASHR
–
Table 12-4
Table 12-5
Table 12-6
Boolean Bit Manipulation Instructions
Shift and Rotate Instructions
Prioritize Instruction
Determination of the number of shift cycles required to PRIOR
normalize a word operand (floating point support):
User’s Manual
InstrSummary_X, V2.0
12-2
–
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Table 12-7
Instruction Set Summary
Data Movement Instructions
Standard data movement of a word or byte:
MOV
MOVB
Data movement of a byte to a word location with either MOVBS
sign or zero byte extension:
MOVBZ
Note: The data movement instructions can be used with a big number of different
addressing modes including indirect addressing and automatic pointer in-/
decrementing.
Table 12-8
System Stack Instructions
Pushing of a word onto the system stack:
PUSH
–
Popping of a word from the system stack:
POP
–
Saving of a word on the system stack, and then
updating the old word with a new value (provided for
register bank switching):
SCXT
–
Table 12-9
Jump Instructions
Conditional jumping to an either absolutely, indirectly, JMPA
or relatively addressed target instruction within the
current code segment:
JMPI
JMPR
Unconditional jumping to an absolutely addressed
target instruction within any code segment:
–
–
Conditional jumping to a relatively addressed target
JB
instruction within the current code segment depending
on the state of a selectable bit:
JNB
–
Conditional jumping to a relatively addressed target
JBC
instruction within the current code segment depending
on the state of a selectable bit with a post-inversion of
the tested bit in case of jump taken (semaphore
support):
JNBS
–
User’s Manual
InstrSummary_X, V2.0
12-3
JMPS
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Instruction Set Summary
Table 12-10 Call Instructions
Conditional calling of an either absolutely or indirectly CALLA
addressed subroutine within the current code
segment:
CALLI
Unconditional calling of a relatively addressed
subroutine within the current code segment:
CALLR
–
Unconditional calling of an absolutely addressed
subroutine within any code segment:
CALLS
–
Unconditional calling of an absolutely addressed
subroutine within the current code segment plus an
additional pushing of a selectable register onto the
system stack:
PCALL
–
Unconditional branching to the interrupt or trap vector TRAP
jump table in code segment <VECSEG>:
–
Table 12-11 Return Instructions
Returning from a subroutine within the current code
segment:
RET
–
Returning from a subroutine within any code segment: RETS
–
Returning from a subroutine within the current code
segment plus an additional popping of a selectable
register from the system stack:
RETP
–
Returning from an interrupt service routine:
RETI
–
User’s Manual
InstrSummary_X, V2.0
12-4
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Instruction Set Summary
Table 12-12 System Control Instructions
Resetting the XC2000 via software:
SRST
–
Entering the Idle mode or Sleep mode:
IDLE
–
Entering the Power Down mode:
PWRDN
–
Servicing the Watchdog Timer:
SRVWDT
–
Disabling the Watchdog Timer:
DISWDT
–
Enabling the Watchdog Timer (can only be executed
in WDT enhanced mode):
ENWDT
–
Signifying the end of the initialization routine (pulls pin EINIT
RSTOUT high, and disables the effect of any later
execution of a DISWDT instruction in WDT
compatibility mode):
–
Table 12-13 Miscellaneous
Null operation which requires 2 Bytes of storage and
the minimum time for execution:
NOP
–
Definition of an unseparable instruction sequence:
ATOMIC
–
Switch ‘reg’, ‘bitoff’ and ‘bitaddr’ addressing modes to EXTR
the Extended SFR space:
–
Override the DPP addressing scheme using a specific EXTP
data page instead of the DPPs, and optionally switch
to ESFR space:
EXTPR
Override the DPP addressing scheme using a specific EXTS
segment instead of the DPPs, and optionally switch to
ESFR space:
EXTSR
Note: The ATOMIC and EXT* instructions provide support for uninterruptable code
sequences e.g. for semaphore operations. They also support data addressing
beyond the limits of the current DPPs (except ATOMIC), which is advantageous
for bigger memory models in high level languages.
User’s Manual
InstrSummary_X, V2.0
12-5
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Instruction Set Summary
Table 12-14 MAC-Unit Instructions
Multiply (and Accumulate):
CoMUL
CoMAC
Add/Subtract:
CoADD
CoSUB
Shift right/Shift left:
CoSHR
CoSHL
Arithmetic Shift right:
CoASHR
–
Load Accumulator:
CoLOAD
–
Store MAC register:
CoSTORE
–
Compare values:
CoCMP
–
Minimum/Maximum:
CoMIN
CoMAX
Absolute value:
CoABS
–
Rounding:
CoRND
–
Move data:
CoMOV
–
Negate accumulator:
CoNEG
–
Null operation:
CoNOP
–
Protected Instructions
Some instructions of the XC2000 which are critical for the functionality of the controller
are implemented as so-called Protected Instructions. These protected instructions use
the maximum instruction format of 32 bits for decoding, while the regular instructions
only use a part of it (e.g. the lower 8 bits) with the other bits providing additional
information like involved registers. Decoding all 32 bits of a protected doubleword
instruction increases the security in cases of data distortion during instruction fetching.
Critical operations like a software reset are therefore only executed if the complete
instruction is decoded without an error. This enhances the safety and reliability of a
microcontroller system.
User’s Manual
InstrSummary_X, V2.0
12-6
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
13
Device Specification
Device Specification
The device specification describes the electrical parameters of the device. It lists DC
characteristics like input, output or supply voltages or currents, and AC characteristics
like timing characteristics and requirements.
Other than the architecture, the instruction set, or the basic functions of the XC2000 core
and its peripherals, these DC and AC characteristics are subject to changes due to
device improvements or specific derivatives of the standard device.
Therefore, these characteristics are not contained in this manual, but rather provided in
a separate Data Sheet, which can be updated more frequently.
Please refer to the current version of the Data Sheet of the respective device for all
electrical parameters.
Note: In any case the specific characteristics of a device should be verified, before a new
design is started. This ensures that the used information is up to date.
The XC2000 derivatives are shipped in several packages. Figure 13-1 and Figure 13-2
show the basic pin diagrams of the XC2000. They show the location of the different
supply and IO pins. A detailed description of all the pins and their selectable functions
can be found in the corresponding Data Sheet.
Note: Not all alternate functions shown in Figure 13-1 are supported by all derivatives.
Please refer to the corresponding descriptions in the data sheets.
User’s Manual
DeviceSpecX2K, V1.0
13-1
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
VDDPB
VSS
P9.5
P9.4
P1.3
P10 .13
P9.3
P10 .12
P1.2
P9.2
P10 .11
P10 .10
P1.1
P10 .9
P9.1
P10 .8
P9.0
P1.0
14 4
14 3
14 2
14 1
14 0
13 9
13 8
13 7
13 6
13 5
13 4
13 3
13 2
13 1
13 0
12 9
12 8
12 7
12 6
12 5
12 4
12 3
12 2
12 1
12 0
11 9
11 8
11 7
11 6
11 5
11 4
11 3
11 2
11 1
11 0
10 9
VDDI1
P8.5
P8.6
ESR0
ESR2
ESR1
PORS T
XTAL 1
XTAL2
P1.7
P9.7
P1.6
P9.6
P1.5
P10 .15
P1.4
P10 .14
Device Specification
VDDPB
Preliminary
V SS
V DDPB
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
XC2xxx
V DDPB
P3.7
P0.7
P10.7
P3.6
P10.6
P0.6
P3.5
P10.5
P3.4
P10.4
P3.3
P0.5
P10.3
P2.10
P3.2
TRef
V DDI1
P0.4
P10.2
P3.1
P0.3
P10.1
P3.0
P10.0
P0.2
P2.9
P4.7
P2.8
P0.1
P2.7
P4.6
P4.5
P0.0
V DDPB
V SS
VDDPB
P2. 0
P2. 1
P11. 4
P2 .2
P11. 3
P4. 0
P2. 3
P11. 2
P4. 1
P2. 4
P11. 1
P11. 0
P2. 5
P4. 2
P2. 6
P4. 4
P4. 3
VDDI1
P5. 4
P5. 5
P5.6
P5.7
P5. 8
P5. 9
P5.1 0
P5.1 1
P5.1 2
P5.1 3
P5.1 4
P5.1 5
P2.1 2
P2.1 1
P11. 5
VSS
VDDPB
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TEST M
P7.2
P8.4
TRST
P8.3
P7.0
P7.3
P8.2
P7.1
P7.4
P8.1
P8.0
VDDIM
P6.0
P6.1
P6.2
P6.3
V DDPA
P15.0
P15.1
P15.2
P15.3
P15.4
P15.5
P15.6
P15.7
VAREF1
VAREF0
VAGND
P5.0
P5.1
P5.2
P5.3
V DDPB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MC_XC2X_PIN144
Figure 13-1 Pin Configuration PG-LQFP-144 Package (top view)
User’s Manual
DeviceSpecX2K, V1.0
13-2
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDDI1
P1.3
P10.13
P10.12
P1.2
P10.11
P10.10
P1.1
P10.9
P10.8
P1.0
VDDPB
VSS
Device Specification
VDDPB
ESR0
ESR1
PORST
XTAL1
XTAL2
P1.7
P1.6
Preliminary
VSS
VDDP
B
TESTM
P7.2
TRST
P7.0
P7.3
P7.1
P7.4
VDDIM
P6.0
P6.1
P6.2
VDDPA
P15.0
P15.2
P15.4
P15.5
P15.6
VAREF
VAGND
P5.0
P5.2
P5.3
XC2xxx
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDPB
P0. 7
P10.7
P10.6
P0. 6
P10.5
P10.4
P0. 5
P10.3
P2. 10
TRef
VDDI1
P0. 4
P10. 2
P0. 3
P10.1
P10.0
P0. 2
P2. 9
P2. 8
P0. 1
P2. 7
P0. 0
VDDPB
VSS
V SS
V DDPB
P5.4
P5.5
P5.8
P5.9
P5.10
P5.11
P5.13
P5.15
P2.12
P2.11
VDDI1
P2.0
P2.1
P2.2
P4.0
P2.3
P4.1
P2.4
P2.5
P4.2
P2.6
P4.3
V DDPB
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDPB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Figure 13-2 Pin Configuration PG-LQFP-100 Package (top view)
User’s Manual
DeviceSpecX2K, V1.0
13-3
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
User’s Manual
DeviceSpecX2K, V1.0
Device Specification
13-4
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Keyword Index
Keyword Index
This section lists a number of keywords which refer to specific details of the XC2000 in
terms of its architecture, its functional units or functions. This helps to quickly find the
answer to specific questions about the XC2000.
This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For
your convenience this keyword index refers to both volumes, so you can immediately
find the reference to the desired section in the corresponding document ([1] or [2]).
Note: Registers are listed in a separate index: Register Index.
A
Bit timing 20-10 [2]
Block diagram 20-7 [2]
Error handling 20-12 [2]
Gateway mode 20-42 [2]
Interrupts 20-13 [2]
Message acceptance filtering
20-22 [2]
Message object FIFO 20-37 [2]
Message object lists 20-14 [2]
Node control 20-10 [2]
Overview 20-4 [2]
Registers
LISTiH 20-58 [2]
LISTiL 20-59 [2]
MCR 20-56 [2]
MITR 20-57 [2]
MOAMRnH 20-95 [2]
MOAMRnL 20-95 [2]
MOARnH 20-97 [2]
MOARnL 20-98 [2]
MOCTRnH 20-80 [2], 20-82 [2]
MOCTRnL 20-81 [2], 20-82 [2]
MODATAnHH 20-101 [2]
MODATAnHL 20-101 [2]
MODATAnLH 20-100 [2]
MODATAnLL 20-100 [2]
MOFCRnH 20-89 [2]
MOFCRnL 20-91 [2]
MOFGPRnH 20-93 [2]
MOFGPRnL 20-93 [2]
MOIPRnH 20-87 [2]
Acronyms 1-9 [1]
Addressing Modes
CoREG Addressing Mode 4-50 [1]
DSP Addressing Modes 4-46 [1]
Indirect Addressing Modes 4-44 [1]
Long Addressing Modes 4-41 [1]
Short Addressing Modes 4-39 [1]
ALU 4-57 [1]
B
Baudrate
Bootstrap Loader 10-9 [1]
Bit
Handling 4-60 [1]
Manipulation Instructions 12-2 [1]
protected 4-61 [1]
reserved 2-17 [1]
Block Diagram ITC / PEC 5-3 [1]
Bootstrap Loader 10-4 [1]
C
CAN
Block diagram 20-2 [2]
Clock control 20-102 [2]
Features 20-2 [2]
Functional description 20-4 [2]
Interrupt structure 20-105 [2]
Module implementation 20-106 [2]
MultiCAN
Analysis mode 20-19 [2]
User’s Manual
L-1
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Keyword Index
MOIPRnL 20-87 [2]
MSIDk 20-61 [2]
MSIMASKH 20-62 [2]
MSIMASKL 20-62 [2]
MSPNDkH 20-60 [2]
MSPNDkL 20-60 [2]
NBTRxH 20-72 [2]
NBTRxL 20-73 [2]
NCRx 20-63 [2]
NECNTxH 20-74 [2]
NECNTxL 20-74 [2]
NFCRxH 20-76 [2]
NFCRxL 20-77 [2]
NIPRx 20-70 [2]
NPCRx 20-71 [2]
NSRx 20-66 [2]
PANCTRH 20-51 [2]
PANCTRL 20-51 [2]
CAPCOM12
Capture Mode 17-14 [2]
Counter Mode 17-9 [2]
CAPCOM2 2-17 [1]
Capture Mode
GPT1 14-26 [2]
GPT2 (CAPREL) 14-48 [2]
Capture/Compare Registers 17-11 [2]
CCU6 2-19 [1]
Clock
generation 2-32 [1]
Clock System 6-2 [1]
Clock Control Unit 6-13 [1]
Clock Generation Unit 6-2 [1]
Clock Output 6-15 [1]
Crystal oscillator 6-3 [1]
Crystal Oscillator run detection 6-11 [1]
Emergency Clock Operation 6-14 [1]
PLL 6-5 [1]
Switching parameters 6-12 [1]
Concatenation of Timers 14-22 [2],
14-47 [2]
Context
Pointer Updating 4-34 [1]
Switch 4-33 [1]
User’s Manual
Switching 5-33 [1]
Count direction 14-6 [2], 14-36 [2]
Counter 14-20 [2], 14-45 [2]
Counter Mode (GPT1) 14-10 [2], 14-40 [2]
CPU 2-2 [1], 4-1 [1]
D
Data Management Unit (Introduction)
2-9 [1]
Data Page 4-42 [1]
Development Support 1-8 [1]
Direction
count 14-6 [2], 14-36 [2]
Disable
Interrupt 5-30 [1]
Division 4-62 [1]
Double-Register Compare 17-24 [2]
DPP 4-42 [1]
E
EBC
Bus Signals 9-3 [1]
Memory Table 9-33 [1]
Enable
Interrupt 5-30 [1]
End of PEC Interrupt Sub Node 5-29 [1]
ESRx 5-1 [1]
External
Bus 2-14 [1]
Interrupts 5-36 [1]
External Request Unit (ERU) 6-64 [1]
ERS 6-72 [1]
ETL 6-74 [1]
Internal Connections 6-76 [1]
OGU 6-77 [1]
Operation 6-64 [1]
Pin Connetions 6-66 [1]
External Service Request (ESR) 6-52 [1]
ESR Pad Control 6-57 [1]
ESR Reset 6-55 [1]
ESR Trap 6-56 [1]
ESR Wake-up 6-56 [1]
Operation 6-52 [1]
L-2
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Keyword Index
F
L
Flags 4-56 [1]–4-59 [1]
Fractional divider
Block diagram 20-108 [2]
Operating modes 20-110 [2]
Suspend mode 20-111 [2]
Latency
Interrupt, PEC 5-39 [1]
LXBus 2-14 [1]
G
Gated timer mode (GPT1) 14-9 [2]
Gated timer mode (GPT2) 14-39 [2]
Global State Controller (GSC) 6-156 [1]
Commands 6-157 [1]
Operation 6-156 [1]
Priorities 6-156 [1]
GPT 2-20 [1]
GPT1 14-2 [2]
GPT2 14-32 [2]
H
Hardware
Traps 5-41 [1]
I
Incremental Interface Mode (GPT1)
14-11 [2]
Instruction 12-1 [1]
Bit Manipulation 12-2 [1]
Pipeline 4-11 [1]
protected 12-6 [1]
Interface
External Bus 9-1 [1]
Interrupt
Arbitration 5-4 [1]
Enable/Disable 5-30 [1]
External 5-36 [1]
Jump Table Cache 5-17 [1]
Latency 5-39 [1]
Node Sharing 5-35 [1]
Priority 5-7 [1]
Processing 5-1 [1]
RTC 15-13 [2]
System 2-8 [1], 5-2 [1]
User’s Manual
M
Memory 2-10 [1]
Multiplication 4-62 [1]
O
OCDS
Requests 5-38 [1]
P
PEC 2-10 [1], 5-19 [1]
Latency 5-39 [1]
Transfer Count 5-20 [1]
Peripheral
Event Controller --> PEC 5-19 [1]
Summary 2-15 [1]
Pins 8-1 [1]
Pipeline 4-11 [1]
Port 2-30 [1]
Ports
Configuring a Pin 7-15 [1]
I/O Description Entry 7-6 [1]
Output register Pn_OUT 7-10 [1]
Pad driver control 7-7 [1]
Structure
Analog 7-4 [1]
Hardware Override 7-3 [1]
Standard 7-2 [1]
Power Control 6-90 [1]
Changing Core Voltage 6-126 [1]
Control of Core Voltage 6-115 [1]
EVR 6-115 [1]
Monitoring Core Voltage 6-97 [1]
PSC 6-128 [1]
PVC 6-97 [1]
Supply Watchdog (SWD) 6-91 [1]
Program Management Unit (Introduction)
2-9 [1]
L-3
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Keyword Index
Stack 4-52 [1]
Protected
Bits 4-61 [1]
instruction 12-6 [1]
T
R
Real Time Clock (->RTC) 2-22 [1], 15-1 [2]
Reserved bits 2-17 [1]
Reset 6-33 [1]
Modules behavior 6-40 [1]
Reset Operation 6-33 [1]
Reset Types 6-33 [1]
CPU Reset 6-38 [1]
ESR Reset 6-37 [1]
Memory Parity Reset 6-38 [1]
OCDS Controlled Reset 6-38 [1]
Power-on Reset 6-37 [1]
Software Reset 6-38 [1]
Supply Watchdog Reset 6-37 [1]
Voltage Monitoring Reset 6-37 [1]
Watchdog Timer Reset 6-38 [1]
RTC 2-22 [1], 15-1 [2]
Registers
T14 15-8 [2]
T14REL 15-8 [2]
S
SCU
Identification 6-218 [1]
Interrupt 6-186 [1]
Buffering 6-210 [1]
Operation 6-187 [1]
Register Access 6-181 [1]
Register Overview 6-220 [1]
Trap 6-186 [1]
Buffering 6-210 [1]
Operation 6-200 [1]
Segmentation 4-37 [1]
Sharing
Interrupt Nodes 5-35 [1]
Software
Traps 5-41 [1]
SR0 5-46 [1]
SR1 5-46 [1]
User’s Manual
Temperature Compensation Unit 6-165 [1]
Timer 14-2 [2], 14-32 [2]
Auxiliary Timer 14-15 [2], 14-41 [2]
Concatenation 14-22 [2], 14-47 [2]
Core Timer 14-4 [2], 14-34 [2]
Counter Mode (GPT1) 14-10 [2],
14-40 [2]
Gated Mode (GPT1) 14-9 [2]
Gated Mode (GPT2) 14-39 [2]
Incremental Interface Mode (GPT1)
14-11 [2]
Mode (GPT1) 14-8 [2]
Mode (GPT2) 14-38 [2]
Tools 1-8 [1]
Traps 5-41 [1]
W
Wake-up Timer 6-176 [1]
Watchdog 2-29 [1]
Watchdog Timer 6-168 [1]
Operation 6-168 [1]
Disable Mode 6-171 [1]
Normal Mode 6-170 [1]
Prewarning Mode 6-171 [1]
Suspend Mode 6-172 [1]
L-4
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Register Index
Register Index
This section lists the registers of the XC2000. This helps to quickly find the reference to
the description of the respective register.
This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For
your convenience this register index refers to both volumes, so you can immediately find
the reference to the desired section in the corresponding document ([1] or [2]).
Note: Keywords are listed in a separate index: Keyword Index.
A
ADC0_KSCFG 16-24 [2]
ADCx_ALR0 16-77 [2]
ADCx_ASENR 16-37 [2]
ADCx_CHCTRx 16-68 [2]
ADCx_CHINCR 16-73 [2]
ADCx_CHINFR 16-72 [2]
ADCx_CHINPRx 16-74 [2]
ADCx_CRCRx 16-43 [2]
ADCx_CRMRx 16-45 [2]
ADCx_CRPRx 16-44 [2]
ADCx_EMCTR 16-102 [2]
ADCx_EMENR 16-103 [2]
ADCx_EVINCR 16-93 [2]
ADCx_EVINFR 16-92 [2]
ADCx_EVINPRx 16-94 [2]
ADCx_GLOBCTR 16-26 [2]
ADCx_GLOBSTR 16-28 [2]
ADCx_INPRx 16-70 [2]
ADCx_LCBRx 16-71 [2]
ADCx_PISEL 16-31 [2]
ADCx_Q0Rx 16-57 [2]
ADCx_QBURx 16-59 [2]
ADCx_QINRx 16-61 [2]
ADCx_QMRx 16-52 [2]
ADCx_QSRx 16-55 [2]
ADCx_RCRx 16-90 [2]
ADCx_RESRAVx 16-87 [2]
ADCx_RESRAx 16-87 [2]
ADCx_RESRVx 16-86 [2]
ADCx_RESRx 16-86 [2]
ADCx_RSPRx 16-38 [2]
User’s Manual
ADCx_RSSR 16-88 [2]
ADCx_SYNCTR 16-104 [2]
ADCx_VFR 16-89 [2]
ADDRSELx 9-22 [1]
B
BANKSELx 5-34 [1]
C
CAN_LISTiH 20-58 [2]
CAN_LISTiL 20-59 [2]
CAN_MCR 20-56 [2]
CAN_MITR 20-57 [2]
CAN_MOAMRnH 20-95 [2]
CAN_MOAMRnL 20-95 [2]
CAN_MOARnH 20-97 [2]
CAN_MOARnL 20-98 [2]
CAN_MOCTRnH 20-80 [2]
CAN_MOCTRnL 20-81 [2]
CAN_MODATAnHH 20-101 [2]
CAN_MODATAnHL 20-101 [2]
CAN_MODATAnLH 20-100 [2]
CAN_MODATAnLL 20-100 [2]
CAN_MOFCRnH 20-89 [2]
CAN_MOFCRnL 20-91 [2]
CAN_MOFGPRnH 20-93 [2]
CAN_MOFGPRnL 20-93 [2]
CAN_MOIPRnH 20-87 [2]
CAN_MOIPRnL 20-87 [2]
CAN_MOSTATnH 20-82 [2]
CAN_MOSTATnL 20-82 [2]
CAN_MSIDk 20-61 [2]
L-5
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
CAN_MSIMASKH 20-62 [2]
CAN_MSIMASKL 20-62 [2]
CAN_MSPNDkH 20-60 [2]
CAN_MSPNDkL 20-60 [2]
CAN_NBTRxH 20-72 [2]
CAN_NBTRxL 20-73 [2]
CAN_NCRx 20-63 [2]
CAN_NECNTxH 20-74 [2]
CAN_NECNTxL 20-74 [2]
CAN_NFCRxH 20-76 [2]
CAN_NFCRxL 20-77 [2]
CAN_NIPRx 20-70 [2]
CAN_NPCRx 20-71 [2]
CAN_NSRx 20-66 [2]
CAN_PANCTRH 20-51 [2]
CAN_PANCTRL 20-51 [2]
CAPREL 14-56 [2]
CC2_CCyIC 17-36 [2]
CC2_DRM 17-25 [2]
CC2_IOC 17-31 [2]
CC2_KSCCFG 17-39 [2]
CC2_M4/5/6/7 17-11 [2]
CC2_OUT 17-27 [2]
CC2_SEE 17-29 [2]
CC2_SEM 17-29 [2]
CC2_T78CON 17-5 [2]
CC2_T7IC 17-10 [2]
CC2_T8IC 17-10 [2]
CCU6x_CC63R 18-65 [2]
CCU6x_CC63SR 18-65 [2]
CCU6x_CC6xR 18-34 [2]
CCU6x_CC6xSR 18-35 [2]
CCU6x_CMPMODIF 18-40 [2]
CCU6x_CMPSTAT 18-38 [2]
CCU6x_IEN 18-98 [2]
CCU6x_INP 18-101 [2]
CCU6x_IS 18-91 [2]
CCU6x_ISR 18-96 [2]
CCU6x_ISS 18-94 [2]
CCU6x_KSCFG 18-111 [2]
CCU6x_KSCSR 18-113 [2]
CCU6x_MCFG 18-114 [2]
CCU6x_MCMCTR 18-84 [2]
User’s Manual
Register Index
CCU6x_MCMOUT 18-87 [2]
CCU6x_MCMOUTS 18-86 [2]
CCU6x_MODCTR 18-78 [2]
CCU6x_PISELH 18-109 [2]
CCU6x_PISELL 18-107 [2]
CCU6x_PSLR 18-83 [2]
CCU6x_T12 18-33 [2]
CCU6x_T12DTC 18-36 [2]
CCU6x_T12MSEL 18-41 [2]
CCU6x_T12PR 18-33 [2]
CCU6x_T13 18-63 [2]
CCU6x_T13PR 18-64 [2]
CCU6x_TCTR0 18-42 [2]
CCU6x_TCTR2 18-45 [2]
CCU6x_TCTR4 18-48 [2]
CCU6x_TRPCTR 18-80 [2]
CP 4-36 [1]
CPUCON1 4-26 [1]
CPUCON2 4-27 [1]
CRIC 14-57 [2]
CSP 4-38 [1]
D
DPP0/1/2/3 4-42 [1]
DSTPx 5-24 [1]
E
EBCMOD0 9-13 [1]
EBCMOD1 9-15 [1]
EOPIC 5-28 [1]
F
FCONCS0 9-19 [1]
FCONCS1/2/3/4/7 9-20 [1]
FINT0/1ADDR 5-17 [1]
FINT0/1CSP 5-17 [1]
FL_KSCCFG 3-64 [1]
FSR_BUSY 3-57 [1]
FSR_OP 3-57 [1]
FSR_PROT 3-59 [1]
G
GPT12E_CAPREL 14-56 [2]
L-6
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
GPT12E_CRIC 14-57 [2]
GPT12E_KSCCFG 14-58 [2]
GPT12E_T2,-T3,-T4 14-30 [2]
GPT12E_T2/3/4IC 14-31 [2]
GPT12E_T2CON 14-15 [2]
GPT12E_T3CON 14-4 [2]
GPT12E_T4CON 14-15 [2]
GPT12E_T5,-T6 14-56 [2]
GPT12E_T5/6IC 14-57 [2]
GPT12E_T5CON 14-41 [2]
GPT12E_T6CON 14-34 [2]
I
Register Index
Pn_IN 7-13 [1]
Pn_IOCRx 7-14 [1]
Pn_OMRH
P10 7-11 [1]
P2 7-11 [1]
Pn_OMRL 7-11 [1]
Pn_OUT 7-10 [1]
Pn_POCON 7-8 [1]
Ports
Pn_IN 7-13 [1]
Pn_IOCRx 7-14 [1]
Pn_OMR 7-11 [1]
PROCONx 3-62 [1]
PSW 4-56 [1]
IDX0/1 4-46 [1]
IMBCTRH 3-54 [1]
IMBCTRL 3-52 [1]
INTCTR 3-55 [1]
IP 4-38 [1]
Q
M
R
MAH 4-69 [1]
MAL 4-68 [1]
MAR 3-61 [1]
MCW 4-65 [1]
MDC 4-63 [1]
MDH 4-62 [1]
MDL 4-63 [1]
MEM_KSCCFG 3-63 [1]
MKMEM0/1 3-76 [1]
MRW 4-72 [1]
MSW 4-70 [1]
RELH/L 15-10 [2]
RTC_CON 15-5 [2]
RTC_IC 15-14 [2]
RTC_ISNC 15-14 [2]
RTC_KSCCFG 15-15 [2]
RTC_RELH/L 15-10 [2]
RTC_RTCH/L 15-9 [2]
RTC_T14 15-8 [2]
RTC_T14REL 15-8 [2]
RTCH/L 15-9 [2]
O
SBRAM_DATA0 3-74 [1]
SBRAM_DATA1 3-75 [1]
SBRAM_RADD 3-72 [1]
SBRAM_WADD 3-73 [1]
SCU
Registers
DMPMIT 6-211 [1]
DMPMITCLR 6-214 [1]
ESRCFG0 6-61 [1]
ESRCFG1 6-61 [1]
ESRCFG2 6-61 [1]
ONES 4-74 [1]
P
PECCx 5-20 [1]
PECISNC 5-28 [1]
PECON 3-78 [1]
PECSEGx 5-24 [1]
Pn_DIDIS
P15 7-17 [1]
P5 7-17 [1]
User’s Manual
QR0/1 4-45 [1]
QX0/1 4-47 [1]
S
L-7
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Register Index
PVC1CON0 6-100 [1]
PVC1CONA1 6-106 [1]
PVC1CONA2 6-106 [1]
PVC1CONA3 6-106 [1]
PVC1CONA4 6-106 [1]
PVC1CONA5 6-106 [1]
PVC1CONA6 6-106 [1]
PVC1CONB1 6-112 [1]
PVC1CONB3 6-112 [1]
PVC1CONB4 6-112 [1]
PVC1CONB5 6-112 [1]
PVC1CONB6 6-112 [1]
PVCMCON0 6-98 [1]
PVCMCONA1 6-103 [1]
PVCMCONA2 6-103 [1]
PVCMCONA3 6-103 [1]
PVCMCONA4 6-103 [1]
PVCMCONA5 6-103 [1]
PVCMCONA6 6-103 [1]
PVCMCONB1 6-109 [1]
PVCMCONB2 6-109 [1]
PVCMCONB3 6-109 [1]
PVCMCONB4 6-109 [1]
PVCMCONB5 6-109 [1]
PVCMCONB6 6-109 [1]
RSTCNTCON 6-50 [1]
RSTCON0 6-47 [1]
RSTCON1 6-48 [1]
RSTSTAT0 6-41 [1]
RSTSTAT1 6-42 [1]
RSTSTAT2 6-44 [1]
RTCCLKCON 6-31 [1]
SEQASTEP1 6-139 [1]
SEQASTEP2 6-144 [1]
SEQASTEP3 6-144 [1]
SEQASTEP4 6-144 [1]
SEQASTEP5 6-144 [1]
SEQASTEP6 6-144 [1]
SEQBSTEP1 6-147 [1]
SEQBSTEP2 6-152 [1]
SEQBSTEP3 6-152 [1]
SEQBSTEP4 6-152 [1]
SEQBSTEP5 6-152 [1]
ESRDAT 6-63 [1]
ESREXCON1 6-58 [1]
ESREXCON2 6-59 [1]
EVR1CON0 6-118 [1]
EVR1SET10V 6-123 [1]
EVR1SET15VHP 6-125 [1]
EVR1SET15VLP 6-124 [1]
EVRMCON0 6-117 [1]
EVRMCON1 6-119 [1]
EVRMSET10V 6-120 [1]
EVRMSET15VHP 6-122 [1]
EVRMSET15VLP 6-121 [1]
EXICON0 6-85 [1]
EXICON1 6-85 [1]
EXICON2 6-85 [1]
EXICON3 6-85 [1]
EXISEL 6-83 [1]
EXOCON0 6-88 [1]
EXOCON1 6-88 [1]
EXOCON2 6-88 [1]
EXOCON3 6-88 [1]
EXTCON 6-31 [1]
GSCEN 6-160 [1]
GSCSTAT 6-163 [1]
GSCSWREQ 6-160 [1]
HPOSCCON 6-19 [1]
IDCHIP 6-218 [1]
IDMANUF 6-218 [1]
IDMEM 6-219 [1]
IDPROG 6-219 [1]
INTCLR 6-192 [1]
INTDIS 6-195 [1]
INTNP0 6-196 [1]
INTNP1 6-199 [1]
INTSET 6-193 [1]
INTSTAT 6-189 [1]
ISSR 6-216 [1]
PLLCON0 6-24 [1]
PLLCON1 6-25 [1]
PLLCON2 6-26 [1]
PLLCON3 6-27 [1]
PLLOSCCON 6-21 [1]
PLLSTAT 6-22 [1]
User’s Manual
L-8
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
SEQBSTEP6 6-152 [1]
SEQCON 6-134 [1]
SLC 6-183 [1]
SLS 6-184 [1]
STATCLR0 6-29 [1]
STATCLR1 6-30 [1]
STEP0 6-136 [1]
SWDCON0 6-94 [1]
SWDCON1 6-95 [1]
SWRSTCON 6-51 [1]
SYSCON0 6-28 [1]
SYSCON1 6-185 [1]
TCCR 6-166 [1]
TCLR 6-167 [1]
TRAPCLR 6-204 [1], 6-205 [1]
TRAPDIS 6-206 [1]
TRAPNP 6-207 [1]
TRAPSTAT 6-202 [1]
WDTCS 6-173 [1]
WDTREL 6-173 [1]
WDTTIM 6-175 [1]
WICR 6-178 [1]
WUCR 6-178 [1]
WUOSCCON 6-18 [1]
SCU_STSTAT 6-46 [1]
SP 4-53 [1]
SPSEG 4-53 [1]
SRCPx 5-24 [1]
STKOV 4-55 [1]
STKUN 4-55 [1]
STSTAT 6-46 [1]
T
T14 15-8 [2]
T14REL 15-8 [2]
T2, T3, T4 14-30 [2]
T2/3/4IC 14-31 [2]
T2CON 14-15 [2]
T3CON 14-4 [2]
T4CON 14-15 [2]
T5, T6 14-56 [2]
T5/6IC 14-57 [2]
T5CON 14-41 [2]
User’s Manual
Register Index
T6CON 14-34 [2]
T7IC 17-10 [2]
T8IC 17-10 [2]
TCONCS0 9-16 [1]
TCONCS1/2/3/4 9-17 [1]
TFR 5-43 [1]
U
USIC_BRGH 19-53 [2]
USIC_BRGL 19-51 [2]
USIC_BYP 19-91 [2]
USIC_BYPCRH 19-93 [2]
USIC_BYPCRL 19-91 [2]
USIC_CCFG 19-31 [2]
USIC_CCR 19-28 [2]
USIC_DXxCR 19-42 [2]
USIC_FDRH 19-50 [2]
USIC_FDRL 19-49 [2]
USIC_FMRH 19-71 [2]
USIC_FMRL 19-70 [2]
USIC_INPRH 19-36 [2]
USIC_INPRL 19-35 [2]
USIC_INx 19-107 [2]
USIC_KSCFG 19-33 [2]
USIC_OUTDRH 19-109 [2]
USIC_OUTDRL 19-109 [2]
USIC_OUTRH 19-108 [2]
USIC_OUTRL 19-108 [2]
USIC_PCRH 19-37 [2]
USIC_PCRL 19-37 [2]
USIC_PSCR 19-39 [2]
USIC_PSR 19-38 [2]
USIC_RBCTRH 19-103 [2]
USIC_RBCTRL 19-103 [2]
USIC_RBUF 19-79 [2]
USIC_RBUF0 19-73 [2]
USIC_RBUF01SRH 19-76 [2]
USIC_RBUF01SRL 19-73 [2]
USIC_RBUF1 19-76 [2]
USIC_RBUFD 19-79 [2]
USIC_RBUFSR 19-80 [2]
USIC_SCTRH 19-62 [2]
USIC_SCTRL 19-60 [2]
L-9
V1.0, 2007-06
XC2000 Derivatives
System Units (Vol. 1 of 2)
Preliminary
Register Index
USIC_TBCTRH 19-100 [2]
USIC_TBCTRL 19-100 [2]
USIC_TBUFx 19-72 [2]
USIC_TCSRH 19-68 [2]
USIC_TCSRL 19-63 [2]
USIC_TRBPTRH 19-110 [2]
USIC_TRBPTRL 19-110 [2]
USIC_TRBSCR 19-98 [2]
USIC_TRBSRH 19-97 [2]
USIC_TRBSRL 19-94 [2]
V
VECSEG 5-11 [1]
X
xxIC (gen.) 5-6 [1]
Z
ZEROS 4-74 [1]
User’s Manual
L-10
V1.0, 2007-06
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG