AN206375 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed The DMA function transfers data concurrently with the CPU process and it is convenient for shortening the data transfer time and enhancing the processing speed. To obtain the time of data transfer by this DMA function, the number of cycles must be obtained according to the conditions because the data transfer route depends on the transfer source or destination. This document discusses access speeds under various conditions for the DMA function mounted on the FR80S/T series. Contents 1 2 3 4 1 Introduction ..................................................................1 Overview of DMA Transfer ..........................................2 2.1 DMA Transfer Cycles ..........................................2 2.2 Access Cycles Depending on Bus Difference .....2 2.3 Disincentive Against DMA Transfer ....................3 Number of DMA Transfer Cycles .................................4 3.1 Number of Peripheral Function -> DMA Transfer Cycles .................................................................4 3.2 Number of DMA -> Peripheral Function Transfer Cycles .................................................................4 3.3 Number of RAM -> DMA Transfer Cycles ...........5 3.4 Number of DMA -> RAM Transfer Cycles ...........5 3.5 Number of USB -> DMA Transfer Cycles............6 3.6 Number of DMA -> USB Transfer Cycles............6 3.7 Number of External Bus -> DMA Transfer Cycles .................................................................7 3.8 Number of DMA -> External Bus Transfer Cycles .................................................................8 Calculation Examples ................................................ 10 4.1 4.2 4.3 Peripheral Function -> DMA -> RAM ................ 10 RAM -> DMA -> Peripheral Function ................ 10 Peripheral Function -> DMA -> Peripheral Function ............................................................ 10 5 Timing Chart Examples ............................................. 11 5.1 Peripheral Function -> DMA -> RAM ................ 11 5.2 RAM -> DMA -> Peripheral Function ................ 13 5.3 Peripheral Function -> DMA -> Peripheral Function ............................................................ 14 5.4 RAM -> DMA -> RAM ....................................... 15 5.5 USB -> DMA -> RAM ........................................ 15 5.6 RAM -> DMA -> USB ........................................ 15 5.7 External bus -> DMA -> RAM ........................... 16 5.8 RAM -> DMA -> External Bus ........................... 18 5.9 Peripheral Function -> DMA -> External Bus .... 21 Document History............................................................ 23 Introduction The DMA function transfers data concurrently with the CPU process and it is convenient for shortening the data transfer time and enhancing the processing speed. To obtain the time of data transfer by this DMA function, the number of cycles must be obtained according to the conditions because the data transfer route depends on the transfer source or destination. This document discusses access speeds under various conditions for the DMA function mounted on the FR80S/T series. www.cypress.com Document No. 002-06375 Rev. *A 1 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 2 2.1 Overview of DMA Transfer DMA Transfer Cycles When data is being transferred using the DMA function, data is retrieved from the transfer source to the DMA then data is written from the DMA to the transfer destination. Therefore, the number of DMA transfer cycles can be calculated as the sum of [Transfer source -> DMA cycle] and [DMA -> Transfer destination cycle]. [DMA transfer cycle] = [Transfer source -> DMA cycle] + [DMA -> Transfer destination cycle] … (1) 2.2 Access Cycles Depending on Bus Difference The data access cycles can be categorized under the Flash memory, RAM, peripheral function, external bus, or USB depending on the data transfer route. (See Figure 1.) If [Transfer source -> DMA cycles] and [DMA -> Transfer destination cycles] can be obtained under these five conditions, the DMA transfer cycles under each condition can be obtained. Since the on-chip bus has the blue and green lines (Figure 1) and two layers (multi-layer bus), DMA transfer can be performed concurrently with CPU access if the access destination is different. The XBS (cross-bar switch bus) can perform DMA transfer to the RAM while the CPU is accessing the Flash memory to give instructions. CPU XBS DMA Flash memory Peripheral function RAM External bus On-chip bus Port USB Micro-computer Figure 1 FR80S internal bus pattern www.cypress.com Document No. 002-06375 Rev.*A 2 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 2.3 Disincentive Against DMA Transfer Although the DMA function can transfer data concurrently with the CPU process, it shares the data transfer bus of the DMA function with the CPU. If both access the same bus, they block transfer to each other. Since the effect of disincentive to DMA transfer depends on instructions executed by the CPU, it is hard to represent the effect in a quantitative manner. Therefore, this document proceeds with the discussion on the number of cycles on the assumption that there is no blocking by the CPU. Described below are specific examples of disincentives against DMA transfer. 2.3.1 S p e c i f i c E x a m p l e 1 o f D i s i n c e n t i ve : A c c e s s i n g t h e F l a s h m e m o r y f o r D M A T r a n s f e r Since the CPU executes the program on the Flash memory, accessing the Flash memory data by the DMA function is blocked. Therefore, this document excludes the Flash memory from the discussion on the number of cycles and proceeds with the discussion under the remaining four conditions. 2.3.2 S p e c i f i c E x a m p l e 2 o f D i s i n c e n t i ve : C P U Ac c e s s i n g t h e R AM While the CPU is accessing the data in the RAM, accessing the RAM by the DMA function is blocked. 2.3.3 S p e c i a l S p e c i f i c E x a m p l e 3 W i t h o u t B l o c k i n g : U s i n g T w o L a ye r s o f O n -c h i p B u s If the DMA function transfers data from the RAM to a peripheral function while the CPU is accessing an external bus, transfer is not blocked. The reason is that there are two buses; the XBS and the bus connecting the DMA, peripheral function, external bus, or USB. While the CPU is accessing the external bus, the DMA can use the other bus to access the RAM or peripheral function. CPU access conditions as disincentives against the DMA function are summarized as follows: Mark X in the table below is the blocking condition. DMA Peripheral function RAM CPU External bus USB RAM X O O O Peripheral function O X O O External bus O O X O USB O O O X O: The CPU and DMA are concurrently accessible. X: CPU access blocks DMA access. www.cypress.com Document No. 002-06375 Rev.*A 3 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 3 Number of DMA Transfer Cycles Described below is the number of DMA transfer cycles under each condition of data transfer routes. 3.1 Number of Peripheral Function -> DMA Transfer Cycles Minimum value: 1CCLK+2PCLK Maximum value: 3PCLK *) CCLK: CPU frequency PCLK: Peripheral function frequency CPU XBS DMA Flash memory Peripheral function RAM External bus Port USB Micro-computer Figure 2 Peripheral function -> DMA transfer 3.2 Number of DMA -> Peripheral Function Transfer Cycles Minimum value: 1CCLK+2PCLK Maximum value: 3PCLK *) CCLK: CPU frequency PCLK: Peripheral function frequency CPU XBS DMA Flash memory Peripheral function RAM External bus Port USB Micro-computer Figure 3 DMA -> Peripheral function transfer www.cypress.com Document No. 002-06375 Rev.*A 4 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 3.3 Number of RAM -> DMA Transfer Cycles 2CCLK *) CCLK: CPU frequency CPU DMA XBS Flash memory Peripheral function RAM External Port USB Micro-computer Figure 4 RAM -> DMA transfer 3.4 Number of DMA -> RAM Transfer Cycles 1CCLK *) CCLK: CPU frequency CPU DMA XBS Flash memory Peripheral function RAM External bus Port USB Micro-computer Figure 5 DMA -> RAM transfer www.cypress.com Document No. 002-06375 Rev.*A 5 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 3.5 Number of USB -> DMA Transfer Cycles Minimum value: 1CCLK *) CCLK: CPU frequency PCLK: Peripheral function frequency CPU DMA XBS Flash memory Peripheral function RAM External bus Port USB Micro-computer Figure 6 Peripheral function -> DMA transfer 3.6 Number of DMA -> USB Transfer Cycles Minimum value: 1CCLK *) CCLK: CPU frequency PCLK: Peripheral function frequency CPU DMA XBS Flash memory Peripheral function RAM External bus ポート USB Micro-computer Figure 7 DMA -> USB transfer www.cypress.com Document No. 002-06375 Rev.*A 6 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 3.7 Number of External Bus -> DMA Transfer Cycles Minimum value: 2TCLK+3CCLK Maximum value: 3TCLK+2CCLK *) CCLK: CPU frequency TCLK: External bus frequency CPU DMA XBS Flash memory Peripheral function RAM External bus Port External device USB Micro-computer Figure 8 External bus -> DMA transfer *) For the external bus, one external bus is accessed at 3TCLK. www.cypress.com Document No. 002-06375 Rev.*A 7 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 3.8 Number of DMA -> External Bus Transfer Cycles a) If 3TCLK – [Transfer source -> DMA cycles] < 0 1CCLK b) If 3TCLK – [Transfer source -> DMA cycles] = 0 1TCLK c) If 3TCLK – [Transfer source -> DMA cycles] = 1CCK Minimum value: 1CCLK Maximum value: 1TCLK+1CCLK d) If 3TCLK – [Transfer source -> DMA cycles] => 2CCLK 1CCLK or 3TCLK – [Transfer source -> DMA cycles] or 4TCLK – [Transfer source -> DMA cycle] *) CCLK: CPU frequency TCLK: External bus frequency *) [Transfer source -> DMA cycles]: Number of cycles for transfer from the transfer source to the DMA For example, if the transfer source is the RAM, the number of transfer cycles is 2CCLK according to the above table. *) For the external bus, one external bus is accessed at 3TCLK. However, since the external bus has a write buffer, data is written to the write buffer of the external bus at 1TCLK. Then, data written to the write buffer is written to the external device at 3TCLK. However, since there is only one write buffer, writing to the write buffer must wait until access to the external device is completed. Therefore, the number of cycles higher than 1TCLK is required. CPU DMA XBS Flash memory Peripheral function RAM External bus Port External device USB Micro-computer Figure 9 DMA -> External bus transfer www.cypress.com Document No. 002-06375 Rev.*A 8 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed The numbers of transfer cycles described above are summarized under respective conditions: Minimum value Peripheral function -> Maximum value 1CCLK+2PCLK 3PCLK 1CCLK+2PCLK 3PCLK Remarks DMA DMA -> Peripheral function RAM -> DMA 2CCLK DMA -> RAM 1CCLK USB -> DMA 1CCLK DMA -> USB 1CCLK External bus -> DMA 2TCLK+3CCLK DMA -> External bus 1CCLK If 3TCLK – [Transfer source -> DMA cycles] < 0 1TCLK If 3TCLK – [Transfer source -> DMA cycles] = 0 1CCLK 3TCLK+2CCLK 1TCLK+1CCLK If 3TCLK – [Transfer source -> DMA cycles] = 1CCLK 1CCLK If 3TCLK – [Transfer source -> DMA cycles] => 2CCLK 3TCLK – [Transfer source -> (For details, see the timing chart example.) DMA cycles] 3TCLK – [Transfer source -> DMA cycles] CCLK: CPU frequency PCLK: Peripheral function frequency TCLK: External bus frequency [Transfer source -> DMA cycles]: Number of cycles for transfer from the transfer source to the DMA For example, if the transfer source is the RAM, the number of transfer cycles is 2CCLK according to the above table. www.cypress.com Document No. 002-06375 Rev.*A 9 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 4 Calculation Examples The maximum and minimum values are obtained using the number of transfer cycles under each condition above and expression (1) in 2.1. 4.1 Peripheral Function -> DMA -> RAM The maximum value is calculated as follows: [DMA transfer cycles] = [Transfer source -> DMA cycles] + [DMA -> Transfer destination cycles] = 3PCLK + 1CCLK The minimum value is calculated as follows: [DMA transfer cycles] = [Transfer source -> DMA cycles] + [DMA -> Transfer destination cycles] = 1CCLK + 1CCLK + 2PCLK = 2CCLK + 2PCLK 4.2 RAM -> DMA -> Peripheral Function The maximum value is calculated as follows: [DMA transfer cycles] = [Transfer source -> DMA cycles] + [DMA -> Transfer destination cycles] = 2CCLK + 3PCLK The minimum value is calculated as follows: [DMA transfer cycles] = [Transfer source -> DMA cycles] + [DMA -> Transfer destination cycles] = 2CCLK + 1CCLK + 2PCLK = 3CCLK + 2PCLK 4.3 Peripheral Function -> DMA -> Peripheral Function The maximum value is calculated as follows: [DMA transfer cycles] = [Transfer source -> DMA cycles] + [DMA -> Transfer destination cycles] = 3PCLK + 3PCLK = 6PCLK The minimum value is calculated as follows: [DMA transfer cycles] = [Transfer source -> DMA cycles] + [DMA -> Transfer destination cycles] = 1CCLK + 2PCLK + 1CCLK + 2PCLK = 2CCLK + 4PCLK www.cypress.com Document No. 002-06375 Rev.*A 10 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 5 Timing Chart Examples Examples of the number of transfer cycles are shown below using the timing chart. However, these are examples of the number of transfer cycles, so use “3. Number of Transfer Cycles” above to obtain the number of transfer cycles. Since the contents are detailed, you need not read them. The audience are those who want to get deeper understanding on the DMA transfer cycles including the internal operation. 5.1 Peripheral Function -> DMA -> RAM ■If CCLK:PCLK=1:1 PCLK 1CCLK R-Bus access R1 R2 R3 R1 R2 R3 3PCLK (Peripheral function -> DMA) CCLK W1 Internal RAM access W1 1CCLK(DMA→RAM) ■If CCLK:PCLK=1:2 PCLK 1CCLK R-Bus access R1 R2 R3 R4 R5 R1 R2 R3 R4 R5 1CCLK+2PCLK (Peripheral function -> DMA) CCLK Internal RAM access W1 W1 1CCLK(DMA→RAM) www.cypress.com Document No. 002-06375 Rev.*A 11 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed ■If CCLK:PCLK=1:3 PCLK 1CCLK R-Bus access R1 R2 R3 R4 R5 R6 R7 R1 R8 R2 R3 R4 R5 R6 R7 R8 2CCLK+2PCLK (Peripheral function -> DMA) CCLK Internal RAM access W1 W1 1CCLK(DMA→RAM) www.cypress.com Document No. 002-06375 Rev.*A 12 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 5.2 RAM -> DMA -> Peripheral Function ■ If CCLK:PCLK=1:1 CCLK 1CCLK R1 Internal RAM access R2 R1 R2 R1 R2 2CCLK(RAM -> DMA) PCLK R-Bus access W1 W2 W3 W1 W2 W3 3PCLK(DMA -> Peripheral function) ■ If CCLK:PCLK=1:2 CCLK 1CCLK R1 Internal RAM access R2 R1 R2 R1 R2 2CCLK(RAM -> DMA) PCLK R-Bus access W2 W1 W3 W4 W5 W6 W1 W2 W3 W5 W4 W6 3PCLK(DMA -> Peripheral function) ■ If CCLK:PCLK=1:3 CCLK Internal RAM access 1CCLK R1 R2 R1 R2 R1 2CCLK(RAM -> DMA) PCLK R-Bus access W1 W2 W3 W4 W5 W6 W7 W1 W2 W3 W4 W5 W6 W7 1CCLK+2PCLK(DMA -> Peripheral function) www.cypress.com Document No. 002-06375 Rev.*A 13 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 5.3 Peripheral Function -> DMA -> Peripheral Function ■ If CCLK:PCLK=1:1 PCLK 1CCLK R-Bus access R1 R2 R3 W1 3PCLK (Peripheral function -> DMA) W2 W3 R2 R1 R3 3PCLK (DMA -> Peripheral function) CCLK ■ If CCLK:PCLK=1:2 PCLK 1CCLK R-Bus access R1 R2 R3 R4 R5 R6 3PCLK (Peripheral function -> DMA) W1 W2 W3 W4 W5 W6 R1 3PCLK (DMA -> Peripheral function) CCLK ■ If CCLK:PCLK=1:3 PCLK 1CCLK R-Bus access R1 R2 R3 R4 R5 R6 3PCLK(Peripheral function -> DMA) R7 R8 R9 W1 W2 W3 W4 W5 W6 W7 W8 W9 R1 3PCLK(DMA -> Peripheral function) CCLK www.cypress.com Document No. 002-06375 Rev.*A 14 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 5.4 RAM -> DMA -> RAM CCLK 1CCLK R1 Internal RAM access R2 W1 R1 R2 W1 R1 R2 W1 2CCLK(RAM -> DMA) 1CCLK(DMA -> RAM) 5.5 USB -> DMA -> RAM CCLK 1CCLK USB access R1 R1 R1 R1 R1 1CCLK(USB -> DMA) Internal RAM access W1 W1 W1 W1 1CCLK(DMA -> USB) 5.6 RAM -> DMA -> USB CCLK 1CCLK Internal RAM access USB access R1 R2 R1 2CCLK(RAM -> DMA) W1 R1 R2 W1 R2 W1 1CCLK(DMA -> USB) www.cypress.com Document No. 002-06375 Rev.*A 15 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 5.7 External bus -> DMA -> RAM ■ If CCLK:TCLK=1:1 TCLK CSnX ASX RDX 1CCLK External bus access R1 R3 R2 R4 R1 R5 R2 R3 R5 R4 2TCLK+3CCLK(External bus -> DMA) CCLK W1 W1 Internal RAM access 1CCLK(DMA -> RAM) ■ If CCLK:TCLK=1:2 TCLK CSnX ASX RDX External bus access 1CCLK R1 R2 R3 R4 R5 R6 R7 R1 R2 R3 R4 R5 R6 R7 2TCLK+3CCLK(External bus -> DMA) CCLK Internal RAM access W1 W1 1CCLK(DMA -> RAM) www.cypress.com Document No. 002-06375 Rev.*A 16 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed ■ If CCLK:TCLK=1:3 TCLK CSnX ASX RDX External bus access 1CCLK R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 3TCLK+2CCLK(External bus -> DMA) CCLK W1 Internal RAM access W1 1CCLK(DMA -> RAM) ■ If CCLK:TCLK=1:4 TCLK CSnX ASX RDX 1CCLK External bus access R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 2TCLK+3CCLK(External bus -> DMA) CCLK Internal RAM access W1 W1 1CCLK(DMA -> RAM) www.cypress.com Document No. 002-06375 Rev.*A 17 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 5.8 RAM -> DMA -> External Bus Since the write buffer is provided, data is read from the internal RAM during writing to ■ If CCLK:TCLK=1:1 CCLK 1CCLK Internal RAM access R1 R1 R2 2CCLK(RAM -> DMA) R1 R2 R1 R2 R1 R2 R2 2CCLK TCLK CSnX ASX WRnX 3TCLK(Write buffer -> External device) External bus access W1 1TCLK(DMA -> Write buffer) W1 3TCLK 3TCLK W2 W1 3TCLK W1 W2 W1 1CCLK+1TCLK Writing to the write buffer must wait until writing to the external device is completed. Data is written to the write buffer at 1TCLK. If 3TCLK - [Transfer source -> DMA cycles] = 1CCLK, writing takes "1CCLK" or "1CCLK+1TCLK". www.cypress.com Document No. 002-06375 Rev.*A 18 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed ■ If CCLK:TCLK=1:2 CCLK 1CCLK Internal RAM access R1 R1 R2 R1 R2 R1 R2 R2 2CCLK(RAM -> DMA) TCLK CSnX ASX WRnX 3TCLK(Write buffer -> External device) External bus access W1 1CCLK(DMA -> Write buffer) Data is written to the write buffer at 1TCLK. W1 W2 W3 W4 W5 W6 3TCLK(DMA -> Write buffer) W1 W2 W3 W4 W1 W2 W3 W4 2TCLK(DMA -> Write buffer) Writing to the write buffer must wait until writing to the external device is completed. If 3TCLK - [Transfer source -> DMA cycles] => 2CCLK, writing takes 1TCLK or "3TCLK - [Transfer source -> DMA cycles]" or "4TCLK - [Transfer source -> DMA cycles]". www.cypress.com Document No. 002-06375 Rev.*A 19 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed ■ If CCLK:TCLK=1:3 CCLK 1CCLK Internal RAM access R1 R2 R1 R2 R1 R2 2CCLK(RAM ->DMA) TCLK CSnX ASX WRnX 3TCLK(Write buffer -> External device) W1 External bus access W1 W2 W3 W4 W5 W6 W7 3TCLK W8 W9 W10 W2 W3 W4 W5 W6 W7 2TCLK+1CCLK(DMA -> Write buffer) 3TCLK+1CCLK(DMA -> Write buffer) 1CCLK(DMA -> Write buffer) W1 ■ If CCLK:TCLK=1:4 CCLK 1CCLK Internal RAM access R1 R2 R1 R2 R1 R2 2CCLK(RAM -> DMA) TCLK CSnX ASX WRnX 3TCLK(Write buffer -> External device) External bus access W1 1CCLK(DMA -> Write buffer) www.cypress.com W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W1 W2 3TCLK+2CCLK(DMA -> Write buffer) Document No. 002-06375 Rev.*A 20 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed 5.9 Peripheral Function -> DMA -> External Bus Since the write buffer is provided, data is read from the peripheral function during writing to the external bus. ■ If CCLK:TCLK:PCLK=1:1:1 PCLK R-Bus access R1 R2 R3 R1 R2 R3 R1 R2 R3 R1 R2 R3 3PCLK(Peripheral function -> DMA) TCLK CSnX ASX WRnX 3TCLK 3TCLK(Write buffer -> External device) External bus access W1 W1 W1 W1 1TCLK(DMA -> External bus) Data is written to the write buffer at 1TCLK. www.cypress.com If 3TCLK - [Transfer source -> DMA cycles] = 0, writing takes "1TCLK". Document No. 002-06375 Rev.*A 21 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed Since the write buffer is provided, data is read from the peripheral function during writing to the external buffer. ■ If CCLK:TCLK:PCLK=1:1:2 PCLK 1CCLK R-Bus access R1 R2 R3 R4 R5 R1 R2 R3 R4 R5 R1 R2 R3 R4 R5 R1 R2 R3 R4 R5 5CCLK(Peripheral function -> DMA) TCLK CSnX ASX WRnX 3TCLK(Write buffer -> External devic External bus access W1 W1 W1 W1 1CCLK(DMA -> Write buffer) If 3TCLK - [Transfer source -> DMA cycles] < 0, writing takes "1CCLK". Data is written to the write buffer at 1CCLK. ■ If CCLK:TCLK:PCLK=1:2:2 PCLK 1CCLK R-Bus access R1 R2 R3 R4 R5 R1 R2 R3 R4 R5 R1 R2 R3 R4 R5 R1 R2 R3 R4 R5 5CCLK(Peripheral function -> DMA) TCLK CSnX ASX WRnX 3TCLK 3TCLK(Write buffer -> External device) W1 External bus access 1CCLK(DMA -> Write buffer) W1 W2 W3 W1 1CCLK+1TCLK(DMA -> Write buffer) If 3TCLK - [Transfer source -> DMA cycles] = 1CCLK, writing takes "1CCLK" or "1CCLK+1TCLK". www.cypress.com Document No. 002-06375 Rev.*A 22 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed Document History Document Title: AN206375 - FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed Document Number: 002-06375 Revision ECN Orig. of Change Submission Date ** - YUIS 11/21/2008 First Edition *A 5293700 YUIS 06/02/2016 Migrated Spansion Application Note “AN07-00156-1E” to Cypress format. www.cypress.com Description of Change Document No. 002-06375 Rev.*A 23 FR Family, 32-Bit Microcontroller, FR80S/T-series DMA Access Speed Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. 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