PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Programmable System-on-Chip (PSoC) General Description PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4100S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S products will be upward compatible with members of the PSoC 4 platform for new applications and design needs. Features 32-bit MCU Subsystem Serial Communication ■ 48-MHz ARM Cortex-M0+ CPU ■ Up to 64 KB of flash with Read Accelerator ■ Up to 8 KB of SRAM ■ Timing and Pulse-Width Modulation Programmable Analog ■ Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode. ■ 12-bit 1-Msps SAR ADC with differential and single-ended modes, and Channel Sequencer with signal averaging ■ Single-slope 10-bit ADC function provided by a capacitance sensing block ■ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin ■ Two low-power comparators that operate in Deep Sleep low-power mode Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs Low-Power 1.71-V to 5.5-V Operation ■ ■ Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks ■ Center-aligned, Edge, and Pseudo-random modes ■ Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 36 Programmable GPIO Pins ■ 48-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball WLCSP packages ■ Any GPIO pin can be CapSense, analog, or digital ■ Drive modes, strengths, and slew rates are programmable PSoC Creator Design Environment Programmable Digital ■ Three independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI, or UART functionality Deep Sleep mode with operational analog and 2.5-A digital system current Capacitive Sensing ■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance ■ Cypress-supplied software component makes capacitive sensing design easy ■ Automatic hardware tuning (SmartSense™) ■ Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing) ■ Applications Programming Interface (API) component for all fixed-function and programmable peripherals Industry-Standard Tool Compatibility ■ After schematic entry, development can be done with ARM-based industry-standard development tools LCD Drive Capability ■ LCD segment drive capability on GPIOs Cypress Semiconductor Corporation Document Number: 002-00122 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 15, 2016 PRELIMINARY PSoC® 4: PSoC 4100S Family Datasheet Contents Functional Definition........................................................ 4 CPU and Memory Subsystem ..................................... 4 System Resources ...................................................... 4 Analog Blocks.............................................................. 5 Fixed Function Digital.................................................. 5 GPIO ........................................................................... 6 Special Function Peripherals....................................... 6 Pinouts .............................................................................. 7 Alternate Pin Functions ............................................... 9 Power............................................................................... 11 Mode 1: 1.8 V to 5.5 V External Supply .................... 11 Mode 2: 1.8 V ±5% External Supply.......................... 11 Development Support .................................................... 12 Documentation .......................................................... 12 Online ........................................................................ 12 Tools.......................................................................... 12 Electrical Specifications ................................................ 13 Absolute Maximum Ratings....................................... 13 Device Level Specifications....................................... 13 Analog Peripherals .................................................... 17 Digital Peripherals ..................................................... 25 Document Number: 002-00122 Rev. *E Memory ..................................................................... System Resources .................................................... Ordering Information...................................................... Packaging........................................................................ Package Diagrams .................................................... Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Errata ............................................................................... Part Numbers Affected .............................................. PSoC 4000S Qualification Status.............................. PSoC 4000S Errata Summary .................................. Revision History ............................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC® Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... 28 28 31 33 34 36 38 38 39 39 39 39 40 41 41 41 41 41 41 Page 2 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Figure 1. Block Diagram CPU Subsystem SWD/TC 32-bit 48 MHz System Resources Lite SRAM Controller ROM 8 KB ROM Controller Peripherals SAR ADC (12-bit) x1 SARMUX WCO Programmable Analog 2x LP Comparator Peripheral Interconnect (MMIO) PCLK 3x SCB-I2C/SPI/UART Test TestMode Entry Digital DFT Analog DFT Read Accelerator CapSense Reset Reset Control XRES SRAM 8 KB System Interconnect (Single Layer AHB) IOSS GPIO (5x ports) Clock Clock Control WDT ILO IMO FLASH 64 KB FAST MUL NVIC, IRQMUX AHB- Lite Power Sleep Control WIC POR REF PWRSYS SPCIF Cortex M0+ 5x TCPWM PSoC 4100S Architecture CTBm x1 2x Opamp High Speed I/O Matrix & 2 x Programmable I/O Power Modes Active/ Sleep DeepSleep 36x GPIOs, LCD I/O Subsystem PSoC 4100S devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. The ARM Serial-Wire Debug (SWD) interface supports all programming and debug features of the device. Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator IDE provides fully integrated programming and debug support for the PSoC 4100S devices. The SWD interface is fully compatible with industry-standard third-party tools. The PSoC 4100S family provides a level of security not possible with multi-chip application solutions or with microcontrollers. It has the following advantages: ■ Allows disabling of debug features ■ Robust flash protection ■ Allows customer-proprietary functionality to be implemented in on-chip programmable blocks Document Number: 002-00122 Rev. *E The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the firmware thus providing security. Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. Therefore, PSoC 4100S, with device security enabled, may not be returned for failure analysis. This is a trade-off the PSoC 4100S allows the customer to make. Page 3 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Functional Definition between different clock sources without glitching. In addition, the clock system ensures that there are no metastable conditions. CPU and Memory Subsystem The clock system for the PSoC 4100S consists of the internal main oscillator (IMO), internal low-frequency oscillator (ILO), a 32 kHz Watch Crystal Oscillator (WCO) and provision for an external clock. Clock dividers are provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to enable clocking of higher data rates for UARTs. CPU The Cortex-M0+ CPU in the PSoC 4100S is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of the Thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the processor from Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode. Figure 2. PSoC 4100S MCU Clocking Architecture IMO Divide By 2,4,8 HFCLK External Clock The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG. The debug configuration used for PSoC 4100S has four breakpoint (address) comparators and two watchpoint (data) comparators. ILO LFCLK Flash The PSoC 4100S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS) access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. HFCLK Prescaler Integer Dividers Fractional Dividers SYSCLK 6X 16-bit 2X 16.5-bit SROM The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals. There are eight clock dividers for the PSoC 4100S; two of those are fractional dividers. The 16-bit capability allows flexible generation of fine-grained frequency values and is fully supported in PSoC Creator An 8 KB supervisory ROM that contains boot and configuration routines is provided. IMO Clock Source SRAM Eight KB of SRAM are provided with zero wait-state access at 48 MHz. System Resources Power System The power system is described in detail in the section Power on page 11. It provides assurance that voltage levels are as required for each respective mode and either delays mode entry (for example, on power-on reset (POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detection). The PSoC 4100S operates with a single external supply over the range of either 1.8 V ±5% (externally regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which are managed by the power system. The PSoC 4100S provides Active, Sleep, and Deep Sleep low-power modes. All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes 35 µs. The opamps can remain operational in Deep Sleep mode. Clock System The PSoC 4100S clock system is responsible for providing clocks to all subsystems that require clocks and for switching Document Number: 002-00122 Rev. *E The IMO is the primary source of internal clocking in the PSoC 4100S. It is trimmed during testing to achieve the specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance with Cypress-provided calibration settings is ±2%. ILO Clock Source The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. Watch Crystal Oscillator (WCO) The PSoC 4100S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can be used for precision timing applications. Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is recorded in a Reset Cause register, which is firmware readable. Page 4 of 41 PRELIMINARY Reset The PSoC 4100S can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled. Analog Blocks 12-bit SAR ADC The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion. PSoC® 4: PSoC 4100S Family Datasheet Buffers, Filters, Trans-Impedance Amplifiers, and other functions can be realized, in some cases with external passives. saving power, cost, and space. The on-chip opamps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without requiring external buffering. Low-power Comparators (LPC) The PSoC 4100S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event. The LPC outputs can be routed to pins. The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier. Current DACs The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware driven switching. A feature provided by the sequencer is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying source impedance and frequency, it is possible to have different sample times programmable for each channel. Also, signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. The PSoC 4100S has two concentric independent buses that go around the periphery of the chip. These buses (called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal resources (IDACs, comparator) to connect to any pin on the I/O Ports. The SAR is not available in Deep Sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating range is 1.71 V to 5.5 V. Figure 3. SAR ADC AHB System Bus and Programmable Logic Interconnect SAR Sequencer vminus vplus P7 Port 2 (8 inputs) SARMUX P0 Sequencing and Control Data and Status Flags POS SARADC NEG External Reference and Bypass (optional ) Reference Selection VDD/2 VDDD VREF Inputs from other Ports Two Opamps (Continuous-Time Block; CTB) The PSoC 4100S has two opamps with Comparator modes which allow most common analog functions to be performed on-chip eliminating external components; PGAs, Voltage Document Number: 002-00122 Rev. *E The PSoC 4100S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable current ranges. Analog Multiplexed Buses Programmable Digital Blocks The Programmable I/O (PRGIO will be branded Smart I/O pending legal clearance) block is a fabric of switches and LUTs that allows Boolean functions to be performed in signals being routed to the pins of a GPIO port. The PRGIO can perform logical operations on input pins to the chip and on signals going out as outputs. Fixed Function Digital Timer/Counter/PWM (TCPWM) Block The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register to record the count value at the time of an event (which may be an I/O event), a period register that is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as dead-band programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC 4100S. Serial Communication Block (SCB) The PSoC 4100S has three serial communication blocks, which can be programmed to have SPI, I2C, or UART functionality. I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multi-master arbitration). This block is capable of operating at speeds of up to 400 kbps (Fast Mode) and has flexible buffering options to Page 5 of 41 PRELIMINARY reduce interrupt overhead and latency for the CPU. It also supports EZI2C that creates a mailbox address range in the memory of the PSoC 4100S and effectively reduces I2C communication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The I2C peripheral is compatible with the I2C Standard-mode and Fast-mode devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. The PSoC 4100S is not completely compliant with the I2C spec in the following respect: ■ GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO. GPIO The PSoC 4100S has up to 36 GPIOs. The GPIO block implements the following: ■ Eight drive modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL). ■ Individual control of input and output buffer enabling/disabling in addition to the drive strength modes ■ Selectable slew rates for dV/dt related noise control to improve EMI The pins are organized in logical entities called ports, which are 8-bit in width (less for Ports 2 and 3). During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Document Number: 002-00122 Rev. *E PSoC® 4: PSoC 4100S Family Datasheet Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4100S). Special Function Peripherals CapSense CapSense is supported in the PSoC 4100S through a CapSense Sigma-Delta (CSD) block that can be connected to any pins through an analog multiplex bus via analog switches. CapSense function can thus be provided on any available pin or group of pins in a system under software control. A PSoC Creator component is provided for the CapSense block to make it easy for the user. Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Proximity sensing can also be implemented. The CapSense block has two IDACs, which can be used for general purposes if CapSense is not being used (both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available). The CapSense block also provides a 10-bit Slope ADC function which can be used in conjunction with the CapSense function. The CapSense block is an advanced, low-noise, programmable block with programmable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and ground to null out power-supply related noise. LCD Segment Drive The PSoC 4100S has an LCD controller, which can drive up to 4 commons and up to 32 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as Digital Correlation and PWM. Digital Correlation pertains to modulating the frequency and drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port). Page 6 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Pinouts The following table provides the pin list for PSoC 4100S for the 48-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball CSP packages. All port pins support GPIO. Table 1. Pin List 48-TQFP 40-QFN 32-QFN 35-CSP Pin Name Pin Name Pin Name Pin Name 28 P0.0 22 P0.0 17 P0.0 C3 P0.0 29 P0.1 23 P0.1 18 P0.1 A5 P0.1 30 P0.2 24 P0.2 19 P0.2 A4 P0.2 31 P0.3 25 P0.3 20 P0.3 A3 P0.3 32 P0.4 26 P0.4 21 P0.4 B3 P0.4 33 P0.5 27 P0.5 22 P0.5 A6 P0.5 34 P0.6 28 P0.6 23 P0.6 B4 P0.6 35 P0.7 29 P0.7 B5 P0.7 36 XRES 30 XRES 24 XRES B6 XRES 37 VCCD 31 VCCD 25 VCCD A7 VCCD 38 VSSD DN VSSD 26 VSSD 39 VDDD 32 VDDD 40 VDDA 33 VDDA 27 41 VSSA 34 VSSA 28 42 P1.0 35 P1.0 29 43 P1.1 36 P1.1 30 44 P1.2 37 P1.2 45 P1.3 38 P1.3 46 P1.4 39 P1.4 47 P1.5 B7 VSS C7 VDD VDD C7 VDD VSSA B7 VSS P1.0 C4 P1.0 P1.1 C5 P1.1 31 P1.2 C6 P1.2 32 P1.3 D7 P1.3 D4 P1.4 D5 P1.5 48 P1.6 1 P1.7/VREF 40 P1.7/VREF 1 P1.7/VREF D6 P1.6 E7 P1.7/VREF 2 P2.0 1 P2.0 2 P2.0 3 P2.1 2 P2.1 3 P2.1 4 P2.2 3 P2.2 4 5 P2.3 4 P2.3 5 P2.2 D3 P2.2 P2.3 E4 P2.3 6 P2.4 5 P2.4 7 P2.5 6 P2.5 6 P2.5 E5 P2.4 E6 P2.5 8 P2.6 7 P2.6 7 9 P2.7 8 P2.7 8 P2.6 E3 P2.6 P2.7 E2 P2.7 10 VSSD 9 VSSD 12 P3.0 10 P3.0 9 P3.0 E1 P3.0 13 P3.1 11 14 P3.2 12 P3.1 10 P3.1 D2 P3.1 P3.2 11 P3.2 D1 P3.2 16 P3.3 17 P3.4 13 P3.3 12 P3.3 C1 P3.3 14 P3.4 C2 P3.4 18 19 P3.5 15 P3.5 P3.6 16 P3.6 Document Number: 002-00122 Rev. *E Page 7 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 1. Pin List (continued) 48-TQFP 40-QFN Pin Name Pin Name 20 P3.7 17 P3.7 21 VDDD 22 P4.0 18 23 P4.1 24 P4.2 25 P4.3 32-QFN 35-CSP Pin Name Pin Name P4.0 13 P4.0 B1 P4.0 19 P4.1 14 P4.1 B2 P4.1 20 P4.2 15 P4.2 A2 P4.2 21 P4.3 16 P4.3 A1 P4.3 Note: Pins 11, 15, 26, and 27 are No Connects (NC) on the 48-pin TQFP. Descriptions of the Power pins are as follows: VDDD: Power supply for the digital section. VDDA: Power supply for the analog section. VSSD, VSSA: Ground pins for the digital and analog sections respectively. VCCD: Regulated digital supply (1.8 V ±5%) Document Number: 002-00122 Rev. *E Page 8 of 41 PRELIMINARY PSoC® 4: PSoC 4100S Family Datasheet Alternate Pin Functions Each Port pin has can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin assignments are shown in the following table. PRGIO will be branded Smart I/O pending legal clearance. Port/Pin Analog Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 Deep Sleep 2 P0.0 lpcomp.in_p[0] P0.1 lpcomp.in_n[0] tcpwm.tr_in[0] scb[2].i2c_scl:0 scb[0].spi_select1:0 tcpwm.tr_in[1] scb[2].i2c_sda:0 scb[0].spi_select2:0 P0.2 lpcomp.in_p[1] scb[0].spi_select3:0 P0.3 lpcomp.in_n[1] scb[2].spi_select0 P0.4 wco.wco_in scb[1].uart_rx:0 scb[2].uart_rx:0 scb[1].i2c_scl:0 scb[1].spi_mosi:1 P0.5 wco.wco_out scb[1].uart_tx:0 scb[2].uart_tx:0 scb[1].i2c_sda:0 scb[1].spi_miso:1 scb[2].uart_tx:1 P0.6 srss.ext_clk scb[1].uart_cts:0 P0.7 tcpwm.line[0]:2 scb[1].uart_rts:0 scb[1].spi_clk:1 scb[1].spi_select0:1 P1.0 ctb0_oa0+ tcpwm.line[2]:1 scb[0].uart_rx:1 scb[0].i2c_scl:0 scb[0].spi_mosi:1 P1.1 ctb0_oa0- tcpwm.line_compl[2]:1 scb[0].uart_tx:1 scb[0].i2c_sda:0 scb[0].spi_miso:1 P1.2 ctb0_oa0_out tcpwm.line[3]:1 scb[0].uart_cts:1 tcpwm.tr_in[2] scb[2].i2c_scl:1 scb[0].spi_clk:1 P1.3 ctb0_oa1_out tcpwm.line_compl[3]:1 scb[0].uart_rts:1 tcpwm.tr_in[3] scb[2].i2c_sda:1 scb[0].spi_select0:1 P1.4 ctb0_oa1- scb[0].spi_select1:1 P1.5 ctb0_oa1+ scb[0].spi_select2:1 P1.6 ctb0_oa0+ scb[0].spi_select3:1 P1.7 ctb0_oa1+ sar_ext_vref0 sar_ext_vref1 scb[2].spi_clk P2.0 sarmux[0] prgio[0].io[0] tcpwm.line[4]:0 P2.1 sarmux[1] prgio[0].io[1] tcpwm.line_compl[4]:0 P2.2 sarmux[2] prgio[0].io[2] scb[1].spi_clk:2 P2.3 sarmux[3] prgio[0].io[3] scb[1].spi_select0:2 Document Number: 002-00122 Rev. *E csd.comp tcpwm.tr_in[4] scb[1].i2c_scl:1 scb[1].spi_mosi:2 tcpwm.tr_in[5] scb[1].i2c_sda:1 scb[1].spi_miso:2 Page 9 of 41 PRELIMINARY Alternate Function 2 PSoC® 4: PSoC 4100S Family Datasheet Port/Pin Analog Smart I/O Alternate Function 1 P2.4 sarmux[4] prgio[0].io[4] tcpwm.line[0]:1 Alternate Function 3 Deep Sleep 1 Deep Sleep 2 P2.5 sarmux[5] prgio[0].io[5] tcpwm.line_compl[0]:1 scb[1].spi_select2:1 P2.6 sarmux[6] prgio[0].io[6] tcpwm.line[1]:1 scb[1].spi_select3:1 P2.7 sarmux[7] scb[1].spi_select1:1 prgio[0].io[7] tcpwm.line_compl[1]:1 lpcomp.comp[0]:1 scb[2].spi_mosi P3.0 prgio[1].io[0] tcpwm.line[0]:0 scb[1].uart_rx:1 scb[1].i2c_scl:2 scb[1].spi_mosi:0 P3.1 prgio[1].io[1] tcpwm.line_compl[0]:0 scb[1].uart_tx:1 scb[1].i2c_sda:2 scb[1].spi_miso:0 P3.2 prgio[1].io[2] tcpwm.line[1]:0 scb[1].uart_cts:1 cpuss.swd_data scb[1].spi_clk:0 P3.3 prgio[1].io[3] tcpwm.line_compl[1]:0 scb[1].uart_rts:1 cpuss.swd_clk scb[1].spi_select0:0 P3.4 prgio[1].io[4] tcpwm.line[2]:0 P3.5 prgio[1].io[5] tcpwm.line_compl[2]:0 P3.6 prgio[1].io[6] tcpwm.line[3]:0 P3.7 prgio[1].io[7] tcpwm.line_compl[3]:0 tcpwm.tr_in[6] scb[1].spi_select1:0 scb[1].spi_select2:0 scb[1].spi_select3:0 lpcomp.comp[1]:1 scb[2].spi_miso P4.0 csd.vref_ext scb[0].uart_rx:0 scb[0].i2c_scl:1 scb[0].spi_mosi:0 P4.1 csd.cshieldpads scb[0].uart_tx:0 scb[0].i2c_sda:1 scb[0].spi_miso:0 P4.2 csd.cmodpad scb[0].uart_cts:0 lpcomp.comp[0]:0 scb[0].spi_clk:0 P4.3 csd.csh_tank scb[0].uart_rts:0 lpcomp.comp[1]:0 scb[0].spi_select0:0 Document Number: 002-00122 Rev. *E Page 10 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Power Mode 1: 1.8 V to 5.5 V External Supply In this mode, the PSoC 4100S is powered by an external power supply that can be anywhere in the range of 1.8 to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the PSoC 4100S supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else. The following power system diagram shows the set of power supply pins as implemented for the PSoC 4100S. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the VDD input. Figure 4. Power Supply Connections VDDA VDDD VDDA VSSA Analog Domain VDDD Mode 2: 1.8 V ±5% External Supply VSSD In this mode, the PSoC 4100S is powered by an external power supply that must be within the range of 1.71 to 1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins are shorted together and bypassed. The internal regulator can be disabled in the firmware. Digital Domain 1.8 Volt Regulator Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. VCCD There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5% (externally regulated; 1.71 to 1.89, internal regulator bypassed). An example of a bypass scheme is shown in the following diagram. Figure 5. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active Power supply bypass connections example 1.8V to 5.5V VDD PSoC 4100S 1.8V to 5.5V VDDA F 0.1F 0.1F VCCD 0.1F VSS Document Number: 002-00122 Rev. *E Page 11 of 41 PRELIMINARY PSoC® 4: PSoC 4100S Family Datasheet Development Support The PSoC 4100S family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/go/psoc4 to find out more. Documentation A suite of documentation supports the PSoC 4100S family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers. The TRM is available in the Documentation section at www.cypress.com/psoc4. Online In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week. Tools With industry standard cores, programming, and debugging interfaces, the PSoC 4100S family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Document Number: 002-00122 Rev. *E Page 12 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Electrical Specifications Absolute Maximum Ratings Table 2. Absolute Maximum Ratings[1] Spec ID# Parameter Description Min Typ Max Units Details/ Conditions VDDD_ABS Digital supply relative to VSS –0.5 – 6 SID2 VCCD_ABS Direct digital core voltage input relative to VSS –0.5 – 1.95 SID3 VGPIO_ABS GPIO voltage –0.5 – VDD+0.5 – SID4 IGPIO_ABS Maximum current per GPIO –25 – 25 – SID5 IGPIO_injection GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS –0.5 – 0.5 BID44 ESD_HBM Electrostatic discharge human body model 2200 – – SID1 – V mA – Current injected per pin – V BID45 ESD_CDM Electrostatic discharge charged device model 500 – – BID46 LU Pin current for latch-up –140 – 140 – mA – Device Level Specifications All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 3. DC Specifications Typical values measured at VDD = 3.3 V and 25 °C. Spec ID# Parameter Description Min Typ Max SID53 VDD Power supply input voltage 1.8 – 5.5 SID255 VDD Power supply input voltage (VCCD = VDDD = VDDA) 1.71 – 1.89 SID54 VCCD Output voltage (for core logic) – 1.8 – SID55 CEFC External regulator voltage bypass – 0.1 – SID56 CEXC Power supply bypass capacitor – 1 – Units Details/ Conditions Internally regulated supply V Internally unregulated supply – µF X5R ceramic or better X5R ceramic or better Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C. SID10 IDD5 Execute from flash; CPU at 6 MHz – 2 – SID16 IDD8 Execute from flash; CPU at 24 MHz – 5.6 – SID19 IDD11 Execute from flash; CPU at 48 MHz – 10.4 – – 1.1 – – 3.1 – – – mA – Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on) SID22 SID25 IDD17 IDD20 I2C wakeup WDT, and Comparators on 2 I C wakeup, WDT, and Comparators on. mA 6 MHz 12 MHz Note 1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 002-00122 Rev. *E Page 13 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 3. DC Specifications (continued) Typical values measured at VDD = 3.3 V and 25 °C. Spec ID# Parameter Description Details/ Conditions Min Typ Max Units – 1.1 – mA 6 MHz – 3.1 – mA 12 MHz – 2.5 – µA – – 2.5 – µA – Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed) SID28 SID28A IDD23 IDD23A I2C wakeup, WDT, and Comparators on 2 I C wakeup, WDT, and Comparators on Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on) SID31 IDD26 I2C wakeup and WDT on Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on) SID34 IDD29 I2C wakeup and WDT on Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed) SID37 IDD32 I2C wakeup and WDT on – 2.5 – µA – IDD_XR Supply current while XRES asserted – 2 5 mA – Min Typ Max Units DC – 48 MHz XRES Current SID307 Table 4. AC Specifications Spec ID# Parameter Description FCPU CPU frequency SID49 TSLEEP Wakeup from Sleep mode – 0 – SID50[3] TDEEPSLEEP Wakeup from Deep Sleep mode – 35 – SID48 [3] Details/ Conditions 1.71 VDD 5.5 µs Note 2. Guaranteed by characterization. Document Number: 002-00122 Rev. *E Page 14 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY GPIO Table 5. GPIO DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID57 VIH[3] Input voltage high threshold 0.7 VDDD – – CMOS Input SID58 VIL Input voltage low threshold – – CMOS Input SID241 VIH[3] LVTTL input, VDDD < 2.7 V 0.7 VDDD 0.3 VDDD – – – SID242 VIL LVTTL input, VDDD < 2.7 V – – 0.3 VDDD – SID243 VIH[3] LVTTL input, VDDD 2.7 V 2.0 – – – SID244 VIL LVTTL input, VDDD 2.7 V – – 0.8 SID59 VOH Output voltage high level VDDD –0.6 – – IOH = 4 mA at 3 V VDDD SID60 VOH Output voltage high level VDDD –0.5 – – IOH = 1 mA at 1.8 V VDDD SID61 VOL Output voltage low level – – 0.6 IOL = 4 mA at 1.8 V VDDD SID62 VOL Output voltage low level – – 0.6 IOL = 10 mA at 3 V VDDD SID62A VOL Output voltage low level – – 0.4 IOL = 3 mA at 3 V VDDD SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 SID65 IIL Input leakage current (absolute value) – – 2 nA SID66 CIN Input capacitance – – 7 pF – mV VDD < 4.5 V [4] V kΩ – – – 25 °C, VDDD = 3.0 V VDDD 2.7 V SID67 VHYSTTL Input hysteresis LVTTL 25 40 – SID68[4] VHYSCMOS Input hysteresis CMOS 0.05 × VDDD – – SID68A[4] VHYSCMOS5V5 Input hysteresis CMOS 200 – – SID69[4] IDIODE Current through protection diode to VDD/VSS – – 100 µA – SID69A[4] ITOT_GPIO Maximum total source or sink chip current – – 200 mA – VDD > 4.5 V Table 6. GPIO AC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Min Typ Max SID70 TRISEF Rise time in fast strong mode 2 – 12 SID71 TFALLF Fall time in fast strong mode 2 – 12 SID72 TRISES Rise time in slow strong mode 10 – 60 Units ns – Details/ Conditions 3.3 V VDDD, Cload = 25 pF 3.3 V VDDD, Cload = 25 pF 3.3 V VDDD, Cload = 25 pF Notes 3. VIH must not exceed VDDD + 0.2 V. 4. Guaranteed by characterization. Document Number: 002-00122 Rev. *E Page 15 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 6. GPIO AC Specifications (Guaranteed by Characterization) (continued) Spec ID# Parameter Description Min Typ Max Units – Details/ Conditions 3.3 V VDDD, Cload = 25 pF SID73 TFALLS Fall time in slow strong mode 10 – 60 SID74 FGPIOUT1 GPIO FOUT; 3.3 V VDDD 5.5 V Fast strong mode – – 33 90/10%, 25 pF load, 60/40 duty cycle SID75 FGPIOUT2 GPIO FOUT; 1.71 VVDDD3.3 V Fast strong mode – – 16.7 90/10%, 25 pF load, 60/40 duty cycle SID76 FGPIOUT3 GPIO FOUT; 3.3 V VDDD 5.5 V Slow strong mode – – 7 SID245 FGPIOUT4 GPIO FOUT; 1.71 V VDDD 3.3 V Slow strong mode. – – 3.5 90/10%, 25 pF load, 60/40 duty cycle SID246 FGPIOIN GPIO input operating frequency; 1.71 V VDDD 5.5 V – – 48 90/10% VIO MHz 90/10%, 25 pF load, 60/40 duty cycle XRES Table 7. XRES DC Specifications Spec ID# Parameter Description Min Typ Max Units SID77 VIH Input voltage high threshold 0.7 × VDDD – – SID78 VIL Input voltage low threshold – – 0.3 VDDD SID79 RPULLUP Pull-up resistor – 60 SID80 CIN Input capacitance – SID81[5] VHYSXRES Input voltage hysteresis SID82 IDIODE Current through protection diode to VDD/VSS Details/ Conditions V CMOS Input – kΩ – – 7 pF – – 100 – mV Typical hysteresis is 200 mV for VDD > 4.5 V – – 100 µA Table 8. XRES AC Specifications Spec ID# SID83[5] [5] BID194 Parameter Description Min Typ Max Units Details/ Conditions TRESETWIDTH Reset pulse width 1 – – µs – TRESETWAKE Wake-up time from reset release – – 2.7 ms – Note 5. Guaranteed by characterization. Document Number: 002-00122 Rev. *E Page 16 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Analog Peripherals Table 9. CTBm Opamp Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions IDD Opamp block current, External load SID269 IDD_HI power=hi – 1100 1850 SID270 IDD_MED power=med – 550 950 – SID271 IDD_LOW power=lo – 150 350 – GBW Load = 20 pF, 0.1 mA VDDA = 2.7 V SID272 GBW_HI power=hi 6 – – SID273 GBW_MED power=med 3 – – SID274 GBW_LO power=lo – 1 – Input and output are 0.2 V to VDDA-0.2 V IOUT_MAX VDDA = 2.7 V, 500 mV from rail SID275 IOUT_MAX_HI power=hi 10 – – Output is 0.5 V VDDA-0.5 V SID276 IOUT_MAX_MID power=mid 10 – – SID277 IOUT_MAX_LO power=lo – 5 – Output is 0.5 V VDDA-0.5 V IOUT VDDA = 1.71 V, 500 mV from rail SID278 IOUT_MAX_HI power=hi 4 – – Output is 0.5 V VDDA-0.5 V SID279 IOUT_MAX_MID power=mid 4 – – SID280 IOUT_MAX_LO power=lo – 2 – IDD_Int Opamp block current Internal Load SID269_I IDD_HI_Int power=hi – 1500 1700 SID270_I IDD_MED_Int power=med – 700 900 IDD_LOW_Int power=lo – – – – GBW VDDA = 2.7 V – – – – GBW_HI_Int power=hi 8 – – – µA Input and output are 0.2 V to VDDA-0.2 V MHz mA mA Input and output are 0.2 V to VDDA-0.2 V Output is 0.5 V VDDA-0.5 V Output is 0.5 V VDDA-0.5 V Output is 0.5 V VDDA-0.5 V – µA – SID271_I SID272_I Document Number: 002-00122 Rev. *E MHz Output is 0.25 V to VDDA-0.25 V Page 17 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 9. CTBm Opamp Specifications (continued) Spec ID# Parameter Description Min Typ Max – VDDA-0.2 Details/ Conditions Units General opamp specs for both internal and external modes – VIN Charge-pump on, VDDA = 2.7 V –0.05 VCM Charge-pump on, VDDA = 2.7 V –0.05 – VDDA-0.2 – VOUT VDDA = 2.7 V SID283 VOUT_1 power=hi, Iload=10 mA 0.5 – VDDA -0.5 – SID284 VOUT_2 power=hi, Iload=1 mA 0.2 – VDDA -0.2 SID285 VOUT_3 power=med, Iload=1 mA 0.2 – VDDA -0.2 SID286 VOUT_4 power=lo, Iload=0.1 mA 0.2 – VDDA -0.2 – SID288 VOS_TR Offset voltage, trimmed –1.0 0.5 1.0 High mode, input 0 V to VDDA-0.2 V SID288A VOS_TR Offset voltage, trimmed – 1 – SID288B VOS_TR Offset voltage, trimmed – 2 – SID290 VOS_DR_TR Offset voltage drift, trimmed –10 3 10 SID290A VOS_DR_TR Offset voltage drift, trimmed – 10 – SID290B VOS_DR_TR Offset voltage drift, trimmed – 10 – SID291 CMRR DC 70 80 – SID281 SID282 V mV PSRR – Medium mode, input 0 V to VDDA-0.2 V Low mode, input 0 V to VDDA-0.2 V µV/C High mode Medium mode µV/C Low mode Input is 0 V to VDDA-0.2 V, Output is 0.2 V to VDDA-0.2 V dB SID292 – V At 1 kHz, 10-mV ripple 70 85 – VDDD = 3.6 V, high-power mode, input is 0.2 V to VDDA-0.2 V 3 Noise SID294 VN2 Input-referred, 1 kHz, power=Hi – 72 – SID295 VN3 Input-referred, 10 kHz, power=Hi – 28 – Input and output are nV/rtHz at 0.2 V to V DDA-0.2 V SID296 VN4 Input-referred, 100 kHz, power=Hi – 15 – Input and output are at 0.2 V to VDDA-0.2 V SID297 CLOAD Stable up to max. load. Performance specs at 50 pF. – – 125 pF – SID298 SLEW_RATE Cload = 50 pF, Power = High, VDDA = 2.7 V 6 – – V/µs – Document Number: 002-00122 Rev. *E Page 18 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 9. CTBm Opamp Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions – SID299 T_OP_WAKE From disable to enable, no external RC dominating – – 25 µs SID299A OL_GAIN Open Loop Gain – 90 – dB COMP_MODE Comparator mode; 50 mV drive, Trise=Tfall (approx.) SID300 TPD1 Response time; power=hi – 150 – SID301 TPD2 Response time; power=med – 500 – SID302 TPD3 Response time; power=lo – 2500 – SID303 VHYST_OP Hysteresis – 10 – mV – SID304 WUP_CTB Wake-up time from Enabled to Usable – – 25 µs – Deep Sleep Mode Mode 2 is lowest current range. Mode 1 has higher GBW. SID_DS_1 IDD_HI_M1 Mode 1, High current – 1400 – 25 °C SID_DS_2 IDD_MED_M1 Mode 1, Medium current – 700 – 25 °C SID_DS_3 IDD_LOW_M1 Mode 1, Low current – 200 – Input is 0.2 V to VDDA-0.2 V ns Input is 0.2 V to VDDA-0.2 V Input is 0.2 V to VDDA-0.2 V 25 °C µA SID_DS_4 IDD_HI_M2 Mode 2, High current – 120 – 25 °C SID_DS_5 IDD_MED_M2 Mode 2, Medium current – 60 – 25 °C SID_DS_6 IDD_LOW_M2 Mode 2, Low current – 15 – 25 °C Document Number: 002-00122 Rev. *E Page 19 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 9. CTBm Opamp Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID_DS_7 GBW_HI_M1 Mode 1, High current – 4 – 20-pF load, no DC load 0.2 V to VDDA-0.2 V SID_DS_8 GBW_MED_M1 Mode 1, Medium current – 2 – 20-pF load, no DC load 0.2 V to VDDA-0.2 V SID_DS_9 GBW_LOW_M! Mode 1, Low current – 0.5 – 20-pF load, no DC load 0.2 V to VDDA-0.2 V MHz SID_DS_10 GBW_HI_M2 Mode 2, High current – 0.5 – 20-pF load, no DC load 0.2 V to VDDA-0.2 V SID_DS_11 GBW_MED_M2 Mode 2, Medium current – 0.2 – 20-pF load, no DC load 0.2 V to VDDA-0.2 V SID_DS_12 GBW_Low_M2 Mode 2, Low current – 0.1 – 20-pF load, no DC load 0.2 V to VDDA-0.2 V SID_DS_13 VOS_HI_M1 Mode 1, High current – 5 – With trim 25 °C, 0.2 V to VDDA-0.2 V SID_DS_14 VOS_MED_M1 Mode 1, Medium current – 5 – With trim 25 °C, 0.2 V to VDDA-0.2 V SID_DS_15 VOS_LOW_M2 Mode 1, Low current – 5 – With trim 25 °C, 0.2 V to VDDA-0.2 V SID_DS_16 VOS_HI_M2 Mode 2, High current – 5 – With trim 25 °C, 0.2V to VDDA-0.2 V SID_DS_17 VOS_MED_M2 Mode 2, Medium current – 5 – With trim 25 °C, 0.2 V to VDDA-0.2 V SID_DS_18 VOS_LOW_M2 Mode 2, Low current – 5 – With trim 25 °C, 0.2 V to VDDA-0.2 V SID_DS_19 IOUT_HI_M! Mode 1, High current – 10 – Output is 0.5 V to VDDA-0.5 V SID_DS_20 IOUT_MED_M1 Mode 1, Medium current – 10 – Output is 0.5 V to VDDA-0.5 V SID_DS_21 IOUT_LOW_M1 Mode 1, Low current – 4 – Output is 0.5 V to VDDA-0.5 V SID_DS_22 IOUT_HI_M2 Mode 2, High current – 1 – SID_DS_23 IOU_MED_M2 Mode 2, Medium current – 1 – SID_DS_24 IOU_LOW_M2 Mode 2, Low current – 0.5 – mV mA Note 6. Guaranteed by characterization. Document Number: 002-00122 Rev. *E Page 20 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 10. Comparator DC Specifications Spec ID# Parameter Description Min Typ Max SID84 VOFFSET1 Input offset voltage, Factory trim – – ±10 SID85 VOFFSET2 Input offset voltage, Custom trim – – ±4 SID86 VHYST Hysteresis when enabled – 10 35 SID87 VICM1 Input common mode voltage in normal mode 0 – VDDD-0.1 SID247 VICM2 Input common mode voltage in low power mode 0 – VDDD SID247A VICM3 Input common mode voltage in ultra low power mode 0 – VDDD-1.15 SID88 CMRR Common mode rejection ratio 50 – – SID88A CMRR Common mode rejection ratio 42 – – SID89 ICMP1 Block current, normal mode – – 400 SID248 ICMP2 Block current, low power mode – – 100 SID259 ICMP3 Block current in ultra low-power mode – – 6 SID90 ZCMP DC Input impedance of comparator 35 – – Units Details/ Conditions mV Modes 1 and 2 V dB µA VDDD ≥ 2.2 V at –40 °C VDDD ≥ 2.7V VDDD ≤ 2.7V VDDD ≥ 2.2 V at –40 °C MΩ Table 11. Comparator AC Specifications Spec ID# Parameter Description Min Typ Max Units SID91 TRESP1 Response time, normal mode, 50 mV overdrive – 38 110 SID258 TRESP2 Response time, low power mode, 50 mV overdrive – 70 200 SID92 TRESP3 Response time, ultra-low power mode, 200 mV overdrive – 2.3 15 Min Typ Max Units –5 ±1 5 °C Details/ Conditions ns µs VDDD ≥ 2.2 V at –40 °C Table 12. Temperature Sensor Specifications Spec ID# SID93 Parameter Description TSENSACC Temperature sensor accuracy Details / Conditions –40 to +85 °C Table 13. SAR Specifications Spec ID# Parameter Description Min Typ Max Units – – 12 bits Details/ Conditions SAR ADC DC Specifications SID94 A_RES Resolution SID95 A_CHNLS_S Number of channels - single ended – – 8 8 full speed. SID96 A-CHNKS_D Number of channels - differential – – 4 Diff inputs use neighboring I/O SID97 A-MONO – – – Yes. SID98 A_GAINERR Gain error – – ±0.1 Monotonicity Document Number: 002-00122 Rev. *E % With external reference. Page 21 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 13. SAR Specifications (continued) Spec ID# Parameter Description Min Typ Max Units SID99 A_OFFSET Input offset voltage – – 2 mV SID100 A_ISAR Current consumption – – 1 mA SID101 A_VINS Input voltage range - single ended VSS – VDDA V SID102 A_VIND Input voltage range - differential[ VSS – VDDA V SID103 A_INRES Input resistance – – 2.2 KΩ SID104 A_INCAP Input capacitance – – 10 pF SID260 VREFSAR Trimmed internal reference to SAR – – TBD V Details/ Conditions Measured with 1-V reference SAR ADC AC Specifications SID106 A_PSRR Power supply rejection ratio 70 – – dB SID107 A_CMRR Common mode rejection ratio 66 – – dB SID108 A_SAMP Sample rate – – 1 Msps SID109 A_SNR Signal-to-noise and distortion ratio (SINAD) 65 – – dB Measured at 1 V FIN = 10 kHz SID110 A_BW Input bandwidth without aliasing – – A_samp/2 kHz SID111 A_INL Integral non linearity. VDD = 1.71 to 5.5, 1 Msps –1.7 – 2 LSB VREF = 1 to VDD SID111A A_INL Integral non linearity. VDDD = 1.71 to 3.6, 1 Msps –1.5 – 1.7 LSB VREF = 1.71 to VDD SID111B A_INL Integral non linearity. VDD = 1.71 to 5.5, 500 ksps –1.5 – SID112 A_DNL Differential non linearity. VDD = 1.71 to 5.5, 1 Msps –1 SID112A A_DNL Differential non linearity. VDD = 1.71 to 3.6, 1 Msps –1 SID112B A_DNL Differential non linearity. VDD = 1.71 to 5.5, 500 ksps –1 SID113 A_THD Total harmonic distortion – – SID261 FSARINTRE F SAR operating speed without external ref. bypass – – Document Number: 002-00122 Rev. *E – – – 1.7 LSB VREF = 1 to VDD 2.2 LSB VREF = 1 to VDD 2 LSB VREF = 1.71 to VDD 2.2 LSB VREF = 1 to VDD –65 dB 100 ksps Fin = 10 kHz 12-bit resolution Page 22 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 14. CSD and IDAC Specifications SPEC ID# Parameter Description Min Typ Max Details / Conditions SYS.PER#3 VDD_RIPPLE Max allowed ripple on power supply, DC to 10 MHz – – ±50 VDD > 2 V (with ripple), 25 °C TA, Sensitivity = 0.1 pF SYS.PER#16 VDD_RIPPLE_1.8 Max allowed ripple on power supply, DC to 10 MHz – – ±25 VDD > 1.75V (with ripple), 25 °C TA, Parasitic Capacitance (CP) < 20 pF, Sensitivity ≥ 0.4 pF SID.CSD.BLK ICSD Maximum block current – – 4000 Maximum block current for both IDACs in dynamic (switching) mode including comparators, buffer, and reference generator. SID.CSD#15 VREF Voltage reference for CSD and Comparator 0.6 1.2 SID.CSD#15A VREF_EXT External Voltage reference for CSD and Comparator 0.6 SID.CSD#16 IDAC1IDD IDAC1 (7-bits) block current – – 1750 SID.CSD#17 IDAC2IDD IDAC2 (7-bits) block current – – 1750 SID308 VCSD Voltage range of operation 1.71 – 5.5 SID308A VCOMPIDAC Voltage compliance range of IDAC 0.6 – SID309 IDAC1DNL DNL –1 – 1 SID310 IDAC1INL INL –3 – 3 SID311 IDAC2DNL DNL –1 – 1 SID312 IDAC2INL INL –3 – 3 INL is ±5 LSB for VDDA < 2V SID313 SNR Ratio of counts of finger to noise. Guaranteed by characterization 5 – – Capacitance range of 5 to 200 pF, 0.1-pF sensitivity. All use cases. VDDA > 2 V. SID314 IDAC1CRT1 Output current of IDAC1 (7 bits) in low range 4.2 – 5.2 LSB = 37.5-nA typ. SID314A IDAC1CRT2 Output current of IDAC1(7 bits) in medium range 34 – 41 LSB = 300-nA typ. SID314B IDAC1CRT3 Output current of IDAC1(7 bits) in high range 275 – 330 LSB = 2.4-µA typ. SID314C IDAC1CRT12 Output current of IDAC1 (7 bits) in low range, 2X mode 8 – 10.5 LSB = 37.5-nA typ. 2X output stage SID314D IDAC1CRT22 Output current of IDAC1(7 bits) in medium range, 2X mode 69 – 82 LSB = 300-nA typ. 2X output stage SID314E IDAC1CRT32 Output current of IDAC1(7 bits) in high range, 2X mode 540 – 660 LSB = 2.4-µA typ.2X output stage SID315 IDAC2CRT1 Output current of IDAC2 (7 bits) in low range 4.2 – 5.2 LSB = 37.5-nA typ. SID315A IDAC2CRT2 Output current of IDAC2 (7 bits) in medium range 34 – 41 LSB = 300-nA typ. Document Number: 002-00122 Rev. *E VDDA - 0.6 VDDA - 0.06 or 4.4, whichever is lower VDDA - 0.6 VDDA - 0.06 or 4.4, whichever is lower 1.8 V ±5% or 1.8 V to 5.5 V VDDA –0.6 VDDA - 0.06 or 4.4, whichever is lower INL is ±5 LSB for VDDA < 2V Page 23 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 14. CSD and IDAC Specifications (continued) SPEC ID# Parameter Description Min Typ Max Details / Conditions SID315B IDAC2CRT3 Output current of IDAC2 (7 bits) in high range 275 – 330 LSB = 2.4-µA typ. SID315C IDAC2CRT12 Output current of IDAC2 (7 bits) in low range, 2X mode 8 – 10.5 LSB = 37.5-nA typ. 2X output stage SID315D IDAC2CRT22 Output current of IDAC2(7 bits) in medium range, 2X mode 69 – 82 LSB = 300-nA typ. 2X output stage SID315E IDAC2CRT32 Output current of IDAC2(7 bits) in high range, 2X mode 540 – 660 LSB = 2.4-µA typ.2X output stage SID315F IDAC3CRT13 Output current of IDAC in 8-bit mode in low range 8 – 10.5 LSB = 37.5-nA typ. SID315G IDAC3CRT23 Output current of IDAC in 8-bit mode in medium range 69 – 82 LSB = 300-nA typ. SID315H IDAC3CRT33 Output current of IDAC in 8-bit mode in high range 540 – 660 LSB = 2.4-µA typ. SID320 IDACOFFSET All zeroes input – – 1 SID321 IDACGAIN Full-scale error less offset – – ±10 Polarity set by Source or Sink. Offset is 2 LSBs for 37.5 nA/LSB mode SID322 IDACMISMATCH1 Mismatch between IDAC1 and IDAC2 in Low mode – – 9.2 LSB = 37.5-nA typ. SID322A IDACMISMATCH2 Mismatch between IDAC1 and IDAC2 in Medium mode – – 4.6 LSB = 300-nA typ. SID322B IDACMISMATCH3 Mismatch between IDAC1 and IDAC2 in High mode – – 2.3 LSB = 2.4-µA typ. SID323 IDACSET8 Settling time to 0.5 LSB for 8-bit IDAC – – 10 Full-scale transition. No external load. SID324 IDACSET7 Settling time to 0.5 LSB for 7-bit IDAC – – 10 Full-scale transition. No external load. SID325 CMOD External modulator capacitor. – 2.2 – 5-V rating, X7R or NP0 cap. Table 15. 10-bit CapSense ADC Specifications Spec ID# Parameter Description Min Typ Max Details/ Conditions bits Auto-zeroing is required every millisecond Units SIDA94 A_RES Resolution – – 10 SIDA95 A_CHNLS_S Number of channels - single ended – – 16 SIDA97 A-MONO Monotonicity – – – Yes SIDA98 A_GAINERR Gain error – – ±2 % SIDA99 A_OFFSET Input offset voltage – – 3 mV In VREF (2.4 V) mode with VDDA bypass capacitance of 10 µF SIDA100 A_ISAR Current consumption – – 0.25 SIDA101 A_VINS Input voltage range - single ended VSSA – VDDA V SIDA103 A_INRES Input resistance – 2.2 – KΩ SIDA104 A_INCAP Input capacitance – 20 – pF Document Number: 002-00122 Rev. *E Defined by AMUX Bus. In VREF (2.4 V) mode with VDDA bypass capacitance of 10 µF mA Page 24 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 15. 10-bit CapSense ADC Specifications (continued) Spec ID# SIDA106 Parameter A_PSRR Description Min Typ Max Units Power supply rejection ratio – 60 – dB Details/ Conditions In VREF (2.4 V) mode with VDDA bypass capacitance of 10 µF SIDA107 A_TACQ Sample acquisition time – 1 – µs SIDA108 A_CONV8 Conversion time for 8-bit resolution at conversion rate = Fhclk/(2^(N+2)). Clock frequency = 48 MHz. – – 21.3 µs Does not include acquisition time. Equivalent to 44.8 ksps including acquisition time. SIDA108A A_CONV10 Conversion time for 10-bit resolution at conversion rate = Fhclk/(2^(N+2)). Clock frequency = 48 MHz. – – 85.3 µs Does not include acquisition time. Equivalent to 11.6 ksps including acquisition time. SIDA109 A_SND Signal-to-noise and Distortion ratio (SINAD) 61 – – dB With 10-Hz input sine wave, external 2.4-V reference, VREF (2.4 V) mode SIDA110 A_BW Input bandwidth without aliasing – – 22.4 SIDA111 A_INL Integral Non Linearity. 1 ksps – – 2 LSB VREF = 2.4 V or greater SIDA112 A_DNL Differential Non Linearity. 1 ksps – – 1 LSB KHz 8-bit resolution Digital Peripherals Timer Counter Pulse-Width Modulator (TCPWM) Table 16. TCPWM Specifications Spec ID SID.TCPWM.1 Parameter ITCPWM1 Description Block current consumption at 3 MHz Min – Typ – Max 45 Units Details/Conditions All modes (TCPWM) SID.TCPWM.2 ITCPWM2 Block current consumption at 12 MHz – – 155 μA All modes (TCPWM) SID.TCPWM.2A ITCPWM3 Block current consumption at 48 MHz – – 650 – – Fc 2/Fc – – For all trigger events[7] Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) outputs SID.TCPWM.3 TCPWMFREQ Operating frequency SID.TCPWM.4 TPWMENEXT Input trigger pulse width SID.TCPWM.5 TPWMEXT All modes (TCPWM) MHz Fc max = CLK_SYS Maximum = 48 MHz Output trigger pulse widths 2/Fc – – SID.TCPWM.5A TCRES Resolution of counter 1/Fc – – SID.TCPWM.5B PWMRES PWM resolution 1/Fc – – Minimum pulse width of PWM Output SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc – – Minimum pulse width between Quadrature phase inputs ns Minimum time between successive counts Notes 7. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected. Document Number: 002-00122 Rev. *E Page 25 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY I2C Table 17. Fixed I2C DC Specifications[8] Spec ID Parameter Description Min Typ Max Units Details/Conditions – SID149 II2C1 Block current consumption at 100 kHz – – 50 SID150 II2C2 Block current consumption at 400 kHz – – 135 SID151 II2C3 Block current consumption at 1 Mbps – – 310 – – 1.4 Min Typ Max Units Details/Conditions – – 1 Msps – Units Details/Conditions SID152 2 I C enabled in Deep Sleep mode II2C4 – µA – Table 18. Fixed I2C AC Specifications[8] Spec ID Parameter SID153 Description Bit rate FI2C1 Table 19. SPI DC Specifications[9] Spec ID Parameter Description Min Typ Max SID163 ISPI1 Block current consumption at 1 Mbps – – 360 SID164 ISPI2 Block current consumption at 4 Mbps – – 560 SID165 ISPI3 Block current consumption at 8 Mbps – – 600 – µA – – Table 20. SPI AC Specifications[8] Spec ID SID166 Parameter FSPI Description Min Typ Max SPI Operating frequency (Master; 6X Oversampling) – – 8 Units Details/Conditions MHz SID166 Fixed SPI Master Mode AC Specifications SID167 TDMO MOSI Valid after SClock driving edge – – 15 – SID168 TDSI MISO Valid before SClock capturing edge 20 – – SID169 THMO Previous MOSI data hold time 0 – – Referred to Slave capturing edge – ns Full clock, late MISO sampling Fixed SPI Slave Mode AC Specifications SID170 TDMI MOSI Valid before Sclock Capturing edge 40 – – SID171 TDSO MISO Valid after Sclock driving edge – – 42 + 3*Tcpu SID171A TDSO_EXT MISO Valid after Sclock driving edge in Ext. Clk mode – – 48 SID172 THSO Previous MISO data hold time 0 – – SID172A TSSELSSCK SSEL Valid to first SCK Valid edge – – 100 ns TCPU = 1/FCPU – – ns – Note 8. Guaranteed by characterization. Document Number: 002-00122 Rev. *E Page 26 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 21. UART DC Specifications[9] Spec ID Parameter Description Min Typ Max Units Details/Conditions SID160 IUART1 Block current consumption at 100 Kbps – – 55 µA – SID161 IUART2 Block current consumption at 1000 Kbps – – 312 µA – Min Typ Max Units Details/Conditions – – 1 Mbps – Table 22. UART AC Specifications[9] Spec ID SID162 Parameter FUART Description Bit rate Table 23. LCD Direct Drive DC Specifications[9] Spec ID Parameter Description Min SID154 ILCDLOW Operating current in low power mode SID155 CLCDCAP LCD capacitance per segment/common driver – SID156 LCDOFFSET Long-term segment offset – SID157 ILCDOP1 LCD system operating current Vbias = 5 V – LCD system operating current Vbias = 3.3 V – SID158 ILCDOP2 – Typ Max Units Details/Conditions 16 4 small segment disp. at 50 Hz 5 – µA 500 5000 pF – 20 – mV – 2 – 32 4 segments. 50 Hz. 25 °C mA 32 4 segments. 50 Hz. 25 °C 2 – Min Typ Max Units Details/Conditions 10 50 150 Hz – Table 24. LCD Direct Drive AC Specifications[9] Spec ID SID159 Parameter FLCD Description LCD frame rate Note 9. Guaranteed by characterization. Document Number: 002-00122 Rev. *E Page 27 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Memory Table 25. Flash DC Specifications Spec ID SID173 Parameter VPE Description Min Typ Max Units Details/Conditions 1.71 – 5.5 V – Description Min Typ Max Units Details/Conditions Erase and program voltage Table 26. Flash AC Specifications Spec ID Parameter SID174 TROWWRITE[10] Row (block) write time (erase and program) – – 20 SID175 TROWERASE[10] Row erase time – – 16 SID176 Row program time after erase – – 4 – Bulk erase time (64 KB) – – 35 – SID180 TROWPROGRAM[10] TBULKERASE[10] TDEVPROG[10] SID181[11] FEND Flash endurance SID182[11] FRET SID178 [11] ms – – – 7 Seconds – 100 K – – Cycles – Flash retention. TA 55 °C, 100 K P/E cycles 20 – – – Flash retention. TA 85 °C, 10 K P/E cycles 10 – – SID256 TWS48 Number of Wait states at 48 MHz 2 – – CPU execution from Flash SID257 TWS24 Number of Wait states at 24 MHz 1 – – CPU execution from Flash Min Typ Max Units 1 – 67 V/ms V SID182A[11] Total device program time Row (block) = 128 bytes – Years – System Resources Power-on Reset (POR) Table 27. Power On Reset (PRES) Spec ID Parameter Description SID.CLK#6 SR_POWER_UP Power supply slew rate SID185[11] VRISEIPOR Rising trip voltage 0.80 – 1.5 [11] VFALLIPOR Falling trip voltage 0.70 – 1.4 SID186 Details/Conditions At power-up – – Table 28. Brown-out Detect (BOD) for VCCD Min Typ Max Units Details/Conditions SID190[11] Spec ID VFALLPPOR Parameter BOD trip voltage in active and sleep modes Description 1.48 – 1.62 V – SID192[11] VFALLDPSLP BOD trip voltage in Deep Sleep 1.11 – 1.5 – Notes 10. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. 11. Guaranteed by characterization. Document Number: 002-00122 Rev. *E Page 28 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY SWD Interface Table 29. SWD Interface Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions SWDCLK ≤ 1/3 CPU clock frequency SID213 F_SWDCLK1 3.3 V VDD 5.5 V – – 14 SID214 F_SWDCLK2 1.71 V VDD 3.3 V – – 7 SWDCLK ≤ 1/3 CPU clock frequency SID215[12] T_SWDI_SETUP T = 1/f SWDCLK 0.25*T – – – T_SWDI_HOLD 0.25*T – – T_SWDO_VALID T = 1/f SWDCLK – – 0.5*T T_SWDO_HOLD T = 1/f SWDCLK 1 – – Min Typ Max Units Details/Conditions MHz [12] SID216 [12] SID217 SID217A [12] T = 1/f SWDCLK ns – – – Internal Main Oscillator Table 30. IMO DC Specifications (Guaranteed by Design) Spec ID Parameter Description SID218 IIMO1 IMO operating current at 48 MHz – – 250 µA – SID219 IIMO2 IMO operating current at 24 MHz – – 180 µA – Description Min Typ Max Units Details/Conditions Table 31. IMO AC Specifications Spec ID Parameter SID223 FIMOTOL1 Frequency variation at 24, 32, and 48 MHz (trimmed) – – ±2 % SID226 TSTARTIMO IMO startup time – – 7 µs – SID228 TJITRMSIMO2 RMS jitter at 24 MHz – 145 – ps – Min Typ Max Units Details/Conditions – 0.3 1.05 µA – Min Typ Max Units Details/Conditions Internal Low-Speed Oscillator Table 32. ILO DC Specifications (Guaranteed by Design) Spec ID Parameter SID231[12] IILO1 Description ILO operating current Table 33. ILO AC Specifications Spec ID SID234[12] Parameter TSTARTILO1 SID236[12] TILODUTY SID237 FILOTRIM1 Description ILO startup time – – 2 ms – ILO duty cycle 40 50 60 % – ILO frequency range 20 40 80 kHz – Note 12. Guaranteed by characterization. Document Number: 002-00122 Rev. *E Page 29 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 34. Watch Crystal Oscillator (WCO) Specifications Spec ID# Parameter Description Min Typ Max Units SID398 FWCO Crystal Frequency – 32.768 – kHz SID399 FTOL Frequency tolerance – 50 250 ppm SID400 ESR Equivalent series resistance – 50 – kΩ SID401 PD Drive Level – – 1 µW SID402 TSTART Startup time – – 500 ms SID403 CL Crystal Load Capacitance 6 – 12.5 pF SID404 C0 Crystal Shunt Capacitance – 1.35 – pF SID405 IWCO1 Operating Current (high power mode) – – 8 uA SID406 IWCO2 Operating Current (low power mode) – – 1 uA Details / Conditions With 20-ppm crystal Table 35. External Clock Specifications Min Typ Max Units Details/Conditions SID305[13] ExtClkFreq Spec ID Parameter External clock input frequency 0 – 48 MHz – SID306[13] Duty cycle; measured at VDD/2 45 – 55 % – Min Typ Max Units Details/Conditions 3 – 4 Periods – Min Typ Max Units – – 1.6 ns ExtClkDuty Description Table 36. Block Specs Spec ID Parameter SID262[13] TCLKSWITCH Description System clock source switching time Table 37. PRGIO Pass-through Time (Delay in Bypass Mode) Spec ID# SID252 Parameter Description PRG_BYPASS Max. delay added by PRGIO in bypass mode Details / Conditions PRGIO will be branded Smart I/O pending legal clearance Note 13. Guaranteed by characterization. Document Number: 002-00122 Rev. *E Page 30 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Ordering Information The marketing part numbers for the PSoC 4100S family are listed in the following table. 4146 Flash (KB) SRAM (KB) Opamp (CTBm) CSD 12-bit SAR ADC ADC Sample Rate LP Comparators TCPWM Blocks SCB Blocks SMART I/O Pins (Smart I/Os) GPIO 35-WLCSP 32-QFN 40-QFN 48-TQFP 4125 Max CPU Speed (MHz) 4124 Package CY8C4124FNI-S403 24 16 4 2 0 0 – 2 5 2 8 31 X – – – CY8C4124FNI-S413 24 16 4 2 1 0 – 2 5 2 16 31 X – – – CY8C4124LQI-S412 24 16 4 2 1 0 – 2 5 2 16 27 – X – – CY8C4124LQI-S413 24 16 4 2 1 0 – 2 5 2 16 34 – – X – CY8C4124AZI-S413 24 16 4 2 1 0 – 2 5 2 16 36 – – – X CY8C4124FNI-S433 24 16 4 2 1 1 806 ksps 2 5 2 16 31 X – – – CY8C4124LQI-S432 24 16 4 2 1 1 806 ksps 2 5 2 16 27 – X – – CY8C4124LQI-S433 24 16 4 2 1 1 806 ksps 2 5 2 16 34 – – X – CY8C4124AZI-S433 24 16 4 2 1 1 806 ksps 2 5 2 16 36 – – – X CY8C4125FNI-S423 24 32 4 2 0 1 806 ksps 2 5 2 16 31 X – – – CY8C4125LQI-S422 24 32 4 2 0 1 806 ksps 2 5 2 16 27 – X – – CY8C4125LQI-S423 24 32 4 2 0 1 806 ksps 2 5 2 16 34 – – X – CY8C4125AZI-S423 24 32 4 2 0 1 806 ksps 2 5 2 16 36 – – – X CY8C4125FNI-S413 24 32 4 2 1 0 – 2 5 2 16 31 X – – – CY8C4125LQI-S412 24 32 4 2 1 0 – 2 5 2 16 27 – X – – CY8C4125LQI-S413 24 32 4 2 1 0 – 2 5 2 16 34 – – X – MPN Category Features CY8C4125AZI-S413 24 32 4 2 1 0 – 2 5 2 16 36 – – – X CY8C4125FNI-S433 24 32 4 2 1 1 806 ksps 2 5 2 16 31 X – – – CY8C4125LQI-S432 24 32 4 2 1 1 806 ksps 2 5 2 16 27 – X – – CY8C4125LQI-S433 24 32 4 2 1 1 806 ksps 2 5 2 16 34 – – X – CY8C4125AZI-S433 24 32 4 2 1 1 806 ksps 2 5 2 16 36 – – – X CY8C4146FNI-S423 48 64 8 2 0 1 1 Msps 2 5 3 16 31 X – – – CY8C4146LQI-S422 48 64 8 2 0 1 1 Msps 2 5 3 16 27 – X – – CY8C4146LQI-S423 48 64 8 2 0 1 1 Msps 2 5 3 16 34 – – X – CY8C4146AZI-S423 48 64 8 2 0 1 1 Msps 2 5 3 16 36 – – – X CY8C4146FNI-S433 48 64 8 2 1 1 1 Msps 2 5 3 16 31 X – – – CY8C4146LQI-S432 48 64 8 2 1 1 1 Msps 2 5 3 16 27 – X – – CY8C4146LQI-S433 48 64 8 2 1 1 1 Msps 2 5 3 16 34 – – X – CY8C4146AZI-S433 48 64 8 2 1 1 1 Msps 2 5 3 16 36 – – – X Document Number: 002-00122 Rev. *E Page 31 of 41 PRELIMINARY PSoC® 4: PSoC 4100S Family Datasheet The nomenclature used in the preceding table is based on the following part numbering convention: Field Description CY8C Cypress Prefix Values Meaning 4 Architecture 4 PSoC 4 A Family 0 4000 Family B CPU Speed 2 24 MHz 4 48 MHz 4 16 KB 5 32 KB 6 64 KB 7 128 KB AX TQFP (0.8mm pitch) C Flash Capacity DE Package Code AZ TQFP (0.5mm pitch) LQ QFN PV SSOP FN CSP F Temperature Range I Industrial S Silicon Family S PSoC 4A-S1, PSoC 4A-S2 M PSoC 4A-M L PSoC 4A-L XYZ Attributes Code BL PSoC 4A-BLE 000-999 Code of feature set in the specific family The following is an example of a part number: Example CY8C 4 A B C DE F – S XYZ Cypress Prefix Architecture 4: PSoC 4 1: 4100 2: 4200 Family Family Family within Architecture CPU Speed 4: 48 MHz 5: 32 KB Flash Capacity AZ: TQFP AX: TQFP Package Code I: Industrial Temperature Range Silicon Family Attributes Code Document Number: 002-00122 Rev. *E Page 32 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Packaging The PSoC 4100S will be offered in 48-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball WLCSP packages. Package dimensions and Cypress drawing numbers are in the following table. Table 38. Package List Spec ID# Package BID20 48-pin TQFP 7 × 7 × 1.4 mm height with 0.5-mm pitch 51-85135 BID27 40-Pin QFN 6 × 6 × 0.6 mm height with 0.4-mm pitch 001-80659 BID34A 32-Pin QFN BID34D 35-Ball WLCSP Description Package Dwg 5 × 5 × 0.6 mm height with 0.45mm pitch 001-42168 2.6 × 1.1 × 0.48mm height with 0.35-mm pitch 002-09958 Table 39. Package Thermal Characteristics Parameter Description Package Min Typ Max Units –40 25 85 °C –40 – 100 °C – 74.8 – °C/Watt 48-pin TQFP – 35.7 – °C/Watt 40-pin QFN – 17.8 – °C/Watt Package θJC 40-pin QFN – 2.8 – °C/Watt Package θJA 32-pin QFN – 19.9 – °C/Watt TJC Package θJC 32-pin QFN – 4.3 – °C/Watt TJA Package θJA 35-Ball WLCSP – 43 – °C/Watt TJC Package θJC 35-Ball WLCSP – 0.3 – °C/Watt TA Operating Ambient temperature TJ Operating junction temperature TJA Package θJA 48-pin TQFP TJC Package θJC TJA Package θJA TJC TJA Table 40. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature All 260 °C 30 seconds Table 41. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020 Package MSL All MSL 3 Document Number: 002-00122 Rev. *E Page 33 of 41 PRELIMINARY PSoC® 4: PSoC 4100S Family Datasheet Package Diagrams Figure 6. 48-pin TQFP Package Outline 51-85135 *C Figure 7. 40-pin QFN Package Outline 001-80659 *A Document Number: 002-00122 Rev. *E Page 34 of 41 PRELIMINARY PSoC® 4: PSoC 4100S Family Datasheet Figure 8. 32-pin QFN Package Outline 001-42168 *E Figure 9. 35-Ball WLCSP Package Outline 002-09958 *B Document Number: 002-00122 Rev. *E Page 35 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Acronyms Table 42. Acronyms Used in this Document Acronym Description Table 42. Acronyms Used in this Document (continued) Acronym Description ETM embedded trace macrocell FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin arithmetic logic unit HVI high-voltage interrupt, see also LVI, LVD analog multiplexer bus IC integrated circuit API application programming interface IDAC current DAC, see also DAC, VDAC APSR application program status register IDE integrated development environment ARM® advanced RISC machine, a CPU architecture I ATM automatic thump mode BW bandwidth CAN Controller Area Network, a communications protocol abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus ALU AMUXBUS 2C, or IIC Inter-Integrated Circuit, a communications protocol IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL CMRR common-mode rejection ratio INL CPU central processing unit I/O input/output, see also GPIO, DIO, SIO, USBIO CRC cyclic redundancy check, an error-checking protocol IPOR initial power-on reset IPSR interrupt program status register DAC digital-to-analog converter, see also IDAC, VDAC IRQ interrupt request DFB digital filter block ITM instrumentation trace macrocell DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. LCD liquid crystal display DMIPS Dhrystone million instructions per second LIN Local Interconnect Network, a communications protocol. DMA direct memory access, see also TD LR link register DNL differential nonlinearity, see also INL LUT lookup table DNU do not use LVD low-voltage detect, see also LVI DR port write data registers LVI low-voltage interrupt, see also HVI DSI digital system interconnect LVTTL low-voltage transistor-transistor logic DWT data watchpoint and trace MAC multiply-accumulate ECC error correcting code MCU microcontroller unit ECO external crystal oscillator MISO master-in slave-out EEPROM electrically erasable programmable read-only memory NC no connect EMI electromagnetic interference NMI nonmaskable interrupt EMIF external memory interface NRZ non-return-to-zero EOC end of conversion NVIC nested vectored interrupt controller EOF end of frame NVL nonvolatile latch, see also WOL EPSR execution program status register ESD electrostatic discharge Document Number: 002-00122 Rev. *E opamp operational amplifier PAL programmable array logic, see also PLD Page 36 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Table 42. Acronyms Used in this Document (continued) Acronym Description Table 42. Acronyms Used in this Document (continued) Acronym Description PC program counter SWV single-wire viewer PCB printed circuit board TD transaction descriptor, see also DMA PGA programmable gain amplifier THD total harmonic distortion PHUB peripheral hub TIA transimpedance amplifier PHY physical layer TRM technical reference manual PICU port interrupt control unit TTL transistor-transistor logic PLA programmable logic array TX transmit PLD programmable logic device, see also PAL UART PLL phase-locked loop Universal Asynchronous Transmitter Receiver, a communications protocol PMDD package material declaration data sheet UDB universal digital block POR power-on reset PRES precise power-on reset PRS pseudo random sequence PS port read data register PSoC® Programmable System-on-Chip™ PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I2C serial clock SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug, a test protocol Document Number: 002-00122 Rev. *E USB Universal Serial Bus USBIO USB input/output, PSoC pins used to connect to a USB port VDAC voltage DAC, see also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal Page 37 of 41 PRELIMINARY PSoC® 4: PSoC 4100S Family Datasheet Document Conventions Units of Measure Table 43. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibel fF femto farad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz k kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second µA microampere µF microfarad µH microhenry µs microsecond µV microvolt µW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz V volt Document Number: 002-00122 Rev. *E Page 38 of 41 PSoC® 4: PSoC 4100S Family Datasheet PRELIMINARY Errata This section describes the errata for the PSOC 4100S, CY8C412X product family. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. For a list of sales offices, go to http://www.cypress.com/sales. Part Numbers Affected Part Number Device Characteristics CY8C412X PSoC4100S Product Family PSoC 4100S Qualification Status Product Status: Engineering Samples PSoC 4100S Errata Summary The following table defines the errata applicability to available PSOC 4100S family devices. Items CY8C412X Silicon Revision Fix Status All First silicon Silicon and/or firmware fix is planned in Q1 2016 1. Sensitivity in capacitance measurement 1. Sensitivity in capacitance measurement ■ Problem Definition Sensitivity in Capacitance measurement is 0.2 pF instead of 0.1 pF as specified. ■ Parameters Affected Datasheet parameter SID313 (SNR) is measured as 0.2 pF instead of 0.1 pF as specified. ■ Trigger Condition(s) No specific trigger condition. ■ Scope Of Impact Reduced sensitivity implies some corner cases will exhibit increased susceptibility to noise and may not work. ■ Workaround None ■ Fix Status Silicon and/or firmware fix is planned in Q1 2016 when this erratum will be removed from the datasheet. Document Number: 002-00122 Rev. *E Page 39 of 41 PRELIMINARY PSoC® 4: PSoC 4100S Family Datasheet Revision History Description Title: PSoC® 4: PSoC 4100S Family Datasheet Programmable System-on-Chip (PSoC) Document Number: 002-00122 Orig. of Submission Revision ECN Description of Change Change Date ** 4883809 WKA 08/28/2015 New datasheet Updated Pinouts. Added VDDD ≥ 2.2V at –40 °C under Conditions for specs SID247A, SID90, *A 4992376 WKA 10/30/2015 SID92. Updated Table 15. Updated Ordering Information. *B 5037826 SLAN 12/08/2015 Changed datasheet status to Preliminary Updated SCBs from 2 to 3. Updated SRAM size to 8 KB. *C 5060691 WKA 12/22/2015 Changed WLCSP package to 35-ball WLCSP. Updated Pin List and Alternate Pin Functions. Updated Ordering Information. Added Errata. Added 35 WLCSP package details. *D 5139206 WKA 02/16/2016 Updated theta JA and JC values for all packages. Updated copyright information at the end of the document. *E 5173961 WKA 03/15/2016 Updated values for SID79, BID194. SID175, and SID176. Updated CSD and IDAC Specifications. Updated 10-bit CapSense ADC Specifications. Document Number: 002-00122 Rev. *E Page 40 of 41 PRELIMINARY PSoC® 4: PSoC 4100S Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/clocks cypress.com/interface cypress.com/powerpsoc cypress.com/memory PSoC cypress.com/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/support cypress.com/touch USB Controllers Wireless/RF cypress.com/psoc cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation 2015-2016. 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Other names and brands may be claimed as property of their respective owners Document Number: 002-00122 Rev. *E Revised March 15, 2016 Page 41 of 41