A B C D E REVISION # REVISION HISTORY SD PC AD FD IS AN OPTIONAL CAPACITOR. IT IS INSERTED * CIN1 ON THE DC1159A TO DAMPEN THE (POSSIBLE) 0 DESCRIPTION 0 0 0 DATE APPROVED 1st Release RINGING VOLTAGE DUE TO THE LONG INPUT LEADS. ON A NORMAL, TYPICAL PCB, WITH SHORT TRACES, THE CAPACITOR IS NOT NEEDED. 4 4 PGOOD E7 U1 LTC3565EDD VIN 2.5V - 5.5V E1 VIN + CIN2 47uF 20V CIN3 (Opt) + 6 CIN1 10uF 10V CIN4 (Opt) RPG RFILT E2 3 GND 0 CBYP (Opt) RS1 1.0M E8 GND E6 SYNC/MODE PVIN SW 4 8 PGOOD VFB 9 7 SVIN ITH 10 3 SYNC/MODE RT 1 2 RUN PGND 5 100K SGND L1 E3 VOUT 1uH A918CY-1R0M TOKO COUT1 22uF 10V VOUT 1.2A(max) COUT2 (Opt) COUT4 0.1uF + COUT3 (Opt) E4 GND RC 13.0K 1% RT 68.1K 1% 11 RFB1 348K 1% C1 (Opt) 3 E5 GND CFFW CC 1000pF 10pF RS2 1.0M MODE 1 BURST R1 2 PULSE-SKIP JP3 10K 3 RFB2 JP1 174K 1% VOUT 2 1 ON 2 3 OFF RSD 1.0M JP2 PCB LAYOUT 1.8V RFB3 JP4 232K 1% 1.5V 2 RFB4 JP5 348K 1% 1.2V RFB5 JP6 (Opt) USER SELECT L1 COUT2 COUT1 CIN1 CIN4 1 U1 APPROVALS RPG RFB1 A RC CFFW C1 CC RT This circuit is proprietary to Linear Technology and supplied for use with Linear Technology parts. Customer Notice:Linear Technology has made a best effort to design a circuit that meets customer-supplied specifications; however, it remains the customers responsibility to verify proper and reliable operation in the actual application. Component substitution and printed circuit board layout may significantly affect circuit performance or reliability. Contact Linear Applications Engineering for assistance. B C DRAWN: Rudy Bautista ENGINEER: Tom Gross LINEAR TECHNOLOGY CORPORATION 1630 McCARTHY BLVD MILPITAS, CA. 95035 (408)432-1900 (408)434-0507 (FAX) Title: LTC3565EDD APPROVED: SD CHECKED: Date: Tuesday, March 03, 2009 D 1 www.linear.com LTC Confidential For Customer Use Only Monolithic Synchronous Buck Regulator Document Number Rev Demo Circuit 1159A C:\ORCADWIN\CAPTURE\1159A\1159A_REV1.DSN E Sheet 1 1 of 1