SINGLE EVENT LATCH-UP TEST REPORT ADA4077-2S November 2015 Radiation Test Report Product: ADA4077-2S Effective LET: 80.7 MeV-cm2/mg Fluence: 1E7 Ions/cm2 Die Type: 2Y RADEF, Univ. of Jyvaskyla, Facilities: Finland Tested: September 2015 The RADTEST® DATA SERVICE is a compilation of radiation test results on Analog Devices’ Space grade products. It is designed to assist customers in selecting the right product for applications where radiation is a consideration. Many products manufactured by Analog Devices, Inc. have been shown to be radiation tolerant to most tactical radiation environments. Analog Devices, Inc. does not make any claim to maintain or guarantee these levels of radiation tolerance without lot qualification test. It is the responsibility of the Procuring Activity to screen products from Analog Devices, Inc. for compliance to Nuclear Hardness Critical Items (HCI) specifications. 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Analog Devices, Inc. 7910 Triad Center Drive, Greensboro, NC 27409 Page:1 SINGLE EVENT EFFECTS TEST REPORT Test Type: Heavy ion Test facility: RADEF, University of Jyvaskyla, Finland Test Date: September 2015 Part Type: AD4077-2 Part Description: Dual 4 MHz, 7 nV/√Hz, Low Offset and Drift, High Precision Amplifiers Part Manufacturer: Analog Devices Analog Devices PO No 45516080 dated 22/06/2015 Hirex reference : HRX/SEE/0540 Issue : 01 Written by : Mehdi Kaddour Design Engineer Authorized by: F.X. Guerre Study Manager Date : HIREX Engineering SAS au capital de 180 000 € - RCS Toulouse B 389 715 525 Siège social: 2 rue des Satellites - 31520 Toulouse October 28, 2015 Page:2 HIREX Engineering SAS au capital de 180 000 € - RCS Toulouse B 389 715 525 Siège social: 2 rue des Satellites - 31520 Toulouse Page:3 Hirex Engineering SEE Test Report Ref. : Issue : HRX/SEE/0540 01 RESULTS SUMMARY Facility RADEF, University of Jyvaskyla, Finland Test date September 2015 Device description Dual 4 MHz, 7 nV/√Hz, Low Offset and Drift, High Precision Amplifiers Part type: Part number: Manufacturer: Package: Samples used: Top marking: Bottom marking: Date code: Die dimensions: AD4077-2 ADA4077 – 2ARMZ Analog Devices MSOP-08 6 logo A 2X #438 8053 1438 1.088 mm X 0.965 mm SEL Results No SEL neither step current increase has been observed when tested with V+/- set to 16.5V at any LET value at 125°C with all tested samples. HRX/SEE/0540 Issue 01 Page:4 Hirex Engineering Ref. : Issue : SEE Test Report HRX/SEE/0540 01 DOCUMENTATION CHANGE NOTICE Issue Date Page 01 28/10/2015 All Change Item Original issue Contributors to this work: Bendy Tanios Mehdi Kaddour HRX/SEE/0540 Issue 01 Hirex Engineering Hirex Engineering Page:5 Hirex Engineering SEE Test Report Ref. : Issue : HRX/SEE/0540 01 SEE TEST REPORT TABLE OF CONTENTS 1 INTRODUCTION ........................................................................................................................................................ 6 2 APPLICABLE AND REFERENCE DOCUMENTS............................................................................................... 6 2.1 2.2 3 APPLICABLE DOCUMENTS ................................................................................................................................... 6 REFERENCE DOCUMENTS .................................................................................................................................... 6 DEVICE INFORMATION ......................................................................................................................................... 7 3.1 3.2 3.3 DEVICE DESCRIPTION........................................................................................................................................... 7 SAMPLE IDENTIFICATION ..................................................................................................................................... 7 SAMPLE PREPARATION AND EVALUATION OF DEAD LAYER THICKNESS ................................................................ 7 4 RADEF FACILITY .............................................................................................................................................................. 8 5 TEST SET-UP .............................................................................................................................................................. 9 5.1 6 SEE TEST RESULTS ................................................................................................................................................ 11 6.1 7 AD4077-2 TEST PRINCIPLE AND CONDITIONS ...................................................................................................... 9 SEL RESULTS .................................................................................................................................................... 11 GLOSSARY ................................................................................................................................................................ 12 LIST OF FIGURES Figure 1 – AD4077-2 device identification......................................................................................................... 7 Figure 2 - Heavy ion test set-up ........................................................................................................................ 9 Figure 3 – AD4077-2 bias condition ................................................................................................................ 10 Figure 4 – Photo of test board ......................................................................................................................... 10 LIST OF TABLES Table 1 – Ion beam setting .................................................................................................................................... 8 Table 2 - Voltage bias conditions applied to the 2 DUTs .................................................................................. 9 Table 3 - Tester supply channel affectation .................................................................................................... 10 Table 4 - Run table for AD4077-2, RADEF September 2015 ......................................................................... 11 HRX/SEE/0540 Issue 01 Page:6 Hirex Engineering 1 SEE Test Report Ref. : Issue : HRX/SEE/0540 01 Introduction This report presents the results of SEL Heavy Ions test program carried out on Analog Devices AD4077-2. On September 2015, 6 samples were used for heavy ions testing at RADEF, University of Jyvaskyla, Finland .This work was performed for Analog Devices, Greensboro under PO n° 45516080 dated 22/06/2015. 2 Applicable and Reference Documents 2.1 Applicable Documents AD-1. Datasheet: http://www.analog.com/media/en/technical-documentation/datasheets/ADA4077-1_4077-2_4077-4.pdf 2.2 Reference Documents RD-1. Single Event Effects Test method and Guidelines ESA/SCC basic specification No 25100 HRX/SEE/0540 Issue 01 Page:7 Hirex Engineering Ref. : Issue : SEE Test Report HRX/SEE/0540 01 3 DEVICE INFORMATION 3.1 Device description AD4077-2 is a Dual 4 MHz, 7 nV/√Hz, Low Offset and Drift, High Precision Amplifiers. Part type: AD4077-2 Part number: ADA4077 – 2ARMZ Manufacturer: Analog Devices Package: MSOP-08 Samples used: 6 Top marking: logo A 2X Bottom marking: #438 8053 Date code: 1438 Die dimensions: 1.088 mm X 0.965 mm Sample identification 12 AD4077-2 parts were delivered by Analog Devices, Greensboro. Samples were prepared and opened chemically to be tested to heavy ions. 6 samples were verified fully functional before the test campaign, and 6 were tested under irradiation. 3.2 Photo 1 – Device top view Photo 2 – Device delidded Photo 3 – die, full view Photo 4 – Die marking #1 Photo 5 – Die marking #2 Photo 6 – Die marking #3 Figure 1 – AD4077-2 device identification 3.3 Sample preparation and evaluation of dead layer thickness Samples were opened chemically. Die micro-section results are given in appendix. Overall dead layer thickness on top of active zone is less or equal to 10 microns of equivalent silicon. HRX/SEE/0540 Issue 01 Page:8 Hirex Engineering 4 SEE Test Report Ref. : Issue : HRX/SEE/0540 01 RADEF Facility Test at the cyclotron accelerator was performed at University of Jyvaskyla (JYFL) (Finland) under HIREX Engineering responsibility. The facility includes a special beam line dedicated to irradiation studies of semiconductor components and devices. It consists of a vacuum chamber including component movement apparatus and the necessary diagnostic equipment required for the beam quality and intensity analysis. The cyclotron is a versatile, sector‐focused accelerator of beams from hydrogen to xenon equipped with three external ion sources: two electron cyclotron resonance (ECR) ion sources designed for high‐charge‐ state heavy ions, and a multicusp ion source for intense beams of protons. The ECR's are especially valuable in the study of single event effects (SEE) in semiconductor devices. For heavy ions, the maximum energy attainable can be determined using the formula, 130 Q2/M, where Q is the ion charge state and M is the mass in Atomic Mass Units. Test chamber Irradiation of components is performed in a vacuum chamber with an inside diameter of 75 cm and a height of 81 cm. The vacuum in the chamber is achieved after 15 minutes of pumping, and the inflation takes only a few minutes. The position of the components installed in the linear movement apparatus inside the chamber can be adjusted in the X, Y and Z directions. The possibility of rotation around the Y‐axis is provided by a round table. The free movement area reserved for the components is 25 cm x 25 cm, which allows one to perform several consecutive irradiations for several different components without breaking the vacuum. The assembly is equipped with a standard mounting fixture. The adapters required to accommodate the special board configurations and the vacuum feed‐throughs can also be made in the laboratory’s workshops. The chamber has an entrance door, which allows rapid changing of the circuit board or individual components. A CCD camera with a magnifying telescope is located at the other end of the beam line to determine accurate positioning of the components. The coordinates are stored in the computer’s memory allowing fast positioning of various targets during the test. Beam quality control For measuring beam uniformity at low intensity, a CsI(Tl) scintillator with a PIN‐type photodiode readout is fixed in the mounting fixture. The uniformity is measured automatically before component irradiation and the results can be plotted immediately for more detailed analysis. A set of four collimated PIN‐CsI(Tl) detectors is located in front of the beam entrance. The detectors are operated with step motors and are located at 90 degrees with respect to each other. During the irradiation and uniformity scan they are set to the outer edge of the beam in order to monitor the stability of the homogeneity and flux. Two beam wobblers and/or a 0.5 microns diffusion Gold foil can be used to achieve good beam homogeneity. The foil is placed 3 m in front of the chamber. The wobbler‐coils vibrate the beam horizontally and vertically, the proper sweeping area being attained with the adjustable coil‐currents. Dosimetry The flux and intensity dosimeter system contains a Faraday cup, several collimators, a scintillation counter and four PIN‐CsI(Tl) detectors. Three collimators of different size and shape are placed 25 cm in front of the device under test. They can be used to limit the beam to the active area to be studied. At low fluxes a plastic scintillator with a photomultiplier tube is used as an absolute particle counter. It is located behind the vacuum chamber and is used before the irradiation to normalize the count rates of the four PIN‐CsI(Tl) detectors. Range Beam energy LETSRIM at surface Ion [MeV.cm2.mg‐1] [µm] [MeV] 20 Ne6+ 3.63 146 186 40 12+ Ar 10.2 118 372 56 15+ Fe 18.5 97 523 82 22+ Kr 32.1 94 768 131 Xe35+ 60.0 89 1217 SRIM‐2003.26 Table 1 – Ion beam setting HRX/SEE/0540 Issue 01 Page:9 Hirex Engineering 5 Ref. : Issue : SEE Test Report HRX/SEE/0540 01 Test Set-up Test system Figure 2 shows the principle of the Heavy Ion test system. The test system is based on a Virtex5 FPGA (Xilinx). It runs at 50 MHz. The test board has 168 I/Os which can be configured using several I/O standards. The test board includes the voltage/current monitoring and the latch-up management of the DUT power supplies up to 24 independent channels. The communication between the test chamber and the controlling computer is effectively done by a 100 Mbit/s Ethernet link which safely enables high speed data transfer. Chamber Wall External to Chamber Temperature Control system Voltage/Current Monitoring External Power Supplies COMPUTER Graphical User Interface Signal Generators Internal to Chamber I/O Interface VIRTEX 5 FPGA LAN 4 Chanel 400MHz Digitizer DUTs BEAM COUNTER Figure 2 - Heavy ion test set-up 5.1 AD4077-2 test principle and conditions In order to test the AD4077-2, one daughter board was designed. 2DUTs were mounted on this board (Dut1 and Dut2 positions) and bias conditions are given in Figure 3 and Table 2. Table 3 gives the tester supply channel number used in the tester report. DUT heating is performed with a thermal resistor in contact with DUTs back side using a thermal conductive paste. The temperature is regulated thanks to a thermocouple sensor put on top of the DUT package. SEL event is detected when the supply current is over a configurable threshold (in the present case set to 100 mA for V+ and -100mA for V-) and processed (the power supplies are cut off during a configurable wait time, in the present case set to 1s). The tester monitors independently the 2 DUTs supplies at the same time. If an SEL is detected on 1 supply channel, the tester system records current/voltage on all channels. Supply name DUT_V+ DUT_VINPUT voltage +16.5V/15V/5V -16.5V/-15V/-5V Sine wave ±1V at 100 KHz Table 2 - Voltage bias conditions applied to the 2 DUTs Supply name DUT1_V+ DUT1_VDUT2_V+ DUT2_VINPUT HRX/SEE/0540 Issue 01 Tester supply channel # 1 2 3 4 17 Page:10 Hirex Engineering SEE Test Report Ref. : Issue : HRX/SEE/0540 01 Table 3 - Tester supply channel affectation Input: Sine wave ±1V at 100 KHz Supply voltage: ±16.5V max and ±15.0 and ±5.0V if SEL events are monitored Load resistance = 2 kΩ For DUT1 Channel A gain set to +1 Channel B gain set to -1 For DUT2 Channel A gain set to -1 Channel B gain set to +1 Figure 3 – AD4077-2 bias condition AD4077-2 DUT1 & 2 Supplies interface Figure 4 – Photo of test board HRX/SEE/0540 Issue 01 Page:11 Hirex Engineering 6 Ref. : Issue : SEE Test Report HRX/SEE/0540 01 SEE test results Runs performed are listed in Table 4. 3 boards have been tested with 2 AD4077-2 samples mounted on each board (Dut1 and Dut2 positions). Upon test completion, all samples were found fully functional SEL Results No SEL neither step current increase has been observed when tested with V+/- set to 16.5V at any LET value at 125°C with all tested samples. dut_part_number under test test_mode temperature ° C Ion LET MeV/(mg/cm2) roll tilt run_duration s achieved fluence ions/cm2 eff. LET MeV/(mg/cm2) 1,2 16.5V SEL 105 Ar 10.2 0 0 329 1.00E+07 10.2 OK 5 5 2 1,2 16.5V SEL 125 Ar 10.2 0 0 342 1.00E+07 10.2 OK 11 11 3 1,2 16.5V SEL 125 Ar 10.2 0 0 299 1.00E+07 10.2 OK 14 14 3 1,2 16.5V SEL 125 Fe 18.5 0 0 323 1.00E+07 18.5 OK vacuum 17 17 4 1,2 16.5V SEL 125 Fe 18.5 0 0 326 1.00E+07 18.5 OK vacuum 24 24 4 1,2 16.5V SEL 125 Kr 32.1 0 0 310 1.00E+07 32.1 OK RADEF vacuum 27 27 4 1,2 16.5V SEL 125 Kr 32.1 0 37 326 1.00E+07 40.2 OK RADEF vacuum 28 28 4 1,2 16.5V SEL 125 Kr 32.1 0 50 97 2.61E+06 49.9 OK RADEF vacuum 29 29 4 1,2 16.5V SEL 125 Kr 32.1 0 50 139 1.00E+07 49.9 OK RADEF vacuum 38 38 3 1,2 16.5V SEL 125 Kr 32.1 0 0 135 1.00E+07 32.1 OK RADEF vacuum 39 39 3 1,2 16.5V SEL 125 Kr 32.1 0 37 172 1.00E+07 40.2 OK RADEF vacuum 40 40 3 1,2 16.5V SEL 125 Kr 32.1 0 50 191 1.00E+07 49.9 OK RADEF vacuum 53 53 3 1,2 16.5V SEL 125 Xe 60 0 0 526 1.00E+07 60.0 OK RADEF vacuum 54 54 3 1,2 16.5V SEL 125 Xe 60 0 31 389 1.00E+07 70.0 OK RADEF vacuum 55 55 3 1,2 16.5V SEL 125 Xe 60 0 42 364 1.00E+07 80.7 OK RADEF vacuum 59 59 4 1,2 16.5V SEL 125 Xe 60 0 0 300 1.00E+07 60.0 OK RADEF vacuum 60 60 4 1,2 16.5V SEL 125 Xe 60 0 31 269 1.00E+07 70.0 OK RADEF vacuum 61 61 4 1,2 16.5V SEL 125 Xe 60 0 42 335 1.00E+07 80.7 OK vacuum RADEF vacuum RADEF vacuum RADEF vacuum RADEF RADEF dut_comment board_id 2 RADEF power_config Facility_run_number 4 medium 4 Facility hirex_run_number 6.1 Table 4 - Run table for AD4077-2, RADEF September 2015 HRX/SEE/0540 Issue 01 Page:12 Hirex Engineering 7 SEE Test Report Ref. : Issue : HRX/SEE/0540 01 Glossary Most of the definitions here below are from JEDEC standard JESD89A DUT: Device under test. Fluence (of particle radiation incident on a surface): The total amount of particle radiant energy incident on a surface in a given period of time, divided by the area of the surface. In this document, Fluence is expressed in ions per cm2. Flux: The time rate of flow of particle radiant energy incident on a surface, divided by the area of that surface. In this document, Flux is expressed in ions per cm2*s. Single-Event Effect (SEE): Any measurable or observable change in state or performance of a microelectronic device, component, subsystem, or system (digital or analog) resulting from a single energetic particle strike. Single-event effects include single-event upset (SEU), multiple-bit upset (MBU), multiple-cell upset (MCU), single-event functional interrupt (SEFI), single-event latch-up (SEL. Single-Event Transient (SET): A soft error caused by the transient signal induced by a single energetic particle strike. Single-Event Latch-up (SEL): An abnormal high-current state in a device caused by the passage of a single energetic particle through sensitive regions of the device structure and resulting in the loss of device functionality. SEL may cause permanent damage to the device. If the device is not permanently damaged, power cycling of the device (off and back on) is necessary to restore normal operation. An example of SEL in a CMOS device is when the passage of a single particle induces the creation of parasitic bipolar (p-n-p-n) shorting of power to ground. Single-Event Latch-up (SEL) cross-section: the number of events per unit fluence. For chip SEL cross-section, the dimensions are cm2 per chip. Error cross-section: the number of errors per unit fluence. For device error cross-section, the dimensions are cm2 per device. For bit error cross-section, the dimensions are cm2 per bit. Tilt angle: tilt angle, rotation axis of the DUT board is perpendicular to the beam axis; roll angle, board rotation axis is parallel to the beam axis HRX/SEE/0540 Issue 01 Page:13