Preliminary Data Sheet, DS3, July 2003 DuSLIC Dual Channel Subscriber Line Interface Concept PEB 3264, Version 1.4 PEB 3265, Version 1.5 PEB 4264/-2, Version 1.1/1.2 PEB 4364, Version 1.1/1.2 PEB 4265/-2, Version 1.1/1.2 PEB 4365, Version 1.2 PEB 4266, Version 1.2 Wired Communications N e v e r s t o p t h i n k i n g . ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®, 10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft Corporation. Linux® is a registered trademark of Linus Torvalds. The information in this document is subject to change without notice. Edition 2003-07-11 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Preliminary Data Sheet Revision History: 2003-07-11 DS3 Previous Version: DS2 Page Subjects (major changes since last revision) Title Product name corrected to Dual Channel Subscriber Line Interface Concept all PEB 3265 version changed from 1.2 to 1.5 all PEB 4264/-2 and PEB 4265/-2: version 1.2 added all PEB 4266 version changed from 1.1 to 1.2 all PEB 3264 version changed from 1.2 to 1.4 all Bit VRTLIM renamed to VTRLIM all Bit VRTLIM-M renamed to VTRLIM-M all New SLICs TSLIC-E and TSLIC-S added all New SLICOFI-2 (Version 1.5 only) package P-TQFP-64-1 added all New package P-VQFN-48-4 for SLIC-S/-S2, SLIC-E/-E2 and SLIC-P added all Former chapter 2 "Pin Descriptions" removed. See updated device data sheets. Page 18 “Overview” on Page 18: Chapter reworked, tables for codec and SLIC chips added. Page 23 “Features” on Page 23: ITU-T Recommendation G.712 added Page 25 “Logic Symbols” on Page 25: Logic symbol for SLIC-E/-E2 Version 1.2 added. Page 32 “Block Diagram SLICOFI-2/-2S” on Page 32: block diagrams of SLIC devices removed. Page 33 Figure 10 "Signal Paths – DC Feeding" on Page 33: CITA (CITB) renamed to CITACA (CITACB). Page 38 Table 4 "DC Characteristics" on Page 38: VLIM changed from 50 V to 72 V. Page 42 Figure 19 "Signal Paths – AC Transmission" on Page 42: CITA (CITB) renamed to CITACA (CITACB). Page 50 “Internal Balanced Ringing via SLICs” on Page 50: VDROP,RT renamed to VDROP,TR, VRT,RMS renamed to VTR,RMS, VRT0,RMS renamed to VTR0,RMS Page 61 Figure 30 "Bellcore On-Hook Caller ID Physical Layer Transmission" on Page 61: note added. Page 61 “Caller ID Buffer Handling of SLICOFI-2” on Page 61: description for listing item (9) changed Page 64 “Non Linear Processor (NLP) in DuSLIC-E/-E2/-P” on Page 64 added. Page 66 “MIPS Requirements for EDSP Capabilities” on Page 66 updated with NLP examples. Page 68 “Three-party Conferencing in DuSLIC-E/-E2/-P” on Page 68: sentence about Multi-party Conferencing added Page 84 “Hardware and Power On Reset” on Page 84: reset routine duration changed to 1.5 ms. Page 85 Figure 36 "DuSLIC Reset Sequence" on Page 85: textual description changed. Page 86 Table 17, “Default DC and AC Values” on Page 86: LX and LR changed. Page 88 “Recommended Procedure for Reading the Interrupt Registers” on Page 88 added. Page 90 “Power Management and Operating Modes” on Page 90: Power dissipation values and description updated. Page 94 “Integrated Test and Diagnostic Functions (ITDF)” on Page 94: ITDF is now also available for SLICOFI-2S. Page 94 Figure 3.8.1.2 "DuSLIC Line Testing" on Page 94: description on line testing capability modified. Page 97 “Using the Level Metering Integrator” on Page 97: timing for LM-OK bit added. Page 99 Figure 44, “Timing LM-OK Bit” on Page 99: 1 ms delay time for SLICOFI-2 Version 1.5 added. Page 101 Table 20 "KINTDC Setting Table" on Page 101: description about DuSLICOS settings added below. Page 113 “Capacitance Measurements” on Page 113: note on offset calibration added at the end of the chapter. Page 116 “Line Capacitance Measurements Ring and Tip to GND” on Page 116: description of last list item in section "Calculating parameter values" modified, description in table of section "Program Sequence" modified Page 137 Chapter 4.2.3, Operation with IOM-2 TE Devices (1.536 MHz) added. Page 139 “TIP/RING Interface” on Page 139: content removed - see device data sheets for detailed information. Page 144 “SOP Command” on Page 144: note on empty register bits added Page 151 Register XCR: Description for bit ASYNCH-R changed Page 152 Register INTREG1, bits HOOK and GNDK: description changes Page 154 Register INTREG2: reset value changed from 20H to 4FH, description for bit RSTAT modified Page 167 Register BCR1, bit SLEEP-EN: note added Page 170 Register BCR2: description added fot bits UTDX-SRC and PDOT-DIS Page 177 Register BCR5, bit DTMF-SRC: description added Page 179 Register DSCR, bit PTG: description added Page 203 “COP Command” on Page 203: note on empty register bits added Page 205 Table 35 "CRAM Coefficients" on Page 205: TTX Slope extended by nibbles 6 and 7 Page 207 “POP Command” on Page 207: note on the necessity of immediate programming added Page 207 “Sequence for POP Register Programming” on Page 207 added (because added NLP coefficients) Page 208 “POP Register Overview” on Page 208: NLP coefficients added Page 213 “POP Register Description” on Page 213: NLP coefficients added Page 233 Table 53 "Range of DeltaPLEC" on Page 233: "0x80 - no detection" added. Page 248 Register CIS/LEC-MODE: description added for bit UTDX-SUM and note on bit 3 added. Page 258 “Recommended NLP Coefficients” on Page 258 added Page 266 “SOP Command” on Page 266: note on empty register bits added Page 273 Register XCR: Description for bit ASYNCH-R changed Page 278 Register LMRES1: bits added. Page 278 Register LMRES2: bits added. Page 287 Register BCR1: bits added. Page 295 Register DSCR, bit PTG: description added Page 297 Register LMCR1: bits added. Page 299 Register LMCR2: bits added. Page 301 Register LMCR3: bits added. Page 315 “COP Command” on Page 315: note on empty register bits added Page 318 Table 73 "CRAM Coefficients" on Page 318: TTX slope extended by nibbles 6 and 7 Page 325 “Electrical Characteristics” on Page 325: SLIC and SLICOFI-2x data removed - for detailed information see device data sheets. Page 326 Table 76, “AC Transmission” on Page 326: Symbol VRT renamed to VTR Page 331 AC Transmission Characteristics: Values for Distortion and associated figures changed Page 342 “Input/Output Waveform for AC Tests” on Page 342 added. Page 344 PCM interface timings “Single-Clocking Mode” on Page 344 and “Double-Clocking Mode” on Page 346: FSC hold time (tFSC_h) renamed to FSC hold time 1 (tFSC_h1), FSC hold time 2 (tFSC_h2) added, formula of max. value for TCA/B delay time off (tdTCoff) modified Page 349 IOM-2 interface timings “Single-Clocking Mode” on Page 349 and “Double-Clocking Mode” on Page 351: FSC hold time (tFSC_h) renamed to FSC hold time 1 (tFSC_h1), FSC hold time 2 (tFSC_h2) added, parameters and timing of pin DU modified Period PCLK (tPCLK) for double clocking: formula for typ. value modified. Page 353 Figure 90, “Internal (balanced and unbalanced) Ringing with SLIC-P” on Page 353: pin TS2/CS changed to TS2/CS, illustration of connection between pins C3 and IO2A modified, SLIC supply voltages added, arrangement of diodes D1 and D2 modified. Page 355 Table 79, “External Components in Application Circuit DuSLIC-E/-E2/S/-S2/-P” on Page 355: tolerance of RSTAB and RPROT changed to 1%, footnote added. Page 357 Figure 92, “External Unbalanced Ringing with SLIC-E/-E2 or SLIC-S/S2” on Page 357: pin TS2/CS changed to TS2/CS, illustration of connection between pins C3 and IO2A modified,SLIC supply voltages added Page 359 Figure 94, “External Unb. Ringing (Long Loops) with SLIC-E/-E2 or SLIC-S/-S2” on Page 359: pin TS2/CS changed to TS2/CS, illustration of connection between pins C3 and IO2A modified, SLIC supply voltages added Page 363 Figure 97, “SLIC-S/-S2, SLIC-E/-E2, SLIC-P (PEB 426x)” on Page 363: note on SLIC clockwise pin counting added, security warning for all SLIC packages added DuSLIC Table of Contents Page 1 1.1 1.2 1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 23 24 25 2 2.1 2.1.1 2.1.2 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.4 2.4.1 2.4.2 2.4.3 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.6 2.7 2.7.1 2.7.2 2.7.2.1 2.8 2.8.1 2.8.2 2.8.2.1 2.8.3 2.8.4 2.8.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Functions of all DuSLIC Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . Additional Functions of the DuSLIC-E/-E2/-P Chip Sets . . . . . . . . . . . . Block Diagram SLICOFI-2/-2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristic Feeding Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Current Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistive Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Voltage Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Voltage and Current Range: DC Characteristics . . . . . SLIC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Necessary Voltage Reserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Battery Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringer Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ring Trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DuSLIC Ringing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Balanced Ringing via SLICs . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Unbalanced Ringing with SLIC-P . . . . . . . . . . . . . . . . . . . . . . . External Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signaling (Supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metering by 12/16 kHz Sinusoidal Bursts . . . . . . . . . . . . . . . . . . . . . . . Metering by Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DuSLIC Enhanced Signal Processing Capabilities . . . . . . . . . . . . . . . . . . DTMF Generation and Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Caller ID Generation in DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . . . . . . Caller ID Buffer Handling of SLICOFI-2 . . . . . . . . . . . . . . . . . . . . . . . Line Echo Cancellation in DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . . . . Non Linear Processor (NLP) in DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . Universal Tone Detection in DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . . 29 29 29 30 32 33 34 35 36 37 38 39 40 41 42 43 43 44 45 45 45 46 47 50 51 52 52 54 54 55 55 56 57 59 61 63 64 65 Preliminary Data Sheet 7 DS3, 2003-07-11 DuSLIC Table of Contents Page 2.8.6 2.9 2.10 2.10.1 2.11 MIPS Requirements for EDSP Capabilities . . . . . . . . . . . . . . . . . . . . . . Message Waiting Indication in DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . . . Three-party Conferencing in DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . . . . Conferencing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 kHz Mode on PCM Highways . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.6 3.6.1 3.7 3.7.1 3.7.2 3.7.2.1 3.7.2.2 3.7.2.3 3.8 3.8.1 3.8.1.1 3.8.1.2 3.8.2 3.8.2.1 3.8.2.2 3.8.2.3 3.8.2.4 3.8.2.5 3.8.2.6 3.8.2.7 3.8.2.8 3.8.2.9 3.8.2.10 3.8.2.11 3.8.2.12 3.8.2.13 3.9 3.9.1 3.9.2 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Overview of all DuSLIC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . 74 Operating Modes for the DuSLIC-S/-S2/-SE/-SE2 Chip Set . . . . . . . . . . . 78 Operating Modes for the DuSLIC-E/-E2/-ES/-ES2 Chip Set . . . . . . . . . . . 80 Operating Modes for the DuSLIC-P Chip Set . . . . . . . . . . . . . . . . . . . . . . 82 Reset Mode and Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Hardware and Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Recommended Procedure for Reading the Interrupt Registers . . . . . . . 88 Power Management and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . 90 SLICOFI-2x Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SLIC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Active Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Ringing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Integrated Test and Diagnostic Functions (ITDF) . . . . . . . . . . . . . . . . . . . 94 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Conventional Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 DuSLIC Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Line Test Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Integrated Signal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Result Register Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Using the Level Metering Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . 97 DC Level Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 AC Level Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Level Meter Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Current Offset Error Compensation . . . . . . . . . . . . . . . . . . . . . . . . . 110 Loop Resistance Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Line Resistance Tip/GND and Ring/GND . . . . . . . . . . . . . . . . . . . . 113 Capacitance Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Line Capacitance Measurements Ring and Tip to GND . . . . . . . . . 116 Foreign- and Ring Voltage Measurements . . . . . . . . . . . . . . . . . . . 116 Signal Path and Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 AC Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 DC Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Preliminary Data Sheet 8 66 67 68 69 71 DS3, 2003-07-11 DuSLIC Table of Contents Page 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.3 4.3 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface with a Serial Microcontroller Interface . . . . . . . . . . . . . . . PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control of the Active PCM Channels . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . . SLICOFI-2x Identification Command . . . . . . . . . . . . . . . . . . . . . . . . . . Operation with IOM-2 TE Devices (1.536 MHz) . . . . . . . . . . . . . . . . . TIP/RING Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 122 122 126 127 129 133 137 137 139 5 5.1 5.2 5.2.1 5.2.1.1 5.2.1.2 5.2.2 5.2.2.1 5.2.3 5.2.3.1 5.2.3.2 5.2.3.3 5.2.3.4 5.2.4 5.2.5 5.2.5.1 5.2.5.2 5.3 5.3.1 5.3.1.1 5.3.1.2 5.3.2 5.3.2.1 5.3.3 5.3.4 5.3.4.1 5.3.4.2 SLICOFI-2x Command Structure and Programming . . . . . . . . . . . . . Overview of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2 Command Structure and Programming . . . . . . . . . . . . . . . . . SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequence for POP Register Programming . . . . . . . . . . . . . . . . . . . POP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended NLP Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Command/Indication Byte . . . . . . . . . . . . . . . . . . . . . Programming Examples of the SLICOFI-2 . . . . . . . . . . . . . . . . . . . . . Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2S Command Structure and Programming . . . . . . . . . . . . . . . SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Command/Indication Byte . . . . . . . . . . . . . . . . . . . . . Programming Examples of the SLICOFI-2S . . . . . . . . . . . . . . . . . . . . Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 143 144 144 144 149 203 206 207 207 208 213 258 260 262 262 263 266 266 266 271 315 319 320 322 322 323 6 6.1 6.1.1 6.1.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Transmission DuSLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Tracking (Receive or Transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . 325 325 334 335 Preliminary Data Sheet 9 DS3, 2003-07-11 DuSLIC Table of Contents Page 6.1.3 6.1.4 6.1.5 6.1.6 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.3.1 6.4.3.2 6.4.4 6.4.5 6.4.5.1 6.4.5.2 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Out-of-Band Signals at Analog Output (Receive) . . . . . . . . . . . . . . . . Out-of-Band Signals at Analog Input (Transmit) . . . . . . . . . . . . . . . . . Total Distortion Measured with Sine Wave . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DuSLIC Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DuSLIC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . MCLK/FSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 336 338 339 341 342 342 342 343 344 344 346 348 349 349 351 7 7.1 7.1.1 7.1.2 7.2 7.2.1 7.3 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Ringing (Balanced/Unbalanced) . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Diagrams Internal Ringing (Balanced & Unbalanced) . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Unbalanced Ringing with DuSLIC-E/-E2/-S/-S2/-P . . . . . . . . . . Circuit Diagrams External Unbalanced Ringing . . . . . . . . . . . . . . . . . . DuSLIC Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 352 353 355 356 357 361 8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 9 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 10 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Preliminary Data Sheet 10 DS3, 2003-07-11 DuSLIC List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Page DuSLIC Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol: SLICOFI-2/-2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol: SLIC-S/SLIC-S2 (V1.1, V1.2), SLIC-E/SLIC-E2 (V1.1) Logic Symbol: SLIC-E/SLIC-E2 (V1.2) . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol: SLIC-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol: TSLIC-S/TSLIC-E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Circuit Functions in the DuSLIC-S/-S2 . . . . . . . . . . . . . . . . . . . . . Line Circuit Functions in the DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . Block Diagram: SLICOFI-2/-2S (PEB 3265, PEB 3264) . . . . . . . . . . . Signal Paths – DC Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Feeding Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Current Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistive Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Voltage Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTX Voltage Reserve Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Feeding Characteristics (ACTH, ACTR) . . . . . . . . . . . . . . . . . . . . Signal Paths – AC Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Flow in Voice Channel (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nyquist Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Ringer Loads of 1 and 5 REN used in USA. . . . . . . . . . . . . . . External Ringing Zero Crossing Synchronization . . . . . . . . . . . . . . . . Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC-P. . . . . . . . . . . . Unbalanced Ringing Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Teletax Injection and Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft Reversal (Example for Open Loop) . . . . . . . . . . . . . . . . . . . . . . . DuSLIC AC Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DuSLIC EDSP Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bellcore On-Hook Caller ID Physical Layer Transmission . . . . . . . . . . Line Echo Cancellation Unit Block Diagram . . . . . . . . . . . . . . . . . . . . UTD Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MWI Circuitry with Glow Lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conference Block for One DuSLIC Channel . . . . . . . . . . . . . . . . . . . . DuSLIC Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical SLIC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DuSLIC Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level Metering Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Measurement Sequence (AC & DC Level Metering) . . . . . . . . Continuous Measurement Sequence (DC Level Metering) . . . . . . . . . Preliminary Data Sheet 11 22 25 26 26 27 28 31 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 49 50 51 54 55 56 56 61 63 65 67 68 69 85 89 92 94 96 97 98 DS3, 2003-07-11 DuSLIC List of Figures Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Page Continuous Measurement Sequence (AC Level Metering) . . . . . . . . . 98 Timing LM-OK Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Example Resistance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Differential Resistance Measurement . . . . . . . . . . . . . . . . . . . . . . . . 112 Capacitance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Foreign Voltage Measurement Principle . . . . . . . . . . . . . . . . . . . . . . 117 AC Test Loops DuSLIC-E/-E2/-P/-ES/-ES2 . . . . . . . . . . . . . . . . . . . . 119 AC Test Loops DuSLIC-S/-S2/-SE/-SE2 . . . . . . . . . . . . . . . . . . . . . . 120 DC Test Loops DuSLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 General PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Setting the Slopes in Register PCMC1 . . . . . . . . . . . . . . . . . . . . . . . 125 Serial Microcontroller Interface Write Access . . . . . . . . . . . . . . . . . . 128 Serial Microcontroller Interface Read Access . . . . . . . . . . . . . . . . . . 128 IOM-2 I/F Timing for up to 16 Voice Channels (Per 8 kHz Frame) . . 130 IOM-2 Interface Timing (DCL = 4096 kHz, Per 8 kHz Frame) . . . . . . 131 IOM-2 Interface Timing (DCL = 2048 kHz, Per 8 kHz Frame) . . . . . . 131 IOM-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . 133 State Diagram of the SLICOFI-2x Monitor Transmitter . . . . . . . . . . . 135 State Diagram of the SLICOFI-2x Monitor Receiver . . . . . . . . . . . . . 136 PCM/mC Mode used for IOM-2 TE Interface at 1.536 MHz. . . . . . . . 138 Example for Switching Between Different Ring Offset Voltages . . . . 187 Example for UTD Recognition Timing . . . . . . . . . . . . . . . . . . . . . . . . 256 Example for UTD Tone End Detection Timing . . . . . . . . . . . . . . . . . . 258 Waveform of Programming Example SOP-Write to Channel 0 . . . . . 262 Waveform of Programming Example SOP Read from Channel 0 . . . 263 Example for Switching Between Different Ring Offset Voltages . . . . 303 Waveform of Programming Example SOP Write to Channel 0 . . . . . 322 Waveform of Programming Example SOP Read from Channel 0 . . . 322 Signal Definitions Transmit, Receive . . . . . . . . . . . . . . . . . . . . . . . . . 325 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Frequency Response Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Frequency Response Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Gain Tracking Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Gain Tracking Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Group Delay Distortion Receive and Transmit. . . . . . . . . . . . . . . . . . 336 Out-of-Band Signals at Analog Output (Receive) . . . . . . . . . . . . . . . 337 Out-of-Band Signals at Analog Input (Transmit) . . . . . . . . . . . . . . . . 338 Total Distortion Transmit (LX = 0 dBr) . . . . . . . . . . . . . . . . . . . . . . . . 339 Total Distortion Receive (LR = –7 dBr) . . . . . . . . . . . . . . . . . . . . . . . 339 Total Distortion Receive (LR = 0 dBr) . . . . . . . . . . . . . . . . . . . . . . . . 340 Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 MCLK/FSC-Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Preliminary Data Sheet 12 DS3, 2003-07-11 DuSLIC List of Figures Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 Figure 99 Figure 100 Figure 101 Figure 102 Page PCM Interface Timing – Single-Clocking Mode . . . . . . . . . . . . . . . . . PCM Interface Timing – Double-Clocking Mode . . . . . . . . . . . . . . . . Microcontroller Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Timing – Single-Clocking Mode . . . . . . . . . . . . . . . . IOM-2 Interface Timing – Double-Clocking Mode . . . . . . . . . . . . . . . Internal (balanced and unbalanced) Ringing with SLIC-P . . . . . . . . . Internal (balanced) Ringing with SLIC-E/-E2 or SLIC-S/-S2 . . . . . . . External Unbalanced Ringing with SLIC-E/-E2 or SLIC-S/-S2. . . . . . External Unbalanced Ringing with SLIC-P . . . . . . . . . . . . . . . . . . . . External Unb. Ringing (Long Loops) with SLIC-E/-E2 or SLIC-S/-S2 External Unbalanced Ringing (Long Loops) with SLIC-P . . . . . . . . . DuSLIC Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIC-S/-S2, SLIC-E/-E2, SLIC-P (PEB 426x) . . . . . . . . . . . . . . . . . . SLIC-S/-S2, SLIC-E/-E2, SLIC-P (PEB426x). . . . . . . . . . . . . . . . . . . TSLIC-S (PEB 4364) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSLIC-E (PEB 4365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2x (PEB 3265, PEB 3264) . . . . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2x (PEB 3265, PEB 3264) . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Data Sheet 13 344 346 348 349 351 353 354 357 358 359 360 362 363 364 365 366 367 368 DS3, 2003-07-11 DuSLIC List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Page Codec Feature Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SLIC Feature Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DuSLIC Chip Sets Presented in this Data Sheet . . . . . . . . . . . . . . . . . 20 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ringing Options with SLIC-S, SLIC-E/-E2 and SLIC-P . . . . . . . . . . . . 47 Performance Characteristics of the DTMF Decoder Algorithm . . . . . . 58 FSK Modulation Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MIPS Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Conferencing Modes: Receive Channels. . . . . . . . . . . . . . . . . . . . . . . 69 Conferencing Modes: Transmit Channels . . . . . . . . . . . . . . . . . . . . . . 70 Possible Modes in PCM/∝C Interface Mode: Receive Channels . . . . . 72 Possible Modes in PCM/∝C Interface Mode: Transmit Channels . . . . 72 Overview of all DuSLIC Operating Modes . . . . . . . . . . . . . . . . . . . . . . 74 DuSLIC-S/-S2/-SE/-SE2 Operating Modes . . . . . . . . . . . . . . . . . . . . . 78 DuSLIC-E/-E2/-ES/-ES2 Operating Modes . . . . . . . . . . . . . . . . . . . . . 80 DuSLIC-P Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Default DC and AC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Level Metering Result Value Range . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Selecting DC Level Meter Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 KINTDC Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 NSamples Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Level Meter Results with and without Integrator Function . . . . . . . . . 103 Selecting AC Level Meter Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 KINTAC Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 KTG Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Threshold Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Measurement Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SLICOFI-2x PCM Interface Configuration . . . . . . . . . . . . . . . . . . . . . 124 Active PCM Channel Configuration Bits . . . . . . . . . . . . . . . . . . . . . . 126 IOM-2 Time Slot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . 141 Valid DTMF Keys (Bit DTMF-KEY4 = 1) . . . . . . . . . . . . . . . . . . . . . . 155 DTMF Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Typical Usage for the three Ring Offsets . . . . . . . . . . . . . . . . . . . . . . 187 CRAM Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Range of TPOW-LPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Range of Twistacc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Range of TPOW-LPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Range of PowBN-LEV-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Range of PowBN-LEV-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Range of TBN-INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Preliminary Data Sheet 14 DS3, 2003-07-11 DuSLIC List of Tables Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Page Range of TBN-DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Ranges of GDTMF[dB] dependent on “e” . . . . . . . . . . . . . . . . . . . . . 224 Example for DTMF-GAIN Calculation . . . . . . . . . . . . . . . . . . . . . . . . 224 Range of PowBN-MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Range for DeltaBN-ADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Range of ERLLRE-MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Range of ERLLRE-EST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Range of SSD-LEV-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Range of PowLECR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Range of SSD-LEV-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Range of DeltaPLEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Range of DeltaSD-LEV-BN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Examples for DeltaQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Range of DeltaSD-LEV-RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Ranges of GLEC-XI[dB] Dependent on “e” . . . . . . . . . . . . . . . . . . . . 237 Example for LEC-GAIN-XI Calculation . . . . . . . . . . . . . . . . . . . . . . . 237 Range of tSD-OT-DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Ranges of GLEC-RI[dB] Dependent on “e” . . . . . . . . . . . . . . . . . . . . 239 Example for LEC-GAIN-RI Calculation . . . . . . . . . . . . . . . . . . . . . . . 239 Range of TERL-LIN-LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Ranges of GLEC-X0[dB] Dependent on “e” . . . . . . . . . . . . . . . . . . . . 241 Example for LEC-GAIN-X0 Calculation . . . . . . . . . . . . . . . . . . . . . . . 241 Range of TERL-LEC-LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Range of DeltaCT-LEV-RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Range of LevCIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 UTD Inband/Outband Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Recommended NLP Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . 260 DTMF Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Typical Usage for the three Ring Offsets . . . . . . . . . . . . . . . . . . . . . . 303 CRAM Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . 320 AC Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Group Delay Absolute Values: Signal level 0 dBm0 . . . . . . . . . . . . . 336 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 External Components in Application Circuit DuSLIC-E/-E2/-S/-S2/-P 355 Preliminary Data Sheet 15 DS3, 2003-07-11 DuSLIC Preface This Preliminary Data Sheet describes the family of DuSLIC chip sets. Each chip set comprises a dual channel SLICOFI-2x codec and two single- or one dual-channel SLICs. For more DuSLIC related documents, please see our webpage at http://www.infineon.com/duslic. To simplify matters, the following synonyms are used: SLICOFI-2x: Synonym used for all codec versions SLICOFI-2/-2S SLIC: Synonym used for all SLIC versions SLIC-S/-S2, TSLIC-S, SLIC-E/-E2, TSLIC-E and SLIC-P. Attention: The TSLIC-S (PEB 4364) and TSLIC-E (PEB 4365) chips are dual channel versions of the SLIC-S (PEB 4364) and SLIC-E (PEB 4365) with identical technical specifications for each channel. Therefore whenever SLIC-S or SLIC-E are mentioned in the specification, also TSLIC-S and TSLIC-E can be deployed. Organization of this Document • Chapter 1, Overview A general description of the chip set, the key features, and some typical applications. • Chapter 2, Functional Description The main functions of the chip set are presented with functional block diagrams. • Chapter 3, Operational Description A brief description of the operating modes, the power management, and the integrated test and diagnostic functions. • Chapter 4, Interfaces Connection information including standard IOM-2 and PCM interface timing frames and pins. Chapter 5, SLICOFI-2x Command Structure and Programming A general description of the SLICOFI-2x command structure. • • Chapter 6, Electrical Characteristics Parameters, symbols, and limit values are provided for the chip set. • Chapter 7, Application Circuits External components and layout recommendations are identified. Illustrations of balanced ringing, unbalanced ringing, and protection circuits are included. • Chapter 8, Package Outlines Illustrations and dimensions of the package outlines. Preliminary Data Sheet 16 DS3, 2003-07-11 DuSLIC • Chapter 9, Terminology List of abbreviations and descriptions of symbols. • Chapter 10, Index Preliminary Data Sheet 17 DS3, 2003-07-11 DuSLIC Overview 1 Overview DuSLIC is a family of communications chip sets. Each chip set comprises one dual-channel SLICOFI-2x codec and two single-channel SLICs or one dual-channel TSLIC. It is a highly flexible codec/SLIC solution for an analog line circuit and is easily programmable via software. Users can now serve different markets with a single hardware design that meets all standards worldwide. The key benefits of the DuSLIC family include: Integrated DSP Features • • • • Line echo cancellation (up to 8 ms) DTMF Caller-ID Full V.90 performance Integrated Ringing • • • Balanced ringing up to 85 Vrms Unbalanced ringing up to 50 Vrms Full support for external ringing Smallest Footprint • • Only 121 mm² per channel Minimum external components System Features • • Test & diagnostic functions (complete AC & DC) Time-slot assignment on two PCM highways Proven Technology • • • A single hardware design meets/exceeds worldwide requirements. 15+ years experience. Several million lines deployed worldwide. Preliminary Data Sheet 18 DS3, 2003-07-11 DuSLIC Overview The DuSLIC family allows any combination of the codec and SLIC chips shown in Table 1 and Table 2. Table 1 Codec Feature Overview Features SLICOFI-2 SLICOFI-2S Number of Voice Channels 2 2 DTMF Detection Yes No Line Echo Cancellation (up to 8 ms) Yes No Caller-ID Generation Yes No Integrated Test and Diagnostics (Linetesting) Yes Yes Modem (V.90) transmission Yes Yes Modem tone detection Yes No Metering pulses (TTX) up to 2.5 Vrms up to 1.2 Vrms PCM/Serial Controller Interface Yes Yes IOM2 Interface Yes Yes Internal Ring Support Yes Yes External Ringing Support Yes Yes Supply Voltage 3.3 V 3.3 V Table 2 SLIC Feature Overview Features SLIC-S/ SLIC-S22) SLIC-E/ SLIC-E24) SLIC-P 1) 3) TSLIC-S TSLIC-E Maximum DC Feeding 32 mA 50 mA 32 mA 50 mA 32 mA Maximum Ringing Voltage (balanced) 45 Vrms 45 Vrms 85 Vrms 85 Vrms 85 Vrms Maximum Ringing Voltage (unbalanced) – – – – 50 Vrms Longitudinal Balance 53 dB 60 dB 53 dB 60 dB 53 dB Supply Voltages (negative/positive) 2/1 2/1 2/1 2/1 3/0 Supply Voltage 3.3 V... 5V 3.3 V... 5V 5.0 V 5.0 V 3.3 V External Ring Support Yes Yes Yes Yes Yes Preliminary Data Sheet 19 DS3, 2003-07-11 DuSLIC Overview Table 2 SLIC Feature Overview (cont’d) Features SLIC-S22) SLIC-E/ SLIC-E24) SLIC-P SLIC-S/ TSLIC-E3) TSLIC-S1) Technology 90 V 90 V 170 V 170 V 170 V On-Hook Transmission Yes Yes Yes Yes Yes Current Limitation 105 mA 105 mA 105 mA 105 mA 60/90 mA Target Application Low Cost CPE Linecard (external ringing) CPE Linecard Low Power CPE 1) Same specifications as SLIC-S, but two voice channels 2) Chip marked as PEB 4264 – packaging unit labeled with PEB 4264-2. 3) Same specifications as SLIC-E, but two voice channels 4) Chip marked as PEB 4265 – packaging unit labeled with PEB 4265-2. To allow the most cost effective and feature optimized design the following table presents the available SLIC and Codec combinations. The choice of different combinations meets world wide design requirements. Table 3 DuSLIC Chip Sets Presented in this Data Sheet Chip Set DuSLIC-S/ -S2 Marketing Name SLICOFI-2S/ SLICOFI-2S/ SLICOFI-2/ SLIC-S/-S2 SLIC-E/-E2 SLIC-S/-S2 (TSLIC-S)1) (TSLIC-E)2) (TSLIC-S)1) Product ID PEB 3264/ PEB 3264/ PEB 3265/ PEB 3265/ PEB 3265/ PEB 4264/-2 PEB 4265/-2 PEB 4264/-2 PEB 4265/-2 PEB 4266 (PEB 4364) (PEB 4365) (PEB 4364) (PEB 4365) DuSLICSE/-SE2 DuSLICES/-ES2 DuSLIC-E/ -E2 DuSLIC-P SLICOFI-2/ SLIC-E/-E2 (TSLIC-E)2) SLICOFI-2/ SLIC-P 1) Single channel SLIC-S or dual channel TSLIC-S package 2) Single channel SLIC-E or dual channel TSLIC-E package • The DuSLIC chip sets presented in this Data Sheet are differentiated in terms of the DSP features and ringing voltage : – DuSLIC-S (Standard) – DuSLIC-SE (Standard Codec, Enhanced SLIC) – DuSLIC-ES (Enhanced Codec, Standard SLIC) – DuSLIC-E (Enhanced) – DuSLIC-P (Power Management). Preliminary Data Sheet 20 DS3, 2003-07-11 DuSLIC Overview • For both the DuSLIC-S and DuSLIC-E there are also long-haul versions, offering increased longitudinal balance (60 dB) : – DuSLIC-E2 (using SLIC-E2) – DuSLIC-S2 (using SLIC-S2) Usage of Codecs and SLICs The DuSLIC-S and DuSLIC-S2 chip sets use the SLICOFI-2S (PEB 3264) codec offering full basic POTS functionality, including programmable AC and DC characteristics, integrated ringing and Integrated Test & Diagnostic Functions (ITDF) etc. The DuSLIC-E, DuSLIC-E2, and DuSLIC-P chip sets use the same SLICOFI-2 (PEB 3265) codec with full EDSP (Enhanced Digital Signal Processor) features such as DTMF detection, Caller ID generation, Universal Tone Detection (UTD) and Line Echo Cancellation (LEC). These codecs (SLICOFI-2 and SLICOFI-2S) are manufactured using an advanced 0.35 µm 3.3 V CMOS process. The main criteria for choosing the appropriate SLIC device, are the ringing voltage and longitudinal balance. • • • SLIC-S and SLIC-S2 offer balanced ringing (up to 45 Vrms) SLIC-E and SLIC-E2 offer balanced ringing (up to 85 Vrms) SLIC-P offers both balanced (85Vrms) and unbalanced ringing (50 Vrms) Note: the above ring voltages are achievable with 20 Vdc offset. Smaller dc offset will increase the maximum achievable ring voltage The SLIC-S2 and SLIC-E2 are optimized for longhaul applications, and offer a minimum of 60 dB longitudinal balance. All Infineon SLICs are manufactured in our well-proven 90 V and 170 V Smart Power Technology (SPT) processes. Dual-channel SLICs : TSLIC-S & TSLIC-E The TSLIC-S (PEB 4364) and TSLIC-E (PEB 4365) chips are dual channel versions of the SLIC-S (PEB 4264) and SLIC-E (PEB 4265) with identical technical specifications for each channel. Therefore whenever SLIC-S or SLIC-E are mentioned in this and other DuSLIC documentation, also TSLIC-S and TSLIC-E can be deployed. DuSLIC Architecture Unlike traditional designs, DuSLIC splits the SLIC function into high-voltage SLIC functions and low-voltage SLIC functions. The low-voltage functions are handled in the SLICOFI-2x device. The partitioning of the functions is shown in Figure 1. Preliminary Data Sheet 21 DS3, 2003-07-11 DuSLIC Overview For further information see Chapter 2.1. PCM SLIC µC SLICOFI-2x IOM®-2 SLIC HV SLIC Functions LV SLIC Functions Codec Filter Functions Voltage feeding Transversal current sensing Longitudinal current sensing Overload protection Battery switching Ring amplification On-hook transmission Polarity reversal Programmable DC feeding Ring generation Supervision Teletax generation Teletax notch filter Ring trip detection Ground key detection Hook switch detection Filtering A-law/µ-law companding Programmable gain Programmable frequency Impedance matching Trans-hybrid balance DTMF generation DTMF detection FSK generation (Caller ID) Linear mode support (16-bit uncompressed voice data) IOM-2 and PCM/µC interface Integrated Test and Diagnostic Functions (ITDF) Line Echo Cancellation (LEC) Universal Tone Detection (UTD) Three-party conferencing Message waiting lamp support ezm14034 Figure 1 DuSLIC Chip Set Preliminary Data Sheet 22 DS3, 2003-07-11 Dual Channel Subscriber Line Interface Concept DuSLIC 1.1 • • • • • • • • • • • • • • • • • • • PEB 3264 PEB 3265 PEB 4264/-2 PEB 4364 PEB 4265/-2 PEB 4365 PEB 4266 Features Fully programmable dual-channel codec Programmable AC and DC characteristics Integrated Test and Diagnostic Functions (ITDF) Programmable integrated ringing : Balanced (85 Vrms) and/or Unbalanced (50 Vrms) Programmable Teletax (TTX) generation Programmable battery feeding with capability for driving longer loops Ground start/loop start signaling supported Polarity reversal (hard or soft) On-hook transmission Integrated DTMF generator Integrated DTMF decoder Integrated Caller ID generator (FSK or DTMF) Universal Tone Detection (UTD) - fax/modem detection Integrated Line Echo Cancellation (LEC) up to 8 ms Optimized filter structure for modem transmission Three-party conferencing (in PCM/µC mode) Message waiting lamp support (PBX) Power optimized architecture Power management capability (integrated battery switches) P-MQFP-64-1,-2 P-TQFP-64-1 P-DSO-20-5 P-VQFN-48-4 P-DSO-36-15 P-DSO-36-12, -10 Type Package PEB 3264 P-MQFP-64-1 or P-TQFP-64-1 PEB 3265 P-MQFP-64-1 or P-TQFP-64-1 PEB 4264/-2 P-DSO-20-5 or P-VQFN-48-4 PEB 4364 P-DSO-36-15 PEB 4265/-2 P-DSO-20-5 or P-VQFN-48-4 PEB 4365 P-DSO-36-15 PEB 4266 P-DSO-20-5 or P-VQFN-48-4 Preliminary Data Sheet 23 2003-07-11 DuSLIC Overview • • • • 8 kHz and 16 kHz PCM Transmission IOM-2 or PCM/µC Interface selectable G.711 A-law / µ-law companding Specifications: ITU-T G.712, Q.552, LSSGR, TR57 1.2 Typical Applications DuSLIC offers an optimized solution for various applications. applications can be highlighted: • • The following main Access Networks – Central Office (CO) – Next-Generation Digital Subscriber Line Access Module (NG-DSLAM) – Digital Loop Carrier (DLC) – Wireless Local Loop (WLL) – Fiber in the Loop (FITL) – Digital Added Main Line (DAML) / PCM-x – Multi-dwelling / Multi-tennant units (MDU / MTU) Customer Premises Equipment – Private Branch Exchange (PBX) – Integrated Access Device (IAD) – Voice over Packet (VoDSL, VoIP, VoATM, etc.) – ISDN Intelligent Network Termination (iNT) – ISDN Terminal Adapter (TA) – Cable Modem – xDSL NT – Router Preliminary Data Sheet 24 DS3, 2003-07-11 DuSLIC Overview 1.3 Logic Symbols ITA ITB ITACA ITACB ILA ILB VCMITA VCMITB Line current PCM/IOM-2 DCPA DCPB DCNA DCNB DC loop CDCPA CDCNA CDCPB CDCNB VCM VCMS PEB 3265 PEB 3264 Logic control C1A C1B C2A C2B I/O feeding IO1A IO2A IO3A IO4A IO1B IO2B IO3B IO4B IOM-2 interface µC-interface PCM interface RSYNC RESET TEST ACPA ACPB ACNA ACNB AC loop INT TS0/DIN TS1/DCLK TS2/CS DU/DOUT DD/DRB SEL24/DRA DCL/PCLK FSC MCLK DXA DXB TCA TCB CREF SELCLK VDDA VDDB GNDA GNDB VDDR GNDR VDDD GNDD VDDPLL GNDPLL Power supply ezm14096 Figure 2 Logic Symbol: SLICOFI-2/-2S Preliminary Data Sheet 25 DS3, 2003-07-11 DuSLIC Overview Tip/Ring interface Power supply VCMS CEXT TIP PEB 4264 PEB 4264-2 PEB 4265 VDD AGND PEB 4265-2 RING VHR BGND VBATL VBATH IT IL ACP ACN DCP DCN C1 C2 Line current AC & DC feeding Logic control ezm14094 Figure 3 Logic Symbol: SLIC-S/SLIC-S2 (V1.1, V1.2), SLIC-E/SLIC-E2 (V1.1) Tip/Ring interface VCMS CEXT TIP RING IT IL PEB 4265/-2 VDD AGND Power supply VHR BGND VBATL VBATH ACP ACN DCP DCN C1 C2 C3 Scaled line current outputs AC & DC input voltage Logic control ezm14094_12 Figure 4 Logic Symbol: SLIC-E/SLIC-E2 (V1.2) Preliminary Data Sheet 26 DS3, 2003-07-11 DuSLIC Overview VCMS CEXT Tip/Ring interface TIP IT IL RING PEB 4266 VDD AGND Power supply ACP ACN DCP DCN C1 C2 C3 BGND VBATL VBATH VBATR Line current AC & DC feeding Logic control ezm14095 Figure 5 Logic Symbol: SLIC-P Preliminary Data Sheet 27 DS3, 2003-07-11 DuSLIC Overview Tip/Ring interface channel A VCMSA CEXTA TIPA RINGA ITA ILA VDDA AGNDA channel A Power supply channel A Tip/Ring interface channel B VHRA BGNDA VBATH VBATLA TIPB Power supply channel B AC & DC feeding channel A C1A C2A Logic control channel A ITB ILB VDDB AGNDB channel B ACPA ACNA DCPA DCNA PEB 4364 PEB 4365 VCMSB CEXTB RINGB VHRB BGNDB VBATH VBATLB Line current channel A Line current channel B ACPB ACNB DCPB DCNB AC & DC feeding channel B C1B C2B Logic control channel B ezm14094TT Figure 6 Logic Symbol: TSLIC-S/TSLIC-E Preliminary Data Sheet 28 DS3, 2003-07-11 DuSLIC Functional Description 2 Functional Description 2.1 Functional Overview 2.1.1 Basic Functions of all DuSLIC Chip Sets The functions described in this section are integrated into all DuSLIC chip sets (see Figure 7 for DuSLIC-S/-S2 and Figure 8 for DuSLIC-E/-E2/-P). All BORSCHT functions are integrated: • • • • • • • Battery feed Overvoltage protection (implemented by the robust high-voltage SLIC technology and additional circuitry) Ringing1) Signaling (supervision) Coding Hybrid for 2/4-wire conversion Testing An important feature of the DuSLIC design is the fact that all the SLIC and codec functions are programmable via the IOM-2 or PCM/µC Interface of the dual-channel SLICOFI-2x device: • • • • • • • • • • DC (battery) feed characteristics AC impedance matching Transmit gain Receive gain Hybrid balance Frequency response in transmit and receive direction Ring frequency and amplitude1) Hook thresholds TTX modes2) DTMF/tone generator Because signal processing within the SLICOFI-2x is completely digital, it is possible to adapt to the requirements listed above by simply updating the coefficients that control DSP processing of all data. This means, for example, that changing impedance matching or hybrid balance requires no hardware modifications. A single hardware design is now capable of meeting the requirements for different markets. The digital nature of the filters and gain stages also assures high reliability, no drifts (over temperature or time), and minimal variations between different lines. 1) For the DuSLIC-S2 chip set, only external ringing is supported 2) Not available with the DuSLIC-S2 chip set Preliminary Data Sheet 29 DS3, 2003-07-11 DuSLIC Functional Description The characteristics for the two voice channels within SLICOFI-2x can be programmed independently of each other. The DuSLIC Coefficients Software (DuSLICOS) is provided to automate calculation of coefficients to match different requirements. DuSLICOS also verifies the calculated coefficients. 2.1.2 Additional Functions of the DuSLIC-E/-E2/-P Chip Sets The following line circuit functions are integrated only in the DuSLIC-E/-E2/-P chip sets (see Figure 8): • Teletax metering For pulse metering, a 12/16 kHz sinusoidal metering burst must be transmitted. The DuSLIC chip set generates the metering signal internally and has an integrated notch filter. • DTMF DuSLIC has an integrated DTMF generator comprising two tone generators and one DTMF decoder. The decoder is able to monitor the transmit or receive path for valid tone pairs and outputs the corresponding digital code for each DTMF tone pair. • Caller ID Frequency Shift Keying (FSK) Modulator DuSLIC has an integrated FSK modulator capable of sending Caller ID information. The Caller ID modulator complies with all requirements of ITU-T Recommendation V.23 and Bell 202 (Caller ID can also be done using DTMF generators). • Line Echo Cancellation (LEC) DuSLIC contains an adaptive Line Echo Cancellation unit for the cancellation of near end echoes (up to 8 ms cancelable echo delay time). • Universal Tone Detection (UTD) DuSLIC has an integrated Universal Tone Detection unit to detect special tones in the receive or transmit path (e.g. fax or modem tones). Preliminary Data Sheet 30 DS3, 2003-07-11 DuSLIC Functional Description SLIC-S/-S2 Current Sensor & Offhook Detection TIP TTX Metering Supervision Gain Channel A RING Battery Switch Control Logic SLIC-S/-S2 Current Sensor & Offhook Detection TIP SLICOFI-2S Gain Control Logic ADC DAC Hardware Filters Channel B Prefilter Postfilter RING Battery Switch Prefilter Postfilter SLIC-S/-S2 Interface Control ADC DAC Hardware Filters Programmable Filters and Gain A-Law or µ-Law Digital Signal Processing (DSP) Compander Programmable Filters and Gain A-Law or µ-Law Ringing Controller PCM Interface PCM / IOM-2 Interface IOM-2 Interface Serial µC Interface DCCTL one SLICOFI-2S channel both SLICOFI-2S channels ezm22020 Figure 7 Line Circuit Functions in the DuSLIC-S/-S2 SLIC-E/-E2/-P Current Sensor & Offhook Detection TIP Gain Control Logic SLIC-E/-E2/-P Current Sensor & Offhook Detection TIP Gain RING Battery Switch Supervision Level Metering TTX Metering CID Generation LEC UTD DTMF Channel A RING Battery Switch SLICOFI-2 Control Logic Prefilter Postfilter ADC DAC Hardware Filters Channel B Prefilter Postfilter SLIC-E/-E2/-P Interface Control ADC DAC Hardware Filters Programmable Filters and Gain A-Law or µ-Law Digital Signal Processing (DSP) Compander Programmable Filters and Gain A-Law or µ-Law Controller Ringing PCM / IOM-2 Interface DCCTL one SLICOFI-2 channel PCM Interface IOM-2 Interface Serial µC Interface both SLICOFI-2 channels ezm22007 Figure 8 Line Circuit Functions in the DuSLIC-E/-E2/-P Preliminary Data Sheet 31 DS3, 2003-07-11 DuSLIC Functional Description 2.2 Block Diagram SLICOFI-2/-2S Figure 9 shows the internal block structure of all available SLICOFI-2x codec versions. The Enhanced Digital Signal Processor (EDSP) providing the add-on functions1) is only integrated in the SLICOFI-2 (PEB 3265) device. PEB 3265 / PEB 3264 CDCNA CDCPA Prefi VCM VCMS IO1A IO2A IO3A IO4A IO1B IO2B IO3B IO4B Channel A Supervision ILA ITA CDCNB CDCPB PEB 3265 only ADC HW-Fi DAC HW-Fi EDSP ITACA VCMITA IMa ACNA ACPA DCNA + Pofi DCPA C1A C2A COMPAND IOM-2 IOM-2 Interface HV Interf. Channel B Supervision ILB or CRAM PCM ITB ADC Prefi ITACB VCMITB + Pofi DCPB C1B C2B GNDD µC DSP DAC HW-Fi HV Interf. GNDA Figure 9 PCM / µC Interface CONTR IMa ACNB ACPB DCNB HW-Fi DBUS GNDR GNDPLL VDDA VDDD VDDR VDDPLL CREF RESET PCM/IOM-2 ezm22021 Block Diagram: SLICOFI-2/-2S (PEB 3265, PEB 3264) 1) The add-on functions are DTMF detection, Caller ID generation, Message Waiting lamp support, Three-party Conferencing, Universal Tone Detection (UTD), Line Echo Cancellation (LEC), and Sleep Mode. Preliminary Data Sheet 32 DS3, 2003-07-11 DuSLIC Functional Description 2.3 DC Feeding DC feeding with the DuSLIC is fully programmable as shown in Table 4 on Page 38. Figure 10 shows the signal paths for DC feeding between the SLIC and the SLICOFI-2x: Transmit path IL IT TIP RING CITACA ILA ITACA RIT1A R ILA SLIC R IT2A CVCMITA Channel A DCP DCN ACP ACN ITA VCMITA PCM out VCM DCPA DCNA ACPA ACNA (data upstream) SLICOFI-2x IL IT ILB ITACB R IT1B TIP SLIC RING C ITACB R ILB R IT2B CVCMITB ITB Transmit PCM or IOM-2 Interface PCM in (data downstream) Receive VCMITB Channel B DCP DCN ACP ACN VCM DCPB DCNB ACPB ACNB Receive path ezm140374 Figure 10 Signal Paths – DC Feeding Preliminary Data Sheet 33 DS3, 2003-07-11 DuSLIC Functional Description 2.3.1 DC Characteristic Feeding Zones The DuSLIC DC feeding characteristic has three different zones: the constant current zone, the resistive zone, and the constant voltage zone. A voltage reserve VRES (see Chapter 2.3.7) can be selected to avoid clipping the high level AC signals (such as TTX) and to take into account the voltage drop of the SLIC. The DC feeding characteristic is shown in Figure 11. ITIP/RING Constant current zone Resistive zone I0 Necessary voltage reserve VRES Constant voltage zone |VBAT| VTIP/RING ezm14017 Figure 11 DC Feeding Characteristic This simplified diagram shows the constant current zone as an ideal current source with an infinite internal resistance, while the constant voltage zone is shown as an ideal voltage source with an internal resistance of 0 Ω. For the specification of the internal resistances, see Chapter 2.3.5. Preliminary Data Sheet 34 DS3, 2003-07-11 DuSLIC Functional Description 2.3.2 Constant Current Zone In the off-hook state, the feed current must usually be kept at a constant value independent of load (see Figure 12). The SLIC senses the DC current and supplies this information to the SLICOFI-2x via the IT pin (input pin for DC control). The SLICOFI-2x compares the actual current with the programmed value and adjusts the SLIC drivers as necessary. ITIP/RING in the constant current zone is programmable from 0 to 32 mA or 0 to 50 mA depending on the particular SLIC version in use. ITIP/RING RLOAD RI I0 RK12 VRES |VBAT| VTIP/RING ezm14016 Figure 12 Constant Current Zone Depending on the load, the operating point is determined by the voltage VTIP/RING between the Tip and Ring pins. The operating point is calculated from: VTIP/RING = RLOAD × ITIP/RING where RLOAD = RPRE + RLINE + RPHONE,OFF-HOOK RPRE = RPROT + RSTAB. The lower the load resistance RLOAD, the lower the voltage between the Tip and Ring pins. A typical value for the programmable feeding resistance in the constant current zone is about RI = 10 kΩ (see Table 4). Preliminary Data Sheet 35 DS3, 2003-07-11 DuSLIC Functional Description 2.3.3 Resistive Zone The programmable resistive zone RK12 of the DuSLIC provides extra flexibility over a wide range of applications. The resistive zone is used for very long lines where the battery is incapable of feeding a constant current into the line. The operating point in this case crosses from the constant current zone for low and medium impedance loops to the resistive zone for high impedance loops (see Figure 13). The resistance of the zone RK12 is programmable from RV to 1000 Ω. ITIP/RING RI I0 RLOAD RK12 VRES |VBAT| VTIP/RING ezm14035 Figure 13 Resistive Zone Preliminary Data Sheet 36 DS3, 2003-07-11 DuSLIC Functional Description 2.3.4 Constant Voltage Zone The constant voltage zone (see Figure 14) is used in some applications to supply a constant voltage to the line. In this case, VTIP/RING = VLIM is constant and the current depends on the load between the Tip and Ring pin. VLIM is set by the DuSLICOS software. In the constant voltage zone, the external resistors RPRE = RPROT + RSTAB necessary for stability and protection define the resistance RV seen at the RING and TIP wires of the application. The programmable range of the parameters RI, I0, IK1, VK1, RK12 and VLIM is given in Table 4. ITIP/RING I0 RK12 VRES VLIM |VBAT| RLOAD VTIP/RING ezm14036 Figure 14 Constant Voltage Zone Preliminary Data Sheet 37 DS3, 2003-07-11 DuSLIC Functional Description 2.3.5 Programmable Voltage and Current Range: DC Characteristics The DC characteristics and all symbols are shown in Figure 15. ITIP/RING I0 IK1 RI 1 RK12 2 IK2 RV = RPRE = RPROT + RSTAB VK1 VK2 VLIM VTIP/RING ezm22009 Figure 15 DC Characteristics Table 4 DC Characteristics Symbol Programmable Range Condition RI I0 1.8 kΩ … 40 kΩ – 0 … 32 mA only for DuSLIC-S, DuSLIC-E, DuSLIC-P 0 … 50 mA only for DuSLIC-S2, DuSLIC-E2 0 … 32 mA only for DuSLIC-S, DuSLIC-E, DuSLIC-P 0 … 50 mA only for DuSLIC-S2, DuSLIC-E2 0 … 50 V – VK1 < VLIM – IK1 × RK12 VK1 < VLIM – IK1 × RV VK1 > VLIM – IK1 × RK12 RV … 1000 Ω only (VK1, IK1) 0 … 72 V – VLIM > VK1 + IK1 × RK12 only (VK1, IK1) IK1 VK1 RK12 VLIM Preliminary Data Sheet (VK1, IK1) and (VK2, IK2) – 38 DS3, 2003-07-11 DuSLIC Functional Description 2.3.6 SLIC Power Dissipation The major portion of the power dissipation in the SLIC can be estimated by the power dissipation in the output stages. The power dissipation can be calculated from: PSLIC ≈ (VBAT – VTIP/RING) × ITIP/RING ITIP/RING SLIC output stage power dissipation constant current zone I0 SLIC output stage power dissipation constant voltage zone |VBAT| VTIP/RING ezm14021 Figure 16 Power Dissipation For further information, see Chapter 3.7.2 on Page 91. Preliminary Data Sheet 39 DS3, 2003-07-11 DuSLIC Functional Description 2.3.7 Necessary Voltage Reserve To avoid clipping AC speech signals as well as AC metering pulses, a voltage reserve VRES (see Figure 11) must be provided. VRES = |VBAT| – VLIM (see Page 37) |VBAT| is the selected battery voltage, which can be either VBATH, VBATL, or |VHR – VBATH| for the SLIC-S/-S2/-E/-E2, depending on the mode. Similarly, it can be VBATH, VBATL, or VBATR for the SLIC-P, depending on the mode. VRES consists of: • • • Voltage reserve of the SLIC output buffers: this voltage drop depends on the output current through the Tip and Ring pins. For a standard output current of 25 mA, this voltage reserve is a few volts. Voltage reserve for AC speech signals: max. signal amplitude (example 2 V) Voltage reserve for AC metering pulses: The TTX signal amplitude VTTX depends on local specifications and varies from 0.1 Vrms to several Vrms at a load of 200 Ω. To obtain VTTX = 2 Vrms at a load of 200 Ω and RPRE = 50 Ω (RPRE = RPROT + RSTAB), 3 Vrms = 4.24 Vpeak are needed at the SLIC output. Therefore, a VRES value of 10.24 V must be selected (= 4 V (SLIC drop for peak current of DC and speech and TTX) + 2 V (AC speech signals) + 4.24 V (TTX-signal)). RPRE SLIC 200 Ω VTTX RPRE ezm14032 Figure 17 TTX Voltage Reserve Schematic Preliminary Data Sheet 40 DS3, 2003-07-11 DuSLIC Functional Description 2.3.8 Extended Battery Feeding If the battery voltage is not sufficient to supply the minimum required current through the line even in the resistive zone, the auxiliary positive battery voltage can be used to expand the voltage swing between Tip and Ring. With this extended supply voltage – VHR (DuSLIC-S/-S2/E/-E2) or VBATR (DuSLIC-P) – it is possible to supply the constant current for long lines. Figure 18 shows the DC feeding impedances RMAX,ACTH in ACTH mode and RMAX,ACTR in ACTR mode (for more information about the ACTH and ACTR modes, see Chapter 3.1). ITIP/RING ACTR Extended Battery Feeding Mode ACTH Normal Mode IK1 VK1 RMAX RMAX, ACTR RK12 RK12, ACTR VLIM |VBATH| VK1, ACTR VTIP/RING VLIM, ACTR |VHR – VBATH|1) |VBATR|2) 1) 2) DuSLIC-S/-S2/-E/-E2, DuSLIC-P ezm23019 Figure 18 DC Feeding Characteristics (ACTH, ACTR) The extended feeding characteristic is determined by the feeding characteristic in normal mode (ACTH) and an additional gain factor KB (DuSLICOS DC Control Parameter 1/4: Additional Gain in active Ring): VLIM,ACTR = VLIM × KB VK1,ACTR = VK1 × KB + RV × IK1 × (KB – 1) ≈ VK1 × KB RK12,ACTR = KB × (RK12 – RV) + RV ≈ RK12 × KB RI,ACTR = RI × KB/2 IK2,ACTR = IK2 × KB × (RK12 – RV)/(KB × RK12 – RV) VK2,ACTR = VLIM,ACTR – IK2,ACTR × RV Preliminary Data Sheet 41 DS3, 2003-07-11 DuSLIC Functional Description 2.4 AC Transmission Characteristics SLICOFI-2x uses either an IOM-2 or a PCM digital interface. In receive direction, SLICOFI-2x converts PCM data from the network and outputs a differential analog signal (ACP and ACN) to the SLIC that amplifies the signal and applies it to the subscriber line. In transmit direction, the transversal (IT) and longitudinal (IL) currents on the line are sensed by the SLIC and fed to the SLICOFI-2x. A capacitor separates the transversal line current into DC (IT) and AC (ITAC) components. Because ITAC is the sensed transversal (also called metallic) current on the line, it includes both the receive and transmit components. SLICOFI-2x separates the receive and transmit components digitally, via a transhybrid circuit. Figure 19 shows the signal paths for AC transmission between the SLICs and SLICOFI-2x: Transmit path IL IT TIP RING CITACA ILA ITACA R IT1A R ILA SLIC R IT2A CVCMITA Channel A DCP DCN ACP ACN ITA VCMITA PCM out VCM DCPA DCNA ACPA ACNA (data upstream) SLICOFI-2x IL IT ILB ITACB R IT1B TIP SLIC RING C ITACB R ILB R IT2B CVCMITB ITB Transmit PCM or IOM-2 Interface PCM in (data downstream) Receive VCMITB Channel B DCP DCN ACP ACN VCM DCPB DCNB ACPB ACNB Receive path ezm140373 Figure 19 Signal Paths – AC Transmission The signal flow within the SLICOFI-2x for one voice channel is shown in schematic circuitry of Figure 20. With the exception of a few analog filter functions, signal processing is performed digitally in the SLICOFI-2x codec. Preliminary Data Sheet 42 DS3, 2003-07-11 DuSLIC Functional Description SLICOFI-2x Transmit Channel B Channel A ITAC DTMF detection Prefilter TTX filter Amplify transmit A/D Impedance matching Impedance matching + Frequency response transmit CMP PCM out Transhybrid filter TG 1 TG 2 ACP + Postfilter D/A + Amplify receive Frequency response receive + EXP PCM in CID generation ACN Teletax generator Receive ezm14026 Figure 20 2.4.1 Signal Flow in Voice Channel (A) Transmit Path The current sense signal (ITAC) is converted to a voltage by an external resistor. This voltage is first filtered by an anti-aliasing filter (pre-filter) that stops producing noise in the voice band from signals near the A/D sampling frequency. A/D conversion is done by a 1-bit sigma-delta converter. The digital signal is down-sampled further and routed through programmable gain and filter stages. The coefficients for the filter and gain stages can be programmed to meet specific requirements. The processed digital signal goes through a compander (CMP) that converts the voice data into A-Law or µ-Law codes. A time slot assignment unit outputs the voice data to the programmed time slot. SLICOFI-2x can also operate in 16-bit linear mode for processing uncompressed voice data. In this case, two time slots are used for one voice channel. 2.4.2 Receive Path The digital input signal is received via the IOM-2 or PCM Interface. Expansion (EXP), PCM low-pass filtering, frequency response correction, and gain correction are performed by the DSP. The digital data stream is up-sampled and converted to a corresponding analog signal. After smoothing by post-filters in the SLICOFI-2x, the AC signal is fed to the SLIC, where it is superimposed on the DC signal. The DC signal has been processed in a separate DC path. A TTX signal, generated digitally within SLICOFI-2x can also be added. Preliminary Data Sheet 43 DS3, 2003-07-11 DuSLIC Functional Description 2.4.3 Matching The SLIC outputs the voice signal to the line (receive direction) and also senses the voice signal coming from the subscriber. The AC impedance of the SLIC and the load impedance need to be matched to maximize power transfer and minimize two-wire return loss. The two-wire return loss is a measure of the impedance matching between a transmission line and the AC termination of DuSLIC. Impedance matching is done digitally within the SLICOFI-2x by three integrated impedance matching feedback loops. The loops feed the transmit signal back to the receive signal simulating the programmed impedance through the SLIC. When calculating the feedback filter coefficients, the external resistors between the protection circuit and the SLIC (RPRE = RPROT + RSTAB, see Figure 92, Page 357) must be taken into account. The impedance can be programmed to any appropriate real and complex values shown in the Nyquist diagram Figure 21. This means that the device can be adapted to requirements anywhere in the world without requiring the hardware changes that are necessary with conventional linecard designs. Re ZL 0 200 400 600 800 1000 1200 1400 -200 Possible Values for Line Impedance Im ZL -400 -600 ezm22019 Figure 21 Nyquist Diagram Preliminary Data Sheet 44 DS3, 2003-07-11 DuSLIC Functional Description 2.5 Ringing Because of the 170 V technology used for the SLIC, a ringing voltage of up to 85 Vrms sinusoidal or up to 100 Vrms trapezoidal can be generated on-chip without the need for an external ringing generator (This is with 20 V offset. Higher ring amplitudes are possible if lower DC offset voltage is required.) The SLICOFI-2x generates a sinusoidal ringing signal that causes less noise and crosstalk in neighboring lines than a trapezoidal ringing signal. The ringing frequency is programmable from 3 Hz to 300 Hz. SLIC-E/-E2, SLIC-S/-S2 and SLIC-P support different ringing methods (see Chapter 2.5.3). 2.5.1 Ringer Load A typical ringer load can be thought of as a resistor in series with a capacitor. Ringer loads are usually described as a Ringer Equivalence Number (REN) value. REN is used to describe the on-hook impedance of the terminal equipment and is actually a dimensionless ratio that reflects a certain load. REN definitions vary from country to country. A commonly used REN is described in FCC Part 68 that defines a single REN as either 5 kΩ, 7 kΩ, or 8 kΩ of AC impedance at 20 Hz. The impedance of an n-multiple REN is equivalent to parallel connection of n single RENs. In this manual, all references to REN assume the 7 kΩ model. For example, a 1 REN and 5 REN load, typically used in the USA, would be: 6930 Ω 1386 Ω 8 µF 1 REN 40 µF 5 REN ezm14024 Figure 22 2.5.2 Typical Ringer Loads of 1 and 5 REN used in USA Ring Trip After the subscriber has gone off-hook, the ringing signal must be removed within a specified time, and power must start feeding to the subscriber's phone. There are two ring trip methods: DC Ring Trip Detection and AC Ring Trip Detection. DC Ring Trip Detection Most applications that utilize the DuSLIC chip set use DC ring trip detection. By applying a DC offset together with the ringing signal, a transversal DC loop current starts to flow when the subscriber goes off-hook. This DC current is sensed by the SLIC and in this way is used as an off-hook criterion. The SLIC supplies this information to the SLICOFI-2x at the IT pin. The SLICOFI-2x continuously integrates the sensed line Preliminary Data Sheet 45 DS3, 2003-07-11 DuSLIC Functional Description current ITRANS over one ringer period. This causes the integration result to represent the DC component of the ring current. If the DC current exceeds the programmed ring trip threshold, SLICOFI-2x generates an interrupt. Ring trip is reliably detected and reported within two ring signal periods. The ringing signal is switched off automatically at zero crossing by the SLICOFI-2x. The threshold for the ring trip DC current is set internally in the SLICOFI-2x and programmed via the digital interface. The DC offset for ring trip detection can be generated by the DuSLIC chip set and the internal ring trip function can be used even if an external ringing generator is used. AC Ring Trip Detection For short lines (< 1 kΩ loop length) and for low-power applications, the DC offset can be avoided to reduce the battery voltage for a given ring amplitude. Ring trip detection is done by rectifying the ring current ITRANS, integrating it over one ringer period and comparing it to a programmable AC ring trip threshold. If the ring current exceeds the programmed threshold, the HOOK bit in register INTREG1 is set accordingly. Most applications that utilize the DuSLIC chip set use the DC ring trip detection, which is more reliable than AC ring trip detection. 2.5.3 Ringing Methods There are two methods of ringing: • • Balanced ringing (bridged ringing) Unbalanced ringing (divided ringing) Internal balanced ringing generally offers more benefits compared to unbalanced ringing: • • Balanced ringing produces much less longitudinal voltage, which results in a lower amount of noise coupled into adjacent cable pairs (e.g. ADSL lines). By using a differential ringing signal, lower supply voltages become possible The phone itself cannot distinguish between balanced and unbalanced ringing. Where unbalanced ringing is still used, it is often simply an historical leftover. For a comparison between balanced and unbalanced ringing, see also ANSI document T1.401-1993. Additionally, integrated ringing with the DuSLIC offers the following advantages: • • • • • Internal ringing (no need for external ringing generator and relays) Reduction of board space because of much higher integration and fewer external components Programmable ringing amplitude, frequency, and ringing DC offset without hardware changes Programmable ring trip thresholds Switching of the ringing signal at zero-crossing. With relays there is always some residual switching noise, which can cause interference on adjacent cable pairs (e.g. ADSL). Preliminary Data Sheet 46 DS3, 2003-07-11 DuSLIC Functional Description 2.5.4 DuSLIC Ringing Options Application requirements differ with regard to ringing amplitudes, power requirements, loop length, and loads. The DuSLIC options include three different SLICs to ensure the most appropriate ringing methods (see Table 5) for these applications: Table 5 Ringing Options with SLIC-S, SLIC-E/-E2 and SLIC-P SLIC-S PEB 4264 SLIC-E/-E2 PEB 4265 PEB 4265-2 SLIC-P PEB 4266 45 Vrms 53 Vrms 85 Vrms 100 Vrms 85 Vrms 100 Vrms DC voltage for balanced ringing1) programmable typ. 0 … 50 V programmable typ. 0 … 50 V programmable typ. 0 … 50 V Internal unbalanced ringing max. voltage in Vrms sinusoidal trapezoidal NO NO NO NO 50 Vrms 58 Vrms DC voltage for unbalanced ringing NO NO VBATR/2 Required SLIC supply voltages for maximum ringing amplitude (typically) VDD = 5 V2), VDD = 3.3 V3) VBATH = –54 V, VHR = 36 V VDD = 5 V, VBATH = –70 V, VHR = 80 V VDD = 5 V or 3.3 Number of battery voltages for power saving 2 (VBATL & VBATH) 2 (VBATL & VBATH) 2 (when internal ringing is used) 3 (when external ringing is used) SLIC Version/ Ringing Facility, Battery Voltages Internal max. balanced ringing voltage in Vrms [with 20 VDC used for ring trip detection] sinusoidal trapezoidal V, VBATH = –48 V, VBATR = –150 V 1) In most applications, 20 VDC are sufficient for reliable ring trip detection. A higher DC voltage will reduce the achievable maximum ringing voltage. For short loops, 10 VDC may be sufficient. 2) 170 V technology 3) 90 V technology SLIC-S allows balanced ringing up to 45 Vrms and is dedicated to short loop or PBX applications. Preliminary Data Sheet 47 DS3, 2003-07-11 DuSLIC Functional Description For SLIC-S2, only external ringing is provided. SLIC-E/-E2 allows balanced ringing up to 85 Vrms and can, therefore, be used in systems with higher loop impedance. The low-power SLIC-P is optimized for power-critical applications (such as intelligent ISDN network termination). Internal ringing can be used up to 85 Vrms balanced or 50 Vrms unbalanced. For lowest power applications where external ringing is preferred, three different battery voltages (VBATR, VBATH, VBATL) can be used to optimize the power consumption of the application.1) SLIC-E/-E2 and SLIC-P differ in supply voltage configuration and the ring voltages at Tip and Ring VT and VR. External ringing is supported by both SLICs. Both internal and external ringing are activated by switching the DuSLIC to ringing mode by setting the CIDD/CIOP2) bits M2, M1, M0 to 101 (see “Overview of all DuSLIC Operating Modes” on Page 74). External Ringing Support by DuSLIC The following settings must be made: • • • • Enable the use of an external ring signal generator by setting bit REXT-EN in register BCR2 to 1. A TTL compatible zero crossing signal must be applied to the RSYNC pin of the SLICOFI-2x (see Figure 23). Activate the ringing mode by setting the CIDD/CIOP bits M2, M1, M0 to 101. Set the DuSLIC internal ring frequency to a value according a factor of approximately 0.75 of the external ring frequency. The ring relay is controlled by the IO1 pin (see Figure 92). Due to the high current drive capability of the IO1 output, no additional relay driver is necessary. The relay is switched either synchronously or asynchronously as follows: • Synchronous to the zero crossing of the external ringing frequency (bit ASYNCH-R in register XCR set to 0) A ring generator delay TRING,DELAY (see DuSLICOS control parameters 2/4) can be programmed to consider the ring relay delay TRING-RELAY,DELAY as shown in Figure 23. • Asynchronous (bit ASYNCH-R in register XCR set to 1) The ring relay is switched immediately with the ring command. 1) In this case, VBATR is typically used for the on-hook state, while VBATH and VBATL are used for optimized feeding of different loop lengths in the off-hook state. 2) CIDD = Data Downstream Command/Indication Channel Byte (IOM-2 interface) CIOP = Command/Indication Operation Preliminary Data Sheet 48 DS3, 2003-07-11 DuSLIC Functional Description E xte rn a l R in g in g V o lta g e t VRSYNC t V IO 1 T R IN G ,D E L A Y T R IN G -R E L A Y ,D E LA Y t V R IN G t duslic_0015_zero_crossing Figure 23 External Ringing Zero Crossing Synchronization Preliminary Data Sheet 49 DS3, 2003-07-11 DuSLIC Functional Description 2.5.5 Internal Balanced Ringing via SLICs SLIC-E/-E2 and SLIC-P support internal balanced ringing up to VRING,RMS = 85 Vrms, while SLIC-S supports balanced ringing up to VRING,RMS = 45 Vrms1). The ringing signal is generated digitally within the SLICOFI-2x. VDROP,T vT VHR BGND VBATH VBATR VRING,pp= VTp - VRp VTp VDC,RING VRp vR VDROP,R SLIC-E SLIC-E2 SLIC-P SLIC-S Figure 24 ezm140315 Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC-P In ringing mode, the DC feeding regulation loop is not active. A programmable DC ring offset voltage is applied to the line instead. During ring bursts, the ringing DC offset and the ringing signal are summed digitally within SLICOFI-2x in accordance with the programmed values. This signal is then converted to an analog signal and is applied to the SLIC. The SLIC amplifies the signal and supplies the line with ringing voltages up to 85 Vrms. In balanced ringing mode, the SLIC uses an additional supply voltage VHR for SLIC-E/-E2/-S and VBATR for SLIC-P. The total supply span is now VHR – VBATH for SLIC-E/-E2/-S and VBATR for SLIC-P. The maximum ringing voltage that can be achieved is: for SLIC-E/-E2/-S: for SLIC-P: where: VRING,RMS = (VHR – VBATH – VDROP,TR – VDC,RING)/1.41 VRING,RMS = (–VBATR – VDROP,TR – VDC,RING)/1.41 VDROP,TR = VDROP,T + VDROP,R 1) In this case VRING,RMS = VTR,RMS = VTR0,RMS because of the low impedance of the SLIC output (< 1 Ω). VTR,RMS is the open-circuit rms voltage measured directly at pins RING and TIP at the SLIC output with ringer load. VTR0,RMS is the rms voltage measured directly at pins RING and TIP at the SLIC output without any ringer load. For calculation of the ringing voltage at the ringer load, see the Application Note DuSLIC Voltage and Power Dissipation Calculation and its accompanying MS Excel Sheet for calculation. Preliminary Data Sheet 50 DS3, 2003-07-11 DuSLIC Functional Description Using the DuSLIC chip set, ringing voltages up to 85 Vrms sinusoidal can be applied, and trapezoidal ringing can be programmed as well. For a detailed application diagram of internal balanced ringing see Figure 90 on Page 353. 2.5.6 Internal Unbalanced Ringing with SLIC-P The internal unbalanced ringing supported by SLIC-P can be used for ringing voltages up to 50 Vrms. The SLICOFI-2 integrated ringing generator is used and the ringing signal is applied to either the Tip or Ring line. Ringing signal generation is the same as described above for balanced ringing. As only one line is used for ringing, technology limits the ringing amplitude to about half the value of balanced ringing, to a maximum of 50 Vrms. VDROP,R,BGND ≈ VDROP,T VDROP,T BGND VT VDC,RING VBATR / 2 VRING,p vR VDROP,R,VBATR Figure 25 vRING = vR VBATR ezm140316 Unbalanced Ringing Signal Figure 25 shows an example with the Ring line used for ringing and the Tip line fixed at –VDROP,T which is the drop in the output buffer of the Tip line of SLIC-P (typ. < 1 V). The ring line has a fixed DC voltage of VBATR/2 used for ring trip detection. The maximum ringing voltage is: VRING,RMS = (–VBATR – VDROP,R,VBATR – VDROP,T)/2.82 When the called subscriber goes off-hook, a DC path is established from the Ring to the Tip line. The DC current is recognized by the SLICOFI-2 because it monitors the IT pin. An interrupt indicates ring trip if the line current exceeds the programmed threshold. The same hardware can be used for integrated balanced or unbalanced ringing. The balanced and unbalanced modes are configured by software. The maximum achievable amplitudes depend on the values selected for VBATR. Preliminary Data Sheet 51 DS3, 2003-07-11 DuSLIC Functional Description In both balanced and unbalanced ringing modes, SLICOFI-2 automatically applies and removes the ringing signal during zero-crossing. This reduces noise and cross-talk to adjacent lines. 2.5.7 External Unbalanced Ringing SLICOFI-2x supports external (balanced or unbalanced) ringing for higher ringing voltage requirements with all SLIC versions. In this case, the integrated ring trip functionality of the DuSLIC may be used. For a detailed application diagram of unbalanced ringing, see Figure 92 (Page 357) and Figure 94 (Page 359). Because high voltages are involved, an external relay should be used to switch the RING line off and to switch the external ringing signal together with a DC voltage to the line. The DC voltage must be applied for the internal ring trip detection mechanism that operates for external ringing in the same way as for internal ringing. The SLICOFI-2x must be set to the external ringing mode by the REXT-EN bit in register BCR2. A synchronization signal of the external ringer is applied to the SLICOFI-2x via the RSYNC pin. The external relay is switched on or off synchronously to this signal via the IO1 pin of the SLICOFI-2x, according to the actual mode of the DuSLIC. An interrupt is generated if the DC current exceeds the programmed ring trip threshold. 2.6 Signaling (Supervision) Signaling in the subscriber loop is monitored internally by the DuSLIC chip set. Supervision is performed by sensing the longitudinal and transversal line currents on the Ring and Tip wires. The scaled values of these currents are generated in the SLIC and are fed to the SLICOFI-2x via the IT and IL pins. Transversal line current: ITRANS = (IR + IT)/2 Longitudinal line current: ILONG = (IR – IT)/2 where IR, IT are the loop currents on the Ring and Tip wires. Off-hook Detection Loop start signaling is the most common type of signaling. The subscriber loop is closed by the hook switch inside the subscriber equipment. • In Active mode, the resulting transversal loop current is sensed by the internal current sensor in the SLIC. The IT pin of the SLIC indicates the subscriber loop current to the SLICOFI-2x. External resistors (RIT1, RIT2, see Figure 90 on Page 353) convert the current information to a voltage on the ITA (or ITB) pin. The analog information is first converted to a digital value. It is then filtered and processed further which effectively suppresses line disturbances. If the result exceeds a programmable threshold, an interrupt is generated to indicate off-hook detection. Preliminary Data Sheet 52 DS3, 2003-07-11 DuSLIC Functional Description • In Sleep/Power Down mode (PDRx), a similar mechanism is used. In this mode, the internal current sensor of the SLIC is switched off to minimize power consumption. The loop current is therefore fed and sensed through 5 kΩ resistors integrated within the SLIC. The information is made available on the IT pin and is interpreted by the SLICOFI-2x. – In Sleep mode, the analog information is fed to an analog comparator integrated within the SLICOFI-2x that directly indicates off-hook. – In Power Down mode, the SLICOFI-2x converts the analog information to a digital value. It is then filtered and processed further to effectively suppress line disturbances. If the result exceeds a programmable threshold, an interrupt is generated to indicate off-hook detection. In applications using ground start signaling, DuSLIC can be set to the ground start mode. In this mode, the Tip wire is switched to high impedance mode. Ring ground detection is performed by the internal current sensor in the SLIC and is transferred to the SLICOFI-2x via the IT pin. Ground Key Detection The scaled longitudinal current information is transferred from the SLIC via the IL pin and the external resistor RIL to SLICOFI-2x. This voltage is compared with a fixed threshold value. For the specified RIL (1.6 kΩ, see application circuit Figure 90, Page 353) this threshold corresponds to 17 mA (positive and negative). After further post-processing, this information generates an interrupt (GNDK bit in the INTREG1 register) and ground key detection is indicated. The polarity of the longitudinal current is indicated by the GNKP bit in the INTREG1 register. Each change of the GNKP bit generates an interrupt. Both bits (GNDK, GNKP) can be masked in the MASK register. The post-processing is performed to guarantee ground key detection, even if longitudinal AC currents with frequencies of 162/3, 50 or 60 Hz are superimposed. The time delay between triggering the ground key function and registering the ground key interrupt will be less than 40 ms in most cases (f = 50 Hz, 60 Hz). For longitudinal DC signals, the blocking period can be programmed by the Data Upstream Persistence Counter end value (DUP) in register IOCTL3. DC signals with less duration will not be detected. The DUP time is equivalent to the half of the cycle time for the lowest frequency for AC suppression (for values see register IOCTL3 on Page 166). In Power Down mode, the SLIC’s internal current sensors are switched off and ground key detection is disabled. Preliminary Data Sheet 53 DS3, 2003-07-11 DuSLIC Functional Description 2.7 Metering One of two different metering methods may be specified: • • Metering by sinusoidal bursts of either 12 kHz or 16 kHz Polarity reversal of Tip and Ring. 2.7.1 Metering by 12/16 kHz Sinusoidal Bursts To satisfy worldwide application requirements, SLICOFI-2/-2S offers integrated metering injection of either 12 or 16 kHz signals with programmable amplitudes. SLICOFI-2/-2S also has an integrated adaptive TTX notch filter and can switch the TTX signal to the line in a smooth way. When switching the signal to the line, the switching noise is less than 1 mV. Figure 26 shows TTX bursts at certain points of the signal flow within SLICOFI-2/2S. ZL/2 y + Transmit Path A/D - D/A SLIC-E/-E2 SLIC-S SLIC-P ε TTX Adaptive Filter x1 ZL/2 D/A + TTX Gen. IM Filter + Receive Path SLICOFI-2/-2S ezm14027 Figure 26 Teletax Injection and Metering The integrated, adaptive TTX notch filter guarantees an attenuation of > 40 dB. No external components for filtering TTX bursts are required. Preliminary Data Sheet 54 DS3, 2003-07-11 DuSLIC Functional Description 2.7.2 Metering by Polarity Reversal SLICOFI-2/-2S also supports metering by polarity reversal by changing the actual polarity of the voltages on the TIP/RING lines. Polarity reversal is activated by switching the REVPOL bit in register BCR1 to one or by switching to the “Active with Metering” mode by the CIDD or CIOP command (see “Overview of all DuSLIC Operating Modes” on Page 74). 2.7.2.1 Soft Reversal Some applications require a smooth polarity reversal (soft reversal), as shown in Figure 27. Soft reversal helps prevent negative effects such as non-required ringing. Soft reversal is deactivated by the SOFT-DIS bit in register BCR2. SOFT-DIS = 1 Immediate reversal is performed (hard reversal) SOFT-DIS = 0 Soft reversal is performed. Transition time (time from START to SR-END1, see Figure 27) is programmable by CRAM coefficients; default value is 80 ms. VTIP/RING [V] 25 START 20 15 10 5 ∆U 0 -5 -10 SR-END1 -15 SR-END2 = 1/16*SR-END1 ∆U/8 -20 -25 0 Figure 27 50 100 150 200 250 t [ms] ezm14038 Soft Reversal (Example for Open Loop) START: The soft ramp starts by setting the REVPOL bit in register BCR1 to 1. The DC characteristic is switched off. SR-END1: At the soft reversal end one point, the DC characteristic is switched on again. Programmable by the DuSLICOS software, such as ∆U/8. SR-END2: At the soft reversal end two point, the soft ramp is switched off. Programmable by the DuSLICOS software, such as 1/16 × SR-END1. From START to SR-END2 the READY bit in register INTREG2 is set to 0 (see register description in Chapter 5.3.1.2 for further information). Preliminary Data Sheet 55 DS3, 2003-07-11 DuSLIC Functional Description 2.8 DuSLIC Enhanced Signal Processing Capabilities The signal processing capabilities described in this section are implemented by an Enhanced Digital Signal Processor (EDSP), with the exception of DTMF generation. Each function can be individually enabled or disabled for each DuSLIC channel. Therefore, power consumption can be reduced according to the needs of the application. For the MIPS requirements of the different EDSP algorithms see Chapter 2.8.6. Figure 28 shows the AC signal path for DuSLIC with the ADCs and DACs, impedance matching loop, trans-hybrid filter, gain stages, and the connection to the EDSP. VIN + AX2 HPX2 ADC IM1 LPX FRX AX1 HPX1 CMP IM2 XOUT UTD ε DAC TTXA IM3 Switch LEC TH DTMF ε TTXG UTD CID EDSP VOUT + + DAC AR2 HPR2 + LPR FRR AR1 HPR1 + EXP RIN TG DuSLIC_0005_ACsignal_path Figure 28 DuSLIC AC Signal Path Figure 29 shows a close-up on the EDSP signal path shown in Figure 28 identifying signal names and SOP commands. Sx LPX FRX AX1 HPX1 L E C -O U T CMP XOUT LE C-E N UTDX -E N U TD X-S UM U TD X -S RC S L E C ,T IN G TH G L E C -X I UTDX S L E C ,T O U T G LEC S L E C ,R G D TM F-SR C LEC -EN G L E C -X 0 G L E C -R I DTM F-EN G DTMF G D TM F + UTDR -E N SSUM U TD R -S UM UTDR CID LPR FRR AR1 EXP + TG Figure 29 SR R IN Switch position shown for control bit set to 0 DuSLIC_0006_EDSPsignal_path DuSLIC EDSP Signal Path Preliminary Data Sheet 56 DS3, 2003-07-11 DuSLIC Functional Description The enhanced Signal Processing capabilities are available only for the DuSLIC-E/-E2/-P versions, with an exception of DTMF generation. The DTMF generation is available for all DuSLIC versions. The functions of the EDSP are configured and controlled by POP register settings (see Chapter 5.2.3). 2.8.1 DTMF Generation and Detection Dual Tone Multi-Frequency (DTMF) is a signaling scheme using voice frequency tones to signal dialing information. A DTMF signal is the sum of two tones, one from a low group (697–941 Hz) and one from a high group (1209–1633 Hz), with each group containing four individual tones. This scheme allows sixteen unique combinations. Ten of these codes represent the numbers from zero through nine on the telephone keypad, the remaining six codes (*, #, A, B, C, D) are reserved for special signaling. The buttons are arranged in a matrix, with the rows determining the low group tones, and the columns determining the high group tone for each button. In all SLICOFI-2x codec versions, the sixteen standard DTMF tone pairs can be generated independently in each channel via two integrated tone generators. Alternatively, the frequency and amplitude of the tone generators can be programmed individually via the digital interface. Each tone generator can be switched on and off. The generated DTMF tone signals meet the frequency variation tolerances specified in the ITU-T Q.23 recommendation. Both Channels A and B of SLICOFI-21) have a powerful built-in DTMF decoder that will meet most national requirements. The receiver algorithm performance meets the quality criteria for central office/exchange applications. It complies with the requirements of ITU-T Q.24, Bellcore GR-30-CORE (TR-NWT-000506), and Deutsche Telekom network (BAPT 223 ZV 5, Approval Specification of the Federal Office for Post and Telecommunications, Germany), among others. Note: DTMF Detection is only available for DuSLIC-E/-E2/-P The performance of the algorithm can be adapted according to the needs of the application via the digital interface (detection level, twist, bandwidth, and center frequency of the notch filter). Preliminary Data Sheet 57 DS3, 2003-07-11 DuSLIC Functional Description Table 6 shows the performance characteristics of the DTMF decoder algorithm: Table 6 Performance Characteristics of the DTMF Decoder Algorithm No. Characteristic Value Notes 1 Valid input signal detection level –48 to 0 dBm0 Programmable 2 Input signal rejection level –5 dB of valid signal detection level – 3 Positive twist accept < 8 dB Programmable 4 Negative twist accept < 8 dB Programmable 5 Frequency deviation accept < ±(1.5% + 4 Hz) and < Related to center ±1.8% frequency 6 Frequency deviation reject > ±3% Related to center frequency 7 DTMF noise tolerance (could be the same as 14) –12 dB dB referenced to lowest amplitude tone 8 Minimum tone accept duration 40 ms – 9 Maximum tone reject duration 25 ms – 10 Signaling velocity ≥ 93 ms/digit – 11 Minimum inter-digit pause duration 40 ms – 12 Maximum tone drop-out duration 20 ms – 13 Interference rejection 30 Hz to 480 Hz for valid DTMF recognition dB referenced to Level in frequency range 30 Hz … 480 Hz ≤ lowest amplitude tone level of DTMF frequency +22 dB 14 Gaussian noise influence Signal level –22 dBm0, SNR = 23 dB Error rate better than 1 in 10000 – 15 Pulse noise influence Impulse noise tape 201 according to Bellcore TR-TSY-000762 Error rate better than 14 in 10000 measured with DTMF level –22 dBm0 Impulse Noise –10 dBm0 and –12 dBm0 Preliminary Data Sheet 58 DS3, 2003-07-11 DuSLIC Functional Description In the event of pauses < 20 ms: • • If the pause is followed by a tone pair with the same frequencies as before, this is interpreted as drop-out. If the pause is followed by a tone pair with different frequencies and if all other conditions are valid, this is interpreted as two different numbers. DTMF decoders can be switched on or off individually to reduce power consumption. In normal operation, the decoder monitors the Tip and Ring wires via the ITAC pins (transmit path). Alternatively, the decoder can also be switched in the receive path. On detection of a valid DTMF tone pair, SLICOFI-2 generates an interrupt via the appropriate INT pin and indicates a change of status. The DTMF code information is provided by a register that is read via the digital interface. The DTMF decoder also has excellent speech-rejection capabilities and complies with Bellcore TR-TSY-000763. The algorithm has been fully tested with the speech sample sequences in the Series-1 Digit Simulation Test Tapes for DTMF decoders from Bellcore. The characteristics of DTMF detection can be controlled by POP registers 30h to 39H. 2.8.2 Caller ID Generation in DuSLIC-E/-E2/-P A generator to send calling line identification (Caller ID, CID) is integrated in the DuSLIC-E/-E2/-P chip set. Caller ID is a generic name for the service provided by telephone utilities that supply information such as the telephone number or the name of the calling party to the called subscriber at the start of a call. In call waiting, the Caller ID service supplies information about a second incoming caller to a subscriber already busy with a phone call. In typical Caller ID systems, the coded calling number information is sent from the central exchange to the called phone. This information can be shown on a display on the subscriber telephone set. In this case, the Caller ID information is usually displayed before the subscriber decides to answer the incoming call. If the line is connected to a computer, caller information can be used to search in databases and additional services can be offered. There are two methods used for sending CID information depending on the application and country-specific requirements: • • Caller ID generation using DTMF signaling (see Chapter 2.8.1) Caller ID generation using FSK DuSLIC-E/-E2/-P contains DTMF generation units and FSK generation units that can be used for both channels simultaneously. The characteristics of the Caller ID generation circuitry can be controlled by POP registers 00H, 43H to 4AH. Preliminary Data Sheet 59 DS3, 2003-07-11 DuSLIC Functional Description DuSLIC-E/-E2/-P FSK Generation Different countries use different standards to send Caller ID information. The DuSLIC-E/-E2/-P chip set is compatible with the widely used Bellcore GR-30CORE, British Telecom (BT) SIN227, SIN242, and the UK Cable Communications Association (CCA) specification TW/P&E/312 standards. Continuous phase binary Frequency Shift Keying (FSK) modulation is used for coding that is compatible with BELL 202 (see Table 7) and ITU-T V.23, the most common standards. The SLICOFI-2 can be easily adapted to these requirements by programming via the microcontroller interface. Coefficient sets are provided for the most common standards. Table 7 FSK Modulation Characteristics Characteristic ITU-T V.23 Bell 202 Mark (Logic 1) 1300 ± 3 Hz 1200 ± 3 Hz Space (Logic 0) 2100 ± 3 Hz 2200 ± 3 Hz Modulation FSK Transmission rate 1200 ± 6 baud Data format Serial binary asynchronous The Caller ID data of the calling party can be transferred via the microcontroller interface into a SLICOFI-2 buffer register. The SLICOFI-2 will start sending the FSK signal when the CIS-EN bit is set and the CID-data buffer is filled up to CIS-BRS plus 1 byte. The data transfer into the buffer register is handled by a SLICOFI-2 interrupt signal. Caller data is transferred from the buffer via the interface pins to the SLIC-E/-E2/-P and is fed to the Tip and Ring wires. The Caller ID data bytes from the CID-data buffer are sent with the Least Significant Bit (LSB) first. DuSLIC-E/-E2/-P offers two different levels of framing: • A basic low-level framing mode All the data necessary to implement the FSK data stream—including channel seizure, mark sequence, and framing for the data packet or checksum—must be configured by firmware. SLICOFI-2 transmits the data stream in the same order in which the data is written to the buffer register. • A high-level framing mode The number of channel seizure and mark bits can be programmed and are automatically sent by the DuSLIC-E/-E2/-P. Only the data packet information must be written into the CID buffer. Start and stop bits are automatically inserted by the SLICOFI-2. The example below shows the signaling of a CID on-hook data transmission in accordance with Bellcore specifications. The Caller ID information applied on Tip and Ring is sent during the period between the first and second ring burst. Preliminary Data Sheet 60 DS3, 2003-07-11 DuSLIC Functional Description Bellcore On-hook Caller ID Physical Layer Transmission First Ring Burst A B Channel Seizure Mark Data Packet C D E Second Ring Burst F G Parameter Message Parameter Header Parameter Body Message Type Message Length1 Parameter Type Parameter Length Message Header Parameter Byte More Parameter Bytes More Parameter Messages Checksum Message Body Message 1 Message length equals the number of bytes to follow in the message body, excluding the checksum. A: 0.2 - 3 second ring burst B: 0.5 - 1.5 seconds between first ring burst and start of data transmission C: 300 alternating mark and space bits D: 180 mark bits C + D + E = 2.9 to 3.7 seconds F: ≥200ms G: 1.8 - 3 second ring burst ezm14014 Figure 30 Bellcore On-Hook Caller ID Physical Layer Transmission Note: As a CID transmission is an on-hook transmission the DuSLIC has to be programmed to Actice Mode. 2.8.2.1 Caller ID Buffer Handling of SLICOFI-2 This section describes the handling of the Caller ID buffer and the corresponding handshake bits in the interrupt registers. Programming Sequence In order to send Caller ID information over the telephone line, the following sequence should be programmed between the first and the second ring burst. The initialization part of the coefficients in the POP registers 43h to 4Ah must be done prior to that sequence. 1. 2. 3. 4. Enable the extended feature DSP in register XCR (EDSP-EN = 1) Enable the Caller ID sender feature in register BCR5 (CIS-EN = 1) Wait for an interrupt. Read out all 4 interrupt registers to serve the interrupt and check the CIS-REQ bit. Preliminary Data Sheet 61 DS3, 2003-07-11 DuSLIC Functional Description 5. If this bit is set, write at least BRS + 2 bytes (see POP register CIS-BRS) of Caller ID data but not more than 48 bytes to the Caller ID sender buffer register CIS-DAT. 6. Wait for the next interrupt and check again the CIS-REQ bit. 7. If this bit is set, send the next data to the Caller ID-data buffer but not more than (48 – BRS) bytes. CIS-REQ bit gets reset to 0, if the data buffer is filled again above the Caller ID sender buffer request size (BRS). 8. Repeat steps 6 and 7 as long as there is data to be sent. 9. Immediately after sending the last Caller ID data bit to the Caller ID sender buffer, set the bit CIS-AUTO to 1 and subsequently, after a time delay of at least 500 µs, the bit CIS-EN to 0. After processing the last bit, the Caller ID sender will stop automatically and reset the CIS-ACT bit in register INTREG4 to 0. No more CIS interrupts will be generated until the Caller ID sender is enabled again (interrupt bits: CIS-BOF, CISBUF and CIS-REQ). The end of the CID transmission can also be controlled by not setting CIS-AUTO and leaving CIS-EN at 1. If the Caller ID buffer becomes empty, an interrupt is generated to indicate buffer underflow (CIS-BUF). If CIS-BUF is set, reset CIS-EN to 0 with at least 1 ms delay, in order to allow to send the last bit of Caller ID data. In case of errors in the handling of the CID data buffer, CIS-BUF (buffer underflow) and CIS-BOF (buffer overflow) indicate these errors. CID transmission should be stopped in any of these cases as unpredictable results may occur. Note: CID data will be sent out with the LSB first If CIS-FRM is set to 1: seizure and mark bits are generated automatically (according to the settings of CIS-SEIZ-H/L and CIS-MARK-H/L) as well as start and stop bits for every byte. Preliminary Data Sheet 62 DS3, 2003-07-11 DuSLIC Functional Description 2.8.3 Line Echo Cancellation in DuSLIC-E/-E2/-P The DuSLIC-E/-E2/-P contains an adaptive Line Echo Cancellation (LEC) unit for the cancellation of near end echoes. With the adaptive balancing of the LEC unit, the Transhybrid Loss can be improved up to a value of approximately 50 dB. The maximum echo cancellation time selectable is 8 ms. The line echo cancellation unit is especially useful in combination with the DTMF detection unit. In critical situations the performance of the DTMF detection can be improved. If a line echo cancellation length (LEC Length) of 8 ms is used, please take care about the MIPS requirements described in Chapter 2.8.6. The DuSLIC-E/-E2/-P line echo canceller is compatible with applicable ITU-T G.165 and G.168 standards. An echo cancellation delay time of up to 8 ms can be programmed. The LEC unit basically consists of an Finite Impulse Response (FIR) filter, a shadow FIR filter, and a coefficient adaptation mechanism between these two filters as shown in Figure 31. SLEC, TIN ∑ SLEC, TOUT Adapt Coeff. Shadow FIR Filter Copy Coeff. FIR Filter SLEC,R DuSLIC_0004_LECunit Figure 31 Line Echo Cancellation Unit Block Diagram The adaptation process is controlled by the three parameters PowLECR (Power Detection Level Receive), DeltaPLEC (Delta Power) and DeltaQ (Delta Quality) (“POP Command” on Page 207). Adaptation takes place only if both of the following conditions hold: 1. SLEC,R > PowLECR 2. SLEC,R – SLEC,TIN > DeltaPLEC With the first condition, adaptation to small signals can be avoided. The second condition avoids adaptation during double talk. The parameter DeltaPLEC represents the echo loss Preliminary Data Sheet 63 DS3, 2003-07-11 DuSLIC Functional Description provided by external circuitry. If the adaptation of the shadow filter is performed better than the adaptation of the actual filter by a value of more than DeltaQ, then the shadow filter coefficients will be copied to the actual filter. At the start of an adaptation process, the coefficients of the LEC unit can be reset to default initial values or can be set to the old coefficient values. The coefficients may also be frozen. 2.8.4 Non Linear Processor (NLP) in DuSLIC-E/-E2/-P In SLICOFI-2 Version 1.5 a Non Linear Processor (NLP) in addition or as an option to the existing Line Echo Canceller (LEC) is implemented. Please note that the NLP is not available with SLICOFI-2 Version 1.5. The principle of the NLP is based on a limitation of the input signal. This means, that all samples which are below a limit (in the case of a negative sample above the negative limit), can pass the NLP without any modification. All samples which are above the limit (in the case of a negative sample below the negative limit), will be set to this limit (or negative limit). The value for the limit is the estimated background noise. The advantage of the limitation is, that the background noise can pass the NLP unchanged. Therefore the far end talker can not hear the NLP. The decision when the NLP should be activated, is based on the estimated residual echo after the LEC. If the signal after the LEC is higher than the estimated residual echo, the NLP is bypassed. When both the transmit and receive speech detectors are detecting speech (double talk), the NLP is also bypassed. An overhang counter ensures, that the end of the speech signal can pass the NLP unchanged. If end of speech is detected, the overhang counter starts counting from a predefined start value down to zero. This time ensures that silent parts at the end of the speech are not ignored. Important coefficients: – – – – BN-LEV-X, BN-LEV-R, BN-MAX and BN-ADJ for the background noise estimation RE-EST-ERLL for the NLP behavior in the simple mode SD-LEV-R, SD-LEV-X and SD-LEV-RE for the speech detection CT-LEV-RE for early double talk and near end speech detection For all other coefficients the default values (see Table 5.2.3.4) should be chosen. LEC and NLP implementation The NLP is integrated in the LEC unit. That means when the LEC and NLP are active, the output signal of the LEC is influenced by the NLP. If the DTMF receiver and/or the Universal Tone Detection (UTD) unit are active, the input signal for both is the LEC and the NLP output signal1). Usually this is no problem, as the 1) For the UTD this is only valid when the sum signal of receive and transmit is fed to the UTD (see Figure 29). Preliminary Data Sheet 64 DS3, 2003-07-11 DuSLIC Functional Description NLP bypasses local DTMF signals, but it would be a good strategy to only enable the NLP after the call has been completely established (far end talker connected). 2.8.5 Universal Tone Detection in DuSLIC-E/-E2/-P Each channel of the DuSLIC-E/-E2/-P has two Universal Tone Detection (UTD) units that can be used to detect special tones in the receive and transmit paths, especially fax or modem tones (for example, see the modem startup sequence described in the ITU-T V.8 recommendation). This allows the use of modem-optimized filter for V.34 and V.90 connections. If the DuSLIC-E/-E2/-P UTD detects that a modem connection is about to be established, the optimized filter coefficients for the modem connection can be downloaded before the modem connection is set up. With this mechanism implemented in the DuSLIC-E/-E2/-P chip set, the optimum modem transmission rate can always be achieved. Figure 32 shows the functional block diagram of the UTD unit: P rogram m able B and-pass Lim it |x| + LP E valuation Logic S UTD |x| + Lim it Figure 32 LP E Z M 14061 UTD Functional Block Diagram Initially, the input signal is filtered by a programmable band-pass filter (center frequency fC and bandwidth fBW). Both the in-band signal (upper path) and the out-of-band signal (lower path) are determined, and the absolute value is calculated. Both signals are furthermore filtered by a limiter and a low-pass filter. All signal samples (absolute values) below a programmable limit LevN (noise level) are set to zero and all other signal samples are diminished by LevN. The purpose of this limiter is to increase noise robustness. After the limiter stages, both signals are filtered by a fixed low-pass filter. The evaluation logic block determines whether a tone interval or silence interval is detected and whether an interrupt is generated for the receive or transmit path. Preliminary Data Sheet 65 DS3, 2003-07-11 DuSLIC Functional Description The UTDR-OK or UTDX-OK bit (register INTREG3 on Page 155) will be set if both of the following conditions hold for a time span of at least RTime1) without breaks longer than RBRKTime: 1. The in-band signal exceeds a programmable level LevS. 2. The difference of the in-band and the out-of-band signal levels exceeds DeltaUTD. The UTDR-OK or UTDX-OK bit will be reset if at least one of these conditions is violated for a time span of at least ETime during which the violation continues for at least EBRKTime. ETime and EBRKTime help reduce the effects of sporadic dropouts. If the bandwidth parameter is programmed to a negative value, the UTD unit can be used for the detection of silence intervals in the entire frequency range. The DuSLIC-E/-E2/-P UTD unit is compatible with the ITU-T G.164 recommendation. The UTD is resistant to a modulation with 15 Hz sinusoidal signals and a phase reversal, but is not able to detect the 15 Hz modulation and the phase reversal. 2.8.6 MIPS Requirements for EDSP Capabilities Table 8 shows the MIPS requirements for each algorithm using the EDSP: Table 8 MIPS Requirements Algorithm Used MIPS Conditions Caller ID Sender (CIS) 1.736*nCIS nCIS = 0...2 Universal Tone Detection (UTD) 1.208*nUTD nUTD = 0...4, transmit and receive for two channels DTMF Receiver 6.296*nDTMF nDTMF = 0...2 Line Echo Canceller (LEC) (3.536 + 0.032*LEN)*nLEC nLEC = 0...2 (for LEN see register LEC-LEN on Page 229) Non Linear Processor (NLP)1) 2.448*nNLP nNLP = 0...2 Operating System 1.432 – 1) SLICOFI-2 Version 1.5 only Attention: The maximum capability of the EDSP is 32 MIPS. The user has to make sure that the sum of all enabled algorithms does not exceed 32 MIPS in any case! 1) for RTime, RBRKTime, ETime and EBRKTime see Chapter 5.2.3.3. Preliminary Data Sheet 66 DS3, 2003-07-11 DuSLIC Functional Description Example: • • • All algorithms for all channels enabled and LEC Length = 8 ms (LEN = 64): →33.32 MIPS total computing load exceeding the 32 MIPS limit! All algorithms for all channels enabled and LEC Length = 4 ms (LEN = 32): →31.272 MIPS total computing load within the 32 MIPS limit. 4 x UTD, 2 x DTMF Receiver and 2 x LEC (8 ms) enabled: →29.85 MIPS total computing load within the 32 MIPS limit. Example for SLICOFI-2 Version 1.5 (with NLP): • • All algorithms for all channels enabled and LEC Length = 4 ms (LEN = 32): →36.344 MIPS total computing load exceeding the 32 MIPS limit! 2 x DTMF Receiver, 2 x LEC (8 ms) and 2 x NLP enabled: →30.1 MIPS total computing load within the 32 MIPS limit. 2.9 Message Waiting Indication in DuSLIC-E/-E2/-P Message Waiting Indication (MWI) is usually performed using a glow lamp at the subscriber phone. Current does not flow through a glow lamp until the voltage reaches a threshold value above approximately 80 V. At this threshold, the neon gas in the lamp will start to glow. When the voltage is reduced, the current falls under a certain threshold and the lamp glow is extinguished. DuSLIC has high-voltage SLIC technology (170 V) that is able to activate the glow lamp without any external components. The hardware circuitry is shown in Figure 33. The figure shows a typical telephone circuit with the hook switch in the on-hook mode, together with the impedances for the on-hook (ZR) and off-hook (ZL) modes. RMW ZL ZR MW Lamp ZL ZR RMW AC Impedance Ringer Impedance Pre Resistor Message Waiting ezm14066 Figure 33 MWI Circuitry with Glow Lamp Preliminary Data Sheet 67 DS3, 2003-07-11 DuSLIC Functional Description The glow lamp circuit also requires a resistor (RMW) and a lamp (MW Lamp) built into the phone. When activated, the lamp must be able to either blink or remain on constantly. In non-DuSLIC-E/-E2/-P solutions, the telephone ringer may respond briefly if the signal slope is too steep; behavior that is not desirable. The integrated ramp generator of the DuSLIC-E/-E2/-P can be programmed to increase the voltage slowly, to ensure that the lamp is activated and not the ringer. To activate the Message Waiting function of DuSLIC-E/-E2/-P, the following steps should be performed: 1. 2. 3. 4. Activating Ring Pause mode by setting the M0-M2 bits Select Ring Offset RO2 by setting the bits in register LMCR3 Enable the ramp generator by setting bit RAMP-EN in register LMCR2 Switch between the Ring Offsets RO3 and RO2 in register LMCR3 to flash the lamp on and off (see Figure 34). The values for RO2 and RO3 must first be programmed in the CRAM to the appropriate values so that the lamp will flash on and off. VTR VHIGH RO 3 Lamp On Lamp Off VLOW RO 2 Power Down State Ring Pause State t RNG-OFFSET Bits 11 t 10 ezm14067 Figure 34 2.10 Timing Diagram Three-party Conferencing in DuSLIC-E/-E2/-P Each DuSLIC-E/-E2/-P channel has a three-party conferencing facility implemented which consist of four PCM registers, adders and gain stages in the microprogram and the corresponding control registers (see Figure 35). Cascading DuSLIC-E/-E2/-P channels allows Multi-party Conferencing as well. Preliminary Data Sheet 68 DS3, 2003-07-11 DuSLIC Functional Description This facility is available in PCM/µC mode only. The PCM control registers PCMR1 through PCMR4 and PCMX1 through PCMX4 control the time slot assignment and PCM highway selection, while the bits PCMX-EN, CONF-EN, and CONFX-EN in the BCR3 register control the behavior of the conferencing facility and the PCM line drivers (see Figure 35). A programmable gain stage G is able to adjust the gain of the conferencing voice data (B, C, D, S) in a range from –6 dB to +3 dB to prevent an overload of the sum signals. PCM Highways Subscribers PCM channel X4 X1 X3 D R4 X2 B R2 C R3 A R1 X2 = (R3 – R4)*G X3 = (R2 – R4)*G X4 = (R2 – R3)*G G + G - + - + G 1 CONF_EN = 0 1 0 0 CONF_EN = 0 Subscriber S ezm14069 Figure 35 Conference Block for One DuSLIC Channel Note: G … Gain Stage (Gain Factor) set in CRAM coefficients, X1 - X4 … PCM transmit channels, R1 - R4 … PCM receive channels, A, B, C, D, S … examples for voice data on PCM channels X1–X4, R1–R4. 2.10.1 Conferencing Modes Table 9 Conferencing Modes: Receive Channels Configuration Registers Receive Channels Subscr. Mode PCMXEN CONFEN CONFX- R1 EN R2 R3 R4 S PCM Off 0 0 0 – – – – off PCM Active 1 0 0 A – – – A Preliminary Data Sheet 69 DS3, 2003-07-11 DuSLIC Functional Description Table 9 Conferencing Modes: Receive Channels (cont’d) Configuration Registers Receive Channels Subscr. Mode PCMXEN CONFEN CONFX- R1 EN R2 R3 R4 S External Conference 0 0 1 – B C D off 1 External Conference + PCM Active 0 1 A B C D A Internal Conference 1 0 – B C – G(B+C) Table 10 0 Conferencing Modes: Transmit Channels Configuration Registers Transmit Channels Subscr. Mode PCMXEN CONFEN CONFX- X1 EN X2 X3 X4 S PCM Off 0 0 0 off off off off off PCM Active 1 0 0 S off off off A External Conference 0 0 1 off G(C+D) G(B+D) G(B+C) off 1 External Conference + PCM Active 0 1 S G(C+D) G(B+D) G(B+C) A Internal Conference 1 0 off G(C+S) G(B+S) off 0 G(B+C) (see also “Control of the Active PCM Channels” on Page 126) Preliminary Data Sheet 70 DS3, 2003-07-11 DuSLIC Functional Description PCM Off After a reset, or in power down mode, there is no communication via the PCM highways. Also, when selecting new time slots, it is recommended to switch off the PCM line drivers by setting the control bits to zero. PCM Active This is the normal operating mode without conferencing. Only the channels R1 and X1 are in use, and voice data are transferred from subscriber A to analog subscriber S and vice versa. External Conference In this mode, the SLICOFI-2 acts as a server for a three-party conference of subscribers B, C, and D that may be controlled by any device connected to the PCM highways. The SLICOFI-2 channel itself can remain in power down mode to reduce power consumption. External Conference + PCM Active As in External Conference mode, any external three-party conference is supported. At the same time, an internal phone call is active using the channels R1 and X1. Internal Conference If the analog subscriber S is one of the conference partners, the internal conference mode will be selected. The partners (B, C) do not need any conference facility as the SLICOFI-2 performs all required functions for them as well. 2.11 16 kHz Mode on PCM Highways In addition to the standard 8 kHz transmission PCM interface modes, there are also two 16 kHz modes for high-speed data transmission performance. Table 11 and Table 12 show the configuration of PCM channels for the different PCM interface modes (see “Control of the Active PCM Channels” on Page 126). Preliminary Data Sheet 71 DS3, 2003-07-11 DuSLIC Functional Description Table 11 Possible Modes in PCM/µC Interface Mode: Receive Channels Mode Configuration Bits Receive PCM Channels PCM16K LIN R1 R1L1) R2 R3 R4 PCM 0 0 A 2) B C D LIN 0 1 A-HB A-LB B C D PCM16 1 0 DS1 – – DS2 – LIN16 1 1 DS1-HB – DS1-LB DS2-HB DS2-LB 1) Time slot R1 + 1 2) Empty cells in the table indicate unused data in the PCM receive channels and switched-off line drivers in the PCM transmit channels Table 12 Mode Possible Modes in PCM/µC Interface Mode: Transmit Channels Configuration Bits Transmit PCM Channels PCM16K LIN X1 X1L1) X2 PCM 0 0 S – depends on conference mode LIN 0 1 S-HB S-LB depends on conference mode PCM16 1 0 DS1 – – DS2 – LIN16 1 1 DS1-HB – DS1-LB DS2-HB DS2-LB X3 X4 1) Time slot X1 + 1 The configuration bits PCM16K and LIN (in the BCR3 register) are used to select the following PCM interface modes: PCM Mode Normal mode used for voice transmission via channels R1 and X1 (receive and transmit). The PCM input channels R2, R3 and R4 are always available for use in different conference configurations. The status of the PCM output channels depends on the conference mode configuration. LIN Mode Similar to the PCM mode, but for 16 bit linear data at 8 kHz sample rate via the PCM channels R1, R1L (receive) and channels X1, X1L (transmit). Data are sent MSB first, two’s complement. Preliminary Data Sheet 72 DS3, 2003-07-11 DuSLIC Functional Description PCM16 Mode Mode for higher data transmission rate of PCM encoded data using a 16 kHz sample rate (only in PCM/µC Interface mode with the PCMX-EN bit in the BCR3 register set to one). In this mode, the channels R1, R3 (X1, X3) are used to receive (transmit) two samples of data (DS1, DS2) in each 8 kHz frame. LIN16 Mode Like the PCM16 mode for 16 kHz sample rate, but for linear data. Channels R1 to R4 (X1 to X4) are used for receiving (transmitting) the high and low bytes of the two linear data samples DS1 and DS2. Preliminary Data Sheet 73 DS3, 2003-07-11 DuSLIC Operational Description 3 Operational Description 3.1 Overview of all DuSLIC Operating Modes Table 13 Overview of all DuSLIC Operating Modes SLICOFI-2x Mode Sleep (SL) CIDD/CIOP Additional Bits used2) SLIC Type 1) SLIC-S/ SLIC-S2 SLIC-E/ SLIC-P M2 M1 M0 SLIC-E2 – PDRH PDRH 1 1 1 SLEEP-EN = 1 PDRR 1 1 1 SLEEP-EN = 1, ACTR = 1 PDRH 1 1 1 SLEEP-EN = 0 PDRR 1 1 1 SLEEP-EN = 0, ACTR = 1 Power Down PDRH Resistive (PDR) PDRH PDH Power Down High Impedance (PDH) PDH PDH 0 0 0 – Active High (ACTH) ACTH ACTH ACTH 0 1 0 – Active Low (ACTL) ACTL ACTL ACTL 0 1 0 ACTL = 1 Active Ring (ACTR) ACTR ACTR ACTR 0 1 0 ACTR = 1 Ringing (Ring) ACTR3) ACTR ACTR 1 0 1 – – – ROT 1 0 1 HIT = 1 – – ROR 1 0 1 HIR = 1 HIT 0 0 1 1 0 0 HIT = 1 HIT = 1, ACTR = 0 HIR 0 0 1 1 0 0 HIR = 0 HIR = 0, ACTR = 0 Active with Ring to Ground ROT 0 1 0 HIT = 1, ACTR = 1 Active with Tip to Ground ROR 0 1 0 HIR = 1, ACTR = 1 HIRT 0 1 0 HIR = 1, HIT = 1 Active with HIT4) HIT Active with HIR5) HIR High Impedance – on Ring and Tip (HIRT) Preliminary Data Sheet HIT HIR HIRT 74 DS3, 2003-07-11 DuSLIC Operational Description Table 13 Overview of all DuSLIC Operating Modes (cont’d) SLICOFI-2x Mode CIDD/CIOP Additional Bits used2) SLIC Type 1) SLIC-S/ SLIC-S2 SLIC-E/ SLIC-P M2 M1 M0 SLIC-E2 Active with Metering ACTx3) 6) ACTx4) ACTx4) 1 1 0 TTX-DIS to select Reverse Polarity or TTX Metering Ground Start HIT 1 1 0 0 0 0 – ACTR = 0 0 0 1 HIT HIT Ring Pause ACTR3) ACTR ACTR ROR ROT HIR = 1 HIT = 1 1) CIDD = Data Downstream Command/Indication Channel Byte (IOM-2 Interface) CIOP = Command/Indication Operation For further information, see “SLICOFI-2x Command Structure and Programming” on Page 140. 2) If not otherwise stated in the table, the bits ACTL, ACTR, HIT, HIR must be set to 0. 3) Only for SLIC-S 4) HIT = High Impedance on Tip 5) HIR = High Impedance on Ring 6) ACTx means ACTH, ACTL or ACTR. Sleep (SL) – only available with DuSLIC-E/-E2/-P/-ES/-ES2 The SLICOFI-2 is able to go into Sleep mode with minimal power dissipation. In this mode, off-hook detection is performed without any checks on spikes or glitches. The Sleep mode can be used for either channel, but for the most effective power savings, both channels should be set to this mode. Note that this requires the following: • • • If both channels are set to the Sleep mode, only non-noisy lines should be used due to the lack of persistence checking. Wake up takes about 1.25 ms, as the on-chip PLL is also switched off. Therefore, it is also possible to switch off all external clocks. In this mode, no programming or other functionality is available. The off-hook event is indicated either by (1) setting the interrupt pin to Low level, if the PCM/µC Interface mode is selected, or (2) pulling down the DU pin, if IOM-2 Interface is used. If only one channel is set to Sleep mode, persistence checking and off-hook indication are performed as in any other mode, but the off-hook level is fixed to 2 mA at the subscriber line. No special wake up is needed if only one channel is in Sleep mode. A simple mode change ends the Sleep mode. A sleeping SLICOFI-2 wakes up if the CS pin is drawn to low level when the PCM/µC Interface is used or if the MX bit is set to 0 when the IOM-2 Interface is used. Note Preliminary Data Sheet 75 DS3, 2003-07-11 DuSLIC Operational Description • that no programming is possible until the SLICOFI-2 wakes up. In IOM-2 mode, the identification request can be used as a wake up signal as this command is independent of the internal clock. In the PCM/µC mode, it is recommended that CS be set to 0 for only one clock cycle. After a wake up from Sleep mode, the SLICOFI-2 enters the PDRH or PDRR mode. To re-enter Sleep mode, it is necessary to first perform a mode change to any Active mode on at least one channel. Power Down Resistive (PDRH for SLIC-E/-E2/-S/-S2 and PDRH, PDRR for SLIC-P) The Power Down Resistive mode is the standard mode for none-active lines. Off-hook is detected by a current value fed to the DSP, is compared with a programmable threshold, and is filtered by a data upstream persistence checker. The power management SLIC-P can be switched to a Power Down Resistive High (PDRH) mode or to a Power Down Resistive Ring (PDRR) mode. High Impedance on Ring and Tip (HIRT) The line drivers in the SLIC-E/-E2/-P are shut down and no resistors are switched to the line. Off-hook detection is not possible. In HIRT mode, the SLICOFI-2 is able to measure the input offset of the current sensors. Power Down High Impedance (PDH) In Power Down High Impedance mode, the SLIC is totally powered down. No off-hook sensing can be performed. This mode can be used for emergency shutdown of a line. Active High (ACTH) A regular call can be performed, voice and metering pulses can be transferred via the telephone line, and the DC loop is operational in the Active High mode using VBATH. Active Low (ACTL) The Active Low mode is similar to the Active High mode. The only difference is that the SLIC uses a lower battery voltage, VBATL (bit ACTL = 1). Active Ring (ACTR) The Active Ring mode for the SLIC-E/-E2 is different from the Active Ring mode for the SLIC-P. The SLIC-E/-E2 uses the additional positive voltage VHR for extended feeding, whereas the SLIC-P switches to the negative battery voltage VBATR. Preliminary Data Sheet 76 DS3, 2003-07-11 DuSLIC Operational Description Ringing If the SLICOFI-2x is switched to Ringing mode, the SLIC is switched to ACTR mode. With the SLIC-P connected to the SLICOFI-2, the Ring on Ring (ROR) mode allows unbalanced internal ringing on the Ring wire. The Tip wire is set to battery ground. The Ring signal will be superimposed by VBATR/2. The Ring on Tip (ROT) mode is equivalent to the ROR mode. Active with HIT This is a testing mode where the Tip wire is set to a high impedance mode. It is used for special line testing. It is only available in an Active mode of the SLICOFI-2x to enable all necessary test features. Active with HIR HIR is similar to HIT but with the Ring wire set to high impedance. Active with Metering Any available Active mode can be used for metering, with either Reverse Polarity or with TTX Signals. Ground Start The Tip wire is set to high impedance in Ground Start mode. Any current drawn on the Ring wire leads to a signal on IT, indicating off-hook. Ring Pause The Ring burst is switched off in Ring Pause, but the SLIC remains in the specified mode and the off-hook recognition behaves the same as in Ringing mode (Ring Trip). Preliminary Data Sheet 77 DS3, 2003-07-11 DuSLIC Operational Description 3.2 Operating Modes for the DuSLIC-S/-S2/-SE/-SE2 Chip Set Table 14 DuSLIC-S/-S2/-SE/-SE2 Operating Modes SLICOFI-2S SLIC-S/S2 SLIC-S/-S2 System Active /SLICOFI-2S2 /SLIC-E/E2 /SLICE/E2 Functionality Circuits Internal Mode Mode Supply Voltages (+/–) [VHI/VBI] Tip/Ring Output Voltage PDH PDH Open/VBATH None None Power Down Resistive PDRH Open/VBATH Off-hook detect as in Active mode (DSP) Off-hook, VBGND/VBATH DC transmit (via 5 kΩ) path – PDRHL1) Open/VBATH Off-hook detect as in Active mode (DSP) Off-hook, VBGND/VBATH DC transmit (via 5 kΩ) path Active Low (ACTL) ACTL VBGND/VBATL Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (VBATL + VAC + VDC)/2 Ring: (VBATL –VAC – VDC)/2 Active High (ACTH) ACTH VBGND/VBATH Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (VBATH + VAC + VDC)/2 Ring: (VBATH –VAC – VDC)/2 Active Ring (ACTR) ACTR VHR/VBATH Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (+ VBATH + VHR + VAC + VDC)/2 Ring: (+ VBATH + VHR – VAC – VDC)/2 Preliminary Data Sheet 78 High Impedance DS3, 2003-07-11 DuSLIC Operational Description Table 14 DuSLIC-S/-S2/-SE/-SE2 Operating Modes (cont’d) System Active SLICOFI-2S SLIC-S/S2 SLIC-S/-S2 Functionality Circuits /SLICOFI-2S2 /SLIC-E/E2 /SLICE/E2 Mode Mode Internal Supply Voltages (+/–) [VHI/VBI] Tip/Ring Output Voltage Ringing (Ring) ACTR VHR/VBATH Balanced ring signal feed (including DC offset) Buffer, Sensor, DC loop, Ring generator Tip: (VBATH + VHR + VDC)/2 Ring: (VBATH + VHR – VDC)/2 Ring Pause ACTR VHR/VBATH DC offset feed Buffer, Sensor, DC loop, Ramp generator Tip: (VBATH + VHR + VDC)/2 Ring: (VBATH + VHR – VDC)/2 HIRT HIRT VHR/VBATH For example: sensor offset calibration Sensor, DC High Impedance transmit path Active with HIR HIR VHR/VBATH For example: line test (Tip) Tip Buffer, Sensor, DC + AC loop Active with HIT HIT VHR/VBATH For example: Ring Buffer, line test (Ring) Sensor, DC + AC loop Tip: (VBATH + VHR + VAC + VDC)/2 Ring: High impedance Ring: (VBATH + VHR – VAC –VDC)/2 Tip: High impedance 1) Load external C for switching from PDRH to ACTH in on-hook mode. VAC … Tip/Ring AC Voltage VDC … Tip/Ring DC Voltage Preliminary Data Sheet 79 DS3, 2003-07-11 DuSLIC Operational Description 3.3 Table 15 Operating Modes for the DuSLIC-E/-E2/-ES/-ES2 Chip Set DuSLIC-E/-E2/-ES/-ES2 Operating Modes SLICOFI-2 SLIC-E/E2 SLIC-E/-E2 System Active Mode /SLIC-S/S2 /SLIC-S/S2 Functionality Circuits Internal Mode Supply Voltages (+/–) [VHI/VBI] Tip/Ring Output Voltage PDH PDH Open/VBATH None None High Impedance Sleep PDRH Open/VBATH Off-hook detect via off-hook comparator Off-hook, Analog comparator VBGND/VBATH Off-hook detect as in Active mode (DSP) Off-hook, DC transmit path VBGND/VBATH Off-hook detect as in Active mode (DSP) Off-hook, DC transmit path VBGND/VBATH Power Down Resistive PDRH – PDRHL1) Open/VBATH Open/VBATH (via 5 kΩ) (via 5 kΩ) (via 5 kΩ) Active Low ACTL (ACTL) VBGND/VBATL Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (VBATL + VAC + VDC)/2 Ring: (VBATL –VAC – VDC)/2 Active High (ACTH) ACTH VBGND/VBATH Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (VBATH + VAC + VDC)/2 Ring: (VBATH –VAC – VDC)/2 Active Ring (ACTR) ACTR VHR/VBATH Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (+ VBATH + VHR + VAC + VDC)/2 Ring: (+ VBATH + VHR – VAC – VDC)/2 Preliminary Data Sheet 80 DS3, 2003-07-11 DuSLIC Operational Description Table 15 DuSLIC-E/-E2/-ES/-ES2 Operating Modes (cont’d) System Active SLICOFI-2 SLIC-E/E2 SLIC-E/-E2 Functionality Circuits Mode /SLIC-S/S2 /SLIC-S/S2 Mode Internal Supply Voltages (+/–) [VHI/VBI] Tip/Ring Output Voltage Ringing (Ring) ACTR VHR/VBATH Buffer, Sensor, Balanced DC loop, Ring Ring signal generator feed (including DC offset) Tip: (VBATH + VHR + VDC)/2 Ring: (VBATH + VHR – VDC)/2 Ring Pause ACTR VHR/VBATH DC offset feed Buffer, Sensor, Tip: (VBATH + DC loop, Ramp VHR + VDC)/2 generator Ring: (VBATH + VHR – VDC)/2 HIRT HIRT VHR/VBATH For example: Sensor, DC sensor offset transmit path calibration High Impedance Active with HIR HIR VHR/VBATH For example: Tip-Buffer, line test (Tip) Sensor, DC + AC loop Tip: (VBATH + VHR + VAC + VDC)/2 Ring: High impedance Active with HIT HIT VHR/VBATH For example: Ring-Buffer, line test (Ring) Sensor, DC + AC loop Ring: (VBATH + VHR – VAC –VDC)/2 Tip: High impedance 1) Load external C for switching from PDRH to ACTH in on-hook mode VAC … Tip/Ring AC Voltage VDC … Tip/Ring DC Voltage Preliminary Data Sheet 81 DS3, 2003-07-11 DuSLIC Operational Description 3.4 Table 16 Operating Modes for the DuSLIC-P Chip Set DuSLIC-P Operating Modes SLICOFI-2 SLIC-P Mode Mode SLIC-P Internal Supply Voltages [VBI] System Functionality Active Circuits Tip/Ring Output Voltage PDH PDH VBATR None None Sleep PDRH VBATH Off-hook detect Off-hook, via off-hook Analog comparator comparator VBGND/VBATH Off-hook detect Off-hook, via off-hook Analog comparator comparator VBGND/VBATR Off-hook detect Off-hook, DC as in Active transmit path mode (DSP) VBGND/VBATH Off-hook detect Off-hook, DC transmit path as in Active mode (DSP) VBGND/VBATH Off-hook detect Off-hook, Analog as in Active comparator mode (DSP) VBGND/VBATR Off-hook detect Off-hook, DC as in Active transmit path mode (DSP) VBGND/VBATR Sleep PDRR VBATR VBATH Power Down Resistive PDRH – PDRHL1) VBATH – – PDRR VBATR PDRRL2) VBATR High impedance (via 5 kΩ) (via 5 kΩ) (via 5 kΩ) (via 5 kΩ) (via 5 kΩ) (via 5 kΩ) Active Low ACTL (ACTL) VBATL Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (VBATL + VAC + VDC)/2 Ring: (VBATL – VAC – VDC)/2 Active High ACTH (ACTH) VBATH Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (VBATH + VAC + VDC)/2 Ring: (VBATH –VAC – VDC)/2 Preliminary Data Sheet 82 DS3, 2003-07-11 DuSLIC Operational Description Table 16 DuSLIC-P Operating Modes (cont’d) SLICOFI-2 SLIC-P Mode Mode SLIC-P Internal Supply Voltages [VBI] System Functionality Active Circuits Tip/Ring Output Voltage Active Ring ACTR (ACTR) VBATR Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (VBATR + VAC + VDC)/2 Ring: (VBATR – VAC – VDC)/2 Ringing (Ring) ACTR VBATR Balanced ring signal feed (including DC offset) Buffer, Sensor, DC loop, ring generator Tip: (VBATR + VDC)/2 Ring: (VBATR –VDC)/2 Ringing (Ring) ROR VBATR Ring signal on Buffer, Sensor, DC loop, ring ring, Tip on generator BGND Ring: (VBATR –VDC)/2 Tip: 0 V Ringing (Ring) ROT VBATR Ring signal on Buffer, Sensor, DC loop, ring ring, Tip on generator BGND Tip: (VBATR + VDC)/2 Ring: 0 V Ring Pause ACTR, ROR, ROT VBATR DC offset feed Buffer, Sensor, DC loop, ramp generator Tip: (VBATR + VDC)/2 Ring: (VBATR –VDC)/2 HIRT VBATR For example: sensor offset calibration Sensor, DC transmit path High impedance Active with HIR HIR VBATR For example: line test (Tip) Tip-Buffer, Sensor, DC + AC loop Tip: (VBATR + VAC + VDC)/2 Ring: High impedance Active with HIT HIT VBATR For example: Ring-Buffer, line test (Ring) Sensor, DC + AC loop HIRT Ring: (VBATR –VAC – VDC)/2 Tip: High impedance 1) Load external C for switching from PDRH to ACTH in On-Hook mode 2) Load external C for switching from PDRR to ACTR in On-Hook mode Preliminary Data Sheet 83 DS3, 2003-07-11 DuSLIC Operational Description 3.5 Reset Mode and Reset Behavior 3.5.1 Hardware and Power On Reset A reset of the DuSLIC is initiated by a power-on reset or by a hardware reset. Hardware reset requires setting the signal at RESET input pin to low level for at least 4 µs. The reset input pin has a spike rejection that will safely suppress spikes with a duration of less than 1 µs. Note: Maximum spike rejection time is trej, max. Minimum spike rejection time is trej,min. The SLICOFI-2x is reset by taking the RESET line to low (see Figure 36). During this time: • • • • • all I/O pins are deactivated all outputs are inactive (e.g. DXA/DXB) internal PLL is stopped internal clocks are deactivated the chip enters the power down high impedance mode (PDH) when the Reset is 1 (otherwise the chip is in a kind of Reset Mode that does not exactly equal the power down high impedance mode as the VCM voltage for the SLIC is missing) With the high going reset signal, the following actions take place: • • • • Clock detection PLL synchronization Reset routine runs when the reset routine has finished the chip is in power down impedance mode (PDH) The internal reset routine will then initialize the entire chip to default condition as described in the SOP default register setting (see Chapter 5). To run through the internal reset routine, it is necessary that all external clocks are supplied. The clocks are determined by the mode: • • µC/PCM mode: FSC, MCLK, PCLK IOM-2 mode: FSC and DCL. Note: Without valid and stable external clock signals, the DuSLIC will not complete the reset sequence properly. The internal reset routine requires 12 frames (12 × 125 µs = 1.5 ms) to be finished (including PLL start up and clock synchronization) and requires setting the default values given in Table 17. The first register access to the SLICOFI-2x may be performed after the internal reset routine is finished. Preliminary Data Sheet 84 DS3, 2003-07-11 DuSLIC Operational Description Reset signal at pin RESET t trej (1 to 4 µs) SLICOFI-2x internal reset routine min. 12*125 µs = 1.5 ms Chip reset: - all I/O pins deactivated - all outputs inactive (e.g. DXA/DXB) - internal PLL stopped - internal clocks deactivated First access to SLICOFI-2x possible (RESET interrupt must be cleared). Chip in power down high impedance (PDH) duslic_0016_reset_sequence Figure 36 DuSLIC Reset Sequence Preliminary Data Sheet 85 DS3, 2003-07-11 DuSLIC Operational Description 3.5.2 Software Reset When performing a software reset, the DuSLIC runs the reset routine and sets the default settings of the configuration registers. The software reset can be performed individually for each channel. Table 17 Default DC and AC Values DC IK1 VK1 20 mA Limit for Constant Current 34 V Voltage of limit between Constant Current and Resistive Zone KB 1 – Additional gain with extended battery feeding RI RK12 fRING ARING 10 kΩ Output Resistance in constant current zone 100 Ω Programmable resistance in resistive zone 25.4 Hz Ring frequency 62 Vrms Ring amplitude at Tip/Ring wire RO1 23 V Ring offset voltage RO1 RO2 0 V Ring offset voltage RO2 RO3 50 V Ring offset voltage RO3 fRINGLP 75 Hz Corner frequency of Ring low-pass filter Off-hookPD 2 mA Current threshold for Off-hook Detection in Power Down mode Off-hookAct 8 mA Off-hook Detection in Active with 2 mA hysteresis Off-hookRing 5 mA DC-Current threshold for Off-hook Detection in Ringing mode Off-hookMW 5 mA DC-Current threshold for Off-hook Detection in Message Waiting Off-hookAC 22 mArms Current threshold for AC Ring Trip detection LineSup 5 mA Current threshold Line-Supervision for ground start Tip/Ring 30 V Voltage threshold at Tip/Ring wire for VTRLIM bit DC-Lowpass 1.2/20 Hz DC low-pass set to 1.2 and 20 Hz respectively ConstRamp 300 V/s Slope of the ramp generator delayRING 0 ms Delay of Ring burst SRend1 1/128 – Soft-reversal threshold 1 (referred to the input of the ramp generator) Preliminary Data Sheet 86 DS3, 2003-07-11 DuSLIC Operational Description Table 17 Default DC and AC Values (cont’d) SRend2 1/512 – Soft-reversal threshold 2 (referred to the input of the ramp generator) DUP 10 ms Data Upstream Persistence Counter is set to 10 ms DUP-IO 16.5 ms Data Upstream Persistence Counter for I/O pins, VTRLIM and ICON bits (register INTREG1) is set to 16.5 ms SR-Time 80 ms Time for soft-reversal IM-Filter 900 Ω Approximately 900 Ω real input impedance TH-Filter THGER – Approximately complex german impedance for balanced network LX 0 dBr Relative level in transmit LR –7 dBr Relative level in receive ATTX 2.5 Vrms Teletax generator amplitude at the resistance of 200 Ω fTTX 16 kHz Teletax generator frequency TG1 940 Hz Tone generator 1 (–12 dBm) TG2 1633 Hz Tone generator 2 (–10 dBm) AC-LM-BP 1004 Hz AC level meter band pass AC Preliminary Data Sheet 87 DS3, 2003-07-11 DuSLIC Operational Description 3.6 Interrupt Handling Attention: Even if interrupts are not used in the system application, the user has to clear the reset interrupt after each power-up reset. SLICOFI-2x provides extensive interrupt data for the host system. Interrupt handling is performed by the on-chip microprogram that handles the interrupts in a fixed 2 kHz (500 µs) frame. Therefore, some delays up to 500 µs can occur in the reactions of SLICOFI-2x, depending on when the host reads the interrupt registers. Independent of the selected interface mode (PCM/µC or IOM-2), the general behavior of the interrupt is as follows: • • • • Any change in one of the four interrupt registers (at some bits, only transitions from 0 to 1) leads to an interrupt. The interrupt channel bit INT-CH in INTREG1 is set to 1 and all interrupt registers of one DuSLIC channel are locked at the end of the interrupt procedure (500 µs period). Therefore, all changes within one 2 kHz frame are stored in the interrupt registers. The lock remains until the interrupt channel bit is cleared (Release Interrupt by reading all four interrupt registers INTREG1 to INTREG4 with one command). In IOM-2 Interface mode, the interrupt channel bits are fed to the CIDU channel (see IOM-CIDU). In PCM mode, the INT pin is set to active (low). The interrupt is released (INT-CH bit reset to 0) by reading all four interrupt registers by one command. Reading the interrupt registers one-by-one using a series of commands does not release the interrupt even if all four registers are read. A hardware or power-on reset of the chip clears all pending interrupts and resets the INT line to inactive (PCM/µC mode) or resets the INT-CH bit in CIDU (IOM-2 mode). The behavior after a software reset of both channels is similar, the interrupt signal switches to non-active within 500 µs. A software reset of one DuSLIC channel deactivates the interrupt signal if there is no active interrupt on the other DuSLIC channel. If the reset line is deactivated, a reset interrupt is generated for each channel (bit RSTAT in register INTREG2). 3.6.1 Recommended Procedure for Reading the Interrupt Registers When using SLICOFI-2, the following procedure has to be applied: In case of an interrupt it is recommended to identify the interrupting channels first, before reading all four interrupt registers (see Figure 37): Preliminary Data Sheet 88 DS3, 2003-07-11 DuSLIC Operational Description S ta rt In te rru p t R o utin e R e a d R e giste r IN T R E G 1 o f C h a n ne l A IN T -C H B it o f C h a nn e l A = 1 ? No Yes R e a d a ll 4 In te rru p t R e g iste rs o f C ha n n e l A w ith one SOP Read Com m and R e ad IN T R E G 1 o f C h a n ne l B IN T -C H B it o f C h a nn e l B = 1 ? No Yes R e a d a ll 4 In te rru p t R e g iste rs o f C ha n n e l B w ith one SOP Read Com m and A n a lyze In te rru p tin g E ve n t a n d R ea ct to In te rru p t (A pp licatio n S p e cific: F o r E xa m ple S w itch to A ctive M o d e in C a se o f a n O ff-ho o k) E n d In te rru p t R o u tin e Reading_IR Figure 37 Reading Interrupt Registers Preliminary Data Sheet 89 DS3, 2003-07-11 DuSLIC Operational Description 3.7 Power Management and Operating Modes In many applications the power dissipated on the linecard is a critical parameter. In large systems it is the mean power value (taking into account traffic statistics and line length distribution) that determines cooling requirements. On the other hand, particularly in remotely fed systems, the maximum power per line must be kept below a given limit. Generally, system power dissipation is determined primarily by the high-voltage part. The most effective power-saving method thus is to optimize both SLIC functionality and supply voltage. This is primarily achieved by using different operating modes. The three main modes (Power Down, Active and Ringing) correspond to the main system states: on-hook, signal transmission (voice, DTMF and/or TTX) and ring signal feed. Power Down Off-hook detection is the only function available. It is achieved by internally connecting 5 kΩ resistors from Tip to BGND and from Ring to VBAT. A simple sensing circuit supervises the DC current through these resistors (zero in on-hook and non-zero in off-hook state). This scaled transversal line current is transferred to the IT pin and compared with a programmable current threshold in the SLICOFI-2x. Only the DC loop in the SLICOFI-2x is active. Sleep Mode In Sleep mode both AC and DC loops are inactive. Off-hook detection, however, is still possible using an analog comparator. For lowest power consumption the clocks fed to the MCLK and PCLK pins also must be shut off. To change the DuSLIC to another state, it must be woken up according to the procedure described in Chapter 3.1. Active Both AC and DC loops are operative. The SLIC provides low-impedance voltage feed to the line. An integrated supply voltage switch allows to choose between two (SLIC-S/E) or even three (SLIC-P) different battery voltages, depending on loop length. Ringing For internal ringing applications, the total supply range can be extended to 150 V to allow ring signals up to 85 Vrms. Whereas SLIC-S/E uses a positive supply VHR, the most negative battery voltage VBATR is intended for ringing with SLIC-P. The voltage capability is sufficient to drive very long lines at any ringer load and to reliably detect Ring trip. For an overview of all DuSLIC operating modes, see Table 14 for PEB 4264/-2, Table 15 for PEB 4265/-2 and Table 16 for PEB 4266. Preliminary Data Sheet 90 DS3, 2003-07-11 DuSLIC Operational Description 3.7.1 SLICOFI-2x Power Dissipation For optimized power consumption, unused EDSP functions must be switched off. Typical power dissipation values for different operating modes of the SLICOFI-2x can be found in the device data sheets. 3.7.2 SLIC Power Dissipation The SLIC’s power dissipation can be divided into two parts, the first arising from internal bias currents, the second being caused by any current fed to the line: P = PQ + PO with PQ = VDD * IDD + |VBATL| * IBATL + |VBATH| * IBATH + |VBATR| * IBATR + VHR * IHR [1] PO = (1.05 * VBATx - VTR) * ITR = 1.05 * VBATx * ITR - RLoop * ITR2 [2] Note: VBATx is the relevant output stage supply voltage, whereas VTR, ITR and RLoop denote line voltage, current and total line resistance, resp.. For any operating mode, the quiescent power dissipation PQ (power at zero line current) thus is determined by the internal supply currents as specified in the respective SLIC data sheets (IBATR = 0 for SLIC-E/S, IHR = 0 for SLIC-P). Significant design effort has been spent to keep them low. Nevertheless, in typical active operations, the power component PO caused by the line current dominates. This power is dissipated in the output stages (to some small extent also in the current sensor) and is approximately proportional to the difference of respective supply voltage VBATx and line voltage VTR. Obviously, the best way for power reduction is to keep the supply voltage as low as possible. 3.7.2.1 Power Down Modes In all Power Down modes, the internal bias currents are extremely small and no current is fed to the line. Even with active off-hook detection, the resulting power dissipation of 5 mW is negligible. It is worth pointing out, that in large systems, due to the high percentage of inactive lines, this is the dominant factor for achieving a very low mean power value. Preliminary Data Sheet 91 DS3, 2003-07-11 DuSLIC Operational Description 3.7.2.2 Active Modes In all active modes, the total power dissipation usually is dominated by the line current part PO (eq. 2); the quiescent power typically is below 150 mW. For any line with total resistance RLoop, the battery supply VBATx has to fulfill the condition VBATx > ITR,DC * RLoop + VAC,pk + VDrop VAC,pk peak value of AC signal VDrop sum of voltage drops in SLIC output stage (typ. 2 V @ 20 mA) Ideally, the supply voltage would be optimized individually for any line. This, however, is only possible at the expense of high effort, as it would require an highly efficient DC/DC converter per line. On the other hand, a single fixed VBAT is determined by the longest loop (largest RLoop) to be served, and from eq. [2] would lead to very high power at short lines. A very efficient way to reduce short-loop power dissipation now is to use a second, lower battery supply voltage (VBATL) whenever line resistance is small enough. This method is supported on all SLICs by the integration of a battery switch (SLIC-P even allows the use of 3 battery voltages). The efficiency is demonstrated in Figure 38 comparing typical total active power dissipation values for a 20 mA line current as a function of loop resistance for single -48 V (dotted) and double -48/-24 V (solid) battery voltages, resp.. P [mW] 1200 1000 800 600 400 200 0 0 500 1000 1500 2000 RLOOP [Ω] SLIC_power_diss Figure 38 Typical SLIC Power Dissipation Preliminary Data Sheet 92 DS3, 2003-07-11 DuSLIC Operational Description 3.7.2.3 Ringing Mode Basically the considerations above are also valid in Ringing Mode. The only difference results from the fact, that in Ringing a large sinusoidal signal is applied to a complex RC load (compared with DC drive of an ohmic load in active modes). Eq. [2] is still valid, but obviously PO now is time dependent due to the time dependence of both ringing voltage VTR and the resulting loop current. If the total load impedance (loop resistance plus ringer load) is denoted as ZL = |ZL| * e jφ = RLoop + RRing + 1 / jωCRing calculation of the average ring power yields PO = (4 * VBATx - π * VRing,pk* cos φ) * VRing,pk / (2 * π * ZL) Here VBATx again denotes the total battery supply voltage. The minimum value can be derived from the condition VBATx > VRing,pk + VRing,DC + VDrop = VRing,rms * crest factor + VRing,DC + VDrop The crest factor is the ratio of peak and rms value (here 1.41, as sinusoidal ringing is assumed). VRing,DC superimposed DC voltage for Ring trip detection (10 to 20 V) VDrop sum of voltage drops in SLIC output stage (typ. 2 V @ 20 mA) VRing,pk / rms peak / effective ring voltage at Tip/Ring pins As the resulting VBATx for ringing typically is significantly larger than in active transmission modes, the total supply range is increased by either using an additional positive supply VHR (so VBATx = VHR - VBATH for SLIC-S/E) or providing a third battery voltage VBATR (VBATx = VBATR for SLIC-P). Again, to minimize power dissipation, VBATx has to be kept as low as possible. In ringing, however, the voltage at the ringer rather than at the TIP/RING pins is decisive. Due to voltage division between ringer and line, the worst case for VBATx is represented by maximum ringer load (minimum ringer impedance, e.g 5 US REN) at maximum loop length. The above calculation is valid for power dissipation during the ring burst. The power values cover a broad range from typically 1 W to 3 W, mainly depending on the ringer load. The mean ring power then can be calculated by averaging over the burst / pause cycle. So for a typical ringing cadence (1 second on and 4 seconds off) power is given by Paverage = k * PRing + (1 – k) * PRingPause with k = 0.20 Preliminary Data Sheet 93 DS3, 2003-07-11 DuSLIC Operational Description 3.8 Integrated Test and Diagnostic Functions (ITDF) 3.8.1 Introduction Subscriber loops are affected by a variety of failures that must be monitored. Monitoring the loop requires access to the subscriber loop and requires test equipment in place that is capable of performing certain specific measurements. The tests involve measurement of resistance, capacitance, leakage, and any interfering currents and voltages. 3.8.1.1 Conventional Line Testing Conventional linecards in Central Office (CO) applications usually need two test relays per channel to access the subscriber loop with the appropriate test equipment. One relay (test-out) connects the actual test unit to the local loop. All required line tests can be accomplished that way. The second relay (test-in) separates the local loop from the SLIC and connects a termination impedance to it. Hence, sending a tone signal allows the entire loop to be checked, including the SLICOFI-2x and SLIC. 3.8.1.2 DuSLIC Line Testing The DuSLIC chip set uses its Integrated Test and Diagnostic Functions (ITDF) to perform all tests necessary for monitoring the local loop without an external test unit and test relays. The fact that measurements can be accomplished much faster than with conventional test capabilities makes an even more compelling argument for the use of the DuSLIC chip set. With the DuSLIC, line tests on both channels can be performed concurrently, which also has a tremendous impact on the test time. All in all, the DuSLIC increases the quality of service and reduces the costs in various applications. Line failure Line Testing DuSLIC-S Yes DuSLIC-S2 Yes DuSLIC-E Yes DuSLIC-E2 Yes DuSLIC-P Yes ? CO duslic_0025_linetesting Figure 39 DuSLIC Line Testing Preliminary Data Sheet 94 DS3, 2003-07-11 DuSLIC Operational Description 3.8.2 Diagnostics DuSLIC incorporates signal generators and test features implemented to accomplish a variety of diagnostic functions. The SLICOFI-2x device generates all test signals, processes the information that comes back from the SLIC, and provides the data to a higher level master device, such as a microprocessor. All the tests can be initiated by the microprocessor and the results can be read back very easily. 3.8.2.1 Line Test Capabilities The line test comprises the following functions: • • • • • • • • • • • • • • • Loop resistance Leakage current Tip/Ring Leakage current Tip/GND Leakage current Ring/GND Ringer capacitance Line capacitance Tip/Ring Line capacitance Tip/GND Line capacitance Ring/GND Foreign voltage measurement Tip/GND Foreign voltage measurement Ring/GND Foreign voltage measurement Tip/Ring Measurement of ringing voltage Measurement of line feed current Measurement of supply voltage VDD of the SLICOFI-2x Measurement of transversal- and longitudinal current Two main transfer paths (level metering) are implemented to accomplish all the different line measurement functions (refer to Figure 40). 3.8.2.2 Integrated Signal Sources The signal sources available on the DuSLIC chip set are: • • • • Constant DC voltage (three programmable ringing DC offset voltages) Refer to the CRAM coefficient set and register LMCR3 (bits RNG-OFFSET[1:0]) on Page 185 for more information. 2 independent tone generators TG1 and TG2: Refer to the CRAM coefficient set and register DSCR (bits PTG, TG2-EN, TG1-EN) on Page 179 for more information. TTX metering signal generator (12/16 kHz) Refer to the CRAM coefficient set and register BCR2 (bits TTX-DIS, TTX-12k) on Page 170 for more information. Ramp generator (used for capacitance measurements) Refer to the CRAM coefficient set and register LMCR2 (bit RAMP-EN) on Page 183. Preliminary Data Sheet 95 DS3, 2003-07-11 DuSLIC Operational Description • Ring generator (5 Hz - 300 Hz) Refer to the CRAM coefficient Table 35 "CRAM Coefficients" on Page 205. Figure 40 shows the entire level metering block for AC and DC: A/D SIGMA DELTA 4 MHz AC PREFI ITAC VOICE PATH DECIMATION a AC LEVELMETER + PCM IN: Receive Data from PCM or IOM-2 Interface BANDPASS NOTCH FILTER MUX RECTIFIER CRAM LMCR2: LM-NOTCH LM-FILT LMCR2: LM-SEL[3:0] SHIFT FACTOR KINTAC INTEGRATOR 1x16ms ... 16x16ms CRAM LMCR3: LM-ITIME[3:0] b OFR1/2 IT IL IO3 IO4 OFFSET REGISTER A/D MUX 1 Bit SIGMA DELTA 1 MHz DC PREFI IO4 - IO3 Offset DECIMATION VDD 2 kHz +/- 19 Bit + c DC Output Voltage VDC on DCN – DCP LMCR2: LM-SEL[3:0] LMCR2: LM-SEL[3:0] A-B A-B a VOICE PATH PCM OUT: Transmit Data to PCM or IOM-2 Interface b DC LEVELMETER MUX LMCR1: LM2PCM RECTIFIER c 16 / 1 ON / OFF PROGR GAIN STAGE LMCR1: DC-AD16 LMCR2: LM-RECT SHIFT FACTOR KINTDC INTEGRATOR (Ring Period) CRAM CRAM RESULT REG LMCR1: LM-EN MUX LMRES1/2 TTX ADAPTIVE FILTER TTX REAL TTX IMG. Programmable Not Programmable LMCR2: LM-SEL[3:0] duslic_0010_level_meter_block Figure 40 Level Metering Block Diagram Preliminary Data Sheet 96 DS3, 2003-07-11 DuSLIC Operational Description 3.8.2.3 Result Register Data Format The result of any measurement can be read via the result registers LMRES1/2. This gives a 16-bit value, with LMRES1 being the high and LMRES2 being the low byte. The result is coded in 16-bit two´s complement: Table 18 Level Metering Result Value Range Negative Value Range Positive Value Range –Full Scale +Full Scale 0x8000 0xFFFF 0 0x7FFF –32768 –1 0 +32767 3.8.2.4 Using the Level Metering Integrator Both AC and DC level metering allows use of a programmable integrator. The integrator may be configured for a single measurement or to run continuously. See Figure 41 through Figure 43. Single Measurement Sequence (AC & DC Level Metering) S ta rt N ew M easurem ent LM C R 1: L M -O N C E = 1 LM C R 1: LM -E N In t. P e rio d In t. P e rio d IN T R E G 2: LM -O K Read Result LMRES1/2 Figure 41 duslic_0019_LM_single Single Measurement Sequence (AC & DC Level Metering) Preliminary Data Sheet 97 DS3, 2003-07-11 DuSLIC Operational Description Continuous Measurement Sequence (DC Level Metering) LM C R 1: L M -O N C E = 0 L M C R 1 : LM -E N In t. P e rio d In t. P e rio d 500 µs In t. P e rio d In t. P e rio d 500 µs 500 µs IN T R E G 2: LM -O K Read Result LMRES1/2 Read Result LMRES1/2 Read Result LMRES1/2 duslic_0020_LM_contDC Figure 42 Continuous Measurement Sequence (DC Level Metering) Continuous Measurement Sequence (AC Level Metering) LM C R 1: L M -O N C E = 0 L M C R 1: LM -E N 1 ms In t. P e rio d 1 ms In t. P e rio d 500 µs In t. P e rio d 500 µs 500 µs IN T R E G 2: LM -O K Read Result LMRES1/2 Read Result LMRES1/2 Read Result LMRES1/2 duslic_0021_LM_contAC Figure 43 Continuous Measurement Sequence (AC Level Metering) Preliminary Data Sheet 98 DS3, 2003-07-11 DuSLIC Operational Description The integrated test and diagnostic functions of the DuSLIC allow to do measurements with and without an integrator. A measurement with the integrator is started by setting the bit LM-EN in register LMCR1 from 0 to 1. LM-EN LM-OK Integration Period Read LM result register After bit LM-EN is set from 0 to 1, bit LM-OK can still be 1 from a previous measurement: - SLICOFI-2 V1.5: 1000 µs delay until bit LM-OK is set to 0. Figure 44 Timing_LM-OK Timing LM-OK Bit When using the integrator for doing levelmeter measurements, the LM-OK bit in register INTREG2 is used to indicate if the integration has started or is finished, respectively. After the bit LM-OK is set to 1 again, the result registers can be read to get the measurement result. Figure 44 shows the timing of the bit LM-OK in relation to the start of the integration period (transition of LM-EN from 0 to 1) and in relation to a valid result in the result registers. The user control software must take care of the mentioned timing relationship: 1. After starting the integrator by setting bit LM-EN from 0 to 1, the bit LM-OK could still be set to 1 from a previous measurement, which would indicate the end of the integration period while the actual integration is still going on. – With SLICOFI-2x Version 1.5, the firmware must wait at least 1 ms before polling the bit LM-OK. 2. After the integration is finished, the bit LM-OK is set to 1 by SLICOFI-2x. – With SLICOFI-2x Version 1.5, the LM-OK bit is set to 1 synchronous with the availability of the LM result. Therefore no delay is necessary before reading the levelmeter result registers. Preliminary Data Sheet 99 DS3, 2003-07-11 DuSLIC Operational Description 3.8.2.5 DC Level Metering The path of the DC level meter is shown in Figure 40. Hereby, the DC level meter results will be determined and prepared depending on certain configuration settings. The selected input signal becomes digitized after pre-filtering and analog-to-digital conversion. The DC level meter is selected and enabled as shown in Table 19: Table 19 Selecting DC Level Meter Path LM-SEL[3:0] in register LMCR2 DC Level Meter Path 0100 DC out voltage on DCP-DCN 0101 DC current on IT 1001 DC current on IL 1010 Voltage on IO3 1011 Voltage on IO4 1101 VDD 1110 Offset of DC-pre-filter (short circuit on DC-pre-filter input) 1111 Voltage on IO4 – IO3 The effective sampling rate after the decimation stages is 2 kHz. The decimated value has a resolution of 19 bits. The offset compensation value (see Chapter 3.8.2.8) within the offset registers OFR1 (bits OFFSET-H[7:0]) and OFR2 (bits OFFSET-L[7:0]) can be set to eliminate the offset caused by the SLIC current sensor, pre-filter, and analog-todigital converter. After the summation point the signal passes a programmable digital gain filter. The additional gain factor is either 1 or 16 depending on register LMCR1 (bit DC-AD16): • • LMCR1 (bit DC-AD16) = 0: No additional gain factor LMCR1 (bit DC-AD16) = 1: Additional gain factor of 16 The rectifier after the gain filter can be turned on/off with: • • LMCR2 (bit LM-RECT) = 0: Rectifier disabled LMCR2 (bit LM-RECT) = 1: Rectifier enabled A shift-factor KINTDC in front of the integrator prevents the level meter during an integration operation to create an overflow. If an overflow in the level meter occurs, the output result will be ± full scale (see Table 18). If the shift factor KINTDC is set to e.g. 1/8, the content of the level meter result register is the integration result divided by 8. Preliminary Data Sheet 100 DS3, 2003-07-11 DuSLIC Operational Description The shift factor KINTDC is set in the CRAM (offset address 0x76): CRAM: Address Address 0x76: LMDC2/LMDC1 0x77: 0/LMDC3 LMDC1, LMDC2 and LMDC3 are 4-bit nibbles which contain KINTDC. Table 20 KINTDC Setting Table LMDC1 LMDC2 LMDC3 KINTDC 8 8 0 1 8 8 1 ½ 8 8 : : 8 8 6 1/64 8 8 7 1/128 DuSLICOS allows automatic calculation of the coefficients for KINTDC for ITRANS measurement. The according parameter is "DC Levelmeter current 50% full scale" (see DuSLICOS DC Control Parameters 4/4). The setting of this parameter affects the shift factor (KINTDC) of the DC levelmeter. The set current will result in 50% full scale of the levelmeter result registers if the integration of the DC levelmeter is done over the integration period determined by the ring frequency. Example: if the DC levelmeter current 50% full scale is set to 2 mA and the actual current to be measured is 3 mA, the value of the levelmeter result register is 24575D (75% full scale). DuSLICOS uses finer steps as the examples listed in Table 20. If the user wants to set the KINTDC factor manually, the listed steps should be sufficient. The expected “Current for Ring Off-hook Detection” (see DuSLICOS DC Control Parameter 2/4) of 20 mA, for example, is entered in to the program and then KINTDC is automatically calculated to achieve 50 % full scale if the current of 20 mA is integrated over the set ringer period. The integration function accumulates and sums up the level meter values over a set time period. The time period is determined by the programmed ring frequency. A ring frequency fRING of 20 Hz results in 100 samples (NSamples), because of the 2 kHz effective DC sampling rate fS,DC. f S, DC N Samples = --------------= 2000Hz --------------------f RING f RING The number of integration samples NSamples may also be programmed directly by accessing dedicated bytes in the Coefficient RAM (CRAM). Preliminary Data Sheet 101 DS3, 2003-07-11 DuSLIC Operational Description CRAM: Address Address 0x73: RGF2/RGF1 0x74: RGA1/RGF3 RGF1, RGF2 and RGF3 are 4-bit nibbles which control the ring frequency fRING. RGA1 is a 4-bit nibble that is calculated by DuSLICOS and which controls the ringer amplitude (see DuSLICOS byte file). To ensure that RGA1 is not changed, please perform a read/modify/write operation. Table 21 NSamples Setting Table RGF1 RGF2 RGF3 fRING NSamples 8 8 0 500 4 8 8 1 250 8 8 8 : : : 8 8 6 7.81 256 8 8 7 3.91 512 The integration function can be turned on and off by bit LM-EN in register LMCR1. The level meter result of the selected signal source will be stored in the result registers LMRES1 (bits LM-VAL-H[7:0]) and LMRES2 (bits LM-VAL-L[7:0]) depending on the LM-SEL[3:0] bits in register LMCR2. The result registers get frequently updated every 500 µs if bit LM-EN in register LMCR1 = 0, or after an integration period, if bit LM-EN in register LMCR1 = 1. If the bit LM-ONCE in register LMCR1 is set to 1, then the integration is executed only once. To start again, bit LM-EN must be changed from 0 to 1. The level meter source/result can be transferred to the PCM/IOM-2 Interface, depending on the bit LM2PCM in register LMCR1. Table 22 shows the level meter results without and with integrator function. The integrator is enabled if bit LM-EN in register LMCR1 = 1. The level meter result LMValue is a 16 bit two´s complement value of LM-VAL-H[7:0] and LM-VAL-L[7:0]. The factor LMResult used in Table 22 is defined: LM Value LM Result = --------------------32768 • Example for positive value of LMResult: LM-VAL-H = “0010 0100" = 0x24 LM-VAL-L = “1010 0101" = 0xA5 LMValue = 0x24A5 = 9381 Preliminary Data Sheet 102 DS3, 2003-07-11 DuSLIC Operational Description LMResult = 0.2863 • Example for negative value of LMResult: LM-VAL-H = “1001 1001" = 0x99 LM-VAL-L = “0110 0010" = 0x62 LMValue = 0x9962 = –26270 LMResult = –0.8017 Table 22 Level Meter Results with and without Integrator Function LM-EN = 0 (without Integrator) ITRANS1): Power Down Resistive ITRANS1): any other mode I = LM TRANS I TRANS ACTR, ringing mode TRANS = LM Result 7.966 mA × -------------------------------------------------------------N Samples × K INTDC K × V IT AD × ----------------------------------------------------------------------------------R × N × K IT2 Samples INTDC I I × 79.66 mA 79.66 mA I TRANS = LM Result × -------------------------------------------------------------N × K Samples INTDC TRANS = LM LONG LONG = – LM V INPUT Result – LMResult × = Result = – LM × Result IT2 K IL--------× V AD R IL 67.7 mA I I × VAD V V Result × Result × DC = – LM DC = – LM TRANS LONG V 76.35 V V 152.7 V V = LM = – LM LONG V V DD = – LM Result × 3.9 V ACTL, ACTH VDC6) with I × 7.966 mA K × V IT, PDR AD × ----------------------------------------------------------------------------------Result R × N × K IT2 Samples INTDC K IT ------------ × V AD R I VDC6) with Result TRANS = LM × I VDD = LM I I TRANS = LM Result ILONG2) Voltage: IO33), IO44), IO4-IO35) K IT, PDR × ---------------------------- × V AD Result R IT2 LM-EN = 1 (with Integrator) Result Result = – LM INPUT K × V IL AD × ------------------------------------------------------------------------------R × N × K IL Samples INTDC Result = – LM × Result 67.7 mA ------------------------------------------------------------× K N Samples INT DC V AD × -------------------------------------------------------------N × K Samples INTDC DD = – LM Result 3.9 V × ------------------------------------------------------------N × K Samples INT DC DC = – LM Result 76.35 V × ------------------------------------------------------------× K N Samples INT DC DC = – LM Result 152.7 V × ------------------------------------------------------------× K N Samples INT DC 1) DC current on pin IT (bits LM-SEL[3:0] = 0101) Preliminary Data Sheet 103 DS3, 2003-07-11 DuSLIC Operational Description 2) DC current on pin IL (bits LM-SEL[3:0] = 1001) 3) Voltage on IO3 referenced to VVCM (typical 1.5 V) (bits LM-SEL[3:0] = 1010) 4) Voltage on IO4 referenced to VVCM (typical 1.5 V) (bits LM-SEL[3:0] = 1011) 5) Voltage on IO4 – IO3 referenced to VVCM (typical 1.5 V) (bits LM-SEL[3:0] = 1111) 6) DC output voltage at SLIC measured via DCN – DCP (bits LM-SEL[3:0] = 0100) KINTDC Shift Factor (see Table 20) KIT,PDR Value of the current divider in power down resistive mode 5 KIT Value of the current divider for transversal current 50 KIL Value of the current divider for longitudinal current 100 RIT2 Sense resistor for transversal current 680 Ω RIL Sense resistor for longitudinal current 1600 Ω VAD VDC Voltage at A/D converter referred to digital full scale 1.0834 DC output voltage at SLIC measured via DCN – DCP Note: Measurement of pins IL, IO3, IO4, IO4-IO3 and VDD can cause problems in the DC loop. The measured value is always interpreted as ITRANS current. This can disturb the DC regulation and the off-hook indication. In Active mode, the output of the DC loop can be frozen by setting the bit DC-HOLD to 1. In Ringburst mode, it is possible for DuSLIC to automatically switch back to Ringpause mode if the measurement result was interpreted as off-hook. This can be avoided by programming the off-hook current to the maximum value (79.66 mA). Measurement of AC Signals via DC Level Meter This method is applicable for a single frequency sinusoidal AC signal that is superimposed on a DC signal. 1. Set the ring frequency fRING to the frequency of the signal to be measured. Multiples of the expected signal period may also be used. 2. Set the offset registers OFR1 and OFR2 to 0x00. 3. Measure the DC contents with disabled rectifier (bit LM-RECT = 0). The DC contents can be calculated as described in Table 22. Note: If there was an overflow inside the integrator during the integration period, the result will be ± full scale. Reduce the shift factor KINTDC or the number of samples NSamples and start the measurement again. Preliminary Data Sheet 104 DS3, 2003-07-11 DuSLIC Operational Description 4. The offset registers OFR1 and OFR2 must be programmed to the value LM Value OFFSET = – -----------------------------------------------------------N Samples × K INTDC where OFR1 is the high byte and OFR2 is the low byte of the 16 bit word OFFSET. 5. Repeating the measurement of the DC content should result in a LMValue of zero. 6. Perform a new measurement with the rectifier enabled (bit LM-RECT = 1). The result is the rectified mean value of the measured signal an can be calculated with the formulas of Table 22. 7. From this result, the peak value and the RMS value can be calculated: V Mean × π V Peak = ----------------------------2 V Peak V RMS = --------------2 3.8.2.6 AC Level Meter The AC level meter is selected and enabled as shown in Table 23: Table 23 Selecting AC Level Meter Path LM-SEL[3:0] in register LMCR2 AC Level Meter Path 0000 AC level meter in transmit 0110 AC level meter in receive 0111 AC level meter receive + transmit Figure 40 on Page 96 shows the path of the AC/TTX level meter functions. The AC level meter allows access to the voice signal while the active voice signal is being processed. The input signal for the AC level meter might get processed with a programmable filter characteristic, such as a bandpass- or notch filter. Depending on the following settings, the bandpass or notch filter is turned on or off: • • • • Register LMCR2 bit LM-FILT = 0: No filter enabled (normal operation) Register LMCR2 bit LM-FILT = 1: Bandpass/notch filter characteristics enabled Register LMCR2 bit LM-NOTCH = 0: Notch filter enabled, bandpass filter disabled Register LMCR2 bit LM-NOTCH = 1: Bandpass filter enabled, notch filter disabled The rectifier cannot be turned off, it is always active in the AC path. A shift-factor in front of the integrator prevents the level meter from creating an overflow during an integration operation. The shift-factor can be set by the coefficient LM-AC gain (see CRAM coefficient set Table 35 "CRAM Coefficients" on Page 205). Preliminary Data Sheet 105 DS3, 2003-07-11 DuSLIC Operational Description KINTAC can be set via coefficient LM-AC: CRAM: Address 0x34: CG1/LM-AC LM-AC is a 4-bit nibble which contains KINTAC. CG1 is a 4-bit nibble that is calculated by DuSLICOS and which controls the conference gain (see DuSLICOS byte file). To ensure that CG1 is not changed, please perform a read/modify/write operation. Table 24 KINTAC Setting Table LM-AC KINTAC 0 1 1 ½ : : 6 1/64 7 1/128 The integration function accumulates and sums up the level meter values over a set time period. The time period from 1*16 ms to 16*16 ms is set by the bits LM-ITIME[3:0] in register LMCR3. The integration function can be turned on and off by bit LM-EN in register LMCR1. The number of samples NSamples for the integrator is defined by: NSamples = LM-ITIME * 8000 The level can be calculated by: π U dBm0 = 20 × log LM Result × --------------------------------------------------------------- + 3.14 2 × K INT × N Samples The result registers get frequently updated after an integration period, if bit LM-EN in register LMCR1 = 1. If the bit LM-ONCE in register LMCR1 is set to 1 then the integration is executed only once. To start again, bit LM-EN must be changed from 0 to 1. The level meter result can be transferred to the PCM/IOM-2 Interface, depending on bit LM2PCM in register LMCR1. Measurement of Currents via ITAC To take current measurements via pin ITAC, all feedback loops (IM-filters and TH-filters) should be disabled. To simplify the formulas, the programmable receive and transmit gain is disabled. This is done by setting the following bits: Preliminary Data Sheet 106 DS3, 2003-07-11 DuSLIC Operational Description Register BCR4: AR-DIS = 1, AX-DIS = 1, TH-DIS = 1, IM-DIS = 1, FRR-DIS = 1, FRX-DIS = 1 Register TSTR4: OPIM-AN = 1, OPIM-4M = 1 Register LMCR1: TEST-EN = 1 This setting results in a receive gain of 11.88 dB caused by the internal filters. Based on this, a factor KAD (analog to digital) can be defined: filter AD ------------------20 11.88 --------------20 –1 10 10 K AD = ---------------------- = ------------------ = 3.272 V 1.2 V V ADC Transversal current IRMS measured at SLIC: RMS LM Result LM Result × K IT × π = ---------------------------------------------------------------------------------------------------------------------- = --------------------------------------------------- × 14.76 mA K INTAC × N Samples K AD × R ITAC × K INTAC × N Samples × 2 × 2 RITAC Sense resistor for AC transversal current (RIT1 + RIT2) 1150 Ω KAD Constant factor from Analog to Digital 3.272 V–1 VADC Voltage at A/D converter referred to digital full scale 1.2 V KIT Value of the current divider for transversal current 50 To prevent overloading the analog input, the maximum AC transversal current may not be higher than 9 mA rms. Usage of Tone Generator as Signal Source To simplify the formulas, the programmable receive and transmit gain is disabled. This is done by setting the following bits: Register BCR4: AR-DIS = 1, AX-DIS = 1, TH-DIS = 1, IM-DIS = 1, FRR-DIS = 1, FRX-DIS = 1 Register TSTR4: OPIM-AN = 1, OPIM-4M = 1 Register LMCR1: TEST-EN = 1 The tone generator level is influenced by a factor KTG, which is set in the tone generator coefficients. The internal filter attenuation is 2.87 dB. K DA = V DAC × 10 –2.87 --------------20 Preliminary Data Sheet Trapez × -------------------- × K AC ,SLIC = 1.2 × 10 2 107 –2.87 --------------20 1.05 × ---------- × 6 2 DS3, 2003-07-11 DuSLIC Operational Description KDA Constant factor from Digital to Analog 3.84 Vrms KAC,SLIC Amplification factor of the SLIC 6 VDAC Voltage at D/A converter referred to digital full scale 1.2 V Trapez Crest factor of the trapezoidal signal 1.05 Output voltage between Tip and Ring: VOUT = KDA * KTG The bytes below are valid for tone generator TG1 an a frequency of 1000 Hz. CRAM: Address Address Address Address Address Address 0x38: 0x08 0x39: T11G/0 0x40: T13G/T12G 0x41: 0x05 0x42: 0xB3 0x43: 0x01 T11G, T12G and T13G are 4-bit nibbles which control the amplitude of the tone generator TG1. Table 25 KTG Setting Table T11G T12G T13G KTG 8 9 1 7/8 8 0 8 ½ 8 1 8 ¼ 8 : 8 : 8 5 8 1/64 8 6 8 1/128 8 7 8 1/256 3.8.2.7 Level Meter Threshold A threshold can be set for the level meter result. When the result exceeds the threshold, then bit LM-THRES in register INTREG 2 is set to 1. It is also possible to activate an interrupt when the LM-THRES bit changes by setting the bit LM-THM (level meter threshold mask bit) in register LMCR2 to 0. Preliminary Data Sheet 108 DS3, 2003-07-11 DuSLIC Operational Description The level meter threshold can be calculated with DuSLICOS or may be taken from Table 26. CRAM: Address Address 0x2C: LMTH2/LMTH1 0x2D: 0/LMTH3 (LMTH1, LMTH2 and LMTH3 are 4 bit nibbles) Table 26 Threshold Setting Table LMTH1 LMTH2 LMTH3 Threshold 1 0 0 75.0 % 0 1 0 62.5 % 8 8 0 50.0 % 8 9 0 37.5 % 9 0 0 25.0 % 8 1 0 12.5 % 8 0 0 0.0 % Preliminary Data Sheet 109 DS3, 2003-07-11 DuSLIC Operational Description 3.8.2.8 Current Offset Error Compensation The current offset error caused by the current sensor inside the SLIC can be compensated by programming the compensation registers OFR1 and OFR2 accordingly. The current offset error can be measured with the DC level meter. The following settings are necessary to accomplish this: • • • • The DuSLIC must be set into the HIRT mode by setting the bits HIR and HIT in register BCR1 to 1. In HIRT mode, the line-drivers of the SLIC are shut down and no resistors are switched to the line. As a matter of fact, no current is present in that mode, but the current sensor wrongly indicates a current flowing (current offset error). The DC path for ITRANS current level meter must be selected by setting the LM-SEL[3:0] bits in register LMCR2 to 0101 (see Table 19). The offset registers OFR1 and OFR2 must be set to 0000h. IOff-Err can be calculated like shown for “ITRANS: any other mode” in Table 22 (see the example below). The current offset error can be eliminated by programming the offset registers OFR1 and OFR2 according to the inverse value of the measured current offset error. Example: KINTDC = 1, NSamples = 256, LMValue = 0x0605 = 1541 LM Value 1541- = 0.047 LM Result = --------------------- = --------------32768 32768 79.66 mA 79.66 mA I off – Err = LM Result × ------------------------------------------------------------- = 0.047 × ------------------------- = 0.0146 mA 256 × 1 N Samples × K INTDC I Off – Err 0.0146 mA OFFSET = – ------------------------- × 32768 = – ----------------------------- × 32768 ≈ – 6 = 0xFFFA 79.66 mA 79.66 mA Short form: LM Value OFFSET = – ------------------------------------------------------------N Samples × K INTDC OFR1 = OFFSET-H = 0xFF OFR2 = OFFSET-L = 0xFA Preliminary Data Sheet 110 DS3, 2003-07-11 DuSLIC Operational Description 3.8.2.9 Loop Resistance Measurements The DC loop resistance can be determined by supplying a constant DC voltage VTR,DC to the Ring- and Tip line and measuring the DC loop current via IT pin. The following steps are necessary to accomplish this: • • • • • • Program a certain ring offset voltage RO1, RO2, RO3 (see DuSLICOS DC Control Parameter 2/4). Select ring offset voltage RNG-OFFSET[1:0] in register LMCR3 either to 01, 10 or 11. If 00 is selected, the DC regulation would be still active and would not allow resistance measurement. Choose an operation mode, either Active High (ACTH) or Ring Pause. Select the DC path for level meter by setting the bits LM-SEL[3:0] in register LMCR2 to 0101 (DC current on IT). The transversal current can be determined by reading the level meter result registers LMRES1, LMRES2. Based on the known constant output voltage VTR,DC (DC voltage according to RNG-OFFSET[1:0]) and the measured ITRANS current, the resistance can be calculated. It should be noted that the calculated resistance includes also the onboard resistors RPROT and RSTAB. In order to increase the accuracy of the result, either the current offset can be compensated or the measurement can be done differentially. The latter approach eliminates the current- and voltage offsets. Figure 45 shows an example circuit for resistance measurement: LINECARD line current sense signal to be measured IT IL ILINE RPROT + RSTAB V TR,DC * RLINE SLIC SLICOFI-2x RPROT + RSTAB DC P DC N * DC Offset Voltage according to RNG-OFFSET[1:0] Figure 45 duslic_0011_measurement_tip_ring Example Resistance Measurement Preliminary Data Sheet 111 DS3, 2003-07-11 DuSLIC Operational Description Assumption: • • • Loop resistance Rloop = 1000 Ω; Rloop = RLINE + 2*RPROT + 2*RSTAB Ring offset RO2 = 60 V (CRAM coefficient set accordingly). Ring offset RO2 is selected by setting bits RNG-OFFSET[1:0] in register LMCR3 to 10. The exact value for the Ring offset voltage can be determined from the *.res result file generated by DuSLICOS during the calculation of the appropriate coefficients. Select Active High (ACTH) mode by setting the line mode command CIDD/CIOP bits M2, M1, M0 to 010. In ACTH mode half of the ring offset voltage RO2 of e.g. 60 V will be present and applied to Ring and Tip. Sequence to determine the loop resistance Rloop differentially: • • • • Select DC level meter by setting bits LM-SEL[3:0] in register LMCR2 to 0101. Read level meter result registers LMRES1, LMRES2. Switch into reverse polarity mode by setting bit REVPOL in register BCR1 to 1. Read level meter result registers LMRES1, LMRES2. If the loop resistor connected between Ring and Tip is 1000 Ω (RLINE + RPROT + RSTAB), the expected current will be 30 mA, because the actual voltage applied to Ring and Tip is 30 V. Considering the fact that the current measurement in reverse polarity mode will also become inverted, the read results must be added. The sum of both level meter results (normal- and reverse polarity) should therefore be 60 mA current difference. Figure 46 shows the differential measurement method and the elimination of the offsets. Normal Polarity ITIP/RING expected values measured values dI VTIP/RING Offsets Ioffset Uoffset dU Reverse Polarity duslic_0008_differentially Figure 46 Differential Resistance Measurement The following calculation shows the elimination of the voltage and current offset caused by output stage and current sensor. This differential measurement method eliminates the offsets caused by the SLIC current sensor and the offset caused by the DC voltage output (Ring offset voltage). Preliminary Data Sheet 112 DS3, 2003-07-11 DuSLIC Operational Description Differential Resistance Calculation: V TR, prog + V offset I measure ( normal ) = -----------------------------------------------+ I offset R – V TR, prog + V offset - + I offset I measure ( reverse ) = --------------------------------------------------R measure ( normal ) 2 × V TR, prog – I measure ( reverse ) = ---------------------------------R 2 × V TR, prog R = ------------------------------------------------------------------------------------------- = R LINE + R PROT + R STAB I measure ( normal ) – I measure ( reverse ) 3.8.2.10 Line Resistance Tip/GND and Ring/GND The DuSLIC offers a choice of modes: either the Tip- or the Ring line or both can be set to high impedance by setting the bits HIR and HIT in register BCR1 accordingly. While one of the two lines is set to high impedance, the other line is still active and able to supply a known voltage. The transversal and/or longitudinal current can be measured and the line impedance can be calculated. Because of one line (Tip or Ring) being high impedance, there is only current flowing in either Tip or Ring line. This causes the calculated current (according Table 22) to be half the actual value. Therefore, in either HIR or HIT mode, the calculated current must be multiplied by a factor of two. 3.8.2.11 Capacitance Measurements Capacitance measurements with the DuSLIC are accomplished by using the integrated ramp generator function. The ramp generator is capable of applying a voltage ramp to the Ring- and Tip line with the flexibility of: – Programmable slopes from 30 V/s to 2000 V/s – Programmable start- and stop DC voltage offsets via ring offsets – Programmable start time of the voltage ramp after enabling the level meter function Figure 47 shows the voltage ramp and the voltage levels at the Ring and Tip line. The slope of the ramp can be programmed (refer to CRAM coefficients). The ring offset voltages RO1, RO2, and RO3 might be used as start and stop voltages. The ramp starts, for instance, at RO1 and stops at RO2. The current can be calculated as i(t) = CMeasure*dU/dt, where dU/dt is the slope and i(t) is the current that will be measured by the level meter. To accurately measure values, the integration must start after the current has settled to a constant value. This can be calculated by the time constant of the ringer load. It is recommended that the programmable ring generator delay be set higher than three times the time constant of the ringer load. When there is a resistor in parallel to the capacitor (for example, leakage), it is recommended to measure symmetrically around Preliminary Data Sheet 113 DS3, 2003-07-11 DuSLIC Operational Description the voltage zero crossing. This can be achieved by programming the ring generator delay appropriately (see DuSLICOS DC Control Parameter 2/4). The integration time for the current measurement is determined by the ring frequency (refer to CRAM coefficients, see Table 21). After the integration time, measurement stops automatically only if the bit LM-ONCE in register LMCR1 is set. Otherwise, the level meter would continuously measure the current even if the ramp is finished and turned into its constant voltage position. Because of the constant voltage, no current will flow. SLIC-E/-E2 SLIC-S/-S2 SLIC-P VHR GND TIP GND RING (VHR+VBATH )/2 VDC,Stop V DC,Start VBATR/2 TIP RING Programmable Voltage Slope VBATH VBATR Settling of line current i: Set ringer delay T RING,DELAY high enough to do the actual current measurement in the settled current range. Line Current i LMCR1: LM-EN TRING,DELAY Int. Period INTREG2: LM-OK INTREG2: READY ezm14053 Figure 47 Capacitance Measurement Preliminary Data Sheet 114 DS3, 2003-07-11 DuSLIC Operational Description Example • Assumptions: – Capacitance as object to be determined: CMeasure = 9.8 µF – Resistor RMeasure in series to CMeasure: RMeasure = 6930 Ω – τ = RMeasure*CMeasure = 67.9 ms • Calculating parameter values: – Choose Ring Offset voltage 1: RO1 = 70 V (Start voltage on Tip/Ring where the ramp should start; programmed by ring offset voltage RO1) – Choose Ring Offset voltage 2: RO2 = –30 V (End voltage on Tip/Ring where the ramp should stop; programmed by ring offset voltage RO2) – Choose slope of ramp while testing: dU/dt = 200 V/s – Time from start to stop of the ramp from RO1 to RO2 is 100 V/200 V/s = 500 ms – Time from start to zero cross is 70 V/200 V/s = 350 ms – Choose Integration time: TI = 1/fRING = 1/100 Hz = 10 ms – Measure around zero cross →from 345 ms to 355 ms – TRING,DELAY is programmed to 345 ms – Check ring generator delay: TRING,DELAY > 3*τ = 204 ms →OK! – Expected current i = CMeasure*dU/dt = 1.96 mA – Choose current for DC levelmeter current 50% full scale ILM,DC = 2 mA Note: A current of 2 mA will result in LMResult = 0.5 (half of the full scale value) Program Sequence • Set the following parameter values: Parameter Symbol & Value DuSLICOS Voltage slope of ramp generator dU/dt = 200 V/s DC Control Parameter 3/4 Ring frequency fRING = 100 Hz DC Control Parameter 2/4 Ring generator delay TRING,DELAY = 345 ms DC Control Parameter 2/4 Ring offset voltage 1 RO1 = 70 V DC Control Parameter 2/4 Ring offset voltage 2 RO2 = –30 V DC Control Parameter 2/4 DC levelmeter current 50% full scale ILM,DC = 2 mA DC Control Parameter 4/4 • • • • Integration time TI = 1/fRING = 1/100 Hz = 10 ms Select the DC level meter by setting bits LM-SEL[3:0] in register LMCR2 to 0101 Execute the level meter only once by setting bit LM-ONCE in register LMCR1 to 1. Apply Ring Offset voltage RO1 to Ring and Tip line by setting bits RNG-OFFSET[1:0] in register LMCR3 to 01. Preliminary Data Sheet 115 DS3, 2003-07-11 DuSLIC Operational Description • • Enable the ramp generator by setting bit RAMP-EN in register LMCR2 to 1. Apply Ring Offset voltage RO2 to Ring and Tip line by setting bits RNG-OFFSET[1:0] in register LMCR3 to 10. • Enable the level meter by setting bit LM-EN in register LMCR1 to 1. – Comment: The voltage ramp starts at RO1 and ramps up/down until RO2 is achieved. After the integration time, the result will be stored within LMRES1 and LMRES2 registers. • Read the result registers LMRES1 and LMRES2 The actual current ICMeasure amounts to: I CMeasure = 2 × I LM, DC × LM Result The capacitance CMeasure calculates as: I CMeasure C Measure = ------------------------dU -------dt Example: LMValue = 0x3AF2 = 15090 LMResult = 0.4605 ICMeasure = 2*2 mA*0.4605 = 1.842 mA CMeasure = 1,842 mA/200 V/s = 9.21 µF Note: To increase the accuracy an offset calibration can be performed. The voltage ramp can be applied when the line is set to high impedance by setting bits HIR and HIT in register BCR1. In this way, the offset currents can be measured and substracted later. As an alternative a rising and a falling ramp can be used to compensate current offsets. 3.8.2.12 Line Capacitance Measurements Ring and Tip to GND The voltage ramp can be applied to either line, whereas the other line is set to high impedance by setting bits HIR and HIT in register BCR1 accordingly. In this way, capacitance measurements from Ring and Tip to GND may be accomplished. Because of one line being set to high impedance, the actual line current will be twice the calculated one (multiplication by a factor of two necessary). 3.8.2.13 Foreign- and Ring Voltage Measurements The DuSLIC supports two user-programmable input/output pins (IO3, IO4) that can be used for measuring external voltages. If the pins IO3 and/or IO4 are led properly over a voltage divider to the Ring- and Tip wire, foreign voltages from external voltage sources supplied to the lines can be measured on either pin; even a differential measurement will Preliminary Data Sheet 116 DS3, 2003-07-11 DuSLIC Operational Description be supported (IO4-IO3). To select the input information that is to be taken for the measurement, set bits LM-SEL[3:0] in configuration register LMCR2 (see Table 27). Table 27 Measurement Input Selection LM-SEL[3:0] in Register LMCR2 Measurement Input 1010 Voltage on IO3 1011 Voltage on IO4 1111 Voltage IO4 – IO3 The measurement is accomplished by the DC level meter function. VCM R2 R1 FOREIGN VOLTAGE SOURCE IT IO4 IL R PROT + R STAB AC SLICOFI-2/-2S SLIC LINECARD DC RPROT + RSTAB ACN / P DCN / P R3 IO3 R4 VCM Figure 48 duslic_0009_foreign_voltage Foreign Voltage Measurement Principle Figure 48 shows the connection and external resistors used for supporting foreign voltage measurements at the Ring and Tip lines. Since the pins IO3 and IO4 support analog input functionality and are limited to a certain voltage range of VVCM ± 1.0 V (typ. 1.5 V ± 1.0 V), the values for the voltage divider must be determined according to following conditions: Preliminary Data Sheet 117 DS3, 2003-07-11 DuSLIC Operational Description • • Maximum level of the expected foreign voltages Voltage range of IO3 and IO4 = VVCM ± 1.0 V The voltage on IO3 or IO4 is measured with a reference to VCM. Hence, an input voltage of VVCM on either input pin would result into zero output value. Whereas a voltage of VVCM + 1 V would result into the negative full scale value, VVCM – 1 V would result into the positive full scale value respectively. For that reason the voltage divider must be referenced to VCM. The unknown foreign voltage VFOREIGN can be calculated as: R1 + R2 V FOREIGN = V INPUT × ---------------------- + V VCM R2 VINPUT = VIOx – VVCM (refer to Table 22) VIOx = Voltage on pins IOx (e.g. pins IO3, IO4) The resistor directly connected to either Ring or Tip (R1, R3) should be high enough so that the loop impedance will not be affected by them. Several MΩ s, such as 10 MΩ, would be a reasonable value. The following example illustrates the potential voltage range that can be measured by choosing the values as: • • R1 = R3 = 10 MΩ R2 = R4 = 47 kΩ The values given for the maximum and minimum voltage levels are: • • • VVCM = 1.5 V VINPUT,max = 1 V →VIOX,max = 2.5 V VINPUT,min = –1 V →VIOX,min = 0.5 V V FOREIGN, max V FOREIGN, min = V INPUT, = V INPUT, R1 + R2 × ---------------------- + V VCM = 215 V R2 R1 + R2 ---------------------- + V VCM = –212 V min × R2 max The voltage range would span from 215 V to –212 V. To measure small input voltages on IO3/IO4 more accurately, the integration function may be enabled by setting bit LM-EN in register LMCR1 to 1 (see Figure 40). To measure the ring voltage supplied to either Ring or Tip or even both (balanced ringing) pins via IO3 and IO4, the rectifier can be enabled by setting bit LM-RECT in register LMCR2 to 1. Preliminary Data Sheet 118 DS3, 2003-07-11 DuSLIC Operational Description 3.9 Signal Path and Test Loops The following figures show the main AC and DC signal path and the integrated analog and digital loops of the DuSLIC-E/-E2/-P and DuSLIC-S/-S2. Please note the interconnections between the AC and DC pictures of the respective chip set. 3.9.1 AC Test Loops L M -D C d L M -N O T C H L M -F IL T L M -E N AC-DLB-32K HPX2 AX-DIS LM-VAL* M U-LAW LIN LM -S E L [3 :0 ] AX2 a LM-AC 16K COX16 LPX HPX-DIS LPRX-CR FRX FRX-DIS AX1 CMP HPX1 LM 2PCM AX-DIS HPX-DIS AC-DLB-8K PCM16K *L M -V A L-H [7 :0 ] LM -V A L -L [7 :0 ] PCM OUT: Transmit Data to PCM or IOM-2 Interface TH PCM 2DC PCM16K b AR-DIS LPX -CR FRR-DIS HP R-DIS AR-DIS AR2 LPR FRR HPR AR1 COR-64 + c COR8 EXP PCM IN: P TG , TG1-E N, TG2-E N TH-DIS ITAC PD-AC-GN PD-AC-PR PD-AC-AD AC-XGAIN AC-DLB-4M + PREFI TTX Adapt. Not Programmable SWITCH Always available SWITCH Available only when bit TEST-EN = 1 TTX-12K TTX-DIS P D -T T X -A ACN/ACP AC-DLB-128K ADC HIM-AN a IM2 TTX -12K TTX -DIS OPIM_4M OPIM_AN IM3 TTX Gen. PD-AC-PO PD-AC-DA + Programmable via CRAM IM1 TG TG M U-LAW Receive Data from PCM or LIN IOM-2 Interface POFI DAC + + b IM-DIS duslic_0022_intstru_slicofi2_a Figure 49 AC Test Loops DuSLIC-E/-E2/-P/-ES/-ES2 Preliminary Data Sheet 119 DS3, 2003-07-11 DuSLIC Operational Description LM-DC d LM-NOTCH LM-FILT LM-EN AC-DLB-32K a AX2 LM-VAL* MU-LAW LIN LM-SEL[3:0] HPX2 LPX HPX-DIS AX-DIS LM-AC 16K COX16 LPRX-CR FRX FRX-DIS AX1 AX-DIS HPX1 CMP LM2PCM HPX-DIS PCM OUT: Transmit Data to PCM or IOM-2 Interface AC-DLB-8K *LM-VAL-H[7:0] LM-VAL-L[7:0] TH PCM2DC b AR-DIS LPX-CR FRR-DIS HPR-DIS AR-DIS AR2 LPR FRR HPR AR1 COR-64 PTG, TG1-EN, TG2-EN TH-DIS ITAC PD-AC-GN + PREFI TTX Adapt. Not Programmable SWITCH Always available SWITCH Available only when bit TEST-EN = 1 IM1 TTX-12K TTX-DIS PD-TTX-A ACN/ACP HIM-AN COR8 TG TG EXP MU-LAW LIN AC-DLB-128K ADC PCM IN: Receive Data from PCM or IOM-2 Interface a IM2 TTX-12K TTX-DIS OPIM_4M OPIM_AN IM3 TTX Gen. PD-AC-PO PD-AC-DA + Programmable via CRAM PD-AC-PR AC-XGAIN PD-AC-AD AC-DLB-4M + c POFI DAC + b + IM-DIS duslic_0023_intstru_slicofi2S_c Figure 50 AC Test Loops DuSLIC-S/-S2/-SE/-SE2 Preliminary Data Sheet 120 DS3, 2003-07-11 DuSLIC Operational Description 3.9.2 DC Test Loops LM-SEL[3:0] LM-EN LM-RECT *O F F S E T -H [7 :0 ] O F F S E T -L [7 :0 ] IT IL LM-DC OFFSET* IO3 RTR-SEL PD-DC-PR PD-DC-AD DC DC ADC PREFI IO4 IO4 – IO3 + Hook LP RN G -O FFSET[1:0] VDD DC Char. Offset DCN/DCP PD-DCBUF PC-POFI-HI PD-DC-DA DC BUF DC POFI DC DAC c IL PD-OVTC OFFHOOK COMP PD-GNKC Available only when bit TEST-EN = 1 + PD-OFHK Not Programmable SWITCH + PCM 2DC IT SWITCH RO1 RO1 RO1 RG DC-HOLD RAMP-EN RAMP Programmable via CRAM Always available d GNK COMP OVERT. COMP C1 C2 HV-INT. PD-HVI duslic_0022_intstru_slicofi2_b Figure 51 DC Test Loops DuSLIC Preliminary Data Sheet 121 DS3, 2003-07-11 DuSLIC Interfaces 4 Interfaces The DuSLIC offers two different interfaces to connect to a digital network: • • PCM Interface combined with a serial microcontroller interface IOM-2 Interface. The PCM/IOM-2 pin selects the interface mode. – PCM/IOM-2 = 0: IOM-2 mode. – PCM/IOM-2 = 1: PCM/µC mode. The analog TIP/RING Interface connects the DuSLIC to the subscriber. 4.1 PCM Interface with a Serial Microcontroller Interface In PCM/µC Interface mode, voice and control data are separated and handled by different pins of the SLICOFI-2x. Voice data are transferred via the PCM highways while control data are transferred using the Microcontroller Interface. 4.1.1 PCM Interface The serial PCM Interface is used to transfer A-Law or µ-Law-compressed voice data. In test mode, the PCM Interface can also transfer linear data. The eight signals of the PCM Interface are used as follows (two PCM highways): PCLK: PCM Clock, 128 kHz to 8192 kHz FSC: Frame Synchronization Clock, 8 kHz DRA: Receive Data Input for PCM Highway A DRB: Receive Data Input for PCM Highway B DXA: Transmit Data Output for PCM Highway A DXB: Transmit Data Output for PCM Highway B TCA: Transmit Control Output for PCM Highway A. Active low during transmission TCB: Transmit Control Output for PCM Highway B. Active low during transmission The FSC pulse identifies the beginning of a receive and transmit frame for both channels (see Figure 52). The PCLK clock signal synchronizes the data transfer on the DXA (DXB) and DRA (DRB) lines. On all channels, bytes are serialized with the MSB first. As a default setting, the rising edge indicates the start of the bit, while the falling edge is used to buffer the contents of the received data on DRA (DRB). If double clock rate is selected (PCLK clock rate is twice the data rate), the first rising edge indicates the start of a bit, while, by default, the second falling edge is used to buffer the contents of the data line DRA (DRB). Preliminary Data Sheet 122 DS3, 2003-07-11 DuSLIC Interfaces 125 µs FSC PCLK DRA Time Slot 0 1 2 3 Time Slot High 'Z' 31 High 'Z' DXA TCA Detail A DETAIL A: FSC Clock 0 1 2 3 4 5 6 7 PCLK Voice Data DRA Bit High 'Z' DXA 7 6 5 4 3 2 1 0 Voice Data High 'Z' TCA ezm14046 Figure 52 General PCM Interface Timing The data rate of the interface can vary from 2*128 kbit/s to 2*8192 kbit/s (two highways). A frame may consist of up to 128 time slots of 8 bits each. The time slot and PCM highway assignment for each DuSLIC channel can be programmed. Receive and transmit time slots can also be programmed individually. Preliminary Data Sheet 123 DS3, 2003-07-11 DuSLIC Interfaces When DuSLIC is transmitting data on DXA (DXB), pin TCA (TCB) is activated to control an external driving device. The DRA/B and DXA/B pins may be connected to form a bidirectional data pin for special purposes, such as for the Serial Interface Port (SIP) with the Subscriber Line Data (SLD) bus. The SLD approach provides a common interface for analog or digital per-line components. For more details, please see the ICs for Communications1) User’s Manual available on request from Infineon Technologies. Table 28 shows PCM Interface examples; other frequencies are also possible (such as 1536 kHz). Table 28 SLICOFI-2x PCM Interface Configuration Clock Rate PCLK [kHz] Single/Double Clock [1/2] Time Slots [per highway] Data Rate [kbit/s per highway] 128 1 2 128 256 2 2 128 256 1 4 256 512 2 4 256 512 1 8 512 768 2 6 384 768 1 12 768 1024 2 8 512 1024 1 16 1024 2048 2 16 1024 2048 1 32 2048 4096 2 32 2048 4096 1 64 4096 8192 2 64 4096 8192 1 128 8192 f 1 f/64 f f 2 f/128 f/2 Valid PCLK clock rates are: f = n × 64 kHz (2 ≤n ≤128) 1) Ordering No. B115-H6377-X-X-7600, published by Infineon Technologies. Preliminary Data Sheet 124 DS3, 2003-07-11 DuSLIC Interfaces transmit slope receive slope FSC Single Clock Mode PCMC1: PCLK Bit 7 Time-Slot 0 XSLOPE RSLOPE NODRIVE SHIFT 0 0 0 0 0 DBLCLK XSLOPE RSLOPE NODRIVE SHIFT 0 0 1 0 0 DBLCLK XSLOPE RSLOPE NODRIVE SHIFT 0 1 0 0 0 DBLCLK XSLOPE RSLOPE NODRIVE SHIFT 0 1 1 0 0 PCMO[2:0] 0 0 0 PCMO[2:0] 0 0 0 PCMO[2:0] 0 0 0 PCMO[2:0] 0 0 0 Double Clock Mode PCMC1: PCLK DBLCLK DBLCLK XSLOPE RSLOPE NODRIVE SHIFT 1 0 0 0 0 DBLCLK XSLOPE RSLOPE NODRIVE SHIFT 1 0 1 0 0 DBLCLK XSLOPE RSLOPE NODRIVE SHIFT 1 1 0 0 0 DBLCLK XSLOPE RSLOPE NODRIVE SHIFT 1 1 1 0 0 PCMO[2:0] 0 0 0 PCMO[2:0] 0 0 0 PCMO[2:0] 0 0 0 PCMO[2:0] 0 0 0 ezm22011 Figure 53 Setting the Slopes in Register PCMC1 Preliminary Data Sheet 125 DS3, 2003-07-11 DuSLIC Interfaces 4.1.2 Control of the Active PCM Channels The SLICOFI-2x offers additional functionality on the PCM Interface including three-party conferencing and a 16 kHz sample rate. Five configuration bits and the PCM configuration registers control the activation of the PCM transmit channels. For details of the different functions see Chapter 5.2. Table 29 gives an overview of the data transmission configuration of the PCM channels. X1L is used only when linear data are transmitted. In this case, the time slot for X1 is defined by the number X1-TS from the PCMX1 register. The time slot for X1L is defined by the number X1-TS + 1. Table 29 Active PCM Channel Configuration Bits Control Bits Transmit PCM Channel PCMXEN CONF- CONFX- PCM16K LIN EN EN X1 X1L X2 X3 X4 0 0 0 – – – – – – – 1 0 0 0 0 PCM – – – – 1 0 0 0 1 HB LB – – – 0 1 0 – – – – PCM PCM – 1 1 0 0 0 PCM – PCM PCM – 1 1 0 0 1 HB LB PCM PCM – 0 0 1 – – – – PCM PCM PCM 1 0 1 0 0 PCM – PCM PCM PCM 1 0 1 0 1 HB LB PCM PCM PCM 0 1 1 – – – – PCM PCM PCM 1 1 1 0 0 PCM – PCM PCM PCM 1 1 1 0 1 HB LB PCM PCM PCM 1 – – 1 0 DS1 – – DS2 – 1 – – 1 1 HB1 – LB1 HB2 LB2 Note: PCM means PCM-coded data (A-Law/µ-Law) HB1 and HB2, and LB1 and LB2 indicate the high byte and low byte of linearly transmitted data for an 8 kHz (16 kHz) sample rate. Note: Modes in rows with gray background are for testing purposes only. Preliminary Data Sheet 126 DS3, 2003-07-11 DuSLIC Interfaces 4.1.3 Serial Microcontroller Interface The microcontroller interface consists of four lines: CS, DCLK, DIN and DOUT. CS: A synchronization signal starting a read or write access to SLICOFI-2x. DCLK: A clock signal (up to 8.192 MHz) supplied to SLICOFI-2x. DIN: Data input carries data from the master device to the SLICOFI-2x. DOUT: Data output carries data from SLICOFI-2x to a master device. There are two different command types. Reset commands have just one byte. Read/write commands have two command bytes with the address offset information located in the second byte. A write command (see Figure 54) consists of two command bytes and the following data bytes. The first command byte determines whether the command is read or write, how the command field is to be used, and which DuSLIC channel (A or B) is written. The second command byte contains the address offset. A read command (see Figure 55) consists of two command bytes written to DIN. After the second command byte is applied to DIN, a dump-byte consisting of 1s is written to DOUT. Data transfer starts with the first byte following the ‘dump-byte’. Preliminary Data Sheet 127 DS3, 2003-07-11 DuSLIC Interfaces CS n Data Bytes write command DIN Comm 1st Comm 2nd Data Data Data Data Byte n Data Byte 1 DCLK CS Single Byte write command Comm 1st DIN ezm14057 Figure 54 Serial Microcontroller Interface Write Access Note: Serial Microcontroller Interfaces Write Access shown in Figure 54 is for n data bytes and single byte commands. CS DIN Comm 1st Comm 2nd DCLK * DOUT 'Dump Byte' Data Data Data Byte 1 Data * Data Byte n * high impedance ezm14058 Figure 55 Serial Microcontroller Interface Read Access Preliminary Data Sheet 128 DS3, 2003-07-11 DuSLIC Interfaces Programming the Microcontroller Interface Without Clocks at FSC, MCLK, PCLK The SLICOFI-2x can also be programmed via the µC Interface without any clocks connected to the FSC, MCLK, and PCLK pins. This can be useful in Power Down modes when additional power savings at the system level is necessary. In this case, a data clock of up to 1.024 MHz can be used on pin DCLK. Because the SLICOFI-2x exits the basic reset routine only if clocks at the FSC, MCLK, and PCLK pins are applied, it is not possible to program the SLICOFI-2x without any clocks at these pins directly after the hardware reset or power on reset. Note: It is necessary to first exit the basic reset routine with the clocks applied in oder to get the system running. 4.2 The IOM-2 Interface IOM-2 defines an industry-standard serial bus for interconnecting telecommunication ICs for a broad range of applications – typically ISDN-based applications. The IOM-2 bus provides a symmetrical full-duplex communication link containing data, control/programming and status channels. Providing data, control, and status information via a serial channel reduces the pin count and cost by simplifying the line card layout. The IOM-2 Interface consists of two data lines and two clock lines as follows: DU: Data Upstream carries data from the SLICOFI-2x to a master device. DD: Data Downstream carries data from the master device to the SLICOFI-2x. FSC: A Frame Synchronization Signal (8 kHz) supplied to SLICOFI-2x. DCL: A Data Clock Signal (2048 kHz or 4096 kHz) supplied to SLICOFI-2x. SLICOFI-2x handles data as described in the IOM-2 specification for analog devices. This specification is available on request from Infineon Technologies. Preliminary Data Sheet 129 DS3, 2003-07-11 DuSLIC Interfaces 125 µs FSC DCL DD TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 DU TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 Detail A Detail A DD Voice Channel A Voice Channel B Monitor Channel C/I Channel MR MX DU Voice Channel A Voice Channel B Monitor Channel C/I Channel MR MX ezm04104 Figure 56 IOM-2 I/F Timing for up to 16 Voice Channels (Per 8 kHz Frame) The information is multiplexed into frames that are transmitted at an 8 kHz rate. The frames are subdivided into eight sub-frames (see Figure 56), with one sub-frame dedicated to each transceiver or pair of codecs (in this case, each sub-frame is dedicated to two SLICOFI-2x channels). The sub-frames provide channels for data, programming, and status information for a single transceiver or codec pair. Figure 57 and Figure 58 show IOM-2 Interface timings for the two possible Data Clock (DCL) signal frequencies: Preliminary Data Sheet 130 DS3, 2003-07-11 DuSLIC Interfaces 125 µs FSC DCL 4096 kHz DD TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 DU TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 Detail B Detail B FSC DCL Bit N DD/DU Bit 0 Bit 1 ezm04105 Figure 57 IOM-2 Interface Timing (DCL = 4096 kHz, Per 8 kHz Frame) 125 µs FSC DCL 2048 kHz DD TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 DU TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 Detail C Detail C FSC DCL Bit N DD/DU Bit 0 Bit 1 ezm04106 Figure 58 IOM-2 Interface Timing (DCL = 2048 kHz, Per 8 kHz Frame) Both DuSLIC channels (see Figure 56) can be assigned to one of the eight time slots. Set the IOM-2 time slot selection as shown in Table 30 by pin-strapping. In this way, up to 16 channels can be handled with one IOM-2 Interface on the linecard. Preliminary Data Sheet 131 DS3, 2003-07-11 DuSLIC Interfaces Table 30 IOM-2 Time Slot Assignment TS2 TS1 TS0 IOM-2 Operating Mode 0 0 0 0 0 0 1 1 0 1 0 1 Time slot 0; DCL = 2048, 4096 kHz Time slot 1; DCL = 2048, 4096 kHz Time slot 2; DCL = 2048, 4096 kHz Time slot 3; DCL = 2048, 4096 kHz 1 1 1 1 0 0 1 1 0 1 0 1 Time slot 4; DCL = 2048, 4096 kHz Time slot 5; DCL = 2048, 4096 kHz Time slot 6; DCL = 2048, 4096 kHz Time slot 7; DCL = 2048, 4096 kHz 2 MHz or 4 MHz DCL is selected by the SEL24 pin: SEL24 = 0: DCL = 2048 kHz SEL24 = 1: DCL = 4096 kHz Preliminary Data Sheet 132 DS3, 2003-07-11 DuSLIC Interfaces 4.2.1 IOM-2 Interface Monitor Transfer Protocol Monitor Channel Operation The monitor channel is used for the transfer of maintenance information between two functional blocks. Using two monitor control bits (MR and MX) per direction, the data is transferred in a complete handshake procedure. The MR and MX bits in the fourth byte (C/I channel) of the IOM-2 frame are used for the handshake procedure of the monitor channel. The monitor channel transmission operates on a pseudo-asynchronous basis: Data transfer (in bits) on the bus is synchronized to Frame Sync FSC. Data flow (in bytes) is asynchronously controlled by the handshake procedure. For example: Data is placed onto the DD-Monitor-Channel by the monitor transmitter of the master device (bit DD-MX is activated: set to 0). This data transfer will be repeated within each frame (125 µs rate) until it is acknowledged by the SLICOFI-2x monitor receiver by setting the bit DU-MR to 0, which is checked by the monitor transmitter of the master device. The data rate on IOM-2 monitor channels is 4 kbits/s. MX MX Monitor Transmitter Monitor Receiver MR MR DD DU MR MR Monitor Receiver Monitor Transmitter MX MX Master Device SLICOFI-2x ezm04125 Figure 59 IOM-2 Interface Monitor Transfer Protocol Preliminary Data Sheet 133 DS3, 2003-07-11 DuSLIC Interfaces Monitor Handshake Procedure The monitor channel works in three states Idle state: A pair of inactive (set to 1) MR and MX bits during two or more consecutive frames: End of Message (EOM) Sending state: MX bit is activated (set to 0) by the monitor transmitter, together with data bytes (can be changed) on the monitor channel Acknowledging: MR bit is set to active (set to 0) by the monitor receiver, together with a data byte remaining in the monitor channel. A start of a transmission is initiated by a monitor transmitter in sending out an active MX bit together with the first byte of data (the address of the receiver) to be transmitted in the monitor channel. The monitor channel remains in this state until the addressed monitor receiver acknowledges the received data by sending out an active MR bit, which means that the data transmission is repeated each 125 µs frame (minimum is one repetition). At this time, the monitor transmitter evaluates the MR bit. Flow control can only take place when the transmitter’s MX and the receiver’s MR bit are in active state. Because the receiver is capable of receiving the monitor data at least twice (in two consecutive frames), it is able to check for data errors. If two different bytes are received, the receiver will wait for the receipt of two identical successive bytes (last look function). A collision resolution mechanism (checks if another device is trying to send data at the same time) is implemented in the transmitter. This is done by looking for the inactive (1) phase of the MX bit and making a per-bit collision check on the transmitted monitor data (check if there are transmitted 1s on DU/DD line; DU/DD line are open-drain lines). Any abort leads to a reset of the SLICOFI-2x command stack, the device is ready to receive new commands. To maximize speed during data transfers, the transmitter anticipates the falling edge of the receiver’s acknowledgment. Due to the programming structure, duplex operation is not possible. Sending any data to the SLICOFI-2x while transmission is active is not allowed. Data transfer to the SLICOFI-2x starts with a SLICOFI-2x-specific address byte (81H). Attention: Each byte on the monitor channel must be sent at least twice according to the IOM-2 Monitor handshake procedure. Preliminary Data Sheet 134 DS3, 2003-07-11 DuSLIC Interfaces MR + MXR Idle MX = 1 MR ° MXR wait MX = 1 MXR MR ° MXR abort MX = 1 initial state MR ° RQT MR 1st byte MX = 0 MR ° RQT EOM MX = 1 MR MR ° RQT nth byte ack MX = 1 MR MR MR ° RQT wait for ack MX = 0 Figure 60 MR ° RQT CLS/ABT any state State Diagram of the SLICOFI-2x Monitor Transmitter MR … MR bit received on DD line MX … MX bit calculated and expected on DU line MXR … MX bit sampled on DU line CLS … Collision within the monitor data byte on DU line RQT … Request for transmission form internal source ABT … Abort request/indication Preliminary Data Sheet 135 DS3, 2003-07-11 DuSLIC Interfaces Idle MR = 1 MX ° LL initial state MX 1st byte MX rec. MR = 0 abort MR = 1 MX ABT any state MX MX wait for LL MR = 0 MX ° LL MX ° LL byte valid MR = 0 MX ° LL MX MX MX new byte MR = 1 MX ° LL nth byte rec. MR = 1 MX ° LL wait for LL MR = 0 MX ezm04127 Figure 61 State Diagram of the SLICOFI-2x Monitor Receiver MR … MR bit calculated and transmitted on DU line MX … MX bit received data downstream (DD line) LL … Last look of monitor byte received on DD line ABT … Abort indication to internal source Preliminary Data Sheet 136 DS3, 2003-07-11 DuSLIC Interfaces Address Byte Messages to and from the SLICOFI-2x start with the following byte: Bit 4.2.2 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 1 SLICOFI-2x Identification Command For the IOM-2 Interface only, a two-byte identification command is defined for analog line IOM-2 devices to unambiguously identify different devices by software. A device requesting the identification of the SLICOFI-2x will send the following two byte code: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Each device will then respond with its specific identification code. For the SLICOFI-2x, this two byte identification code is: 4.2.3 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 Operation with IOM-2 TE Devices (1.536 MHz) The DuSLIC can be operated either in PCM/µC mode or IOM-2 mode. In case of IOM-2 mode the DuSLIC supports the standard IOM-2 data clock rates of 4.096 MHz (double clock) or 2.048 MHz (single clock). Some applications however require the IOM-2 TE mode which uses a clock rate of 1.536 MHz and a data rate of 768 kBit/s, respectively. As the IOM-2 mode of the DuSLIC doesn´t support a clock rate of 1.536 MHz, the PCM/µC mode is used: It is possible to operate the DuSLIC in PCM/µC mode at 1.536 MHz and to connect its PCM interface directly to the IOM-2 interface of the host device as shown in Figure 62. Preliminary Data Sheet 137 DS3, 2003-07-11 DuSLIC Interfaces DU DD DCLK FSC MCLK FSC PCM/IOM-2 SELCLK Other IOM-2 device 1.536 MHz mode DXA or DXB VDD DRA or DRB SLICOFI-2x PCM/µc mode Serial µController Interface PCLK µController IOM-2 Interface 1.536 MHz DCLK FSC 8 kHz DCLK/1.536 MHz DD/768 kBit/s DU/768 kBit/s FSC SLICOFI-2x DXA or DXB IOM-2 DU SLICOFI-2x DRA or DRB IOM-2 DD TS0 high imp. B1 TS1 high imp. TS2 high imp. TS3 high imp. TS4 high imp. B2 M C/I B1 IOM Channel 0 TS0 B1 TS6 high imp. TS7 high imp. TS8 high imp. B2 M C/I B1 IOM Channel 1 TS1 TS2 TS3 TS4 B2 M C/I B1 IOM Channel 0 TS5 active TS10 high imp. TS11 high imp. B2 M C/I IOM Channel 2 0 TS5 TS6 TS7 TS8 B2 M C/I B1 IOM Channel 1 TS9 high imp. TS9 TS10 TS11 B2 M C/I IOM Channel 2 0 IOM1536_768kBits_mode Figure 62 PCM/mC Mode used for IOM-2 TE Interface at 1.536 MHz As shown in Figure 62 the SLICOFI-2x is operated in PCM/µC mode. The controlling is done via the serial µC interface by a microcontroller, whereas the voice data is mapped from the PCM output of the SLICOFI-2x to the IOM-2 interface and vice versa. Special care has to be taken about the time slot counting: in the example shown in Figure 62, the PCM timeslot TS5 corresponds to the B2 channel of IOM channel 1. The SLICOFI-2x has to be programmed for PCM double clock rate (bit DBL-CLK in register PCM1). The PCM time slot (receive and transmit) can be programmed with register PCMR1 and PCMX1. As the DXA/B output of the SLICOFI-2x is only active in the selected time slot and is high impedance in other time slots, the PCM output of the SLICOFI-2x can be directly connected to the IOM-2 bus without any additional hardware (provided that the driving capability of the SLICOFI-2x is strong enough for the connected IOM-2 bus). Preliminary Data Sheet 138 DS3, 2003-07-11 DuSLIC Interfaces It has also to be considered that the SLICOFI-2x offers 3.3 V logic levels for the PCM voice data. If the driving capability or the 3.3 V level of the SLICOFI-2x are not sufficient, an external driver/levelshifter has to be used. The SLICOFI-2x offers appropriate signals for controlling an external bus driver. 4.3 TIP/RING Interface The TIP/RING Interface is the interface that connects the subscriber to the DuSLIC. It meets ITU-T Recommendation Q.552 for Z Interface and applicable LSSGR. For the performance of the TIP/RING Interface, see Chapter 6.1 and Chapter 6.2; for application circuits, see Chapter 7. Preliminary Data Sheet 139 DS3, 2003-07-11 DuSLIC SLICOFI-2x Command Structure and Programming 5 SLICOFI-2x Command Structure and Programming With the commands described in this chapter, the SLICOFI-2x can be programmed, configured, and tested very flexibly via the microcontroller interface or via the IOM-2 interface monitor channel. The command structure uses one-byte and two-byte commands to ensure a highly flexible and quick programming procedure for the most common commands. Structure of the First Command Byte The first command byte includes the R/W bit, the addresses of the different channels, and the command type. Bit RD 7 6 RD OP 5 4 3 2 1 ADR[2:0] 0 CMD[2:0] Read Data RD = 0 Write data to chip. RD = 1 Read data from chip. OP Selects the usage of the CMD field OP = 0 The CMD field works as a Command/Indication Operation (CIOP) command and acts like the M[2:0] bits located in the CIDD byte of the IOM Interface. See Table 31. . Bit 7 6 0 0 5 4 ADR[2:0] 3 2 1 0 M2 M1 M0 OP = 1 The CMD field acts as the SOP, COP, or POP command described below (microcontroller interface mode only). Preliminary Data Sheet 140 DS3, 2003-07-11 DuSLIC SLICOFI-2x Command Structure and Programming M2, M1, M0: General Operating Mode Table 31 Command/Indication Operation (CIOP) M2 M1 M0 SLICOFI-2x Operating Mode (for details see “Overview of all DuSLIC Operating Modes” on Page 74) 1 1 1 Sleep, Power Down (PDRx) 0 0 0 Power Down High Impedance (PDH) 0 1 0 Any Active mode 1 0 1 Ringing (ACTR Burst On) 1 1 0 Active with Metering 1 0 0 Ground Start 0 0 1 Ring Pause ADR[2:0] Channel address for the subsequent data ADR[2:0] = 0 0 0 Channel A ADR[2:0] = 0 0 1 Channel B (other codes reserved for future use) CMD[2:0] Command for programming the SLICOFI-2x (OP = 1) or command equivalent to the CIDD channel bits M[2:0] in microcontroller interface mode (OP = 0) The first four commands have no second command byte following. All necessary information is present in the first command byte. CMD[2:0] = 0 0 0 Soft reset of the chip (reset routine for all channels will reset all configuration registers, CRAM data is not affected). CMD[2:0] = 0 0 1 Soft reset for the specified channel A or B in ADR field CMD[2:0] = 0 1 0 Resychronization of the PCM interface (only available when pin PCM/IOM-2 = 1) CMD[2:0] = 0 1 1 Reserved for future use The second four commands are followed by a second command byte that defines additional information, such as specifying sub-addresses of the CRAM. CMD[2:0] = 1 0 0 SOP command (Status Operation; programming, and monitoring of all status-relevant data). CMD[2:0] = 1 0 1 COP command (Coefficient Operation; programming, and monitoring of all coefficients in the CRAM). Preliminary Data Sheet 141 DS3, 2003-07-11 DuSLIC SLICOFI-2x Command Structure and Programming CMD[2:0] = 1 1 0 POP command (Signal Processing Operation Programming). CMD[2:0] = 1 1 1 Reserved for production tests Structure of the Second Command Byte The second command byte specifies a particular SOP, COP, or POP command, depending on the CMD[2:0] bits of the first command byte. In the following sections, the contents of this register are described for each command group. The second command byte specifies the initial offset for the subsequent data bytes. After each data byte is transferred, the internal offset is incremented automatically. Therefore, it is possible to send a varied number of data bytes with one SOP, COP, or POP command. Writing over read-only registers will not destroy their contents. Register Description Example At the beginning of each register description, a single line gives information about: • • • • • • Offset: Offset of register address (hex) Name: Short name of the register Detailed Name: Detailed name of the register Reset Value: Value of the register after reset (hex) “hw” – value depends on specific hardware fuses Test Status: “T” – the register has no effect unless the TEST-EN bit in register LMCR1 is set to 1 Channel Selection: “N” – the register affects both SLICOFI-2x channels, “Y” – the register affects a specific SLICOFI-2x channel The line is organized as follows (with example): Offset Name Detailed Name Reset Value Test Per Channel 27H TSTR1 Test Register 1 00H T Y Preliminary Data Sheet 142 DS3, 2003-07-11 DuSLIC SLICOFI-2x Command Structure and Programming 5.1 Overview of Commands SOP STATUS OPERATION Bit 7 6 Byte 1 RD 1 5 4 ADR[2:0] Byte 2 COP 2 1 0 1 0 0 2 1 0 1 0 1 OFFSET[7:0] COEFFICIENT OPERATION Bit 7 6 Byte 1 RD 1 5 4 3 ADR[2:0] Byte 2 POP 3 OFFSET[7:0] POP OPERATION (only SLICOFI-2 PEB 3265 used for DuSLIC-E/-E2/-P) Bit 7 6 Byte 1 RD 1 Byte 2 Preliminary Data Sheet 5 4 3 ADR[2:0] 2 1 0 1 1 0 OFFSET[7:0] 143 DS3, 2003-07-11 DuSLIC 5.2 SLICOFI-2 Command Structure and Programming This section describes only the SLICOFI-2 PEB 3265 command structure and programming. 5.2.1 SOP Command The Status Operation (SOP) command provides access to the configuration and status registers of the SLICOFI-2. Common registers change the mode of the entire SLICOFI-2 chip. All other registers are channel-specific. It is possible to access single or multiple registers. Multiple register access is achieved by an automatic offset increment. Write access to read-only registers is ignored and does not abort the command sequence. Offsets may change in future versions of the SLICOFI-2. Attention: To ensure proper functionality, it is essential that all unused register bits have to be filled with zeros. 5.2.1.1 00H SOP Register Overview REVISION Revision Number (read-only) REV[7:0] 01H CHIPID 1 Chip Identification 1 (read-only) for internal use only 02H CHIPID 2 Chip Identification 2 (read-only) for internal use only 03H CHIPID 3 Chip Identification 3 (read-only) for internal use only 04H FUSE1 Fuse Register 1 for internal use only 05H PCMC1 DBL-CLK PCM Configuration Register 1 X-SLOPE Preliminary Data Sheet R-SLOPE NO-DRIVE-0 144 SHIFT PCMO[2:0] DS3, 2003-07-11 DuSLIC 06H XCR EDSP-EN 07H Extended Configuration Register ASYNCH-R INTREG1 HOOK INTREG2 GNDK READY INTREG3 0BH ICON VTRLIM LM-OK OTEMP SYNC-FAIL IO[4:1]-DU DTMF-KEY[4:0] UTDR-OK UTDX-OK Interrupt Register 4 (read-only) 0 CHKR1 0 0 CIS-BOF CHKR2 CIS-BUF CIS-REQ CIS-ACT Checksum Register 1 (High Byte) (read-only) SUM-OK 0CH 0 Interrupt Register 3 (read-only) INTREG4 EDSP-FAIL GNKP RSTAT DTMF-OK 0AH 0 Interrupt Register 2 (read-only) LM-THRES 09H 0 Interrupt Register 1 (read-only) INT-CH 08H 0 CHKSUM-H[6:0] Checksum Register 2 (Low Byte) (read-only) CHKSUM-L[7:0] 0DH LMRES1 Level Metering Result 1 (High Byte) (read-only) LM-VAL-H[7:0] 0EH LMRES2 Level Metering Result 2 (Low Byte) (read-only) LM-VAL-L[7:0] 0FH FUSE2 Fuse Register 2 for internal use only 10H FUSE3 Fuse Register 3 for internal use only Preliminary Data Sheet 145 DS3, 2003-07-11 DuSLIC 11H MASK READY-M 12H Mask Register HOOK-M IOCTL1 GNDK-M GNKP-M ICON-M VTRLIM-M IOCTL2 IO[4:1]-M I/O Control Register 2 IO[4:1]-OEN 14H IOCTL3 IO[4:1]-DD I/O Control Register 3 DUP[3:0] 15H BCR1 17H HIT BCR2 REXT-EN SOFT-DIS BCR3 19H 1AH LIN TTX-DIS ACTL HIM-AN AC-XGAIN UTDX-SRC PDOT-DIS CONFX-EN CONF-EN LPRX-CR CRAM-EN FRX-DIS FRR-DIS HPX-DIS HPR-DIS LEC-OUT LEC-EN DTMF-SRC DTMF-EN COR8 PTG TG2-EN TG1-EN 0 0 0 0 TTX-12K PCM16K PCMX-EN IM-DIS AX-DIS AR-DIS SEL-SLIC[1:0] Basic Configuration Register 5 UTDX-EN DSCR CIS-AUTO CIS-EN DTMF Sender Configuration Register DG-KEY[3:0] 1BH ACTR Basic Configuration Register 4 BCR5 -EN REVPOL Basic Configuration Register 3 BCR4 TH-DIS SLEEP-EN Basic Configuration Register 2 MU-LAW 18H DUP-IO[3:0] Basic Configuration Register 1 HIR 16H SYNC-M I/O Control Register 1 IO[4:1]-INEN 13H OTEMP-M Reserved 0 Preliminary Data Sheet 0 0 0 146 DS3, 2003-07-11 DuSLIC 1CH LMCR1 TEST-EN Level Metering Configuration Register 1 LM-EN LM-THM PCM2DC LM2 LM-ONCE LM-MASK DC-AD16 PCM 1DH LMCR2 LM-NOTCH 1EH LM-FILT LMCR3 AC-SHORTEN 1FH Level Metering Configuration Register 2 LM-RECT RAMP-EN LM-SEL[3:0] Level Metering Configuration Register 3 RTR-SEL OFR1 LM-ITIME[3:0] RNG-OFFSET[1:0] Offset Register 1 (High Byte) OFFSET-H[7:0] 20H OFR2 Offset Register 2 (Low Byte) OFFSET-L[7:0] 21H PCMR1 PCM Receive Register 1 R1-HW 22H PCMR2 R1-TS[6:0] PCM Receive Register 2 R2-HW 23H PCMR3 R2-TS[6:0] PCM Receive Register 3 R3-HW 24H PCMR4 R3-TS[6:0] PCM Receive Register 4 R4-HW 25H PCMX1 R4-TS[6:0] PCM Transmit Register 1 X1-HW Preliminary Data Sheet X1-TS[6:0] 147 DS3, 2003-07-11 DuSLIC 26H PCMX2 PCM Transmit Register 2 X2-HW 27H X2-TS[6:0] PCMX3 PCM Transmit Register 3 X3-HW 28H X3-TS[6:0] PCMX4 PCM Transmit Register 4 X4-HW 29H TSTR1 PD-AC-PR 2AH X4-TS[6:0] Test Register 1 PD-AC-PO TSTR2 0 TSTR3 2DH 0 TSTR4 OPIM-AN PD-AC-GN PD-GNKC PD-OFHC PD-OVTC PD-DC-AD PD-DC-DA PD-DCBUF 0 PD-TTX-A PD-HVI AC-DLB128K AC-DLB32K AC-DLB8K 0 0 COX-16 0 0 0 0 DC-POFIHI DC-HOLD 0 0 0 Test Register 3 0 2CH PD-AC-DA Test Register 2 PD-DC-PR 2BH PD-AC-AD AC-DLB-4M Test Register 4 OPIM-4M TSTR5 0 Preliminary Data Sheet COR-64 Test Register 5 0 0 148 DS3, 2003-07-11 DuSLIC 5.2.1.2 00H SOP Register Description REVISION Bit 7 Revision Number (read-only) 6 5 4 curr. rev. 3 2 N 1 0 REV[7:0] REV[7:0] Current revision number of the SLICOFI-2. 01H Bit CHIPID 1 7 Chip Identification 1 (read-only) 6 5 4 hw 3 2 N 1 0 for internal use only 02H Bit CHIPID 2 7 Chip Identification 2 (read-only) 6 5 4 hw 3 2 N 1 0 for internal use only 03H Bit CHIPID 3 7 Chip Identification 3 (read-only) 6 5 4 hw 3 2 N 1 0 for internal use only 04H Bit FUSE1 7 Fuse Register 1 6 hw 5 4 3 2 N 1 0 for internal use only Preliminary Data Sheet 149 DS3, 2003-07-11 DuSLIC 05H PCMC1 Bit 7 PCM Configuration Register 1 6 5 4 DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 DBL-CLK X-SLOPE R-SLOPE NODRIVE-0 SHIFT 00H 3 SHIFT N 2 1 0 PCMO[2:0] Clock mode for the PCM interface (see Figure 53 on Page 125) DBL-CLK = 0 Single-clocking is used. DBL-CLK = 1 Double-clocking is used. Transmit slope (see Figure 53 on Page 125) X-SLOPE = 0 Transmission starts with rising edge of the clock. X-SLOPE = 1 Transmission starts with falling edge of the clock. Receive slope (see Figure 53 on Page 125) R-SLOPE = 0 Data is sampled with falling edge of the clock. R-SLOPE = 1 Data is sampled with rising edge of the clock. Driving mode for bit 0 (only available in single-clocking mode). NO-DRIVE = 0 Bit 0 is driven the entire clock period. NO-DRIVE = 1 Bit 0 is driven during the first half of the clock period only. Shifts the access edges by one clock cycle in double-clocking mode. SHIFT = 0 No shift takes place. SHIFT = 1 Shift takes place. PCMO[2:0] All PCM timing is moved by PCMO data periods against the FSC signal. PCMO[2:0] = 0 0 0 No offset is added. PCMO[2:0] = 0 0 1 One data period is added. … PCMO[2:0] = 1 1 1 Preliminary Data Sheet Seven data periods are added. 150 DS3, 2003-07-11 DuSLIC 06H Bit XCR Extended Configuration Register 7 6 EDSPEN EDSP-EN 5 ASYNC H-R 4 0 3 0 00H 2 0 N 1 0 0 Enables the Enhanced Digital Signal Processor EDSP. EDSP-EN = 0 Enhanced Digital Signal Processor is switched off. EDSP-EN = 1 Enhanced Digital Signal Processor is switched on. ASYNCH-R Enables asynchronous ringing in case of internal or external ringing. ASYNCH-R = 0 Internal or external ringing with zero crossing selected. ASYNCH-R = 1 Asynchronous ringing selected. Note: When internal ringing is used, the ringing signal can be turned off without waiting for zero crossing. Preliminary Data Sheet 151 DS3, 2003-07-11 DuSLIC 07H Bit INT-CH HOOK GNDK GNKP INTREG1 Interrupt Register 1 (read-only) 7 6 5 4 3 INT-CH HOOK GNDK GNKP ICON 80H 2 Y 1 VTRLIM OTEMP 0 SYNCFAIL Interrupt channel bit. This bit indicates that the corresponding channel caused the last interrupt. Will be automatically set to zero after all interrupt registers were read. INT-CH = 0 No interrupt in corresponding channel. INT-CH = 1 Interrupt caused by corresponding channel. Indicates on-hook or off-hook for the loop in all operating modes (via the ITx pin); filtered by the DUP (Data Upstream Persistence) counter and interrupt generation masked by the HOOK-M bit. Indicates ground start in case of ground start mode is selected. A change of this bit generates an interrupt. HOOK = 0 On-hook. HOOK = 1 Off-hook detected. Indicates ground key information in all active modes via the IL pin; filtered for AC suppression by the DUP counter and interrupt generation masked by the GNDK-M bit. A change of this bit generates an interrupt. GNDK = 0 No ground key indicated. GNDK = 1 Ground key indication; longitudinal current (threshold 17 mA) detected. Ground key polarity. Indicating the active Ground Key level (positive/negative) interrupt generation masked by the GNKP-M bit. A change of this bit generates an interrupt. This bit can be used to obtain information about interference voltage influence. GNKP = 0 Negative ground key threshold level active. GNKP = 1 Positive ground key threshold level active. Preliminary Data Sheet 152 DS3, 2003-07-11 DuSLIC ICON VTRLIM OTEMP Constant current information. Filtered by DUP-IO counter and interrupt generation masked by the ICON-M bit. A change of this bit generates an interrupt. ICON = 0 Resistive or constant voltage feeding. ICON = 1 Constant current feeding. Exceeding of a programmed voltage threshold for the TIP/RING voltage, filtered by the DUP-IO counter and interrupt generation masked by the VTRLIM-M bit. A change of this bit causes an interrupt. The voltage threshold for the TIP/RING voltage is set in CRAM (calculated with DuSLICOS DC Control Parameter 2/4: Tip-Ring Threshold). VTRLIM = 0 Voltage at Tip/Ring is below the limit. VTRLIM = 1 Voltage at Tip/Ring is above the limit. Thermal overload warning from the SLIC-E/-E2/-P line drivers masked by the OTEMP-M bit. An interrupt is only generated if the OTEMP bit changes from 0 to1. OTEMP = 0 Temperature at SLIC-E/-E2/-P is below the limit. OTEMP = 1 Temperature at SLIC-E/-E2/-P is above the limit. In case of bit PDOT-DIS = 0 (register BCR2) the DuSLIC is switched automatically into PDH mode and OTEMP is hold at 1 until the SLICOFI-2 is set to PDH by a CIOP/CIDD command. SYNC-FAIL Failure of the Synchronization of the IOM-2/PCM interface. An interrupt is only generated if the SYNC-FAIL bit changes from 0 to1. Resynchronization of the PCM interface can be done with the Resynchronization command (see Chapter 5) SYNC-FAIL = 0 Synchronization OK. SYNC-FAIL = 1 Synchronization failure. Preliminary Data Sheet 153 DS3, 2003-07-11 DuSLIC 08H INTREG2 Bit 7 Interrupt Register 2 (read-only) 6 5 LMREADY RSTAT THRES 4 3 LM-OK 20H 2 Y 1 0 IO[4:1]-DU After a hardware reset, the RSTAT bit is set and generates an interrupt. Therefore the default value of INTREG2 is 20H. After reading all four interrupt registers, the INTREG2 value changes to 4FH. LM-THRES Indication whether the level metering result is above or below the threshold set by the CRAM coefficients LM-THRES = 0 Level metering result is below threshold. LM-THRES = 1 Level metering result is above threshold. READY RSTAT LM-OK IO[4:1]-DU Indication whether the ramp generator has finished. An interrupt is only generated if the READY bit changes from 0 to 1. Upon a new start of the ramp generator, the bit is set to 0. For further information regarding soft reversal see Chapter 2.7.2.1. READY = 0 Ramp generator active. READY = 1 Ramp generator not active. Hardware reset status since last interrupt. RSTAT = 0 No hardware reset has occurred since the last interrupt. RSTAT = 1 Hardware reset has occurred since the last interrupt. Level metering sequence has finished. An interrupt is only generated if the LM-OK bit changes from 0 to 1. LM-OK = 0 Level metering result not ready. LM-OK = 1 Level metering result ready. Data on I/O pins 1 to 4 filtered by DUP-IO counter and interrupt generation masked by the IO[4:1]-DU-M bits. A change of any of this bits generates an interrupt. Preliminary Data Sheet 154 DS3, 2003-07-11 DuSLIC 09H INTREG3 Bit Interrupt Register 3 (read-only) 7 6 5 DTMFOK DTMF-OK 4 00H 3 2 DTMF-KEY[4:0] Y 1 0 UTDROK UTDXOK Indication of a valid DTMF Key by the DTMF receiver. A change of this bit generates an interrupt. DTMF-OK = 0 No valid DTMF Key was encountered by the DTMF receiver. DTMF-OK = 1 A valid DTMF Key was encountered by the DTMF receiver. DTMF-KEY[4:0] Valid DTMF keys decoded by the DTMF receiver. Table 32 Valid DTMF Keys (Bit DTMF-KEY4 = 1) fLOW [Hz] fHIGH [Hz] DIGIT DTMFKEY4 DTMFKEY3 DTMFKEY2 DTMFKEY1 DTMFKEY0 697 1209 1 1 0 0 0 1 697 1336 2 1 0 0 1 0 697 1477 3 1 0 0 1 1 770 1209 4 1 0 1 0 0 770 1336 5 1 0 1 0 1 770 1477 6 1 0 1 1 0 852 1209 7 1 0 1 1 1 852 1336 8 1 1 0 0 0 852 1477 9 1 1 0 0 1 941 1336 0 1 1 0 1 0 941 1209 * 1 1 0 1 1 941 1477 # 1 1 1 0 0 697 1633 A 1 1 1 0 1 770 1633 B 1 1 1 1 0 Preliminary Data Sheet 155 DS3, 2003-07-11 DuSLIC Table 32 Valid DTMF Keys (Bit DTMF-KEY4 = 1) (cont’d) fLOW [Hz] fHIGH [Hz] DIGIT DTMFKEY4 DTMFKEY3 DTMFKEY2 DTMFKEY1 DTMFKEY0 852 1633 C 1 1 1 1 1 941 1633 D 1 0 0 0 0 UTDR-OK UTDX-OK Universal Tone Detection Receive (such as Fax/Modem tones) UTDR-OK = 0 No specific tone signal was detected. UTDR-OK = 1 A specific tone signal was detected. Universal Tone Detection Transmit (such as Fax/Modem tones) UTDX-OK = 0 No specific tone signal was detected. UTDX-OK = 1 A specific tone signal was detected. Preliminary Data Sheet 156 DS3, 2003-07-11 DuSLIC 0AH INTREG4 Bit Interrupt Register 4 (read-only) 00H Y 7 6 5 4 3 2 1 0 EDSPFAIL 0 0 0 CISBOF CISBUF CISREQ CISACT EDSP-FAIL Indication of a malfunction of the Enhanced Digital Signal Processor EDSP. EDSP-FAIL = 0 Enhanced Digital Signal Processor EDSP normal operation. EDSP-FAIL = 1 Enhanced Digital Signal Processor EDSP failure. It is necessary to restart this DSP with bit EDSP-EN in the XCR register set. CIS-BOF CIS-BUF Caller ID buffer overflow. An interrupt is only generated if the CIS-BOF bit changes from 0 to 1. CIS-BOF = 0 Not data buffer overflow has occurred. CIS-BOF = 1 Too many bytes have been written to the data buffer for Caller ID generation. Caller ID generation is aborted and the buffer is cleared. Caller ID buffer underflow. An interrupt is only generated if the CIS-BUF bit changes from 0 to 1. CIS-BUF = 0 Data buffer for Caller ID generation is filled. CIS-BUF = 1 Data buffer for Caller ID generation is empty (underflow). Preliminary Data Sheet 157 DS3, 2003-07-11 DuSLIC CIS-REQ CIS-ACT Caller ID data request. An interrupt is only generated if the CIS-REQ bit changes from 0 to 1. CIS-REQ = 0 Caller ID data buffer requests no data. CIS-REQ = 1 Caller ID data buffer requests more data to transmit, when the amount of data stored in the buffer is less than the buffer request size. Caller ID generator active. This is a status bit only. No interrupt will be generated. CIS-ACT = 0 Caller ID generator is not active. CIS-ACT = 1 Caller ID generator is active. Preliminary Data Sheet 158 DS3, 2003-07-11 DuSLIC 0BH CHKR1 Bit Checksum Register 1 (High Byte) (read-only) 7 6 5 4 SUMOK SUM-OK 3 00H 2 Y 1 0 CHKSUM-H[6:0] Information about the validity of the checksum. The checksum is valid if the internal checksum calculation is finished. Checksum calculation: For (cram_adr = 0 to 159) do cram_dat = cram[cram_adr] csum[14:0] = (csum[13:0] &1) ‘0’) xor (‘0000000’ & cram_dat[7:0]) xor (‘0000000000000’ & csum[14] & csum[14]) End SUM-OK = 0 CRAM checksum is not valid. SUM-OK = 1 CRAM checksum is valid. 1) “&” means a concatenation; not the logic operation CHKSUM-H[6:0] 0CH Bit CRAM checksum High Byte CHKR2 Checksum Register 2 (Low Byte) (read-only) 7 6 5 4 3 00H 2 Y 1 0 CHKSUM-L[7:0] CHKSUM-L[7:0] CRAM checksum Low Byte Preliminary Data Sheet 159 DS3, 2003-07-11 DuSLIC 0DH Bit LMRES1 7 Level Metering Result 1 (High Byte) (read-only) 6 5 4 3 00H 2 Y 1 0 LM-VAL-H[7:0] LM-VAL-H[7:0] 0EH Bit LMRES2 7 LM result High Byte (selected by the LM-SEL bits in the LMCR2 register) Level Metering Result 2 (Low Byte) (read-only) 6 5 4 3 00H 2 Y 1 0 LM-VAL-L[7:0] LM-VAL-L[7:0] 0FH Bit FUSE2 7 LM result Low Byte (selected by the LM-SEL bits in the LMCR2 register) Fuse Register 2 6 5 hw 4 3 2 Y 1 0 for internal use only 10H Bit FUSE3 7 Fuse Register 3 6 5 hw 4 3 2 Y 1 0 for internal use only Preliminary Data Sheet 160 DS3, 2003-07-11 DuSLIC 11H MASK Bit Mask Register FFH 7 6 5 4 3 READY -M HOOK -M GNDK -M GNKP -M ICON -M 2 Y 1 VTRLIM OTEMP -M -M 0 SYNC -M The mask bits in the mask register only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers is updated to show the current status of the corresponding event. READY-M HOOK-M GNDK-M GNKP-M ICON-M Mask bit for Ramp Generator READY bit READY-M = 0 An interrupt is generated if the READY bit changes from 0 to 1. READY-M = 1 Changes of the READY bit do not generate interrupts. Mask bit for Off-hook Detection HOOK bit HOOK-M = 0 Each change of the HOOK bit generates an interrupt. HOOK-M = 1 Changes of the HOOK bit do not generate interrupts. Mask bit for ground key detection GNDK bit GNDK-M = 0 Each change of the GNDK bit generates an interrupt. GNDK-M = 1 Changes of the GNDK bit do not generate interrupts. Mask bit for ground key level GNKP bit GNKP-M = 0 Each change of the GNKP bit generates an interrupt. GNKP-M = 1 Changes of the GNKP bit do not generate interrupts. Mask bit for Constant Current Information ICON bit ICON-M = 0 Each change of the ICON bit generates an interrupt. ICON-M = 1 Changes of the ICON bit do not generate interrupts. VTRLIM-M Mask bit for Programmed Voltage Limit VTRLIM bit VTRLIM-M = 0 Each change of the VTRLIM bit generates an interrupt. VTRLIM-M = 1 Changes of the VTRLIM bit do not generate interrupts. Preliminary Data Sheet 161 DS3, 2003-07-11 DuSLIC OTEMP-M Mask bit for Thermal Overload Warning OTEMP bit SYNC-M OTEMP-M = 0 A change of the OTEMP bit from 0 to 1 generates an interrupt. OTEMP-M = 1 A change of the OTEMP bit from 0 to 1 does not generate interrupts. Mask bit for Synchronization Failure SYNC-FAIL bit SYNC-M = 0 A change of the SYNC-FAIL bit from 0 to 1 generates an interrupt. SYNC-M = 1 A change of the SYNC-FAIL bit from 0 to 1 does not generate interrupts. Preliminary Data Sheet 162 DS3, 2003-07-11 DuSLIC 12H IOCTL1 Bit I/O Control Register 1 7 6 5 4 0FH 3 IO[4:1]-INEN 2 Y 1 0 IO[4:1]-M The mask bits IO[4:1]-M only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers is updated to show the current status of the corresponding event. IO4-INEN Input enable for programmable I/O pin IO4 IO4-INEN = 0 Input Schmitt trigger of pin IO4 is disabled. IO4-INEN = 1 Input Schmitt trigger of pin IO4 is enabled. IO3-INEN Input enable for programmable I/O pin IO3 IO3-INEN = 0 Input Schmitt trigger of pin IO3 is disabled. IO3-INEN = 1 Input Schmitt trigger of pin IO3 is enabled. IO2-INEN Input enable for programmable I/O pin IO2 IO2-INEN = 0 Input Schmitt trigger of pin IO2 is disabled. IO2-INEN = 1 Input Schmitt trigger of pin IO2 is enabled. IO1-INEN Input enable for programmable I/O pin IO1 IO1-INEN = 0 Input Schmitt trigger of pin IO1 is disabled. IO1-INEN = 1 Input Schmitt trigger of pin IO1 is enabled. IO4-M IO3-M Mask bit for IO4-DU bit IO4-M = 0 Each change of the IO4 bit generates an interrupt. IO4-M = 1 Changes of the IO4 bit do not generate interrupts. Mask bit for IO3-DU bit IO3-M = 0 Each change of the IO3 bit generates an interrupt. IO3-M = 1 Changes of the IO3 bit do not generate interrupts. Preliminary Data Sheet 163 DS3, 2003-07-11 DuSLIC IO2-M IO1-M Mask bit for IO2-DU bit IO2-M = 0 Each change of the IO2 bit generates an interrupt. IO2-M = 1 Changes of the IO2 bit do not generate interrupts. Mask bit for IO1-DU bit IO1-M = 0 Each change of the IO1 bit generates an interrupt. IO1-M = 1 Changes of the IO1 bit do not generate interrupts. Preliminary Data Sheet 164 DS3, 2003-07-11 DuSLIC 13H IOCTL2 Bit 7 I/O Control Register 2 6 5 4 IO[4:1]-OEN IO4-OEN IO3-OEN IO2-OEN IO1-OEN IO4-DD IO3-DD 00H 3 2 Y 1 0 IO[4:1]-DD Enabling output driver of the IO4 pin IO4-OEN = 0 The output driver of the IO4 pin is disabled. IO4-OEN = 1 The output driver of the IO4 pin is enabled. Enabling output driver of the IO3 pin IO3-OEN = 0 The output driver of the IO3 pin is disabled. IO3-OEN = 1 The output driver of the IO3 pin is enabled. Enabling output driver of the IO2 pin. If SLIC-P is selected (bits SEL-SLIC [1:0] in register BCR1 set to 01), pin IO2 cannot be controlled by the user but is utilized by the SLICOFI-2 to control the C3 input of SLIC-P. IO2-OEN = 0 The output driver of the IO2 pin is disabled. IO2-OEN = 1 The output driver of the IO2 pin is enabled. Enabling output driver of the IO1 pin. If external ringing is selected (bit REXT-EN in register BCR2 set to 1), pin IO1 cannot be controlled by the user but is utilized by the SLICOFI-2 to control the ring relay. IO1-OEN = 0 The output driver of the IO1 pin is disabled. IO1-OEN = 1 The output driver of the IO1 pin is enabled. Value for the programmable I/O pin IO4 if programmed as an output pin. IO4-DD = 0 The corresponding pin is driving a logic 0. IO4-DD = 1 The corresponding pin is driving a logic 1. Value for the programmable I/O pin IO3 if programmed as an output pin. IO3-DD = 0 The corresponding pin is driving a logic 0. IO3-DD = 1 The corresponding pin is driving a logic 1. Preliminary Data Sheet 165 DS3, 2003-07-11 DuSLIC IO2-DD Value for the programmable I/O pin IO2 if programmed as an output pin. IO1-DD 14H IO2-DD = 0 The corresponding pin is driving a logic 0. IO2-DD = 1 The corresponding pin is driving a logic 1. Value for the programmable I/O pin IO1 if programmed as an output pin. IO1-DD = 0 The corresponding pin is driving a logic 0. IO1-DD = 1 The corresponding pin is driving a logic 1. IOCTL3 Bit I/O Control Register 3 7 6 5 94H 4 3 DUP[3:0] DUP[3:0] 2 Y 1 0 DUP-IO[3:0] Data Upstream Persistence Counter end value. Restricts the rate of interrupts generated by the HOOK bit in the interrupt register INTREG1. The interval is programmable from 1 to 16 ms in steps of 1 ms (reset value is 10 ms). The DUP[3:0] value affects the blocking period for ground key detection (see Chapter 2.6). DUP[3:0] HOOK Active, Ringing HOOK Power Down GNDK GNDK fmin,ACsup1) 0000 1 2 ms 4 ms 125 Hz 0001 2 4 ms 8 ms 62.5 Hz 16 32 ms 64 ms 7.8125 Hz ... 1111 1) Minimum frequency for AC suppression. DUP-IO[3:0] Data Upstream Persistence Counter end value for • the I/O pins when used as digital input pins. • the bits ICON and VTRLIM in register INTREG1. The interval is programmable from 0.5 to 60.5 ms in steps of 4 ms (reset value is 16.5 ms). Preliminary Data Sheet 166 DS3, 2003-07-11 DuSLIC 15H Bit HIR HIT BCR1 Basic Configuration Register 1 7 6 HIR HIT 5 4 00H 3 SLEEP- REVPOL ACTR EN 2 ACTL Y 1 0 SEL-SLIC[1:0] This bit modifies different basic modes. In ringing mode, an unbalanced ringing on the RING wire (ROR) is enabled. In Active mode, high impedance on the RING wire is activated (HIR). If the HIT bit is set in addition to the HIR bit, the HIRT mode is activated. HIR = 0 Normal operation (ringing mode). HIR = 1 Controls SLIC-E/-E2/-P interface and sets the RING wire to high impedance (Active mode). This bit modifies different basic modes. In ringing mode, an unbalanced ringing on the TIP wire (ROT) is enabled. In Active mode, high impedance on the TIP wire is performed (HIT). If the HIR bit is set in addition to the HIT bit, the HIRT mode is activated. HIT = 0 Normal operation (ringing mode). HIT = 1 Controls SLIC-E/-E2/-P interface and sets the TIP wire to high impedance (Active mode). SLEEP-EN Enables Sleep mode of the DuSLIC channel. Valid only in the Power Down mode of the SLICOFI-2. SLEEP-EN = 0 Sleep mode is disabled. SLEEP-EN = 1 Sleep mode is enabled. Note: SLEEP-EN has to be set before entering the Power Down mode. REVPOL Reverses the polarity of DC feeding REVPOL = 0 Normal polarity. REVPOL = 1 Reverse polarity. Preliminary Data Sheet 167 DS3, 2003-07-11 DuSLIC ACTR ACTL Selection of extended battery feeding in Active mode. Also changes the voltage in Power Down Resistive mode for SLIC-P. In this case, VBATR for SLIC-P and VHR – VBATH for SLIC-E/-E2 is used. ACTR = 0 No extended battery feeding selected. ACTR = 1 Extended battery feeding selected. Selection of the low battery supply voltage VBATL on SLIC-E/-E2/-P if available. Valid only in the Active mode of the SLICOFI-2. ACTL = 0 Low battery supply voltage on SLIC-E/-E2/-P is not selected. ACTL = 1 Low battery supply voltage on SLIC-E/-E2/-P is selected. SEL-SLIC[1:0] Selection of the current SLIC type used. For SLIC-E/-E2 and SLIC-P, the appropriate predefined mode table has to be selected. SEL-SLIC[1:0] = 0 0 SLIC-E/-E2 selected. SEL-SLIC[1:0] = 0 1 SLIC-P selected. SEL-SLIC[1:0] = 1 0 SLIC-P selected for extremely power sensitive applications. SEL-SLIC[1:0] = 1 1 Reserved for future use. Preliminary Data Sheet 168 DS3, 2003-07-11 DuSLIC For SLIC-P two selections are possible. • The standard SLIC-P selection automatically uses the IO2 pin of the SLICOFI-2 to control the C3 pin of the SLIC-P. By using pin C3 as well as the pins C1 and C2, all possible operating modes of the SLIC-P V1.1 can be selected. For SLIC-P V1.2 only the operating modes with 90 mA current limitation can be selected (ACTL90, ACTH90, ACTR90). Note: If with SLIC-P V1.2 the 60 mA current limitation modes (ACTL60, ACTH60, ACTR60) are to be used, then the SLIC type SEL-SLIC[1:0] = 10 has to be programmed. In this case the C3 pin of the SLIC-P V1.2 can also be controlled by the IO2 pin of the SLICOFI-2. However, the IO2 pin has then to be programmed manually by the user according to the SLIC-P V1.2 interface code table. • For extremely power sensitive applications using external ringing with SLIC-P SEL-SLIC[1:0] = 10 should be chosen. In this case, internal unbalanced ringing is not needed and therefore there is no need to switch the C3 pin of the SLIC-P to 'High'. The C3 pin of the SLIC-P must be connected to GND and the IO2 pin of the SLICOFI-2 is programmable by the user. There is no need for a high battery voltage for ringing either. This mode uses VBATR for the on-hook voltage (e.g. –48 V) in Power Down Resistive (PDR) mode and the other battery supply voltages (e.g. VBATH = –24 V and VBATL = –18 V) can be used for the off-hook state. This will help to save power because the lowest possible battery voltage can be selected (see DuSLIC Voltage and Power Application Note). Preliminary Data Sheet 169 DS3, 2003-07-11 DuSLIC 16H BCR2 Bit 00H Y 7 6 5 4 3 2 1 0 REXTEN SOFTDIS TTXDIS TTX12K HIM-AN ACXGAIN UTDXSRC PDOTDIS REXT-EN SOFT-DIS TTX-DIS TTX-12K HIM-AN Basic Configuration Register 2 Enables the use of an external ring signal generator. Synchronization is done via the RSYNC pin and the Ring Burst Enable signal is transferred via the IO1 pin. REXT-EN = 0 External ringing is disabled. REXT-EN = 1 External ringing enabled. Polarity soft reversal (to minimize noise on DC feeding) SOFT-DIS = 0 Polarity soft reversal active. SOFT-DIS = 1 Polarity hard reversal. Disables the generation of TTX bursts for metering signals. If TTX bursts are disabled, reverse polarity will be used instead. TTX-DIS = 0 TTX bursts are enabled. TTX-DIS = 1 TTX bursts are disabled, reverse polarity used. Selection of TTX frequencies TTX-12K = 0 Selects 16 kHz TTX signals instead of 12 kHz signals. TTX-12K = 1 12 kHz TTX signals. Higher impedance in analog impedance matching loop. The value of this bit must correspond to the selection done in the DUSLICOS tool when calculating the coefficients. If the coefficients are calculated with standard impedance in analog impedance matching loop, HIM-AN must be set to 0; if the coefficients are calculated with high impedance in analog impedance matching loop, HIM-AN must be set to 1. HIM-AN = 0 Standard impedance in analog impedance matching loop HIM-AN = 1 High impedance in analog impedance matching loop Preliminary Data Sheet 170 DS3, 2003-07-11 DuSLIC AC-XGAIN Analog gain in transmit direction (should be set to zero). UTDX-SRC AC-XGAIN = 0 No additional analog gain in transmit direction. AC-XGAIN = 1 Additional 6 dB analog amplification in transmit direction. Universal Tone Detector transmit source. Any change of bit UTDX-SRC only becomes effective, if bit UTDX-EN in register BCR5 is changed from 0 to 1. UTDX-SRC UTDX-SUM LEC-EN Signal Source for UTDX 0 0 don’t care Transmit 0 0 don’t care Transmit 0 1 0 Receive + Transmit 0 1 1 Receive + Transmit 1 don’t care 0 Transmit 1 don’t care 0 Transmit 1 don’t care 1 Lec-Output 1 don’t care 1 Lec-Output (see Figure 29 on Page 56) Preliminary Data Sheet 171 DS3, 2003-07-11 DuSLIC PDOT-DIS Power Down Overtemperature Disable PDOT-DIS = 0 When overtemperature is detected, the SLIC is automatically switched into Power Down High Impedance mode (PDH). This is the safe operation mode for the SLIC-E/-E2/-P in case of overtemperature. To leave the automatically activated PDH mode, DuSLIC must be switched manually to PDH mode and then in the mode as desired (otherwise the OTEMP bit in INTREG1 will not change back to 0). PDOT-DIS = 1 When overtemperature is detected, the SLIC-E/-E2/-P does not automatically switch into Power Down High Impedance mode. In this case, the output current of the SLIC-E/-E2/-P buffers is limited to a value that keeps the SLIC-E/-E2/-P temperature below the upper temperature limit. The OTEMP bit in INTREG1 changes back to 0 if the SLIC temperature is below the threshold again. The INT registers may be locked in addition if OTEMP-M = 0. Note: Transients on Tip/Ring can cause false overtemperature alarms, because the OTEMP signal is not deglitched. To avoid this situation it is recommended to switch off the automatic power down on overtemperature (PDOT-DIS = 1) and integrate a function for overtemperature handling in the interrupt service routine. Preliminary Data Sheet 172 DS3, 2003-07-11 DuSLIC 17H BCR3 Bit Basic Configuration Register 3 7 6 5 MULAW LIN PCM16K MU-LAW LIN 4 00H 3 PCMX- CONFX EN -EN Y 2 1 0 CONFEN LPRXCR CRAMEN Selects the PCM Law MU-LAW = 0 A-Law enabled. MU-LAW = 1 µ-Law enabled. Voice transmission in a 16-bit linear representation for test purposes. Note: Voice transmission on the other channel is inhibited if one channel is set to linear mode and the IOM-2-interface is used. In the PCM/microcontroller interface mode, both channels can be in linear mode using two consecutive PCM timeslots on the highways. A proper timeslot selection must be specified. PCM16K PCMX-EN LIN = 0 PCM mode enabled (8 bit, A-Law or µ-Law). LIN = 1 Linear mode enabled (16 bit). Selects 16-kHz sample rate for the PCM interface. PCM16K = 0 16-kHz mode disabled (8 kHz sampling rate). PCM16K = 1 16-kHz mode enabled. Enables writing of subscriber voice data to the PCM highway. PCMX-EN = 0 Writing of subscriber voice data to PCM highway is disabled. PCMX-EN = 1 Writing of subscriber voice data to PCM highway is enabled. CONFX-EN Enables an external three-party conference. CONFX-EN = 0 External conference is disabled. CONFX-EN = 1 External conference is enabled. Preliminary Data Sheet 173 DS3, 2003-07-11 DuSLIC CONF-EN LPRX-CR CRAM-EN Selection of three-party conferencing for this channel. The voice data of this channel and the voice data from the corresponding conferencing channels (see Chapter 4.1.1) are added and fed to analog output (see Chapter 2.10). CONF-EN = 0 Three-party conferencing is not selected. CONF-EN = 1 Three-party conferencing is selected. Select CRAM coefficients for the filter characteristic of the LPR/LPX filters. These coefficients may be enabled in case of a modem transmission to improve modem performance. LPRX-CR = 0 Coefficients from ROM are used. LPRX-CR = 1 Coefficients from CRAM are used. Coefficients from CRAM are used for programmable filters and DC loop behavior. CRAM-EN = 0 Coefficients from ROM are used. CRAM-EN = 1 Coefficients from CRAM are used. Preliminary Data Sheet 174 DS3, 2003-07-11 DuSLIC 18H BCR4 Bit Basic Configuration Register 4 7 6 TH-DIS IM-DIS TH-DIS IM-DIS AX-DIS AR-DIS FRX-DIS FRR-DIS HPX-DIS 5 4 AX-DIS AR-DIS 00H Y 3 2 1 0 FRXDIS FRRDIS HPXDIS HPRDIS Disables the TH filter. TH-DIS = 0 TH filter is enabled. TH-DIS = 1 TH filter is disabled (HTH = 0). Disables the IM filter. IM-DIS = 0 IM filter is enabled. IM-DIS = 1 IM filter is disabled (HIM = 0). Disables the AX filter. AX-DIS = 0 AX filter is enabled. AX-DIS = 1 AX filter is disabled (HAX = 1). Disables the AR filter. AX-DIS = 0 AR filter is enabled. AX-DIS = 1 AR filter is disabled (HAR = 1). Disables the FRX filter. FRX-DIS = 0 FRX filter is enabled. FRX-DIS = 1 FRX filter is disabled (HFRX = 1). Disables the FRR filter. FRR-DIS = 0 FRR filter is enabled. FRR-DIS = 1 FRR filter is disabled (HFRR = 1). Disables the high-pass filter in transmit direction. HPX-DIS = 0 High-pass filter is enabled. HPX-DIS = 1 High-pass filter is disabled (HHPX = 1). Preliminary Data Sheet 175 DS3, 2003-07-11 DuSLIC HPR-DIS Disables the high-pass filter in receive direction. HPR-DIS = 0 High-pass filter is enabled. HPR-DIS = 1 High-pass filter is disabled (HHPR = 1). Preliminary Data Sheet 176 DS3, 2003-07-11 DuSLIC 19H BCR5 Bit Basic Configuration Register 5 7 6 5 4 3 UTDREN UTDXEN CISAUTO CIS-EN LECOUT UTDR-EN 00H 2 Y 1 LEC-EN DTMFSRC 0 DTMFEN Enables the Universal Tone detection in receive direction. UTDR-EN = 0 Universal Tone detection is disabled. UTDR-EN = 1 Universal Tone detection is enabled. UTDX-EN Enables the Universal Tone detection in transmit direction. UTDX-EN = 0 Universal Tone detection is disabled. UTDX-EN = 1 Universal Tone detection is enabled. CIS-AUTO Controls the turn-off behavior of the Caller ID sender. CIS-AUTO = 0 The Caller ID sender stops when CIS-EN is switched to 0. CIS-AUTO = 1 The Caller ID sender continues sending data until the data buffer is empty. CIS-EN Enables the Caller ID sender in the SLICOFI-2. Note: The Caller ID sender is configured directly by programming the according POP registers. Caller ID data are written to a 48 byte RAM buffer. According to the buffer request size, this influences the CIS-REQ and CIS-BUF bits. CIS-EN = 0 Caller ID sender is disabled and Caller ID data buffer is cleared after all data are sent or if CIS-AUTO = 0. CIS-EN = 1 Caller ID sender is enabled and Caller ID data can be written to the data buffer. After the last data bit is sent, stop bits are sent to the subscriber. Caller ID data are sent to the subscriber when the number of bytes written to the buffer exceeds CIS-BRS + 2. Preliminary Data Sheet 177 DS3, 2003-07-11 DuSLIC LEC-OUT LEC-EN Line Echo Cancellation result for transmit path. LEC-OUT = 0 Line Echo Cancellation result used for DTMF only. LEC-OUT = 1 Line Echo Cancellation result fed to transmit path. Line Echo Cancellation LEC-EN = 0 Line Echo Cancellation for DTMF disabled. LEC-EN = 1 Line Echo Cancellation for DTMF enabled. DTMF-SRC Selects data source for DTMF receiver. Any change of bit DTMF-SRC only becomes effective, if bit DTMF-EN is changed from 0 to 1. DTMF-SRC = 0 The Transmit path data (with or without LEC) is used for the DTMF detection. DTMF-SRC = 1 The Receive path data is used for the DTMF detection. DTMF-EN Enables the DTMF receiver of the SLICOFI-2. The DTMF receiver will be configured properly by programming registers in the EDSP. DTMF-EN = 0 DTMF receiver is disabled. DTMF-EN = 1 DTMF receiver is enabled. Preliminary Data Sheet 178 DS3, 2003-07-11 DuSLIC 1AH DSCR Bit DTMF Sender Configuration Register 7 6 5 4 DG-KEY[3:0] 00H 3 2 COR8 PTG Y 1 0 TG2-EN TG1-EN DG-KEY[3:0] Selects one of sixteen DTMF keys generated by the two tone generators. The key will be generated if TG1-EN and TG2-EN are 1. Table 33 DTMF Keys fLOW [Hz] fHIGH [Hz] DIGIT DG-KEY3 DG-KEY2 DG-KEY1 DG-KEY0 697 1209 1 0 0 0 1 697 1336 2 0 0 1 0 697 1477 3 0 0 1 1 770 1209 4 0 1 0 0 770 1336 5 0 1 0 1 770 1477 6 0 1 1 0 852 1209 7 0 1 1 1 852 1336 8 1 0 0 0 852 1477 9 1 0 0 1 941 1336 0 1 0 1 0 941 1209 * 1 0 1 1 941 1477 # 1 1 0 0 697 1633 A 1 1 0 1 770 1633 B 1 1 1 0 852 1633 C 1 1 1 1 941 1633 D 0 0 0 0 COR8 Cuts off receive path at 8 kHz before the tone generator summation point. Allows sending of tone generator signals with no overlaid voice. COR8 = 0 Cut off receive path disabled. COR8 = 1 Cut off receive path enabled. Preliminary Data Sheet 179 DS3, 2003-07-11 DuSLIC PTG Programmable coefficients for tone generators will be used. TG2-EN PTG = 0 Frequencies set by DG-KEY are used for both tone generators. Tone generator TG1 level: –5 dBm0 Tone generator TG2 level: –3 dBm0 PTG = 1 CRAM coefficients used for both tone generators. Tone generator TG1 and TG2 frequencies and levels can be programmed in the DuSLICOS DC Control Parameters 3/4. The levels are set in dBm0: Level[dBm] = Level[dBm0] + LR[dBr] Enables tone generator two TG1-EN TG2-EN = 0 Tone generator is disabled. TG2-EN = 1 Tone generator is enabled. Enables tone generator one TG1-EN = 0 Tone generator is disabled. TG1-EN = 1 Tone generator is enabled. Reserved 1BH Bit 00H Y 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Preliminary Data Sheet 180 DS3, 2003-07-11 DuSLIC 1CH LMCR1 Bit Level Metering Configuration Register 1 22H Y 7 6 5 4 3 2 1 0 TESTEN LM-EN LMTHM PCM2DC LM2 PCM LMONCE LMMASK DCAD16 TEST-EN Activates the SLICOFI-2 test features controlled by test registers TSTR1 to TSTR5. TEST-EN = 0 SLICOFI-2 test features are disabled. TEST-EN = 1 SLICOFI-2 test features are enabled. Note: The Test Register bits can be programmed before the TEST-EN bit is set to 1. LM-EN LM-THM PCM2DC LM2PCM Enables level metering. A positive transition of this bit starts level metering (AC and DC). LM-EN = 0 Level metering stops. LM-EN = 1 Level metering enabled. Level metering threshold mask bit LM-THM = 0 A change of the LM-THRES bit (register INTREG2) generates an interrupt. LM-THM = 1 No interrupt is generated. PCM voice channel data added to the DC-output. PCM2DC = 0 Normal operation. PCM2DC = 1 PCM voice channel data is added to DC output. Level metering source/result (depending on LM-EN bit) feeding to PCM or IOM-2 interface. LM2PCM = 0 Normal operation. LM2PCM = 1 Level metering source/result is fed to the PCM or IOM-2 interface. Preliminary Data Sheet 181 DS3, 2003-07-11 DuSLIC LM-ONCE LM-MASK DC-AD16 Level metering execution mode. LM-ONCE = 0 Level metering is executed continuously. LM-ONCE = 1 Level metering is executed only once. To start the Level Meter again, the LM-EN bit must again be set from 0 to 1. Interrupt masking for level metering. LM-MASK = 0 An interrupt is generated after level metering. LM-MASK = 1 No interrupt is generated. Additional digital amplification in the DC AD path for level metering. DC-AD16 = 0 Additional gain factor 16 disabled. DC-AD16 = 1 Additional gain factor 16 enabled. Preliminary Data Sheet 182 DS3, 2003-07-11 DuSLIC 1DH LMCR2 Bit Level Metering Configuration Register 2 7 6 5 4 LMNOTCH LMFILT LMRECT RAMPEN LM-NOTCH LM-FILT LM-RECT RAMP-EN LM-SEL[3:0] 3 00H 2 Y 1 0 LM-SEL[3:0] Selection of a notch filter instead of the band-pass filter for level metering. LM-NOTCH = 0 Notch filter selected. LM-NOTCH = 1 Band-pass filter selected. Enabling of a programmable band-pass or notch filter for level metering. LM-FILT = 0 Normal operation. LM-FILT = 1 Band-pass/notch filter enabled. Rectifier in DC Level Meter LM-RECT = 0 Rectifier disabled. LM-RECT = 1 Rectifier enabled. The ramp generator works together with the RNG-OFFSET bits in LMCR3 and the LM-EN bit to create different voltage slopes in the DCPath. RAMP-EN = 0 Ramp generator disabled. RAMP-EN = 1 Ramp generator enabled. Selection of the source for the level metering. LM-SEL[3:0] = 0 0 0 0 AC level metering in transmit LM-SEL[3:0] = 0 0 0 1 Real part of TTX (TTXREAL) LM-SEL[3:0] = 0 0 1 0 Imaginary part of TTX (TTXIMG) LM-SEL[3:0] = 0 0 1 1 Not used LM-SEL[3:0] = 0 1 0 0 DC out voltage on DCN-DCP LM-SEL[3:0] = 0 1 0 1 DC current on IT LM-SEL[3:0] = 0 1 1 0 AC level metering in receive Preliminary Data Sheet 183 DS3, 2003-07-11 DuSLIC LM-SEL[3:0] = 0 1 1 1 AC level metering in receive and transmit LM-SEL[3:0] = 1 0 0 0 Not used LM-SEL[3:0] = 1 0 0 1 DC current on IL LM-SEL[3:0] = 1 0 1 0 Voltage on IO3 LM-SEL[3:0] = 1 0 1 1 Voltage on IO4 LM-SEL[3:0] = 1 1 0 0 Not used LM-SEL[3:0] = 1 1 0 1 VDD LM-SEL[3:0] = 1 1 1 0 Offset of DC-Prefi (short circuit on DC-Prefi input) LM-SEL[3:0] = 1 1 1 1 Voltage on IO4 – IO3 Preliminary Data Sheet 184 DS3, 2003-07-11 DuSLIC 1EH LMCR3 Bit Level Metering Configuration Register 3 7 6 ACSHORT -EN RTRSEL 5 4 3 LM-ITIME[3:0] 2 00H Y 1 0 RNGOFFSET[1:0] AC-SHORT-EN The input pin ITAC will be set to a lower input impedance so that the capacitor CITAC can be recharged faster during a soft reversal which makes it more silent during conversation. AC-SHORT-EN = 0 Input impedance of the ITAC pin is standard. AC-SHORT-EN = 1 Input impedance of the ITAC pin is lowered. RTR-SEL Ring Trip method selection. RTR-SEL = 0 Ring Trip with a DC offset is selected. RTR-SEL = 1 AC Ring Trip is selected. Recommended for short lines only. LM-ITIME[3:0] Integration Time for AC Level Metering. LM-ITIME[3:0] = 0 0 0 0 16 ms LM-ITIME[3:0] = 0 0 0 1 2 × 16 ms LM-ITIME[3:0] = 0 0 1 0 3 × 16 ms … 16 × 16 ms LM-ITIME[3:0] = 1 1 1 1 RNGOFFSET[1:0] Selection of the Ring Offset source. Preliminary Data Sheet 185 DS3, 2003-07-11 DuSLIC RNGOFFSET[1:0] Ring Offset Voltage in Given Mode Active ACTH ACTL Active Ring ACTR Ring Pause Ringing 00 Voltage given by DC Voltage given by DC Ring Offset RO1 regulation regulation Hook Threshold Ring 01 Ring Offset RO1/2 (no DC regulation) Ring Offset RO1 (no DC regulation) Ring Offset RO1 Hook Threshold Ring 10 Ring Offset RO2/2 (no DC regulation) Ring Offset RO2 (no DC regulation) Ring Offset RO2 Hook Message Waiting 11 Ring Offset RO3/2 (no DC regulation) Ring Offset RO3 (no DC regulation) Ring Offset RO3 Hook Message Waiting By setting the RAMP-EN bit to 1, the ramp generator is started by setting LM-EN from 0 to 1 (see Figure 63). Exception: Transition of RNG-OFFSET from 10 to 11 or 11 to 10 where the ramp generator is started automatically (see Figure 63). For Ring Offset RO1, the usual “Hook Threshold Ring” is used. Using Ring Offset RO2 or RO3 in any ringing mode (Ringing and Ring Pause) also changes the hook thresholds. In this case the “Hook Message Waiting” threshold is used automatically. When using the Ring Offsets RO2 and RO3 for Message Waiting, an additional lamp current is expected. In this case, the Hook Message Waiting threshold should be programmed higher than the Hook Threshold Ring. Preliminary Data Sheet 186 DS3, 2003-07-11 DuSLIC RNG-OFFSET[1:0] 01 10 11 01 RAMP-EN (register LMCR2) LM-EN (register LMCR1) Generated Ring Offset (RO) Voltage RO3 = 120 V RO2 = 40 V RO1 = 20 V t ezm35002 Figure 63 Example for Switching Between Different Ring Offset Voltages The three programmable Ring Offsets are typically used for the following purposes: Table 34 Typical Usage for the three Ring Offsets Ring Offset Voltage Application Ring Offset RO1 Ringing Ring Offset RO2 Low voltage for message waiting lamp Ring Offset RO3 High voltage for message waiting lamp Besides the typical usage described in Table 34, the Ring Offsets RO1, RO2, and RO3 can also be used for the generation of different custom waveforms (see Figure 63). Preliminary Data Sheet 187 DS3, 2003-07-11 DuSLIC 1FH OFR1 Bit Offset Register 1 (High Byte) 7 6 5 4 00H 3 2 Y 1 0 OFFSET-H[7:0] OFFSET-H[7:0] 20H Bit Offset register High Byte. OFR2 7 Offset Register 2 (Low Byte) 6 5 4 3 00H 2 1 Y 0 OFFSET-L[7:0] OFFSET-L[7:0] Offset register Low Byte. The value of this register together with OFFSET-H is added to the input of the DC loop to compensate for a given offset of the current sensors in the SLIC-E/-E2/-P. Preliminary Data Sheet 188 DS3, 2003-07-11 DuSLIC 21H PCMR1 Bit 7 PCM Receive Register 1 6 5 4 R1HW 00H 3 2 Y 1 0 R1-TS[6:0] This register is not applicable and is not used in IOM-2 mode. It is only enabled in PCM/microcontroller mode. R1-HW R1-TS[6:0] Selection of the PCM highway for receiving PCM data or the higher byte of the first data sample if a linear 16-kHz PCM mode is selected. R1-HW = 0 PCM highway A is selected. R1-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for data reception. Note: The programmed PCM timeslot must correspond to the available slots defined by the PCLK frequency. No reception will occur if a slot outside the actual numbers of slots is programmed. In linear mode (bit LIN = 1 in register BCR3), R1-TS defines the first of two consecutive slots used for reception. Preliminary Data Sheet 189 DS3, 2003-07-11 DuSLIC 22H PCMR2 Bit 7 PCM Receive Register 2 6 5 4 R2HW 00H 3 2 Y 1 0 R2-TS[6:0] This register is not applicable and is not used in IOM-2 mode. It is only enabled in PCM/microcontroller mode. R2-HW R2-TS[6:0] Selection of the PCM highway for receiving conferencing data for conference channel B or the lower byte of the first data sample if a linear 16-kHz PCM mode is selected. R2-HW = 0 PCM highway A is selected. R2-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for receiving data (see description of PCMR1 register). Preliminary Data Sheet 190 DS3, 2003-07-11 DuSLIC 23H PCMR3 Bit 7 PCM Receive Register 3 6 5 4 R3HW 00H 3 2 Y 1 0 R3-TS[6:0] This register is not applicable and is not used in IOM-2 mode. It is only enabled in PCM/microcontroller mode. R3-HW R3-TS[6:0] Selection of the PCM highway for receiving conferencing data for conference channel C or the higher byte of the second data sample if a linear 16-kHz PCM mode is selected. R3-HW = 0 PCM highway A is selected. R3-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for receiving data (see description of PCMR1 register). Preliminary Data Sheet 191 DS3, 2003-07-11 DuSLIC 24H PCMR4 Bit 7 PCM Receive Register 4 6 5 4 R4HW 00H 3 2 Y 1 0 R4-TS[6:0] This register is not applicable and is not used in IOM-2 mode. It is only enabled in PCM/microcontroller mode. R4-HW R4-TS[6:0] Selection of the PCM highway for receiving conferencing data for conference channel D or the lower byte of the second data sample if a linear 16-kHz PCM mode is selected. R4-HW = 0 PCM highway A is selected. R4-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for receiving data (see description of PCMR1 register). Preliminary Data Sheet 192 DS3, 2003-07-11 DuSLIC 25H PCMX1 Bit 7 PCM Transmit Register 1 6 5 4 X1HW 00H 3 2 Y 1 0 X1-TS[6:0] This register is not applicable and is not used in IOM-2 mode. It is only enabled in PCM/microcontroller mode. X1-HW X1-TS[6:0] Selection of the PCM highway for transmitting PCM data or the higher byte of the first data sample if a linear 16-kHz PCM mode is selected. X1-HW = 0 PCM highway A is selected. X1-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for data transmission. Note: The programmed PCM timeslot must correspond to the available slots defined by the PCLK frequency. No transmission will occur if a slot outside the actual numbers of slots is programmed. In linear mode X1-TS defines the first of two consecutive slots used for transmission. PCM data transmission is controlled by the bits 6 through 2 in register BCR3. Preliminary Data Sheet 193 DS3, 2003-07-11 DuSLIC 26H PCMX2 Bit 7 PCM Transmit Register 2 6 5 4 X2HW 00H 3 2 Y 1 0 X2-TS[6:0] This register is not applicable and is not used in IOM-2 mode. It is only enabled in PCM/microcontroller mode. X2-HW X2-TS[6:0] Selection of the PCM highway for transmitting conferencing data for conference channel C + S or C + D or the lower byte of the first data sample if a linear 16-kHz PCM mode is selected. X2-HW = 0 PCM highway A is selected. X2-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for transmitting data (see description of PCMX1 register). Preliminary Data Sheet 194 DS3, 2003-07-11 DuSLIC 27H PCMX3 Bit 7 PCM Transmit Register 3 6 5 4 X3HW 00H 3 2 Y 1 0 X3-TS[6:0] This register is not applicable and is not used in IOM-2 mode. It is only enabled in PCM/microcontroller mode. X3-HW X3-TS[6:0] Selection of the PCM highway for transmitting conferencing data for conference channel B + S or B + D or the lower byte of the first data sample if a linear 16-kHz PCM mode is selected. X3-HW = 0 PCM highway A is selected. X3-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for transmitting data (see description of PCMX1 register). Preliminary Data Sheet 195 DS3, 2003-07-11 DuSLIC 28H PCMX4 Bit 7 PCM Transmit Register 4 6 5 4 X4HW 00H 3 2 Y 1 0 X4-TS[6:0] This register is not applicable and is not used in IOM-2 mode. It is only enabled in PCM/microcontroller mode. X4-HW X4-TS[6:0] Selection of the PCM highway for transmitting conferencing data for conference channel B + C or the lower byte of the first data sample if a linear 16-kHz PCM mode is selected. X4-HW = 0 PCM highway A is selected. X4-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for transmitting data (see description of PCMX1 register). Preliminary Data Sheet 196 DS3, 2003-07-11 DuSLIC 29H TSTR1 Bit Test Register 1 7 6 5 00H 4 3 PD-AC- PD-AC- PD-AC- PD-AC- PD-ACPR PO AD DA GN T Y 2 1 0 PDGNKC PDOFHC PDOVTC Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. PD-AC-PR PD-AC-PO PD-AC-AD PD-AC-DA PD-AC-GN PD-GNKC AC-PREFI Power Down PD-AC-PR = 0 Normal operation. PD-AC-PR = 1 Power Down mode. AC-POFI Power Down PD-AC-PO = 0 Normal operation. PD-AC-PO = 1 Power Down mode. AC-ADC Power Down PD-AC-AD = 0 Normal operation. PD-AC-AD = 1 Power Down mode, transmit path is inactive. AC-DAC Power Down PD-AC-DA = 0 Normal operation. PD-AC-DA = 1 Power Down mode, receive path is inactive. AC-Gain Power Down PD-AC-GN = 0 Normal operation. PD-AC-GN = 1 Power Down mode. Ground key comparator (GNKC) is set to Power Down PD-GNKC = 0 Normal operation. PD-GNKC = 1 Power Down mode. Preliminary Data Sheet 197 DS3, 2003-07-11 DuSLIC PD-OFHC PD-OVTC Off-hook comparator (OFHC) Power Down PD-OFHC = 0 Normal operation. PD-OFHC = 1 Power Down mode. Overtemperature comparator (OVTC) Power Down PD-OVTC = 0 Normal operation. PD-OVTC = 1 Power Down mode. Preliminary Data Sheet 198 DS3, 2003-07-11 DuSLIC 2AH TSTR2 Bit Test Register 2 7 6 PD-DCPR 0 5 00H 4 3 PD-DC- PD-DCPDAD DA DCBUF T Y 2 1 0 0 PDTTX-A PD-HVI Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. PD-DC-PR PD-DC-AD PD-DC-DA PD-DCBUF PD-TTX-A PD-HVI DC-PREFI Power Down PD-DC-PR = 0 Normal operation. PD-DC-PR = 1 Power Down mode. DC-ADC Power Down PD-DC-AD = 0 Normal operation. PD-DC-AD = 1 Power Down mode, transmit path is inactive. DC-DAC Power Down PD-DC-DA = 0 Normal operation. PD-DC-DA = 1 Power Down mode, receive path is inactive. DC-BUFFER Power Down PD-DCBUF = 0 Normal operation. PD-DCBUF = 1 Power Down mode. TTX Adaptation DAC and POFI Power Down PD-TTX-A = 0 Normal operation. PD-TTX-A = 1 Power Down mode. HV interface (to SLIC-E/-E2/-P) Power Down PD-HVI = 0 Normal operation. PD-HVI = 1 Power Down mode. Preliminary Data Sheet 199 DS3, 2003-07-11 DuSLIC 2BH Bit TSTR3 Test Register 3 00H T Y 7 6 5 4 3 2 1 0 0 0 ACDLB4M ACDLB128K ACDLB32K ACDLB8K 0 0 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. AC-DLB-4M AC digital loop via a 4-MHz bitstream. (Loop encloses all digital hardware in the AC path. Together with DLB-DC, a pure digital test is possible because there is no influence from the analog hardware.) AC-DLB-4M = 0 Normal operation. AC-DLB-4M = 1 Digital loop closed. AC-DLB-128K AC digital loop via 128 kHz AC-DLB-128K = 0 Normal operation. AC-DLB-128K = 1 Digital loop closed. AC-DLB-32K AC-DLB-8K AC digital loop via 32 kHz AC-DLB-32K = 0 Normal operation. AC-DLB-32K = 1 Digital loop closed. AC digital loop via 8 kHz AC-DLB-8K = 0 Normal operation. AC-DLB-8K = 1 Digital loop closed. Preliminary Data Sheet 200 DS3, 2003-07-11 DuSLIC 2CH TSTR4 Bit Test Register 4 7 6 OPIMAN OPIM4M 5 00H 4 COR-64 COX-16 T Y 3 2 1 0 0 0 0 0 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. OPIM-AN OPIM-4M COR-64 COX-16 Open Impedance Matching Loop in the analog part. OPIM-AN = 0 Normal operation. OPIM-AN = 1 Loop opened. Open fast digital Impedance Matching Loop in the hardware filters. OPIM-4M = 0 Normal operation. OPIM-4M = 1 Loop opened. Cut off the AC receive path at 64 kHz (just before the IM filter). COR-64 = 0 Normal operation. COR-64 = 1 Receive path is cut off. Cut off the AC transmit path at 16 kHz.(The TH filters can be tested without the influence of the analog part.) COX-16 = 0 Normal operation. COX-16 = 1 Transmit path is cut off. Preliminary Data Sheet 201 DS3, 2003-07-11 DuSLIC 2DH TSTR5 Bit Test Register 5 00H T Y 7 6 5 4 3 2 1 0 0 0 0 DCPOFIHI DCHOLD 0 0 0 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. DC-POFI-HI DC-HOLD Higher value for DC post filter limit DC-POFI-HI = 0 Limit frequency is set to 100 Hz (normal operation). DC-POFI-HI = 1 Limit frequency is set to 300 Hz. Actual DC output value hold (value of the last DSP filter stage will be kept) DC-HOLD = 0 Normal operation. DC-HOLD = 1 DC output value hold. Preliminary Data Sheet 202 DS3, 2003-07-11 DuSLIC 5.2.2 COP Command The Coefficient Operation (COP) command gives access to the CRAM data of the DSPs. It is organized in the same way as the SOP command. The offset value allows a direct as well as a block access to the CRAM. Writing beyond the allowed offset will be ignored, reading beyond it will give unpredictable results. The value of a specific CRAM coefficient is calculated by the DuSLICOS software. Attention: To ensure proper functionality, it is essential that all unused register bits have to be filled with zeros. Bit Byte 1 7 6 RD 1 5 4 ADR[2:0] Byte 2 RD 3 2 1 0 1 0 1 OFFSET[7:0] Read Data RD = 0 Write data to chip. RD = 1 Read data from chip. ADR[2:0] Channel address for the subsequent data ADR[2:0] = 0 0 0 Channel A ADR[2:0] = 0 0 1 Channel B (other codes reserved for future use) Preliminary Data Sheet 203 DS3, 2003-07-11 DuSLIC Offset [7:0] Short Name Long Name 00H TH1 Transhybrid Filter Coefficients Part 1 08H TH2 Transhybrid Filter Coefficients Part 2 10H TH3 Transhybrid Filter Coefficients Part 3 18H FRR Frequency-response Filter Coefficients Receive Direction 20H FRX Frequency-response Filter Coefficients Transmit Direction 28H AR Amplification/Attenuation Stage Coefficients Receive 30H AX Amplification/Attenuation Stage Coefficients Transmit 38H PTG1 Tone Generator 1 Coefficients 40H PTG2 Tone Generator 2 Coefficients 48H LPR Low Pass Filter Coefficients Receive 50H LPX Low Pass Filter Coefficients Transmit 58H TTX Teletax Coefficients 60H IM1 Impedance Matching Filter Coefficients Part 1 68H IM2 Impedance Matching Filter Coefficients Part 2 70H RINGF Ringer Frequency and Amplitude Coefficients (DC loop) 78H RAMPF Ramp Generator Coefficients (DC loop) 80H DCF DC Characteristics Coefficients (DC loop) 88H HF Hook Threshold Coefficients (DC loop) 90H TPF Low-pass Filter Coefficients (DC loop) 98H Preliminary Data Sheet Reserved 204 DS3, 2003-07-11 DuSLIC Table 35 Byte 7 CRAM Coefficients Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Transhybrid Coefficient Part 1 00H TH1 08H TH2 10H TH3 FIR Filter in Receive Direction 18H FRR FIR Filter in Transmit Direction 20H FRX Transhybrid Coefficient Part 2 Transhybrid Coefficient Part 3 LM Threshold Band-pass for AC LM Conference Gain LMAC 2nd Gain Stage Receive 1st Gain Stage Receive 28H AR 2nd Gain Stage Transmit 1st Gain Stage Transmit 30H AX TG1 Band-pass TG1 Gain TG1 Frequency 38H PTG1 1) TG2 Band-pass TG2 Gain TG2 Frequency 40H PTG2 1) LPR 48H LPR 2) LPX 50H LPX 2) 58H TTX 60H IM1_F 68H IM2_F FIR Filter for TTX TTX Slope IM K Factor Ring Generator Frequency Ring Generator Low-pass Ring Offset RO1 70H RINGF Soft Reversal End Constant Ramp CR Soft Ramp SS Ring Delay RD 78H RAMPF Knee Voltage VK1 Open Circuit Volt. 80H DCF 88H HF 90H TPF Res. in Constant Current Zone RI Hook Message Waiting Ring Offset RO3 IM WDF Filter Ring Generator Amplitude LM DC Gain Res. in Resistive Zone RK12 TTX Level IM FIR Filter IM 4 MHz Filter Extended Battery Feeding Gain Constant Current IK1 VLIM Hook Threshold AC Ring Trip Ring Offset RO2 Hook Threshold Ring Voltage Level VTR Hook Threshold Active DC Low-pass Filter TP2 Hook Threshold Power Down DC Low-pass Filter TP1 Reserved 16 15 14 13 Offset [7:0] 12 11 10 9 8 98H 7 6 5 4 3 2 1 CRAM coefficients are enabled by setting bit CRAM-EN in register BCR3 to 1, except coefficients marked 1) and 2): Coefficients marked1) are enabled by setting bit PTG in register DSCR to 1. Coefficients marked2) are enabled by setting bit LPRX-CR in register BCR3 to 1. Preliminary Data Sheet 205 DS3, 2003-07-11 DuSLIC 5.2.2.1 Table 36 CRAM Programming Ranges CRAM Programming Ranges Parameter Programming Range Constant Current IK1 0...50 mA, ∆ < 0.5 mA Hook Message Waiting, Hook Thresholds 0..25 mA, ∆ < 0.7 mA 25...50 mA, ∆ < 1.3 mA Ring Generator Frequency fRING 3..40 Hz, ∆ < 1 Hz 40..80 Hz, ∆ < 2 Hz > 80 Hz, ∆ < 4 Hz Ring Generator Amplitude 0..20 V, ∆ < 1.7 V 20..85 V, ∆ < 0.9 V Ring Offset RO1, RO2, RO3 0..25 V, ∆ < 0.6 V 25..50 V, ∆ < 1.2 V 50..100 V, ∆ < 2.4 V, max. 150 V Knee Voltage VK1, Open Circuit Voltge VLIM 0..25 V, ∆ < 0.6 V 25..50 V, ∆ < 1.2 V > 50 V, ∆ < 2.4 V Resistance in Resistive Zone RK12 0..1000 Ω, ∆ < 30 Ω Resistance in Constant Current Zone RI 1.8 kΩ..4.8 kΩ, ∆ < 120 Ω 4.8 kΩ..9.6 kΩ, ∆ < 240 Ω 9.6 kΩ..19 kΩ, ∆ < 480 Ω 19 kΩ..38 kΩ, ∆ < 960 Ω, max. 40 kΩ Preliminary Data Sheet 206 DS3, 2003-07-11 DuSLIC 5.2.3 POP Command The Signal Processing Operation Programming (POP) command provides access to the Enhanced Digital Signal Processor (EDSP) registers of the SLICOFI-2. Before using an EDSP function the according POP registers have to be programmed. Any change in any of the POP registers (except registers CIS-DAT and CIS/LEC-MODE) is only updated with enabling the corresponding device. For example a change of the center frequency fC of the UTD is handled by changing the registers UTD-CF-H and UTD-CF-L, switching off the UTD and switching it on again. The POP registers do no have default values after any kind of reset. Attention: To ensure proper functionality, the POP registers have to be programmed before EDSP-EN = 1. Furthermore, all unused POP register bits must be filled with zeros. 5.2.3.1 Sequence for POP Register Programming Please note that the NLP coefficients share the memory location with DTMF and LEC coefficients. The coefficients are programmed in the following order (Before the first activation of the EDSP all POP registers have to be programmed. By activation of the individual functions the contents of the double-used registers are then taken over.): 1. Program the LEC coefficients. By setting bit LEC-EN in register BCR5 to 1, the coefficients are copied into the EDSP and the LEC is activated. 2. Program the DTMF coefficients. By setting bit DTMF-EN in register BCR5 to 1, the coefficients are copied into the EDSP and the DTMF receiver is activated. 3. Program the NLP coefficients. By setting bit NLP-EN in POP register CIS/LEC-Mode to 1, the coefficients are copied into the EDSP and the NLP is activated. Please note that the NLP can only be activated, when also the LEC is active. If the NLP coefficients have been programmed in a prior session, it is possible to activate the NLP using the old NLP configuration by setting bit NLP-OLDC in POP register NLP-CTRL to 1. Attention: NLP coefficients are only available with SLICOFI-2 Version 1.5 Preliminary Data Sheet 207 DS3, 2003-07-11 DuSLIC 5.2.3.2 POP Register Overview Attention: NLP coefficients are only available with SLICOFI-2 Version 1.5 00H CIS-DAT Caller ID Sender Data Buffer (write-only) 30H DTMF-LEV DTMF Receiver Level Byte 0 30H NLP-POW-LPF b e NLP Power Estimation LP Fast Time Constant POW-LPF 31H DTMF-TWI DTMF Receiver Twist Byte TWI 31H NLP-POW-LPS NLP Power Estimation LP Slow Time Constant POW-LPS 32H DTMF-NCF-H DTMF Receiver Notch Filter Center Frequency High Byte NCF-H 32H NLP-BN-LEV-X NLP Background Noise Estimation Transmit Level BN-LEV-X 33H DTMF-NCF-L DTMF Receiver Notch Filter Center Frequency Low Byte NCF-L 33H NLP-BN-LEV-R NLP Background Noise Estimation Receive Level BN-LEV-R 34H DTMF-NBW-H DTMF Receiver Notch Filter Bandwidth High Byte NBW-H 34H NLP-BN-INC NLP Background Noise Estimation Increment BN-INC 35H DTMF-NBW-L DTMF Receiver Notch Filter Bandwidth Low Byte NBW-L 35H NLP-BN-DEC NLP Background Noise Estimation Decrement BN-DEC Preliminary Data Sheet 208 DS3, 2003-07-11 DuSLIC 36H DTMF-GAIN Gain Stage Control for DTMF Input Signal e 36H NLP-BN-MAX m NLP Background Noise Estimation Maximum Noise BN-MAX 37H NLP-BN-ADJ NLP Background Noise Estimation Noise Adjustment BN-ADJ 38H NLP-RE-MIN-ERLL NLP Residual Echo Minimum ERL for LEC + Line RE-MIN-ERLL 39H NLP-RE-EST-ERLL NLP Residual Echo Estimated ERL for LEC + Line RE-EST-ERLL 3AH LEC-LEN Line Echo Cancellation Length LEN 3AH NLP-SD-LEV-X NLP Speech Detection Transmit Direction Level SD-LEV-X 3BH LEC-POWR Line Echo Cancellation Power Detection Level POWR 3BH NLP-SD-LEV-R NLP Speech Detection Receive Direction Level SD-LEV-R 3CH LEC-DELP Line Echo Cancellation Delta Power DELP 3CH NLP-SD-LEV-BN NLP Speech Detection BN Level SD-LEV-BN 3DH LEC-DELQ Line Echo Cancellation Delta Quality DELQ 3DH NLP-SD-LEV-RE NLP Speech Detection RE Level SD-LEV-RE Preliminary Data Sheet 209 DS3, 2003-07-11 DuSLIC 3EH LEC-GAIN-XI Line Echo Cancellation Input Gain Transmit e 3EH NLP-SD-OT-DT m NLP Speech Detection Overhang Tone for Double Talk SD-OT-DT 3FH LEC-GAIN-RI Line Echo Cancellation Input Gain Receive e 3FH NLP-ERL-LIN-LP m NLP Echo Return Loss Line LP Time Constant ERL-LIN-LP 40H LEC-GAIN-XO Line Echo Cancellation Output Gain Transmit e 40H NLP-ERL-LEC-LP m NLP Echo Return Loss LEC LP Time Constant ERL-LEC-LP 41H NLP-CT-LEV-RE NLP Control RE Level CT-LEV-RE 42H NLP-CTRL 0 43H CIS-LEV-H NLP Control 0 0 0 0 NLP-NM NLP-NG NLP-OLDC Caller ID Sender Level High Byte LEV-H 44H CIS-LEV-L Caller ID Sender Level Low Byte LEV-L 45H CIS-BRS Caller ID Sender Buffer Request Size BRS 46H CIS-SEIZ-H Caller ID Sender Number of Seizure Bits High Byte SEIZ-H Preliminary Data Sheet 210 DS3, 2003-07-11 DuSLIC 47H CIS-SEIZ-L Caller ID Sender Number of Seizure Bits Low Byte SEIZ-L 48H CIS-MARK-H Caller ID Sender Number of Mark Bits High Byte MARK-H 49H CIS-MARK-L Caller ID Sender Number of Mark Bits Low Byte MARK-L 4AH 4BH CIS/LEC-MODE CIS/LEC Mode Setting LEC-ADAPT UTDX-SUM LEC-FREEZE UTD-CF-H UTDR-SUM 0 NLP-EN CIS-FRM CIS-V23 Universal Tone Detection Center Frequency High Byte CF-H 4CH UTD-CF-L Universal Tone Detection Center Frequency Low Byte CF-L 4DH UTD-BW-H Universal Tone Detection Bandwidth High Byte BW-H 4EH UTD-BW-L Universal Tone Detection Bandwidth Low Byte BW-L 4FH UTD-NLEV Universal Tone Detection Noise Level NLEV 50H UTD-SLEV-H Universal Tone Detection Signal Level High Byte SLEV-H 51H UTD-SLEV-L Universal Tone Detection Signal Level Low Byte SLEV-L Preliminary Data Sheet 211 DS3, 2003-07-11 DuSLIC 52H UTD-DELT Universal Tone Detection Delta DELT-H 53H UTD-RBRK Universal Tone Detection Recognition Break Time RBRK 54H UTD-RTIME Universal Tone Detection Recognition Time RTIME 55H UTD-EBRK UTD Allowed Tone End Detection Break Time EBRK 56H UTD-ETIME UTD Tone End Detection Time ETIME Preliminary Data Sheet 212 DS3, 2003-07-11 DuSLIC 5.2.3.3 POP Register Description Attention: NLP coefficients are only available with SLICOFI-2 Version 1.5 00H Bit CIS-DAT 7 Caller ID Sender Data Buffer (write-only) 6 5 4 3 2 Y 1 0 Byte 0 Byte 1 Byte 2 Byte 47 Preliminary Data Sheet 213 DS3, 2003-07-11 DuSLIC 30H Bit DTMF-LEV 7 DTMF Receiver Level Byte 6 5 4 0 Y 3 2 b 1 0 e Minimum DTMF Signal Detection Level LevelDTMFdet • for DTMF detection in transmit: LevelDTMFdet[dB] = LevelDTMFdet[dBm0] – 3.14 + GDTMF[dB] LevelDTMFdet[dB] = LevelDTMFdet[dBm] – Lx[dBr] – 3.14 + GDTMF[dB] • for DTMF detection in receive: LevelDTMFdet[dB] = LevelDTMFdet[dBm0] – 3.14 + AR1[dB] + GDTMF[dB] LevelDTMFdet[dB] = LevelDTMFdet[dBm] – LR[dBr] – 3.14 + AR1[dB] + GDTMF[dB] AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 ≈ LR for LR ≤–2 dBr, AR1 ≈ –2 dB for LR > –2 dBr. LevelDTMFdet[dB] = –30 – b – 3 × e[dB] –54 dB ≤LevelDTMFdet ≤–30 dB with 0 ≤e ≤7 0 ≤b ≤3 Alternative representation b = MOD[(–LevelDTMFdet[dB] – 30),3] e = INT[(–LevelDTMFdet[dB] – 30)/3] Note: MOD = Modulo function, INT = Integer function Preliminary Data Sheet 214 DS3, 2003-07-11 DuSLIC 30H NLP-POWLPF Bit 7 NLP Power Estimation LP Fast Time Constant 6 5 4 3 Y 2 1 0 POW-LPF NLP Power Estimation Low Pass Fast Time Constant: The TPOW-LPF time constant is used for increasing signals. POW-LPF = 255/TPOW-LPF[ms] 1 ms ≤TPOW-LPF ≤255 ms Table 37 Range of TPOW-LPF POW-LPF TPOW-LPF[ms] 0xFF 1 … 0x01 255 Preliminary Data Sheet 215 DS3, 2003-07-11 DuSLIC 31H DTMF-TWI Bit 7 DTMF Receiver Twist Byte 6 5 4 Y 3 2 1 0 TWI DTMF Receiver Twist Byte: The DTMF receiver twist byte defines the maximum allowed difference between the signal levels of the two tones for DTMF detection: TWI = 2 × Twistacc[dB] 0 dB ≤Twistacc ≤12 dB Table 38 Range of Twistacc POW-LPS Twistacc[dB] 0x00 0 … 0x18 12 Preliminary Data Sheet 216 DS3, 2003-07-11 DuSLIC 31H NLP-POWLPS Bit 7 NLP Power Estimation LP Slow Time Constant 6 5 4 3 Y 2 1 0 POW-LPS NLP Power Estimation Low Pass Slow Time Constant: The TPOW-LPS time constant is used for decreasing signals. POW-LPS = 1024/TPOW-LPS[ms] 4 ms < TPOW-LPS ≤1024 ms Table 39 Range of TPOW-LPS POW-LPS TPOW-LPS[ms] 0xFF 4 … 0x01 32H Bit 1024 DTMF-NCF-H DTMF Receiver Notch Filter Center Frequency High Byte 7 6 5 4 3 Y 2 1 0 NCF-H This byte belongs to the DTMF-NCF-L byte described on Page 219. Preliminary Data Sheet 217 DS3, 2003-07-11 DuSLIC 32H NLP-BNLEV-X Bit 7 NLP Background Noise Estimation Transmit Level 6 5 4 3 Y 2 1 0 BN-LEV-X NLP Background Noise Estimation Transmit Level: If the transmit signal SLEC,TIN (Figure 24) is below PowBN-LEV-X and the receive signal is below PowBN-LEV-R (see Page 220), the background noise estimator uses the transmit signal for the background noise estimation. Otherwise the background noise estimator is frozen. PowBN-LEV-X[dB] = SX,BN-LEV[dBm0] – 3.14 + GLEC-XI[dB] – 20*log10(π/2) SX,BN-LEV[dBm0]: Power detection level at digital output for freezing the background noise estimator BN-LEV-X = (6.02 × 16 + PowBN-LEV-X[dB]) × 2/(5 × log102) = (96.32 + PowBN-LEV-X[dB]) × 1.329 –96 dB ≤PowBN-LEV-X ≤0 dB Table 40 Range of PowBN-LEV-X BN-LEV-X PowBN-LEV-X[dB] 0x00 –96 … 0x7F 0 Preliminary Data Sheet 218 DS3, 2003-07-11 DuSLIC 33H Bit DTMF-NCF-L DTMF Receiver Notch Filter Center Frequency Low Byte 7 6 5 4 3 Y 2 1 0 NCF-L DTMF Receiver Notch Filter Center Frequency: NCF = 32768 × f NCF [ Hz ] cos 2π --------------------- = NCF-L + 256 × NCF-H 8000 0 Hz ≤fNCF ≤2000 Hz The bytes are calculated as follows: NCF-L = MOD (NCF,256) = NCF & 0x00FF NCF-H = INT (NCF/256) = NCF >> 8 The echo of the dial tone can activate the double talk detection which means that the DTMF tone will not be detected. Therefore a notchfilter can be programmed to filter out the echo of the dialtone, because the frequency of the dialtone is known. The center frequency and the bandwith of the notch filter can be programmed. Preliminary Data Sheet 219 DS3, 2003-07-11 DuSLIC 33H NLP-BNLEV-R Bit 7 NLP Background Noise Estimation Receive Level 6 5 4 3 Y 2 1 0 BN-LEV-R NLP Background Noise Estimation Receive Level: If the transmit signal is below PowBN-LEV-X (see Page 218) and the receive signal SLEC,R (see Figure 29) is below PowBN-LEV-R, the background noise estimator uses the transmit signal for the background noise estimation. Otherwise the background noise estimator is frozen. PowBN-LEV-R[dB] = SR,BN-LEV[dBm0] – 3.14 + AR1[dB] + GLEC-RI[dB] – 20*log10(π/2) SR,BN-LEV[dBm0]: Power detection level at digital input for freezing the background noise estimator AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 ≈ LR for LR ≤–2 dBr, AR1 ≈ –2 dB for LR > –2 dBr. BN-LEV-R = (6.02 × 16 + PowBN-LEV-R[dB]) × 2/(5 × log102) = (96.32 + PowBN-LEV-R[dB]) × 1.329 –96 dB ≤PowBN-LEV-R ≤0 dB Table 41 Range of PowBN-LEV-R BN-LEV-R PowBN-LEV-R[dB] 0x00 –96 … 0x7F 0 Preliminary Data Sheet 220 DS3, 2003-07-11 DuSLIC 34H DTMF-NBW-H DTMF Receiver Notch Filter Bandwidth High Byte Bit 7 6 5 4 3 2 Y 1 0 NBW-H This byte belongs to the DTMF-NBW-L byte described on Page 222. 34H NLP-BN-INC Bit 7 NLP Background Noise Estimation Increment 6 5 4 3 Y 2 1 0 BN-INC NLP Background Noise Estimation Increment: The TBN-INC increment time constant for the background noise estimation will be used, when the input signal is higher than the actual estimated background noise value. BN-INC = 0.680330873 × TBN-INC[dB/sec.] 1.5 dB/sec. ≤TBN-INC ≤375 dB/sec. Table 42 Range of TBN-INC BN-INC TBN-INC[dB/sec.] 0x01 1.5 … 0xFF 375 Preliminary Data Sheet 221 DS3, 2003-07-11 DuSLIC 35H Bit DTMF-NBW-L 7 DTMF Receiver Notch Filter Bandwidth Low Byte 6 5 4 3 Y 2 1 0 NBW-L DTMF Receiver Notch Filter Bandwidth: a NBW = 65536 × ------------- = NBW-L + 256 × NBW-H 1+a with F NBW [ Hz ] a = tan π ⋅ ---------------------------- 8000 0 Hz ≤FNBW ≤2000 Hz NBWL = MOD (NBW,256) NBWH = INT (NBW/256) Preliminary Data Sheet 222 DS3, 2003-07-11 DuSLIC 35H NLP-BNDEC Bit 7 NLP Background Noise Estimation Decrement 6 5 4 3 Y 2 1 0 BN-DEC NLP Background Noise Estimation Decrement: The TBN-DEC decrement time constant for the background noise estimation will be used, when the input signal is lower than the actual estimated background noise value. BN-DEC = 0.680330873 × TBN-DEC[dB/sec.] 1.5 dB/sec. ≤TBN-DEC ≤375 dB/sec. Table 43 Range of TBN-DEC BN-DEC TBN-DEC[dB/sec.] 0x01 1.5 … 0xFF 375 Preliminary Data Sheet 223 DS3, 2003-07-11 DuSLIC 36H DTMF-GAIN Gain Stage Control for DTMF Input Signal Bit 7 6 5 4 3 2 e Y 1 0 m DTMF Input Signal Gain: GDTMF[dB] = 20 × log1016 + 20 × log10[g/32768] ≈ 24.08 + 20 × log10[g/32768] –24.08 dB ≤GDTMF ≤23.95 dB with g = 2(9 - e) × (32 + m) and 0 ≤m ≤31, 0 ≤e ≤7 Table 44 Ranges of GDTMF[dB] dependent on “e” e DTMF Input Signal Gain GDTMF [dB] Range 0 23.95 dB ≥ GDTMF ≥ 18.06 dB 1 17.93 dB ≥ GDTMF ≥ 12.04 dB 7 –18.20 dB ≥ GDTMF ≥ –24.08 dB Alternative representation: Choose "e" as the next integer value which is higher than or equal to: log 10GDTMF G DTMF [ dB ] e ≥ 3 – log 2GDTMF = 3 – ------------------------------- ≈ 3 – ------------------------------log 102 6.02 m = G DTMF × 2 Table 45 2+e – 32 = 10 G DTMF [ dB ] -----------------------------20 × 2 2+e – 32 Example for DTMF-GAIN Calculation GDTMF[dB] GDTMF e m DTMF-GAIN 0 1 3 0 0x60 –6.02 0.5 4 0 0x80 6.02 2 2 0 0x40 36H NLP-BNMAX Preliminary Data Sheet NLP Background Noise Estimation Maximum Noise 224 Y DS3, 2003-07-11 DuSLIC Bit 7 6 5 4 3 2 1 0 BN-MAX NLP Background Noise Estimation Maximum Noise: The maximum allowed background noise BN-MAX is a coefficient that limits the background noise estimator so that the estimated background noise cannot exceed SX,BN-MAX. PowBN-MAX[dB] = SX,BN-MAX[dBm0] – 3.14 – GLEC-XO[dB] – 20*log10(π/2) SX,BN-MAX[dBm0]: Maximum background noise at digital output BN-MAX = (6.02 × 16 + PowBN-MAX[dB]) × 2/(5 × log102) = (96.32 + PowBN-MAX[dB]) × 1.329 –96 dB ≤PowBN-MAX ≤0 dB Table 46 Range of PowBN-MAX BN-MAX PowBN-MAX[dB] 0x00 –96 … 0x7F 0 Preliminary Data Sheet 225 DS3, 2003-07-11 DuSLIC 37H NLP-BNADJ Bit 7 NLP Background Noise Estimation Noise Adjustment 6 5 4 3 2 Y 1 0 BN-ADJ NLP Background Noise Estimation Noise Adjustment: The BN-ADJ coefficient adjusts the estimated background noise. It is possible to subtract (DeltaBN-ADJ < 0) or to add (DeltaBN-ADJ > 0) a constant level of noise from (to) the estimated background noise. BN-ADJ = DeltaBN-ADJ[dB] × 2/(5 × log102) = DeltaBN-ADJ[dB] × 1.329 –96 dB ≤DeltaBN-ADJ ≤96 dB Table 47 Range for DeltaBN-ADJ BN-ADJ DeltaBN-ADJ[dB] 0x81 –96 … 0x7F 96 Preliminary Data Sheet 226 DS3, 2003-07-11 DuSLIC 38H NLP-REMIN-ERLL Bit 7 NLP Residual Echo Minimum ERL for LEC + Line 6 5 4 3 Y 2 1 0 RE-MIN-ERLL NLP Residual Echo Minimum Echo Return Loss for LEC + Line: The RE-MIN-ERLL coefficients defines, when the NLP should switch from the simple mode to the comfort mode. If the estimated echo return loss for the hybrid plus the echo return loss for the LEC is higher than ERLLRE-MIN, the NLP switches to the comfort mode. In comfort mode, the NLP estimates the residual echo by itself. RE-MIN-ERLL = (2/(5 × log102)) × ERLLRE-MIN [dB] ERLLRE-MIN [dB] = SLEC,R[dB] – SLEC,TOUT[dB] = SR – SX + AR1 + GLEC,RI + GLEC,X0 (see Figure 29) The echo return loss is the difference between the signal level in receive direction SR and the echo level in transmit direction SX. 0 dB ≤ERLLRE-MIN ≤96 dB Table 48 Range of ERLLRE-MIN RE-MIN-ERLL ERLLRE-MIN[dB] 0x00 0 … 0x7F 96 Preliminary Data Sheet 227 DS3, 2003-07-11 DuSLIC 39H NLP-REEST-ERLL Bit 7 NLP Residual Echo Estimated ERL for LEC + Line 6 5 4 3 Y 2 1 0 RE-EST-ERLL NLP Residual Echo Estimated Echo Return Loss for LEC + Line: After being enabled, the NLP has no information regarding the echo return loss of the hybrid and the LEC. Therefore the NLP has two modes for the residual echo estimation: A simple mode, which is used after the NLP activation and a comfort mode which is used when the internal filters have usable values. In the simple mode the equation for the residual echo RE is: RE = SLEC,R – ERLLRE-EST Due to the equation above, ERLLRE-EST should be equal to the worst case echo return loss for the hybrid (which is exactly the worst case echo return loss between the LEC receive input signal and the LEC transmit input signal). For DuSLIC, the worst case echo return loss can be estimated by: ERLLRE-EST = AR1 + GLEC,RI + GLEC,XI – LR + LX AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 ≈ LR for LR ≤–2 dBr, AR1 ≈ –2 dB for LR > –2 dBr. For LR ≤–2 dBr: ERLLRE-EST ≈ GLEC,RI + GLEC,XI + LX A negative ERLLRE-EST value means that there is gain in the loop while a positive ERLLREEST value means that there is attenuation in the loop. RE-EST-ERLL = ERLLRE-EST[dB] × 2/(5 × log102) = ERLLRE-EST[dB] × 1.329 –96 dB ≤ERLLRE-EST ≤96 dB Table 49 Range of ERLLRE-EST RE-EST-ERLL ERLLRE-EST[dB] 0x81 –96 … 0x7F 96 Preliminary Data Sheet 228 DS3, 2003-07-11 DuSLIC 3AH LEC-LEN Bit 7 Line Echo Cancellation Length 6 5 4 3 Y 2 1 0 LEN Line Echo Cancellation Length: LEN = LEC Length[ms]/0.125 LEC Length has to be entered in multiples of 0.125 ms. The selected LEC Length has to be higher than the maximum line echo length but not higher than 8 ms. 0.125 ms ≤LEC Length ≤8 ms Table 5-1 Range of LEC Length LEN LEC Length 0x01 0.125 ms … 0x40 8 ms Preliminary Data Sheet 229 DS3, 2003-07-11 DuSLIC 3AH NLP-SDLEV-X Bit 7 NLP Speech Detection Transmit Direction Level 6 5 4 3 Y 2 1 0 SD-LEV-X NLP Speech Detection Transmit Direction Level: As a condition for valid speech detection in transmit direction, the transmit signal level has to be higher than SSD-LEV-X. For other conditions see SD-LEV-BN on Page 234 and SD-LEV-RE on Page 236. SSD-LEV-X[dB] = SX + GLEC,XI SD-LEV-X = (2/(5 × log102)) × (96.3 + SSD-LEV-X[dB]) –96 dB ≤SSD-LEV-X ≤0 dB Table 50 Range of SSD-LEV-X SD-LEV-X SSD-LEV-X[dB] 0x00 –96 … 0x7F 0 Preliminary Data Sheet 230 DS3, 2003-07-11 DuSLIC 3BH LEC-POWR Bit 7 Line Echo Cancellation Power Detection Level 6 5 4 Y 3 2 1 0 POWR Minimum Power Detection Level for Line Echo Cancellation: PowLECR[dB] = SR,LEC-POWR[dBm0] – 3.14 + AR1[dB] + GLEC-RI[dB] – 20*log10(π/2) SR,LEC-POWR[dBm0]: Minimum Power Detection Level for Line Echo Cancellation at digital input AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 ≈ LR for LR ≤–2 dBr, AR1 ≈ –2 dB for LR > –2 dBr. POWR = (6.02 × 16 + PowLECR[dB]) × 2/(5 × log102) = (96.32 + PowLECR[dB]) × 1.329 –96 dB ≤PowLECR ≤0 dB Table 51 Range of PowLECR POWR PowLECR[dB] 0x00 –96 … 0x7F 0 Example: AR1 = –3 dB SR,LEC-POWR = –40 dBm0 PowLECR = –46.14 dB POWR = 66.69 ≈ 67 = 0x43 Preliminary Data Sheet 231 DS3, 2003-07-11 DuSLIC 3BH NLP-SDLEV-R Bit 7 NLP Speech Detection Receive Direction Level 6 5 4 3 2 Y 1 0 SD-LEV-R NLP Speech Detection Receive Direction Level: If the receive signal level is below SSD-LEV-R, the receive speech detector doesn't detect speech. The transmit and receive speech detectors are used for detecting double talk. SD-LEV-R = (2/(5 × log102)) × (96.3 + SSD-LEV-R[dB]) SSD-LEV-R = SR + AR1 + GLEC,RI –96 dB ≤SSD-LEV-R ≤0 dB Table 52 Range of SSD-LEV-R SD-LEV-R SSD-LEV-R[dB] 0x00 –96 … 0x7F 0 Preliminary Data Sheet 232 DS3, 2003-07-11 DuSLIC 3CH LEC-DELP Bit 7 Line Echo Cancellation Delta Power 6 5 4 3 Y 2 1 0 DELP Line Echo Cancellation Delta Power for Double Talk Detection (DTD): DeltaPLEC[dB] = (SR – SX)DTDThr[dB] + AR1[dB] + GLEC-RI[dB] – GLEC-XI[dB] (SR – SX)DTDThr[dB]: Double Talk Detection threshold AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 ≈ LR for LR ≤–2 dBr, AR1 ≈ –2 dB for LR > –2 dBr. DELP = DeltaPLEC[dB] × 2/(5 × log102) = DeltaPLEC[dB] × 1.329 –96 dB ≤DeltaPLEC ≤96 dB Table 53 Range of DeltaPLEC DELP DeltaPLEC[dB] 0x81 –96 0x80 no detection … 0x7F 96 Example: AR1 = –3 dB expected echo signal < –15 dB →(SR – SX)DTDThr = –15 dB DeltaPLEC = 12 dB DELP = 16 = 0x10 Preliminary Data Sheet 233 DS3, 2003-07-11 DuSLIC 3CH NLP-SDLEV-BN Bit 7 NLP Speech Detection Receive BN Level 6 5 4 3 Y 2 1 0 SD-LEV-BN NLP Speech Detection Background Noise Level: As a condition for valid speech detection in transmit direction, the transmit signal level SX has to be higher than the estimated background noise plus DeltaSD-LEV-BN. For other conditions see SD-LEV-X on Page 230 and SD-LEV-RE on Page 236. SD-LEV-BN = (2/(5 × log102)) × DeltaSD-LEV-BN[dB]) 0 dB ≤DeltaSD-LEV-BN ≤96 dB Table 54 Range of DeltaSD-LEV-BN SD-LEV-BN DeltaSD-LEV-BN[dB] 0x00 0 … 0x7F 96 Preliminary Data Sheet 234 DS3, 2003-07-11 DuSLIC 3DH LEC-DELQ Bit 7 Line Echo Cancellation Delta Quality 6 5 4 3 Y 2 1 0 DELQ Line Echo Cancellation Delta Quality Between Shadow Filter and Main Filter: The higher DeltaQ is, the less copying between shadow filter and main filter takes place and the higher is the quality. DELQ = DeltaQ[dB] × 2/(5 × log102) = DeltaQ[dB] × 1.329 0 dB ≤DeltaQ ≤10 dB Table 55 Examples for DeltaQ DELQ DeltaQ[dB] 0x08 6.02 0x04 3.01 (typical) 0x03 2.26 0x02 1.505 Preliminary Data Sheet 235 DS3, 2003-07-11 DuSLIC 3DH NLP-SDLEV-RE Bit 7 NLP Speech Detection Receive RE Level 6 5 4 3 Y 2 1 0 SD-LEV-RE NLP Speech Detection Residual Echo Level: As a condition for valid speech detection in transmit direction, the transmit signal level SX has to be higher than the estimated residual echo plus DeltaSD-LEV-RE. Therefore, SD-LEV-RE prevents false decisions of the speech detector. A false decision can be a too optimistic estimation for the LEC echo return loss. Due to the hangover time for double talk (see SD-OT-DT on Page 238), this level should be higher than the control level residual echo coefficient (see CT-LEV-RE on Page 243). For other valid speech detection conditions see SD-LEV-X on Page 230 and SD-LEV-BN on Page 234. SD-LEV-RE = (2/(5 × log102)) × DeltaSD-LEV-RE[dB]) 0 dB ≤DeltaSD-LEV-RE ≤96 dB Table 56 Range of DeltaSD-LEV-RE SD-LEV-RE DeltaSD-LEV-RE[dB] 0x00 0 … 0x7F 96 Preliminary Data Sheet 236 DS3, 2003-07-11 DuSLIC 3EH LEC-GAIN-XI Line Echo Cancellation Input Gain Transmit Bit 7 6 5 4 3 Y 2 e 1 0 m Line Echo Cancellation Input Gain Transmit: It is important, that GLEC-XI[dB] will not be changed, so GLEC-XI[dB] = –GLEC-X0[dB] GLEC-XI[dB] = 20 × log1016 + 20 × log10[g/32768] ≈ 24.08 + 20 × log10[g/32768] –24.08 dB ≤GLEC-XI ≤23.95 dB with g = 29-e × (32 + m) and 0 ≤m ≤31, 0 ≤e ≤7 Table 57 Ranges of GLEC-XI[dB] Dependent on “e” e Input Gain GLEC-XI[dB] Range 0 23.95 dB ≥ GLEC-XI ≥ 18.06 dB 1 17.93 dB ≥ GLEC-XI ≥ 12.04 dB 7 –18.20 dB ≥ GLEC-XI ≥ –24.08 dB Alternative representation: Choose "e" as the next integer number which is bigger than or equal to: log 10GLEC – XI G LEC – XI [ dB ] e ≥ 3 – log 2GLEC – XI = 3 – ------------------------------------ ≈ 3 – -----------------------------------log 102 6.02 m = G LEC – XI × 2 Table 58 2+e – 32 = 10 G LEC – XI [ dB ] ---------------------------------20 × 2 2+e – 32 Example for LEC-GAIN-XI Calculation GLEC-XI[dB] GLEC-XI e m LEC-GAIN-XI 0 1 3 0 0x60 –6.02 0.5 4 0 0x80 6.02 2 2 0 0x40 Preliminary Data Sheet 237 DS3, 2003-07-11 DuSLIC 3EH NLP-SDOT-DT Bit 7 NLP Speech Detection Overhang Time for Double Talk 6 5 4 3 2 Y 1 0 SD-OT-DT NLP Speech Detection Overhang Time for Double Talk: Double talk exists, when speech is detected at the same time by the receive and the transmit speech detector. In that case, the NLP will be bypassed. To make sure that the silent end of a speech signal can pass the NLP, the bypass is extended by the overhang time tSD-OT-DT. SD-OT-DT = 0.5 × tSD-OT-DT[ms] 2 ms ≤tSD-OT-DT ≤500 ms Table 59 Range of tSD-OT-DT SD-OT-DT tSD-OT-DT[ms] 0x01 2 … 0xFA 500 Preliminary Data Sheet 238 DS3, 2003-07-11 DuSLIC 3FH LEC-GAIN-RI Line Echo Cancellation Input Gain Receive Bit 7 6 5 4 3 Y 2 e 1 0 m Line Echo Cancellation Input Gain Receive: GLEC-RI[dB] = 20 × log1016 + 20 × log10[g/32768] ≈ 24.08 + 20 × log10[g/32768] –24.08 dB ≤GLEC-RI ≤23.95 dB with g = 29-e × (32 + m) and 0 ≤m ≤31, 0 ≤e ≤7 Table 60 Ranges of GLEC-RI[dB] Dependent on “e” e Input Gain GLEC-RI[dB] Range 0 23.95 dB ≥ GLEC-RI ≥ 18.06 dB 1 17.93 dB ≥ GLEC-RI ≥ 12.04 dB 7 –18.20 dB ≥ GLEC-RI ≥ –24.08 dB Alternative representation: Choose "e" as the next integer number which is bigger than or equal to: log 10GLEC – RI G LEC – RI [ dB ] ≈ 3 – -----------------------------------e ≥ 3 – log 2GLEC – RI = 3 – ------------------------------------log 102 6.02 m = G LEC – RI × 2 Table 61 2+e – 32 = 10 G LEC – RI [ dB ] ----------------------------------20 × 2 2+e – 32 Example for LEC-GAIN-RI Calculation GLEC-RI[dB] GLEC-RI e m LEC-GAIN-RI 0 1 3 0 0x60 –6.02 0.5 4 0 0x80 6.02 2 2 0 0x40 Preliminary Data Sheet 239 DS3, 2003-07-11 DuSLIC 3FH NLP-ERLLIN-LP Bit 7 NLP Echo Return Loss Line LP Time Constant 6 5 4 3 Y 2 1 0 ERL-LIN-LP NLP Echo Return Loss Line Low Pass Time Constant: TERL-LIN-LP is a time constant for the hybrid echo return estimation. ERL-LIN-LP = 16384/TERL-LIN-LP[ms] 64.25 ms ≤TERL-LIN-LP ≤16.384 s Table 62 Range of TERL-LIN-LP ERL-LIN-LP TERL-LIN-LP[ms] 0xFF 64.25 … 0x01 16384 Preliminary Data Sheet 240 DS3, 2003-07-11 DuSLIC 40H LEC-GAIN-XO Line Echo Cancellation Output Gain Transmit Bit 7 6 5 4 3 Y 2 e 1 0 m Line Echo Cancellation Output Gain Transmit: It is important, that GLEC-X0[dB] will not be changed, so GLEC-X0[dB] = –GLEC-XI[dB] GLEC-X0[dB] = 20 × log1016 + 20 × log10[g/32768] ≈ 24.08 + 20 × log10[g/32768] –24.08 dB ≤GLEC-X0 ≤23.95 dB with g = 29-e × (32 + m) and 0 ≤m ≤31, 0 ≤e ≤7 Table 63 Ranges of GLEC-X0[dB] Dependent on “e” e Output Gain GLEC-X0[dB] Range 0 23.95 dB ≥ GLEC-X0 ≥ 18.06 dB 1 17.93 dB ≥ GLEC-X0 ≥ 12.04 dB 7 –18.20 dB ≥ GLEC-X0 ≥ –24.08 dB Alternative representation: Choose "e" as the next integer number which is bigger than or equal to: log 10GLEC – X0 G LEC – X0 [ dB ] e ≥ 3 – log 2GLEC – X0 = 3 – -------------------------------------- ≈ 3 – ------------------------------------6.02 log 102 m = G LEC – X0 × 2 Table 64 2+e – 32 = 10 G LEC – X0 [ dB ] -----------------------------------20 × 2 2+e – 32 Example for LEC-GAIN-X0 Calculation GLEC-X0[dB] GLEC-X0 e m LEC-GAIN-X0 0 1 3 0 0x60 –6.02 0.5 4 0 0x80 6.02 2 2 0 0x40 Preliminary Data Sheet 241 DS3, 2003-07-11 DuSLIC 40H NLP-ERLLEC-LP Bit 7 NLP Echo Return Loss LEC LP Time Constant 6 5 4 3 Y 2 1 0 ERL-LEC-LP NLP Echo Return Loss LEC Low Pass Time Constant: TERL-LEC-LP is a time constant for the LEC echo return estimation. ERL-LEC-LP = 16384/TERL-LEC-LP[ms] 64.25 ms ≤TERL-LEC-LP ≤16.384 s Table 65 Range of TERL-LEC-LP ERL-LEC-LP TERL-LEC-LP[ms] 0xFF 64.25 … 0x01 16384 Preliminary Data Sheet 242 DS3, 2003-07-11 DuSLIC 41H NLP-CTLEV-RE Bit 7 NLP Control RE Level 6 5 4 Y 3 2 1 0 CT-LEV-RE NLP Control Level Residual Echo: If the speech level after the LEC is above the estimated residual echo plus DeltaCT-LEV-RE, the NLP is inactive (bypassed). Otherwise the NLP is active, when there is no double talk. CT-LEV-RE = (2/(5 × log102)) × DeltaCT-LEV-RE[dB]) 0 dB ≤DeltaCT-LEV-RE ≤96 dB Table 66 Range of DeltaCT-LEV-RE CT-LEV-RE DeltaCT-LEV-RE[dB] 0x00 0 … 0x7F 96 Preliminary Data Sheet 243 DS3, 2003-07-11 DuSLIC 42H NLP-CTRL Bit NLP Control Y 7 6 5 4 3 2 1 0 0 0 0 0 0 NLPNM NLPNG NLPOLDC NLP-NM When the echo path is cut of by the NLP, there are two possible ways to add a comfort noise to the line. This ensures that the subscriber doesn´t assume a dead line. NLP-NM = 0 White noise is selected. NLP-NM = 1 Sign noise (spectrum shaped noise) is selected. NLP-NG = 0 The noise generator is off. NLP-NG = 1 The noise generator is active. NLP-OLDC = 0 After the activation of the NLP the coefficients are copied from the I/O-buffer to the local RAM. NLP-OLDC = 1 The NLP uses the old coefficients. NLP-NG NLP-OLDC Preliminary Data Sheet 244 DS3, 2003-07-11 DuSLIC 43H CIS-LEV-H Bit 7 Caller ID Sender Level High Byte 6 5 4 3 Y 2 1 0 LEV-H 44H CIS-LEV-L Bit 7 Caller ID Sender Level Low Byte 6 5 4 3 Y 2 1 0 LEV-L Caller ID Sender Level: LevCIS[dB] = LevCIS[dBm0] – 3.14 – 3.37 LevCIS[dB] = LevCIS[dBm] – LR[dBr] – 3.14 – 3.37 LEV = 32767 × 10 (LevCIS[dB]/20) –90.31 dB ≤LevCIS ≤0 dB LEV-L = MOD (LEV,256) LEV-H = INT (LEV/256) Table 67 Range of LevCIS LEV LevCIS[dB] 0 – ∞ (signal off) 1 –90.31 32767 0 Preliminary Data Sheet 245 DS3, 2003-07-11 DuSLIC 45H Bit CIS-BRS 7 Caller ID Sender Buffer Request Size 6 5 4 3 Y 2 1 0 BRS Caller ID Sender Buffer Request Size: 0 ≤BRS ≤46 CIS-BRS is a threshold to be set within the Caller ID sender buffer (CIS-DAT, 48 bytes). If the number of bytes in the CID sender buffer falls below the buffer request size, an interrupt is generated. This is the indication to fill up the buffer again. The first bit will be sent if the number of bytes in the CID sender buffer exceeds the buffer request size (start sending with BRS + 1 number of bytes). The buffer request size BRS must always be smaller than the number of bytes to be sent: BRS < Number of bytes to be sent Typical values: 10 - 30. Preliminary Data Sheet 246 DS3, 2003-07-11 DuSLIC 46H Bit CIS-SEIZ-H 7 Caller ID Sender Number of Seizure Bits High Byte 6 5 4 3 2 Y 1 0 SEIZ-H 47H Bit CIS-SEIZ-L 7 Caller ID Sender Number of Seizure Bits Low Byte 6 5 4 3 2 Y 1 0 SEIZ-L Caller ID Sender Number of Seizure Bits: (only if High Level Framing is selected in the CIS/LEC-MODE register (see Page 248)) 0 ≤SEIZ ≤32767 SEIZ-L = MOD (SEIZ,256) SEIZ-H = INT (SEIZ/256) Preliminary Data Sheet 247 DS3, 2003-07-11 DuSLIC 48H Bit CIS-MARK-H 7 Caller ID Sender Number of Mark Bits High Byte 6 5 4 3 Y 2 1 0 MARK-H 49H Bit CIS-MARK-L 7 Caller ID Sender Number of Mark Bits Low Byte 6 5 4 3 Y 2 1 0 MARK-L Caller ID Sender Number of Mark Bits: (only if High Level Framing is selected in the CIS/LEC-MODE register) 0 ≤MARK ≤32767 MARK-L = MOD (MARK,256) MARK-H = INT (MARK/256) 4AH Bit CIS/LECMODE 7 CIS/LEC Mode Setting 6 5 LECLECUTDXADAPT FREEZE SUM Y 4 3 2 1 0 UTDRSUM 0 NLP-EN CISFRM CISV23 Attention: Bit 3 must be set to 0. Preliminary Data Sheet 248 DS3, 2003-07-11 DuSLIC LEC-ADAPT Line Echo Cancellation Adaptation Start. The LEC-ADAPT bit is only evaluated if the LEC-EN is changed from 0 to 1. To initialize the LEC coefficients to 0 requires the LEC-ADAPT bit set to 0 followed by the LEC-EN bit changed from 0 to 1. It is not possible to reset the LEC coefficients to 0 while the LEC is running. The LEC has to be disabled first by setting bit LEC-EN to 0 and then it is necessary to enable the LEC again (LEC-EN = 1, LEC-ADAPT = 0). If valid coefficients from a former LEC adaptation are present in the RAM, it is possible to activate the LEC with this coefficents by setting bit LEC-ADAPT to 1. It is also possible to read out adapted coefficients from the LEC for external storage and to reuse these coefficients as a start up value for the next connection (see the available Application Notes). LEC-ADAPT = 0 Line Echo Cancellation coefficients initialized with zero. LEC-ADAPT = 1 Line Echo Cancellation coefficients initialized with old coefficients. LEC-FREEZE Line Echo Cancellation Adaptation Freeze LEC-FREEZE = 0 No freezing of coefficients LEC-FREEZE = 1 Freezing of coefficients CIS-FRM CIS-V23 Caller ID Sender Framing CIS-FRM = 0 Low-level framing: all data for CID transmissions must be written to the CID Buffer including channel seizure and mark sequence, start and stop bits. CIS-FRM = 1 High-level framing: channel seizure and mark sequence as well as start and stop bits are automatically inserted by the SLICOFI-2x. Only transmission bytes from the Data Packet (see Figure 30) have to be written to the CIS buffer. Caller ID Sender Mode CIS-V23 = 0 Bell 202 selected CIS-V23 = 1 V.23 selected Preliminary Data Sheet 249 DS3, 2003-07-11 DuSLIC 4BH Bit UTD-CF-H 7 Universal Tone Detection Center Frequency High Byte 6 5 4 3 Y 2 1 0 CF-H 4CH Bit UTD-CF-L 7 Universal Tone Detection Center Frequency Low Byte 6 5 4 3 Y 2 1 0 CF-L Universal Tone Detection Center Frequency: ··· 2 π f c [ Hz ] CF = 32768 × cos ----------------------- 8000 0 < fC < 4000 Hz CF-L = MOD (CF,256) CF-H = INT (CF/256) Preliminary Data Sheet 250 DS3, 2003-07-11 DuSLIC 4DH Bit UTD-BW-H 7 Universal Tone Detection Bandwidth High Byte 6 5 4 3 Y 2 1 0 BW-H 4EH Bit UTD-BW-L 7 Universal Tone Detection Bandwidth Low Byte 6 5 4 3 Y 2 1 0 BW-L Universal Tone Detection Bandwidth: a BW = 65536 × ------------1+a with f BW [ Hz ] × π a = tan --------------------------------- 8000 0 < fBW < 2000 Hz BW-L = MOD (BW,256) BW-H = INT (BW/256) Preliminary Data Sheet 251 DS3, 2003-07-11 DuSLIC 4FH Bit UTD-NLEV 7 Universal Tone Detection Noise Level 6 5 4 3 2 Y 1 0 NLEV Universal Tone Detection Noise Level: NLEV = 32768 × 10(LevN[dB])/20 –96 dB ≤LevN ≤–42.18 dB Preliminary Data Sheet 252 DS3, 2003-07-11 DuSLIC 50H Bit UTD-SLEV-H Universal Tone Detection Signal Level High Byte 7 6 5 4 3 2 Y 1 0 SLEV-H 51H Bit UTD-SLEV-L Universal Tone Detection Signal Level Low Byte 7 6 5 4 3 2 Y 1 0 SLEV-L Universal Tone Detection Signal Level: Calculation for Transmit: LevS[dB] = LevS[dBm0] – 3.14 – 20*log10(π/2) LevS[dB] = LevS[dBm] – Lx[dBr] – 3.14 – 20*log10(π/2) Calculation for Receive: LevS[dB] = LevS[dBm0] – 3.14 + AR1[dB] – 20*log10(π/2) LevS[dB] = LevS[dBm] – LR[dBr] – 3.14 + AR1[dB] – 20*log10(π/2) AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 ≈ LR for LR ≤–2 dBr, AR1 ≈ –2 dB for LR > –2 dBr. SLEV = 32768 × 10(LevS[dB])/20 – NLEV –96 dB ≤LevS ≤0 dB Signal Level: SLEV-L = MOD (SLEV,256) SLEV-H = INT (SLEV/256) UTD for Receive and Transmit: By enabling the UTD, the coefficients in the UTD registers are copied to the main memory. Therefore, different coefficients can be set for receive and transmit direction. Preliminary Data Sheet 253 DS3, 2003-07-11 DuSLIC 52H UTD-DELT Bit 7 Universal Tone Detection Delta 6 5 4 3 Y 2 1 0 DELT Universal Tone Detection Delta Inband/Outband: DELT = Sign(DeltaUTD) × 128 × 10–|DeltaUTD[dB]|/20 –42 dB ≤DeltaUTD ≤42 dB Example: Detection of a tone that is between 1975 Hz and 2025 Hz → fC = 2000 Hz • • fBW = 50 Hz Tone at 2025 Hz: Outband = –3 dB, Inband = –3 dB (see Table 68) DeltaUTD = 0 dB →DELT = 128 = 0x80 fBW = 500 Hz Tone at 2025 Hz: Outband = –20 dB, Inband = –0.04 dB (see Table 68) DeltaUTD ≈ 20 dB →DELT = 13 = 0x0D Table 68 UTD Inband/Outband Attenuation f Outband Inband fC ± fBW/0.2 fC ± fBW/2 fC ± fBW/20 fC ± fBW/200 –0.04 dB –20 dB –3 dB –3 dB –20 dB –0.04 dB –40 dB –0 dB Preliminary Data Sheet 254 DS3, 2003-07-11 DuSLIC 53H Bit UTD-RBRK 7 Universal Tone Detection Recognition Break Time 6 5 4 3 2 Y 1 0 RBRK Allowed Recognition Break Time for Universal Tone Detection: RBRK = RBRKTime[ms]/4 RBRKTime must be entered in multiples of 4 ms. 0 ms ≤RBRKTime ≤1000 ms For an example, see Figure 64. Preliminary Data Sheet 255 DS3, 2003-07-11 DuSLIC 54H UTD-RTIME Bit 7 Universal Tone Detection Recognition Time 6 5 4 3 2 Y 1 0 RTIME Universal Tone Detection Recognition Time: RTIME = RTime[ms]/16 RTime must be entered in multiples of 16 ms. 0 ms ≤RTime ≤4000 ms Tone 1 0 U T D i-O K b it (IN T R E G 3 ) t R B R K T im e 1 R T im e 0 t U T D i-O K b it (IN T R E G 3 ) R B R K T im e 1 R T im e t 0 duslic_0013_RBRK_timing Figure 64 Example for UTD Recognition Timing Preliminary Data Sheet 256 DS3, 2003-07-11 DuSLIC 55H Bit UTD-EBRK 7 UTD Allowed Tone End Detection Break Time 6 5 4 3 2 Y 1 0 EBRK Allowed tone end detection break time for Universal Tone Detection: EBRK = EBRKTime [ms] 0 ms ≤EBRKTime ≤255 ms For an example, see Figure 65. Preliminary Data Sheet 257 DS3, 2003-07-11 DuSLIC 56H UTD-ETIME Bit 7 UTD Tone End Detection Time 6 5 4 3 Y 2 1 0 ETIME Tone End Detection Time for Universal Tone Detection: ETIME = ETime[ms]/4 ETime must be entered in multiples of 4 ms. 0 ms ≤ETime ≤1000 ms Tone 1 0 U T D i-O K b it (IN T R E G 3 ) t E B R K T im e 1 E T im e 0 t U T D i-O K b it (IN T R E G 3 ) E B R K T im e 1 E T im e 0 t duslic_0014_EBRK_timing Figure 65 5.2.3.4 Example for UTD Tone End Detection Timing Recommended NLP Coefficients Table 69 shows recommended NLP register values and the respective parameter values. Preliminary Data Sheet 258 DS3, 2003-07-11 DuSLIC Table 69 Recommended NLP Coefficients Register Name Register Value Parameter Value NLP-POW-LPF 0x6A TPOW-LPF = 2.4 msec NLP-POW-LPS 0x2A TPOW-LPS = 24.4 msec NLP-BN-LEV-X 0x44 PowBN-LEV-X = –45.1 dB NLP-BN-LEV-R 0x44 PowBN-LEV-R = –45.1 dB NLP-BN-INC 0x10 TBN-INC = 23.5 dB/sec NLP-BN-DEC 0x40 TBN-DEC = 94.1 dB/sec NLP-BN-MAX 0x40 PowBN-MAX = –48.0 dB NLP-BN-ADJ 0x04 DeltaBN-ADJ = 3.0 dB NLP-RE-MIN-ERLL 0x10 ERLLRE-MIN = 12.0 dB NLP-RE-EST-ERLL 0x0C ERLLRE-EST = 9.0 dB NLP-SD-LEV-X 0x44 SSD-LEV-X = –45.1 dB NLP-SD-LEV-R 0x44 SSD-LEV-R = –45.1 dB NLP-SD-LEV-BN 0x0C DeltaSD-LEV-BN = 9.0 dB NLP-SD-LEV-RE 0x10 DeltaSD-LEV-RE = 12.0 dB NLP-SD-OT-DT 0x3C tSD-OT-DT = 120.0 msec NLP-ERL-LIN-LP 0x20 TERL-LIN-LP = 512.0 msec NLP-ERL-LEC-LP 0x10 TERL-LEC-LP = 1024.0 msec NLP-CT-LEV-RE 0x0C DeltaCT-LEV-RE = 9.0 dB Preliminary Data Sheet 259 DS3, 2003-07-11 DuSLIC 5.2.4 IOM-2 Interface Command/Indication Byte The Command/Indication (C/I) channel is used to communicate real time status information and for fast controlling of the DuSLIC. Data on the C/I channel are continuously transmitted in each frame until new data are sent. Data Downstream C/I – Channel Byte (Receive) – IOM-CIDD The first six CIDD data bits control the general operating modes for both DuSLIC channels. According to the IOM-2 specifications, new data must be present for at least two frames to be accepted. Table 70 M2, M1, M0: General Operating Mode CIDD M2 M1 M0 SLICOFI-2 Operating Mode (for details see “Overview of all DuSLIC Operating Modes” on Page 74) 1 1 1 Sleep, Power Down (PDRx) 0 0 0 Power Down High Impedance (PDH) 0 1 0 Any Active mode 1 0 1 Ringing (ACTR Burst On) 1 1 0 Active with Metering 1 0 0 Ground Start 0 0 1 Ring Pause CIDD Bit Data Downstream C/I – Channel Byte N 7 6 5 4 3 2 1 0 M2A M1A M0A M2B M1B M0B MR MX ) M2A, M1A, M0A Select operating mode for DuSLIC channel A M2B, M1B, M0B Select operating mode for DuSLIC channel B MR, MX Handshake bits Monitor Receive and Transmit (see “IOM-2 Interface Monitor Transfer Protocol” on Page 133) Preliminary Data Sheet 260 DS3, 2003-07-11 DuSLIC Data Upstream C/I – Channel Byte (Transmit) – IOM-CIDU This byte is used to quickly transfer the most important and time-critical information from the DuSLIC. Each transfer from the DuSLIC lasts for at least 2 consecutive frames. CIDU Bit 7 Data Upstream C/I – Channel Byte 6 5 4 3 N 00H 2 INT-CHA HOOKA GNDKA INT-CHB HOOKB GNDKB 1 0 MR MX INT-CHA Interrupt information channel A INT-CHA = 0 No interrupt in channel A INT-CHA = 1 Interrupt in channel A HOOKA Hook information channel A HOOKA = 0 On-hook channel A HOOKA = 1 Off-hook channel A GNDKA Ground key information channel A GNDKA = 0 No longitudinal current detected GNDKA = 1 Longitudinal current detected in channel A INT-CHB Interrupt information channel B INT-CHB = 0 No interrupt in channel B INT-CHB = 1 Interrupt in channel B HOOKB Hook information channel B HOOKB = 0 On-hook Channel B HOOKB = 1 Off-hook Channel B GNDKB Ground key information channel B GNDKB = 0 No longitudinal current detected GNDKB = 1 Longitudinal current detected in channel B MR, MX Handshake bits Monitor Receive and Transmit (see “IOM-2 Interface Monitor Transfer Protocol” on Page 133) Preliminary Data Sheet 261 DS3, 2003-07-11 DuSLIC 5.2.5 Programming Examples of the SLICOFI-2 5.2.5.1 Microcontroller Interface SOP Write to Channel 0 Starting After the Channel Specific Read-only Registers 01000100 First command byte (SOP write for channel 0) 00010101 Second command byte (Offset to BCR1 register) 00000000 Contents of BCR1 register 00000000 Contents of BCR2 register 00010001 Contents of BCR3 register 00000000 Contents of BCR4 register 00000000 Contents of BCR5 register Command Offset BCR1 BCR2 BCR3 BCR4 BCR5 DIN DCLK CS ezm220121 Figure 66 Waveform of Programming Example SOP-Write to Channel 0 SOP Read from Channel 1 Reading Out the Interrupt Registers 11001100 First command byte (SOP read for channel 1). 00000111 Second command byte (Offset to Interrupt register 1). The SLICOFI-2 will send data when it has completely received the second command byte. 11111111 Dump byte (This byte is always FFH). 11000000 Interrupt register INTREG1 (An interrupt has occurred, Off-hook was detected). 00000010 Interrupt register INTREG2 (I/O pin 2 is ‘1’). 00000000 Interrupt register INTREG3 00000000 Interrupt register INTREG4 Preliminary Data Sheet 262 DS3, 2003-07-11 DuSLIC Command Offset Dump Intreg 1 Intreg 2 Intreg 3 Intreg 4 DIN DOUT DCLK CS ezm220122 Figure 67 5.2.5.2 Waveform of Programming Example SOP Read from Channel 0 IOM-2 Interface An example with the same programming sequence as before, using the IOM-2 interface is presented here to show the differences between the microcontroller interface and the IOM-2 interface. SOP Write to Channel 0 Starting After the Channel-Specific Read-only Registers Monitor MR/MX Monitor data down data up 10000001 10 01000100 11 01000100 10 00010101 11 00010101 10 00000000 11 00000000 10 00000000 11 00000000 10 00010001 11 00010001 10 00000000 11 00000000 10 11111111 11 11111111 11 11111111 01 11111111 01 11111111 11 11111111 01 11111111 11 11111111 01 11111111 11 11111111 01 11111111 11 11111111 01 11111111 11 11111111 01 11111111 11 11111111 01 11111111 11 MR/MX Comment IOM-2 address second byte First command byte (SOP write for channel 0) First command byte second time Second command byte (Offset to BCR1 register) Second command byte second time Contents of BCR1 register Contents of BCR1 register second time Contents of BCR2 register Contents of BCR2 register second time Contents of BCR3 register Contents of BCR3 register second time Contents of BCR4 register Contents of BCR4 register second time No more information (dummy byte) Signaling EOM (end of message) by holding MX bit at ‘1’. Because the SLICOFI-2 has an open command structure, there is no fixed command length. The IOM-2 handshake protocol allows for an infinite length of a data stream. Therefore, the host must terminate the data transfer by sending an end-of-message signal (EOM) to the SLICOFI-2. The SLICOFI-2 will abort the transfer only if the host tries to write or read beyond the allowed maximum offset given by the different types of commands. Each transfer must start with the SLICOFI-2-specific IOM-2 address (81H) Preliminary Data Sheet 263 DS3, 2003-07-11 DuSLIC and must end with an EOM of the handshake bits. Appending a command immediately to its predecessor without an EOM in between is not allowed. When reading interrupt registers, SLICOFI-2 stops the transfer after the fourth register in IOM-2 mode. This is to prevent some host chips from reading 16 bytes because they cannot terminate the transfer after n bytes. Preliminary Data Sheet 264 DS3, 2003-07-11 DuSLIC SOP-Read from Channel 1 Reading Out the Interrupt Registers Monitor MR/MX Monitor MR/MX Comment data down data up 10000001 10 10000001 10 11001100 11 11001100 10 00001000 11 00001000 10 11111111 11 11111111 11 11111111 01 11111111 01 11111111 11 11111111 01 11111111 11 11111111 01 11111111 11 11111111 01 11111111 11 11111111 11 11111111 11 1111111111IOM-2 address first byte 1111111101IOM-2 address second byte 1111111101First command byte (SOP read for channel 1) 1111111111First command byte second time 1111111101Second command byte (offset to interrupt register 1) 1111111111Second command byte second time 1111111101Acknowledgement for the second command byte 1000000110IOM-2 Address first byte (answer) 1000000110IOM-2 Address second byte 1100000011Interrupt register INTREG1 1100000010Interrupt register INTREG1 second time 0000001011Interrupt register INTREG2 0000001010Interrupt register INTREG2 second time 0000000011Interrupt register INTREG3 0000000010Interrupt register INTREG3 second time 0000000011Interrupt register INTREG4 0000000010Interrupt register INTREG4 second time 0100110111SLICOFI-2 sends the next register 1111111111SLICOFI-2 aborts transmission Preliminary Data Sheet 265 DS3, 2003-07-11 DuSLIC 5.3 SLICOFI-2S Command Structure and Programming This section describes only the SLICOFI-2S PEB 3264 command structure and programming. Therefore, this section pertains only to the DuSLIC-S and DuSLIC-S2 chip sets. 5.3.1 SOP Command The Status Operation (SOP) command provides access to the configuration and status registers of the SLICOFI-2S. Common registers change the mode of the entire SLICOFI-2S chip. All other registers are channel-specific. It is possible to access single or multiple registers. Multiple register access is achieved by an automatic offset increment. Write access to read-only registers is ignored and does not abort the command sequence. Offsets may change in future versions of the SLICOFI-2S. Attention: To ensure proper functionality, it is essential that all unused register bits have to be filled with zeros. 5.3.1.1 00H SOP Register Overview REVISION Revision Number (read-only) REV[7:0] 01H CHIPID 1 Chip Identification 1 (read-only) for internal use only 02H CHIPID 2 Chip Identification 2 (read-only) for internal use only 03H CHIPID 3 Chip Identification 3 (read-only) for internal use only 04H FUSE1 Fuse Register 1 for internal use only 05H PCMC1 DBL-CLK PCM Configuration Register 1 X-SLOPE Preliminary Data Sheet R-SLOPE NO-DRIVE-0 266 SHIFT PCMO[2:0] DS3, 2003-07-11 DuSLIC 06H XCR Extended Configuration Register 0 07H INTREG1 INT-CH 08H HOOK READY INTREG3 GNDK GNKP CHKR1 RSTAT 0 ICON 0 VTRLIM 0 0 0 0 OTEMP SYNC-FAIL CHKR2 IO[4:1]-DU 0 0 0 0 0 0 0 0 0 Interrupt Register 4 (read-only) 0 0 0 Checksum Register 1 (High Byte) (read-only) SUM-OK 0CH 0 Interrupt Register 3 (read-only) INTREG4 0 0BH 0 Interrupt Register 2 (read-only) 0 0AH 0 Interrupt Register 1 (read-only) INTREG2 0 09H ASYNCH-R CHKSUM-H[6:0] Checksum Register 2 (Low Byte) (read-only) CHKSUM-L[7:0] 0DH LMRES1 Level Metering Result 1 (High Byte) (read-only) LM-VAL-H[7:0] 0EH LMRES2 Level Metering Result 2 (Low Byte) (read-only) LM-VAL-L[7:0] 0FH FUSE2 Fuse Register 2 for internal use only 10H FUSE3 Fuse Register 3 for internal use only Preliminary Data Sheet 267 DS3, 2003-07-11 DuSLIC 11H MASK READY-M 12H Mask Register HOOK-M IOCTL1 GNDK-M GNKP-M ICON-M VTRLIM-M IOCTL2 IO[4:1]-M I/O Control Register 2 IO[4:1]-OEN 14H IOCTL3 IO[4:1]-DD I/O Control Register 3 DUP[3:0] 15H BCR1 17H HIT BCR2 REXT-EN SOFT-DIS BCR3 19H TTX-DIS1) LIN TTX-12K2) 0 PCMX-EN ACTL SEL-SLIC[1:0] HIM-AN AC-XGAIN 0 PDOT-DIS 0 0 0 CRAM-EN IM-DIS AX-DIS AR-DIS FRX-DIS FRR-DIS HPX-DIS HPR-DIS 0 0 0 0 0 0 0 COR8 PTG TG2-EN TG1-EN 0 0 0 0 Reserved DSCR DTMF Sender Configuration Register DG-KEY[3:0] 1BH ACTR Basic Configuration Register 4 0 1AH REVPOL Basic Configuration Register 3 BCR4 TH-DIS 0 Basic Configuration Register 2 MU-LAW 18H DUP-IO[3:0] Basic Configuration Register 1 HIR 16H SYNC-M I/O Control Register 1 IO[4:1]-INEN 13H OTEMP-M Reserved 0 Preliminary Data Sheet 0 0 0 268 DS3, 2003-07-11 DuSLIC 1CH LMCR1 TEST-EN Level Metering Configuration Register 1 LM-EN LM-THM PCM2DC LM2 LM-ONCE LM-MASK DC-AD16 PCM 1DH LMCR2 LM-NOTCH 1EH LM-FILT LMCR3 AC-SHORTEN 1FH Level Metering Configuration Register 2 LM-RECT RAMP-EN LM-SEL[3:0] Level Metering Configuration Register 3 RTR-SEL OFR1 LM-ITIME[3:0] RNG-OFFSET[1:0] Offset Register 1 (High Byte) OFFSET-H[7:0] 20H OFR2 Offset Register 2 (Low Byte) OFFSET-L[7:0] 21H PCMR1 PCM Receive Register 1 R1-HW 22H Reserved 23H Reserved 24H Reserved 25H PCMX1 R1-TS[6:0] PCM Transmit Register 1 X1-HW Preliminary Data Sheet X1-TS[6:0] 269 DS3, 2003-07-11 DuSLIC 26H Reserved 27H Reserved 28H Reserved 29H TSTR1 PD-AC-PR 2AH Test Register 1 PD-AC-PO TSTR2 0 TSTR3 2DH 0 TSTR4 OPIM-AN PD-AC-GN PD-GNKC PD-OFHC PD-OVTC PD-DC-AD PD-DC-DA PD-DCBUF 0 PD-TTX-A2) PD-HVI AC-DLB128K AC-DLB32K AC-DLB8K 0 0 Test Register 3 0 2CH PD-AC-DA Test Register 2 PD-DC-PR 2BH PD-AC-AD AC-DLB-4M Test Register 4 OPIM-4M TSTR5 0 COR-64 0 0 0 0 Test Register 5 0 0 1) Only for DuSLIC-S; is set to 1 for DuSLIC-S2. 2) Only for DuSLIC-S; is set to 0 for DuSLIC-S2. Preliminary Data Sheet COX-16 DC-POFIHI 270 DC-HOLD 0 0 0 DS3, 2003-07-11 DuSLIC 5.3.1.2 00H SOP Register Description REVISION Bit 7 Revision Number (read-only) 6 5 4 curr. rev. 3 2 N 1 0 REV[7:0] REV[7:0] 01H Bit Current revision number of the SLICOFI-2S. CHIPID 1 7 Chip Identification 1 (read-only) 6 5 4 3 hw 2 N 1 0 for internal use only 02H Bit CHIPID 2 7 Chip Identification 2 (read-only) 6 5 4 3 hw 2 N 1 0 for internal use only 03H Bit CHIPID 3 7 Chip Identification 3 (read-only) 6 5 4 3 hw 2 N 1 0 for internal use only 04H Bit FUSE1 7 Fuse Register 1 6 5 hw 4 3 2 N 1 0 for internal use only Preliminary Data Sheet 271 DS3, 2003-07-11 DuSLIC PCMC1 05H Bit 7 PCM Configuration Register 1 6 5 4 DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 DBL-CLK X-SLOPE R-SLOPE NODRIVE-0 SHIFT 00H 3 SHIFT N 2 1 0 PCMO[2:0] Clock mode for the PCM interface (see Figure 53 on Page 125). DBL-CLK = 0 Single clocking is used. DBL-CLK = 1 Double clocking is used. Transmit Slope (see Figure 53 on Page 125). X-SLOPE = 0 Transmission starts with rising edge of the clock. X-SLOPE = 1 Transmission starts with falling edge of the clock. Receive Slope (see Figure 53 on Page 125). R-SLOPE = 0 Data is sampled with falling edge of the clock. R-SLOPE = 1 Data is sampled with rising edge of the clock. Driving Mode for Bit 0 (only available in single-clocking mode). NO-DRIVE = 0 Bit 0 is driven the entire clock period. NO-DRIVE = 1 Bit 0 is driven during the first half of the clock period only. Shifts the access edges by one clock cycle in double clocking mode. SHIFT = 0 No shift takes place. SHIFT = 1 Shift takes place. PCMO[2:0] All PCM timing is moved by PCMO data periods against the FSC signal. PCMO[2:0] = 0 0 0 No offset is added. PCMO[2:0] = 0 0 1 One data period is added. … PCMO[2:0] = 1 1 1 Preliminary Data Sheet Seven data periods are added. 272 DS3, 2003-07-11 DuSLIC 06H Bit XCR Extended Configuration Register 00H N 7 6 5 4 3 2 1 0 0 ASYNCH -R 0 0 0 0 0 0 ASYNCH-R Enables asynchronous ringing in case of internal or external ringing. ASYNCH-R = 0 Internal or external ringing with zero crossing selected ASYNCH-R = 1 Asynchronous ringing selected. Preliminary Data Sheet 273 DS3, 2003-07-11 DuSLIC 07H Bit INT-CH HOOK GNDK GNKP INTREG1 Interrupt Register 1 (read-only) 7 6 5 4 3 INT-CH HOOK GNDK GNKP ICON 80H 2 Y 1 VTRLIM OTEMP 0 SYNCFAIL Interrupt channel bit. This bit indicates that the corresponding channel caused the last interrupt. Will be set automatically to zero after all interrupt registers have been read. INT-CH = 0 No interrupt in corresponding channel. INT-CH = 1 Interrupt caused by corresponding channel. On/Off-hook information for the loop in all operating modes, filtered by DUP (Data Upstream Persistence) counter and interrupt generation masked by the HOOK-M bit. A change of this bit generates an interrupt. HOOK = 0 On-hook. HOOK = 1 Off-hook. Ground key or ground start information via the IL pin in all active modes, filtered for AC suppression by the DUP counter and interrupt generation masked by the GNDK-M bit. A change of this bit generates an interrupt. GNDK = 0 No longitudinal current detected. GNDK = 1 Longitudinal current detected (ground key or ground start). Ground key polarity. Indicates the active ground key level (positive/negative) interrupt generation masked by the GNKP-M bit. A change of this bit generates an interrupt. This bit can be used to obtain information about interference voltage influence. GNKP = 0 Negative ground key threshold level active. GNKP = 1 Positive ground key threshold level active. Preliminary Data Sheet 274 DS3, 2003-07-11 DuSLIC ICON VTRLIM OTEMP Constant current information. Filtered by DUP-IO counter and interrupt generation masked by the ICON-M bit. A change of this bit generates an interrupt. ICON = 0 Resistive or constant voltage feeding. ICON = 1 Constant current feeding. Exceeding of a programmed voltage threshold for the TIP/RING voltage, filtered by the DUP-IO counter and interrupt generation masked by the VTRLIM-M bit. A change of this bit causes an interrupt. The voltage threshold for the TIP/RING voltage is set in CRAM (calculated with DuSLICOS DC Control Parameter 2/4: Tip-Ring Threshold). VTRLIM = 0 Voltage at Tip/Ring is below the limit. VTRLIM = 1 Voltage at Tip/Ring is above the limit. Thermal overload warning from the SLIC-S/-S2 line drivers masked by the OTEMP-M bit. An interrupt is only generated if the OTEMP bit changes from 0 to1. OTEMP = 0 Temperature at SLIC-S/-S2 is below the limit. OTEMP = 1 Temperature at SLIC-S/-S2 is above the limit. In case of bit PDOT-DIS = 0 (register BCR2) the DuSLIC is switched automatically into PDH mode and OTEMP is hold at 1 until the SLICOFI-2S is set to PDH by a CIOP/CIDD command. SYNC-FAIL Failure of the synchronization of the IOM-2/PCM Interface. An interrupt is only generated if the SYNC-FAIL bit changes from 0 to 1. Resynchronization of the PCM interface can be done with the Resynchronization command (see Chapter 5) SYNC-FAIL = 0 Synchronization OK. SYNC-FAIL = 1 Synchronization failure. Preliminary Data Sheet 275 DS3, 2003-07-11 DuSLIC 08H INTREG2 Bit Interrupt Register 2 (read-only) 7 6 0 5 READY RSTAT 4 3 0 20H 2 Y 1 0 IO[4:1]-DU After a hardware reset, the RSTAT bit is set and generates an interrupt. Therefore, the default value of INTREG2 is 20H. After reading all four interrupt registers, the INTREG2 value changes to 4FH. READY Indicates whether ramp generator has finished. An interrupt is only generated if the READY bit changes from 0 to 1. At a new start of the ramp generator, the bit is set to 0. For further information regarding soft reversal see Chapter 2.7.2.1. RSTAT Bit 0AH Bit Ramp generator active. READY = 1 Ramp generator not active. Reset status since last interrupt. IO[4:1]-DU 09H READY = 0 RSTAT = 0 No reset has occurred since the last interrupt. RSTAT = 1 Reset has occurred since the last interrupt. Data on I/O pins 1 to 4 filtered by the DUP-IO counter and interrupt generation masked by the IO[4:1]-DU-M bits. A change of any of these bits generates an interrupt. INTREG3 Interrupt Register 3 (read-only) 00H Y 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 INTREG4 Interrupt Register 4 (read-only) 00H Y 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Preliminary Data Sheet 276 DS3, 2003-07-11 DuSLIC 0BH CHKR1 Bit Checksum Register 1 (High Byte) (read-only) 7 6 5 4 SUMOK SUM-OK 3 00H 2 Y 1 0 CHKSUM-H[6:0] Information about the validity of the checksum. The checksum is valid if the internal checksum calculation is finished. Checksum calculation: For (cram_adr = 0 to 159) do cram_dat = cram[cram_adr] csum[14:0] = (csum[13:0] &1) ‘0’) xor (‘0000000’ & cram_dat[7:0]) xor (‘0000000000000’ & csum[14] & csum[14]) End SUM-OK = 0 CRAM checksum is not valid. SUM-OK = 1 CRAM checksum is valid. 1) “&” means a concatenation; not the logic operation CHKSUM-H[6:0] CRAM checksum High Byte Preliminary Data Sheet 277 DS3, 2003-07-11 DuSLIC 0CH CHKR2 Bit Checksum Register 2 (Low Byte) (read-only) 7 6 5 4 00H 3 2 Y 1 0 CHKSUM-L[7:0] CHKSUM-L[7:0] 0DH Bit CRAM-checksum Low Byte LMRES1 7 Level Metering Result 1 (High Byte) (read-only) 6 5 4 3 00H 2 Y 1 0 LM-VAL-H[7:0] LM-VAL-H[7:0] 0EH Bit LMRES2 7 LM result High Byte (selected by the LM-SEL bits in the LMCR2 register) Level Metering Result 2 (Low Byte) (read-only) 6 5 4 3 00H 2 Y 1 0 LM-VAL-L[7:0] LM-VAL-L[7:0] 0FH Bit FUSE2 7 LM result Low Byte (selected by the LM-SEL bits in the LMCR2 register) Fuse Register 2 6 5 hw 4 3 2 Y 1 0 for internal use only 10H FUSE3 Preliminary Data Sheet Fuse Register 3 hw 278 Y DS3, 2003-07-11 DuSLIC Bit 7 6 5 4 3 2 1 0 for internal use only Preliminary Data Sheet 279 DS3, 2003-07-11 DuSLIC 11H MASK Bit Mask Register FFH 7 6 5 4 3 READY -M HOOK -M GNDK -M GNKP -M ICON -M 2 Y 1 VTRLIM OTEMP -M -M 0 SYNC -M The mask bits in the mask register influence only the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers is updated to show the current status of the corresponding event. READY-M HOOK-M GNDK-M GNKP-M ICON-M Mask bit for Ramp Generator READY bit READY-M = 0 An interrupt is generated if the READY bit changes from 0 to 1. READY-M = 1 Changes of the READY bit don’t generate interrupts. Mask bit for Off-Hook Detection HOOK bit HOOK-M = 0 Each change of the HOOK bit generates an interrupt. HOOK-M = 1 Changes of the HOOK bit don’t generate interrupts. Mask bit for ground key detection GNDK bit GNDK-M = 0 Each change of the GNDK bit generates an interrupt. GNDK-M = 1 Changes of the GNDK bit do not generate interrupts. Mask bit for ground key level GNKP bit GNKP-M = 0 Each change of the GNKP bit generates an interrupt. GNKP-M = 1 Changes of the GNKP bit do not generate interrupts. Mask bit for Constant Current Information ICON bit ICON-M = 0 Each change of the ICON bit generates an interrupt. ICON-M = 1 Changes of the ICON bit do not generate interrupts. VTRLIM-M Mask bit for Programmed Voltage Limit VTRLIM bit VTRLIM-M = 0 Each change of the VTRLIM bit generates an interrupt. VTRLIM-M = 1 Changes of the VTRLIM bit do not generate interrupts. Preliminary Data Sheet 280 DS3, 2003-07-11 DuSLIC OTEMP-M Mask bit for Thermal Overload Warning OTEMP bit SYNC-M OTEMP-M = 0 A change of the OTEMP bit from 0 to 1 generates an interrupt. OTEMP-M = 1 A change of the OTEMP bit from 0 to 1 does not generate interrupts. Mask bit for Synchronization Failure SYNC-FAIL bit SYNC-M = 0 A change of the SYNC-FAIL bit from 0 to 1 generates an interrupt. SYNC-M = 1 A change of the SYNC-FAIL bit from 0 to 1 does not generate interrupts. Preliminary Data Sheet 281 DS3, 2003-07-11 DuSLIC 12H IOCTL1 Bit I/O Control Register 1 7 6 5 4 0FH 3 IO[4:1]-INEN 2 Y 1 0 IO[4:1]-M The mask bits IO[4:1]-M influence only the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers is updated to show the current status of the corresponding event. IO4-INEN Input enable for programmable I/O pin IO4 IO4-INEN = 0 Input Schmitt trigger of pin IO4 is disabled. IO4-INEN = 1 Input Schmitt trigger of pin IO4 is enabled. IO3-INEN Input enable for programmable I/O pin IO3 IO3-INEN = 0 Input Schmitt trigger of pin IO3 is disabled. IO3-INEN = 1 Input Schmitt trigger of pin IO3 is enabled. IO2-INEN Input enable for programmable I/O pin IO2 IO2-INEN = 0 Input Schmitt trigger of pin IO2 is disabled. IO2-INEN = 1 Input Schmitt trigger of pin IO2 is enabled. IO1-INEN Input enable for programmable I/O pin IO1 IO1-INEN = 0 Input Schmitt trigger of pin IO1 is disabled. IO1-INEN = 1 Input Schmitt trigger of pin IO1 is enabled. IO4-M IO3-M Mask bit for IO4-DU bit IO4-M = 0 Each change of the IO4 bit generates an interrupt. IO4-M = 1 Changes of the IO4 bit do not generate interrupts. Mask bit for IO3-DU bit IO3-M = 0 Each change of the IO3 bit generates an interrupt. IO3-M = 1 Changes of the IO3 bit do not generate interrupts. Preliminary Data Sheet 282 DS3, 2003-07-11 DuSLIC IO2-M IO1-M Mask bit for IO2-DU bit IO2-M = 0 Each change of the IO2 bit generates an interrupt. IO2-M = 1 Changes of the IO2 bit do not generate interrupts. Mask bit for IO1-DU bit IO1-M = 0 Each change of the IO1 bit generates an interrupt. IO1-M = 1 Changes of the IO1 bit do not generate interrupts. Preliminary Data Sheet 283 DS3, 2003-07-11 DuSLIC 13H IOCTL2 Bit 7 I/O Control Register 2 6 5 4 IO[4:1]-OEN IO4-OEN IO3-OEN IO2-OEN IO1-OEN IO4-DD IO3-DD 00H 3 2 Y 1 0 IO[4:1]-DD Enabling the output driver of pin IO4 IO4-OEN = 0 The output driver of pin IO4 is disabled. IO4-OEN = 1 The output driver of pin IO4 is enabled. Enabling the output driver of pin IO3 IO3-OEN = 0 The output driver of pin IO3 is disabled. IO3-OEN = 1 The output driver of pin IO3 is enabled. Enabling the output driver of pin IO2 IO2-OEN = 0 The output driver of pin IO2 is disabled. IO2-OEN = 1 The output driver of pin IO2 is enabled. Enabling the output driver of pin IO1 If external ringing is selected (bit REXT-EN in register BCR2 set to 1), pin IO1 cannot be controlled by the user but is utilized by the SLICOFI-2S to control the ring relay. IO1-OEN = 0 The output driver of pin IO1 is disabled. IO1-OEN = 1 The output driver of pin IO1 is enabled. Value for the programmable I/O pin IO4 if programmed as an output pin. IO4-DD = 0 The corresponding pin is driving a logical 0. IO4-DD = 1 The corresponding pin is driving a logical 1. Value for the programmable I/O pin IO3 if programmed as an output pin. IO3-DD = 0 The corresponding pin is driving a logical 0. IO3-DD = 1 The corresponding pin is driving a logical 1. Preliminary Data Sheet 284 DS3, 2003-07-11 DuSLIC IO2-DD IO1-DD Value for the programmable I/O pin IO2 if programmed as an output pin. IO2-DD = 0 The corresponding pin is driving a logical 0. IO2-DD = 1 The corresponding pin is driving a logical 1. Value for the programmable I/O pin IO1 if programmed as an output pin. IO1-DD = 0 The corresponding pin is driving a logical 0. IO1-DD = 1 The corresponding pin is driving a logical 1. Preliminary Data Sheet 285 DS3, 2003-07-11 DuSLIC 14H IOCTL3 Bit I/O Control Register 3 7 6 5 94H 4 3 DUP[3:0] DUP[3:0] 2 Y 1 0 DUP-IO[3:0] Data Upstream Persistence Counter end value. Restricts the rate of interrupts generated by the HOOK bit in the interrupt register INTREG1. The interval is programmable from 1 to 16 ms in steps of 1 ms (reset value is 10 ms). The DUP[3:0] value affects the blocking period for ground key detection (see Chapter 2.6). DUP[3:0] HOOK Active, Ringing HOOK Power Down GNDK GNDK fmin,ACsup1) 0000 1 2 ms 4 ms 125 Hz 0001 2 4 ms 8 ms 62.5 Hz 16 32 ms 64 ms 7.8125 Hz ... 1111 1) Minimum frequency for AC suppression. DUP-IO[3:0] Data Upstream Persistence Counter end value for • the I/O pins when used as digital input pins. • the bits ICON and VTRLIM in register INTREG1. The interval is programmable from 0.5 to 60.5 ms in steps of 4 ms (reset value is 16.5 ms). Preliminary Data Sheet 286 DS3, 2003-07-11 DuSLIC 15H Bit HIR HIT BCR1 Basic Configuration Register 1 7 6 5 HIR HIT 0 4 00H 3 REVPOL ACTR 2 ACTL Y 1 0 SEL-SLIC[1:0] This bit modifies different basic modes. In ringing mode, an unbalanced ringing on the RING-wire (ROR) is enabled. In Active mode, high impedance on the RING-wire is performed (HIR). It enables the HIRT-mode, together with the HIT bit. HIR = 0 Normal operation (ringing mode). HIR = 1 Controls SLIC-S/-S2-interface and sets the RING wire to high impedance (Active mode). This bit modifies different basic modes. In ringing mode, an unbalanced ringing on the TIP-wire (ROT) is enabled. In Active mode, high impedance on the TIP-wire is performed (HIT). It enables the HIRT-mode, together with the HIR bit. HIT = 0 Normal operation (ringing mode). HIT = 1 Controls SLIC-S/-S2-interface and sets the TIP-wire to high impedance (Active mode). REVPOL Reverse polarity of DC feeding ACTR REVPOL = 0 Normal polarity. REVPOL = 1 Reverse polarity. Selection of extended battery feeding in Active mode. In this caseVHR – VBATH for SLIC-S/-S2 is used. ACTR = 0 No extended battery feeding selected. ACTR = 1 Extended battery feeding selected. Preliminary Data Sheet 287 DS3, 2003-07-11 DuSLIC ACTL Selection of the low battery supply voltage VBATL on SLIC-S/-S2 if available. Valid only in Active mode of the SLICOFI-2S. ACTL = 0 Low battery supply voltage on SLIC-S/-S2 is not selected. ACTL = 1 Low battery supply voltage on SLIC-S/-S2 is selected. SEL-SLIC[1:0] Selection of the current SLIC type used. For SLIC-E/-E2 and SLIC-P, the appropriate predefined mode table has to be selected. SEL-SLIC[1:0] = 0 0 SLIC-E/-E2 selected. SEL-SLIC[1:0] = 0 1 SLIC-P selected. SEL-SLIC[1:0] = 1 0 SLIC-P selected for extremely power sensitive applications using external ringing. SEL-SLIC[1:0] = 1 1 Reserved for future use. Preliminary Data Sheet 288 DS3, 2003-07-11 DuSLIC For SLIC-P two selections are possible. • The standard SLIC-P selection automatically uses the IO2 pin of the SLICOFI-2 to control the C3 pin of the SLIC-P. By using pin C3 as well as the pins C1 and C2, all possible operating modes of the SLIC-P can be selected. For SLIC-P 1.2 only the operating modes with 90 mA current limitation can be selected (ACTL90, ACTH90, ACTR90). Note: If with SLIC-P V1.2 the 60 mA current limitation modes (ACTL60, ACTH60, ACTR60) are to be used, then the SLIC type SEL-SLIC[1:0] = 10 has to be programmed. In this case the C3 pin of the SLIC-P V1.2 can also be controlled by the IO2 pin of the SLICOFI-2. However, the IO2 pin has then to be programmed manually by the user according to the SLIC-P V1.2 interface code table. • For extremely power sensitive applications using external ringing with SLIC-P SEL-SLIC[1:0] = 10 should be chosen. In this case, internal unbalanced ringing is not needed and therefore there is no need to switch the C3 pin of the SLIC-P to 'High'. The C3 pin of the SLIC-P must be connected to GND and the IO2 pin of the SLICOFI-2 is programmable by the user. There is no need for a high battery voltage for ringing either. This mode uses VBATR for the on-hook voltage (e.g. –48 V) in Power Down Resistive (PDR) mode and the other battery supply voltages (e.g. VBATH = –24 V and VBATL = –18 V) can be used for the off-hook state. This will help to save power because the lowest possible battery voltage can be selected (see DuSLIC Voltage and Power Application Note). Preliminary Data Sheet 289 DS3, 2003-07-11 DuSLIC 16H BCR2 Bit Basic Configuration Register 2 00H Y 7 6 5 4 3 2 1 0 REXTEN SOFTDIS TTXDIS1) TTX12K2) HIM-AN ACXGAIN 0 PDOTDIS 1) Only for DuSLIC-S, is set to 1 for DuSLIC-S2 2) Only for DuSLIC-S, is set to 0 for DuSLIC-S2 REXT-EN SOFT-DIS TTX-DIS TTX-12K Enables the use of an external ring-signal generator. The synchronization is done via the RSYNC pin and the ring-burst-enable signal is transferred via the IO1 pin. REXT-EN = 0 External ringing is disabled. REXT-EN = 1 External ringing enabled. Polarity soft reversal (to minimize noise on DC feeding) SOFT-DIS = 0 Polarity soft reversal active. SOFT-DIS = 1 Polarity hard reversal. Disables the generation of TTX bursts for metering signals. If they are disabled, reverse polarity is used instead. TTX-DIS = 0 TTX bursts are enabled. TTX-DIS = 1 TTX bursts are disabled, reverse polarity used. Selection of TTX frequencies TTX-12K = 0 Selects 16 kHz TTX signals instead of 12 kHz signals. TTX-12K = 1 12 kHz TTX signals. Preliminary Data Sheet 290 DS3, 2003-07-11 DuSLIC HIM-AN Higher impedance in analog impedance matching loop. The value of this bit must correspond to the selection done in the DUSLICOS tool when calculating the coefficients. If the coefficients are calculated with standard impedance in analog impedance matching loop, HIM-AN must be set to 0; if the coefficients are calculated with high impedance in analog impedance matching loop, HIM-AN must be set to 1. HIM-AN = 0 Standard impedance in analog impedance matching loop HIM-AN = 1 High impedance in analog impedance matching loop AC-XGAIN Analog gain in transmit direction (should be set to zero). PDOT-DIS AC-XGAIN = 0 No additional analog gain in transmit direction. AC-XGAIN = 1 Additional 6 dB analog amplification in transmit direction. Power Down Overtemperature Disable PDOT-DIS = 0 When overtemperature is detected, the SLIC-S/-S2 is automatically switched into Power Down High Impedance mode (PDH). This is the safe operation mode for the SLIC-S/-S2 in case of overtemperature. To leave the automatically activated PDH mode, DuSLIC must be switched manually to PDH mode and then in the mode as desired. PDOT-DIS = 1 When overtemperature is detected, the SLIC-S/-S2 does not automatically switch into Power Down High Impedance mode. In this case, the output current of the SLIC-S/-S2 buffers is limited to a value which keeps the SLIC-S/-S2 temperature below the upper temperature limit. Preliminary Data Sheet 291 DS3, 2003-07-11 DuSLIC 17H BCR3 Bit Basic Configuration Register 3 00H Y 7 6 5 4 3 2 1 0 MULAW LIN 0 PCMXEN 0 0 0 CRAMEN MU-LAW LIN Selects the PCM Law MU-LAW = 0 A-Law enabled. MU-LAW = 1 µ-Law enabled. Voice transmission in a 16-bit linear representation for test purposes. Note: Voice transmission on the other channel is inhibited if one channel is set to linear mode and the IOM-2 interface is used. In PCM/microcontroller interface mode, both channels can be in linear mode using two consecutive PCM timeslots on the highways. A proper timeslot selection must be specified. PCMX-EN CRAM-EN LIN = 0 PCM mode enabled (8 bit, A-Law, or µ-Law). LIN = 1 Linear mode enabled (16 bit). Enables writing of subscriber voice data to the PCM highway. PCMX-EN = 0 Writing of subscriber voice data to PCM highway is disabled. PCMX-EN = 1 Writing of subscriber voice data to PCM highway is enabled. Coefficients from CRAM are used for programmable filters and DC loop behavior. CRAM-EN = 0 Coefficients from ROM are used. CRAM-EN = 1 Coefficients from CRAM are used. Preliminary Data Sheet 292 DS3, 2003-07-11 DuSLIC 18H BCR4 Bit Basic Configuration Register 4 7 6 TH-DIS IM-DIS TH-DIS IM-DIS AX-DIS AR-DIS FRX-DIS FRR-DIS HPX-DIS 5 4 AX-DIS AR-DIS 00H Y 3 2 1 0 FRXDIS FRRDIS HPXDIS HPRDIS Disables the TH filter. TH-DIS = 0 TH filter is enabled. TH-DIS = 1 TH filter is disabled (HTH = 0). Disables the IM filter. IM-DIS = 0 IM filter is enabled. IM-DIS = 1 IM filter is disabled (HIM = 0). Disables the AX filter. AX-DIS = 0 AX filter is enabled. AX-DIS = 1 AX filter is disabled (HAX = 1). Disables the AR filter. AX-DIS = 0 AR filter is enabled. AX-DIS = 1 AR filter is disabled (HAR = 1). Disables the FRX filter. FRX-DIS = 0 FRX filter is enabled. FRX-DIS = 1 FRX filter is disabled (HFRX = 1). Disables the FRR filter. FRR-DIS = 0 FRR filter is enabled. FRR-DIS = 1 FRR filter is disabled (HFRR = 1). Disables the high-pass filter in transmit direction. HPX-DIS = 0 High-pass filter is enabled. HPX-DIS = 1 High-pass filter is disabled (HHPX = 1). Preliminary Data Sheet 293 DS3, 2003-07-11 DuSLIC HPR-DIS Disables the high-pass filter in receive direction. HPR-DIS = 0 High-pass filter is enabled. HPR-DIS = 1 High-pass filter is disabled (HHPR = 1). Reserved 19H Bit 00H Y 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Preliminary Data Sheet 294 DS3, 2003-07-11 DuSLIC 1AH DSCR Bit DTMF Sender Configuration Register 7 6 5 4 DG-KEY[3:0] 00H 3 2 COR8 PTG Y 1 0 TG2-EN TG1-EN DG-KEY[3:0] Selects one of sixteen DTMF keys generated by the 2 tone generators. The key will be generated if both TG1-EN and TG2-EN are 1. Table 71 DTMF Keys fLOW [Hz] fHIGH [Hz] DIGIT DG-KEY3 DG-KEY2 DG-KEY1 DG-KEY0 697 1209 1 0 0 0 1 697 1336 2 0 0 1 0 697 1477 3 0 0 1 1 770 1209 4 0 1 0 0 770 1336 5 0 1 0 1 770 1477 6 0 1 1 0 852 1209 7 0 1 1 1 852 1336 8 1 0 0 0 852 1477 9 1 0 0 1 941 1336 0 1 0 1 0 941 1209 * 1 0 1 1 941 1477 # 1 1 0 0 697 1633 A 1 1 0 1 770 1633 B 1 1 1 0 852 1633 C 1 1 1 1 941 1633 D 0 0 0 0 COR8 Cuts off the receive path at 8 kHz before the tone generator summation point. Allows sending of tone generator signals without overlaid voice. COR8 = 0 Cut off receive path disabled. COR8 = 1 Cut off receive path enabled. Preliminary Data Sheet 295 DS3, 2003-07-11 DuSLIC PTG Programmable coefficients for tone generators will be used. TG2-EN PTG = 0 Frequencies set by DG-KEY are used for both tone generators. Tone generator TG1 level: –5 dBm0 Tone generator TG2 level: –3 dBm0 PTG = 1 CRAM coefficients used for both tone generators. Tone generator TG1 and TG2 frequencies and levels can be programmed in the DuSLICOS DC Control Parameters 3/4. The levels are set in dBm0: Level[dBm] = Level[dBm0] + LR[dBr] Enables tone generator two TG1-EN TG2-EN = 0 Tone generator is disabled. TG2-EN = 1 Tone generator is enabled. Enables tone generator one TG1-EN = 0 Tone generator is disabled. TG1-EN = 1 Tone generator is enabled. Reserved 1BH Bit 00H Y 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Preliminary Data Sheet 296 DS3, 2003-07-11 DuSLIC 1CH LMCR1 Bit Level Metering Configuration Register 1 22H Y 7 6 5 4 3 2 1 0 TESTEN LM-EN LMTHM PCM2DC LM2 PCM LMONCE LMMASK DCAD16 TEST-EN Activates the SLICOFI-2S test features controlled by test registers TSTR1 to TSTR5. TEST-EN = 0 SLICOFI-2S test features are disabled. TEST-EN = 1 SLICOFI-2S test features are enabled. Note: The Test Register bits can be programmed before the TEST-EN bit is set to 1. LM-EN LM-THM PCM2DC LM2PCM LM-ONCE Enables level metering. A positive transition of this bit starts level metering (AC and DC). LM-EN = 0 Level metering stops. LM-EN = 1 Level metering enabled. Level metering threshold mask bit LM-THM = 0 A change of the LM-THRES bit (register INTREG2) generates an interrupt. LM-THM = 1 No interrupt is generated. PCM voice channel data added to the DC-output. PCM2DC = 0 Normal operation. PCM2DC = 1 PCM voice channel data is added to DC output. Level metering source/result (depending on LM-EN bit) feeding to PCM or IOM-2 interface. LM2PCM = 0 Normal operation. LM2PCM = 1 Level metering source/result is fed to the PCM or IOM-2 interface. Level metering execution mode. Preliminary Data Sheet 297 DS3, 2003-07-11 DuSLIC LM-MASK DC-AD16 LM-ONCE = 0 Level metering is executed continuously. LM-ONCE = 1 Level metering is executed only once. To start the Level Meter again, the LM-EN bit must again be set from 0 to 1. Interrupt masking for level metering. LM-MASK = 0 An interrupt is generated after level metering. LM-MASK = 1 No interrupt is generated. Additional digital amplification in the DC AD path for level metering. DC-AD16 = 0 Additional gain factor 16 disabled. DC-AD16 = 1 Additional gain factor 16 enabled. Preliminary Data Sheet 298 DS3, 2003-07-11 DuSLIC 1DH LMCR2 Bit Level Metering Configuration Register 2 7 6 5 4 LMNOTCH LMFILT LMRECT RAMPEN LM-NOTCH LM-FILT LM-RECT RAMP-EN LM-SEL[3:0] 3 00H 2 Y 1 0 LM-SEL[3:0] Selection of a notch filter instead of the band-pass filter for level metering. LM-NOTCH = 0 Notch filter selected. LM-NOTCH = 1 Band-pass filter selected. Enabling of a programmable band-pass or notch filter for level metering. LM-FILT = 0 Normal operation. LM-FILT = 1 Band-pass/notch filter enabled. Rectifier in DC Level Meter LM-RECT = 0 Rectifier disabled. LM-RECT = 1 Rectifier enabled. The ramp generator works together with the RNG-OFFSET bits in LMCR3 and the LM-EN bit to create different voltage slopes in the DCPath. RAMP-EN = 0 Ramp generator disabled. RAMP-EN = 1 Ramp generator enabled. Selection of the source for the level metering. LM-SEL[3:0] = 0 0 0 0 AC level metering in transmit LM-SEL[3:0] = 0 0 0 1 Real part of TTX (TTXREAL) LM-SEL[3:0] = 0 0 1 0 Imaginary part of TTX (TTXIMG) LM-SEL[3:0] = 0 0 1 1 Not used LM-SEL[3:0] = 0 1 0 0 DC out voltage on DCN-DCP LM-SEL[3:0] = 0 1 0 1 DC current on IT LM-SEL[3:0] = 0 1 1 0 AC level metering in receive Preliminary Data Sheet 299 DS3, 2003-07-11 DuSLIC LM-SEL[3:0] = 0 1 1 1 AC level metering in receive and transmit LM-SEL[3:0] = 1 0 0 0 Not used LM-SEL[3:0] = 1 0 0 1 DC current on IL LM-SEL[3:0] = 1 0 1 0 Voltage on IO3 LM-SEL[3:0] = 1 0 1 1 Voltage on IO4 LM-SEL[3:0] = 1 1 0 0 Not used LM-SEL[3:0] = 1 1 0 1 VDD LM-SEL[3:0] = 1 1 1 0 Offset of DC-Prefi (short circuit on DC-Prefi input) LM-SEL[3:0] = 1 1 1 1 Voltage on IO4 – IO3 Preliminary Data Sheet 300 DS3, 2003-07-11 DuSLIC 1EH LMCR3 Bit Level Metering Configuration Register 3 7 6 ACSHORT -EN RTRSEL 5 4 3 LM-ITIME[3:0] 2 00H Y 1 0 RNGOFFSET[1:0] AC-SHORT-EN The input pin ITAC will be set to a lower input impedance so that the capacitor CITAC can be recharged faster during a soft reversal which makes it more silent during conversation. AC-SHORT-EN = 0 Input impedance of the ITAC pin is standard. AC-SHORT-EN = 1 Input impedance of the ITAC pin is lowered. RTR-SEL Ring Trip method selection. RTR-SEL = 0 Ring Trip with a DC offset is selected. RTR-SEL = 1 AC Ring Trip is selected. Recommended for short lines only. LM-ITIME[3:0] Integration Time for AC Level Metering. LM-ITIME[3:0] = 0 0 0 0 16 ms LM-ITIME[3:0] = 0 0 0 1 2 × 16 ms LM-ITIME[3:0] = 0 0 1 0 3 × 16 ms … 16 × 16 ms LM-ITIME[3:0] = 1 1 1 1 RNGOFFSET[1:0] Selection of the Ring Offset source. Preliminary Data Sheet 301 DS3, 2003-07-11 DuSLIC RNGOFFSET[1:0] Ring Offset Voltage in Given Mode Active ACTH ACTL Active Ring ACTR Ring Pause Ringing 00 Voltage given by DC Voltage given by DC Ring Offset RO1 regulation regulation Hook Threshold Ring 01 Ring Offset RO1/2 (no DC regulation) Ring Offset RO1 (no DC regulation) Ring Offset RO1 Hook Threshold Ring 10 Ring Offset RO2/2 (no DC regulation) Ring Offset RO2 (no DC regulation) Ring Offset RO2 Hook Message Waiting 11 Ring Offset RO3/2 (no DC regulation) Ring Offset RO3 (no DC regulation) Ring Offset RO3 Hook Message Waiting By setting the RAMP-EN bit to 1, the ramp generator is started by setting LM-EN from 0 to 1 (see Figure 68). Exception: Transition of RNG-OFFSET from 10 to 11 or 11 to 10 where the ramp generator is started automatically (see Figure 68). For Ring Offset RO1, the usual “Hook Threshold Ring” is used. Using Ring Offset RO2 or RO3 in any ringing mode (Ringing and Ring Pause) also changes the hook thresholds. In this case the “Hook Message Waiting” threshold is used automatically. When using the Ring Offsets RO2 and RO3 for Message Waiting, an additional lamp current is expected. In this case, the Hook Message Waiting threshold should be programmed higher than the Hook Threshold Ring. ook Threshold Ring. Preliminary Data Sheet 302 DS3, 2003-07-11 DuSLIC RNG-OFFSET[1:0] 01 10 11 01 RAMP-EN (register LMCR2) LM-EN (register LMCR1) Generated Ring Offset (RO) Voltage RO3 = 120 V RO2 = 40 V RO1 = 20 V t ezm35002 Figure 68 Example for Switching Between Different Ring Offset Voltages The three programmable Ring Offsets are typically used for the following purposes: Table 72 Typical Usage for the three Ring Offsets Ring Offset Voltage Application Ring Offset RO1 Ringing Ring Offset RO2 Low voltage for message waiting lamp Ring Offset RO3 High voltage for message waiting lamp Besides the typical usage described in Table 72, the Ring Offsets RO1, RO2, and RO3 can also be used for the generation of different custom waveforms (see Figure 68). Preliminary Data Sheet 303 DS3, 2003-07-11 DuSLIC 1FH OFR1 Bit Offset Register 1 (High Byte) 7 6 5 4 00H 3 2 Y 1 0 OFFSET-H[7:0] OFFSET-H[7:0] 20H Bit Offset register High Byte. OFR2 7 Offset Register 2 (Low Byte) 6 5 4 3 00H 2 1 Y 0 OFFSET-L[7:0] OFFSET-L[7:0] Offset register Low Byte. The value of this register together with OFFSET-H is added to the input of the DC loop to compensate a given offset of the current sensors in the SLIC-S/-S2. Preliminary Data Sheet 304 DS3, 2003-07-11 DuSLIC 21H PCMR1 Bit 7 PCM Receive Register 1 6 5 4 R1HW R1-HW R1-TS[6:0] 00H 3 2 Y 1 0 R1-TS[6:0] Selection of the PCM highway for receiving PCM data or the higher byte of the first data sample if linear 16 kHz PCM mode is selected. R1-HW = 0 PCM highway A is selected. R1-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for data reception. Note: The programmed PCM timeslot must correspond to the available slots defined by the PCLK frequency. No reception will occur if a slot outside the actual numbers of slots is programmed. In linear mode (bit LIN = 1 in register BCR3) R1-TS defines the first of two consecutive slots used for reception. Preliminary Data Sheet 305 DS3, 2003-07-11 DuSLIC 22H Bit Reserved 7 7 24H Bit 5 4 3 2 Reserved 23H Bit 6 00H 6 5 Preliminary Data Sheet 6 5 1 00H 4 3 2 Reserved 7 Y Y 1 00H 4 306 3 2 0 0 Y 1 0 DS3, 2003-07-11 DuSLIC 25H PCMX1 Bit 7 PCM Transmit Register 1 6 5 4 X1-HW X1-HW X1-TS[6:0] 00H 3 2 Y 1 0 X1-TS[6:0] Selection of the PCM highway for transmitting PCM data or the higher byte of the first data sample if linear 16 kHz PCM mode is selected. X1-HW = 0 PCM highway A is selected. X1-HW = 1 PCM highway B is selected. Selection of the PCM timeslot used for data transmission. Note: The programmed PCM timeslot must correspond to the available slots defined by the PCLK frequency. No transmission will occur if a slot outside the actual numbers of slots is programmed. In linear mode, X1-TS defines the first of two consecutive slots used for transmission. PCM data transmission is controlled by bits 6 to 2 in register BCR3. Preliminary Data Sheet 307 DS3, 2003-07-11 DuSLIC 26H Bit Reserved 7 7 28H Bit 5 4 3 2 Reserved 27H Bit 6 00H 6 5 Preliminary Data Sheet 6 5 1 00H 4 3 2 Reserved 7 Y Y 1 00H 4 308 3 2 0 0 Y 1 0 DS3, 2003-07-11 DuSLIC 29H TSTR1 Bit Test Register 1 7 6 5 00H 4 3 PD-AC- PD-AC- PD-AC- PD-AC- PD-ACPR PO AD DA GN T Y 2 1 0 PDGNKC PDOFHC PDOVTC Register setting is active only if bit TEST-EN in register LMCR1 is set to 1. PD-AC-PR PD-AC-PO PD-AC-AD PD-AC-DA PD-AC-GN PD-GNKC AC-PREFI Power Down PD-AC-PR = 0 Normal operation. PD-AC-PR = 1 Power down mode. AC-POFI Power Down PD-AC-PO = 0 Normal operation. PD-AC-PO = 1 Power down mode. AC-ADC Power Down PD-AC-AD = 0 Normal operation. PD-AC-AD = 1 Power down mode, transmit path is inactive. AC-DAC Power Down PD-AC-DA = 0 Normal operation. PD-AC-DA = 1 Power down mode, receive path is inactive. AC-Gain Power Down PD-AC-GN = 0 Normal operation. PD-AC-GN = 1 Power down mode. Ground key comparator (GNKC) is set to Power Down PD-GNKC = 0 Normal operation. PD-GNKC = 1 Power down mode. Preliminary Data Sheet 309 DS3, 2003-07-11 DuSLIC PD-OFHC PD-OVTC Off-hook comparator (OFHC) Power Down PD-OFHC = 0 Normal operation. PD-OFHC = 1 Power down mode. Overtemperature comparator (OVTC) Power Down PD-OVTC = 0 Normal operation. PD-OVTC = 1 Power down mode. Preliminary Data Sheet 310 DS3, 2003-07-11 DuSLIC 2AH TSTR2 Bit 1) Test Register 2 7 6 PD-DCPR 0 5 00H 4 3 PD-DC- PD-DCPDAD DA DCBUF 2 0 T 1 Y 0 PD-HVI PD1) TTX-A Only for DuSLIC-S; for DuSLIC-S2, is set to 0. Register setting is active only if bit TEST-EN in register LMCR1 is set to 1. PD-DC-PR PD-DC-AD PD-DC-DA PD-DCBUF PD-TTX-A PD-HVI DC-PREFI Power Down PD-DC-PR = 0 Normal operation. PD-DC-PR = 1 Power down mode. DC-ADC Power Down PD-DC-AD = 0 Normal operation. PD-DC-AD = 1 Power down mode, transmit path is inactive. DC-DAC Power Down PD-DC-DA = 0 Normal operation. PD-DC-DA = 1 Power down mode, receive path is inactive. DC-BUFFER Power Down PD-DCBUF = 0 Normal operation. PD-DCBUF = 1 Power down mode. TTX adaptation DAC and POFI Power Down PD-TTX-A = 0 Normal operation. PD-TTX-A = 1 Power down mode. HV interface (to SLIC-S/-S2) Power Down PD-HVI = 0 Normal operation. PD-HVI = 1 Power down mode. Preliminary Data Sheet 311 DS3, 2003-07-11 DuSLIC 2BH Bit TSTR3 Test Register 3 00H T Y 7 6 5 4 3 2 1 0 0 0 ACDLB4M ACDLB128K ACDLB32K ACDLB8K 0 0 Register setting is active only if bit TEST-EN in register LMCR1 is set to 1. AC-DLB-4M AC digital loop via 4 MHz bitstream. (The loop encloses all digital hardware in the AC path. Together with DLB-DC, a pure digital test is possible because there is no influence of the analog hardware.) AC-DLB-4M = 0 Normal operation. AC-DLB-4M = 1 Digital loop closed. AC-DLB-128K AC digital loop via 128 kHz AC-DLB-128K = 0 Normal operation. AC-DLB-128K = 1 Digital loop closed. AC-DLB-32K AC-DLB-8K AC digital loop via 32 kHz AC-DLB-32K = 0 Normal operation. AC-DLB-32K = 1 Digital loop closed. AC digital loop via 8 kHz AC-DLB-8K = 0 Normal operation. AC-DLB-8K = 1 Digital loop closed. Preliminary Data Sheet 312 DS3, 2003-07-11 DuSLIC 2CH TSTR4 Bit Test Register 4 7 6 OPIMAN OPIM4M 5 00H 4 COR-64 COX-16 T Y 3 2 1 0 0 0 0 0 Register setting is active only if bit TEST-EN in register LMCR1 is set to 1. OPIM-AN OPIM-4M COR-64 COX-16 Open Impedance Matching Loop in the analog part. OPIM-AN = 0 Normal operation. OPIM-AN = 1 Loop opened. Open fast digital Impedance Matching Loop in the hardware filters. OPIM-4M = 0 Normal operation. OPIM-4M = 1 Loop opened. Cut off the AC receive path at 64 kHz (just before the IM filter). COR-64 = 0 Normal operation. COR-64 = 1 Receive path is cut off. Cut off the AC transmit path at 16 kHz. (The TH filters can be tested without the influence of the analog part.) COX-16 = 0 Normal operation. COX-16 = 1 Transmit path is cut off. Preliminary Data Sheet 313 DS3, 2003-07-11 DuSLIC 2DH TSTR5 Bit Test Register 5 00H T Y 7 6 5 4 3 2 1 0 0 0 0 DCPOFIHI DCHOLD 0 0 0 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. DC-POFI-HI DC-HOLD DC post filter limit frequency higher value DC-POFI-HI = 0 Limit frequency is set to 100 Hz (normal operation). DC-POFI-HI = 1 Limit frequency is set to 300 Hz. Actual DC output value hold (value of the last DSP filter stage will be kept) DC-HOLD = 0 Normal operation. DC-HOLD = 1 DC output value hold. Preliminary Data Sheet 314 DS3, 2003-07-11 DuSLIC 5.3.2 COP Command The Coefficient Operation (COP) command gives access to the CRAM data of the DSPs. It is organized in the same way as the SOP command. The offset value allows a direct as well as a block access to the CRAM. Writing beyond the allowed offset will be ignored, reading beyond it will give unpredictable results. The value of a specific CRAM coefficient is calculated by the DuSLICOS software. Attention: To ensure proper functionality, it is essential that all unused register bits have to be filled with zeros. Bit Byte 1 7 6 RD 1 5 4 ADR[2:0] Byte 2 RD 3 2 1 0 1 0 1 OFFSET[7:0] Read Data RD = 0 Write data to chip. RD = 1 Read data from chip. ADR[2:0] Channel address for the subsequent data ADR[2:0] = 0 0 0 Channel A ADR[2:0] = 0 0 1 Channel B (other codes reserved for future use) Preliminary Data Sheet 315 DS3, 2003-07-11 DuSLIC CRAM coefficients are enabled by setting bit CRAM-EN in register BCR3 to 1, except Preliminary Data Sheet 316 DS3, 2003-07-11 DuSLIC Offset [7:0] Short Name Long Name 00H TH1 Transhybrid Filter Coefficients Part 1 08H TH2 Transhybrid Filter Coefficients Part 2 10H TH3 Transhybrid Filter Coefficients Part 3 18H FRR Frequency-response Filter Coefficients Receive Direction 20H FRX Frequency-response Filter Coefficients Transmit Direction 28H AR Amplification/Attenuation Stage Coefficients Receive 30H AX Amplification/Attenuation Stage Coefficients Transmit 38H PTG1 Tone Generator 1 Coefficients 40H PTG2 Tone Generator 2 Coefficients 48H LPR Low Pass Filter Coefficients Receive 50H LPX Low Pass Filter Coefficients Transmit 58H TTX Teletax Coefficients 60H IM1 Impedance Matching Filter Coefficients Part 1 68H IM2 Impedance Matching Filter Coefficients Part 2 70H RINGF Ringer Frequency and Amplitude Coefficients (DC loop) 78H RAMPF Ramp Generator Coefficients (DC loop) 80H DCF DC-Characteristics Coefficients (DC loop) 88H HF Hook Threshold Coefficients (DC loop) 90H TPF Low Pass Filter Coefficients (DC loop) 98H Preliminary Data Sheet Reserved 317 DS3, 2003-07-11 DuSLIC Table 73 Byte 7 CRAM Coefficients Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Transhybrid Coefficient Part 1 00H TH1 08H TH2 10H TH3 FIR Filter in Receive Direction 18H FRR FIR Filter in Transmit Direction 20H FRX Transhybrid Coefficient Part 2 Transhybrid Coefficient Part 3 2nd Gain Stage Receive 1st Gain Stage Receive 28H AR 2nd Gain Stage Transmit 1st Gain Stage Transmit 30H AX TG1 Band-pass TG1 Gain TG1 Frequency 38H PTG11) TG2 Band-pass TG2 Gain TG2 Frequency 40H PTG21) Reserved 48H Reserved 50H FIR Filter for TTX TTX Slope IM K Factor Res. in Resistive Zone RK12 TTX Level IM FIR Filter IM 4 MHz Filter Extended Battery Feeding Gain IM WDF Filter IM1_F 68H IM2_F Ring Offset RO1 70H RINGF Soft Reversal End Constant Ramp CR Soft Ramp SS Ring Delay RD 78H RAMPF Knee Voltage VK1 Open Circuit Volt. 80H DCF 88H HF 90H TPF Res. in Constant Current Zone RI 13 60H Ring Generator Lowpass Constant Current IK1 VLIM Hook Threshold AC Ring Trip Hook Threshold Ring Hook Threshold Active DC Lowpass Filter TP2 Hook Threshold Power Down DC Lowpass Filter TP1 Reserved 14 TTX Ring Generator Frequency Voltage Level VTR 15 58H Ring Generator Amplitude Hook Message Waiting 16 Offset [7:0] 12 11 10 9 8 98H 7 6 5 4 3 2 1 coefficients PTG1 and PTG21) which are enabled by setting bit PTG in register DSCR to 1. Preliminary Data Sheet 318 DS3, 2003-07-11 DuSLIC 5.3.2.1 Table 74 CRAM Programming Ranges CRAM Programming Ranges Parameter Programming Range Constant Current IK1 0...50 mA, ∆ < 0.5 mA Hook Message Waiting, Hook Thresholds 0..25 mA, ∆ < 0.7 mA 25...50 mA, ∆ < 1.3 mA Ring Generator Frequency fRING 3..40 Hz, ∆ < 1 Hz 40..80 Hz, ∆ < 2 Hz > 80 Hz, ∆ < 4 Hz Ring Generator Amplitude 0..20 V, ∆ < 1.7 V 20..85 V, ∆ < 0.9 V Ring Offset RO1 0..25 V, ∆ < 0.6 V 25..50 V, ∆ < 1.2 V 50..100 V, ∆ < 2.4 V, max. 150 V Knee Voltage VK1, Open Circuit Voltge VLIM 0..25 V, ∆ < 0.6 V 25..50 V, ∆ < 1.2 V > 50 V, ∆ < 2.4 V Resistance in Resistive Zone RK12 0..1000 Ω, ∆ < 30 Ω Resistance in Constant Current Zone RI 1.8 kΩ..4.8 kΩ, ∆ < 120 Ω 4.8 kΩ..9.6 kΩ, ∆ < 240 Ω 9.6 kΩ..19 kΩ, ∆ < 480 Ω 19 kΩ..38 kΩ, ∆ < 960 Ω, max. 40 kΩ Preliminary Data Sheet 319 DS3, 2003-07-11 DuSLIC 5.3.3 IOM-2 Interface Command/Indication Byte The Command/Indication (C/I) channel is used to communicate real time status information and for fast control of the DuSLIC. Data on the C/I channel are continuously transmitted in each frame until new data are sent. Data Downstream C/I – Channel Byte (Receive) – IOM-CIDD The first six CIDD data bits control the general operating modes for both DuSLIC channels. According to the IOM-2 specification, new data must be present for at least two frames to be accepted. Table 75 M2, M1, M0: General Operating Mode CIDD M2 M1 M0 SLICOFI-2S Operating Mode (for details see “Overview of all DuSLIC Operating Modes” on Page 74) 1 1 1 Sleep, Power Down (PDRx) 0 0 0 Power Down High Impedance (PDH) 0 1 0 Any Active mode 1 0 1 Ringing (ACTR Burst On) 1 1 0 Active with Metering 1 0 0 Ground Start 0 0 1 Ring Pause CIDD Bit Data Downstream C/I – Channel Byte N 7 6 5 4 3 2 1 0 M2A M1A M0A M2B M1B M0B MR MX ) M2A, M1A, M0A Select operating mode for DuSLIC channel A M2B, M1B, M0B Select operating mode for DuSLIC channel B MR, MX Handshake bits Monitor Receive and Transmit (see “IOM-2 Interface Monitor Transfer Protocol” on Page 133) Preliminary Data Sheet 320 DS3, 2003-07-11 DuSLIC Data Upstream C/I – Channel Byte (Transmit) – IOM-CIDU This byte is used to quickly transfer the most important and time-critical information from the DuSLIC. Each transfer from the DuSLIC lasts for at least two consecutive frames. CIDU Bit 7 Data Upstream C/I – Channel Byte 6 5 4 3 N 00H 2 INT-CHA HOOKA GNDKA INT-CHB HOOKB GNDKB 1 0 MR MX INT-CHA Interrupt information channel A INT-CHA = 0 No interrupt in channel A INT-CHA = 1 Interrupt in channel A HOOKA Hook information channel A HOOKA = 0 On-hook channel A HOOKA = 1 Off-hook channel A GNDKA Ground key information channel A GNDKA = 0 No longitudinal current detected GNDKA = 1 Longitudinal current detected in channel A INT-CHB Interrupt information channel B INT-CHB = 0 No interrupt in channel B INT-CHB = 1 Interrupt in channel B HOOKB Hook information channel B HOOKB = 0 On-hook channel B HOOKB = 1 Off-hook channel B GNDKB Ground key information channel B GNDKB = 0 No longitudinal current detected GNDKB = 1 Longitudinal current detected in channel B MR, MX Handshake bits Monitor Receive and Transmit (see “IOM-2 Interface Monitor Transfer Protocol” on Page 133) Preliminary Data Sheet 321 DS3, 2003-07-11 DuSLIC 5.3.4 Programming Examples of the SLICOFI-2S 5.3.4.1 Microcontroller Interface SOP Write to Channel 0 Starting After the Channel-Specific Read-Only Registers 01000100 00010101 00000000 00000000 00010001 00000000 00000000 First command byte (SOP write for channel 0) Second command byte (offset to BCR1 register) Contents of BCR1 register Contents of BCR2 register Contents of BCR3 register Contents of BCR4 register Contents of BCR5 register Command Offset BCR1 BCR2 BCR3 BCR4 BCR5 DIN DCLK CS ezm220121 Figure 69 Waveform of Programming Example SOP Write to Channel 0 SOP Read from Channel 1 Reading Out the Interrupt Registers 11001100 00000111 First command byte (SOP read for channel 1). Second command byte (offset to Interrupt register 1). The SLICOFI-2S will send data when it has completely received the second command byte. 11111111 11000000 00000010 00000000 00000000 Dump byte (this byte is always FFH). Interrupt register INTREG1 (an interrupt has occurred, Off-hook was detected). Interrupt register INTREG2 (I/O pin 2 is 1). Interrupt register INTREG3 Interrupt register INTREG4 Command Offset Dump Intreg 1 Intreg 2 Intreg 3 Intreg 4 DIN DOUT DCLK CS ezm220122 Figure 70 Waveform of Programming Example SOP Read from Channel 0 Preliminary Data Sheet 322 DS3, 2003-07-11 DuSLIC 5.3.4.2 IOM-2 Interface An example with the same programming sequence as before, using the IOM-2 interface is presented here to show the differences between the microcontroller interface and the IOM-2 interface. SOP Write to Channel 0 Starting After the Channel-Specific Read-Only Registers Monitor MR/MX Monitor data down data up MR/MX Comment 10000001 10000001 01000100 01000100 00010101 00010101 00000000 00000000 00000000 00000000 00010001 00010001 00000000 00000000 11111111 11111111 11 01 01 11 01 11 01 11 01 11 01 11 01 11 01 11 10 10 11 10 11 10 11 10 11 10 11 10 11 10 11 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 IOM-2 address first byte IOM-2 address second byte First command byte (SOP write for channel 0) First command byte second time Second command byte (offset to BCR1 register) Second command byte second time Contents of BCR1 register Contents of BCR1 register second time Contents of BCR2 register Contents of BCR2 register second time Contents of BCR3 register Contents of BCR3 register second time Contents of BCR4 register Contents of BCR4 register second time No more information (dummy byte) Signaling EOM (end of message) by holding MX bit at ‘1’. Because the SLICOFI-2S has an open command structure, no fixed command length is given. The IOM-2 handshake protocol allows for an infinite length of a data stream; therefore, the host must terminate the data transfer by sending an end-of-message signal (EOM) to the SLICOFI-2S. The SLICOFI-2S will abort the transfer only if the host tries to write or read beyond the allowed maximum offsets given by the different types of commands. Each transfer must start with the SLICOFI-2S-specific IOM-2 Address (81H) and must end with an EOM of the handshake bits. Appending a command immediately to its predecessor without an EOM in between is not allowed. When reading interrupt registers, SLICOFI-2S stops the transfer after the fourth register in IOM-2 mode. This is to prevent some host chips from reading 16 bytes because they cannot terminate the transfer after n bytes. Preliminary Data Sheet 323 DS3, 2003-07-11 DuSLIC SOP-Read from Channel 1 Reading Out the Interrupt Registers Monitor MR/MX Monitor data down data up MR/MX Comment 10000001 10000001 11001100 11001100 00001000 00001000 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11 01 01 11 01 11 01 10 10 11 10 11 10 11 10 11 10 11 11 10 10 11 10 11 10 11 11 01 01 11 01 11 01 11 01 11 11 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 10000001 10000001 11000000 11000000 00000010 00000010 00000000 00000000 00000000 00000000 01001101 11111111 Preliminary Data Sheet IOM-2 address first byte IOM-2 address second byte First command byte (SOP read for channel 1) First command byte second time Second command byte (offset to interrupt register 1) Second command byte second time Acknowledgement for the second command byte IOM-2 Address first byte (answer) IOM-2 Address second byte Interrupt register INTREG1 Interrupt register INTREG1 second time Interrupt register INTREG2 Interrupt register INTREG2 second time Interrupt register INTREG3 Interrupt register INTREG3 second time Interrupt register INTREG4 Interrupt register INTREG4 second time SLICOFI-2S sends the next register SLICOFI-2S aborts transmission 324 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6 Electrical Characteristics 6.1 AC Transmission DuSLIC The target figures in this specification are based on the subscriber linecard requirements. The proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) requires the consideration of the complete analog environment of the SLICOFI-2x device. Functionality and performance are guaranteed for TA = 0 to 70 °C by production testing. Extented temperature range operation at –40 °C < TA < 85 °C is guaranteed by design, characterization and periodically sampling and testing production devices at the temperature extremes. Test Conditions TA = –40 °C to 85 °C, unless otherwise stated. VDDD = VDDA = VDDB = VDDR = VDDPLL = 3.3 V ± 5%; VGNDA = VGNDB = VGNDR = VGNDD = VGNDPLL = 0 V RL > 600 Ω; CL < 10 pF LR = 0 … –10 dBr LX = 0 … +3 dBr f = 1014 Hz; 0 dBm0; A-Law or µ-Law; 600Ω R STAB 30Ω x r tra n sm it (x) 0dBm 0 T IP C STAB 1n S L IC S L IC O F I-2 x PEB 426x P E B 3 2 6x 600Ω r 2·0.775V rm s x 0.775V rm s R STAB 30Ω IOM®-2 PCM R IN G C STAB 1n re ce ive (r) 0dBm 0 ezm22018 Figure 71 Signal Definitions Transmit, Receive Note: To ensure the stability of the SLIC output buffer, RSTAB and CSTAB must be set to the values RSTAB = 30 Ω and CSTAB ≥ 300 pF (1 nF in the test circuit Figure 71). For electromagnetic compatibility, CSTAB must be set to the much higher value of CSTAB = 15 nF. Preliminary Data Sheet 325 DS3, 2003-07-11 DuSLIC Electrical Characteristics The 0 dBm0 definitions for Receive and Transmit are: A 0 dBm0 AC signal in transmit direction is equivalent to 0.775 Vrms (referred to an impedance of 600 Ω). A 0 dBm0 AC signal in receive direction is equivalent to 0.775 Vrms (referred to an impedance of 600 Ω). LR = –10 dBr means: A signal of 0 dBm0 at the digital input corresponds to –10 dBm at the analog interface. LX = +3 dBr means: A signal of 3 dBm at the analog interface corresponds to 0 dBm0 at the digital output. Table 76 AC Transmission Parameter Symbol Conditions Limit Values min. typ. max. Unit Longitudinal current capability AC Ill per active line 30 – – mArms Overload level VTR 300 - 4000 Hz 2.3 – – Vrms 26 – – dB Transmission Performance (2-wire) Return loss RL 200 - 3600 Hz Insertion Loss (2-wire to 4-wire and 4-wire to 2-wire) Gain accuracy – Transmit GX 0 dBm0, 1014 Hz –0.25 – +0.25 dB Gain accuracy – Receive GR 0 dBm0, 1014 Hz –0.25 – +0.25 dB Gain variation with temperature –40 … +85 ° C – – – ±0.1 Preliminary Data Sheet 326 – dB DS3, 2003-07-11 DuSLIC Electrical Characteristics Table 76 AC Transmission (cont’d) Parameter Symbol Conditions Limit Values min. typ. Unit max. Frequency Response (see Figure 73 and Figure 74) Receive loss Frequency variation Transmit loss Frequency variation Preliminary Data Sheet GRAF Reference frequency 1014 Hz, signal level 0 dBm0, HFRR = 1 f = 0 - 300 Hz f = 300 - 400 Hz f = 400 - 600 Hz f = 600 - 2400 Hz f = 2400 - 3000 Hz f = 3000 - 3400 Hz f = 3400 - 3600 Hz GXAF –0.25 – – dB –0.25 – 0.9 dB –0.25 – 0.65 dB –0.25 – 0.25 dB –0.25 – 0.45 dB –0.25 – 1.4 dB –0.25 – – dB Reference frequency 1014 Hz, signal level 0 dBm0, HFRX = 1 f = 0 - 200 Hz f = 200 - 300 Hz f = 300 - 400 Hz f = 400 - 600 Hz f = 600 - 2400 Hz f = 2400 - 3000 Hz f = 3000 - 3400 Hz f = 3400 - 3600 Hz 327 – – dB –0.25 – – dB –0.25 – 0.9 dB –0.25 – 0.65 dB –0.25 – 0.25 dB –0.25 – 0.45 dB –0.25 – 1.4 dB –0.25 – – dB 0 DS3, 2003-07-11 DuSLIC Electrical Characteristics Table 76 AC Transmission (cont’d) Parameter Symbol Conditions Limit Values min. typ. Unit max. Gain Tracking (see Figure 75 and Figure 76) Transmit gain Signal level variation Receive gain Signal level variation GXAL GRAL Balance return loss Sinusoidal test method f = 1014 Hz, reference level –10 dBm0 VFXI = –55 to –50 dBm0 –1.4 – 1.4 dB VFXI = –50 to –40 dBm0 –0.5 – 0.5 dB VFXI = –40 to +3 dBm0 –0.25 – 0.25 dB Sinusoidal test method f = 1014 Hz, reference level –10 dBm0 DR0 = –55 to –50 dBm0 –1.4 – 1.4 dB DR0 = –50 to –40 dBm0 –0.5 – 0.5 dB DR0 = –40 to +3 dBm0 –0.25 – 0.25 dB 300 - 3400 Hz 26 – – dB Group Delay (see Figure 77) Transmit delay, absolute DXA f = 500 - 2800 Hz 400 490 585 µs Receive delay, absolute DRA f = 500 - 2800 Hz 290 380 475 µs f = 500 - 600 Hz f = 600 - 1000 Hz f = 1000 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz – – 300 µs – – 150 µs – – 100 µs – – 150 µs – – 300 µs – – – – Group delay, Receive DXR and Transmit, relative to 1500 Hz Overload compression OC A/D Preliminary Data Sheet – 328 DS3, 2003-07-11 DuSLIC Electrical Characteristics Table 76 AC Transmission (cont’d) Parameter Symbol Conditions Limit Values Unit min. typ. max. 53 60 58 65 – – dB dB 52 56 55 59 – – dB dB 53 60 58 65 – – dB dB 52 56 55 59 – – dB dB Longitudinal Balance (according to ITU-T O.9) Longitudinal conversion loss Input longitudinal interference loss L-T L-4 300 - 1000 Hz DuSLIC-S/-E/-P DuSLIC-S2/-E2 3400 Hz DuSLIC-S/-E/-P DuSLIC-S2/-E2 300 - 1000 Hz DuSLIC-S/-E/-P DuSLIC-S2/-E2 3400 Hz DuSLIC-S/-E/-P DuSLIC-S2/-E2 Transversal to longitudinal T-L 300 - 4000 Hz 46 – – dB Longitudinal signal generation 4-L 300 - 4000 Hz 46 – – dB at 200 Ω – – 2.5 Vrms TTX Signal Generation TTX signal VTTX Out-of-Band Noise (Single Frequency Inband –25 dBm0) Transversal VTR 12 kHz - 200 kHz – –55 –50 dBm Longitudinal VTR 12 kHz - 200 kHz – –55 –50 dBm Out-of-Band Idle Channel Noise at Analog Output Measured with 3 kHz Bandwidth Preliminary Data Sheet VTR 10 kHz – – –50 dBm VTR 300 kHz – – –50 dBm VTR 500 kHz – – –70 dBm VTR 1000 kHz – – –70 dBm 329 DS3, 2003-07-11 DuSLIC Electrical Characteristics Table 76 AC Transmission (cont’d) Parameter Symbol Conditions Limit Values min. typ. Unit max. Out-of-Band Signals at Analog Output (Receive) (see Figure 78) Out-of-Band Signals at Analog Input (Transmit) (see Figure 79) Total Harmonic Distortion 2-wire to 4-wire THD4 –7 dBm0, 300 - 3400 Hz – –50 –44 dB 4-wire to 2-wire THD2 –7 dBm0, 300 - 3400 Hz – –50 –44 dB 2-wire port (receive) A-Law NRP Psophometric TTX disabled TTX enabled – – – – –74 –70 dBmp dBmp µ-Law NRC C message TTX disabled TTX enabled – – – – 16 20 dBrnC dBrnC Psophometric TTX disabled TTX enabled – – – – –69 –67 dBm0p dBm0p C message TTX disabled TTX enabled – – – – 18 20 dBrnC dBrnC Idle Channel Noise PCM side (transmit) A-Law NTP µ-Law NTC Preliminary Data Sheet 330 DS3, 2003-07-11 DuSLIC Electrical Characteristics Table 76 AC Transmission (cont’d) Parameter Symbol Conditions Limit Values min. typ. Unit max. Distortion (Sinusoidal Test Method, see Figure 81, Figure 80 and Figure 82) Signal to total distortion Transmit Signal to total distortion Transmit Signal to total distortion Receive Preliminary Data Sheet STDX STDX STDR Output connection: LX = 0 dBr f = 1014 Hz (C message-weighted for µ-Law, psophometrically weighted for A-Law), TTX-DIS = 1 –45 dBm0 24 – – dB –40 dBm0 29 – – dB –30 dBm0 35 – – dB –20 dBm0 36 – – dB –10 dBm0 36 – – dB 3 dBm0 36 – – dB Output connection: LX = 0 dBr f = 1014 Hz (C message-weighted for µ-Law, psophometrically weighted for A-Law), TTX-DIS = 0 –45 dBm0 23 – – dB –40 dBm0 28 – – dB –30 dBm0 34 – – dB –20 dBm0 36 – – dB –10 dBm0 36 – – dB 3 dBm0 36 – – dB Input connection: LR = –7 dBr f = 1014 Hz (C message-weighted for µ-Law, psophometrically weighted for A-Law), TTX-DIS = 1 –45 dBm0 21 – – dB –40 dBm0 26 – – dB –30 dBm0 33 – – dB –20 dBm0 35.5 – – dB –10 dBm0 36 – – dB 3 dBm0 36 – – dB 331 DS3, 2003-07-11 DuSLIC Electrical Characteristics Table 76 AC Transmission (cont’d) Parameter Symbol Conditions Limit Values min. Signal to total distortion Receive Signal to total distortion Receive Signal to total distortion Receive Preliminary Data Sheet STDR STDR STDR typ. Unit max. Input connection: LR = –7 dBr f = 1014 Hz (C message-weighted for µ-Law, psophometrically weighted for A-Law), TTX-DIS = 0 –45 dBm0 19 – – dB –40 dBm0 23.5 – – dB –30 dBm0 31 – – dB –20 dBm0 35.5 – – dB –10 dBm0 36 – – dB 3 dBm0 36 – – dB Input connection: LR = 0 dBr f = 1014 Hz (C message-weighted for µ-Law, psophometrically weighted for A-Law), TTX-DIS = 1 –45 dBm0 24 – – dB –40 dBm0 29 – – dB –30 dBm0 35 – – dB –20 dBm0 36 – – dB –10 dBm0 36 – – dB 3 dBm0 36 – – dB Input connection: LR = 0 dBr f = 1014 Hz (C message-weighted for µ-Law, psophometrically weighted for A-Law), TTX-DIS = 0 –45 dBm0 23 – – dB –40 dBm0 28 – – dB –30 dBm0 34 – – dB –20 dBm0 36 – – dB –10 dBm0 36 – – dB 3 dBm0 36 – – dB 332 DS3, 2003-07-11 DuSLIC Electrical Characteristics Table 76 AC Transmission (cont’d) Parameter Symbol Conditions Limit Values min. typ. max. Unit Power Supply Rejection Ratio VDD/VTR PSRR 300 - 3400 Hz ACTL, ACTH 33 – – dB PSRR 300 - 3400 Hz ACTL, ACTH 27 – – dB PSRR 300 - 3400 Hz 33 – – dB (SLIC) VDDi/VTR (SLICOFI-2x) i = A, B, D, R, PLL VBATH/VTR, VBATL/VTR (SLIC) 9 8 7 6 4.5 4.2 5 4 3 Fundamental Output Power (dBm0) 2 1 0.25 0 -0.25 -1 3.4 0 1 2 3 4 5 6 7 8 9 Fundamental Input Power (dBm0) ezm14009 Figure 72 Overload Compression Preliminary Data Sheet 333 DS3, 2003-07-11 DuSLIC Electrical Characteristics dB Frequency Response 2 Attenuation 6.1.1 1.4 1 0.9 0.65 0.45 0.25 x 0 -0.25 -1 0 .2 .3 .4 .6 1.0 2.0 2.4 3.0 Frequency 3.4 3.6 kHz ezm00110 Figure 73 Frequency Response Transmit dB 2 Attenuation Reference frequency 1 kHz, signal level 0 dBm0, HFRX = 1 1.4 1 0.9 0.65 0.45 0.25 x 0 -0.25 -1 0 .3 .4 .6 1.0 2.0 2.4 Frequency 3.0 3.4 3.6 kHz ezm00111 Figure 74 Frequency Response Receive Reference frequency 1 kHz, signal level 0 dBm0, HFRR = 1 Preliminary Data Sheet 334 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.1.2 Gain Tracking (Receive or Transmit) The gain deviations stay within the limits in the figures below. dB +2 + 1.4 G +1 + 0.5 + 0.25 - 0.25 - 0.5 -1 - 1.4 -2 -70 -60 -55 -50 -40 -30 -20 -10 0 3 10 dBm0 Input level ezm00117 Figure 75 Gain Tracking Receive dB Measured with a sine wave of f = 1014 Hz, reference level is –10 dBm0 +2 G + 1.4 +1 + 0.5 + 0.25 - 0.25 - 0.5 -1 - 1.4 -2 -70 -60 -55 -50 -40 -30 -20 -10 0 3 Input level 10 dBm0 ezm00118 Figure 76 Gain Tracking Transmit Measured with a sine wave of f = 1014 Hz, reference level is –10 dBm0 Preliminary Data Sheet 335 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.1.3 Group Delay Minimum delays occur when both Frequency Response Receive and Transmit filters (bit FRR-DIS and bit FRX-DIS in register BCR4 set to 1) are disabled. That includes the delay through A/D and D/A converters. Specific filter programming may cause additional group delays. Absolute Group delay also depends on the programmed time slot. Group delay distortion stays within the limits in the figures below. Table 77 Group Delay Absolute Values: Signal level 0 dBm0 Parameter Symbol Limit Values min. typ. max. Unit Test Condition Fig. f = 1.5 kHz f = 1.5 kHz – DXA 400 490 585 µs Receive delay DRA 290 380 475 µs 1 1.5 2 TG µs Transmit delay – 500 400 300 200 150 100 0 0 0.5 0.6 2.6 2.8 3 Frequency 3.5 4 kHz ezm00112 Figure 77 Group Delay Distortion Receive and Transmit Signal level 0 dBm0 6.1.4 Out-of-Band Signals at Analog Output (Receive) With a 0 dBm0 sine wave with a frequency of f (300 Hz to 3.4 kHz) applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog output. Preliminary Data Sheet 336 DS3, 2003-07-11 DuSLIC Electrical Characteristics 45 dB 40 35 Receive Out-of-Band Discrimination X 30 25 28 20 15 10 5 0 0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 200 18.0 f 3.4 ... 4.6 kHz: Figure 78 4000 – f X = – 14 sin π --------------------- – 1 1200 kHz itd09762 Out-of-Band Signals at Analog Output (Receive) Preliminary Data Sheet 337 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.1.5 Out-of-Band Signals at Analog Input (Transmit) With a 0 dBm0 out-of-band sine wave signal with a frequency of f (< 100 Hz or 3.4 kHz to 100 kHz) applied to the analog input, the level of any resulting frequency component at the digital output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog input.1) Transmit Out-of-Band Discrimination X dB 40 35 32 30 25 20 15 10 0 0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 f Figure 79 3.4 ... 4.0 kHz: 4000 – f X = – 14 sin π --------------------- – 1 1200 4.0 ... 4.6 kHz: 4000 – f 7 X = – 18 sin π --------------------- – --- 1200 9 100 kHz itd09763 Out-of-Band Signals at Analog Input (Transmit) 1) Poles at 12 kHz ± 150 Hz and 16 kHz ± 150 Hz respectively and harmonics will be provided Preliminary Data Sheet 338 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.1.6 Total Distortion Measured with Sine Wave dB The signal to total distortion ratio exceeds the limits in the following figure: 40 S/D 36 35 34 30 29 28 24 23 20 10 0 -60 -50 -45 -40 -30 -10 Input level TTX-DIS = 0 TTX-DIS = 1 Figure 80 -20 0 3 dBm0 ezm00120 Total Distortion Transmit (LX = 0 dBr) dB Measured with a sine wave of f = 1014 Hz (C message-weighted for µ-Law, psophometrically weighted for A-Law) 40 S/D 36 35,5 34 36 31 30 26 23.5 21 20 19 10 0 -60 -50 -45 -40 -30 Input level TTX-DIS = 0 TTX-DIS = 1 Figure 81 -20 -10 0 3 dBm0 ezm00119 Total Distortion Receive (LR = –7 dBr) Measured with a sine wave of f = 1014 Hz (C message-weighted for µ-Law, psophometrically weighted for A-Law) Preliminary Data Sheet 339 DS3, 2003-07-11 DuSLIC dB Electrical Characteristics 40 S/D 36 35 34 30 29 28 24 23 20 10 0 -60 -50 -45 -40 -30 -20 Input level TTX-DIS = 0 TTX-DIS = 1 -10 0 3 dBm0 ezm00120 Figure 82 Total Distortion Receive (LR = 0 dBr) Measured with a sine wave of f = 1014 Hz (C message-weighted for µ-Law, psophometrically weighted for A-Law) Preliminary Data Sheet 340 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.2 DC Characteristics TA = –40 °C to 85 °C, unless otherwise stated. Table 78 DC Characteristics Parameter Symbol Conditions Limit Values min. Unit typ. max. – – Vrms – – Vrms – – Vrms 61 – Ω – – 5 % 130 110 mA mA 3 % Line Termination Tip, Ring Sinusoidal Ringing Max. ringing voltage VRNG0 VHR – VBATH = 150 V, 85 VDC = 20 V for ring trip (DuSLIC-E/-E2) –VBATR = 150 V, VDC = 85 20 V for ring trip (DuSLIC-P) VHR – VBATH = 90 V, VDC = 20 V for ring trip 45 (DuSLIC-S/-S2) Output impedance ROUT SLIC output buffer and – RSTAB Harmonic distortion THD – Output current limit |IR, max.|, |IT, max.| Modes: Active SLIC-E/-E2/-S/-S2: SLIC-P: 80 70 – 105 90 Loop current gain accuracy – – – – Loop current offset error1) – – –0.75 – 0.75 mA Loop open resistance RTG TIP to BGND Modes: Power Down IT = 2 mA, TA = 25 °C – 5 – kΩ Loop open resistance RBG RING to VBAT Modes: Power Down IR = 2 mA, TA = 25 °C – 5 – kΩ Ring trip function – – – – – – Ring trip DC voltage – SLIC-E/-E2/-S/-S2: SLIC-P: balanced SLIC-P: unbalanced 0 0 – – – Preliminary Data Sheet 341 30 30 VBATR/2 – Vdc Vdc Vdc DS3, 2003-07-11 DuSLIC Electrical Characteristics Table 78 DC Characteristics (cont’d) Parameter Symbol Conditions Limit Values min. typ. max. Unit Ring trip detection time delay – – – – 2 cycle Ring off time delay – – – – 2 cycle 1) can be reduced with current offset error compensation described in Chapter 3.8.2.8 6.3 DuSLIC Power Up For power up of SLICOFI-2/-2S and SLIC devices please refer to the instructions given in the device data sheets. 6.4 DuSLIC Timing Characteristics TA = –40 °C to 85 °C, unless otherwise stated. 6.4.1 Input/Output Waveform for AC Tests O u tp u t P a d : Device under test VD D – 0 .5 V 0 .5 V 2 .0 V 0 .8 V T e st P o in ts IO L , IO H 2 .0 V CLoad = 5 0 p F m a x 0 .8 V In p u t P a d : Device under test VIL , VIH ezm37010 Figure 83 Waveform for AC Tests During AC-Testing, the CMOS inputs are driven at a low level of 0.8 V and a high level of 2.0 V. The CMOS outputs are measured at 0.5 V and VDD – 0.5 V respectively. Preliminary Data Sheet 342 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.4.2 MCLK/FSC Timing t MCLKh t MCLK MCLK 50% t FSC t FSC_S t FSC_H FSC ezm35000 Figure 84 MCLK/FSC-Timing Parameter Symbol Limit Values min. Period MCLK1) 512 kHz ± 100 ppM 1536 kHz ± 100 ppM 2048 kHz ± 100 ppM 4096 kHz ± 100 ppM 7168 kHz ± 100 ppM 8192 kHz ± 100 ppM tMCLK MCLK high time tMCLKh tFSC tFSC_s tFSC_h Period FSC1) FSC setup time FSC hold time FSC (or PCM) jitter time typ. Unit max. ns 1952.93 650.98 488.23 244.116 139.495 122.058 1953.13 651.04 488.28 244.141 139.509 122.070 1953.32 651.11 488.33 244.165 139.523 122.082 0.4 × tMCLK 0.5 × tMCLK 0.6 × tMCLK µs – 125 – µs 10 50 – ns 40 50 – ns +0.2 × tMCLK ns –0.2 × tMCLK – 1) The MCLK frequency must be an integer multiple of the FSC frequency. Preliminary Data Sheet 343 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.4.3 PCM Interface Timing 6.4.3.1 Single-Clocking Mode t PCLKh t PCLK PCLK 50% t FSC t FSC_H2 t FSC_S t FSC_H1 FSC t DR_S t DR_H DRA/B t dDX t dDXhz High Imp. DXA/B tdTCon t dTCoff TCA/B ezm22013 Figure 85 PCM Interface Timing – Single-Clocking Mode Parameter Symbol Limit Values min. typ. Unit max. Period PCLK1) tPCLK 1/8192 1/(n*64) with 1/128 2 ≤n ≤128 ms PCLK high time tPCLKh tFSC tFSC_s tFSC_h1 0.4 × tPCLK 0.5 × tPCLK 0.6 × tPCLK µs – 125 – µs 10 50 – ns 40 50 tFSC – tPCLK – tFSC_s ns tFSC_h2 tDR_s tDR_h 40 50 – ns 10 50 – ns 10 50 – ns Period FSC1) FSC setup time FSC hold time 1 FSC hold time 2 DRA/B setup time DRA/B hold time Preliminary Data Sheet 344 DS3, 2003-07-11 DuSLIC Electrical Characteristics Parameter Symbol Limit Values min. typ. max. tdDX 25 – tdDX_min + 0.4[ns/pF] × CLoad[pF] ns tdDXhz 25 – 50 ns tdTCon 25 – tdTCon_min + 0.4[ns/pF] × CLoad[pF] ns tdTCoff 25 – tdTCoff_min + 2 × RPullup[kΩ] × CLoad[pF]) ns 2) DXA/B delay time DXA/B delay time to high Z Unit TCA/B delay time on TCA/B delay time off 1) The PCLK frequency must be an integer multiple of the FSC frequency. 2) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad, RPullup > 1.5 kΩ) Preliminary Data Sheet 345 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.4.3.2 Double-Clocking Mode t PCLKh t PCLK PCLK 50% t FSC_S t FSC_H1 t FSC_H2 t FSC FSC t DR_S t DR_H DRA/B t dDX t dDXhz High Imp. DXA/B t dTCon t dDTCoff TCA/B ezm22014 Figure 86 PCM Interface Timing – Double-Clocking Mode Preliminary Data Sheet 346 DS3, 2003-07-11 DuSLIC Electrical Characteristics Parameter Symbol Limit Values min. typ. Unit max. Period PCLK1) tPCLK 1/8192 1/(n*64) with 1/256 4 ≤n ≤128 ms PCLK high time tPCLKh tFSC tFSC_s tFSC_h1 0.4 × tPCLK 0.5 × tPCLK 0.6 × tPCLK µs – 125 – µs 10 50 – ns 40 50 tFSC – tPCLK – tFSC_s ns tFSC_h2 tDR_s tDR_h tdDX 40 50 – ns 10 50 – ns 10 50 – ns 25 – tdDX_min + 0.4[ns/pF] × CLoad[pF] ns DXA/B delay time to tdDXhz high Z 25 – 50 ns tdTCon 25 – tdTCon_min + 0.4[ns/pF] × CLoad[pF] ns tdTCoff 25 – tdTCoff_min + 2 × RPullup[kΩ] × CLoad[pF]) ns Period FSC1) FSC setup time FSC hold time 1 FSC hold time 2 DRA/B setup time DRA/B hold time DXA/B delay time2) TCA/B delay time on TCA/B delay time off 1) The PCLK frequency must be an integer multiple of the FSC frequency. 2) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad, RPullup > 1.5 kΩ) Preliminary Data Sheet 347 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.4.4 Microcontroller Interface Timing t DCLK DCLK t DCLKh 50% t CS_S t CS_h CS t DIN_S t DIN_H DIN t dDOUThz t dDOUT High Imp. DOUT ezm22015 Figure 87 Microcontroller Interface Timing Parameter Period DCLK DCLK high time CS setup time CS hold time DIN setup time DIN hold time DOUT delay time1) DOUT delay time to high Z Symbol Limit Values Unit min. typ. max. tDCLK tDCLKh tCS_s tCS_h tDIN_s tDIN_h tdDOUT 1/8192 – – ms – 0.5 × tDCLK – µs 10 50 – ns 30 50 – ns 10 50 – ns 10 50 – ns 30 – tdDOUT_min + 0.4[ns/pF] × CLoad[pF] ns tdDOUThz 30 – 50 ns 1) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad) Preliminary Data Sheet 348 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.4.5 IOM-2 Interface Timing 6.4.5.1 Single-Clocking Mode t DCLh t DCL DCL 50% t FSC t FSC_H2 t FSC_S t FSC_H1 FSC t DD_S t DD_H DD t dDU_low t dDU_high DU ezm22016 Figure 88 IOM-2 Interface Timing – Single-Clocking Mode Parameter Symbol 1) tDCL DCL high time tDCLh Period FSC1) tFSC FSC setup time tFSC_s FSC hold time 1 tFSC_h1 FSC hold time 2 tFSC_h2 DD setup time tDD_s DD hold time tDD_h tdDU_low 2) Period DCL DU low time DU high time2) tdDU_high Limit Values min. typ. max. – 1/2048 – Unit ms 0.4 × tDCL 0.5 × tDCL 0.6 × tDCL µs – 125 – µs 10 50 – ns 40 50 tFSC – tDCL – tFSC_s ns 40 50 – ns 10 50 – ns 10 50 – ns 25 – tdDU_low (min) + 0.4[ns/pF] × CLoad[pF] ns 25 – tdDU_high (min) + 2 × Rpull-up[kΩ] × CLoad[pF] ns 1) The DCL frequency must be an integer multiple of the FSC frequency. Preliminary Data Sheet 349 DS3, 2003-07-11 DuSLIC Electrical Characteristics 2) DU low and high times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad, RPullup > 1.5 kΩ) Preliminary Data Sheet 350 DS3, 2003-07-11 DuSLIC Electrical Characteristics 6.4.5.2 Double-Clocking Mode t DCLh t DCL DCL 50% t FSC t FSC_S t FSC_H1 t FSC_H2 FSC t DD_S t DD_H DD t dDU_low t dDU_high DU Figure 89 ezm22017 IOM-2 Interface Timing – Double-Clocking Mode Parameter Symbol Period DCL1) tDCL DCL high time tDCLh 1) Period FSC tFSC FSC setup time tFSC_s FSC hold time 1 tFSC_h1 FSC hold time 2 tFSC_h2 tDD_s DD setup time DD hold time tDD_h tdDU_low 2) DU low time DU high time2) tdDU_high Limit Values min. typ. max. – 1/4096 – Unit ms 0.4 × tDCL 0.5 × tDCL 0.6 × tDCL µs – 125 – µs 10 50 – ns 40 50 tFSC – tDCL – tFSC_s ns 40 50 – ns 10 50 – ns 10 50 – ns 25 – tdDU_low (min) + 0.4[ns/pF] × CLoad[pF] ns 25 – tdDU_high (min) + 2 × Rpull-up[kΩ] × CLoad[pF] ns 1) The DCL frequency must be an integer multiple of the FSC frequency. 2) DU low and high times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad, RPullup > 1.5 kΩ) Preliminary Data Sheet 351 DS3, 2003-07-11 DuSLIC Application Circuits 7 Application Circuits Application circuits are shown for internal ringing with DuSLIC-E/-E2/-S/-P (balanced and unbalanced) and for external unbalanced ringing with DuSLIC-E/-E2/-S/-S2/-P for one line. Channel A and the SLIC must be duplicated in the circuit diagrams to show all necessary components for two channels. 7.1 Internal Ringing (Balanced/Unbalanced) Internal balanced ringing is supported up to 85 Vrms for DuSLIC-E/-E2/-P and up to 45 Vrms for DuSLIC-S. Internal unbalanced ringing is supported for SLIC-P with ringing amplitudes up to 50 Vrms without any additional components. All DuSLIC chip sets incorporate internal off-hook- and ring trip detection. Preliminary Data Sheet 352 DS3, 2003-07-11 Figure 90 Preliminary Data Sheet RING TIP RPROT 20 Ω fuseable resistor RPROT 20 Ω fuseable resistor 353 Ring U1 Tip Overvoltage Protection RSTAB 30 Ω CSTAB BGND CSTAB RSTAB 30 Ω V BATR D2 AG ND AGND BG ND PEB 4266 SLIC-P V BATL D1 BG ND R IN G TIP VDD D2 C1 D2 BG ND C1 V BATH AGND CEXT CEXT VCM S IL IT RILA RIT2A C 2A C2 RIT1A C 1A AGND CREF CVCMITA CITACA DCNA C1 CDC DCPA DCN VDDD C1 C2 AGND GNDA GNDAB C R E FA B VCM S VCM ILA AG ND GNDD P EB 3265 P EB 3264 V D D P LL AGND C1 VCCA AGND G N D P LL SLICO FI-2 SLICO FI-2S AGND VCCA Channel A VDDR AGND C1 VCCA on ly cha nn el A a nd S L IC interfa ce p ins con ne cte d for this e xam p le V C M ITA ITA ITA C A CDCPA CDCNA IO 2A ACNA DCP C3 ACPA ACP VDDA AGND C1 VCCA ACN V BATH D1 BGND BG ND D1 C1 C1 V BATR IO M -2 In terfa ce PCM / µC In te rface 7.1.1 AG ND V BATL VDD DuSLIC Application Circuits Circuit Diagrams Internal Ringing (Balanced & Unbalanced) ezm20004a2 Internal (balanced and unbalanced) Ringing with SLIC-P DS3, 2003-07-11 Figure 91 Preliminary Data Sheet RING1) TIP1) RPROT 20 Ω fuseable resistor RPROT 20 Ω fuseable resistor 354 Ring U1 Tip Overvoltage Protection RSTAB 30 Ω CSTAB BGND CSTAB RSTAB 30 Ω VHR V BA TH AG ND AGND BGND PEB 4265/-2 PEB 4264/-2 SLIC-E/-E2 SLIC-S/-S2 VDD BGND R IN G TIP C1 C1 C1 D2 IL IT CEXT AGND RILA RIT2A AGND CREF CVCMITA CITACA C2A C2 VDDD C1 C2 AG ND GNDA GNDAB C R E FA B VCM S VCM ILA AG ND GNDD PEB 3265 PEB 3264 V D D PLL AGND C1 VCCA AGND G NDPLL SLICO FI-2 SLICO FI-2S AG ND VCCA Channel A VDDR AG ND C1 VCCA on ly ch an ne l A an d S L IC inte rface pins co nn e cte d for th is exa m p le V C M ITA ITA ITA C A CDCPA CDCNA C1A VCM S CEXT RIT1A CDC DCNA DCPA C1 ACNA DCP DCN ACPA ACP VDDA AGND C1 VCCA ACN BGND C1 V BATL V BA TL BG ND AG ND BG ND D2 D1 V BATH VDD VH IO M -2 Interface PCM / µC In te rfa ce DuSLIC Application Circuits ezm20004a11 Internal (balanced) Ringing with SLIC-E/-E2 or SLIC-S/-S2 DS3, 2003-07-11 DuSLIC Application Circuits As Figure 90 shows, balanced and unbalanced internal ringing use the same line circuit. 7.1.2 Bill of Materials Table 79 shows the external passive components needed for a dual-channel solution consisting of one SLICOFI-2/-2S and two SLIC-E/-E2/-S/-S2/-P. Table 79 External Components in Application Circuit DuSLIC-E/-E2/-S/-S2/-P Rating No. Symbol Value Unit Relat. Tol. 2 RIT1 470 Ω 1% 2 RIT2 680 Ω 1% 2 RIL 1.6 kΩ 1% 4 RSTAB 30 Ω 1 %1) 4 RPROT2) 20 Ω 1 %1) 4 CSTAB 15 (typ.) nF 10 % 100 V 2 CDC 120 nF 10 % 10 V 2 CITAC 680 nF 10 % 10 V 2 CVCMIT 680 nF 10 % 10 V 1 CREF 68 nF 20 % 10 V 2 CEXT 470 nF 20 % 10 V 12 C1 100 (typ.) nF 10 % 1 C23) 4.7 µF 20 % 10 V, Tantal – D1 4) BAS21 – – – 4 D2 BAS21 – – – 2 U12) Overvoltage Protection Element – – – 1) Matching tolerance dependent on longitudinal balance requirements (for details see the Application Note External Components). 2) See Application Note Protection of DuSLIC / VINETIC Linecard Chip Sets against Overvoltages and Overcurrents. 3) As close as possible connected to VDDD and GNDD at SLICOFI-2 4) Optional; recommended only if power supply relation VBATR < VBATH < VBATL can not be guaranteed. To handle higher electromagnetic compatibility (EMC) requirements, additional effort in the circuit design may be necessary, such as a current-compensated choke of 470 µH in the Tip/Ring lines. As well as the C1 capacitors, one 22 µF capacitor per 8 Tip/Ring lines is recommended for buffering the supply voltages. Preliminary Data Sheet 355 DS3, 2003-07-11 DuSLIC Application Circuits 7.2 External Unbalanced Ringing with DuSLIC-E/-E2/-S/-S2/-P External unbalanced ringing application circuits are shown for a standard solution (see Figure 92 and Figure 93) and for a solution dedicated to higher loop lengths (see Figure 94 and Figure 95). Note: Only the codec/SLIC combinations shown in Table 3 "DuSLIC Chip Sets Presented in this Data Sheet" on Page 20 are possible. Preliminary Data Sheet 356 DS3, 2003-07-11 Figure 92 Preliminary Data Sheet 357 + 5V 1N4148 RING TIP 22 kΩ 5.1 kΩ RPROT 20 Ω fuseable resistor R PROT 20 Ω fuseable resistor External Ring Generator Ring U1 Tip Overvoltage Protection Pin RSYNC SLICOFI-2/-2S R STAB 30 Ω C STAB BGND C STAB R STAB 30 Ω VHR BGND BGND RING TIP AGND AGND PEB 4265/-2 PEB 4264/-2 SLIC-E/-E2 SLIC-S/-S2 VDD R IT1A C DC CEXT VCMS IL IT C2 AGND R ILA R IT2A AGND CREF C VCMITA CITACA DCNA AGND GNDA GNDR AGND GNDD PEB 3265 PEB 3264 (Channel A, B) VCMS CREF MCLK INT TS2/CS TS1/DCLK TS0/DIN DU/DOUT DD/DRB DCL/PCLK FSC PCM/IOM-2 AGND GNDPLL IO1A IO2A IO3A IO4A IO1B IO2B IO3B IO4B TEST RESET RSYNC TCB TCA DXB DXA SEL24/DRA SLICOFI-2 SLICOFI-2S Channel A VDDPLL AGND AGND AGND C1 VCCA SELCLK AGND C2 VCM ILA VCMITA ITA ITACA CDCPA CDCNA C2A C1A DCPA DCP DCN C1 ACNA ACN C1 VCCA VDDD AGND C1 VCCA VDDR AGND ACPA VDDA C1 VCCA ACP VBATL D2 BGND C1 CEXT BGND D2 D1 AGND VBATH C1 C1 C1 VBATL 7.2.1 BGND VBATH VDD VHR DuSLIC Application Circuits Circuit Diagrams External Unbalanced Ringing ezm14044 External Unbalanced Ringing with SLIC-E/-E2 or SLIC-S/-S2 DS3, 2003-07-11 Figure 93 Preliminary Data Sheet 358 + 5V 1N4148 RING TIP 22 kΩ 5.1 kΩ RPROT 20 Ω fuseable resistor R PROT 20 Ω fuseable resistor External Ring Generator Ring U1 Tip Overvoltage Protection Pin RSYNC SLICOFI-2/-2S * optional R STAB 30 Ω C STAB BGND C STAB R STAB 30 Ω BGND BGND RING TIP VDD D1 VBATR D2 AGND AGND PEB 4266 SLIC-P VBATL D2 C1 VBATR VCMS IL IT * C3 CEXT AGND C EXT RIT1A RILA RIT2A C1A C1 AGND C REF CVCMITA C ITACA C DC DCNA DCN VDDD C1 VCCA (Channel A, B) AGND GNDA GNDR AGND GNDD PEB 3265 PEB 3264 MCLK INT TS2/CS TS1/DCLK TS0/DIN DU/DOUT DD/DRB DCL/PCLK FSC PCM/IOM-2 AGND GNDPLL IO1A IO2A IO3A IO4A IO1B IO2B IO3B IO4B TEST RESET RSYNC TCB TCA DXB DXA SEL24/DRA VCMS CREF VDDPLL AGND AGND AGND C1 VCCA SELCLK AGND C2 SLICOFI-2 SLICOFI-2S Channel A VDDR AGND C1 VCCA VCM ILA VCMITA ITA ITACA CDCPA CDCNA C2A DCPA DCP connected to IO2A ACNA ACN C2 ACPA VDDA AGND C1 VCCA ACP D2 BGND C1 VBATH VBATH D1 BGND BGND D1 C1 C1 AGND VBATL VDD DuSLIC Application Circuits ezm14044P External Unbalanced Ringing with SLIC-P In the circuits shown in Figure 92 and Figure 93 the ring current is sensed on only one line (Tip line). It is therefore restricted to applications with low longitudinal influence (short lines). DS3, 2003-07-11 Figure 94 Preliminary Data Sheet 359 150 Ω 2 MΩ 2 MΩ 150 Ω 2 MΩ + - LM358 68 kΩ Ring U1 Tip VCMS of SLICOFI-2/-2S 68 kΩ R PROT 20 Ω fuseable resistor 2 MΩ IO1A of SLICOFI-2/-2S IO3A or IO4A of SLICOFI-2/-2S Overvoltage Protection RPROT 20 Ω fuseable resistor 22 kΩ 5.1 kΩ 1N4148 Zero Crossing Signal (TTL level) RSYNC of SLICOFI-2/-2S Ring Generator – 48 VDC 80 VRMS RING TIP Relay + 5V RSTAB 30 Ω CSTAB BGND CSTAB RSTAB 30 Ω BGND BGND RING TIP VHR VBATH AGND AGND PEB 4265/-2 PEB 4264/-2 RIT1A IL IT CEXT AGND RILA RIT2A C1A C1 AGND C REF CVCMITA C ITACA DCNA DCN CDC DCPA DCP AGND GNDA GNDR CREF VCMS VCM ILA VCMITA ITA ITACA CDCPA CDCNA C2A ACNA C2 ACPA C1 VCCA AGND GNDD PEB 3265 PEB 3264 VDDPLL AGND GNDPLL IO1A IO3A IO4A IO1B IO2B IO3B IO4B TEST RESET RSYNC TCB TCA DXB DXA SEL24/DRA MCLK INT TS2/CS TS1/DCLK TS0/DIN DU/DOUT DD/DRB DCL/PCLK FSC PCM/IOM-2 AGND AGND AGND C1 VCCA SELCLK AGND C2 SLICOFI-2 SLICOFI-2S (Channel A, B) Channel A VDDD AGND C1 VCCA VDDR AGND ACP VDDA C1 VCCA ACN VCMS VBATL D2 BGND C1 VBATL C EXT BGND D2 D1 SLIC-E/-E2 SLIC-S/-S2 VDD AGND C1 C1 C1 BGND VBATH VDD VHR DuSLIC Application Circuits ezm35003 External Unb. Ringing (Long Loops) with SLIC-E/-E2 or SLIC-S/-S2 DS3, 2003-07-11 Figure 95 Preliminary Data Sheet 360 150 Ω 2 MΩ 2 MΩ 150 Ω 2 MΩ Ring U1 Tip VCMS of SLICOFI-2/-2S 68 kΩ + - LM358 68 kΩ R PROT 20 Ω fuseable resistor 2 MΩ IO1A of SLICOFI-2/-2S IO3A or IO4A of SLICOFI-2/-2S Overvoltage Protection RPROT 20 Ω fuseable resistor 22 kΩ 5.1 kΩ 1N4148 Zero Crossing Signal (TTL level) RSYNC of SLICOFI-2/-2S Ring Generator – 48 VDC 80 VRMS RING TIP Relay + 5V * optional RSTAB 30 Ω CSTAB BGND CSTAB RSTAB 30 Ω BGND BGND RING TIP VDD C1 VBATR D1 AGND AGND PEB 4266 SLIC-P VBATR D2 VCMS IL IT * C3 CEXT AGND C EXT RIT1A RILA RIT2A C1A C1 AGND C REF CVCMITA C ITACA CDC DCNA DCN connected to IO2A DCPA DCP AGND GNDA GNDR CREF VCMS VCM ILA VCMITA ITA ITACA CDCPA CDCNA C2A ACNA C2 ACPA C1 VCCA AGND GNDD PEB 3265 PEB 3264 VDDPLL AGND GNDPLL IO1A IO3A IO4A IO1B IO2B IO3B IO4B TEST RESET RSYNC TCB TCA DXB DXA SEL24/DRA MCLK INT TS2/CS TS1/DCLK TS0/DIN DU/DOUT DD/DRB DCL/PCLK FSC PCM/IOM-2 AGND AGND AGND C1 VCCA SELCLK AGND C2 SLICOFI-2 SLICOFI-2S (Channel A, B) Channel A VDDD AGND C1 VCCA VDDR AGND ACN VDDA C1 VCCA ACP D2 BGND C1 VBATH VBATH D1 BGND BGND D1 C1 VBATL VBATL D2 AGND C1 VDD DuSLIC Application Circuits ezm35003P External Unbalanced Ringing (Long Loops) with SLIC-P DS3, 2003-07-11 DuSLIC Application Circuits In the circuits shown in Figure 94 and Figure 95 the ring current is sensed in both Tip and Ring lines. Longitudinal influence is cancelled out. This circuit therefore is recommended for long line applications. 7.3 • • • • • • • • • • • • DuSLIC Layout Recommendations For each of the supply pins of SLICOFI-2x and SLIC, 100 nF capacitors should be used. These capacitors should be placed as close as possible to the supply pin of the associated ground/supply pins. SLICOFI-2x and SLIC should be placed as close to each other as possible. SLICOFI-2x and SLIC should be placed in such way that lines ACP, ACN, DCP, DCN, IT, ITAC are as short as possible. ACP/ACN lines should be placed in parallel and symmetrical; connections via holes should be avoided. ACP/ACN lines should be run above a GND plane; DCP/DCN lines should be placed in parallel and symmetrical; connections via holes should be avoided. DCP/DCN lines should be run above a GND plane VCMITA and VCM should be connected directly (VCMITA via CVCMITA) at resistor RIT2A (680 Ω). VCMITB and VCM should be connected directly (VCMITB via CVCMITB) at resistor RIT2B (680 Ω). Use separate traces for connecting VCM/VCMITA and VCM/VCMITB; these two VCM traces should be connected directly at the VCM pin of SLICOFI-2x In case of a multilayer board, it is recommended to use one common ground layer (AGND, BGND, GNDD, GNDA, GNDB, GNDPLL connected together and share one ground layer). In case of a two-layer board, a common ground should be used for AGND, BGND, GNDD, GNDA, GNDB and GNDPLL. Ground traces should be laid out as large as possible. Connections to and from ground pins should be as short as possible. Any unused area of the board should be filled with ground (copper pouring). The connection of GND, VH and VBAT to the protection devices should be lowimpedance in order to avoid such issues as a GND shift due to the high impulse currents in case of an overvoltage strike. Tip/ring traces from the SLIC should be symmetrical. Preliminary Data Sheet 361 DS3, 2003-07-11 DuSLIC Application Circuits Parallel/symmetrical as short as possible no via holes, should run above a GND plane ACNA ACPA S LIC A DCNB DCPB IL -A IT A C A IT -A R IL A R IT 1 A IT A R IT 2 A V C M IT A C V C M IT A Connection directly at resistor VCM C V C M IT B V C M IT B R IT 2 B R IT 1 B S L IC O F I-2 x IT B R IL B IT -B Connection directly at SLICOFI-2 IT A C B IL -B DCPB S LIC B ACNB DCNB ACPB Parallel/symmetrical as short as possible no via holes, should run above a GND plane Figure 96 layout_r DuSLIC Layout Recommendation Preliminary Data Sheet 362 DS3, 2003-07-11 DuSLIC Package Outlines 8 Package Outlines P-DSO-20-5 (Plastic Dual Small Outline) Top View Gps05755 Figure 97 SLIC-S/-S2, SLIC-E/-E2, SLIC-P (PEB 426x) Note: The P-DSO-20-5 package is designed with heatsink on top. The pin counting for this package is clockwise (top view). Attention: The heatsink is connected to VBATH (VBATR) via the chip substrate. Due to the high voltage of up to 150 V between VHR and VBATH (BGND and VBATR), touching of the heatsink or any attached conducting part can be hazardous. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Preliminary Data Sheet 363 DS3, 2003-07-11 DuSLIC Package Outlines P-VQFN-48-4 (Very thin Profile Quad Flatpack No-lead) Top View Exposed Die Pad Die Pad Edge gvq09350 Figure 98 SLIC-S/-S2, SLIC-E/-E2, SLIC-P (PEB426x) Attention: The exposed die pad and die pad edges are connected to VBATH (VBATR) via the chip substrate. Due to the high voltage of up to 150 V between VHR and VBATH (VBATR and BGND), touching of the die pad or any attached conducting part can be hazardous. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Preliminary Data Sheet 364 DS3, 2003-07-11 DuSLIC Package Outlines 0.65 6.3 0.1 C (Mold) Heatslug 0.95 ±0.15 36x 0.25 M A B C 0.25 +0.13 5û±3û 0.25 2.8 1.3 15.74 ±0.1 (Heatslug) B +0.07 -0.02 11 ±0.15 1) 3.5 MAX. 0 +0.1 1.1 ±0.1 3.25 ±0.1 P-DSO-36-15 (Plastic Dual Small Outline) 14.2 ±0.3 0.25 B 36 19 5.9 ±0.1 (Metal) 19 3.2 ±0.1 (Metal) Bottom View 36 Index Marking Top View 1 x 45û 1 18 15.9 ±0.1 1) (Mold) 1) 10 A 13.7 -0.2 (Metal) 1 Heatslug Does not include plastic or metal protrusion of 0.15 max. per side gps09181 Figure 99 TSLIC-S (PEB 4364) Attention: The heatslug is connected to VBATH via the chip substrate. Due to the high voltages of up to 90 V between VHRA (VHRB) and VBATH, touching of the heatslug or any attached conducting part can be hazardous. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Preliminary Data Sheet 365 DS3, 2003-07-11 DuSLIC Package Outlines 0.65 6.3 0.1 C (Mold) Heatslug 0.95 ±0.15 36x 0.25 M A B C 0.25 +0.13 5û±3û 0.25 2.8 1.3 15.74 ±0.1 (Heatslug) B +0.07 -0.02 11 ±0.15 1) 3.5 MAX. 0 +0.1 1.1 ±0.1 3.25 ±0.1 P-DSO-36-10 (Plastic Dual Small Outline) 14.2 ±0.3 0.25 B 19 36 19 5.9 ±0.1 (Metal) 36 3.2 ±0.1 (Metal) Bottom View Index Marking Top View 1 x 45û 1 18 15.9 ±0.1 1) (Mold) 1) 10 A 13.7 -0.2 (Metal) 1 Heatslug Does not include plastic or metal protrusion of 0.15 max. per side gps09181 Figure 100 TSLIC-E (PEB 4365) Attention: The heatslug is connected to VBATH via the chip substrate. Due to the high voltages of up to 150 V between VHRA (VHRB) and VBATH, touching of the heatslug or any attached conducting part can be hazardous. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Preliminary Data Sheet 366 DS3, 2003-07-11 DuSLIC Package Outlines P-MQFP-64-1 (Plastic Metric Quad Flat Package) Top View Gpm05250 Figure 101 SLICOFI-2x (PEB 3265, PEB 3264) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Preliminary Data Sheet 367 DS3, 2003-07-11 DuSLIC Package Outlines P-TQFP-64-1 (Plastic Thin Quad Flat Package) Top View Gpm05250 Figure 102 SLICOFI-2x (PEB 3265, PEB 3264) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Preliminary Data Sheet 368 DS3, 2003-07-11 DuSLIC Terminology 9 Terminology A ACTH Active with VBATH ACTL Active with VBATL ACTR Active with VBATR or VHR and VBATH ADC Analog Digital Converter AR Attenuation Receive AX Attenuation Transmit B BP Band-pass C CMP Compander Codec Coder Decoder COP Coefficient Operation CRAM Coefficient RAM D DAC Digital Analog Converter DSP Digital Signal Processor DUP Data Upstream Persistence Counter DuSLIC Dual Channel Subscriber Line Interface Concept DuSLICOS Dual Channel Subscriber Line Interface Concept Coefficients Software E EXP Expander F FRR Frequency Response Receive Filter FRX Frequency Response Transmit Filter L LSSGR Local area transport access Switching System Generic Requirements P PCM Pulse Code Modulation Preliminary Data Sheet 369 DS3, 2003-07-11 DuSLIC Terminology PDH Power Down High Impedance PDRHL Power Down Load Resistive with VBATH and BGND PDRRL Power Down Load Resisitve with VBATR and BGND PDRH Power Down Resistive with VBATH and BGND PDRR Power Down Resistive with VBATR and BGND POFI Post Filter PREFI Antialiasing Pre Filter R RECT Rectifier (Testloops, Levelmetering) S SLIC Subscriber Line Interface Circuit (same for all versions) SLIC-S/-S2 Subscriber Line Interface Circuit Standard Feature Set PEB 4264/-2 SLIC-E/-E2 Subscriber Line Interface Circuit Enhanced Feature Set PEB 4265/-2 SLIC-P Subscriber Line Interface Circuit Enhanced Power Management PEB 4266 SLICOFI-2x Dual Channel Subscriber Line Interface Codec Filter (same for all versions) SLICOFI-2 Dual Channel Subscriber Line Interface Codec Filter PEB 3265 SLICOFI-2S Dual Channel Subscriber Line Interface Codec Filter PEB 3264 SOP Status Operation T TG Tone Generator TH Transhybrid Balancing THFIX Transhybrid Balancing Filter (fixed) TS Time Slot TSLIC-S Twin Subscriber Line Interface Circuit Standard Feature Set PEB 3264 TSLIC-E Twin Subscriber Line Interface Circuit Standard Feature Set PEB 3265 TTX Teletax Preliminary Data Sheet 370 DS3, 2003-07-11 DuSLIC Index 10 Index External Components DuSLIC-P 355 External conference 71 External Ringing 48, 94, 170, 290 Numerics 170V technology 45 A F Active 90 Active High 74, 76, 78, 80, 82 Active Low 74, 76, 78, 80, 82 Active Ring 74, 76, 78, 80, 83 Active State 52, 92 Active with HIR 74, 77, 79, 81, 83 Active with HIT 74, 77, 79, 81, 83 Active with Metering 75, 77, 141, 260, 320 Fiber in the Loop 24 First Command Byte 140, 262, 263, 322, 323 Frequency response 29, 327 FSK 30 B H Balanced ringing 46, 352 Battery feed 29 Hybrid 29 Hybrid balance C I Caller ID 23, 30, 59, 66, 157 Central Office 24 Coding 29 Constant Current Zone 35 Constant Voltage Zone 37 COP-command 141, 142, 203, 315 CRAM coefficients 205, 318 Impedance matching 29 Intelligent NT 24 Internal conference 71 IOM-2 interface 122, 129, 260, 263, 320, 323 ISDN Terminal Adapters 24 D Layout Recommendation 361 Levelmeter AC 105 DC 100 TTX 108 LIN mode 72 LIN16 mode 73 Line Echo Cancellation 30, 63, 66, 178 POP Commands 229 Line Resistance 113 Line Testing 94 E Preliminary Data Sheet Ground key 152 Ground start 77 29 L DC characteristic 38 Digital Loop Carrier 24 DTMF 30, 66, 155, 177, 179, 295 DTMF decoder 30 DTMF generator 23, 30, 56 DuSLICOS 30, 203, 315 Enhanced Digital Signal Processor 151, 157 MIPS Requirements 66 POP Commands 207 G 56, M Message waiting 371 23, 67 DS3, 2003-07-11 DuSLIC Index Metering 23, 54, 181, 183, 185, 297, 299, 301 Microcontroller interface 122, 127 Monitor Channel Operation 133 Monitor Receiver 136 Monitor Transfer Protocol 133 Monitor Transmitter 135 Private Branch Exchange 24 R Operating Modes CIDD byte SLICOFI-2 260 CIDD byte SLICOFI-2S 320 CIOP byte 141 DuSLIC 74 DuSLIC-E/-E2 80 DuSLIC-P 82 DuSLIC-S/-S2 78 Power Management 90 Overvoltage protection 29 Ramp generator 68, 79, 81, 83 Read command 127 Receive gain 29 Receive path 43, 178, 197, 199, 201, 309, 311, 313 Register Description Example 142 Reset 84, 141 Status 154, 276 Resistive Zone 36 Ring on Ring 77 Ring on Tip 77 Ring Pause 75, 77, 79, 81, 83 Ring Trip 45, 77, 341 Ringer Equivalence Number 45 Ringing 29, 45, 74, 77, 79, 81, 83, 90, 141, 260, 320 P S PCM channel 126 PCM interface 43, 122, 150, 153, 272, 275, 344 PCM mode 72, 88, 189, 193, 305, 307 PCM/µC interface 72, 122, 173, 292 PCM16 mode 73 PCM-active 71 PCM-off 71 Polarity Reversal 23, 55 POP command 142, 207 Power Dissipation Operating Modes 90 SLIC 91 SLIC output stage 39 SLICOFI-2 91 Power Down 90, 141, 167, 260, 320 Power Down High Impedance 74, 76, 141, 172, 260, 291, 320 Power Down Resistive 74, 76, 78, 80, 82 Power Down state 53, 71, 91, 197, 199, 309, 311 Power Management 20, 23, 76, 90 Second Command Byte 127, 142, 262, 263, 322, 323 Signaling 29, 52, 58, 263, 323 Sleep 74, 75, 80, 82, 141, 260, 320 Soft reversal 55, 170, 290 SOP-command 141, 144, 266 Supervision 29, 52 O Preliminary Data Sheet T Teletax Metering 30 Test Loops 119 Three-party Conferencing 68, 173 Time Slot Assignment 43, 132 TIP/RING interface 122, 139 Transmit gain 29, 328 Transmit path 43, 178, 197, 199, 201, 309, 311, 313 TTX 29, 54, 77, 170, 199, 204, 311, 317 U Unbalanced ringing 46, 90, 167, 287 Universal Tone Detection 30, 65, 66, 156 372 DS3, 2003-07-11 DuSLIC Index POP Commands 250 Universal Tone detection 177 V Voice over Packet Network Voltage reserve 34, 40 24 W Wireless Local Loop 24 Write command 127 Preliminary Data Sheet 373 2003-07-11 http://www.infineon.com Published by Infineon Technologies AG