Serial Communication NRZ NRZI • Serial communication is as widely (or even more widely used) than parallel communication – Especially true if communication occurs over long wires Non-return to zero (NRZ) normal data transitions. • Many new high speed serial communication standards have been developed – USB, IEEE Firewire, HyperTransport, etc. NRZ Inverted (NRZI, not a good description, is not inverse of NRZ). A transition for every zero bit. • This lab will introduce you to some basic serial communication concepts, namely bit-stuffing and NRZI encoding – These techniques are used in the USB (Universal Serial Bus) interface. 3/31/2002 BR Strings of zeros means lots of transitions. Strings of ‘1’s means steady line. 1 Bit Stuffing – a ‘0’ is inserted after every six consecutive ‘1’s in order to ensure a signal transition so that receiver clock can remain synchronized to the bit stream. 3/31/2002 NRZ serial stream NRZ serial stream Bit stuffing done automatically by sending logic. Sync pattern starts data transmission and is seven ‘0’s followed by a ‘1’. BR 3 Bit Stuff (insert a ‘0’ after every 6 consecutive ‘1’s) Bit DeStuff (remove a ‘0’ after every 6 consecutive ‘1’s) 3/31/2002 – reset – synchronous reset, high true – clk – clock signal – serclk – clock signal for serial stream (clk divided by 4, one pulse for every four clks) – sin - NRZ serial input stream – start – will be high for one clock cycle indicating start of valid data on serial NRZ stream. Serial bit is valid every time ‘serclk’ = ‘1’. NRZ bitstuffed serial stream (sout_nrz) NRZ bitstuffed serial stream NRZI bitstuffed serial stream NRZI Encoding (sout_nrzi) NRZI Decode Bytes send LSB first!!! BR The Task • Design a block that performs bitstuffing of a ‘0’ after every six consecutive ‘1’s from an NRZ serial stream and does NRZI encoding of the output • Inputs 2 You must design these two blocks (sin) 3/31/2002 BR 4 Testbench You are provided with a testbench called tbusbser clk Ser clock sclk gen clk reset start sin usbser (an empty schematic, do your work here) bit_insert sout_nrz sout_nrzi • Outputs Dout[7..0] – Sout_nrzi -- bit stuffed stream, NRZI encoding – Sout_nrz – bit stuffed stream, NRZ encoding (use this for debugging) – Bit_insert – assert high whenever a ‘0’ bit is inserted (use this for debugging). 3/31/2002 BR De-serialized byte output 5 3/31/2002 DES (de-serializer, provided by me) BR 6 1 Part 2: Read 32 Bytes from Ram and send over serial interface tbusbser_gold.scf • tbusbser_gold.scf is the golden waveform • Provides all input signals (start, reset, clk and most importantly, the serial input stream sin ) • The DES block is provided de-serializes the sout_nrzi stream into bytes usbserp2.gdf (part 2) addr 5 – This byte stream shown as dout[7..0] on the golden waveform Din • It might help to look at the structure of the DES block before attempting your design, it might give you some ideas. sin_nrz 32byte RAM 8 Shift Reg usbser sout_nrzi (part 1) 8 FSM Bytes send LSB first!!! 3/31/2002 BR 7 3/31/2002 • RAM, counter for address lines, shift register already in usbserp2.gdf schematic • Exactly the same as used for bifilt interface • Inputs – Clock generator for serclk included also – Clk, reset – clock and asynchronous reset – we, addr[4..0], din[7..0] – write enable, address, data for RAM – start – when start asserted, read 32 bytes from RAM from send over serial interface (usbser done in part 1) • May have to add other datapath elements as well (perhaps a 3 bit counter for determining when 8 bits are shifted out), maybe other components as well • Have to add a FSM that will control reading of RAM and shift register • Outputs – busy – asserted when sending reading ram and sending serial data – sout_nrzi – serial output (bit stuffed, NRZI) from usbser block BR – Will also have to monitor bit_insert output from usbser block – if inserting a bit into the serial data stream will have to halt shift operation 9 3/31/2002 Part #2 Testbench (tbusbserp2.gdf ) tbusbserp2.gdf connects the usbserp2 block to the deserializer block • The output of the deserializer block will match the values read from RAM if the everything is working ok. • Golden waveform is tbusbserp2_gold.scf BR BR 10 Due Dates • 3/31/2002 8 usbserp2.gdf datapath, FSM usbserp2.gdf Interface 3/31/2002 BR • • • • • One week for each part 1 and part 2. Each part is about the same difficulty Each part is worth 100 points. No extra credit for this lab. Only functional requirements, no clock frequency requirements. • Can use any mixture of VHDL + schematic capture for the design. 11 3/31/2002 BR 12 2 DESerializer Operation NRZI bitstuffed serial stream Bit DeStuff (remove a ‘0’ after every 6 NRZ consecutive bitstuffed ‘1’s) serial stream NRZI Decode Dout[7..0] equal sin_nrzi D Q en en LD D Q sin_nrz LD newbit NRZ serial stream D Q S0 sin_nrzi S1 S2 Shift Register S3 S4 3/31/2002 If last bit = this bit, then output a ‘1’ else ‘0’. NRZI Decode Understanding the DESerializer operation may help with implementation of the serializer. BR 13 3/31/2002 en newbit is asserted when sin_nrz has valid data. S0 is reset state. Sin_nrzi = 0 is start of transmission (idle state is ‘1’, a ‘0’ bit is always transmitted first). en is asserted every four clocks (know that serial clock is ¼ of clock frequency). BR 14 S0 S1 S2 S6 0 newbit 1 sin 1 0 newbit 1 sin 1 0 pause asserted when six ‘1’ bits detected. The pause signal used to halt shift register so that the ‘0’ bit which was stuffed is not shifted into register. 0 0 pause newbit 3/31/2002 Bit De-stuffing 0 newbit 1 sin 1 0 BR 15 3