1.8V 8 6 7 2 3 4 5 1 REVISIONS SYNC_IO-BUF SDO SDIO SCLK-BUF CSB-BUF 0 0 0 0 0 MPI04 MPI03 MPI02 MPI01 MPI00 R106 R107 R108 R109 3.3V R114 0 100 GND C122 DACBP DNI R133 P102-DRCTL-BUF DNI 0.1UF DNI C119 1UF GND 50 R123 1 J108 SINGLE-ENDED DAC OUT 0.1UF 6 1 T102 5 4 3 2 AOUTN 100 OHM DIFF PAIR C106 PRI SEC 0.1UF 4 3 50 R124 B GND C107 T102 PIN3 TO J108 ALL GND PINS GROUND POUR TOP LAYER R135 0 J105-DRCTL-BUF 1 J105 0 5 4 3 2 GND TSW-110-08-G-S GND A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9914 ENGINEERING BD. DESIGN VIEW <DESIGN_VIEW> DRAWING NO. REV 9914EE04 A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 7 ENABLE CLK INPUT 2 1 R138 150 R127 50 GND GND DIGITAL RAMP CONTROL 3.3V TSW-110-08-G-S 8 P105 0.1UF C120 R136 0 R128 150 1 43PF 560PF GND 3.3K GND GND GND 3.3V DNI 3.3V GND C 0.1UF DRCTL-BUF U203-DRCTL-BUF A C101 R121 R129 GND C121 C115 0.1UF RSET GND GND GND 100 OHM DIFF PAIR 3.3V 5 4 3 2 DRCTL-BUF TO U100 AD9914 PIN# 63 1 2 3 4 5 6 7 8 9 10 GND TP100 600OHM AD9914_PRELIM DNI P103 0 P102 1 2 3 4 5 6 7 8 9 10 TSW-110-08-G-S DNI C112 0.1UF 3.3V R134 DROVR-BUF DRHOLD-BUF P102-DRCTL-BUF PS0-BUF PS1-BUF PS2-BUF GND C114 0.1UF 3.3V U101 J111 1 TRIGGER OUT 0 TC1-1-13M+ EXTPDCTL-BUF OSK-BUF RESET-BUF GND GND VTUNE 13 8 GND CONFIGURE AS TRIPLE ROW HEADER LABEL ALL SIGNALS ON SILKSCREEN AT PIN LABEL POWER/GND ON BOTH EDGES OF HEADER P100 1 2 3 4 5 6 7 8 9 10 DNI DNI GND C118 1UF AOUTP 3.3V 3.3V 3.3V 3.3V PS0-BUF PS1-BUF PS2-BUF IOCFG0 IOCFG1 IOCFG2 IOCFG3 B 50 DNI R139B 1.8V DVDD DVSS PS0 PS1 PS2 IOCFG0 IOCFG1 IOCFG2 IOCFG3 AVDD AVSS AVDD3 AVSS3 AVDD3 AVSS3 AVSS3 AVDD3 AVDD3 AOUTN AOUTP AVDD3 AVSS3 1.8V 1.8V GND 14 7 R122 1.8V CLKP CLKN 3.3V 3.3V PAD VCO FILTER R111B 2 GND C116B 0.22UF TPGND PAD 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 50 R137B 1 GND GND ADCLK925BCPZ-WP CLOSE TO DUT C117 GND GND 0.22UF 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 REMOVE FOR PARALLEL USE 3.3V SEVERAL VIAS GND GND GND 0.1UF 2 3 4 5 150 R105 GND CLOSE TO DUT OSK-BUF DROVR DRHOLD-BUF DRCTL-BUF SYNC IN SYNC OUT 3.3V REG E100 VTUNE VT=VREF C104 R126 SYNC_IO SDO SDIO SCLK CSB SYNC IN 150 1 R125 J102 GND GND 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 C105 0.1UF GND DRCTL-BUF DNI D GND 12 11 10 9 PLEASE SILKSCREEN AT PIN AD9914 DNI GND 0 MPI18 MPI19 2 3 4 5 EXTAMPCTL SWPOVR LSHOLD LSCTL SYNCIN SYNCOUT AVDD3 REG VTUNE AVDD AVDD CLKP CLKN AVDD3 AVDD3 AVSS3 AVDD3 AVSS3 RSET AVDD3 AVSS3 DACBP U100 GND VCC Q1 Q1_N Q2 Q2_N MPI12 MPI11 MPI10 MPI09 MPI08 MPI07 MPI06 MPI05 3.3V MPIO17 MPIO16 MPIO15 MPIO14 MPIO13 DVDD DVSS MPIO12 MPIO11 MPIO10 MPIO9 MPIO8 MPIO7 MPIO6 MPIO5 DVDD3 DVSS3 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 5 4 3 2 2 3 4 5 VT VREF D D_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MPI17 MPI16 MPI15 MPI14 MPI13 1.8V 1 16 15 1 2 PIN 1 1 GND ONLY USE WITH J105 GND SYNC OUT C100 GND GND GND GND MPI27 MPI28 MPI29 MPI30 MPI31 EXTPDCTL-BUF GND GND J103 1 3.3V SYNCCLK MPI20 MPI21 MPI22 MPI23 MPI24 MPI25 MPI26 DNI RESET-BUF 5 4 3 2 IOUPDATE-BUF DNI 50 0 0 0 DNI 5 4 3 2 J104 J109 VEE MPI31 MPI30 MPI29 MPI28 MPI27 MPI26 MPI25 MPI24 MPI23 MPI22 MPI21 MPI20 MPI19 MPI18 MPI17 MPI16 MPI15 MPI14 MPI13 MPI12 MPI11 MPI10 MPI09 MPI08 MPI07 MPI06 MPI05 MPI04 MPI03 MPI02 MPI01 MPI00 R131 J100 PAD MPIO18 MPIO19 IOUPDATE RESET DVSS3 DVDD3 IOSYNCCLK MPIO20 MPIO21 MPIO22 MPIO23 MPIO24 MPIO25 MPIO26 DVSS DVDD MPIO27 MPIO28 MPIO29 MPIO30 MPIO31 EXTPDCTL SYNC_IO-BUF R130 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 J101 1 SINGLE ENDED CLK IN PAD C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 R132 D IOCFG0 IOCFG1 IOCFG2 IOCFG3 RESET-BUF P101C-IOUPDATE-BUF APPROVED DATE SYNCCLK 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 J101-IOUPDATE-BUF U202-IOUPDATE-BUF P101A P101C-IOUPDATE-BUF DESCRIPTION ONLY USE WITH J101 R136B P101B P101C REV IOUPDATE-BUF TO U100 AD9914 PIN# 86 IOUPDATE-BUF CONFIGURE AS TRIPLE ROW HEADER LABEL ALL SIGNALS ON SILKSCREEN AT PIN LABEL POWER/GND ON BOTH EDGES OF HEADER 6 5 4 3 <PTD_ENGINEER> 2 D SCALE NONE SHEET 1 1 OF 3 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION APPROVED DATE D D R205 100K R206 100K 3.3V SYNC_IO CSB SDIO SCLK 3.3V SDO-BUF C205 10UF C206 1UF SYNC_IO CSB SDIO SCLK SDO PLEASE SILKSCREEN AT PIN 74LVC541APW 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 U200 C201B C 3.3V 2.2UF D200 GND C GND R201 A C203 3.3V USB_D+ USB_D- 470 LNJ308G8TRA (GREEN) P201 GND PINS 1 2 3 4 100 OHM DIFF PAIR VBUS R202 1MEG G1 G2 C204 0.047UF GND 3.3V GND1 3.3V CY7C68013A-128AXC 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 DROVR-BUF DRHOLD DRCTL OSK GND DROVR DRHOLD DRCTL OSK 1 EXTPDCTL RESET EXTPDCTL R200 10K P202 GND 3.3V GND 74LVC541APW P205 GND 3.3V 20 2 3 4 5 6 7 8 9 SDO CSB SCLK IOUPDATE 3.3V 10 VCC GND I0 O0 I1 O1 I2 O2 O3 I3 O4 I4 I5 O5 I6 O6 I7 O7 EN1_N EN2_N 1 SAMTECTSW10608GS3PIN U202 18 SDO-BUF 17 CSB-BUF 16 SCLK-BUF 15 14 U202-IOUPDATE-BUF 13 12 11 19 ENABLE DISABLE 3.3V GND 74LVC541APW 3.3V 3.3V PS2 PS1 PS0 IOUPDATE 3.3V GND RESET OSK EXTPDCTL RESET SYNC_IO GND PS2 PS1 PS0 IOUPDATE 24LC00-I/P 3.3V VCC NC4 SCL SDA 1 2 NC1 NC2 NC3 VSS ENABLE 3.3V GND 20 8 7 6 5 C USB CONTROL DISABLE U201 1 2 3 GND 4 19 PLEASE SILKSCREEN AT PIN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 2.2K R204 2.2K A2 A1 A0 GND6 PA7/FLAGD/SLCS_N PA6/PKTEND PA5/FIFOADR1 PA4/FIFOADR0 D7 D6 D5 PA3/WU2 PA2/SLOE PA1/INT1_N PA0/INT0_N VCC6 GND5 PC7/GPIFADR7 PC6/GPIFADR6 PC5/GPIFADR5 PC4/GPIFADR4 PC3/GPIFADR3 PC2/GPIFADR2 PC1/GPIFADR1 PC0/GPIFADR0 CTL2/FLAGC CTL1/FLAGB CTL0/FLAGA VCC5 CTL4 CTL3 GND4 GND DROVR 2 VCC I0 O0 DRHOLD 3 O1 I1 DRCTL 4 I2 O2 5 I3 O3 6 I4 O4 PS0 7 I5 O5 PS1 8 I6 O6 PS2 9 I7 O7 EN1_N EN2_N U203 18 DROVR-BUF 17 DRHOLD-BUF 16 U203-DRCTL-BUF 15 14 13 PS0-BUF 12 PS1-BUF 11 PS2-BUF 2 3 4 5 6 7 8 9 10 VCC GND I0 O0 I1 O1 I2 O2 I3 O3 I4 O4 I5 O5 I6 O6 I7 O7 EN1_N EN2_N 1 B P203 1 2 3 R203 B CLKOUT VCC GND RDY0/SLRD RDY1/SLWR RDY2 RDY3 RDY4 RDY5 AVCC1 XTALOUT XTALIN AGND1 NC1 NC2 NC3 AVCC2 DPLUS DMINUS AGND2 A11 A12 A13 A14 A15 VCC1 GND1 INT4 T0 T1 T2 IFCLK 10 1 2 3 USB CONNECTOR 12PF 1 2 24.000MEGHZ 12PF Y200 2 1 C202 1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A10 A9 A8 GND8 PD7/FD15 PD6/FD14 PD5/FD13 PD4/FD12 A7 A6 A5 A4 GND7 PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RXD1OUT PE3/RXD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT VCC8 INT5_N PD3/FD11 PD2/FD10 PD1/FD9 PD0/FD8 WAKEUP VCC7 RESET_N CTL5 A3 0.1UF GND 20 RESERVED BKPT EA SCL SDA OE_N PSEN_N RD_N WR_N CS_N VCC2 PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 VCC3 GND2 TXD0 RXD0 TXD1 RXD1 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 GND3 D0 D1 D2 D3 D4 VCC4 C200B 3.3V U204 18OSK-BUF 17EXTPDCTL-BUF 16RESET-BUF 15SYNC_IO-BUF 14 13 12 11 SAMTECTSW10608GS3PIN 19 PLEASE SILKSCREEN AT PIN DISABLE 3.3V ENABLE GND P204 1 2 3 SAMTECTSW10608GS3PIN A A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9914 ENGINEERING BD. DESIGN VIEW <DESIGN_VIEW> DRAWING NO. REV 9914EE04 A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 <PTD_ENGINEER> 2 D SCALE NONE SHEET 1 2 OF 3 8 6 7 4 5 2 3 1 REVISIONS REV DESCRIPTION DATE APPROVED C322 0.1UF C321 0.1UF C320 0.1UF C319 0.1UF C318 0.1UF C317 0.1UF C316 0.1UF C315 0.1UF C314 0.1UF C313 0.1UF C312 0.1UF C311B 10UF POWER SUPPLY BYPASS CAPACITORS CYP7C68013A POWER SUPPLY HOOKUP LABEL ALL SUPPLY NAMES ON SILKSCREEN AT PIN D D GND P300 3.3V GND 1.8V 3.3V 1 2 3 4 C351B 0.1UF C350B 0.1UF C349B 0.1UF C348B 0.1UF C347B 0.1UF C346B 0.1UF C345B 0.1UF C344B 0.1UF C343B 0.1UF 0.1UF AD9914 C303 0.1UF 0.1UF C302 C300 10UF C301 POWER SUPPLY BYPASS CAPACITORS 1.8V C342B 0.1UF C341B 0.1UF C340 0.1UF C339 0.1UF C338 0.1UF C337 0.1UF Z5.530.0425.0 3.3V 0.1UF 0.1UF C306 J300 1 1.8V C 5 4 3 2 GND 0.1UF 10UF C308 1.8V C307 C 10UF C305 C304 DNI DNI J301 3.3V 0.1UF 10UF C310 C309 3.3V 1 5 4 3 2 GND C366 10UF C367 0.1UF C368 10UF C369 0.1UF C370 3.3V 0.1UF 0.1UF C371B 0.1UF C371 3.3V B 0.1UF 0.1UF C374 C372 10UF B C373 3.3V C382 0.1UF C384 0.1UF C388 0.1UF C381 10UF 3.3V C383 10UF 1.8V C385 10UF 1.8V C387 10UF 3.3V GND A A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9914 ENGINEERING BD. DESIGN VIEW <DESIGN_VIEW> DRAWING NO. REV 9914EE04 A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 <PTD_ENGINEER> 2 D SCALE NONE SHEET 1 3 OF 3