CY8C20110, CY8C20180, CY8C20160, CY8C20140, CY8C20142: CapSense® Express™ Button Capacitive Controllers

CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
®
CapSense Express™ Button
Capacitive Controllers
CapSense® Express™ Button Capacitive Controllers
Overview
■
10/8/6/4 capacitive button input
❐ Robust sensing algorithm
❐ High sensitivity, low noise
❐ Immunity to RF and AC noise
❐ Low radiated EMC noise
❐ Supports wide range of input capacitance, sensor shapes,
and sizes
These CapSense Express™ controllers support four to ten
capacitive sensing (CapSense) buttons. The device functionality
is configured through an I2C port and can be stored in onboard
nonvolatile memory for automatic loading at power-on. The
CY8C20110 is optimized for dimming LEDs in 15 selectable duty
cycles for back light applications. The device can be configured
to have up to 10 GPIOs connected to the PWM output. The PWM
duty cycle is programmable for variable LED intensities.
■
Target applications
❐ Printers
❐ Cellular handsets
❐ LCD monitors
❐ Portable DVD players
■
Low operating current
❐ Active current: continuous sensor scan: 1.5 mA
❐ Deep sleep current: 4 µA
■
Industry's best configurability
❐ Custom sensor tuning, one optional capacitor
❐ Output supports strong drive for LED
2
❐ Output state can be controlled through I C or directly from
CapSense® input state
2
❐ Run time reconfigurable over I C
The four key blocks that make up these devices are: a robust
capacitive sensing core with high immunity against radiated and
conductive noise, control registers with nonvolatile storage,
configurable outputs, and I2C communications. The user can
configure registers with parameters needed to adjust the
operation and sensitivity of the CapSense buttons and outputs
and permanently store the settings. The standard I2C serial
communication interface enables the host to configure the
device and read sensor information in real time. The I2C address
is fully configurable without any external hardware strapping.
■
Advanced features
❐ All GPIOs support LED dimming with configurable delay
option in CY8C20110
❐ Interrupt outputs
❐ User defined inputs
❐ Wake on interrupt input
❐ Sleep control pin
❐ Nonvolatile storage of custom settings
❐ Easy integration into existing products – configure output to
match system
❐ No external components required
❐ World-class free configuration tool
■
Wide range of operating voltages
❐ 2.4 V to 2.9 V
❐ 3.10 V to 3.6 V
❐ 4.75 V to 5.25 V
■
I2C communication
❐ Supported from 1.8 V
❐ Internal pull-up resistor support option
❐ Data rate up to 400 kbps
2
❐ Configurable I C addressing
■
Industrial temperature range: –40 °C to +85 °C
■
Available in 16-pin QFN, 8-pin, and 16-pin SOIC packages
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Features
Errata: For information on silicon errata, see “Errata” on page 40. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 001-54606 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 19, 2016
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Contents
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Button Layout Design ................................................ 18
Recommended via Hole Placement .......................... 18
Example PCB Layout Design with Two
CapSense Buttons and Two LEDs ............................ 20
Operating Voltages ......................................................... 21
CapSense Constraints ................................................... 21
Absolute Maximum Ratings .......................................... 22
Operating Temperature .................................................. 22
Electrical Specifications ................................................ 23
DC Electrical Specifications ...................................... 23
CapSense Electrical Characteristics ......................... 26
AC Electrical Specifications ....................................... 26
Appendix ......................................................................... 29
Examples of Frequently Used I2C Commands ......... 29
Ordering Information ...................................................... 30
Ordering Code Definitions ......................................... 30
Thermal Impedances ..................................................... 31
Solder Reflow Specifications ........................................ 31
Package Diagrams .......................................................... 32
Acronyms ........................................................................ 34
Reference Documents .................................................... 34
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Numeric Conventions ................................................ 34
Glossary .......................................................................... 35
Errata ............................................................................... 40
CY8C20110 ............................................................... 40
CY8C20140/142/160/180/1A0 .................................. 41
Document History Page ................................................. 43
Sales, Solutions, and Legal Information ...................... 45
Worldwide Sales and Design Support ....................... 45
Products .................................................................... 45
PSoC® Solutions ...................................................... 45
Cypress Developer Community ................................. 45
Technical Support ..................................................... 45
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Pinouts -16-Pin QFN ......................................................... 3
Pin Definitions .................................................................. 3
Pinouts - 16-Pin SOIC ....................................................... 4
Pin Definitions .................................................................. 4
Pinouts - 8-pin SOIC ......................................................... 5
Pin Definitions .................................................................. 5
Typical Circuits ................................................................. 6
I2C Interface ...................................................................... 8
I2C Device Addressing ................................................ 8
I2C Clock Stretching .................................................... 8
Format for Register Write and Read ........................... 9
Operating Modes of I2C Commands ............................. 10
Normal Mode ............................................................. 10
Setup Mode ............................................................... 10
Device Operation Modes ................................................ 10
Active Mode ............................................................... 10
Periodic Sleep Mode ................................................. 10
Deep Sleep Mode ...................................................... 10
Sleep Control Pin ............................................................ 10
Interrupt Pin to Master ................................................... 10
LED Dimming .................................................................. 10
LED Dimming Mode 1: Change Intensity on
ON/OFF Button Status .............................................. 11
LED Dimming Mode 2: Flash Intensity on
ON Button Status ...................................................... 11
LED Dimming Mode 3: Hold Intensity After
ON/OFF Button Transition ......................................... 12
LED Dimming Mode 4: Toggle Intensity on
ON/OFF or OFF/ON Button Transitions .................... 12
Registers ......................................................................... 13
Register Map ............................................................. 13
Device IDs ................................................................. 17
CapSense Express Commands ................................ 17
Register Conventions ................................................ 17
Layout Guidelines and Best Practices ......................... 18
CapSense Button Shapes ......................................... 18
Document Number: 001-54606 Rev. *M
Page 2 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Pinouts -16-Pin QFN
Figure 1. 16-pin QFN (3 × 3 × 0.6 mm) (no e-pad) Pinout[1]
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QFN
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Pin Definitions
Pin No.
Pin Name
Description
Configurable as CapSense or GPIO
2
GP0[1]
Configurable as CapSense or GPIO
3
I2C SCL
I2C clock
4
I2C SDA
I2C data
5
GP1[0]
6
GP1[1][3]
7
VSS
8
GP1[2][3]
Configurable as CapSense or GPIO
9
GP1[3]
Configurable as CapSense or GPIO
10
GP1[4]
Configurable as CapSense or GPIO
11
XRES
Active high external reset with internal pull-down
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Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
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Ground connection
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GP0[2]
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GP0[0]
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16-pin QFN (no e-pad)[1, 2]
13
VDD
14
GP0[3]
15
CSInt
16
GP0[4]
Configurable as CapSense or GPIO
Supply voltage
Configurable as CapSense or GPIO
Integrating capacitor Input. The external capacitance is required only if 5:1 SNR cannot be achieved.
Typical range is 1 nF to 4.7 nF
Configurable as CapSense or GPIO
Notes
1. CY8C20110 (10 Buttons) / CY8C20180 (8 Buttons) / CY8C20160 (6 Buttons) / CY8C20140 (4 Buttons)
2. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package
are not available for any functionality.
3. Avoid using GP1[1] and GP1[2] for driving LEDs. These two pins have special functions during power-up which is used at factory. LEDs connected to these two pins
blink during the power-up of the device.
Document Number: 001-54606 Rev. *M
Page 3 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Pinouts - 16-Pin SOIC
Figure 2. 16-pin SOIC (150 Mils) Pinout[4]
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Pin Definitions
16-pin SOIC[4, 5]
Name
d
Pin No.
GP0[3]
2
CSint
Configurable as CapSense or GPIO
3
GP0[4]
Configurable as CapSense or GPIO
4
GP0[0]
Configurable as CapSense or GPIO
5
GP0[1]
Configurable as CapSense or GPIO
6
I2C
I2C clock
7
I2
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1
C SDA
GP1[1][6]
I2C data
Configurable as CapSense or GPIO
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GP1[0]
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SCL
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Integrating capacitor input. The external capacitance is required only if 5:1 SNR cannot be achieved.
Typical range is 1 nF to 4.7 nF.
8
Configurable as CapSense or GPIO
VSS
11
GP1[2][6]
Ground connection
Configurable as CapSense or GPIO
12
GP1[3]
Configurable as CapSense or GPIO
GP1[4]
Configurable as CapSense or GPIO
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10
13
Description
14
XRES
Active high external reset with internal pull-down
15
GP0[2]
Configurable as CapSense or GPIO
16
VDD
Supply voltage
Notes
4. CY8C20110 (10 Buttons) / CY8C20180 (8 Buttons) / CY8C20160 (6 Buttons) / CY8C20140 (4 Buttons)
5. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package
are not available for any functionality.
6. Avoid using GP1[1] and GP1[2] for driving LEDs. These two pins have special functions during power-up which is used at factory. LEDs connected to these two pins
blink during the power-up of the device.
Document Number: 001-54606 Rev. *M
Page 4 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Pinouts - 8-pin SOIC
Figure 3. 8-pin SOIC (150 Mils) pinout
CY8C20142 (4 Button)
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Pin Definitions
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8-pin SOIC
CY8C20142 (4 Button)
Name
Description
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Pin No.
VSS
2
I2C SCL
I2C Clock
Ground
3
I2C SDA
I2C Data
4
GP1[0][7]
Configurable as CapSense or GPIO
5
GP1[1][7]
Configurable as CapSense or GPIO
6
GP0[0]
Configurable as CapSense or GPIO
7
GP0[1]
Configurable as CapSense or GPIO
8
VDD
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Supply voltage
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Important Note For information on the preferred dimensions for mounting QFN packages, see the "Application Notes for Surface
Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.
Note
7. Avoid using GP1[0] and GP1[1] for driving LED. These two pins have special functions during power up which is used at factory. LEDs connected to these two pins
will blink during power up of the device.
Document Number: 001-54606 Rev. *M
Page 5 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Typical Circuits
Figure 4. Circuit 1 – Five Buttons and Five LEDs with I2C Interface
CapSense
sensor
B2
B3
VDD_CE
C1
560E
1.2nF 560E
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VDD_CE
R1
R2
C2
0.1uF
2
13
VDD
14
15
GPO[1]
XRES
12
11
R9
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GP1[3]
9
CapSense
sensor
R11
VDD_CE
560E
D3
LED
560E
D4
LED
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5
10
B4
GP1[2]
I2C_SDA
GP1[0]
4
GP1[4]
560E
8
330E
I2C_SCL
VSS
3
R6
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560E
GPO[2]
CY8C20110
330E
R10
R7
GPO[0]
7
R8
LED
1
D
D2
560E
GP1[1]
R4
4.7K
I2C COMM
INTERFACE
R5
VDD_CE
6
R3
4.7K
LED
GP0[3]
D1
GPO[4]
U1
CSint
16
VDD_CE
R13
R14
560E
560E
560E
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D5
LED
VDD_CE B1
B0
CapSense
sensor
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Figure 5. Circuit 2 – Two Buttons and Two LEDs with I2C Interface
CapSense
Sensor
Document Number: 001-54606 Rev. *M
CapSense
Sensor
Page 6 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Typical Circuits (continued)
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Figure 6. Circuit 3 – Compatibility with 1.8 V I2C Signaling[8, 9]
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CapSense
Sensor
CapSense
Sensor
Output
enable
Output
VDD
LED
I2C Pull
UPs
CapSense Express
SDA
I2C
BUS
SCL
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Master
Or
Host
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LDO
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Figure 7. Circuit 4 – Powering Down CapSense Express Device for Low Power Requirements[10]
Notes
8. 1.8 V  VDD_I2C  VDD_CE and 2.4 V  VDD_CE  5.25 V.
9. The I2C drive mode of the CapSense device should be configured properly before using in an I2C environment with external pull-ups. Please refer to I2C_ADDR_DM
register and its factory setting.
10. For low power requirements, if VDD is to be turned off, this concept can be used. The requirement is that the VDDs of CapSense Express, I2C pull-ups, and LEDs
should be from the same source such that turning off the VDD ensures that no signal is applied to the device while it is unpowered. The I2C signals should not be
driven high by the master in this situation. If a port pin or group of port pins of the master can cater to the power supply requirements of the circuit, the LDO can be
avoided.
Document Number: 001-54606 Rev. *M
Page 7 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
I2C Interface
The CapSense Express devices support the industry-standard I2C protocol, which can be used for:
■
Configuring the device
■
Reading the status and data registers of the device
■
Controlling device operation
■
Executing commands
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The I2C address can be modified during configuration.
I2C Device Addressing
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The device uses a seven-bit addressing protocol. The I2C data transfer is always initiated by the master sending a one-byte address:
the first seven bits contain the address and the LSB indicates the data transfer direction. Zero in the LSB bit indicates the write
transaction from master and one indicates the read transfer by the master. The following table shows examples for different I2C
addresses.
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Table 1. I2C Address Examples
D7
D6
D5
D4
D3
D2
D1
D0
8-bit Slave Address
1
0
0
0
0
0
0
1
0(W)
02
1
0
0
0
0
0
0
1
1(R)
03
75
1
0
0
1
0
1
1
0(W)
96
75
1
0
0
1
1
1(W)
97
0
1
bit is transmitted. The I2C master must check the SCL status (it
should be high) before the I2C master initiates any data transfer
with CapSense Express. If the master fails to do so and
continues to communicate, the communication is erroneous.
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‘Clock stretching’ or ‘bus stalling’ in I2C communication protocol
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait
until the SCL is released by the slave.
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I2C Clock Stretching
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7-bit Slave Address
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When an I2C master communicates with the CapSense Express
device, the CapSense Express stalls the I2C bus after the
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I2C compliant master to communicate
with the CapSense Express device.
The following diagrams represent the ACK time delays shown in
Format for Register Write and Read on page 9 for write and read.
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If the I2C master does not support clock stretching (a bit banged
software I2C Master), the master must wait for a specific amount
of time (as specified in Format for Register Write and Read on
page 9) for each register write and read operation before the next
Also note that, while using CapSense Express Devices on an I2C
bus, I2C master should not generate a start or stop condition in
the I2C bus before CapSense Express device generates an
acknowledgement (ACK/NCK) for the previous transaction. An
acknowledgement state produced by the CapSense Express
Device for the previous data after the master generates a start
condition or stop condition, may produce unexpected behavior
from CapSense Express I2C slave interface.
Document Number: 001-54606 Rev. *M
Page 8 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
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Figure 8. Write ACK Time Representation[11]
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Figure 9. Read ACK Time Representation[12]
Register write format
Start
Slave Addr + W
A
Reg Addr
A
A
Reg Addr
Data
A
Data
A
A
Stop
Data
A
A
Data
.....
A
.....
Data
Data
N
A
Stop
Stop
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A – ACK
N – NAK
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Legends:
Master
Slave
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Register read format
Start
Slave Addr + W
Start
Slave Addr + R
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Format for Register Write and Read
Notes
11. Time to process the received data.
12. Time taken for the device to send next byte.
Document Number: 001-54606 Rev. *M
Page 9 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Operating Modes of I2C Commands
The sleep interval should be 8 Hz or 1 Hz when using save to
flash command. The configuration sequence should be:
1. Write configuration data to registers with sleep interval being
8 Hz or 1 Hz
2. Save the settings to flash
3. Change the sleep interval as per design.
Normal Mode
In normal mode of operation, the acknowledgment time[13] is
optimized. The timings remain approximately the same for
different configurations of the slave. To reduce the
acknowledgment times in normal mode, the registers
0x06–0x09, 0x0C, 0x0D, 0x10–0x17, 0x50, 0x51, 0x57–0x60,
0x7E are given only read access. Write to these registers can be
done only in setup mode.
Deep Sleep Mode
Device Operation Modes
Sleep Control Pin
CapSense Express devices are configured to operate in any of
the following three modes to meet different power consumption
requirements:
The devices require a dedicated sleep control pin to enable
reliable I2C communication in case any sleep mode is enabled.
This is achieved by pulling the sleep control pin low to wake up
the device and start I2C communication. The sleep control pin
can be configured on any GPIO.
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All registers have read and write access (except those which are
read only) in this mode. The acknowledgment times[14] are
longer compared to normal mode. When CapSense scanning is
disabled (command code 0x0A in command register 0xA0), the
acknowledgment times can be improved to values similar to the
normal mode of operation.
Deep Sleep mode provides the lowest power consumption
because there is no operation running. All CapSense scanning
is disabled during this mode. In this mode, the device wakes up
only using an external GPIO interrupt. A sleep timer interrupt
cannot wake up a device from deep sleep mode. This is treated
as a continuous sleep mode without periodic wakeups. Refer to
the application note “CapSense Express Power and Sleep
Considerations” - AN44209 for details on different sleep modes.
To get the lowest power during this mode the sleep timer
frequency should be set to 1 Hz.
■
Periodic Sleep Mode
■
Deep Sleep Mode
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Active Mode
Interrupt Pin to Master
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Setup Mode
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Active Mode
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In the Active mode, all the device blocks including the CapSense
subsystem are powered. Typical active current consumption of
the device across the operating voltage range is 1.5 mA.
Periodic Sleep Mode
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Sleep mode provides an intermediate power operation mode. It
is enabled by configuring the corresponding device registers
(0x7E, 0x7F). The device goes into sleep after there is no event
for stay awake counter (Reg 0x80) number of sleep intervals.
The device wakes up on sleep interval and scans the capacitive
sensors before going back to sleep again. If any sensor is active,
then the device wakes up. The device can also wake up from
Sleep mode with a GPIO interrupt. The sleep interval is
configured through registers. The following sleep intervals are
supported in CapSense Express:
1.95 ms (512 Hz)
■
15.6 ms (64 Hz)
■
125 ms (8 Hz)
■
1 s (1 Hz)
N
■
To inform the master of any button press a GPIO can be
configured as interrupt output and all CapSense buttons can be
connected to this GPIO with an OR logic operator. This can be
configured using the software tool.
LED Dimming
To change the brightness and intensity of the LEDs, the host
master (MCU, MPU, DSP, and so on) must send I2C commands
and program the PWM registers to enable output pins, set duty
cycle, and mode configuration. The single PWM source is
connected to all GPIO pins and has a common user defined duty
cycle. Each PWM enabled pin has two possible outputs: PWM
and 0/1 (depending on the configuration). Four different modes
of LED[15] dimming are possible, as shown in LED Dimming
Mode 1: Change Intensity on ON/OFF Button Status on page 11
to LED Dimming Mode 4: Toggle Intensity on ON/OFF or
OFF/ON Button Transitions on page 12. The operation mode and
duty cycle of the PWM enabled pins is common. This means that
one pin cannot behave as in Mode 1 and another pin as in Mode
2.
Notes
13. Errata: The worst case Acknowledgment time for all critical registers is 140 µs. For more information, see “Errata” on page 40.
14. Errata: The CY8C20110 device acknowledges to host within 100 µs, but is not accessible for any other operation until configuration is successfully stored into flash
memory and the device is ready to execute the next command. For more information, see “Errata” on page 40.
15. Errata: Applicable only for CY8C20110 device. For more information, see “Errata” on page 40.
Document Number: 001-54606 Rev. *M
Page 10 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
LED Dimming Mode 1: Change Intensity on ON/OFF Button Status
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LED Dimming Mode 2: Flash Intensity on ON Button Status
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Document Number: 001-54606 Rev. *M
Page 11 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
LED Dimming Mode 3: Hold Intensity After ON/OFF Button Transition
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LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON Button Transitions
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Note LED DIMMING is available only in CY8C20110.
Document Number: 001-54606 Rev. *M
Page 12 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Registers
Register Map
I2C Max ACK
Time in Setup
Mode (ms)[17]
–
–
–
–
–
–
11
11
11
11
–
–
11
11
–
–
11
11
11
11
11
11
11
11
–
–
–
–
11
11
11
11
11
11
11
11
11
11
11
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I2C Max ACK
Time in Normal
Mode (ms)[17]
0.1
0.1
0.1
0.1
0.1
0.1
–
–
–
–
0.11
0.11
–
–
0.11
0.11
–
–
–
–
–
–
–
–
0.1
0.1
0.1
0.1
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
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R
ot
N
R
R
R
R
W
W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Factory Default
Writable Only in Values
of Registers
SETUP Mode[16]
(in Hex)
–
00
–
00
–
00
–
00
–
00
–
00
YES
00
YES
00
YES
00
YES
00
–
00
–
00
YES
00
YES
00
–
03/1F [18]
–
03/1F [18]
YES
00
YES
00
YES
00
YES
00
YES
00
YES
00
YES
00
YES
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–]
00
–
00
–
00
–
00
–
00
–
00
de
Access
ec
INPUT_PORT0
INPUT_PORT1
STATUS_POR0
STATUS_POR1
OUTPUT_PORT0
OUTPUT_PORT1
CS_ENABL0
CS_ENABLE
GPIO_ENABLE0
GPIO_ENABLE1
INVERSION_MASK0
INVERSION_MASK1
INT_MASK0
INT_MASK1
STATUS_HOLD_MSK0
STATUS_HOLD_MSK1
DM_PULL_UP0
DM_STRONG0
DM_HIGHZ0
DM_OD_LOW0
DM_PULL_UP1
DM_STRONG1
DM_HIGHZ1
DM_OD_LOW1
PWM_ENABLE0[19]
PWM_ENABLE1[19]
PWM_MODE_DC[19]
PWM_DELAY[19]
OP_SEL_00
OPR1_PRT0_00
OPR1_PRT1_00
OPR2_PRT0_00
OPR2_PRT1_00
OP_SEL_01
OPR1_PRT0_01
OPR1_PRT1_01
OPR2_PRT0_01
OPR2_PRT1_01
OP_SEL_02
Register
Address
(in Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
om
Name
Notes
16. These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode.
17. The "I2C Max ACK Time" values mentioned in this table are for 3.3-V and 5-V operation; the timing values for 2.7-V operation are 4x the values provided in this table.
Refer to Operating Voltages on page 21.
18. The factory defaults of Reg 0x0E and 0x0F is 0x03 for 20142 device and 0x1F for 20140/60/80/10 devices.
19. Errata: These registers are available only in CY8C20110. For more information, see “Errata” on page 40.
Document Number: 001-54606 Rev. *M
Page 13 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Register Map (continued)
ec
R
N
Document Number: 001-54606 Rev. *M
I2C Max ACK
Time in Setup
Mode (ms)[17]
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
35
35
11
11
es
ig
ns
I2C Max ACK
Time in Normal
Mode (ms)[17]
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.11
0.11
–
–
0.11
0.11
D
ew
N
fo
r
d
m
en
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Factory Default
Writable Only in Values
of Registers
SETUP Mode[16]
(in Hex)
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
00
–
28
–
64
YES
A0
YES
00
–
0A
–
03
de
Access
ot
OPR1_PRT0_02
OPR1_PRT1_02
OPR2_PRT0_02
OPR2_PRT1_02
OP_SEL_03
OPR1_PRT0_03
OPR1_PRT1_03
OPR2_PRT0_03
OPR2_PRT1_03
OP_SEL_04
OPR1_PRT0_04
OPR1_PRT1_04
OPR2_PRT0_04
OPR2_PRT1_04
OP_SEL_10
OPR1_PRT0_10
OPR1_PRT1_10
OPR2_PRT0_10
OPR2_PRT1_10
OP_SEL_11
OPR1_PRT0_11
OPR1_PRT1_11
OPR2_PRT0_11
OPR2_PRT1_11
OP_SEL_12
OPR1_PRT0_12
OPR1_PRT1_12
OPR2_PRT0_12
OPR2_PRT1_12
OP_SEL_13
OPR1_PRT0_13
OPR1_PRT1_13
OPR2_PRT0_13
OPR2_PRT1_13
OP_SEL_14
OPR1_PRT0_14
OPR1_PRT1_14
OPR2_PRT0_14
OPR2_PRT1_14
CS_NOISE_TH
CS_BL_UPD_TH
CS_SETL_TIME
CS_OTH_SET
CS_HYSTERISIS
CS_DEBOUNCE
Register
Address
(in Hex)
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
om
Name
Page 14 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Register Map (continued)
om
I2C Max ACK
Time in Setup
Mode (ms)[17]
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
0.11
0.11
0.11
0.11
11
11
11
11
es
ig
ns
I2C Max ACK
Time in Normal
Mode (ms)[17]
0.11
0.11
0.11
–
–
–
–
–
–
–
–
–
–
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
D
ew
N
fo
r
d
m
en
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Factory Default
Writable Only in Values
of Registers
[16]
SETUP Mode
(in Hex)
–
14
–
14
–
20
YES
FF
YES
FF
YES
FF
YES
FF
YES
FF
YES
FF
YES
FF
YES
FF
YES
FF
YES
FF
–
64
–
64
–
64
–
64
–
64
–
64
–
64
–
64
–
64
–
64
–
0A
–
0A
–
0A
–
0A
–
0A
–
0A
–
0A
–
0A
–
0A
–
0A
de
Access
N
ot
R
CS_NEG_NOISE_TH
CS_LOW_BL_RST
CS_FILTERING[20,21]
CS_SCAN_POS_00
CS_SCAN_POS_01
CS_SCAN_POS_02
CS_SCAN_POS_03
CS_SCAN_POS_04
CS_SCAN_POS_10
CS_SCAN_POS_11
CS_SCAN_POS_12
CS_SCAN_POS_13
CS_SCAN_POS_14
CS_FINGER_TH_00
CS_FINGER_TH_01
CS_FINGER_TH_02
CS_FINGER_TH_03
CS_FINGER_TH_04
CS_FINGER_TH_10
CS_FINGER_TH_11
CS_FINGER_TH_12
CS_FINGER_TH_13
CS_FINGER_TH_14
CS_IDAC_00
CS_IDAC_01
CS_IDAC_02
CS_IDAC_03
CS_IDAC_04
CS_IDAC_10
CS_IDAC_11
CS_IDAC_12
CS_IDAC_13
CS_IDAC_14
Register
Address
(in Hex)
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75[22]
76[22]
77[22]
78[22]
79
7A
7B
7C
ec
Name
I2C_ADDR_LOCK
DEVICE_ID
DEVICE_STATUS
I2C_ADDR_DM
RW
R
R
RW
–
–
–
–
01
42/40/60/80/10[23]
03
00
Notes
20. Errata: Added two on-chip filtering algorithms for improved CapSense performance and better noise immunity.
21. Errata: If a finger is on the sensor, during power-up the sensor triggers and the baseline gets stuck. Baseline is stuck only when Averaging Filter is enabled. For more
information, see “Errata” on page 40.
22. The register 0x75–0x78, 0x7,D and 0x8A–0x8D are reserved.
23. The Device ID for different devices are tabulated in Device IDs on page 17.
Document Number: 001-54606 Rev. *M
Page 15 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Register Map (continued)
–
0.1
0.1
0.1
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
11
11
11
11
11
11
11
11
11
11
11
11
0.1
11
es
W
00
00
00
00
00
00
00
00
00
00
00
00
I2C Max ACK
Time in Setup
Mode (ms)[17]
D
YES
–
–
–
–
–
–
–
–
–
–
–
ew
RW
RW
RW
RW
R
R
R
R
R
R
R
R
I2C Max ACK
Time in Normal
Mode (ms)[17]
ig
ns
Factory Default
Writable Only in Values
of Registers
SETUP Mode[16]
(in Hex)
00
N
ot
R
ec
om
m
en
de
d
COMMAND_REG
Access
N
SLEEP_PIN
SLEEP_CTRL
SLEEP_SA_CNTR
CS_READ_BUTTON
CS_READ_BLM
CS_READ_BLL
CS_READ_DIFFM
CS_READ_DIFFL
CS_READ_RAWM
CS_READ_RAWL
CS_READ_STATUSM
CS_READ_STATUSL
Register
Address
(in Hex)
7D[25]
7E
7F
80
81
82
83
84
85
86
87
88
89
8A[25]
8B[25]
8C[25]
8D[25]
A0
fo
r
Name
Notes
24. These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode.
25. The register 0x75–0x78, 0x7D and 0x8A–0x8D are reserved.
Document Number: 001-54606 Rev. *M
Page 16 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Device IDs
Part Number
Device ID
42
CY8C20140
40
CY8C20160
60
CY8C20180
80
CY8C20110
10
ig
ns
CY8C20142
CapSense Express Commands
Command[26]
Description
Duration the Device is not accessible
after ACK (in ms)[27]
Setup/Normal
Store current configuration to NVM
Setup/Normal
W 00 A0 02
Restore factory configuration
Setup/Normal
W 00 A0 03
Write NVM POR defaults
Setup/Normal
W 00 A0 04
Read NVM POR defaults
Setup/Normal
5
W 00 A0 05
Read current configurations (RAM)
Setup/Normal
5
W 00 A0 06
Reconfigure device (POR)
Setup
5
Set normal mode of operation
Set setup mode of operation
W 00 A0 09
Start scan
W 00 A0 0A
Stop scan
W 00 A0 0B
Get CapSense scan status
N
120
fo
r
120
Setup/Normal
0
Setup/Normal
1.2*(loop time[29] + 1 ms)
Setup/Normal
10
Setup/Normal
5
Setup/Normal
0
om
m
en
W 00 A0 07
W 00 A0 08
120
d
W 00 A0 01
0
ew
Get firmware revision
[28]
de
W 00 A0 00
Executable Mode
D
es
Note All the Ack times specified are maximum values with all buttons enabled and filer enabled, with maximum order for 5-V and
3.3-V operation. The timing values for 2.7-V operation will be 4x these values.
Register Conventions
ec
This table lists the register conventions that are specific to this section.
RW
R
Description
Register has both read and write access
Register has only read access
N
ot
R
Convention
Notes
26. The ‘W’ indicates the write transfer. The next byte of data represents the 7-bit I2C address.
27. The "not accessible" timing values are the maximum values for 5-V and 3.3-V operation. The timing values for 2.7-V operation will be 4x the values provided in this
table. Refer to Operating Voltages on page 21.
28. Errata: Save to flash command fails when the sleep interval is set to 512 or 64 Hz. For more information, see “Errata” on page 40.
29. Loop time can be measured by probing any sensor using an oscilloscope and measuring the time between two consecutive scans.
Document Number: 001-54606 Rev. *M
Page 17 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Layout Guidelines and Best Practices
This section provides a set of high level rules for board design. Cypress also provides an extensive set of design guidelines for
CapSense board designs. Refer to the “Getting Started with CapSense Design Guide” for complete system guidelines.
CapSense Button Shapes
es
ig
ns
de
d
fo
r
N
ew
D
Button Layout Design
X: Button to ground clearance (Refer to Table 2 on page 18)
m
en
Y: Button to button clearance (Refer to Table 2 on page 18)
ec
om
Recommended via Hole Placement
R
Table 2. Recommended Layout Guidelines and Best Practices
2
ot
1
Category
Button shape
N
S. No.
Button size
Min
Max
Recommendations/Remarks
–
–
Solid round pattern, round with LED hole, rectangle with
round corners
5 mm
15 mm
Equal to button
ground clearance
–
0.5 mm
2 mm
10 mm
3
Button-button spacing
4
Button ground clearance
5
Ground flood-top layer
–
–
Hatched ground 7-mil trace and 45-mil grid (15% filling)
6
Ground flood-bottom layer
–
–
Hatched ground 7-mil trace and 70-mil grid (10% filling)
7
Trace length from sensor to
PSoC-buttons
–
200 mm
< 100 mm
8
Trace width
0.17 mm
0.20 mm
0.17 mm (7-mil)
Document Number: 001-54606 Rev. *M
8 mm [X]
Button ground clearance = Overlay thickness [Y]
Page 18 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Table 2. Recommended Layout Guidelines and Best Practices (continued)
S. No.
Category
Min
Max
Recommendations/Remarks
Trace routing
–
–
Traces should be routed on the non sensor side. If any
non CapSense trace crosses CapSense trace, ensure
that intersection is orthogonal.
10
Via position for the sensors
–
–
Via should be placed near the edge of the button/slider to
reduce trace length thereby increasing sensitivity.
11
Via hole size for sensor traces
–
–
10-mil
12
Number of vias on sensor trace
1
2
1
13
CapSense series resistor
placement
–
10 mm
Place CapSense series resistors close to PSoC for noise
suppression. CapSense resistors have highest priority
place them first.
14
Distance between any
CapSense trace to ground flood
10-mil
20-mil
20-mil
15
Device placement
–
–
Mount the device on the layer opposite to sensor. The
CapSense trace length between the device and sensors
should be minimum
16
Placement of components in
2-layer PCB
–
–
Top layer – sensor pads and
bottom layer – PSoC, other components, and traces.
–
18
Overlay material
–
19
Overlay adhesives
20
LED back lighting
21
Board thickness
–
es
D
ew
N
Should to be non conductive material. Glass, ABS plastic,
Formica
–
–
Adhesive should be non conductive and dielectrically
homogenous. 467MP and 468MP adhesives made by 3M
are recommended.
–
–
Cut a hole in the sensor pad and use rear mountable
LEDs. Refer the PCB layout below.
–
–
Standard board thickness for CapSense FR4 based
designs is 1.6 mm.
de
–
m
en
om
Top layer – sensor pads,
second layer – CapSense traces,
third layer – hatched ground,
bottom layer – PSoC, other components, and non
CapSense traces
fo
r
Placement of components in
4-layer PCB
d
17
ig
ns
9
ec
The recommended maximum overlay thickness is 5 mm (with external CSInt)/ 2 mm (without external CSInt). For more details refer
to the section “The Integrating Capacitor (Cint)” in AN53490.
N
ot
R
Note Some device packages does not have CSInt pin and external capacitor cannot be connected.
Document Number: 001-54606 Rev. *M
Page 19 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Example PCB Layout Design with Two CapSense Buttons and Two LEDs
de
d
fo
r
N
ew
D
es
ig
ns
Figure 10. Top Layer
N
ot
R
ec
om
m
en
Figure 11. Bottom Layer
Document Number: 001-54606 Rev. *M
Page 20 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
de
d
fo
r
N
ew
D
es
ig
ns
Operating Voltages
CapSense Constraints
Min
Typ
Max
Units
Notes
Parasitic capacitance (CP) of the CapSense sensor
–
–
30
pF
–
Supply voltage variation (VDD)
–
–
±5%
–
–
N
ot
R
ec
om
Parameter
m
en
For details on I2C 1x ACK time, refer to Register Map on page 13 and CapSense Express Commands on page 17. I2C 4x ACK time
is approximately four times the values mentioned in these tables.
Document Number: 001-54606 Rev. *M
Page 21 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Absolute Maximum Ratings
°C
–
125
See Package
label
°C
See
package
label
–
72
Hours
–
Ambient temperature with power
applied
–40
–
+85
°C
–
VDD
Supply voltage on VDD relative to
VSS
–0.5
–
VIO
DC input voltage
VSS – 0.5
–
VIOZ
DC voltage applied to tristate
VSS – 0.5
–
IMIO
Maximum current into any GPIO
pin
–25
ESD
Electro static discharge voltage
2000
LU
Latch-up current
Operating Temperature
Parameter
–
Description
Ambient temperature
TJ
Junction temperature
–
+6.0
V
–
VDD + 0.5
V
–
VDD + 0.5
V
–
–
–
+50
mA
–
–
V
–
200
mA
Human body model ESD
–
Min
Typ
Max
Unit
Notes
–40
–
+85
°C
–
–40
–
+100
°C
–
N
ot
R
ec
om
TA
ig
ns
TA
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C
(0 °C to 50 °C). Extended duration
storage temperatures above 65
°C degrade reliability
ew
Bake time
Notes
+100
N
tBAKETIME
Unit
25
fo
r
Bake temperature
Max
–55
d
TBAKETEMP
Typ
de
Storage temperature
m
en
TSTG
Min
es
Description
D
Parameter
Document Number: 001-54606 Rev. *M
Page 22 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Electrical Specifications
DC Electrical Specifications
DC Chip-Level Specifications
Table 3. DC Chip-Level Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
Supply voltage
2.40
–
5.25
V
IDD
Supply current
–
1.5
2.5
mA
Conditions are VDD = 3.10 V,
TA = 25 °C
–
ISB
Deep sleep mode current with
POR and LVD active
–
2.6
4
µA
VDD = 2.55 V, 0 °C < TA < 40 °C
ISB
Deep sleep mode current with
POR and LVD active
–
2.8
5
µA
ISB
Deep sleep mode current with
POR and LVD active
–
5.2
6.4
es
ig
ns
VDD
D
VDD = 3.3 V, –40 °C < TA < 85 °C
VDD = 5.25 V, –40 °C < TA < 85 °C
ew
µA
DC GPIO Specifications
Table 4. 5-V and 3.3-V DC GPIO Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
–
V
–
–
V
IOH = 1 mA, VDD > 3.10 V, maximum
of 20 mA source current in all I/Os.
High output voltage on Port 1 pins VDD – 0.2
–
–
V
IOH < 10 µA, VDD > 3.10 V, maximum
of 20 mA source current in all I/Os.
High output voltage on Port 1 pins VDD – 0.9
–
–
V
IOH = 5 mA, VDD > 3.10 V, maximum
of 20 mA source current in all I/Os.
d
–
IOH < 10 µA, VDD > 3.10 V, maximum
of 20 mA source current in all I/Os.
High output voltage on Port 0 pins VDD – 0.2
VOH2
High output voltage on Port 0 pins VDD – 0.9
VOH3
VOH4
om
m
en
de
VOH1
–
–
0.75
V
IOL = 20 mA/pin, VDD > 3.10,
maximum of 40/60 mA sink current
on even port pins and of 40/60 mA
sink current on odd port pins.[30]
High output current on Port 0 pins
0.01
–
1
mA
VDD  3.1 V, maximum of 20 mA
source current in all IOs
High output current on Port 1 pins
0.01
–
5
mA
VDD  3.1 V, maximum of 20 mA
source current in all IOs
VDD  3.1 V, maximum of 60 mA sink
current on pins P0_2, P1_2, P1_3,
P1_4 and 60 mA sink current on
pins P0_0, P0_1, P0_3, P0_4,
P1_0, P1_1
Low output voltage
IOH1
IOH2
N
ot
R
ec
VOL
IOL
fo
r
N
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design
guidance only.
Low output current
–
–
20
mA
VIL
Input low voltage
–
–
0.75
V
VDD = 3.10 V to 3.6 V.
VIH
Input high voltage
1.6
–
–
V
VDD = 3.10 V to 3.6 V.
VIL
Input low voltage
–
–
0.8
V
VDD = 4.75 V to 5.25 V.
VIH
Input high voltage
2.0
–
–
V
VDD = 4.75 V to 5.25 V.
Note
30. The maximum sink current is 40 mA for 20140 and 20142 devices and for all other devices the maximum sink current is 60 mA.
Document Number: 001-54606 Rev. *M
Page 23 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Table 4. 5-V and 3.3-V DC GPIO Specifications (continued)
Parameter
Typ
Max
Unit
Notes
Input hysteresis voltage
Description
–
140
–
mV
–
IIL
Input leakage
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25 °C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25 °C.
ig
ns
Min
VH
Table 5. 2.7-V DC GPIO Specifications
Min
Typ
Max
–
V
IOH <10 µA, maximum of 10 mA
source current in all I/Os.
–
V
IOH = 0.2 mA, maximum of 10 mA
source current in all I/Os.
V
IOH <10 µA, maximum of 10 mA
source current in all I/Os.
–
V
IOH = 2 mA, maximum of 10 mA
source current in all I/Os.
–
0.75
V
IOL = 10 mA/pin, VDD > 3.10,
maximum of 20/30 mA sink current
on even port pins and of 20/30 mA
sink current on odd port pins. [31]
–
2
mA
VDD < 2.9 V, maximum of 10 mA
source current in all I/Os
mA
VDD < 2.9 V, maximum of 30 mA sink
current on pins P0_2, P1_2, P1_3,
P1_4 and 30 mA sink current on
pins P0_0, P0_1, P0_3, P0_4,
P1_0, P1_1
VDD < 2.9 V, maximum of 50 mA sink
current on pins P0_2, P1_2, P1_3,
P1_4 and 50 mA sink current on
pins P0_0, P0_1, P0_3, P0_4,
P1_0, P1_1
High output voltage on Port 0 pins VDD – 0.2
–
VOH2
High output voltage on Port 0 pins VDD – 0.5
–
VOH3
High output voltage on Port 1 pins VDD – 0.2
–
VOH4
High output voltage on Port 1 pins VDD – 0.5
VOL1
Low output voltage
IOH
High output current
d
de
m
en
0.01
–
–
–
10
om
Low output current on Port 0 pins
ec
IOL1
–
–
fo
r
VOH1
Unit
ew
Description
N
Parameter
D
es
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 2.90 V and
–40 °C < TA < 85 °C, respectively. Typical parameters apply to 2.7 V at 25 °C and are for design guidance only.
IOL2
Low output current
VIL
–
20
mA
Input low voltage
–
–
0.75
V
Input high voltage
1.4
–
–
V
VDD = 2.4 to 2.7 V.
VDD = 2.7 to 2.90 V and 3.10 V to
3.6 V.
VIH2
ot
R
–
N
VIH1
Notes
Input high voltage
1.6
–
–
V
VDD = 2.4 to 2.90 V and 3.10 V to
3.6 V.
VH
Input hysteresis voltage
–
60
–
mV
IIL
Input leakage
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25 °C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25 °C
Note
31. The maximum sink current per port is 20 mA for 20140 and 20142 devices and for all other devices the maximum sink current is 30 mA.
Document Number: 001-54606 Rev. *M
Page 24 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
DC POR and LVD Specifications
Table 6. DC POR and LVD Specifications
VPPOR0
VPPOR1
VLVD0
VLVD2
VLVD6
Description
VDD value for PPOR trip
VDD = 2.7 V
VDD = 3.3 V, 5 V
VDD value for LVD trip
VDD = 2.7 V
VDD = 3.3 V
VDD = 5 V
Min
Typ
Max
Unit
–
–
2.36
2.60
2.40
2.65
V
V
2.39
2.75
3.98
2.45
2.92
4.05
2.51
2.99
4.12
V
V
V
DC Flash Write Specifications
Notes
VDD must be greater than or equal
to 2.5 V during startup or internal
reset.
–
ig
ns
Parameter
IDDP
Supply current for flash write
operations
FlashENPB
FlashDR
Flash endurance
Flash data retention
Min
Typ
2.7
–
–
–
5
25
–
–
–
–
d
50,000[32]
10
Max
fo
r
VDDIWRITE
Description
Supply voltage for flash write
operations
Units
Notes
V
–
mA
–
– Erase/write cycles
Years
–
de
Symbol
N
Table 7. DC Flash Write Specifications
ew
D
es
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C or 2.4 V to 2.90 V and –40 °C < TA < 85 °C, respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash Endurance and Retention specifications
are valid only within the range: 25 °C ± 20 °C during the flash write operation. It is at the user’s own risk to operate out of this
temperature range. If flash writing is done out of this temperature range, the endurance and data retention reduces.
DC I2C Specifications
om
Table 8. DC I2C Specifications
m
en
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design
guidance only.
Symbol[33]
Min
Typ
Max
Units
–
–
0.3 × VDD
V
–
–
–
0.25 × VDD
–
0.4
V
V
V
1.7
5
pF
4
5.6
8
k
Input low level
VIHI2C
VOLP
Input high level
Low output voltage
–
0.7 × VDD
–
CI2C
Capacitive load on I2C pins
0.5
ot
Pull-up resistor
N
RPU
R
VILI2C
ec
Description
Notes
2.4 V VDD  2.9 V
3.1 V VDD  3.6 V
4.75 V  VDD  5.25 V
2.4 V  VDD  5.25 V
IOL = 5 mA/pin
Package and pin dependent.
Temp = 25 °C
–
Notes
32. Commands involving flash writes (0x01, 0x02, 0x03) and flash read (0x04) must be executed only within the same VCC voltage range detected at POR (power on, or
command 0x06) and above 2.7 V.
33. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
Document Number: 001-54606 Rev. *M
Page 25 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
CapSense Electrical Characteristics
Min (V)
3.6
3.3
3.1
Conditions for
Supply Voltage
Result
< 2.9
The device automatically reconfigures itself to work in 2.7 V mode
of operation.
> 2.9 or < 3.10
This range is not recommended for CapSense usage.
The scanning for CapSense parameters shuts down until the
voltage returns to over 2.45 V.
< 2.45 V
2.7
5.25
2.45
5.0
The device automatically reconfigures itself to work in 3.3 V mode
of operation.
> 3.10
4.75
< 2.4 V
The device goes into reset.
< 4.73 V
The scanning for CapSense parameters shuts down until the
voltage returns to over 4.73 V.
D
2.90
AC Chip-Level Specifications
Table 9. 5-V and 3.3-V AC Chip-Level Specifications
Min
15
tXRST
External reset pulse width
10
tPOWERUP
Time from end of POR to CPU
executing code
–
SRPOWER_UP
Power supply slew rate
Max
Notes
Calculations during sleep operations
kHz
are done based on ILO frequency.
64
–
–
µs
–
150
–
ms
–
–
250
V/ms
–
de
m
en
–
Units
32
d
F32K1
Typ
fo
r
Description
Internal low-speed oscillator
(ILO) frequency
N
ew
AC Electrical Specifications
Parameter
ig
ns
Typ (V)
es
Max (V)
Table 10. 2.7-V AC Chip-Level Specifications
Description
om
Parameter
F32K1
ILO frequency
tXRST
Min
Typ
Max
Units
Notes
Calculations during sleep
kHz operations are done based on ILO
frequency.
32
96
External reset pulse width
10
–
–
µs
–
tPOWERUP
Time from end of POR to CPU
executing code
–
600
–
ms
–
SRPOWER_UP
Power supply slew rate
–
–
250
V/ms
–
N
ot
R
ec
8
Document Number: 001-54606 Rev. *M
Page 26 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
AC GPIO Specifications
Table 11. 5-V and 3.3-V AC GPIO Specifications
Parameter
Description
Min
Max
Unit
Notes
Rise time, strong mode,
Cload = 50 pF, Port 0
15
80
ns
VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10%
to 90%
tRise1
Rise time, strong mode,
Cload = 50 pF, Port 1
15
50
ns
VDD = 3.10 V to 3.6 V, 10% to 90%
tFall
Fall time, strong mode,
Cload = 50 pF, all ports
10
50
ns
VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10%
to 90%
Min
Max
Unit
es
ig
ns
tRise0
Description
tRise0
Rise time, strong mode,
Cload = 50 pF, Port 0
15
100
ns
tRise1
Rise time, strong mode,
Cload = 50 pF, Port 1
15
70
tFall
Fall time, strong mode,
Cload = 50 pF
ew
Parameter
D
Table 12. 2.7-V AC GPIO Specifications
10
70
VDD = 2.4 V to 2.90 V, 10% to 90%
VDD = 2.4 V to 2.90 V, 10% to 90%
N
ns
ns
VDD = 2.4 V to 2.90 V, 10% to 90%
fo
r
AC I2C Specifications
Table 13. AC I2C Specifications
Standard Mode
d
Description
SCL clock frequency
tHDSTAI2C
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated
Units
Notes
Max
Min
Max
0
100
0
400
4.0
–
0.6
–
µs
–
m
en
FSCLI2C
Fast Mode
Min
de
Parameter
Notes
Fast mode not
kbps supported for
VDD < 3.0 V.
LOW period of the SCL clock
4.7
–
1.3
–
µs
–
tHIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
µs
–
tSUSTAI2C
Setup time for a repeated START
condition
4.7
–
0.6
–
µs
–
tHDDATI2C
Data hold time
0
–
0
–
µs
–
tSUDATI2C
tSUSTOI2C
Data setup time
250
–
100
–
ns
–
Setup time for STOP condition
4.0
–
0.6
–
µs
–
BUS free time between a STOP
and START condition
4.7
–
1.3
–
µs
–
Pulse width of spikes suppressed
by the input filter
–
–
0
50
ns
–
ec
R
ot
N
tBUFI2C
om
tLOWI2C
tSPI2C
Document Number: 001-54606 Rev. *M
Page 27 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Figure 12. Definition of Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C
TSPI2C
THDSTAI2C
TBUFI2C
ig
ns
THDDATI2CTSUSTAI2C
I2C_SCL
TSUSTOI2C
es
THIGHI2C TLOWI2C
Sr
P
S
D
S
Repeated START Condition
STOP Condition
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
START Condition
Document Number: 001-54606 Rev. *M
Page 28 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Appendix
Examples of Frequently Used I2C Commands
S. No.
Requirement
I2C commands[34]
Comment
Enter into setup mode
W 00 A0 08
–
2
Enter into normal mode
W 00 A0 07
–
3
Load factory defaults to RAM
registers
W 00 A0 02
–
4
Do a software reset
W 00 A0 08
W 00 A0 06
5
Save current configuration to
flash[35]
W 00 A0 01
6
Load factory defaults to RAM
registers and save as user
configuration
W 00 A0 08
W 00 A0 02
W 00 A0 01
W 00 A0 06
Enter into setup mode
Load factory defaults to SRAM
Save the configuration to flash. Wait for time specified in
CapSense Express Commands on page 17.
Do software reset
7
Enable GP00 as CapSense
button
W 00 A0 08
W 00 06 01
W 00 A0 01
W 00 A0 06
Enter into setup mode
Configuring CapSense buttons
Save the configuration to flash. Wait for time specified in
CapSense Express Commands on page 17.
Do software reset
8
Read CapSense button(GP00)
scan results
W 00 81 01
W 00 82
R 00 RD. RD. RD.
9
Read CapSense button status
register
W 00 88
R 00 RD
ig
ns
1
fo
r
N
ew
D
es
Enter into setup mode
Do software reset
Set the read pointer to 88
Reading a byte gets status CapSense inputs
N
ot
R
ec
om
m
en
de
d
Select CapSense button for reading scan result
Set the read point to 82h
Consecutive 6 reads get baseline, difference count and raw
count (all two byte each)
Notes
34. The ‘W’ indicates the write transfer and the next byte of data represents the 7-bit I2C address. The I2C address is assumed to be ‘0’ in the above examples. Similarly
‘R’ indicates the read transfer followed by 7-bit address and data byte read operations.
35. Errata: Save to flash command fails when the sleep interval is set to 512 or 64 Hz. For more information, see “Errata” on page 40.
Document Number: 001-54606 Rev. *M
Page 29 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Ordering Information
CapSense
Block
GPIOs
XRES Pin
001-09116 16-pin QFN[36]
Industrial
Yes
10
Yes
CY8C20110-SX2I
51-85068
Industrial
Yes
10
Yes
CY8C20180-LDX2I
001-09116 16-pin QFN[36]
Industrial
Yes
08
Yes
CY8C20180-SX2I
51-85068
Industrial
Yes
08
Yes
CY8C20160-LDX2I
001-09116 16-pin QFN[36]
Industrial
Yes
06
Yes
CY8C20160-SX2I
51-85068
Industrial
Yes
06
Yes
CY8C20140-LDX2I
001-09116 16-pin QFN[36]
Industrial
Yes
04
Yes
Yes
04
Yes
04
No
CY8C20110-LDX2I
Package Type
16-pin SOIC
16-pin SOIC
16-pin SOIC
CY8C20140-SX2I
51-85068
16-pin SOIC
Industrial
CY8C20142-SX1I
51-85066
8-pin SOIC
Industrial
es
Package
Diagram
Ordering Code
ig
ns
Operating
Temperature
D
Table 14. Key Features and Ordering Information
Yes
ew
Note For die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
CY
8
C
201
XX - XX
X
X
N
Ordering Code Definitions
I
fo
r
Temperature Range:
I = Industrial
d
X = 2 or 1
2 = 16-pin device; 1 = 8-pin device
de
Pb-free
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Controllers
Company ID: CY = Cypress
N
ot
R
ec
om
m
en
Package Type: XX = LD or S
LD = 16-pin QFN; S = 16-pin SOIC
Note
36. Earlier termed as COL.
Document Number: 001-54606 Rev. *M
Page 30 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Thermal Impedances
Table 15. Thermal Impedances by Package
Typical JA[37]
Package
16-pin QFN[1]
46 °C/W
79.96 °C/W
8-pin SOIC
127.22 °C/W
ig
ns
16-pin SOIC
Solder Reflow Specifications
Table 16. Solder Reflow Specifications
Maximum Time above TC – 5 °C
260 C
30 seconds
16-pin SOIC
260 C
8-pin SOIC
260 C
D
30 seconds
30 seconds
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
Package
es
Maximum Peak Temperature (TC)
16-pin QFN[1]
Note
37. TJ = TA + Power × JA.
Document Number: 001-54606 Rev. *M
Page 31 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Package Diagrams
fo
r
N
ew
D
es
ig
ns
Figure 13. 16-pin Chip On Lead (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Outline, 001-09116
001-09116 *J
N
ot
R
ec
om
m
en
de
d
Figure 14. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *E
Document Number: 001-54606 Rev. *M
Page 32 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Package Diagrams (continued)
51-85066 *H
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Figure 15. 8-pin SOIC (150 Mils) S08.15/SZ08.15 Package Outline, 51-85066
Document Number: 001-54606 Rev. *M
Page 33 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Acronyms
Table 17 lists the acronyms that are used in this document.
Table 17. Acronyms Used in this Datasheet
Acronym
Description
Acronym
Description
LVD
low voltage detect
CMOS
complementary metal oxide semiconductor
MCU
microcontroller unit
DC
direct current
PCB
printed circuit board
EEPROM
electrically erasable programmable read-only
memory
POR
power on reset
EMC
electromagnetic compatibility
PPOR
precision power on reset
GPIO
general-purpose I/O
PSoC®
Programmable System-on-Chip
I/O
input/output
PWM
pulse width modulator
IDAC
current DAC
QFN
quad flat no leads
ILO
internal low speed oscillator
RF
LCD
liquid crystal display
SOIC
SRAM
light-emitting diode
XRES
LSB
least-significant bit
es
D
ew
low dropout regulator
LED
radio frequency
small-outline integrated circuit
static random access memory
external reset
fo
r
LDO
ig
ns
alternating current
N
AC
Reference Documents
d
Capsense® Express™ Power And Sleep Considerations - AN44209 (001-44209)
de
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Units of Measure
Table 18 lists the units of measures.
Symbol
om
Table 18. Units of Measure
m
en
Document Conventions
Unit of Measure
degree Celsius
Hz
hertz
ec
C
Symbol
Unit of Measure
mm
millimeter
ms
millisecond
kilo bits per second
mV
millivolt
kHz
kilohertz
nA
nanoampere
k
kilohm
ns
nanosecond
%
percent
least significant bit
microampere
pF
picofarad
microfarad
V
volt
µs
microsecond
W
watt
mA
milliampere
µF
N
µA
ot
LSB
R
kbps
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Document Number: 001-54606 Rev. *M
Page 34 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Glossary
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that
create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
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active high
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
N
ot
bus
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
Document Number: 001-54606 Rev. *M
Page 35 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Glossary (continued)
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
ig
ns
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
converter performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
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The number of cycles or events per unit of time, for a periodic function.
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frequency
gain
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data bus
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high
with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
Document Number: 001-54606 Rev. *M
Page 36 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Glossary (continued)
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage
detect (LVD)
A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
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interrupt
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
N
ot
Phase-locked
loop (PLL)
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
Document Number: 001-54606 Rev. *M
Page 37 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Glossary (continued)
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
N
tri-state
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
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synchronous
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RAM
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
Document Number: 001-54606 Rev. *M
Page 38 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Glossary (continued)
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
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VDD
Document Number: 001-54606 Rev. *M
Page 39 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Errata
CY8C20110
This section discusses the changes between the firmware revisions ×15 and ×1B in CY8C20110 devices. All shipments of samples
and production parts with firmware version ×1B will encounter the following changes from the previous (×15) version of the firmware.
Cypress inventory has been rotated to the ×1B firmware by WW35, and all distributor inventory will be rotated by WW42 of 2008.
Contact your local Cypress Sales Representative if you have questions.
Part Number
Package Type
CY8C20110
All packages
ig
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Part Numbers Affected
Operating Range
es
Commercial / Industrial
Product Status
D
The CY8C20110 CapSense Express device has been qualified and is available in production quantities. From now on, customers are
requested to use production release of CY8C20110 with x1B firmware version.
Table 19 defines the errata applicable to CY8C20110 device.
Description
Reduction of I2C ACK timing response by the
CapSense Express slave.
Time in Normal Operating Mode.
I2C ACK
Reduction of I2C ACK timing response by the
CapSense Express slave.
Time when executing commands to store
configuration in Flash.
I2C ACK
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Issues/Changes
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Item
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Table 19. CapSense Express CY8C20110 Errata Summary
ew
CapSense Express CY8C20110 Errata Summary
Fix Status
Worst case Ack timing of 140 µs for all critical
registers (Input, Output, CapSense Global
Parameters, CapSense Buttons/Slider
Read-back Values). For more information on
critical registers I2C timings, refer to application
note AN44208 “CapSense Express - I2C
Communication Timing Analysis”.
The CY8C20110 device ACK to host within
100 µs, but is not accessible for any other
operation until configuration is successfully stored
into flash memory and the device is ready to
execute the next command. For more information
on I2C timings, refer to application note AN44208
“CapSense Express - I2C Communication Timing
Analysis”.
Data Filtering
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ot
3
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Averaging Filter
This smoothens the raw count data, and results in
better noise immunity and performance. The filter
can average 2, 4, 8, or 16 samples.
Addition of two on-chip filtering algorithms for im- Drop the Sample Filter
proved CapSense performance and better noise This discards any acquired CapSense sample if
immunity.
an I2C communication occurs after the scan
process has already started.
For more information on filtering, refer to
application note AN48430 “CapSense Express
-Noise Filtering Methods”.
4
PWM Control
Four configuration registers (18h, 19h, 1Ah, 1Bh)
are added to set PWM duty cycles and modes.
This set of registers provides options that support
15 duty cycles on PWM output and 4 modes of
The PWM output functionality has been added on PWM operations, which are defined as Normal,
GPIOs to support LED brightness control.
Single Pulse, Delayed Transition, and Toggle
Flip-Flop. For more information on duty cycles and
PWM mode settings, refer to application note
AN47716 “Configuring PWM for LED Intensity
Control”.
Document Number: 001-54606 Rev. *M
Page 40 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Table 19. CapSense Express CY8C20110 Errata Summary (continued)
Item
Issues/Changes
Description
Fix Status
No fix will be provided. When using save to flash
follow these steps:
1. Write configuration data to registers with sleep
interval set to 8 or 1 Hz
2. Save the settings to flash
3. Change the sleep interval settings per design
Save to flash command fails when the sleep
interval is set to 512 or 64 Hz.
Save to Flash
6
If a finger is on the sensor during power-up the
fix will be provided. Disable the Averaging
False Triggering During sensor triggers and the baseline gets stuck. This No
Filter
if your design requires a finger on the sensor
Power-Up
only happens when the Averaging Filter is
during power-up.
enabled.
7
Erroneous I2C
START condition
detection
D
No fix will be provided. Do not initiate I2C
transactions on bus before the device boots up.
ew
During boot-up, CapSense Express device
misinterprets an incoming byte as its own
address, leading to confusion in the I2C state
machine. It controls the SCL and SDA line
in-between the I2C transfer, leading to bus
communication failure.
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5
N
CY8C20140/142/160/180/1A0
fo
r
This section describes the changes between the firmware revisions ×15 and ×1B in CapSense Express devices
(CY8C20140/142/160/180/1A0). All shipments of samples and production parts with firmware version ×1B will encounter the following
changes from the previous (×15) version of the firmware. Cypress inventory has been rotated to the ×1B firmware by WW35, and all
distributor inventory will be rotated by WW42 of 2008.
d
Contact your local Cypress Sales Representative if you have questions.
de
Part Numbers Affected
Part Number
CY8C20142
CY8C20160
All packages
Commercial/Industrial
All packages
Commercial/Industrial
All packages
Commercial/Industrial
All packages
Commercial/Industrial
All packages
Commercial/Industrial
ec
Product Status
om
CY8C20180
CY8C201A0
Operating Range
m
en
CY8C20140
Package Type
N
ot
R
The CY8C20140/142/160/180/1A0 CapSense Express devices have been qualified and are available in production quantities. From
now on, customers are requested to use the production release of CapSense Express device with x1B firmware version.
Document Number: 001-54606 Rev. *M
Page 41 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
CapSense Express CY8C20140/142/160/180/1A0 Errata Summary
Table 20 defines the errata applicable to Cypress CapSense Express devices.
Table 20. CapSense Express CY8C20140/142/160/180/1A0 Errata Summary
Item
Issues
Description
Fix Status
Worst case Ack timing of 140 µs for all critical
registers (Input, Output, CapSense Global
Parameters, and CapSense Buttons and
Slider Read-back Values). For more
information on critical register I2C timings,
refer to application note AN44208
“CapSense Express - I2C Communication
Timing Analysis”.
Reduction of I2C ACK timing response by the
CapSense Express slave.
(Time in Normal Operating Mode)
I2C ACK
The CapSense Express device ACK to host
within 100 µs but is not accessible for any
other operation until the configuration is
Reduction of I2C ACK timing response by the
successfully stored into flash memory, and
CapSense Express slave.
the CapSense Express device is ready to
(Time when executing commands to store configuration execute the next command. For more
information on I2C timings to store
in Flash)
configuration in Flash, refer to application
note AN44208 “CapSense Express - I2C
Communication Timing Analysis”.
Data Filtering
Averaging Filter
This smoothens the raw count data, and
results in better noise immunity and
performance. The filter can average 2, 4, 8,
or 16 samples.
Addition of two on-chip filtering algorithms for improved Drop the Sample Filter
CapSense performance and better noise immunity.
This discards any acquired CapSense
sample if an I2C communication occurs after
the scan process has already started.
For more information on filtering, refer to
application note AN48430 “CapSense
Express-Noise Filtering Methods”.
4
Save to Flash
No fix will be provided. When using save to
flash follow these steps:
1. Write configuration data to registers with
Save to flash command fails when the sleep interval is
sleep interval set to 8 or 1 Hz
set to 512 or 64 Hz.
2. Save the settings to flash
3. Change the sleep interval settings per
design
5
False Triggering
During Power-Up
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I2C ACK
1
6
Erroneous I2C
START condition
detection
If a finger is on the sensor during power-up the sensor No fix will be provided. Disable the Averaging
triggers and the baseline gets stuck. This only happens Filter if your design requires a finger on the
when the Averaging Filter is enabled.
sensor during power-up.
During boot-up, CapSense Express device
misinterprets an incoming byte as its own address,
No fix will be provided. Do not initiate I2C
leading to confusion in the I2C state machine. It controls transactions on bus before the device boots
the SCL and SDA line in-between the I2C transfer,
up.
leading to bus communication failure.
Document Number: 001-54606 Rev. *M
Page 42 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Document History Page
Document Title: CY8C20110/CY8C20180/CY8C20160/CY8C20140/CY8C20142, CapSense® Express™ Button Capacitive
Controllers
Document Number: 001-54606
Rev.
ECN
Orig. of
Change
Submission
Date
**
2741726
SLAN /
FSU
07/21/2009
New data sheet.
12/4/2009
Added Contents.
Updated Absolute Maximum Ratings (Added F32k u, tPOWERUP parameters
and their details).
Updated Electrical Specifications (Updated DC Electrical Specifications
(Updated DC Flash Write Specifications (Updated Note 32))).
03/15/2010
Updated Pin Definitions (Added a Note “For information on the preferred
dimensions for mounting QFN packages, see the "Application Notes for
Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages"
available at http://www.amkor.com.” below the column).
Updated Absolute Maximum Ratings (Added TBAKETEMP and TBAKETIME
parameters and their details).
Updated Package Diagrams (Updated Figure 1 (Changed 16-pin COL to
16-pin QFN).
07/29/2010
Updated Features (Changed the part number from CY8C21110 to
CY8C20110).
Added Acronyms and Units of Measure.
Minor edits across the document.
SSHH /
FSU
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ns
2821828
NJF
ew
2892629
3002214
SLAN
Updated Pin Definitions (Added Note 3 and referred the same Note in all
GP1[1] and GP1[2] pins).
Updated Pin Definitions (Added Note 6 and referred the same Note in all
GP1[1] and GP1[2] pins).
Updated Pin Definitions (Added Note 7 and referred the same Note in all
GP1[1] and GP1[2] pins).
Updated Absolute Maximum Ratings (Removed F32k u, tPOWERUP parameters
and their details).
Updated Electrical Specifications (Updated AC Electrical Specifications
(Added AC Chip-Level Specifications section)).
Updated Typical Circuits (Updated Figure 4 (Replaced with updated one)).
Updated in new template.
3042142
ARVM
09/30/2010
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*D
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*B
D
es
*A
Description of Change
06/07/2011
Updated Layout Guidelines and Best Practices (Updated Table 2 (Removed
“Overlay thickness-buttons” category),
added the following statement after Table 2 –
“The Recommended maximum overlay thickness is 5 mm (with external CSInt)/
2 mm (without external CSInt). For more details refer to the section “The
Integrating Capacitor (Cint)” in AN53490.
Note Some device packages does not have CSInt pin and external capacitor
cannot be connected.”).
Updated CapSense Constraints (Removed the parameter “Overlay
thickness”).
Updated Solder Reflow Specifications (Updated Table 16).
3085081
NJF
N
ot
*E
R
ec
11/12/2010
Updated Electrical Specifications (Updated DC Electrical Specifications
(Updated DC GPIO Specifications (Removed sub-section “2.7-V DC Spec for
I2C Line with 1.8 V External Pull-up”), added DC I2C Specifications)), updated
AC Electrical Specifications (Updated AC I2C Specifications (Updated
Figure 12 (No specific changed were made to I2C Timing Diagram. Updated
for clearer understanding.)))).
Updated Solder Reflow Specifications (Updated Table 16).
Added Reference Documents and Glossary.
Updated in new template.
*F
3276234
ARVM
Document Number: 001-54606 Rev. *M
Page 43 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Document History Page (continued)
Document Title: CY8C20110/CY8C20180/CY8C20160/CY8C20140/CY8C20142, CapSense® Express™ Button Capacitive
Controllers
Document Number: 001-54606
*H
3837914
VAIR /
SLAN
SLAN
Description of Change
05/31/2012
Updated Pin Definitions (Updated description of XRES pin).
Updated Pin Definitions (Updated description of XRES pin).
Updated Typical Circuits (Updated Figure 6 (Added Note 9 and referred the
same Note in Figure 6)).
Updated Package Diagrams (spec 001-09116 (Changed revision from *E to
*F), spec 51-85068 (Changed revision from *C to *D)).
Updated in new template.
12/11/2012
Updated Device Operation Modes (Updated Periodic Sleep Mode (Updated
description)).
Updated Package Diagrams (spec 001-09116 (Changed revision from *F to
*G), spec 51-85068 (Changed revision from *D to *E)).
ig
ns
3631370
Submission
Date
es
*G
Orig. of
Change
ECN
D
Rev.
3992042
SLAN
05/06/2013
*J
4033835
DCHE
06/19/2013
Added Errata Footnotes.
Updated in new template.
*K
4489897
PRIA
09/01/2014
Updated duration for which the device is not accessible after ACK timing for
the "Set Setup mode of operation" command."
Added notes 17, 27, and 29.
08/25/2015
Updated I2C Clock Stretching.
Updated hyperlinks in the document.
Added reference to Getting Started with CapSense Design Guide in Layout
Guidelines and Best Practices.
Updated Errata: Added Errata item 7 in Table 19 and Errata item 6 in Table 20.
Updated Figure 15 in Package Diagrams (spec 51-85066 *F to 51-85066 *G).
PRIA
*M
5277446
PRIA
m
en
4873309
05/19/2016
Added “Not recommended for new designs” watermark.
Updated the template.
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*I
Updated Package Diagrams:
spec 001-09116 – Changed revision from *G to *H.
spec 51-85066 – Changed revision from *E to *F.
Added Errata.
Added CY8C20140/142/160/180/1A0.
Document Number: 001-54606 Rev. *M
Page 44 of 45
CY8C20110, CY8C20180, CY8C20160
CY8C20140, CY8C20142
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Touch Sensing
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PSoC
cypress.com/touch
cypress.com/usb
cypress.com/wireless
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Wireless/RF
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USB Controllers
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Interface
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ARM® Cortex® Microcontrollers
N
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© Cypress Semiconductor Corporation, 2009-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 001-54606 Rev. *M
Revised May 19, 2016
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