SAR ADC in PSoC® 3
AN60832
Author: Anup Mohan
Associated Project: Yes
Associated Part Family: CY8C38xxx
Software Version: PSoC Creator Beta 4.0
Associated Application Notes: None
Application Note Abstract
The application note explains how to implement Successive Approximation Register (SAR) ADC in PSoC® 3 using a
DAC, comparator, and digital logic. It also describes how to extend this logic and implement three simultaneously
sampling SAR ADCs. A triple SAR ADC component and an example project that illustrates its use are provided along
with the application note.
The application note explains the implementation of a
single SAR ADC and how to use that idea to
implement three simultaneously sampling SAR ADCs.
Introduction
The SAR ADC is one of the preferred ADCs for use in
various applications. There is no built in SAR ADC
available in PSoC 3. The highly programmable analog
SAR ADC Implementation
and digital resources available in PSoC 3 enable to
construct a SAR ADC in PSoC 3. An 8 bit SAR ADC
The block diagram of an 8-bit SAR ADC is shown in
can be constructed using a DAC, comparator, and the
the following figure.
SAR logic implemented using the powerful Universal
Digital Blocks (UDB). The PSoC is so flexible that you
can extend the idea of a single SAR ADC and
construct three SAR ADCs with simultaneous
sampling capability.
Figure 1. SAR ADC Block Diagram
ANALOG
INPUT
VOLTAGE
TRACK & HOLD
SAR
COMPARATOR
bit7
bit0
DATA OUT
8
VDAC
The SAR ADC consists of four parts:
Track and Hold: This circuit is used to hold the
input constant during the period of conversion. At
the end of conversion it samples in a new analog
input value.
Comparator: This compares the analog input
voltage with the DAC output voltage.
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Successive
Approximation
Register:
Depending on the comparator output, this
register feeds the DAC input with appropriate
digital count. At the end of conversion, the SAR
holds the 8-bit converted result.
DAC: The voltage DAC is used to convert the
SAR output to an analog voltage which is used to
compare against the analog input voltage.
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In PSoC 3 the DAC has a resolution of 8 bits. Hence the SAR ADC also has 8-bit resolution. The PSoC® Creator™
schematic to implement an 8 bit SAR ADC is shown in Figure 2. Note that the Track and Hold component is not
implemented in the schematic.
Figure 2. PSoC Creator Schematic
Comparator
VDAC
As mentioned earlier, the comparator is used to
compare the analog input voltage with the DAC output
voltage. The SAR uses the comparator output to
decide whether to increase or decrease the current
register value. The configuration settings of
comparator are shown in Figure 3.
The voltage DAC in PSoC 3 generates voltage
according to the digital data present in the SAR. The
VDAC has the option to take the input data through
DAC bus. Thus you can directly transfer data from
SAR to VDAC avoiding CPU involvement. The
configuration settings for VDAC are shown in the
following figure.
Figure 3. Comparator Configuration
Figure 4. VDAC Configuration
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When the data is available on the DAC bus, a strobe
signal must be given to the VDAC so that a
corresponding analog signal is generated. The strobe
signal is generated from the SAR logic. For more
details regarding DAC bus refer the DAC section in
the PSoC 3 and PSoC 5 Technical Reference
Manual.
The different signals used in the SAR component are
as follows:
The input range of the SAR ADC is determined by the
range selected for VDAC. The SAR ADC in this case
is designed to accept input voltages in the range of 0
to 1.024V.
SOC: A high at this pin indicates that delay for
DAC settling is complete and the ADC will restart.
The output of the lookup table delay counter is
connected here. This should not be confused
with the general Start of Conversion signal for
ADCs.
SAR Logic
Successive Approximation Register logic is the heart
of the SAR ADC. As explained earlier, the SAR logic
sets or resets a corresponding bit depending on the
comparator output and sets the next bit. This is
repeated eight times and in the end SAR generates
an end of conversion signal and latches out the
converted data. The SAR logic is implemented
completely in UDB.
The symbol of the SAR component implemented in
UDB is shown in the following figure.
Figure 5. SAR_Logic Symbol
CMP_IN: Input pin where the comparator output
is connected.
CLOCK: The clock for operating entire SAR logic.
ENABLE: Active high enable signal for the SAR
logic.
STROBE: The signal used to strobe the DAC on
a rising edge is provided from this terminal.
PDATA [7:0]: 8-bit parallel data output.
EOC: This is the end of conversion signal. It is
used to latch the output of SAR to a status
register.
TRIGGER: The trigger for the lookup table delay
counter. The delay counter can count only when
the TRIGGER pin is high.
The SAR logic is implemented using the datapath of
the UDB. Verilog coding technique is used here. The
structure of the datapath is as follows.
Figure 6. Datapath Top Level
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The different states in the SAR logic are implemented
using the Control Store RAM. This project uses the
Accumulators (A0, A1), Data registers (D0, D1), ALU,
and Shift unit to perform various operations required
for the SAR logic. The converted data from SAR is
brought out using the parallel out (PO) feature. For
more details regarding datapath refer the Universal
Digital Blocks section in the Technical Reference
Manual.
A detailed state diagram for the SAR logic is as
follows.
Figure 7. SAR Logic State Diagram
If 8 cycles are complete
(A1 = 0)
Strobe the
DAC
Load A0 and A1
with 0x80
Delay for
DAC settling
Comparator
output High
Check
comparator
output
Comparator
output Low
Subtract A1
from A0
Dummy
A0 :- Holds the SAR value
Shift A1
A1 :- used for counting 8 cycles of
SAR and for resetting the current bit
and setting the next bit of the SAR
(A0)
Add A0 to A1
D0 :- contains the value 0x80. Used to
load A0
D1 :- contains the value 0x80. Used to
load A1
The working of the SAR ADC is explained in the
following steps.
6.
Steps 2 to 5 are repeated until all the 8 bits in the
SAR are tested.
1.
Initialize SAR by setting the Most Significant Bit
(0x80).
7.
The final value present in SAR is the digital
approximation of the analog input voltage.
2.
The value in SAR is fed to the DAC; the DAC
generates an equivalent analog voltage.
3.
Wait for the DAC output to settle.
For an 8-bit SAR ADC, steps 2 to 5 should be
repeated eight times. These steps make one cycle,
thus giving the final 8-bit SAR ADC result in eight
cycles.
4.
The comparator compares the DAC output
voltage with the analog input voltage.
5.
The SAR is updated based on the comparator
output:
If comparator output is high, then the current
bit (b7) remains ‘1’ and the next bit (b6) is
set.
The sampling rate of the ADC is limited by the DAC
settling time. For PSoC 3, the DAC settling time is
1 µs. Hence, ensure a delay of 1 µs before the DAC is
updated each time. Because the DAC cannot be
updated faster than this, the total time taken to
complete one conversion is 1 µs×8 = 8 µs. Therefore,
the maximum conversion rate or sampling rate of the
SAR ADC is 1/8 µs = 125 ksps.
If comparator output is low, then the current
bit (b7) is reset and the next bit (b6) is set.
When the comparator output goes high a dummy
state is introduced. This ensures that when
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comparator output goes high or low, the number of
states in a single cycle remains the same. This is
mandatory and without this dummy state, the SAR
ADC cannot have the same conversion time and
hence same sampling rate for different voltages in the
available voltage range.
A Lookup Table (LUT) is used to create the delay for
DAC settling. A counter is implemented using the
LUT, which starts counting when the trigger signal
goes high. A terminal count is generated when the
delay period is over. This terminal count signal is
connected to the SOC pin of the SAR logic.
The Universal Shift Register shown in the schematic
is a custom component created for this project. The
universal shift register is configured to be in parallel in
parallel out mode. The universal shift register is used
as a latch with its clock tied to the EOC output of
SAR_LOGIC. When EOC happens, the universal shift
register latches the SAR data to a status register. You
can read the status register to get the SAR ADC
result.
completes one cycle, it waits for the delay period for
DAC settling to complete. At the same time the first
SAR ADC triggers the second SAR ADC. When the
second SAR ADC completes one cycle, it triggers the
third SAR ADC. Considering maximum speed all
three SAR ADCs complete one cycle under a
minimum time of 1 µs. Therefore all three SAR ADCs
take 8 µs to complete one conversion and each can
have a maximum sampling rate of 125 ksps.
To realize the triple SAR ADC, an additional signal
named MUX_SEL needs to be added to the
SAR_LOGIC component shown in the following
figure.
Figure 8. Modified SAR Logic Symbol
Track and Hold
A track and hold circuit is mainly used to keep the
input voltage to the SAR ADC constant throughout the
eight conversion cycles. The current implementation
does not use a track and hold circuit. Hence, if the
input voltage varies between conversion cycles, it
results in wrong digital data output. It is possible to
easily construct a track and hold circuit with the
generic SC/CT blocks available in PSoC 3. The Track
and Hold will be made available as a component in a
later version of PSoC Creator.
Triple SAR ADC Implementation
The technique described in the previous section can
be used to construct three simultaneously sampling
SAR ADCs with the same sampling rate as that of a
single channel SAR ADC. Because there are four
VDACs and four comparators available in PSoC 3,
there are sufficient resources to construct up to four
SAR ADCs. This application note discusses the
method to implement three SAR ADCs. The same
idea can be used to construct four SAR ADCs.
Triple SAR ADC is made possible by pipelining the
operation of the three ADCs. When the first SAR ADC
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The SAR data from the SAR_LOGIC component is
fed to the VDAC through the DAC bus. When three
SAR ADCs are used, the output data from three
SAR_LOGIC components should be fed to three
different VDACs. But all four VDACs in PSoC 3 share
a single DAC bus. Hence, multiple connections to the
DAC bus are not permitted. Therefore, we need to
use a multiplexer to connect the SAR data from the
three different SAR_LOGIC components to three
different VDACs.
The MUX_SEL signal is used to ensure that the data
from SAR_LOGIC component of a SAR ADC is
available on the DAC bus when a strobe signal is
applied to the VDAC of that particular SAR ADC. The
SAR_LOGIC component of each of the three SAR
ADCs make the MUX_SEL go high before strobe
signal is applied to the respective VDACs. The three
MUX_SEL lines are given to a suitable encoder which
drives the select lines of the multiplexer used to
connect SAR data to the DAC bus.
Figure 9 shows a functional block diagram of the triple
SAR ADC.
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Figure 9. Triple SAR ADC Functional Block Diagram
LOGIC HIGH
ANALOG In1
COMPARATOR 1
DACOut1
ENABLE
STROBE1
COMP_IN
CLOCK
SAR_LOGIC1
STROBE
PDATA1
MUX_SEL1
SOC
VDAC1
TRIGGER1
DACOut1
DATA [7:0]
8
ANALOG In2
ENABLE
COMPARATOR 2
CLOCK
DACOut2
STROBE2
COMP_IN
SAR_LOGIC2
8
PDATA2
TRIGGER2
ENABLE
COMPARATOR 3
DACOut3
STROBE3
COMP_IN
CLOCK
SOC
SAR_LOGIC3
STROBE
VDAC1
DACOut2
2
ENCODER
ANALOG In3
8
8
MUX_SEL2
SOC
M
U
X
DATA [7:0]
STROBE
PDATA3
MUX_SEL3
VDAC1
DACOut3
TRIGGER3
DATA [7:0]
CLOCK
DELAY
COUNTER
(1µs)
EN
The encoder used for multiplexer is realized using a LUT. The configuration of the LUT is provided in Figure 10.
Figure 10. Configuration of LUT as Encoder
A detailed timing diagram of one cycle of the triple SAR ADC showing the different states of the SAR_LOGIC state
machine and the behavior of important signals is shown in Figure 11.
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Figure 11. Triple SAR ADC Timing Diagram
CLOCK
SOC
SAR ADC 1
STATES
CHECK
COMPAR
ATOR
SUB /
DUMMY
SHIFT
ADD
STROBE
DAC
CHECK
COMPAR
ATOR
Delay for DAC settling
STROBE 1
TRIGGER
1
MUX_SEL
1
SAR ADC 2
STATES
CHECK
COMPAR
ATOR
SUB /
DUMMY
SHIFT
ADD
STROBE
DAC
Delay for DAC settling
STROBE 2
TRIGGER
2
MUX_SEL
2
CHECK
COMPARA
TOR
SAR ADC 3
STATES
SUB /
DUMMY
SHIFT
ADD
STROBE
DAC
Delay for DAC settling
STROBE1
3
TRIGGER
3
MUX_SEL
3
Based on the block diagram and the timing diagram,
you can summarize the operation of triple SAR ADC
as follows.
SAR ADC1 starts conversion initially. After computing
SAR value for that cycle, it asserts the MUX_SEL1
signal and then strobes the DAC and makes Trigger1
high. When Trigger1 is high the lookup table delay
period starts; SAR ADC1 waits until the delay period
is over and Trigger3 is high.
After Trigger1 is asserted SAR ADC2 is enabled and
starts computing its SAR value. When complete, it
asserts Trigger2 and waits for the next trigger. When
Trigger2 is asserted SAR ADC 3 is enabled and after
computation it asserts Trigger3 and waits for the next
trigger.
When the delay period is complete and Trigger3 is
high, the signal SOC goes high. At that time SAR
ADC1 starts its second cycle and SAR ADC2 and
SAR ADC3 are stopped until their respective trigger is
asserted.
Refer to the attached project library for details on
PSoC Creator schematic and other necessary files for
triple SAR ADC component.
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Calculating the Sample Rate
The sample rate for all three SAR ADCs is given by
the inverse of the time taken for these ADCs to
complete one conversion. The total time taken for a
conversion is given by the following relation.
TSAMPLERATE = 43 × t_clock + 9 × t_delay
Equation 1
Hence the sample rate can be expressed as:
Sample Rate = 1 / TSAMPLERATE
Equation 2
Where t_clock is the time period of the SAR ADC
clock and t_delay is the delay provided by the lookup
table delay circuit.
As mentioned earlier, the settling time for the DAC
should not be less than 1 µs. From the timing diagram
in Figure 11, the time between two DAC updates is
written as:
T_DAC = t_delay + 5 × t_clock
Equation 3
t_delay can be calculated to satisfy the DAC settling
time criterion as follows.
t_delay ≥ 1µs – 5 × t_clock
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Equation 4
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As shown in the timing diagram, SAR ADC2 and SAR
ADC3 should complete one cycle of operation inside
the t_delay period. Hence t_delay can also be
expressed as follows.
t_delay ≥ 10 × t_clock
Equation 5
The lookup table delay circuit should be designed
such that it satisfies both Equation 4 and Equation 5.
For clock frequencies where the time taken to
complete one cycle of operation for two SAR ADCs is
greater than 1 µs, the lookup table delay can be
avoided to save resources and increase sample rate.
Triple SAR ADC Component
A component for triple SAR ADC is created so that
you can just place the component in the schematic
and use three simultaneously sampling ADCs similar
to other components. Several user configuration
parameters and Application Program Interface (API)
are provided with the component for better usability.
The details of the components are discussed here.
EOC: End of Conversion signal. The signal goes
high when all ADCs complete a conversion.
PDATA1 [7:0]: Parallel data output for SAR
ADC1. Available only if parallel output is enabled
for SAR ADC1.
PDATA2 [7:0]: Parallel data output for SAR
ADC2. Available only if parallel output is enabled
for SAR ADC2.
PDATA3 [7:0]: Parallel data output for SAR
ADC3. Available only if parallel output is enabled
for SAR ADC3.
Configuration Window
The configuration window
component is as follows.
of
Custom_nSAR
Figure 13. Configuration Window for Custom_nSAR
Symbol
The symbol for the triple SAR ADC component is as
shown in the following figure. The component is
named as Custom_nSAR.
Figure 12. Custom_nSAR Symbol
The different configuration parameters are as follows.
The different signals used in the Custom_nSAR are
as follows.
Analog_In1: Analog input pin for SAR ADC1.
Analog_In2: Analog input pin for SAR ADC2.
Available only if the number of SAR ADCs
selected is two or more.
Analog_In3: Analog input pin for SAR ADC3.
Available only if the number of SAR ADCs
selected is three.
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DataOut1: Enable/disable parallel outputs for
SAR ADC1.
DataOut2: Enable/disable parallel outputs for
SAR ADC2.
DataOut3: Enable/disable parallel outputs for
SAR ADC3.
NumOfSAR: Select the required number of SAR
ADCs. You can choose from the three given
options ‘1’, ‘2’, and ‘3’.
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Application Programming Interface (API)
A brief description of the different APIs available with the component is provided in the following table.
Table 1. List of APIs
Function
Description
void Custom_nSAR_Start(void)
Start the SAR ADC.
void Custom_nSAR_Stop(void)
Stop the SAR ADC.
uint8 Custom_nSAR_IsEndConversion(uint8 retMode)
Returns a non zero value if conversion is complete.
uint8 Custom_nSAR_GetResult1(void)
Returns the conversion result for SAR ADC1.
uint8 Custom_nSAR_GetResult2(void)
Returns the conversion result for SAR ADC2. Available only if
the number of SAR ADCs selected is two or more
uint8 Custom_nSAR_GetResult3(void)
Returns the conversion result for SAR ADC3. Available only if
the number of SAR ADCs selected is three.
The APIs are located in the header file that gets
generated with the component (for example,
Custom_nSAR.h). The details regarding the APIs are
in the ‘.c’ file (for example, Custom_nSAR.c).
Configuring Sample Rate for the
Triple SAR ADC Component
The main parameter that determines the sample rate
is the frequency of the clock given to the SAR ADC.
The component is designed such that the sampling
rate is the same irrespective of the number of SAR
ADCs (up to a maximum clock frequency of 20 MHz).
Table 2. Sample Rate vs Clock Frequency
By default, the clock frequency of the custom
component is 12 MHz, which results in a sampling
rate of 66 ksps. Change the clock frequency in the
component schematic to achieve different sampling
rate. When changing the clock frequency of the
custom SAR component, make sure that the master
clock frequency of the project in which the component
is used is a multiple of SAR ADC frequency to obtain
accurate results.
Table 2 shows a set of sample rates achieved for
different SAR ADC clock frequencies and
corresponding master clock frequencies.
SAR ADC Clock Frequency
Master Clock Frequency
Sample Rate (samples/sec)
20 MHz
40 MHz, 60 MHZ
110000
18 MHz
36 MHz, 54 MHz
100000
16 MHz
32 MHz, 48 MHz, 64 MHz
89000
12 MHz
24 MHz, 36 MHz, 48 MHz, 60 MHz
66000
[1]
Note
1. The sample rate values provided are not characterized values.
The design of the lookup table delay circuit in the
component is optimized for 20 MHz clock frequency.
For other frequencies listed in the table, it is possible
to achieve higher sampling rate by suitably designing
the delay circuit as explained in the Calculating the
Sample Rate section.
The component is not properly designed to operate
for clock frequencies higher than 20 MHz.
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Example Project
An example project is provided along with this
application note to demonstrate the use of the
Custom_nSAR component. This section provides an
overview of the example project.
The example project converts three analog input
voltages and displays the result on an LCD. The
schematic for the project is shown in the following
figure.
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}
Figure 14. Example Project Schematic
}
Summary
This application note describes how to use the
programmable analog and digital blocks available in
PSoC 3 to construct a single SAR ADC and also three
simultaneously sampling SAR ADCs.
The application note comes along with a project
library for triple SAR ADC component named as
Custom_nSAR and an example project to
demonstrate the usage of Custom_nSAR component.
The workspace for the example project is named as
Test_Custom_nSAR.
The Custom_nSAR component is configured for
default values and the configuration window is as
shown in Figure 13.
The firmware written for the project is as follows.
void main()
{
uint8 SAR_adc1Value, SAR_adc2Value,
SAR_adc3Value;
LCD_Start();
/*Start the SAR ADC*/
Custom_nSAR_1_Start();
for(;;)
{
/*Read converted result from
SAR ADC1 and display on LCD*/
SAR_adc1Value =
Custom_nSAR_1_GetADCResult1();
LCD_Position(0,0);
LCD_PrintInt8(SAR_adc1Value);
/*Read converted result from SAR
ADC2 and display on LCD*/
SAR_adc2Value =
Custom_nSAR_1_GetADCResult2();
LCD_Position(0,4);
LCD_PrintInt8(SAR_adc2Value);
/*Read converted result
from SAR ADC3 and display on LCD*/
SAR_adc3Value =
Custom_nSAR_1_GetADCResult3();
LCD_Position(0,8);
LCD_PrintInt8(SAR_adc3Value);
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Document History
Document Title: SAR ADC in PSoC® 3
Document Number: 001-60832
Revision
**
ECN
2912868
Orig. of
Change
ANUP
Submission
Date
04/14/10
Description of Change
New Application Note
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