1 A 2 3 4 5 6 Notes: - 4 layer PCB: 2 layers for Customer Reference and 2 layers for Evaluation. - 20 mil trace (minimum) on all power and ground routes. - Decoupling capacitors are physically close to U1 VDD and U2 VCC, respectively. - Designed for TSL2581CS and TSL2581FN. - All passive components are EIA0603 except C1 which is EIA0402. - Assembly drawing: - PCB drawing: A Evaluation Schematic Components mounted on bottom-side of PCB PIC201 PIR201 COC2 C2 PIC202 COU2 U2 CAP NP 1 PIU201 8 PIU208 A0 2 PIU202 A1 3 PIU203 A2 4 PIU204 VSS B VCC 7 WP PIU207 6 SCL PIU206 5 PIU205 SDA PIR301 PIR401 PIR501 COR2 R2 COR3 R3 COR4 R4 Comment Open Open PIR202 PIR302 PIR402 COR5 R5 RESISTOR/SM_0603_10K PIR502 NLEVDD EVDD B PIR102 COR1 R1 24LC04B RESISTOR/SM_0603_OPEN Ground PIR101 Customer Reference Schematic Components mounted on top-side of PCB COJ1 J1 1 PIJ101 NLVDD VDD NLI2CSDA SDA I2C NLInterrupt Interrupt NLDBDetect Detect DB 2 PIJ102 3 PIJ103 4 PIJ104 5 PIJ105 6 PIJ106 7 PIJ107 5V0 VDD GND SDA SCL INT IO MN1213_0_HDR_1X7_DB CONNECTOR COU1 U1 C 1 PIU101 VDD 2 Add Sel 3 PIU103 GND PIU102 PIC101 COC1 C1 C 6 SDA PIU106 5 INT PIU105 4 SCL PIU104 PITP101 TSL2581FN TP1 COTP1 NLGround Ground PITP201 TP2 COTP2 PIC1102 uF Ground D D Title Size Number A Date: File: 1 2 3 4 5 6/28/2013 Sheet of D:\WORK\..\TSL2581CS_Schematic.SchDoc Drawn By: 6 Revision