PHILIPS TDA8310

INTEGRATED CIRCUITS
DATA SHEET
TDA8310
PAL/NTSC colour processor for
PIP applications
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
February 1995
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
FEATURES
GENERAL DESCRIPTION
• Multistandard vision IF circuit (positive and negative
modulation)
The TDA8310 is an alignment-free PAL/NTSC colour
processor for Picture-in-Picture (PIP) applications. The
circuit contains a vision IF amplifier, a PAL/NTSC colour
decoder, horizontal and vertical synchronization and an
RGB/YUV switch.
• Video switch which automatically detects whether the
incoming signal is CVBS or Y/C
• Integrated chrominance trap and bandpass filters
(automatically calibrated)
As input for the colour decoder and sync processor the
demodulated IF signal can be chosen but the circuit also
has a video input which automatically detects whether the
incoming signal is CVBS or Y/C. The output signals for the
PIP processor are:
• Integrated luminance delay line
• Automatic PAL/NTSC decoder which can decode all
standards available in the world
• Easy interfacing with the TDA8395 (SECAM decoder)
for multistandard applications
Luminance signal
• Horizontal PLL with an alignment-free horizontal
oscillator
Horizontal and vertical synchronization pulses.
Colour difference signals (U and V)
• Vertical count-down circuit
The RGB/YUV switch can select between two RGB or
YUV sources, e.g. between the PIP processor and the
SCART input signal.
• RGB/YUV and fast blanking switch with 3-state output
and active clamping
The supply voltage for the IC is 8 V. It is available in a
52-pin SDIP package.
• Low dissipation (560 mW)
• Small amount of peripheral components compared with
competition ICs.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA8310
February 1995
SDIP52
DESCRIPTION
plastic shrink dual in-line package; 52 leads (600 mil)
2
VERSION
SOT247-1
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VP
supply voltage (pins 19 and 41)
7.2
8.0
8.8
V
IP
supply current
−
70
−
mA
Vi(rms)
vision IF amplifier input sensitivity (RMS value)
−
70
100
µV
V17,20(p-p)
CVBS/Y input voltage (peak-to-peak value)
−
1
1.4
V
V16(p-p)
chrominance input voltage (peak-to-peak value)
−
0.3
−
V
Vi(p-p)
RGB/YUV input signal voltage amplitude
(peak-to-peak value)
−
−
1.3
V
Vo(p-p)
demodulated CVBS output voltage
(peak-to-peak value)
−
2.5
−
V
V29
tuner AGC control output voltage
0
−
12
V
Vo(p-p)
luminance output voltage (peak-to-peak value)
−
1.4
−
V
V50(p-p)
(B−Y) output voltage (peak-to-peak value)
1.06
1.33
1.60
V
V51(p-p)
(R−Y) output voltage (peak-to-peak value)
0.84
1.05
1.26
V
V39
horizontal sync pulse output voltage
−
4
−
V
V36
vertical sync pulse output voltage
−
4
−
V
Gv
voltage gain of the RGB switches
−0.5
0
+0.5
dB
control voltage for HUE
0
−
5
V
Input voltages
Output signals
Control voltage
Vcontrol
February 1995
3
DEC DIG
37
35
21
41
19
39
SAND
36
40
10
VCO
+
CONTROL
PHASE
DETECTOR
HOUT VOUT
PULSE
SHAPER
SANDCASTLE
GENERATOR
11
12
TUNER ADJ
TUNER AGC
31
29
30
C AGC
13
AGC FOR
IF AND
TUNER
VERTICAL
SYNC
SEPARATOR
SYNC
SEPARATOR
14
HORIZONTAL/
VERTICAL
DIVIDER
8
RGB/YUV
SWITCH
IF2
4
DEC FT
33
34
6
VIF
AMPLIFIER
DEMODULATOR
5
TDA8310
15
1
2
3
VIDEO
AMPLIFIER
CHROMINANCE
BANDPASS
CHROMINANCE
TRAP
52
FILTER
TUNING
4
REF
28
AUTOMATIC
Y/C
DETECTOR
PAL/NTSC
DECODER
INPUT
SELECTOR
22
VIDEO
20
17
9
CVBS EXT
CHROMA 1
SYSTsw
48
47
45
41
43
42
PLL
XTAL4
XTAL3
XTAL2
XTAL1
SECAM
27
R/W
CHROMA 0
26
COLOUR2
COLOUR1
24
23
50
51
18
LOGIC2
R Y
B Y
GND1
LOGIC1
BLANK1
CLAMP
R
G
B
BLANK
R2
G2
B2
BLANK2
IDENT
HUE
Y
38
MBE245
GND2
TDA8310
Fig.1 Block diagram.
25
B1
49
LUMINANCE
DELAY LINE
46
G1
Preliminary specification
CVBS INT
16
handbook, full pagewidth
IF1
7
R1
Philips Semiconductors
DEC BG
V P1
( 8 V)
PAL/NTSC colour processor for
PIP applications
COINCIDENCE/
NOISE
DETECTOR
PH1LF
V P2
( 8 V)
BLOCK DIAGRAM
February 1995
CVBS sw
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
PINNING
SYMBOL
PIN
DESCRIPTION
SYMBOL
PIN
DESCRIPTION
R2
1
RED input 2 (PIP)
HUE
28
HUE control input
G2
2
GREEN input 2 (PIP)
TUNERAGC
29
tuner AGC output
B2
3
BLUE input 2 (PIP)
CAGC
30
AGC filter capacitor
IDENT
4
colour standard identification output
TUNERADJ
31
tuner take-over adjustment input
BLANK
5
blanking output
CVBSSW
32
B
6
BLUE output
CVBS positive/negative modulation
control switch input
G
7
GREEN output
IF1
33
IF input 1
R
8
RED output
IF2
34
IF input 2
SYSTSW
9
system switch
DECBG
35
bandgap decoupling
36
vertical sync output pulse
37
phase 1 loop filter
R1
10
RED input 1
VOUT
G1
11
GREEN input 1
PH1LF
B1
12
BLUE input 1
GND2
38
ground 2 (0 V)
39
horizontal sync output pulse
BLANK1
13
blanking input 1
HOUT
CLAMP
14
clamping pulse input
SAND
40
sandcastle pulse output
DECFT
15
decoupling filter tuning
VP2
41
supply voltage 2 (+8 V)
42
4.4336 MHz crystal
CHROMAI
16
chrominance input
XTAL1
CVBSEXT
17
external CVBS input
XTAL2
43
3.5820 MHz crystal for PAL-N
GND1
18
ground 1 (0 V)
XTAL3
44
3.5756 MHz crystal for PAL-M
45
3.5795 MHz crystal for NTSC
46
PLL colour filter
VP1
19
supply voltage 1 (+8 V)
XTAL4
CVBSINT
20
internal CVBS input
PLL
DECDIG
21
decoupling digital supply
CHROMAO
47
chrominance output for TDA8395
48
SECAM reference output
VIDEO
22
IF video output
SECAM
LOGIC2
23
crystal logic 2 input/output
Y
49
Y output
LOGIC1
24
crystal logic 1 input/output
B−Y
50
B−Y output
COLOUR2
25
colour system logic 2 input/output
R−Y
51
R−Y output
BLANK2
52
blanking/insertion input 2 (PIP)
COLOUR1
26
colour system logic 1 input/output
R/W
27
read/write selection input
February 1995
5
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
handbook, halfpage
R2
1
52 BLANK2
G2
2
51 R Y
B2
3
50 B Y
IDENT
4
49 Y
BLANK
5
48 SECAM
B
6
47 CHROMA O
G
7
46 PLL
R
8
45 XTAL4
SYST SW
9
44 XTAL3
R1 10
43 XTAL2
G1 11
42 XTAL1
B1 12
41 VP2
BLANK1 13
40 SAND
TDA8310
CLAMP 14
39 HOUT
DEC FT 15
38 GND2
CHROMA I 16
37 PH1LF
CVBS EXT 17
36 VOUT
35 DEC BG
GND1 18
VP1 19
34 IF2
CVBS INT 20
33 IF1
DEC DIG 21
32 CVBS SW
VIDEO 22
31 TUNERADJ
LOGIC2 23
30 CAGC
LOGIC1 24
29 TUNERAGC
COLOUR2 25
28 HUE
26
27 R/W
COLOUR1
MBE244
Fig.2 Pin configuration.
February 1995
6
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
The vertical output pulse is generated by a count-down
circuit. The pulse width is approximately 380 µs. Both the
horizontal and vertical pulses will always be available at
the outputs even when no input signal is available.
FUNCTIONAL DESCRIPTION
Vision IF amplifier
The IF amplifier contains three AC-coupled control stages
with a total gain control range >60 dB. The sensitivity of
the circuit is comparable with that of modern IF-ICs. The
demodulation of the IF signal is achieved by a multiplier.
The demodulator is alignment-free and does not require
external components.
In addition to the horizontal and vertical sync pulse outputs
the IC has a sandcastle pulse output which contains burst
key and blanking pulses.
Integrated video filters
The polarity of the demodulator can be switched to make
the circuit suitable for positive and negative modulated
signals.
The circuit contains a chrominance bandpass and trap
circuit. The filters are realised by gyrator circuits that are
automatically tuned by comparing the tuning frequency
with the crystal frequency of the decoder. When a Y/C
signal is supplied to the input the chrominance trap is
automatically switched off by the Y/C detection circuit, but
it is also possible to force the filters in the CVBS or Y/C
position.
The AGC detector operates on top-sync or top white-level
depending on the position of the demodulator. The AGC
detector time-constant capacitor is externally connected to
facilitate flexibility of the application. During positive
modulation the time-constant of the AGC system is too
long to avoid visible variations of the signal amplitude. To
obtain an acceptable speed of the AGC system a circuit
has been included which detects whether the AGC
detector is activated every frame period. When no action
is detected during three frame periods the speed of the
system is increased.
The luminance delay line is also realised by gyrator
circuits.
Colour decoder
The colour decoder contains an alignment-free crystal
oscillator, a colour killer circuit and colour difference
demodulators. The 90° phase shift for the reference signal
is achieved internally.
Synchronization circuit
The sync separator is preceded by a voltage controlled
amplifier which adjusts the sync pulse amplitude to a fixed
level. The sync pulses are then fed to the slicing stage
(separator) which operates at 50% of the amplitude.
The colour decoder is very flexible. Together with the
SECAM decoder TDA8395 an automatic multistandard
decoder can be designed but it is also possible to use it for
one standard when only one crystal is connected to the IC.
The decoder can be forced to one of the standards via the
“forced mode” pins. The crystal pins which are not used
must be connected to the positive supply line via a 8.2 kΩ
resistor. It is also possible to connect the non-used pins
with one resistor to the positive supply line. In this event
the resistor must have a value of 8.2 kΩ divided by the
number of pins.
The separated sync pulses are fed to the first phase
detector and to the coincidence detector. The coincidence
detector is used to detect whether the line oscillator is
synchronized and for transmitter identification. The first
PLL has a very high static steepness, this ensures that the
phase of the picture is independent of the line frequency.
The line oscillator operates at twice the line frequency.
The oscillator network is internal. Because of the spread of
internal components an automatic adjustment circuit has
been added to the IC.
The chrominance output signal of the video switch is
externally available and must be used as an input signal
for the SECAM decoder.
The circuit compares the oscillator frequency with that of
the crystal oscillator in the colour decoder. This results in
a free-running frequency which deviates less than 2% from
the typical value.
RGB/YUV switch
The RGB/YUV switch is for switching between two RGB or
YUV video sources. The outputs of the switch can be set
to high impedance state so that other switches can be
used in parallel.
The horizontal output pulse is derived from the horizontal
oscillator via a pulse shaper. The pulse width of the output
pulse is 5.4 µs, the front edge of this pulse coincides with
the front edge of the sync pulse at the input.
February 1995
The switch is controlled via pins 13 and 52. The details of
switch control are shown in Table 5.
7
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VP
supply voltage
−
9.0
V
Tstg
storage temperature
−25
+150
°C
Tamb
operating ambient temperature
−25
+70
°C
Tsld
soldering temperature for 5 s
−
260
°C
Tj
maximum operating junction temperature
−
150
°C
Ves
electrostatic discharge
note 1
−2000
+2000
V
note 2
−200
+200
V
Notes
1. Human body model 100 pF, 1500 Ω.
2. Machine model 200 pF, 0 Ω.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air
VALUE
UNIT
≤40
K/W
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611 part E”. The numbers of the quality specification can be found in the “Quality
Reference Handbook”. The handbook can be ordered using the code 9398 510 63011. All pins are protected against
electrostatic discharge by means of internal clamping diodes.
Latch up
At Tamb = 70 °C most pins meet the specification:
Itrigger ≥ 100 mA or ≥ 1.5 VDDmax
Itrigger ≤ −100 mA or ≤ −0.5 VDDmax.
The following pins do not meet this specification:
pin 7 +90 mA
pin 21 +90 mA
pin 32 −90 mA
pin 46 +90 mA.
February 1995
8
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
CHARACTERISTICS
VP = 8 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VP
supply voltage (pins 19 and 41)
7.2
8.0
8.8
V
IP1
supply current (pin 19)
45
65
80
mA
IP2
supply current (pin 41)
3
5
10
mA
Ptot
total power dissipation
−
560
−
mW
fi = 38.90 MHz
−
70
100
µV
fi = 45.75 MHz
−
70
100
µV
fi = 58.75
−
70
100
µV
IF circuit
VISION IF AMPLIFIER INPUT (PINS 33 AND 34)
Vi(rms)
input sensitivity (RMS value)
note 1
RI
Input resistance (differential)
note 2
1.6
2.0
2.4
kΩ
CI
Input capacitance (differential)
note 2
−
3
−
pF
Gcr
gain control range
note 3
Vi(rms)
maximum input signal (RMS value)
64
−
−
dB
100
150
−
mV
4.45
4.60
4.75
V
1.9
2.0
2.1
V
1.85
2.00
2.15
V
4.2
4.3
4.4
V
VIDEO AMPLIFIER OUTPUT; note 4 (PIN 22)
V22(neg)
negative modulation
zero signal output level
note 5
top sync level
V22(pos)
positive modulation
zero signal output level
note 5
white level
∆V22
difference in amplitude between
negative and positive modulation
−
0
15
%
ZO
video output impedance
−
−
75
Ω
Ibias
internal bias current of NPN emitter
follower output transistor
1
−
−
mA
Isource
maximum source current
−
−
5
mA
S/N
signal-to-noise ratio
52
60
−
dB
notes 6 and 7
Vi = 10 mV
V22(rc)
residual carrier signal
February 1995
end of control range
52
61
−
dB
note 6
−
2.5
−
mV
9
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
SYMBOL
PARAMETER
TDA8310
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IF AND TUNER AGC
Timing of IF-AGC (C30 = 2.2 µF)
30% AM for 1 to 100 mV; −
0 to 200 Hz (system B/G)
−
10
%
−
2
5
ms
−
25
50
ms
−
100
200
ms
for negative modulation
−
−
10
µA
for positive modulation
−
−
200
nA
modulated video interference
tinc
response time for an IF input signal
amplitude increase of 52 dB for
positive and negative modulation
tdec
response time for an IF input signal
amplitude decrease of 52 dB
for negative modulation
for positive modulation
Ileak
allowed leakage current of the AGC
capacitor
note 8
Tuner take-over adjustment (pin 31)
V31(rms)
minimum starting level voltage for
tuner take-over (RMS value)
−
0.2
0.5
mV
V31(rms)
maximum starting level voltage for
tuner take-over (RMS value)
100
150
−
mV
Vcr
control voltage range
0.5
−
4.5
V
Tuner control output (pin 29)
V29
maximum tuner AGC output voltage
maximum gain
−
−
12
V
V29(sat)
output saturation voltage
minimum gain;
I29 = 2 mA
−
−
300
mV
I29
maximum tuner AGC output current
swing
5
−
−
mA
Ileak
leakage current RF AGC
−
−
1
µA
∆V29
input signal voltage variation for
complete tuner control
0.5
2.0
4.0
dB
−
1
1.4
V
IO(max) = 1 mA
CVBS and Y/C switch
INTERNAL CVBS AND EXTERNAL CVBS/Y INPUTS (PINS 20 AND 17)
V20,17(p-p)
CVBS/Y input voltage
(peak-to-peak value)
I20,17
input current
−
4
6
µA
Vclamp
top sync clamping voltage level
−
3.3
−
V
Iclamp
clamping input current
80
100
−
µA
February 1995
notes 2 and 9
10
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
SYMBOL
PARAMETER
TDA8310
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CHROMINANCE INPUT (PIN 16)
−
0.3
−
V
input signal amplitude before clipping note 6
occurs (peak-to-peak value)
1.0
−
−
V
RI
chrominance input resistance
14
20
26
kΩ
CI
chrominance input capacitance
−
−
5
pF
V16(p-p)
chrominance input voltage
(peak-to-peak value)
V16(p-p)
notes 2, 10 and 17
note 2
CHROMINANCE OUTPUT (PIN 47)
V47(p-p)
output signal voltage amplitude
(peak-to-peak value)
0.18
0.20
0.22
V
ZO
output impedance
200
250
300
Ω
VO
DC output voltage
1.2
1.4
1.6
V
−
1
V
open-circuit output
SWITCH CONTROL INPUT FOR INTERNAL/EXTERNAL POSITIVE/NEGATIVE MODULATION; note 11 (PIN 32)
V32
internal CVBS signal selected
−
with negative modulation
2
−
3
V
V32
external CVBS or Y/C signal selected IF switched to negative
modulation
3.9
−
VP
V
ZI
input impedance
25
−
−
kΩ
ISS
suppression of non-selected video
input signal
50
−
−
dB
−
−
1
V
2
−
3
V
with positive modulation
note 12
note 6
SWITCH CONTROL INPUT FOR EXTERNAL CVBS OR Y/C SELECTION (PIN 9)
V9
filters switched to CVBS condition
V9
filters switched to Y/C condition
V9
automatic selection of CVBS or Y/C
3.9
−
VP
V
ZI
input impedance
25
−
−
kΩ
−
fosc
−
MHz
−
2
−
20
−
−
dB
−
fosc
−
MHz
note 12
Chrominance filters, luminance delay line and luminance output
CHROMINANCE TRAP CIRCUIT
ftrap
trap frequency
QF
trap quality factor
SR
colour subcarrier rejection
notes 6 and 13
CHROMINANCE BANDPASS CIRCUIT
fc
centre frequency
QBP
bandpass quality factor
note 6
−
3
−
∆td
difference in delay time between the
luminance and the demodulated
chrominance signals
note 6
0
50
100
ns
B
bandwidth of internal delay line
note 6
8
−
−
MHz
Y DELAY LINE
February 1995
11
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
SYMBOL
TDA8310
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Y OUTPUT (PIN 49)
V49(b-w)
output signal voltage amplitude
(black-to-white value)
ZO
note 29
0.8
1.0
1.2
V
output impedance
80
100
120
Ω
V49(DC)
DC output voltage level (top sync)
2.7
2.9
3.1
V
Ibias
internal bias current of NPN emitter
follower output transistor
0.4
0.5
−
mA
Isource
maximum source current
−
−
2
mA
Horizontal and vertical synchronization circuits
SYNC VIDEO INPUT (PINS 17 AND 20)
V17,20
sync pulse voltage amplitude
note 2
50
300
−
mV
SL
slicing level
note 14
−
50
−
%
note 15
22
−
−
µs
−
15625
−
Hz
VERTICAL SYNC
tW
width of the vertical sync pulse
without sync instability
HORIZONTAL OSCILLATOR
ffr
free running frequency
∆ffr
spread on free running frequency
∆fosc/∆VP
frequency variation with respect to
the supply voltage
VP = 8 V ±10%; note 6
∆fosc
frequency variation with temperature
∆fosc( max)
maximum frequency deviation at the
start of the horizontal output
no calibration
−
−
±2
%
−
0.2
0.5
%
Tamb = 0 to 70 °C; note 6 −
−
80
Hz
−
−
75
%
−
±0.9
±1.2
kHz
±0.6
±0.9
−
kHz
HORIZONTAL PLL; note 16 (FILTER CONNECTED TO PIN 37)
fHR
holding range PLL
fCR
catching range PLL
S/N
signal-to-noise ratio of the video
input signal at which the time
constant is switched
14
20
26
dB
HYS
hysteresis at the switching point
1
3
6
dB
−
V
note 6
HORIZONTAL OUTPUT (PIN 39)
VOH
HIGH level output voltage
IO = 2 mA
2.4
4.0
IO = 2 mA
VOL
LOW level output voltage
−
0.3
0.6
V
Isink
sink current
−
−
2
mA
Isource
source current
−
−
2
mA
tW
pulse width
−
5.4
−
µs
td
delay between the positive edge of
the horizontal output pulse and the
start of the horizontal sync pulse at
the input
−
0
−
µs
February 1995
12
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
SYMBOL
PARAMETER
TDA8310
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VERTICAL OUTPUT; note 17 (PIN 36)
ffr
free running frequency
−
50/60
−
Hz
flock
locking range
45
−
64.5
Hz
divider value not locked
−
625/525 −
lines
locking range
488
−
722
lines/
frame
VOH
HIGH level output voltage
IO = 2 mA
2.4
4.0
−
V
VOL
LOW level output voltage
IO = 2 mA
−
0.3
0.6
V
Isink
sink current
−
−
2
mA
Isource
source current
−
−
2
mA
tW
pulse width
−
380
−
µs
td
delay between the start of the vertical
sync pulse at the input and the
positive edge of the output pulse
−
37.5
−
µs
SANDCASTLE PULSE OUTPUT; note18 (PIN 40)
VO
output voltage during scan
IO = 1 mA; note 30
−
−
0.9
V
VO
output voltage during burst key
IO = 1 mA; note 30
4.1
−
5.2
V
ZO
output impedance during blanking
1.0
−
−
MΩ
tW
pulse width
burst key
3.3
3.5
3.7
µs
line blanking
8.4
8.7
9.0
µs
vertical blanking
−
14
−
lines
5.2
5.4
5.6
µs
26
−
−
dB
−
−
2
dB
−38
−41
−44
dB
0
+3
+6
dB
0
+1
+8
dB
2.3
−
2.7
td
delay of start of burst key to start of
sync
Colour demodulation part
CHROMINANCE AMPLIFIER
ACCcr
ACC control range
∆V
change in amplitude of the output
signals over the ACC range
THRon
threshold colour killer ON
HYSoff
hysteresis colour killer OFF
strong input signal
note 19
note 6
S/N ≥ 40 dB
noisy input signal
ACL CIRCUIT
chrominance burst ratio at which the
ACL starts to operate
February 1995
13
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
SYMBOL
PARAMETER
TDA8310
CONDITIONS
MIN.
TYP.
MAX.
UNIT
REFERENCE PART
Phase-locked loop; note 20
fCR
catching range
300
500
−
Hz
∆ϕ
phase shift for a ±300 Hz deviation of note 6
the oscillator frequency
−
−
2
deg
TCosc
temperature coefficient of fosc
note 6
−
2.0
2.5
Hz/K
Oscillator
∆fosc
fosc deviation with respect to VP
note 6; VP = 8 V ±10%
−
−
250
Hz
RI
input resistance (pins 43 to 45)
fi = 3.58 MHz; note 2
−
1.5
−
kΩ
RI
input resistance (pin 42)
fi = 4.43 MHz; note 2
−
1
−
kΩ
CI
input capacitance (pins 42 to 45)
note 2
R
required resistance to VP for a crystal note 21
pin which is not used
−
−
10
pF
7.8
8.2
8.6
kΩ
±35
±40
−
deg
45
−
−
kΩ
note 20
VP−1
−
−
V
HUE CONTROL INPUT; note 22 (PIN 28)
HUEcr
HUE control range
RI
input resistance
Vcontrol
control voltage to switch the colour
PLL in the free-running mode
see also Fig.3
DEMODULATOR OUTPUTS (PINS 50 AND 51)
V50(p-p)
(B−Y) output signal voltage
amplitude (peak-to-peak value)
note 31
1.06
1.33
1.60
V
V51(p-p)
(R−Y) output signal voltage
amplitude (peak-to-peak value)
note 31
0.84
1.05
1.26
V
spread of signal amplitude ratio
PAL/NTSC
note 6
−1
−
+1
dB
−
−
500
Ω
ZO
output impedance (R−Y)/(B−Y)
output
B
bandwidth of demodulators
−3 dB; note 23
−
650
−
kHz
V50(p-p)
(B−Y) residual carrier output voltage
(peak-to-peak value)
f = fosc
−
−
1
mV
f = 2fosc
−
−
5
mV
V51(p-p)
(R−Y) residual carrier output voltage
(peak-to-peak value)
f = fosc
−
−
1
mV
f = 2fosc
−
−
5
mV
V51(p-p)
H/2 ripple at (R−Y) output
(peak-to-peak value)
only burst fed to input
−
−
25
mV
∆VO/∆T
change of output signal amplitude
with temperature
note 6
−
0.1
−
%/K
∆VO/∆VP
change of output signal amplitude
with supply voltage
note 6
−
−
±0.1
dB
Ibias
internal bias current of NPN emitter
follower output transistor
0.16
0.20
−
mA
Isource
maximum source current
−
−
1
mA
February 1995
14
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
SYMBOL
PARAMETER
TDA8310
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DEMODULATION ANGLE AND GAIN RATIO
G
demodulation angle
85
90
95
gain ratio of both demodulators
G(B−Y) to G(R−Y)
1.60
1.78
1.96
deg
−
4.43
−
MHz
0.2
0.25
0.3
V
REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 48)
fref
reference frequency
V48(p-p)
output signal amplitude
(peak-to-peak value)
note 24
VO
output voltage level
PAL/NTSC identified
1.5
1.6
1.7
V
VO
output voltage level
no PAL/NTSC; SECAM
(by TDA8395) identified
4.3
4.5
4.7
V
I48
required current to force the decoder
in SECAM mode
120
−
−
µA
STANDARD IDENTIFICATION AND FORCED SYSTEM SWITCHING; note 25 (PINS 4 AND 23 TO 27)
VI/O
input/output voltage
in “low” condition
−
−
1
V
in “high” condition
4.0
−
5.3
V
−
−
VP
V
−
−
1
mA
−
−
1
µA
−
−
10
µA
80
−
−
kΩ
during PAL
−
−
0.9
V
during SECAM
VI(max)
maximum input voltage
Iload
maximum load current (pins 23 to 26)
II
input current (pins 23 to 26)
note 26
in “low” or “high” condition
when connected to VP
RI
input resistance (pin 27)
VO
output voltage (pin 4)
note 26
notes 27 and 30
4.1
−
5.5
V
ZO
output impedance pin 4 during NTSC note 27
1
−
−
MΩ
Iload
maximum load current (pin 4)
−
−
0.5
mA
RGB switch
RGB INPUTS (PINS 1 TO 3 AND 10 TO 12)
Vi(p-p)
signal voltage amplitude
(peak-to-peak value)
−
−
1.3
V
ZI
input impedance
100
−
−
kΩ
Vclamp
active clamping voltage level
2.6
2.8
3.0
V
ILI
input leakage current
−
−
3
µA
Iclamp
active clamping current
−200
−
+200
µA
February 1995
note 6
15
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
SYMBOL
TDA8310
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FAST BLANKING/SWITCH INPUTS; note 28 (PINS 13 AND 52)
VIH
HIGH level input voltage
0.9
−
3.0
V
VIL
LOW level input voltage
0
−
0.5
V
II
input current
−
−0.2
−0.3
mA
td
delay between input and output pulse
−
−
50
ns
td
delay between switch input and RGB
output
−
−
70
ns
V13
input voltage on pin 13 to make RGB
outputs and the fast blanking output
high-ohmic
4
−
VP
V
4.0
4.5
VP
V
CLAMPING PULSE INPUT (PIN 14)
VIH
HIGH level input voltage
VIL
LOW level input voltage
−
−
1
V
ZI
input impedance
1
−
−
MΩ
RGB OUTPUTS (PINS 6 TO 8)
Gv
voltage gain of the switches
−0.5
0
+0.5
dB
Gdiff
gain difference of the three channels
−
−
0.5
dB
ZO
output impedance
−
−
150
Ω
f = 1 MHz
ZO(off)
output impedance in the “off” state
f = 10 MHz
100
−
−
kΩ
VO
output voltage during blanking
open-circuit output
1.2
1.4
1.6
V
Vos
blanking off-set voltage of the two
sources
−
−
5
mV
Ibias
internal bias current of NPN emitter
follower output transistor
0.16
0.2
−
mA
Isource(max)
maximum source current
−
−
1
mA
ISS
input signal suppression when RGB
outputs are high-ohmic
f = 5 MHz; note 6
60
−
−
dB
f = 10 MHz; note 6
50
−
−
dB
f = 22 MHz; note 6
40
−
−
dB
f = 5 MHz; note 6
−60
−
−
dB
f = 10 MHz; note 6
−50
−
−
dB
f = 22 MHz; note 6
−40
−
−
dB
gain reduction −0.5 dB
5
−
−
MHz
gain reduction −1 dB
10
−
−
MHz
gain reduction −3 dB
22
−
−
MHz
−
−
20
ns
CT
B
td
crosstalk between the two RGB
channels
bandwidth of the RGB channels
delay from RGB input to output
February 1995
CL = 20 pF; note 6
note 6
16
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
SYMBOL
PARAMETER
TDA8310
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FAST BLANKING OUTPUT (PIN 5)
VOH
HIGH level output voltage
2
−
3
V
VOL
LOW level output voltage
0
−
0.3
V
ZO
output impedance
−
−
300
Ω
ZO(off)
output impedance in the “off” state
100
−
−
kΩ
tr
rise time of the output pulse
−
−
30
ns
tf
fall time of the output pulse
−
−
30
ns
td
delay difference between fast
blanking and RGB at the outputs
−
−
30
ns
Iload
maximum load current
−
−
1
mA
Notes
1. On set AGC.
2. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
3. Measured with 0 dB = 500 µV.
4. Measured at 10 mV RMS top sync input signal.
5. So called projected zero point, i.e. with switched demodulator.
6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
7. Measured with a source impedance of 75 Ω, where:
V O (black-to-white)
S/N = 20 log --------------------------------------------------------V m ( rms ) ( B = 5 MHz )
8. When the leakage current of the capacitor exceeds this value it will result in a reduced performance of the AGC
(amplitude variation during line or frame up to 20% maximum) but it will not result in a hang-up situation.
9. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
10. Burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mV (p-p).
11. The IC has two 3-level switch control inputs for the selection of the video signal for the decoder and synchronization
circuits. The video source for internal or external signal is selected via pin 32, also the polarity of the demodulation
for the internal signal. When the video switch is in the external position the voltage level of pin 9 determines whether
the video filters are switched to CVBS or Y/C. It is also possible via pin 9 to select an automatic detection of the
Y/C signal.
12. This value is internally generated when the pin is left open-circuit (the minimum value of the series resistor is 25 kΩ).
13. The −3 dB bandwidth of the circuit can be calculated by means of the following equation:
1
f –3 dB = f osc  1 – -------- 
2Q
14. Slicing level is independent of sync pulse amplitude.
15. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync
pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given
is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync
is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 µs.
February 1995
17
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
16. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time
constant is switched to ‘slow’ when excessive noise is present in the signal. This occurs when the internal video
signal is selected or for an external CVBS signal when the chrominance input (pin 16) is left open-circuit. The time
constant is always ‘fast’ when the chrominance input pin is connected to ground and the input is switched to the Y/C
mode. In the ‘fast’ mode during the vertical retrace time the phase detector current is increased 50% so that phase
errors due to head-switching of the VCR are corrected as soon as possible.
During weak signal conditions (noise detector active) the phase detector is gated and the width of the gate pulse has
a value of 5.7 µs so that the effect of the noise is reduced to a minimum.
The output current of the phase detector for the various conditions is shown in Table 1.
17. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
This divider circuit has 2 search modes of operation:
a) The ‘large window’ mode is switched on when the circuit is not synchronized or, when a non-standard signal is
received (the number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode
between 261 and 264). In the search mode the divider can be triggered between line 244 and line 361
(approximately 45 to 64.5 Hz)
b) The ‘narrow window’ mode is switched on when more than 15 successive vertical sync pulses are detected in the
narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the
vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very
small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses
are found within the window.
18. To obtain a simple interface between the TDA8310 and the PIP processor the sandcastle output has been designed
such that the output is pulled down during scan and pulled up during the burst key pulse. During blanking the output
is high-ohmic and therefore the output voltage is determined by the load.
19. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)) as given in Characteristics first parameter of Section “Chrominance input (pin 16)” the dynamic range
of the ACC is +6 and −20 dB.
20. All frequency variations are referenced to 3.58/4.43 MHz carrier frequency. All oscillator specifications are measured
with the Philips crystal series 9922 520. If the spurious response of the 4.43 MHz crystal is lower than −3 dB with
respect to the fundamental frequency for a damping resistance of 1 kΩ, oscillation at the fundamental frequency is
guaranteed. The spurious response of the 3.58 MHz crystal must be lower than −3 dB with respect to the
fundamental frequency for a damping resistance of 1.5 kΩ. The catching and detuning range are measured for
nominal crystal parameters. These are:
a) load resonance frequency f0 (CL = 20 pF) = 4.433619 or 3.579545 MHz
b) motional capacitance CM = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal)
c) parallel capacitance C0 = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal).
The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off
chip.
The free-running frequency of the oscillator can be checked by the HUE control pin to the positive supply rail. In that
condition the colour killer is not active so that the frequency off-set is visible on the screen. When two or more crystals
are connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator
continuously switching between the various frequencies.
21. The crystal pins which are not used must be connected to the positive supply line via an 8.2 kΩ resistor. It is also
possible to connect the non-used pins together and use a resistor with a value of 8.2 kΩ divided by the number of
pins which are not used.
22. When this pin is left open-circuit the HUE control is set to the nominal value.
23. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter.
The bandwidth of the demodulator low-pass filter is approximately 1 MHz.
February 1995
18
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
24. The reference signal for the TDA8395 is available only when the crystal oscillator is operating at a frequency of
4.43 MHz. When a SECAM signal is identified this signal is only available during the vertical retrace period thus
avoiding crosstalk with the incoming SECAM signal during scan.
25. The identified colour standard can be read from the IC in two ways:
a) From the voltage level of pin 4. The voltage during the demodulation of the various standards is given in the last
three parameters of this section.
b) From the pins 23 to 26 when pin 27 is in the “read” mode.
When pin 27 is in the “write” mode the colour decoder can be forced to one of the colour standards. The levels for
the various standards are given in Tables 2, 3 and 4.
26. When one or more pins have to be connected to the positive supply line the total current must be limited to 40 µA.
This can be achieved by connecting these pins together and connecting them to a positive supply line via a 100 kΩ
resistor. When separate resistors are used a resistor with a higher value must be used so that the total current is
limited to the required level.
27. The output of pin 4 is designed similar to the sandcastle output. The output is pulled down during PAL and pulled up
during SECAM. During NTSC the pin is floating so that the output level is determined by the load.
28. The control possibilities of the RGB switch via pins 13 and 52 are shown in Table 5.
29. This output signal value is obtained when the CVBS or Y input signal at pins 17 and/or 20 has an amplitude of 0.7 V
(black-to-white value).
30. The output buffer consists of a combination of a PMOS and an NMOS. The maximum output impedance in the low
state can be calculated by dividing the maximum output voltage (for this parameter 0.9 V) by the specified current.
For the high state this resistance can be calculated by dividing the difference between the maximum and minimum
output voltage by the specified current. The output impedance is independent of the value of the output current.
31. These output signal values are obtained for a colour bar input signal with 75% saturation.
Table 1 Output current of phase detector
CURRENT PHASE
SCAN
DETECTOR
(µA)
DURING
VERTICAL
RETRACE
(µA)
30
Table 4 Crystal logic (pins 23 and 24)
GATED
YES/NO
Weak signal and
synchronized
30
YES
(5.7 µs)
Strong signal and
synchronized
180
270
NO
Not synchronized
180
270
NO
PIN 24
LOW
LOW
4.43
LOW
HIGH
3.579 (NTSC)
HIGH
LOW
3.575 (PAL-M)
HIGH
HIGH
3.582 (PAL-N)
Table 5 Control logic RGB switch (pins 13 and 52)
PIN 13
PIN 52
RGB
OUTPUT
FAST
BLANKING
OUTPUT
LOW
LOW
black
LOW
Table 2 Read/write pin input (pin 27)
MODE
LEVEL
Decoder automatic
LOW
Forced decoder mode
HIGH
Table 3 Colour system logic (pins 25 and 26)
PIN 25
PIN 26
LOW
LOW
auto/no colour
LOW
HIGH
PAL
HIGH
LOW
NTSC
HIGH
HIGH
SECAM
February 1995
SELECTED CRYSTAL
(MHz)
PIN 23
STANDARD
19
LOW
HIGH
RGB 2
HIGH
HIGH
LOW
RGB 1
HIGH
HIGH
HIGH
RGB 2
HIGH
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
MBE018
handbook, halfpage
40
(deg)
20
0
20
40
0
1
2
3
4
(V)
5
Fig.3 HUE control curve.
February 1995
20
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
PACKAGE OUTLINE
15.80
15.24
seating plane
47.92
47.02
handbook, full pagewidth
4.57 5.08
max max
3.2
2.8
0.51
min
1.73
max
0.53
max
1.778
(25x)
0.18 M
0.32 max
15.24
17.15
15.90
1.3 max
MSA267
52
27
14.1
13.7
1
26
Dimensions in mm.
Fig.4 Plastic shrink dual in-line package; 52 leads; 600 mil (SDIP52, SOT247-1).
SOLDERING
REPAIRING SOLDERED JOINTS
Plastic dual in-line packages
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
February 1995
21
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
February 1995
22
Philips Semiconductors
Preliminary specification
PAL/NTSC colour processor for
PIP applications
TDA8310
NOTES
February 1995
23
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Tel. (022)74 8000, Fax. (022)74 8341
Philips Semiconductors
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KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546.
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For all other countries apply to: Philips Semiconductors,
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SCD36
© Philips Electronics N.V. 1994
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Document order number:
Date of release: February 1995
9397 746 60011