74F543 Octal latched transceiver with dual enable; 3-state Rev. 04 — 26 January 2010 Product data sheet 1. General description The 74F543 octal latched transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA. 2. Features n n n n n n n Combines 74F245 and 74F373 type functions in one device 8-bit octal transceiver with D-type latch Back-to-back registers for storage Separate controls for data flow in each direction A output capability: +20 mA to −3 mA B output capability: +64 mA to −15 mA 3-state outputs for bus-oriented applications 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version N74F543D 0 °C to +70 °C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 N74F543DB 0 °C to +70 °C SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 4. Functional diagram 3 4 5 6 7 8 9 2 23 1 13 11 14 10 11 A0 A1 A2 A3 A4 A5 A6 A7 EAB 23 EBA OEAB 13 3 14 LEAB OEBA 2 4 1 LEBA B0 B1 B2 B3 B4 B5 B6 B7 22 21 20 19 18 17 16 15 001aae900 1EN3 (BA) G1 1C5 2EN4 (AB) G2 2C6 3 5D 2 6D 22 21 5 20 6 19 7 18 8 17 9 16 10 15 001aae901 Fig 1. Logic symbol Fig 2. OEBA IEC logic symbol 2 13 EBA LEBA 23 11 1 14 DETAIL A D 22 Q OEAB EAB LEAB B0 LE A0 3 Q D LE 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 21 20 19 18 17 16 15 DETAIL A × 7 B1 B2 B3 B4 B5 B6 B7 001aae902 Fig 3. Logic diagram 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 2 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 5. Pinning information 5.1 Pinning 74F543 LEBA 1 24 VCC OEBA 2 23 EBA A0 3 22 B0 A1 4 21 B1 A2 5 20 B2 A3 6 19 B3 A4 7 18 B4 A5 8 17 B5 A6 9 16 B6 A7 10 15 B7 EAB 11 14 LEAB GND 12 13 OEAB 001aal173 Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description Unit load HIGH/LOW Load value[1] HIGH/LOW LEBA 1 B-to-A latch enable input (active LOW) 1.0/1.0 20 µA/0.6 mA OEBA 2 B-to-A output enable input (active LOW) 1.0/1.0 20 µA/0.6 mA A0 to A7 3, 4, 5, 6, 7, 8, 9, data input or output 10 inputs 3.5/1.0; outputs 150/40 inputs 70 µA/0.6 mA; outputs 3.0 mA/24 mA EAB 11 1.0/2.0 20 µA/1.2 mA A-to-B enable input (active LOW) GND 12 ground (0 V) OEAB 13 A-to-B output enable input (active LOW) 1.0/1.0 20 µA/0.6 mA LEAB 14 A-to-B latch enable input (active LOW) 1.0/1.0 20 µA/0.6 mA B0 to B7 22, 21, 20, 19, 18, 17, 16, 15 data input or output inputs 3.5/1.0; inputs 70 µA/0.6 mA; outputs 750/106.7 outputs 15 mA/64 mA EBA 23 B-to-A enable input (active LOW) 1.0/2.0 VCC 24 positive supply voltage [1] 20 µA/1.2 mA One FAST Unit Load (UL) is defined as 20 µA in HIGH state, 0.6 µA in LOW state. 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 3 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 6. Functional description 6.1 Function table Table 3. Function selection[1] Input Output OEXX EXX LEXX An or Bn Bn or An H X X X Z X H X X Z L ↑ L h Z l Z L L L L L [1] L ↑ L H h H l L H H L L X NC Status disabled disabled + latch latch + display transparent hold H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA); L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA); ↑ = LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA); NC = no change; X = don’t care; Z = high-impedance OFF-state. 6.2 Description The 74F543 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the A-to-B latch enable (LEAB) input and the A-to-B output latch enable (OEAB) are all LOW, the A-to-B path is transparent. A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-state B output buffers are active and display the data present at the outputs of the A latches. Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs. 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 4 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Conditions +7.0 V −0.5 +7.0 V [1] −0.5 +5.5 V −30 +5 mA pins A0 to A7 - 48 mA pins B0 to B7 - 128 mA 0 70 °C −65 +150 °C input voltage output voltage output in HIGH-state IIK input clamping current VI < 0 V IO output current output in LOW-state Tstg storage temperature Unit −0.5 VI ambient temperature Max [1] VO Tamb Min [2] in free air [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage 4.5 5.0 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IIK input clamping current - - −18 mA IOH HIGH-level output current pins A0 to A7 −3 - - mA pins B0 to B7 −15 - - mA pins A0 to A7 - - 24 mA pins B0 to B7 - - 64 mA IOL LOW-level output current Conditions 74F543_4 Product data sheet Min Typ Max Unit © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 5 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 9. Static characteristics Table 6. Static characteristics Symbol Parameter 25 °C Conditions 0 °C to 70 °C Unit Min Typ[1] Max Min Max −1.2 −0.73 - −1.2 - V VCC = ±10 % - - - 2.4 - V VCC = ±5 % - 3.4 - 2.7 - V VCC = ±10 % - - - 2.0 - V VCC = ±5 % - - - 2.0 - V VCC = ±10 % - 0.35 - - 0.5 V VCC = ±5 % - 0.35 - - 0.5 V VIK input clamping voltage VCC = 4.5 V; IIK = −18 mA VOH HIGH-level output voltage VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0 V pins A0 to A7; IOH = −3 mA pins B0 to B7; IOH = −15 mA LOW-level output voltage VOL VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0 V pins A0 to A7; IOL = 24 mA pins B0 to B7; IOL = 64 mA VCC = ±10 % - - - - 0.55 V VCC = ±5 % - 0.42 - - 0.55 V pins OEAB, OEBA, EAB; VI = 7.0 V - - - - 100 µA other pins; VI = 5.5 V - - - - 1 mA IIH HIGH-level input current VCC = 5.5 V; VI = 2.7 V - - - - 20 µA IIL LOW-level input current input leakage current II VCC = 5.5 V VCC = 5.5 V; VI = 0.5 V pins EAB, EBA - - - - −1.2 mA other pins - - - - −0.6 mA - - - - 70 µA - - - - −600 µA pins A0 to A7 - −60 - - −150 mA pins B0 to B7 - −100 - - −225 mA outputs HIGH-state - 70 - - 105 mA outputs LOW-state - 95 - - 135 mA outputs OFF-state - 95 - - 135 mA OFF-state output current VCC = 5.5 V IOZ VO = 2.7 V; VI = 2.0 V VO = 0.5 V; VI = 0.8 V output current IO supply current ICC [2] VCC = 5.5 V VCC = 5.5 V [1] All typical values are measured at VCC = 5 V. [2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 6 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 10. Symbol Parameter tPLH tPHL LOW to HIGH propagation delay HIGH to LOW propagation delay 25 °C; VCC = 5.0 V Conditions 0 °C to 70 °C; Unit VCC = 5.0 V ± 0.5 V Min Typ Max Min Max An to Bn; see Figure 5 3.5 5.5 8.5 3.0 9.0 ns Bn to An; see Figure 5 2.5 4.0 7.0 2.5 7.5 ns LEBA to An; see Figure 6 5.0 7.0 10.0 4.5 11.0 ns LEAB to Bn; see Figure 6 6.0 8.5 11.5 5.5 12.5 ns An to Bn; see Figure 5 3.0 5.0 8.0 2.5 8.5 ns Bn to An; see Figure 5 2.5 4.5 7.5 2.5 8.0 ns LEBA to An; see Figure 6 4.0 6.0 9.0 4.0 9.5 ns LEAB to Bn; see Figure 6 4.5 6.5 9.5 4.0 10.0 ns OFF-state to HIGH propagation delay OEBA to An, OEAB to Bn; see Figure 7 2.0 4.0 7.5 1.5 8.0 ns EBA to An, EAB to Bn; see Figure 7 4.5 7.0 10.5 4.0 11.5 ns tPZL OFF-state to LOW propagation delay OEBA to An, OEAB to Bn; see Figure 8 3.5 5.0 8.5 3.0 9.0 ns EBA to An, EAB to Bn; see Figure 8 5.0 7.0 10.5 4.5 11.0 ns tPHZ HIGH to OFF-state propagation delay OEBA to An, OEAB to Bn; see Figure 7 1.0 3.0 6.5 1.0 7.5 ns EBA to An, EAB to Bn; see Figure 7 2.5 5.0 8.5 2.0 9.5 ns tPLZ LOW to OFF-state propagation delay OEBA to An, OEAB to Bn; see Figure 8 1.5 4.0 7.5 1.0 8.5 ns EBA to An, EAB to Bn; see Figure 8 4.5 7.0 11.0 3.0 12.0 ns tsu(H) set-up time HIGH An to LEAB, Bn to LEBA; see Figure 9 0.0 - - 0.0 - ns An to EAB, Bn to EBA; see Figure 9 1.0 - - 1.5 - ns An to LEAB, Bn to LEBA; see Figure 9 2.5 - - 3.0 - ns An to EAB, Bn to EBA; see Figure 9 2.5 - - 3.0 - ns An to LEAB, Bn to LEBA; see Figure 9 0.0 - - 0.0 - ns An to EAB, Bn to EBA; see Figure 9 0.0 - - 0.0 - ns An to LEAB, Bn to LEBA; see Figure 9 1.5 - - 2.0 - ns tPZH tsu(L) set-up time LOW th(H) hold time HIGH th(L) hold time LOW tWL pulse width LOW An to EAB, Bn to EBA; see Figure 9 1.5 - - 2.0 - ns latch enable; see Figure 9 4.0 - - 4.5 - ns 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 7 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 11. Waveforms VI An or Bn VM VM GND tPLH tPHL VOH Bn or An VM VM VOL 001aae904 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay input (An, Bn) to output (Bn, An) VI LEBA, LEAB VM VM GND tPLH tPHL VOH VM An, Bn VM VOL 001aac761 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) VI OEAB, OEBA, EAB, EBA VM VM GND tPZH tPHZ VOH An, Bn VM VOH − 0.3 V GND 001aae907 VM = 1.5 V VOH is a typical voltage output level that occurs with the output load. Fig 7. Propagation delay 3-state output enable to HIGH-level and output disable from HIGH-level 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 8 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state VI OEAB, OEBA, EAB, EBA GND VM VM tPZL tPLZ 3.5 V An, Bn VM VOL + 0.3 V VOL 001aae906 VM = 1.5 V VOL is a typical voltage output level that occurs with the output load. Fig 8. Propagation delay 3-state output enable to LOW-level and output disable from LOW-level VI An, Bn VM VM VM VM GND tsu(H) th(H) tsu(L) th(L) tWL VI LEAB, LEBA, VM EAB, EBA GND VM 001aae905 VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times and latch enable pulse width 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 9 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state VI tW 90 % 90 % negative pulse VM 0V VCC 10 % tf tr tr tf VI 90 % positive pulse 0V VEXT VM 10 % VI RL VO G DUT RT 90 % CL RL VM VM 10 % mna616 10 % tW 001aai298 a. Input pulse definition b. Test circuit Test data is given in Table 8. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Load circuitry for switching times Table 8. Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 10 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT137-1 (SO24) 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 11 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 12. Package outline SOT340-1 (SSOP24) 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 12 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 13. Abbreviations Table 9. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74F543_4 20100126 Product data sheet - 74F543_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and.Section 12 “Package outline” 74F543_3 20040722 Product specification - 74F543_544_2 74F543_544_2 19941205 Product specification - - 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 13 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74F543_4 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 04 — 26 January 2010 14 of 15 74F543 NXP Semiconductors Octal latched transceiver with dual enable; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 26 January 2010 Document identifier: 74F543_4