PHILIPS 74ABT543ADB

74ABT543A
Octal latched transceiver with dual enable; 3-state
Rev. 03 — 26 January 2010
Product data sheet
1. General description
The 74ABT543A high performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT543A octal registered transceiver contains two sets of D-type latches for
temporary storage of data flowing in either direction. Separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) inputs are provided for each register to permit
independent control of data transfer in either direction. The outputs are guaranteed to sink
64 mA.
2. Features
n
n
n
n
n
n
n
n
n
n
Combines 74ABT245 and 74ABT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Live insertion and extraction permitted
Output capability: +64 mA to −32 mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
u HBM JESD22-A114F exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74ABT543AD
−40 °C to +85 °C
SO24
plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
74ABT543ADB
−40 °C to +85 °C
SSOP24
plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74ABT543APW
−40 °C to +85 °C
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
4. Functional diagram
3
4
5
6
7
8
9
2
23
1
13
11
14
10
11
A0 A1 A2 A3 A4 A5 A6 A7
EAB
23
EBA
OEAB
13
3
14
LEAB
OEBA
2
4
1
LEBA
B0 B1 B2 B3 B4 B5 B6 B7
22 21 20 19 18 17 16 15
001aae900
1EN3 (BA)
G1
1C5
2EN4 (AB)
G2
2C6
3
5D
2
6D
22
21
5
20
6
19
7
18
8
17
9
16
10
15
001aae901
Fig 1.
Logic symbol
Fig 2.
OEBA
IEC logic symbol
2
13
EBA
LEBA
23
11
1
14
DETAIL A
D
22
Q
OEAB
EAB
LEAB
B0
LE
A0
3
Q
D
LE
4
A1
5
A2
6
A3
7
A4
8
A5
9
A6
10
A7
21
20
19
18
17
16
15
DETAIL A × 7
B1
B2
B3
B4
B5
B6
B7
001aae902
Fig 3.
Logic diagram
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
2 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
5. Pinning information
5.1 Pinning
74ABT543A
LEBA
1
24 VCC
OEBA
2
23 EBA
A0
3
22 B0
A1
4
21 B1
A2
5
20 B2
A3
6
19 B3
A4
7
18 B4
A5
8
17 B5
A6
9
16 B6
A7 10
15 B7
EAB 11
14 LEAB
GND 12
13 OEAB
001aae899
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
LEBA
1
B-to-A latch enable input (active LOW)
OEBA
2
B-to-A output enable input (active LOW)
A0 to A7
3, 4, 5, 6, 7, 8, 9, 10
data input or output
EAB
11
A-to-B enable input (active LOW)
GND
12
ground (0 V)
OEAB
13
A-to-B output enable input (active LOW)
LEAB
14
A-to-B latch enable input (active LOW)
B0 to B7
22, 21, 20, 19, 18, 17, 16, 15
data input or output
EBA
23
B-to-A enable input (active LOW)
VCC
24
positive supply voltage
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
3 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
6. Functional description
6.1 Function table
Table 3.
Function selection[1]
Input
Output
OEXX
EXX
LEXX
An or Bn
Bn or An
H
X
X
X
Z
X
H
X
X
Z
L
↑
L
h
Z
l
Z
L
L
L
L
L
[1]
L
↑
L
H
h
H
l
L
H
H
L
L
X
NC
Status
disabled
disabled + latch
latch + display
transparent
hold
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
↑ = LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
6.2 Description
The 74ABT543A contains two sets of eight D-type latches, with separate control pins for
each set.
Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the
A-to-B latch enable (LEAB) input and the A-to-B output enable (OEAB) input are all LOW,
the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A inputs. With EAB and
OEAB both LOW, the 3-state B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs.
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
4 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
−0.5
+7.0
V
[1]
−1.2
+7.0
V
[1]
−0.5
+5.5
V
VI
input voltage
VO
output voltage
output in OFF-state or HIGH-state
IIK
input clamping current
VI < 0 V
−18
-
mA
IOK
output clamping current
VO < 0 V
−50
-
mA
IO
output current
output in LOW-state
Tj
junction temperature
Tstg
storage temperature
[2]
-
128
mA
-
150
°C
−65
+150
°C
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Typ
Max
Unit
4.5
-
5.5
V
VI
input voltage
0
-
VCC
V
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
IOH
HIGH-level output current
−32
-
-
mA
IOL
LOW-level output current
-
-
64
mA
∆t/∆V
input transition rise and fall rate
0
-
10
ns/V
Tamb
ambient temperature
−40
-
+85
°C
in free air
9. Static characteristics
Table 6.
Static characteristics
Symbol
Parameter
25 °C
Conditions
−40 °C to +85 °C Unit
Min
Typ
Max
Min
Max
VIK
input clamping voltage VCC = 4.5 V; IIK = −18 mA
−1.2
−0.9
-
−1.2
-
V
VOH
HIGH-level output
voltage
VCC = 4.5 V; IOH = −3 mA
2.5
3.2
-
2.5
-
V
VCC = 5.0 V; IOH = −3 mA
3.0
3.7
-
3.0
-
V
VCC = 4.5 V; IOH = −32 mA
VI = VIL or VIH
2.0
2.3
-
2.0
-
V
VOL
LOW-level output
voltage
VCC = 4.5 V; IOL = 64 mA;
VI = VIL or VIH
-
0.3
0.55
-
0.55
V
VOL(pu)
power-up LOW-level
output voltage
VCC = 5.5 V; IO = 1 mA;
VI = GND or VCC
-
0.13
0.55
-
0.55
V
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
5 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
Table 6.
Static characteristics …continued
Symbol
Parameter
II
25 °C
Conditions
input leakage current
−40 °C to +85 °C Unit
Min
Typ
Max
Min
Max
-
±0.01
±1.0
-
±1.0
VCC = 5.5 V; VI = GND or 5.5 V
OEAB, OEBA
An, Bn
VCC = 0.0 V; VI or VO ≤ 4.5 V
IOFF
power-off leakage
current
IO(pu/pd)
power-up/power-down VCC = 2.1 V; VO = 0.5 V;
output current
VI = GND or VCC;
OEAB, OEBA don’t care
IOZ
OFF-state output
current
[1]
µA
-
±5.0
±100
-
±100
µA
-
±5.0
±100
-
±100
µA
-
±5.0
±50
-
±50
µA
-
5.0
50
-
50
µA
VCC = 5.5 V; VI = VIL or VIH
VO = 2.7 V
-
−5.0
−50
-
−50
µA
-
5.0
50
-
50
µA
−180
−65
−40
−180
−40
mA
outputs HIGH-state
-
110
250
-
250
µA
outputs LOW-state
-
20
30
-
30
mA
-
110
250
-
250
µA
-
0.3
1.5
-
1.5
mA
VO = 0.5 V
ILO
output leakage current HIGH-state; VO = 5.5 V;
VCC = 5.5 V; VI = GND or VCC
IO
output current
VCC = 5.5 V; VO = 2.5 V
ICC
supply current
VCC = 5.5 V; VI = GND or VCC
[2]
outputs disabled
∆ICC
additional supply
current
per input pin; VCC = 5.5 V;
one input pin at 3.4 V, other inputs
at VCC or GND
CI
input capacitance
VI = 0 V or VCC
-
4
-
-
-
pF
CI/O
input/output
capacitance
outputs disabled; VO = 0 V or VCC
-
7
-
-
-
pF
[3]
[1]
This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 %,
a transition time of up to 100 ms is permitted.
[2]
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[3]
This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter
25 °C; VCC = 5.0 V
Conditions
−40 °C to +85 °C; Unit
VCC = 5.0 V ± 0.5 V
Min
Typ
Max
Min
Max
tPLH
LOW to HIGH
propagation delay
An to Bn or Bn to An; see Figure 5
1.0
2.9
4.5
1.0
5.2
ns
LEBA to An or LEAB to Bn; see Figure 6
1.0
3.4
5.1
1.0
6.2
ns
tPHL
HIGH to LOW
propagation delay
An to Bn or Bn to An; see Figure 5
1.9
3.6
5.2
1.9
5.7
ns
LEBA to An or LEAB to Bn; see Figure 6
2.1
4.3
6.0
2.1
6.7
ns
OFF-state to HIGH
propagation delay
OEBA to An, OEAB to Bn; see Figure 7
1.0
3.2
5.1
1.0
6.2
ns
EBA to An, EAB to Bn; see Figure 7
1.0
3.4
5.1
1.0
6.2
ns
tPZH
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
6 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
Table 7.
Dynamic characteristics …continued
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter
tPZL
tPHZ
tPLZ
tsu(H)
tsu(L)
th(H)
th(L)
tWL
25 °C; VCC = 5.0 V
Conditions
−40 °C to +85 °C; Unit
VCC = 5.0 V ± 0.5 V
Min
Typ
Max
Min
Max
OFF-state to LOW
propagation delay
OEBA to An, OEAB to Bn; see Figure 8
2.0
4.3
5.9
2.0
6.6
ns
EBA to An, EAB to Bn; see Figure 8
2.0
4.4
6.1
2.0
6.8
ns
HIGH to OFF-state
propagation delay
OEBA to An, OEAB to Bn; see Figure 7
2.0
4.0
5.7
2.0
6.2
ns
EBA to An, EAB to Bn; see Figure 7
2.0
3.6
5.4
2.0
5.9
ns
LOW to OFF-state
propagation delay
OEBA to An, OEAB to Bn; see Figure 8
1.0
3.0
4.6
1.0
5.0
ns
EBA to An, EAB to Bn; see Figure 8
1.0
3.0
4.6
1.0
5.0
ns
set-up time HIGH
An to LEAB, Bn to LEBA; see Figure 9
2.5
1.0
-
2.5
-
ns
An to EAB, Bn to EBA; see Figure 9
3.5
1.3
-
3.5
-
ns
set-up time LOW
hold time HIGH
hold time LOW
pulse width LOW
An to LEAB, Bn to LEBA; see Figure 9
3.0
1.4
-
3.0
-
ns
An to EAB, Bn to EBA; see Figure 9
3.0
1.4
-
3.0
-
ns
LEAB to An, LEBA to Bn; see Figure 9
+0.5
−0.8
-
0.5
-
ns
EAB to An, EBA to Bn; see Figure 9
+0.5
−0.8
-
0.5
-
ns
LEAB to An, LEBA to Bn; see Figure 9
+0.5
−0.6
-
0.5
-
ns
EAB to An, EBA to Bn; see Figure 9
+0.5
−0.6
-
0.5
-
ns
latch enable; see Figure 9
3.5
1.0
-
3.5
-
ns
11. Waveforms
VI
An or Bn
VM
VM
GND
tPLH
tPHL
VOH
Bn or An
VM
VM
VOL
001aae904
VM = 1.5 V.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5.
Propagation delay input (An, Bn) to output (Bn, An)
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
7 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
VI
LEAB or LEBA
VM
VM
GND
tPHL
tPLH
VOH
VM
An or Bn
VM
VOL
001aae903
VM = 1.5 V.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Propagation delay latch enable (LEAB, LEBA) to output (An, Bn)
VI
OEAB, OEBA,
EAB, EBA
VM
VM
GND
tPZH
tPHZ
VOH
An, Bn
VOH − 0.3 V
VM
GND
001aae907
VM = 1.5 V.
VOH is a typical voltage output level that occurs with the output load.
Fig 7.
Propagation delay 3-state output enable to HIGH-level and output disable from HIGH-level
VI
OEAB, OEBA,
EAB, EBA
GND
VM
VM
tPZL
tPLZ
3.5 V
An, Bn
VM
VOL + 0.3 V
VOL
001aae906
VM = 1.5 V.
VOL is a typical voltage output level that occurs with the output load.
Fig 8.
Propagation delay 3-state output enable to LOW-level and output disable from LOW-level
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
8 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
VI
VM
An, Bn
VM
VM
VM
GND
tsu(H)
th(H)
tsu(L)
th(L)
tWL
VI
LEAB, LEBA,
VM
VM
EAB, EBA
GND
001aae905
VM = 1.5 V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9.
Data set-up and hold times and latch enable pulse width
VI
tW
90 %
90 %
negative
pulse
VM
0V
VCC
tf
tr
tr
tf
VI
VI
RL
VO
G
DUT
RT
90 %
positive
pulse
0V
VEXT
VM
10 %
CL
RL
VM
VM
10 %
mna616
10 %
tW
001aac221
a. Input pulse definition
b. Test circuit
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 10. Load circuitry for switching times
Table 8.
Test data
Input
Load
VEXT
VI
fI
tW
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
3.0 V
1 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω
open
open
7.0 V
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
9 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.61
0.60
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT137-1
075E05
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 11. Package outline SOT137-1 (SO24)
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
10 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
D
SOT340-1
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.8
0.4
8
o
0
o
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT340-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 12. Package outline SOT340-1 (SSOP24)
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
11 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 13. Package outline SOT355-1 (TSSOP24)
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
12 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
13. Abbreviations
Table 9.
Abbreviations
Acronym
Description
BiCMOS
Bipolar Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
14. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ABT543A_3
20100126
Product data sheet
-
74ABT543A_2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and.Section
12 “Package outline”
74ABT543A_2
19980924
Product specification
-
74ABT543A_1
74ABT543A_1
19950419
Product specification
-
-
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
13 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74ABT543A_3
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 03 — 26 January 2010
14 of 15
74ABT543A
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 26 January 2010
Document identifier: 74ABT543A_3