INTEGRATED CIRCUITS 74ALVT16373 2.5V/3.3V 16-bit transparent D-type latch (3-State) Product specification Supersedes data of 1998 Feb 13 IC23 Data Handbook 1999 Oct 18 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) FEATURES 74ALVT16373 DESCRIPTION • 16-bit transparent latch • 5V I/O compatibile • 3-State buffers • Output capability: +64mA/-32mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up The 74ALVT16373 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V. This device is a 16-bit transparent D-type latch with non-inverting 3-State bus compatible outputs. The device can be used as two 8-bit latches or one 16-bit latch. When latch enable (LE) input is High, the Q outputs follow the data (D) inputs. When latch enable is taken Low, the Q outputs are latched at the levels of the D inputs one setup time prior to the High-to-Low transition. resistors to hold unused inputs • Live insertion/extraction permitted • Power-up reset • Power-up 3-State • No bus current loading when output is tied to 5V bus • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C PARAMETER tPLH tPHL Propagation delay nDx to nQx CL = 50pF CIN TYPICAL UNIT 2.5V 3.3V 2.0 2.4 1.6 1.8 ns Input capacitance VI = 0V or VCC 3 3 pF COUT Output capacitance Outputs disabled; VO = 0V or 3.0V 9 9 pF ICCZ Total supply current Outputs disabled 40 70 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT16373 DL AV16373 DL SOT370-1 48-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT16373 DGG AV16373 DGG SOT362-1 1999 Oct 18 2 853-1842 22536 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) LOGIC SYMBOL 47 LOGIC SYMBOL (IEEE/IEC) 46 44 43 41 40 38 37 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1LE 1 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2 3 36 35 5 33 6 32 8 30 9 29 11 27 12 2LE 24 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 13 14 16 17 19 20 22 23 SA00044 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 47, 46, 44, 43, 41, 40, 38, 37, 36, 35, 33, 32, 30, 29, 27, 26 1D0 – 1D7 2D0 – 2D7 Data inputs 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 16, 17, 19, 20, 22, 23 1Q0 – 1Q7 2Q0 – 2Q7 Data outputs 1, 24 48, 25 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 1OE, 2OE 1LE, 2LE GND VCC 1OE 1 1EN 1LE 48 C3 2OE 24 2EN 2LE 25 C4 1D1 47 3D 2 1Q1 1D2 46 3 1Q2 1D3 44 5 1Q3 1D4 43 6 1Q4 1D5 41 8 1Q5 1D6 40 9 1Q6 1D7 38 11 1Q7 1D8 37 12 1Q8 2D1 36 13 2Q1 2D2 35 14 2Q2 2D3 33 16 2Q3 2D4 32 17 2Q4 2D5 30 19 2Q5 2D6 29 20 2Q6 2D7 27 22 2Q7 2D8 26 23 2Q8 26 2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7 25 74ALVT16373 4D 1∇ 2∇ SW00010 PIN CONFIGURATION Output enable inputs (active-Low) Enable inputs (active-High) Ground (0V) Positive supply voltage 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE SA00043 1999 Oct 18 3 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) 74ALVT16373 LOGIC DIAGRAM nD0 nD1 D E nD2 D Q E nD3 D Q E nD4 D Q nD5 D E Q E nD6 D Q nD7 D E Q E D Q E Q nLE nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 SA00046 FUNCTION TABLE INPUTS H = h = L = l = NC= X = Z = ↓ = INTERNAL OUTPUTS nOE nLE nDx REGISTER nQ0 – nQ7 L L H H L H L H L H Enable and read register L L ↓ ↓ l h L H L H Latch and read register L L X NC NC H H L H X nDx NC nDx Z Z High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don’t care High impedance “off ” state High-to-Low E transition 1999 Oct 18 4 OPERATING MODE Hold Disable outputs Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) 74ALVT16373 ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC IIK RATING UNIT –0.5 to +4.6 V –50 mA –0.5 to +7.0 V VO < 0 –50 mA Output in Off or High state –0.5 to +7.0 V Output in Low state 128 Output in High state –64 DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current VOUT CONDITIONS DC output voltage3 IOUT O DC output current mA Tstg Storage temperature range –65 to +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC 2.5V RANGE LIMITS PARAMETER DC supply voltage 3.3V RANGE LIMITS UNIT MIN MAX MIN MAX 2.3 2.7 3.0 3.6 V 0 5.5 0 5.5 V VI Input voltage VIH High-level input voltage VIL Input voltage 0.7 0.8 V IOH High-level output current –8 –32 mA Low-level output current 8 32 Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 24 64 ∆t/∆v Input transition rise or fall rate; Outputs enabled 10 10 ns/V Tamb Operating free-air temperature range +85 °C IOL 1999 Oct 18 1.7 –40 5 2.0 +85 –40 V mA Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) 74ALVT16373 DC ELECTRICAL CHARACTERISTICS (3.3V "0.3V RANGE) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK VOH VOL VRST Input clamp voltage VCC = 3.0V; IIK = –18mA High-level out output ut voltage Low–level out output ut voltage Power-up output low voltage6 VCC = 3.0 to 3.6V; IOH = –100µA VCC = 3.0V; IOH = –32mA Input In ut leakage current IHOLD Off current –0.85 –1.2 VCC–0.2 VCC 2.0 2.3 0.07 0.2 0.25 0.4 VCC = 3.0V; IOL = 32mA 0.3 0.5 VCC = 3.0V; IOL = 64mA 0.4 0.55 VCC = 3.6V; IO = 1mA; VI = VCC or GND ±1 VCC = 0 or 3.6V; VI = 5.5V 0.1 10 VCC = 3.6V; VI = VCC 0.5 1 Data pins ins4 VCC = 3V; VI = 0.8V Bus Hold current V V 0.55 0.1 Control pins VCC = 0V; VI or VO = 0 to 4.5V Data inputs7 UNIT V VCC = 3.0V; IOL = 16mA VCC = 3.6V; VI = 0V IOFF MAX VCC = 3.0V; IOL = 100µA VCC = 3.6V; VI = VCC or GND II TYP1 0.1 -5 0.1 ±100 75 130 VCC = 3V; VI = 2.0V –75 –140 VCC = 0V to 3.6V; VCC = 3.6V ±500 V µA µA µA Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 3.0V 10 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don’t care 1 ±100 µA IOZH 3-State output High current VCC = 3.6V; VO = 3.0V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 3.6V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 0.04 0.1 IEX IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 3.5 5 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05 0.05 0.1 VCC = 3V to 3.6V; One input at VCC–0.6V, Other inputs at VCC or GND 0.04 0.4 mA mA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. This is the bus hold overdrive current required to force the input to the opposite logic state. AC CHARACTERISTICS (3.3V "0.3V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V "0.3V WAVEFORM UNIT MIN TYP1 MAX tPLH tPHL Propagation delay nDx to nQx 2 0.5 0.5 1.6 1.8 2.5 2.9 ns tPLH tPHL Propagation delay nLE to nQx 1 1.0 1.0 2.0 2.3 3.1 3.3 ns tPZH tPZL Output enable time to High and Low level 4 5 1.5 1.0 2.3 1.9 4.0 3.1 ns tPHZ tPLZ Output disable time from High and Low Level 4 5 1.5 1.5 2.9 2.3 4.5 3.7 ns NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 1999 Oct 18 6 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) 74ALVT16373 DC ELECTRICAL CHARACTERISTICS (2.5V "0.2V RANGE) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK Input clamp voltage VCC = 2.3V; IIK = –18mA VOH High-level out output ut voltage VOL output Low-level out ut voltage VRST Power-up output low voltage7 VCC = 2.3 to 3.6V; IOH = –100µA Input In ut leakage current MAX –0.85 –1.2 UNIT V VCC–0.2 VCC = 2.3V; IOH = –8mA V 1.8 VCC = 2.3V; IOL = 100µA 0.07 0.2 VCC = 2.3V; IOL = 24mA 0.3 0.5 VCC = 2.7V; IO = 1mA; VI = VCC or GND 0.55 0.1 ±1 VCC = 0 or 2.7V; VI = 5.5V 0.1 10 VCC = 2.7V; VI = VCC 0.1 1 VCC = 2.7V; VI = VCC or GND II TYP1 Control pins Data pins ins4 VCC = 2.7V; VI = 0 V µA 0.1 -5 Off current VCC = 0V; VI or VO = 0 to 4.5V 0.1 "100 Bus Hold current VCC = 2.3V; VI = 0.7V 90 Data inputs6 VCC = 2.3V; VI = 1.7V –10 Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 2.3V 10 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don’t care 1 100 µA IOZH 3-State output High current VCC = 2.7V; VO = 2.3V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 2.7V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0 0.04 0.1 VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0 2.3 4.5 VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO = 05 0.04 0.1 VCC = 2.3V to 2.7V; One input at VCC–0.6V, Other inputs at VCC or GND 0.04 0.4 IOFF IHOLD IEX IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 µA µA mA mA NOTES: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V ± 0.2V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. Not guaranteed. 7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. AC CHARACTERISTICS (2.5V "0.2V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 2.5V "0.2V WAVEFORM UNIT MIN TYP1 MAX tPLH tPHL Propagation delay nDx to nQx 2 1.0 1.0 2.0 2.4 3.2 4.2 ns tPLH tPHL Propagation delay nLE to nQx 1 1.5 1.5 2.6 2.8 4.2 4.5 ns tPZH tPZL Output enable time to High and Low level 4 5 2.0 1.5 3.5 2.6 5.5 4.7 ns tPHZ tPLZ Output disable time from High and Low Level 4 5 1.5 1.0 2.7 2.0 4.5 3.5 ns NOTE: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. 1999 Oct 18 7 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) 74ALVT16373 AC SETUP REQUIREMENTS GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V MIN TYP MIN TYP UNIT tS(H) tS(L) Setup time nDx to nLE 3 0 1.5 –0.7 0.2 0.5 0.8 –0.2 0.2 ns th(H) th(L) Hold time nDx to nLE 3 0.5 1.5 –0.2 0.7 0.8 1.0 0 0.2 ns tW(H) nLE pulse width High 1 1.5 1.5 AC WAVEFORMS 1.5 1.5 ns ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ For all waveforms VM = 1.5V for VCC w 3.0V; VM = VCC/2 for VCC v 2.7V VM = 1.5V for VCC w 3.0V; VM = VCC/2 for VCC v 2.7V VX = VOL + 0.3V for VCC w 3.0V; VX = VOL + 0.15V for VCC v 2.7V VY = VOH – 0.3V for VCC w 3.0V; VY = VOH – 0.15V for VCC v 2.7V nDx 3.0V or VCC whichever is less VM VM ts(H) VM VM ts(L) th(H) 3.0V or VCC whichever is less nLE nLE VM VM VM 3.0V or VCC whichever is less VM VM 0V NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. 0V tw(H) tPHL 0V th(L) SW00165 Waveform 3. Data Setup and Hold Times tPLH VOH nQx VM VM VOL nOE SW00163 Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width VM 3.0V or VCC whichever is less VM 0V tPZH tPHZ VOH nQx nDx VM VX VM 3.0V or VCC whichever is less VM 0V SW00166 0V tPLH Waveform 4. 3-State Output Enable time to High Level and Output Disable Time from High Level tPHL VOH nQx VM VM 3.0V or VCC whichever is less VOL nOE SW00164 VM VM Waveform 2. Propagation Delay for Data to Outputs 0V tPZL tPLZ 3.0V or VCC nQx VM VY VOL SW00167 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1999 Oct 18 8 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) 74ALVT16373 TEST CIRCUIT AND WAVEFORMS 6V or VCC x 2 VCC OPEN VIN VOUT PULSE GENERATOR RL GND tW 90% CL 10% 10% 0V RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs GND tPLZ/tPZL 6V or VCC x 2 tPLH/tPHL open 10% 0V VM = 1.5V or VCC / 2, whichever is less Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. VM VM tW SWITCH tPHZ/tPZH AMP (V) 90% 10% SWITCH POSITION TEST AMP (V) VM VM NEGATIVE PULSE D.U.T. RT 90% 74ALVT16 RT = Termination resistance should be equal to ZOUT of pulse generators. Amplitude Rep. Rate tW tR 3.0V or VCC whichever is less ≤10MHz 500ns ≤2.5ns tF ≤2.5ns SW00162 1999 Oct 18 9 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm 1999 Oct 18 10 74ALVT16373 SOT370-1 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm 1999 Oct 18 11 74ALVT16373 SOT362-1 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) 74ALVT16373 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1999 Oct 18 12 Date of release: 10-99 9397-750-06516