PHILIPS P89LPC9408FBD

P89LPC9408
8-bit microcontroller with two-clock 80C51 core 8 kB 3 V
byte-erasable flash, 32 segment × 4 LCD driver, 10-bit ADC
Rev. 01 — 16 December 2005
Product data sheet
1. General description
The P89LPC9408 is a multi-chip module consisting of a P89LPC938 single-chip
microcontroller combined with a PCF8576D universal LCD controller in a low-cost 64-pin
package. The LCD controller provides 32 segments and supports from 1 to 4 backplanes.
Display overhead is minimized by an on-chip display RAM with auto-increment
addressing.
2. Features
2.1 Principal features
■ 8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.
Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
■ 256-byte RAM data memory.
■ 512-byte customer Data EEPROM on chip allows serialization of devices, storage of
set-up parameters, etc.
■ 32 segment × 4 backplane LCD controller supports from 1 to 4 backplanes.
■ 8-input multiplexed 10-bit ADC. Two analog comparators with selectable inputs and
reference source.
■ Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as a Real-Time Clock (RTC).
■ Enhanced UART with fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
■ CCU provides PWM, input capture, and output compare functions.
■ High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable.
■ 64-pin LQFP package with 20 microcontroller I/O pins minimum and up to 23
microcontroller I/O pins while using on-chip oscillator and reset options.
2.2 Additional features
■ 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
■ Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
■ Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
■ In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application.
■ Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
■ Low voltage detect (brownout) allows a graceful system shutdown when power fails.
May optionally be configured as an interrupt.
■ Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 9 µA typical (total power-down with voltage comparators disabled).
■ Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available.
■ Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
■ Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
■ Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
■ LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
■ Only power and ground connections are required to operate the P89LPC9408 when
internal reset option is selected.
■ Four interrupt priority levels.
■ Eight keypad interrupt inputs, plus two additional external interrupt inputs.
■ Schmitt trigger port inputs.
■ Second data pointer.
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
2 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
3. Ordering information
Table 1:
Ordering information
Type number
Package
P89LPC9408FBD
Name
Description
Version
LQFP64
plastic low profile quad flat package; 64 leads;
body 14 × 14 × 1.4 mm
SOT791-1
3.1 Ordering options
Table 2:
Part options
Type number
Flash memory
Temperature range
Frequency
P89LPC9408FBD
8 kB
−40 °C to +85 °C
0 MHz to 18 MHz
4. Block diagram
P3[1:0]
S[31:0]
P2.5, P2[3:0]
BP[3:0]
PCF8576D
P89LPC938
LCD
CONTROLLER
MCU
P1[7:0]
VLCD
P0[7:0]
A[2:0] SA0 OSC
002aab775
SCL, SDA
SCL_LCD, SDA_LCD
Fig 1. Block diagram
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
3 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
P89LPC938
ACCELERATED 2-CLOCK 80C51 CPU
8 kB
CODE FLASH
internal
bus
256-BYTE
DATA RAM
UART
TXD
RXD
I2C-BUS
SCL
SDA
SPICLK
MOSI
MISO
SS
SPI
512-BYTE
AUXILIARY RAM
REAL-TIME CLOCK/
SYSTEM TIMER
512-BYTE
DATA EEPROM
T0
T1
TIMER 0
TIMER 1
PORT 3
CONFIGURABLE I/Os
P3[1:0]
P2[7:0]
PORT 2
CONFIGURABLE I/Os
P1[7:0]
PORT 1
CONFIGURABLE I/Os
P0[7:0]
PORT 0
CONFIGURABLE I/Os
CMP2
ANALOG
COMPARATORS
CIN2A
CIN1A
OCA
CCU (CAPTURE/
COMPARE UNIT)
OCC
ICA
AD00
AD02
KEYPAD
INTERRUPT
ADC0
AD04
AD06
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
CRYSTAL
OR
RESONATOR
X1
X2
CMP1
CIN1B
OCB
OCD
ICB
AD01
AD03
AD05
AD07
CPU
clock
ON-CHIP
RC
OSCILLATOR
CONFIGURABLE
OSCILLATOR
CIN2B
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aab106
Fig 2. Microcontroller section block diagram
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
4 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
BP0 BP1 BP2 BP3
S0 TO S39
BACKPLANE
OUTPUTS
DISPLAY SEGMENT OUTPUTS
VDD
LCD
VOLTAGE
SELECTOR
DISPLAY LATCH
LCD BIAS
GENERATOR
VLCD
CLK
SHIFT REGISTER
TIMING
BLINKER
SYNC
DISPLAY
CONTROLLER
OSC
POWERON
RESET
OSCILLATOR
SCL
DISPLAY
RAM
40 × 4 BITS
OUTPUT
BANK
SELECTOR
DATA
POINTER
COMMAND
DECODER
VSS
SDA
INPUT
BANK
SELECTOR
INPUT
FILTERS
I2C-BUS
CONTROLLER
SUBADDRESS
COUNTER
SA0
A0 A1 A2
002aab470
Fig 3. LCD display controller block diagram
5. Functional diagram
VDD
AD05
AD00
AD01
AD02
AD03
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
CLKOUT
XTAL2
VSS
PORT 0
PORT 1
P89LPC9408
PORT 3
XTAL1
PORT 2
TXD
RXD
T0
INT0
INT1
RST
OCB
OCC
ICB
OCD
MOSI
MISO
SS
SPICLK
OCA
ICA
SCL
SDA
AD04
AD07
AD06
002aab776
Fig 4. P89LPC9408 functional diagram
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
5 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
6. Pinning information
49 S18
50 S19
51 S20
52 S21
53 S22
54 S23
55 S24
56 S25
57 S26
58 S27
59 S28
60 S29
61 S30
62 S31
63 SDA_LCD
64 SCL_LCD
6.1 Pinning
P0.5/CMPREF/KBI5
1
48 S17
P0.4/CIN1A/KBI4/AD03
2
47 S16
P0.3/CIN1B/KBI3/AD02
3
46 S15
P0.2/CIN2A/KBI2/AD01
4
45 S14
P0.1/CIN2B/KBI1/AD00
5
44 S13
P2.0/ICB/AD07
6
43 S12
P2.1/OCD/AD06
7
42 S11
P0.0/CMP2/KBI0/AD05
8
P1.7/OCC/AD04
9
41 S10
P89LPC9408
40 S9
S1 32
S0 31
BP3 30
BP1 29
BP2 28
BP0 27
VLCD 26
VDD 25
P0.6/CMP1/KBI6 24
33 S2
P0.7/T1/KBI7 23
34 S3
P1.3/INT0/SDA 16
P1.0/TXD 22
35 S4
P1.4/INT1 15
P1.1/RXD 21
36 S5
P3.0/XTAL2/CLKOUT 14
P2.5/SPICLK 20
37 S6
P3.1/XTAL1 13
P2.3/MISO 19
38 S7
VSS 12
P2.2/MOSI 18
39 S8
P1.5/RST 11
P1.2/T0/SCL 17
P1.6/OCB 10
002aab777
Fig 5. Pin configuration
6.2 Pin description
Table 3:
Pin description
Symbol
Pin
P0.0 to P0.7
Type Description
I/O
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 7.13.1 “Port
configurations” and Table 12 “Static electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt trigger inputs.
Port 0 also provides various special functions as described below:
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
6 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Table 3:
Pin description …continued
Symbol
Pin
Type Description
P0.0/CMP2/
KBI0/AD05
8
I/O
P0.0 — Port 0 bit 0.
O
CMP2 — Comparator 2 output.
I
KBI0 — Keyboard input 0.
P0.1/CIN2B/
KBI1/AD00
P0.2/CIN2A/
KBI2/AD01
P0.3/CIN1B/
KBI3/AD02
P0.4/CIN1A/
KBI4/AD03
5
4
3
2
P0.5/
CMPREF/
KBI5
1
P0.6/CMP1/
KBI6
24
P0.7/T1/KBI7
23
I
AD05 — ADC0 channel 5 analog input.
I/O
P0.1 — Port 0 bit 1.
I
CIN2B — Comparator 2 positive input B.
I
KBI1 — Keyboard input 1.
I
AD00 — ADC0 channel 0 analog input.
I/O
P0.2 — Port 0 bit 2.
I
CIN2A — Comparator 2 positive input A.
I
KBI2 — Keyboard input 2.
I
AD01 — ADC0 channel 1 analog input.
I/O
P0.3 — Port 0 bit 3.
I
CIN1B — Comparator 1 positive input B.
I
KBI3 — Keyboard input 3.
I
AD02 — ADC0 channel 2 analog input.
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input A.
I
KBI4 — Keyboard input 4.
I
AD03 — ADC0 channel 3 analog input.
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
I/O
P0.6 — Port 0 bit 6.
O
CMP1 — Comparator 1 output.
I
KBI6 — Keyboard input 6.
I/O
P0.7 — Port 0 bit 7.
I/O
T1 — Timer/counter 1 external count input or overflow output.
I
KBI7 — Keyboard input 7.
I/O, I Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three
[1]
pins as noted below. During reset Port 1 latches are configured in the input only mode
with the internal pull-up disabled. The operation of the configurable Port 1 pins as
inputs and outputs depends upon the port configuration selected. Each of the
configurable port pins are programmed independently. Refer to Section 7.13.1 “Port
configurations” and Table 12 “Static electrical characteristics” for details. P1.2 and P1.3
are open drain when used as outputs. P1.5 is input only.
P1.0 to P1.7
All pins have Schmitt trigger inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD
P1.1/RXD
22
21
I/O
P1.0 — Port 1 bit 0.
O
TXD — Transmitter output for the serial port.
I/O
P1.1 — Port 1 bit 1.
I
RXD — Receiver input for the serial port.
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
7 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Table 3:
Pin description …continued
Symbol
Pin
Type Description
P1.2/T0/SCL
17
I/O
P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O
T0 — Timer/counter 0 external count input or overflow output (open-drain when used
as output).
I/O
SCL — I2C-bus serial clock input/output.
I/O
P1.3 — Port 1 bit 3 (open-drain when used as output).
I
INT0 — External interrupt 0 input.
I/O
SDA — I2C-bus serial data input/output.
P1.3/INT0/
SDA
P1.4/INT1
P1.5/RST
P1.6/OCB
P1.7/OCC/
AD04
16
15
11
10
9
P2.0 to P2.3,
P2.5
I
P1.4 — Port 1 bit 4.
I
INT1 — External interrupt 1 input.
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
When using an oscillator frequency above 12 MHz, the reset input function of
P1.5 must be enabled. An external circuit is required to hold the device in reset at
power-up until VDD has reached its specified level. When system power is
removed VDD will fall below the minimum specified operating voltage. When
using an oscillator frequency above 12 MHz, in some applications, an external
brownout detect circuit may be required to hold the device in reset when VDD falls
below the minimum specified operating range.
I/O
P1.6 — Port 1 bit 6.
O
OCB — Output Compare B.
I/O
P1.7 — Port 1 bit 7.
O
OCC — Output Compare C.
I
AD04 — ADC0 channel 4 analog input.
I/O
Port 2: Port 2 is an 5-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 2 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 7.13.1 “Port
configurations” and Table 12 “Static electrical characteristics” for details.
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0/ICB/
AD07
P2.1/OCD/
AD06
P2.2/MOSI
P2.3/MISO
6
7
18
19
I/O
P2.0 — Port 2 bit 0.
I
ICB — Input Capture B.
I
AD07 — ADC0 channel 7 analog input.
I/O
P2.1 — Port 2 bit 1.
O
OCD — Output Compare D.
I
AD06 — ADC0 channel 6 analog input.
I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When configured as master, this pin is output; when
configured as slave, this pin is input.
I/O
P2.3 — Port 2 bit 3.
I/O
MISO — When configured as master, this pin is input, when configured as slave, this
pin is output.
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
8 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Table 3:
Pin description …continued
Symbol
Pin
Type Description
P2.5/SPICLK
20
I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — SPI clock. When configured as master, this pin is output; when configured
as slave, this pin is input.
I/O
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 3 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 7.13.1 “Port
configurations” and Table 12 “Static electrical characteristics” for details.
P3.0 to P3.1
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT
P3.1/XTAL1
14
13
I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the flash configuration.
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source for
the RTC/system timer.
I/O
P3.1 — Port 3 bit 1.
I
XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the flash configuration). It can be a port pin if internal RC oscillator or
watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used
to generate the clock for the RTC/system timer.
SDA_LCD
63
I/O
SDA LCD — I2C-bus data signal for the LCD controller.
SCL_LCD
64
I
SCL LCD — I2C-bus clock signal for the LCD controller.
BP0 to BP3
27 to 30
O
BP0 to BP3: LCD backplane outputs.
S0 to S31
31 to 62
O
S0 to S31: LCD segment outputs
VSS
12
I
Ground: 0 V reference.
VDD
25
I
Power supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
VLCD
26
I
LCD power supply: LCD supply voltage.
[1]
Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
9 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7. Functional description
Remark: Please refer to the P89LPC9408 User manual for a more detailed functional
description.
7.1 Special function registers
Remark: SFR accesses are restricted in the following ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.
– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
10 of 69
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Philips Semiconductors
P89LPC9408_1
Product data sheet
Table 4:
Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit address
Bit functions and addresses
Reset value
MSB
E7
LSB
E6
E5
E4
E3
E2
E1
Hex
Binary
00
0000 0000
E0
Accumulator
E0H
AD0CON
ADC0 control
register
97H
ENBI0
ENADCI0
TMM0
EDGE0
ADCI0
ENADC0
ADCS01
ADCS00
00
0000 0000
AD0INS
ADC0 input select
A3H
ADI07
ADI06
ADI05
ADI04
ADI03
ADI02
ADI01
ADI00
00
0000 0000
AD0MODA ADC0 mode
register A
C0H
BNDI0
BURST0
SCC0
SCAN0
-
-
-
-
00
0000 0000
AD0MODB ADC0 mode
register B
A1H
CLK2
CLK1
CLK0
-
-
-
-
-
00
000x 0000
AUXR1
A2H
CLKLP
EBRR
ENT1
ENT0
SRST
0
-
DPS
00
0000 00x0
F7
F6
F5
F4
F3
F2
F1
F0
Auxiliary function
register
Bit address
B register
F0H
00
0000 0000
BRGR0 [1]
Baud rate generator
rate low
BEH
00
0000 0000
BRGR1 [1]
Baud rate generator
rate high
BFH
00
0000 0000
BRGCON
Baud rate generator
control
BDH
-
-
-
-
-
-
SBRGS
BRGEN
00 [1]
xxxx xx00
CCCRA
Capture compare A
control register
EAH
ICECA2
ICECA1
ICECA0
ICESA
ICNFA
FCOA
OCMA1
OCMA0
00
0000 0000
CCCRB
Capture compare B
control register
EBH
ICECB2
ICECB1
ICECB0
ICESB
ICNFB
FCOB
OCMB1
OCMB0
00
0000 0000
CCCRC
Capture compare C
control register
ECH
-
-
-
-
-
FCOC
OCMC1
OCMC0
00
xxxx x000
CCCRD
Capture compare D
control register
EDH
-
-
-
-
-
FCOD
OCMD1
OCMD0
00
xxxx x000
CMP1
Comparator 1
control register
ACH
-
-
CE1
CP1
CN1
OE1
CO1
CMF1
00 [2]
xx00 0000
CMP2
Comparator 2
control register
ADH
-
-
CE2
CP2
CN2
OE2
CO2
CMF2
00 [2]
xx00 0000
DEECON
Data EEPROM
control register
F1H
EEIF
HVERR
ECTL1
ECTL0
-
-
-
EADR8
0E
0000 1110
P89LPC9408
11 of 69
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
B*
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Rev. 01 — 16 December 2005
ACC*
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
DEEDAT
Data EEPROM data
register
F2H
00
0000 0000
DEEADR
Data EEPROM
address register
F3H
00
0000 0000
DIVM
CPU clock
divide-by-M control
95H
00
0000 0000
DPTR
Data pointer
(2 bytes)
83H
00
0000 0000
Data pointer low
82H
00
0000 0000
FMADRH
Program flash
address high
E7H
00
0000 0000
FMADRL
Program flash
address low
E6H
00
0000 0000
FMCON
Program flash
control (Read)
E4H
70
0111 0000
Program flash
control (Write)
E4H
FMDATA
Program flash data
E5H
00
0000 0000
I2ADR
I2C
slave address
register
DBH
00
0000 0000
I2CON*
I2C
control register
D8H
00
x000 00x0
I2DAT
I2C
data register
DAH
I2SCLH
Serial clock
generator/SCL duty
cycle register high
DDH
00
0000 0000
I2SCLL
Serial clock
generator/SCL duty
cycle register low
DCH
00
0000 0000
I2STAT
I2C status register
D9H
F8
1111 1000
ICRAH
Input capture A
register high
ABH
00
0000 0000
Bit address
-
-
-
HVA
HVE
SV
OI
FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0
12 of 69
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
I2ADR.6
I2ADR.5
I2ADR.4
I2ADR.3
I2ADR.2
I2ADR.1
I2ADR.0
GC
DF
DE
DD
DC
DB
DA
D9
D8
-
I2EN
STA
STO
SI
AA
-
CRSEL
STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0
P89LPC9408
Data pointer high
DPL
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Rev. 01 — 16 December 2005
DPH
BUSY
Philips Semiconductors
P89LPC9408_1
Product data sheet
Table 4:
Special function registers …continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
ICRAL
Input capture A
register low
AAH
00
0000 0000
ICRBH
Input capture B
register high
AFH
00
0000 0000
ICRBL
Input capture B
register low
AEH
00
0000 0000
00
0000 0000
Bit address
Interrupt enable 0
IEN1*
Interrupt enable 1
A8H
Bit address
Rev. 01 — 16 December 2005
IEN2
Interrupt enable 2
E8H
D5H
Bit address
AF
AE
AD
AC
AB
AA
A9
A8
EA
EWDRT
EBO
ES/ESR
ET1
EX1
ET0
EX0
EF
EE
ED
EC
EB
EA
E9
E8
EIEE
EST
-
ECCU
ESPI
EC
EKBI
EI2C
00 [2]
00x0 0000
00 [2]
00x0 0000
-
-
-
-
-
-
EADC
-
BF
BE
BD
BC
BB
BA
B9
B8
IP0*
Interrupt priority 0
B8H
-
PWDRT
PBO
PS/PSR
PT1
PX1
PT0
PX0
00 [2]
x000 0000
IP0H
Interrupt priority 0
high
B7H
-
PWDRTH
PBOH
PSH/
PSRH
PT1H
PX1H
PT0H
PX0H
00 [2]
x000 0000
FF
FE
FD
FC
FB
FA
F9
F8
Bit address
IP1*
Interrupt priority 1
F8H
PADEE
PST
-
PCCU
PSPI
PC
PKBI
PI2C
00 [2]
00x0 0000
IP1H
Interrupt priority 1
high
F7H
PADEEH
PSTH
-
PCCUH
PSPIH
PCH
PKBIH
PI2CH
00 [2]
00x0 0000
IP2
Interrupt priority 2
D6H
-
-
-
-
-
-
PADC
-
00 [2]
00x0 0000
00x0 0000
Interrupt priority 2
high
D7H
-
-
-
-
-
-
PADCH
-
KBCON
Keypad control
register
94H
-
-
-
-
-
-
PATN
_SEL
KBIF
00 [2]
xxxx xx00
KBMASK
Keypad interrupt
mask register
86H
00
0000 0000
KBPATN
Keypad pattern
register
FF
1111 1111
OCRAH
Output compare A
register high
EFH
00
0000 0000
OCRAL
Output compare A
register low
EEH
00
0000 0000
P89LPC9408
13 of 69
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
IP2H
00 [2]
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
IEN0*
Philips Semiconductors
P89LPC9408_1
Product data sheet
Table 4:
Special function registers …continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
Output compare B
register high
FBH
00
0000 0000
OCRBL
Output compare B
register low
FAH
00
0000 0000
OCRCH
Output compare C
register high
FDH
00
0000 0000
OCRCL
Output compare C
register low
FCH
00
0000 0000
OCRDH
Output compare D
register high
FFH
00
0000 0000
OCRDL
Output compare D
register low
FEH
00
0000 0000
P0*
Port 0
80H
Bit address
P1*
Port 1
90H
Bit address
P2*
Port 2
A0H
Bit address
87
86
85
84
83
82
81
80
T1/KB7
CMP1
/KB6
CMPREF/
KB5
CIN1A
/KB4
CIN1B
/KB3
CIN2A
/KB2
CIN2B
/KB1
CMP2
/KB0
97
96
95
94
93
92
91
90
OCC
OCB
RST
INT1
INT0/SDA
T0/SCL
RXD
TXD
97
96
95
94
93
92
91
90
ICA
OCA
SPICLK
SS
MISO
MOSI
OCD
ICB
B7
B6
B5
B4
B3
B2
B1
B0
[2]
[2]
[2]
[2]
Port 3
B0H
-
-
-
-
-
-
XTAL1
XTAL2
P0M1
Port 0 output
mode 1
84H
(P0M1.7)
(P0M1.6)
(P0M1.5)
(P0M1.4)
(P0M1.3)
(P0M1.2)
(P0M1.1)
(P0M1.0)
FF [2]
1111 1111
P0M2
Port 0 output
mode 2
85H
(P0M2.7)
(P0M2.6)
(P0M2.5)
(P0M2.4)
(P0M2.3)
(P0M2.2)
(P0M2.1)
(P0M2.0)
00 [2]
0000 0000
P1M1
Port 1 output
mode 1
91H
(P1M1.7)
(P1M1.6)
-
(P1M1.4)
(P1M1.3)
(P1M1.2)
(P1M1.1)
(P1M1.0)
D3 [2]
11x1 xx11
P1M2
Port 1 output
mode 2
92H
(P1M2.7)
(P1M2.6)
-
(P1M2.4)
(P1M2.3)
(P1M2.2)
(P1M2.1)
(P1M2.0)
00 [2]
00x0 xx00
P2M1
Port 2 output
mode 1
A4H
(P2M1.7)
(P2M1.6)
(P2M1.5)
(P2M1.4)
(P2M1.3)
(P2M1.2)
(P2M1.1)
(P2M1.0)
FF [2]
1111 1111
P2M2
Port 2 output
mode 2
A5H
(P2M2.7)
(P2M2.6)
(P2M2.5)
(P2M2.4)
(P2M2.3)
(P2M2.2)
(P2M2.1)
(P2M2.0)
00 [2]
0000 0000
P89LPC9408
14 of 69
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
P3*
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Rev. 01 — 16 December 2005
OCRBH
Bit address
Philips Semiconductors
P89LPC9408_1
Product data sheet
Table 4:
Special function registers …continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
xxxx xx11
B1H
-
-
-
-
-
-
(P3M1.1)
(P3M1.0)
P3M2
Port 3 output
mode 2
B2H
-
-
-
-
-
-
(P3M2.1)
(P3M2.0)
00 [2]
xxxx xx00
PCON
Power control
register
87H
SMOD1
SMOD0
BOPD
BOI
GF1
GF0
PMOD1
PMOD0
00
0000 0000
PCONA
Power control
register A
B5H
RTCPD
DEEPD
VCPD
ADPD
I2PD
SPPD
SPD
CCUPD
00 [2]
0000 0000
D7
D6
D5
D4
D3
D2
D1
D0
PSW*
Program status
word
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
00
0000 0000
PT0AD
Port 0 digital input
disable
F6H
-
-
PT0AD.5
PT0AD.4
PT0AD.3
PT0AD.2
PT0AD.1
-
00
xx00 000x
RSTSRC
Reset source
register
DFH
-
-
BOF
POF
R_BK
R_WD
R_SF
R_EX
[3]
RTCCON
RTC control
D1H
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
60 [2] [4] 011x xx00
RTCH
RTC register high
D2H
00 [4]
0000 0000
RTCL
RTC register low
D3H
00 [4]
0000 0000
SADDR
Serial port address
register
A9H
00
0000 0000
SADEN
Serial port address
enable
B9H
00
0000 0000
SBUF
Serial Port data
buffer register
99H
xx
xxxx xxxx
9F
9E
9D
9C
9B
9A
99
98
SCON*
Serial port control
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
00
0000 0000
SSTAT
Serial port extended
status register
BAH
DBMOD
INTLO
CIDIS
DBISEL
FE
BR
OE
STINT
00
0000 0000
SP
Stack pointer
81H
07
0000 0111
SPCTL
SPI control register
E2H
SSIG
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
04
0000 0100
SPSTAT
SPI status register
E1H
SPIF
WCOL
-
-
-
-
-
-
00
00xx xxxx
SPDAT
SPI data register
E3H
00
0000 0000
Rev. 01 — 16 December 2005
15 of 69
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Bit address
P89LPC9408
Port 3 output
mode 1
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
P3M1
03 [2]
Bit address
Philips Semiconductors
P89LPC9408_1
Product data sheet
Table 4:
Special function registers …continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
TAMOD
Description
SFR
addr.
Timer 0 and 1
auxiliary mode
8FH
Bit address
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
00
xxx0 xxx0
-
-
-
T1M2
-
-
-
T0M2
8F
8E
8D
8C
8B
8A
89
88
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00
0000 0000
TCR20*
CCU control
register 0
C8H
PLEEN
HLTRN
HLTEN
ALTCD
ALTAB
TDIR2
TMOD21
TMOD20
00
0000 0000
TCR21
CCU control
register 1
F9H
TCOU2
-
-
-
PLLDV.3
PLLDV.2
PLLDV.1
PLLDV.0
00
0xxx 0000
TH0
Timer 0 high
8CH
00
0000 0000
TH1
Timer 1 high
8DH
00
0000 0000
TH2
CCU timer high
CDH
00
0000 0000
TICR2
CCU interrupt
control register
C9H
TOIE2
TOCIE2D
TOCIE2C
TOCIE2B
TOCIE2A
-
TICIE2B
TICIE2A
00
0000 0x00
TIFR2
CCU interrupt flag
register
E9H
TOIF2
TOCF2D
TOCF2C
TOCF2B
TOCF2A
-
TICF2B
TICF2A
00
0000 0x00
TISE2
CCU interrupt
status encode
register
DEH
-
-
-
-
-
ENCINT.2
ENCINT.1
ENCINT.0 00
xxxx x000
TL0
Timer 0 low
8AH
00
0000 0000
TL1
Timer 1 low
8BH
00
0000 0000
TL2
CCU timer low
CCH
00
0000 0000
TMOD
Timer 0 and 1 mode
89H
00
0000 0000
TOR2H
CCU reload register
high
CFH
00
0000 0000
TOR2L
CCU reload register
low
CEH
00
0000 0000
TPCR2H
Prescaler control
register high
CBH
TPCR2L
Prescaler control
register low
CAH
TRIM
Internal oscillator
trim register
96H
-
T1C/T
-
T1M1
-
T1M0
-
T0GATE
-
T0C/T
-
T0M1
TPCR2H.
1
T0M0
TPCR2H. 00
0
TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0 00
RCCLK
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
xxxx xx00
0000 0000
[4] [5]
P89LPC9408
16 of 69
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Timer 0 and 1
control
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Rev. 01 — 16 December 2005
TCON*
T1GATE
Philips Semiconductors
P89LPC9408_1
Product data sheet
Table 4:
Special function registers …continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
WDCON
Watchdog control
register
A7H
WDL
Watchdog load
C1H
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
Bit functions and addresses
Reset value
MSB
PRE2
LSB
PRE1
PRE0
Philips Semiconductors
P89LPC9408_1
Product data sheet
Table 4:
Special function registers …continued
* indicates SFRs that are bit addressable.
-
-
WDRUN
WDTOF
Hex
Binary
[4] [6]
WDCLK
FF
1111 1111
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[2]
All ports are in input only (high-impedance) state after power-up.
[3]
The RSTSRC register reflects the cause of the P89LPC9408 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx11 0000.
[4]
The only reset source that affects these SFRs is power-on reset.
[5]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
P89LPC9408
17 of 69
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Rev. 01 — 16 December 2005
[1]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors
P89LPC9408_1
Product data sheet
Table 5:
P89LPC938 extended special function registers
Description
SFR addr.
Bit functions and addresses
Hex
Binary
ADC0HBND
ADC0 high _boundary register, left
(MSB)
FFEFH
FF
1111 1111
ADC0LBND
ADC0 low_boundary register (MSB)
FFEEH
00
0000 0000
AD0DAT0R
ADC0 data register 0, right (LSB)
FFFEH
AD0DAT0[7:0]
00
0000 0000
AD0DAT0L
ADC0 data register 0, left (MSB)
FFFFH
AD0DAT0[9:2]
00
0000 0000
AD0DAT1R
ADC0 data register 1, right (LSB)
FFFCH
AD0DAT1[7:0]
00
0000 0000
AD0DAT1L
ADC0 data register 1, left (MSB)
FFFDH
AD0DAT1[9:2]
00
0000 0000
AD0DAT2R
ADC0 data register 2, right (LSB)
FFFAH
AD0DAT2[7:0]
00
0000 0000
AD0DAT2L
ADC0 data register 2, left (MSB)
FFFBH
AD0DAT2[9:2]
00
0000 0000
AD0DAT3R
ADC0 data register 3, right (LSB)
FFF8H
AD0DAT3[7:0]
00
0000 0000
AD0DAT3L
ADC0 data register 3, left (MSB)
FFF9H
AD0DAT3[9:2]
00
0000 0000
AD0DAT4R
ADC0 data register 4, right (LSB)
FFF6H
AD0DAT4[7:0]
00
0000 0000
AD0DAT4L
ADC0 data register 4, left (MSB)
FFF7H
AD0DAT4[9:2]
00
0000 0000
AD0DAT5R
ADC0 data register 5, right (LSB)
FFF4H
AD0DAT5[7:0]
00
0000 0000
AD0DAT5L
ADC0 data register 5, left (MSB)
FFF5H
AD0DAT5[9:2]
00
0000 0000
AD0DAT6R
ADC0 data register 6, right (LSB)
FFF2H
AD0DAT6[7:0]
00
0000 0000
AD0DAT6L
ADC0 data register 6, left (MSB)
FFF3H
AD0DAT6[9:2]
00
0000 0000
AD0DAT7R
ADC0 data register 7, right (LSB)
FFF0H
AD0DAT7[7:0]
AD0DAT7L
ADC0 data register 7, left (MSB)
FFF1H
AD0DAT7[9:2]
BNDSTA0
ADC0 boundary status register
FFEDH
MSB
Reset value
LSB
P89LPC9408
18 of 69
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Rev. 01 — 16 December 2005
Name
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.2 Enhanced CPU
The P89LPC9408 uses an enhanced 80C51 CPU which runs at six times the speed of
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most
instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock definitions
The P89LPC9408 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources (see Figure 6) and can also be optionally divided to a slower frequency (see
Section 7.8 “CCLK modification: DIVM register”).
Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK⁄2.
7.3.2 CPU clock (OSCCLK)
The P89LPC9408 provides several user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the flash is programmed and include an
on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external
crystal, or an external clock source. The crystal oscillator can be optimized for low,
medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.
7.3.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
7.3.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
7.3.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration. When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
specified level. When system power is removed VDD will fall below the minimum
specified operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating range.
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
19 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.3.6 Clock output
The P89LPC9408 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on XTAL1) and if the RTC is not using the crystal oscillator as its clock
source. This allows external devices to synchronize to the P89LPC9408. This output is
enabled by the ENCLK bit in the TRIM register.
The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering idle, saving additional power.
7.4 On-chip RC oscillator option
The P89LPC9408 has a 6-bit TRIM register that can be used to tune the frequency of the
RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value
to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. End-user
applications can write to the TRIM register to adjust the on-chip RC oscillator to other
frequencies.
7.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
7.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the
P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be
used as a standard port pin or a clock output. When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
specified level. When system power is removed VDD will fall below the minimum
specified operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
XTAL1
XTAL2
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
RTC
ADC0
OSCCLK
RC
OSCILLATOR
DIVM
CCLK
CPU
RCCLK
÷2
(7.3728 MHz ± 1 %)
PCLK
WDT
WATCHDOG
OSCILLATOR
PCLK
(400 kHz +30 % −20 %)
TIMER 0 AND
TIMER 1
I2C-BUS
32 × PLL
SPI
UART
CCU
002aab102
Fig 6. Block diagram of oscillator control
7.7 CPU Clock (CCLK) wake-up delay
The P89LPC9408 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus
60 µs to 100 µs. If the clock source is either the internal RC oscillator, watchdog oscillator,
or external clock, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.
7.8 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.9 Low power select
The P89LPC9408 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is
8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power
consumption further. On any reset, CLKLP is logic 0 allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
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7.10 Memory organization
The various P89LPC9408 memory spaces are as follows:
• DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
• IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
• XDATA
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this
space could be implemented on-chip. The P89LPC9408 has 512 bytes of on-chip
XDATA memory, plus extended SFRs located in XDATA.
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC9408 has 8 kB of on-chip Code memory.
7.11 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 6.
Table 6:
On-chip data memory usages
Type
Data RAM
Size (bytes)
DATA
Memory that can be addressed directly and indirectly
128
IDATA
Memory that can be addressed indirectly
256
XDATA
Auxiliary (‘External Data’) on-chip memory that is accessed
using the MOVX instructions
512
7.12 Interrupts
The P89LPC9408 uses a four priority level interrupt structure. This allows great flexibility
in controlling the handling of the many interrupt sources. The P89LPC9408 supports
16 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port
RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard,
comparators 1 and 2, SPI, CCU, data EEPROM write, and ADC completion.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0, IEN1, or IEN2. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
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Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, IP1H, IP2, and
IP2H. An interrupt service routine in progress can be interrupted by a higher priority
interrupt, but not by another interrupt of the same or lower priority. The highest priority
interrupt service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
7.12.1 External interrupt inputs
The P89LPC9408 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard 80C51
microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC9408 is put into Power-down or Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
Section 7.15 “Power reduction modes” for details.
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IE0
EX0
IE1
EX1
BOF
EBO
RTCF
ERTC
(RTCCON.1)
WDOVF
wake-up
(if in power-down)
KBIF
EKBI
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF0
ET0
TF1
ET1
TI and RI/RI
ES/ESR
TI
EST
interrupt
to CPU
SI
EI2C
SPIF
ESPI
any CCU interrupt
ECCU
EEIF
EIEE
ENADCI0
ADCI0
ENBI1
BNDI1
EADC
002aab104
Fig 7. Interrupt sources, interrupt enables, and power-down wake-up sources
7.13 I/O ports
The P89LPC9408 has four I/O ports: Port 0 and Port 1 are 8-bit ports. Port 2 is a 5-bit
port. Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock
and reset options chosen, as shown in Table 7.
Table 7:
Number of I/O pins available
Clock source
Reset option
Number of I/O pins
(not including LCD
pins)
On-chip oscillator or watchdog oscillator
No external reset (except during power-up)
23
External RST pin supported
22
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Table 7:
Number of I/O pins available …continued
Clock source
Reset option
External clock input
No external reset (except during power-up)
External RST pin
Low/medium/high speed oscillator
(external crystal or resonator)
[1]
Number of I/O pins
(not including LCD
pins)
22
supported [1]
21
No external reset (except during power-up)
External RST pin
21
supported [1]
20
Required for operation above 12 MHz.
7.13.1 Port configurations
All but three I/O port pins on the P89LPC9408 may be configured by software to one of
four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin.
1. P1.5 (RST) can only be an input and cannot be configured.
2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
7.13.1.1
Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
The P89LPC9408 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional
mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD,
causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is
discouraged.
A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.13.1.2
Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to VDD.
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.13.1.3
Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt trigger input that
also has a glitch suppression circuit.
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7.13.1.4
Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a Schmitt
trigger input that also has a glitch suppression circuit.
7.13.2 Port 0 analog functions
The P89LPC9408 incorporates two Analog Comparators. In order to give the best analog
function performance and to minimize power consumption, pins that are being used for
analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input-Only
(high-impedance) mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.
On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.
7.13.3 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different from
the LPC76x series of devices.
• After power-up, all I/O pins except P1.5, may be configured by software.
• Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only or
open-drain.
Every output on the P89LPC9408 has been designed to sink typical LED drive current.
However, there is a maximum total output current for all ports which must not be
exceeded. Please refer to Table 12 “Static electrical characteristics” for detailed
specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
7.14 Power monitoring functions
The P89LPC9408 incorporates power monitoring functions designed to prevent incorrect
operation during initial power-up and power loss or reduction during operation. This is
accomplished with two hardware functions: Power-on detect and Brownout detect.
7.14.1 Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor reset,
however it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If Brownout detection is enabled the brownout condition occurs when VDD falls below the
brownout trip voltage, Vbo (see Table 12 “Static electrical characteristics”), and is negated
when VDD rises above Vbo. If the P89LPC9408 device is to operate with a power supply
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that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device
can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from
operating.
For correct activation of Brownout detect, the VDD rise and fall times must be observed.
Please see Table 12 “Static electrical characteristics” for specifications.
7.14.2 Power-on detection
The Power-on detect has a function similar to the Brownout detect, but is designed to work
as power comes up initially, before the power supply voltage reaches a level where
Brownout detect can work. The POF flag in the RSTSRC register is set to indicate an
initial power-up condition. The POF flag will remain set until cleared by software.
7.15 Power reduction modes
The P89LPC9408 supports three different power reduction modes. These modes are Idle
mode, Power-down mode, and total Power-down mode.
7.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
7.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC9408 exits Power-down mode via any reset, or certain interrupts. In Power-down
mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM.
This retains the RAM contents at the point where Power-down mode was entered. SFR
contents are not guaranteed after VDD has been lowered to VRAM, therefore it is highly
recommended to wake up the processor via reset in this case. VDD must be raised to
within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: Brownout detect,
watchdog timer, Comparators (note that Comparators can be powered-down separately),
and RTC/System Timer. The internal RC oscillator is disabled unless both the RC
oscillator has been selected as the system clock and the RTC is enabled.
7.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there will be high power consumption. Please use an external low frequency
clock to achieve low power with the RTC running during power-down.
7.16 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,
P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external
reset input function on P1.5. When cleared, P1.5 may be used as an input pin.
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Remark: During a power-up sequence, the RPE selection is overridden and this pin will
always function as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this input will function either as an external reset input or as a digital input
as defined by the RPE bit. Only a power-up reset will temporarily override the selection
defined by RPE bit. Other sources of reset will not override the RPE bit.
Reset can be triggered from the following sources:
•
•
•
•
•
•
External reset pin (during power-up or if user configured via UCFG1).
Power-on detect.
Brownout detect.
Watchdog timer.
Software reset.
UART break character detect reset.
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These flag bits can be cleared in
software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
• During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
• For any other reset, previously set flag bits that have not been cleared will remain set.
7.16.1 Reset vector
Following reset, the P89LPC9408 will fetch instructions from either address 0000H or the
Boot address. The Boot address is formed by using the Boot Vector as the high byte of the
address and the low byte of the address = 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC9408 User manual). Otherwise, instructions will be fetched from address 0000H.
7.17 Timers/counters 0 and 1
The P89LPC9408 has two general purpose counter/timers which are upward compatible
with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as
timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer
overflow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2
and 6 are the same for both Timers/Counters. Mode 3 is different.
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7.17.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a
13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
7.17.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.17.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2
operation is the same for Timer 0 and Timer 1.
7.17.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is
in Mode 3 it can still be used by the serial port as a baud rate generator.
7.17.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
7.17.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer
overflow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first
timer overflow when this mode is turned on.
7.18 RTC/system timer
The P89LPC9408 has a simple RTC that allows a user to continue running an accurate
timer while the rest of the device is powered-down. The RTC can be a wake-up or an
interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a
16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded
again and the RTCF flag will be set. The clock source for this counter can be either the
CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being
used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will
use CCLK as its clock source. Only power-on reset will reset the RTC and its associated
SFRs to the default state.
7.19 CCU
This unit features:
• A 16-bit timer with 16-bit reload on overflow.
• Selectable clock, with prescaler to divide clock source by any integral number
between 1 and 1024.
• Four compare/PWM outputs with selectable polarity
• Symmetrical/asymmetrical PWM selection
• Two capture inputs with event counter and digital noise rejection filter
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• Seven interrupts with common interrupt vector (one Overflow, two Capture,
four Compare)
• Safe 16-bit read/write via shadow registers.
7.19.1 CCU Clock (CCUCLK)
The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of
a PLL. The PLL is designed to use a clock source between 0.5 MHz to 1 MHz that is
multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode
(asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide PCLK into a
frequency between 0.5 MHz and 1 MHz.
7.19.2 CCU clock prescaling
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented
as a 10-bit free-running counter with programmable reload at overflow.
7.19.3 Basic timer operation
The timer is a free-running up/down counter with a direction control bit. If the timer
counting direction is changed while the counter is running, the count sequence will be
reversed. The timer can be written or read at any time.
When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt
generated if enabled. The 16-bit CCU Timer may also be used as an 8-bit up/down timer.
7.19.4 Output compare
There are four output compare channels A, B, C and D. Each output compare channel
needs to be enabled in order to operate and the user will have to set the associated I/O
pin to the desired output mode to connect the pin. When the contents of the timer matches
that of a capture compare control register, the Timer Output Compare Interrupt Flag
(TOCFx) becomes set. An interrupt will occur if enabled.
7.19.5 Input capture
Input capture is always enabled. Each time a capture event occurs on one of the two input
capture pins, the contents of the timer is transferred to the corresponding 16-bit input
capture register. The capture event can be programmed to be either rising or falling edge
triggered. A simple noise filter can be enabled on the input capture by enabling the Input
Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of
the same value in order to recognize an edge as a capture event. An event counter can be
set to delay a capture by a number of capture events.
7.19.6 PWM operation
PWM operation has two main modes, symmetrical and asymmetrical.
In asymmetrical PWM operation the CCU Timer operates in down-counting mode
regardless of the direction control bit.
In symmetrical mode, the timer counts up/down alternately. The main difference from
basic timer operation is the operation of the compare module, which in PWM mode is
used for PWM waveform generation.
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As with basic timer operation, when the PWM (compare) pins are connected to the
compare logic, their logic state remains unchanged. However, since bit FCOx is used to
hold the halt value, only a compare event can change the state of the pin.
TOR2
compare value
timer value
0x0000
non-inverted
inverted
002aaa893
Fig 8. Asymmetrical PWM, down-counting
TOR2
compare value
timer value
0
non-inverted
inverted
002aaa894
Fig 9. Symmetrical PWM
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7.19.7 Alternating output mode
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
TIMER VALUE
0
PWM OUTPUT (OCA or OCC)
PWM OUTPUT (OCB or OCD)
002aaa895
Fig 10. Alternate output mode
7.19.8 PLL operation
The PWM module features a Phase Locked Loop that can be used to generate a
CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module
provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal
frequency is 1 MHz or higher. The PLL is fed an input signal of 0.5 MHz to 1 MHz and
generates an output signal of 32 times the input frequency. This signal is used to clock the
timer. The user will have to set a divider that scales PCLK by a factor of 1 to 16. This
divider is found in the SFR register TCR21. The PLL frequency can be expressed as
shown in Equation 1.
PLCK
PLL frequency = -----------------(N + 1)
Where: N is the value of PLLDV3:0.
(1)
Since N ranges in 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK⁄16.
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P89LPC9408
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.19.9 CCU interrupts
There are seven interrupt sources on the CCU which share a common interrupt vector.
EA (IEN0.7)
ECCU (IEN1.4)
TOIE2 (TICR2.7)
TOIF2 (TIFR2.7)
TICIE2A (TICR2.0)
TICF2A (TIFR2.0)
TICIE2B (TICR2.1)
TICF2B (TIFR2.1)
TOCIE2A (TICR2.3)
TOCF2A (TIFR2.3)
TOCIE2B (TICR2.4)
TOCF2B (TIFR2.4)
interrupt to
CPU
other
interrupt
sources
TOCIE2C (TICR2.5)
TOCF2C (TIFR2.5)
TOCIE2D (TICR2.6)
TOCF2D (TIFR2.6)
ENCINT.0
PRIORITY
ENCODER
ENCINT.1
ENCINT.2
002aaa896
Fig 11. CCU interrupts
7.20 UART
The P89LPC9408 has an enhanced UART that is compatible with the conventional 80C51
UART except that Timer 2 overflow cannot be used as a baud rate source. The
P89LPC9408 does include an independent Baud Rate Generator. The baud rate can be
selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent
Baud Rate Generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, automatic address recognition,
selectable double buffering and several interrupt options. The UART can be operated in
four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.20.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock
frequency.
7.20.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 7.20.5
“Baud rate generator and selection”).
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.20.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop
bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock
frequency, as determined by the SMOD1 bit in PCON.
7.20.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 7.20.5 “Baud rate generator and selection”).
7.20.5 Baud rate generator and selection
The P89LPC9408 enhanced UART has an independent Baud Rate Generator. The baud
rate is determined by a baud rate preprogrammed into the BRGR1 and BRGR0 SFRs
which together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 12). Note
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses OSCCLK.
timer 1 overflow
(PCLK-based)
SMOD1 = 1
SBRGS = 0
÷2
baud rate modes 1 and 3
SMOD1 = 0
baud rate generator
(CCLK-based)
SBRGS = 1
002aaa897
Fig 12. Baud rate sources for UART (Modes 1, 3)
7.20.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are set up
when SMOD0 is logic 0.
7.20.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.20.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be
written to SBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
7.20.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TX interrupt is generated
when the double buffer is ready to receive new data.
7.20.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TX interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
7.21 I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multi master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
• The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 13. The P89LPC9408 device provides a
byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
RPU
RPU
SDA
I2C-bus
SCL
P1.3/SDA
P1.2/SCL
I2C MCU
OTHER DEVICE
WITH I2C-BUS
INTERFACE
OTHER DEVICE
WITH I2C-BUS
INTERFACE
002aab410
Fig 13. I2C-bus configuration
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
8
I2ADR
ADDRESS REGISTER
P1.3
COMPARATOR
INPUT
FILTER
P1.3/SDA
ACK
SHIFT REGISTER
OUTPUT
STAGE
I2DAT
BIT COUNTER /
ARBITRATION &
SYNC LOGIC
INPUT
FILTER
CCLK
TIMING
AND
CONTROL
LOGIC
P1.2/SCL
SERIAL CLOCK
GENERATOR
OUTPUT
STAGE
interrupt
INTERNAL BUS
8
timer 1
overflow
P1.2
I2CON
I2SCLH
I2SCLL
CONTROL REGISTERS &
SCL DUTY CYCLE REGISTERS
8
status bus
I2STAT
STATUS
DECODER
STATUS REGISTER
8
002aaa899
Fig 14. I2C-bus serial interface block diagram - P89LPC9408
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.22 SPI
The P89LPC9408 provides another high-speed serial communication interface—the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in
Master mode or up to 3 Mbit/s in Slave mode. It has a transfer completion flag and write
collision flag protection.
S
M
CPU clock
8-BIT SHIFT REGISTER
READ DATA BUFFER
DIVIDER
BY 4, 16, 64, 128
MOSI
P2.2
SPICLK
P2.5
SPEN
MSTR
SPR0
SPR1
CPOL
CPHA
MSTR
DORD
SPEN
MSTR
SPEN
SSIG
SPIF
PIN
CONTROL
LOGIC
S
M
CLOCK LOGIC
SPR0
SPR1
SELECT
WCOL
MISO
P2.3
clock
SPI clock (master)
SPI CONTROL
M
S
SPI CONTROL REGISTER
SPI STATUS REGISTER
SPI
interrupt
request
internal
data
bus
002aab466
Fig 15. SPI block diagram
The SPI interface has three pins: SPICLK, MOSI, and MISO:
• SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
Typical connections are shown in Figure 16 through Figure 18.
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.22.1 Typical SPI configurations
master
slave
8-BIT SHIFT
REGISTER
MISO
MISO
MOSI
MOSI
SPICLK
SPI CLOCK
GENERATOR
SS/PORT
8-BIT SHIFT
REGISTER
SPICLK
SS/PORT
002aab467
Fig 16. SPI single master single slave configuration
master
8-BIT SHIFT
REGISTER
slave
MISO
MISO
MOSI
MOSI
SPICLK
SPI CLOCK
GENERATOR
SS/PORT
8-BIT SHIFT
REGISTER
SPICLK
SS/PORT
SPI CLOCK
GENERATOR
002aab468
Fig 17. SPI dual device configuration, where either can be a master or a slave
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
master
slave
8-BIT SHIFT
REGISTER
MISO
MISO
MOSI
MOSI
SPICLK
SPI CLOCK
GENERATOR
port
8-BIT SHIFT
REGISTER
SPICLK
SS
slave
MISO
MOSI
8-BIT SHIFT
REGISTER
SPICLK
port
SS
002aaa903
Fig 18. SPI single master multiple slaves configuration
7.23 Analog comparators
Two analog comparators are provided on the P89LPC9408. Input and output options allow
use of the comparators in a number of different configurations. Comparator operation is
such that the output is a logic 1 (which may be read in a register and/or routed to a pin)
when the positive input (one of two selectable pins) is greater than the negative input
(selectable from a pin or an internal reference voltage). Otherwise the output is a zero.
Each comparator may be configured to cause an interrupt when the output value changes.
The overall connections to both comparators are shown in Figure 19. The comparators
function to VDD = 2.4 V.
When each comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt
should not be enabled during that time, and the comparator interrupt flag must be cleared
before the interrupt is enabled in order to prevent an immediate interrupt service.
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
CP1
OE1
comparator 1
(P0.4) CIN1A
(P0.3) CIN1B
CO1
CMP1 (P0.6)
(P0.5) CMPREF
change detect
Vref(bg)
CMF1
CN1
interrupt
change detect
EC
CP2
CMF2
comparator 2
(P0.2) CIN2A
(P0.1) CIN2B
CMP2 (P0.0)
CO2
OE2
CN2
002aaa904
Fig 19. Comparator input and output connections
7.23.1 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to as
Vref(bg), is 1.23 V ± 10 %.
7.23.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is
set whenever the comparator output changes state. The flag may be polled by software or
may be used to generate an interrupt. The two comparators use one common interrupt
vector. If both comparators enable interrupts, after entering the interrupt service routine,
the user needs to read the flags to determine which comparator caused the interrupt.
7.23.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down mode.
If a comparator interrupt is enabled (except in Total Power-down mode), a change of the
comparator output state will generate an interrupt and wake up the processor. If the
comparator output to a pin is enabled, the pin should be configured in the push-pull mode
in order to obtain fast switching times while in Power-down mode. The reason is that with
the oscillator stopped, the temporary strong pull-up that normally occurs during switching
on a quasi-bidirectional port pin does not take place.
Comparators consume power in Power-down and Idle modes, as well as in the normal
operating mode. This fact should be taken into account when system power consumption
is an issue. To minimize power consumption, the user can disable the comparators via
PCONA.5, or put the device in Total Power-down mode.
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.24 Keypad Interrupt (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can be
used for bus address recognition or keypad recognition. The user can configure the port
via SFRs for different tasks.
The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is
used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag
(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is
matched while the Keypad Interrupt function is active. An interrupt will be generated if
enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to
define equal or not-equal for the comparison.
In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,
the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key
connected to Port 0 which is enabled by the KBMASK register will cause the hardware to
set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to
wake up the CPU from Idle or Power-down modes. This feature is particularly useful in
handheld, battery-powered systems that need to carefully manage power consumption
yet also need to be convenient to use.
In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer
than six CCLKs.
7.25 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog feature is disabled, it can be used as an interval timer
and may generate an interrupt. Figure 20 shows the watchdog timer in Watchdog mode.
Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog
clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a
time-out period that ranges from a few µs to a few seconds. Please refer to the
P89LPC9408 User manual for more details.
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
WDL (C1H)
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
watchdog
oscillator
PCLK
÷32
8-BIT DOWN
COUNTER
PRESCALER
reset(1)
SHADOW REGISTER
WDCON (A7H)
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
002aaa905
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 20. Watchdog timer in Watchdog mode (WDTE = 1)
7.26 Additional features
7.26.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
7.26.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
7.27 LCD controller
7.27.1 General description
The LCD segment driver in the P89LPC9408 can interface to most LCDs using low
multiplex rates. It generates the drive signals for static or multiplexed LCDs containing up
to four backplanes and up to 32 segments. The LCD controller communicates to a host
using the I2C-bus. The I2C-bus clock and data signals for both the microcontroller and the
LCD controller are available on the P89LPC9408 providing system flexibility.
Communication overhead to manage the display is minimized by an on-chip display RAM
with auto-increment addressing, hardware subaddressing, and display memory switching
(static and duplex drive modes).
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7.27.2 Functional description
The LCD controller is a versatile peripheral device designed to interface microcontrollers
to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up
to four backplanes and up to 32 segments. The display configurations possible with the
LCD controller depend on the number of active backplane outputs required. A selection of
display configurations is shown in Table 8. All of these configurations can be implemented
in a typical system.
The microcontroller communicates to the LCD controller using the I2C-bus.The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(VDD, VSS and VLCD) and the LCD panel chosen for the application.
Table 8:
Selection of display configurations
Number of
7-Segments Numeric
14- Segments Alphanumeric
Dot Matrix
Back Planes
Segments
Digits
Indicator
Symbols
Characters
Indicator
Symbols
4
128
16
16
8
16
128
3
96
12
12
6
12
96
2
64
8
8
4
8
64
1
32
4
4
2
4
32
7.27.3 LCD bias voltages
LCD biasing voltages are obtained from an internal voltage divider consisting of three
series resistors connected between VLCD and VSS. The LCD voltage can be temperature
compensated externally via the supply to pin VLCD. A voltage selector drives the
multiplexing of the LCD based on programmable configurations.
7.27.4 Oscillator
An internal oscillator provides the clock signals for the internal logic of the LCD controller
and its LCD drive signals. After power-up, pin SDA must be HIGH to guarantee that the
clock starts.
7.27.5 Timing
The LCD controller timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
the internal or an external clock.
Frame frequency = fCLK/24.
7.27.6 Display register
A display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs, and each column of the display RAM.
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.27.7 Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31. The segment output
signals are generated according to the multiplexed backplane signals and the display
latch data. When less than 32 segment outputs are required, the unused segment outputs
should be left open-circuit.
7.27.8 Backplane outputs
The LCD drive section has four backplane outputs BP0 to BP3. The backplane output
signals are generated based on the selected LCD drive mode. If less than four backplane
outputs are required, the unused outputs can be left open-circuit. In the 1:3 multiplex drive
mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be
tied together to give enhanced drive capabilities. In the 1:2 multiplex drive mode, BP0 and
BP2, BP1 and BP3 respectively carry the same signals and may also be paired to
increase the drive capabilities. In the static drive mode the same signal is carried by all
four backplane outputs and they can be connected in parallel for very high drive
requirements.
7.27.9 Display RAM
The display RAM is a static 32 × 4-bit RAM which stores LCD data. There is a one-to-one
correspondence between the RAM addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs. The first RAM column
corresponds to the 32 segments for backplane 0 (BP0). In multiplexed LCD applications
the segment data of the second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.
7.27.10 Data pointer
The Display RAM is addressed using the data pointer. Either a single byte or a series of
display bytes may be loaded into any location of the display RAM.
7.27.11 Output bank selector
The LCD controller includes a RAM bank switching feature in the static and 1:2 drive
modes. In the static drive mode, the BANK SELECT command may request the contents
of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the contents
of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to
be prepared in an alternative bank and then selected for display when it is assembled.
7.27.12 Input bank selector
The input bank selector loads display data into the display RAM based on the selected
LCD drive configuration. The BANK SELECT command can be used to load display data
in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector
functions are independent of the output bank selector.
7.27.13 Blinker
The LCD controller has a very versatile display blinking capability. The whole display can
blink at a frequency selected by the BLINK command. Each blink frequency is a multiple
integer value of the clock frequency; the ratio between the clock frequency and blink
frequency depends on the blink mode selected, as shown in Table 9.
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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
An additional feature allows an arbitrary selection of LCD segments to be blinked in the
static and 1:2 drive modes. This is implemented without any communication overheads by
the output bank selector which alternates the displayed data between the data in the
display RAM bank and the data in an alternative RAM bank at the blink frequency. This
mode can also be implemented by the BLINK command.
The entire display can be blinked at a frequency other than the nominal blink frequency by
sequentially resetting and setting the display enable bit E at the required rate using the
MODE SET command.
Table 9:
Blinking frequencies
Blink mode
Normal operating mode ratio Normal Blink frequency
Off
-
Blinking off
2 Hz
fosc(LCD)/768
2 Hz
1 Hz
fosc(LCD)/1536
1 Hz
0.5 Hz
fosc(LCD)/3072
0.5 Hz
Blink modes 0.5 Hz, 1 Hz and 2 Hz, and nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz
correspond to an oscillator frequency (fosc(LCD)) of 1536 Hz at pin CLK. The oscillator
frequency range is 397 Hz to 3046 Hz.
7.27.13.1
I2C-bus controller
The LCD controller acts as an I2C-bus slave receiver. In the P89LPC9408 the hardware
subaddress inputs A0, A,1 and A2 are tied to VSS setting the hardware subaddress = 0.
7.27.14 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.27.15 I2C-bus slave addresses
The I2C-bus slave address is 0111 0000. The LCD controller is a write-only device and will
not respond to a read access.
7.28 Data EEPROM
The P89LPC9408 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR
based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can
read, write and fill the memory via SFRs and one interrupt. This Data EEPROM provides
100,000 minimum erase/program cycles for each byte.
• Byte Mode: In this mode, data can be read and written one byte at a time.
• Row Fill: In this mode, the addressed row (64 bytes) is filled with a single value. The
entire row can be erased by writing 00H.
• Sector Fill: In this mode, all 512 bytes are filled with a single value. The entire sector
can be erased by writing 00H.
After the operation finishes, the hardware will set the EEIF bit, which if enabled will
generate an interrupt. The flag is cleared by software.
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P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.29 Flash program memory
7.29.1 General description
The P89LPC9408 flash memory provides in-circuit electrical erasure and programming.
The flash can be erased, read, and written as bytes. The Sector and Page Erase functions
can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase
the entire program memory. ICP using standard commercial programmers is available. In
addition, IAP and byte-erase allows code memory to be used for non-volatile data storage.
On-chip erase and write timing generation contribute to a user-friendly programming
interface. The P89LPC9408 flash reliably stores memory contents even after
100,000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. The P89LPC9408 uses VDD as the supply voltage to perform
the Program/Erase algorithms.
7.29.2 Features
•
•
•
•
•
Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ISP/IAP/ICP.
Internal fixed boot ROM, containing low-level IAP routines available to user code.
Default loader providing ISP via the serial port, located in upper end of user program
memory.
• Boot vector allows user-provided flash loader code to reside anywhere in the flash
memory space, providing flexibility to the user.
•
•
•
•
•
Any flash program or erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the flash for each sector.
100,000 typical erase/program cycles for each byte.
10 year minimum data retention.
7.29.3 Flash organization
The program memory consists of eight 1 kB sectors on the P89LPC9408 device. Each
sector can be further divided into 64-byte pages. In addition to sector erase, page erase,
and byte erase, a 64-byte page register is included which allows from 1 to 64 bytes of a
given page to be programmed at the same time, substantially reducing overall
programming time.
7.29.4 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a MOVC
instruction is not allowed to read code memory contents of a secured sector). Thus any
byte in a non-secured sector may be used for non-volatile data storage.
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47 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.29.5 Flash programming and erasing
Four different methods of erasing or programming of the flash are available. The flash may
be programmed or erased in the end-user application (IAP) under control of the
application’s firmware. Another option is to use the ICP mechanism. This ICP system
provides for programming through a serial clock - serial data interface. As shipped from
the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing
for the device to be programmed in circuit through the serial port. The flash may also be
programmed or erased using a commercially available EPROM programmer which
supports this device. This device does not provide for direct verification of code memory
contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire
user code space.
7.29.6 In-Circuit Programming
In-Circuit Programming is performed without removing the microcontroller from the
system. The ICP facility consists of internal hardware resources to facilitate remote
programming of the P89LPC9408 through a two-wire serial interface. The Philips ICP
facility has made ICP in an embedded application—using commercially available
programmers—possible with a minimum of additional expense in components and circuit
board area. The ICP function uses five pins. Only a small connector needs to be available
to interface your application to a commercial programmer in order to use this feature.
Additional details may be found in the P89LPC9408 User manual.
7.29.7 In-Application Programming
In-Application Programming is performed in the application under the control of the
microcontroller’s firmware. The IAP facility consists of internal hardware resources to
facilitate programming and erasing. The Philips IAP has made IAP in an embedded
application possible without additional components. Two methods are available to
accomplish IAP. A set of predefined IAP functions are provided in a Boot ROM and can be
called through a common interface, PGM_MTP. Several IAP calls are available for use by
an application program to permit selective erasing and programming of flash sectors,
pages, security bits, configuration bytes, and device ID. These functions are selected by
setting up the microcontroller’s registers before making a call to PGM_MTP at FF03H.
The Boot ROM occupies the program memory space at the top of the address space from
FF00H to FEFFH, thereby not conflicting with the user program memory space.
In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC9408 User manual.
7.29.8 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC9408 through the serial port. This firmware is
provided by Philips and embedded within each P89LPC9408 device. The Philips ISP
facility has made ISP in an embedded application possible with a minimum of additional
expense in components and circuit board area. The ISP function uses five pins (VDD, VSS,
TXD, RXD, and RST). Only a small connector needs to be available to interface your
application to an external circuit in order to use this feature.
P89LPC9408_1
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Rev. 01 — 16 December 2005
48 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.29.9 Power-on reset code execution
The P89LPC9408 contains two special flash elements: the Boot Vector and the Boot
Status Bit. Following reset, the P89LPC9408 examines the contents of the Boot Status
Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which
is the normal start address of the user’s application code. When the Boot Status Bit is set
to a value other than zero, the contents of the Boot Vector are used as the HIGH byte of
the execution address and the LOW byte is set to 00H.
Table 10 shows the factory default Boot Vector settings for these devices. Note: These
settings are different than the original P89LPC932. Tools designed to support the
P89LPC9408 should be used to program this device, such as Flash Magic version
1.98, or later. A factory-provided boot loader is preprogrammed into the address space
indicated and uses the indicated boot loader entry point to perform ISP functions. This
code can be erased by the user. Users who wish to use this loader should take
precautions to avoid erasing the 1 kB sector that contains this boot loader. Instead,
the page erase function can be used to erase the first eight 64-byte pages located in
this sector. A custom boot loader can be written with the Boot Vector set to the custom
boot loader, if desired.
Table 10:
Default Boot Vector values and ISP entry points
Device
Default
Boot Vector
Default
boot loader
entry point
Default boot loader 1 kB sector
code range
range
P89LPC9408
1FH
1F00H
1E00H to 1FFFH
1C00H to 1FFFH
7.29.10 Hardware activation of the boot loader
The boot loader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC9408 User manual for specific information). This has
the same effect as having a non-zero status byte. This allows an application to be built that
will normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the Boot Vector (1FH) is changed, it will no longer point to the
factory preprogrammed ISP boot loader code. After programming the flash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
7.30 User configuration bytes
Some user-configurable features of the P89LPC9408 must be defined at power-up and
therefore cannot be set by the program after start of execution. These features are
configured through the use of the flash byte UCFG1. Please see the P89LPC9408 User
manual for additional details.
7.31 User sector security bytes
There are eight User Sector Security Bytes on the P89LPC9408 device. Each byte
corresponds to one sector. Please see the P89LPC9408 User manual for additional
details.
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
49 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
8. ADC
8.1 General description
The P89LPC9408 has a 10-bit, 8-channel multiplexed successive approximation
analog-to-digital converter module. A block diagram of the ADC is shown in Figure 21.
The ADC consists of an 8-input multiplexer which feeds a sample-and-hold circuit
providing an input signal to one of two comparator inputs. The control logic in combination
with the SAR drives a digital-to-analog converter which provides the other input to the
comparator. The output of the comparator is fed to the SAR.
8.2 Features
■ 10-bit, 8-channel multiplexed input, successive approximation ADC.
■ Eight result register pairs.
■ Six operating modes
◆ Fixed channel, single conversion mode
◆ Fixed channel, continuous conversion mode
◆ Auto scan, single conversion mode
◆ Auto scan, continuous conversion mode
◆ Dual channel, continuous conversion mode
◆ Single step mode
■ Three conversion start modes
◆ Timer triggered start
◆ Start immediately
◆ Edge triggered
■ 10-bit conversion time of 4 µs at an ADC clock of 9 MHz
■ Interrupt or polled operation
■ High and Low Boundary limits interrupt; selectable in or out-of-range
■ Clock divider
■ Power-down mode
8.3 Block diagram
comp
+
INPUT
MUX
SAR
–
CONTROL
LOGIC
8
DAC0
CCLK
002aab103
Fig 21. ADC block diagram
P89LPC9408_1
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P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
8.4 ADC operating modes
8.4.1 Fixed channel, single conversion mode
A single input channel can be selected for conversion. A single conversion will be
performed and the result placed in the result register pair which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after the conversion
completes.
8.4.2 Fixed channel, continuous conversion mode
A single input channel can be selected for continuous conversion. The results of the
conversions will be sequentially placed in the eight result register pairs. The user may
select whether an interrupt can be generated after every four or every eight conversions.
Additional conversion results will again cycle through the result register pairs, overwriting
the previous results. Continuous conversions continue until terminated by the user.
8.4.3 Auto scan, single conversion mode
Any combination of the eight input channels can be selected for conversion. A single
conversion of each selected input will be performed and the result placed in the result
register pair which corresponds to the selected input channel. The user may select
whether an interrupt, if enabled, will be generated after either the first four conversions
have occurred or all selected channels have been converted. If the user selects to
generate an interrupt after the four input channels have been converted, a second
interrupt will be generated after the remaining input channels have been converted. If only
a single channel is selected this is equivalent to single channel, single conversion mode.
8.4.4 Auto scan, continuous conversion mode
Any combination of the eight input channels can be selected for conversion. A conversion
of each selected input will be performed and the result placed in the result register pair
which corresponds to the selected input channel. The user may select whether an
interrupt, if enabled, will be generated after either the first four conversions have occurred
or all selected channels have been converted. If the user selects to generate an interrupt
after the four input channels have been converted, a second interrupt will be generated
after the remaining input channels have been converted. After all selected channels have
been converted, the process will repeat starting with the first selected channel. Additional
conversion results will again cycle through the eight result register pairs, overwriting the
previous results. Continuous conversions continue until terminated by the user.
8.4.5 Dual channel, continuous conversion mode
This is a variation of the auto scan continuous conversion mode where conversion occurs
on two user-selectable inputs. The result of the conversion of the first channel is placed in
the result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the
second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The first
channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The
second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L,
etc. An interrupt is generated, if enabled, after every set of four or eight conversions (user
selectable).
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Product data sheet
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51 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
8.4.6 Single step mode
This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any
combination of the eight input channels can be selected for conversion. After each
channel is converted, an interrupt is generated, if enabled, and the ADC waits for the next
start condition. May be used with any of the start modes.
8.5 Conversion start modes
8.5.1 Timer triggered start
The ADC is started by the overflow of Timer 0. Once a conversion has started, additional
Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start
mode is available in all ADC operating modes.
8.5.2 Start immediately
Programming this mode immediately starts a conversion.This start mode is available in all
ADC operating modes.
8.5.3 Edge triggered
The ADC is started by rising or falling edge of P1.4. Once a conversion has started,
additional edge triggers are ignored until the conversion has completed. The edge
triggered start mode is available in all ADC operating modes.
8.6 Boundary limits interrupt
The ADC has both a high and low boundary limit register. The user may select whether an
interrupt is generated when the conversion result is within (or equal to) the high and low
boundary limits or when the conversion result is outside the boundary limits. An interrupt
will be generated, if enabled, if the result meets the selected interrupt criteria. The
boundary limit may be disabled by clearing the boundary limit interrupt enable.
An early detection mechanism exists when the interrupt criteria has been selected to be
outside the boundary limits. In this case, after the four MSBs have been converted, these
four bits are compared with the four MSBs of the boundary high and low registers. If the
four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)
an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt
criteria, the boundary limits will again be compared after all 8 MSBs have been converted.
A boundary status register (BNDSTA0) flags the channels which caused a boundary
interrupt.
8.7 Clock divider
The ADC requires that its internal clock source be in the range of 500 kHz to 3 MHz to
maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is
provided for this purpose.
8.8 Power-down and Idle mode
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit
Idle mode when the conversion is completed if the ADC interrupt is enabled. In
Power-down mode or Total Power-down mode, the ADC does not function. If the ADC is
enabled, it will consume power. Power can be reduced by disabling the ADC.
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
52 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
9. Limiting values
Table 11: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). [1]
Symbol
Parameter
Tamb(bias)
Min
Max
Unit
bias ambient temperature
−55
+125
°C
Tstg
storage temperature
−65
+150
°C
IOH(I/O)
HIGH-state output current per
input/output pin
-
20
mA
IOL(I/O)
LOW-state output current per
input/output pin
-
20
mA
II/Otot(max)
maximum total input/output current
-
100
mA
Vn
voltage on any other pin
except VSS, with respect to
VDD
-
3.5
V
Ptot(pack)
total power dissipation (per package)
based on package heat
transfer, not device power
consumption
-
1.5
W
[1]
Conditions
The following applies to Table 11:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
10. Static characteristics
Table 12: Static electrical characteristics
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Min
Typ [1]
Max
Unit
[2]
-
11
15
mA
VDD = 3.6 V; fosc = 18 MHz
[2]
-
17
23
mA
3.6 V; 12 MHz
[2]
-
3.7
5
mA
3.6 V; 18 MHz
[2]
-
6
8
mA
voltage comparators
powered down;
VDD = 3.6 V
[2]
-
60
85
µA
[3]
-
9
25
µA
Symbol
Parameter
Conditions
IDD(oper)
operating supply current
VDD = 3.6 V; fosc = 12 MHz
IDD(idle)
Idle mode supply current
IDD(pd)
Power-down mode supply
current
IDD(tpd)
total Power-down mode supply VDD = 3.6 V
current
(dV/dt)r
rise rate
of VDD
-
-
2
mV/µs
(dV/dt)f
fall rate
of VDD
-
-
50
mV/µs
VDDR
data retention supply voltage
1.5
-
-
V
Vth(HL)
HIGH-LOW threshold voltage
except SCL, SDA
0.22VDD
0.4VDD
-
V
VIL
LOW-state input voltage
SCL, SDA only
−0.5
-
+0.3VDD
V
Vth(LH)
LOW-HIGH threshold voltage
except SCL, SDA
-
0.6VDD
0.7VDD
V
VIH
HIGH-state input voltage
SCL, SDA only
0.7VDD
-
5.5
V
Vhys
hysteresis voltage
port 1
-
0.2VDD
-
V
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P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Table 12: Static electrical characteristics …continued
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
VOL
Parameter
LOW-state output voltage
VOH
HIGH-state output voltage
Min
Typ [1]
Max
Unit
IOL = 20 mA;
VDD = 2.4 V to 3.6 V,
all ports, all modes except
high-Z
[4]
-
0.6
1.0
V
IOL = 3.2 mA; VDD = 2.4 V
to 3.6 V; all ports; all
modes except high-Z
[4]
-
0.2
0.3
V
IOH = −20 µA;
VDD = 2.4 V to 3.6 V;
all ports;
quasi-bidirectional mode
VDD − 0.3
VDD − 0.2 -
V
IOH = −3.2 mA;
VDD = 2.4 V to 3.6 V;
all ports; push-pull mode
VDD − 0.7
VDD − 0.4 -
V
V
Conditions
Vxtal
crystal voltage
with respect to VSS
−0.5
-
+4.0
Vn
voltage on any other pin
except XTAL1, XTAL2, VDD;
with respect to VSS
−0.5
-
+5.5
Ci
input capacitance
[5]
-
-
15
pF
IIL
LOW-state input current
VI = 0.4 V
[6]
-
-
−80
µA
ILI
input leakage current
VI = VIL or VIH
[7]
-
-
±10
µA
VI = 1.5 V at VDD = 3.6 V
[8]
−30
-
−450
µA
10
-
30
kΩ
2.40
-
2.70
V
ITHL
HIGH-LOW transition current
RRST_N(int)
internal pull-up resistance on
pin RST_N
Vbo
brownout trip voltage
Vref(bg)
band gap reference voltage
1.11
1.23
1.34
V
TCbg
band gap temperature
coefficient
-
10
20
ppm/°C
2.4 V < VDD < 3.6 V; with
BOE = 1, BOPD = 0
[1]
Typical ratings are not guaranteed. The values listed are at room temperature, VDD = 3 V.
[2]
The IDD(oper), IDD(idle), and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators,
real-time clock, and watchdog timer.
[3]
The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock,
brownout detect, and watchdog timer.
[4]
See Section 9 “Limiting values” on page 53 for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition,
VOL/VOH may exceed the related specification.
[5]
Pin capacitance is characterized but not tested.
[6]
Measured with port in quasi-bidirectional mode.
[7]
Measured with port in high-impedance mode.
[8]
Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when VI is approximately 2 V.
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
54 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
11. Dynamic characteristics
Table 13: Dynamic characteristics (12 MHz)
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2]
Symbol
Parameter
Conditions
fosc(RC)
internal RC oscillator frequency
fosc(WD)
internal watchdog oscillator frequency
fosc
oscillator frequency
Tcy(clk)
clock cycle time
fCLKLP
low-power select clock frequency
Variable clock
fosc = 12 MHz
Unit
Min
Max
Min
7.189
7.557
7.189
320
520
320
520
kHz
0
12
-
-
MHz
see Figure 23
Max
7.557 MHz
83
-
-
-
ns
0
8
-
-
MHz
P1.5/RST pin
-
50
-
50
ns
any pin except
P1.5/RST
-
15
-
15
ns
P1.5/RST pin
125
-
125
-
ns
any pin except
P1.5/RST
50
-
50
-
ns
Glitch filter
tgr
tsa
glitch rejection time
signal acceptance time
External clock
tCHCX
clock HIGH time
see Figure 23
33
Tcy(clk) − tCLCX
33
-
ns
tCLCX
clock LOW time
see Figure 23
33
Tcy(clk) − tCHCX
33
-
ns
tCLCH
clock rise time
see Figure 23
-
8
-
8
ns
tCHCL
clock fall time
see Figure 23
-
8
-
8
ns
Shift register (UART mode 0)
TXLXL
serial port clock cycle time
see Figure 22
16Tcy(clk)
-
1333
-
ns
tQVXH
output data setup to clock rising edge see Figure 22
time
13Tcy(clk)
-
1083
-
ns
tXHQX
output data hold after clock rising
edge time
see Figure 22
-
Tcy(clk) + 20
-
103
ns
tXHDX
input data hold after clock rising edge see Figure 22
time
-
0
-
0
ns
tXHDV
input data valid to clock rising edge
time
150
-
150
-
ns
0
CCLK⁄
6
0
2.0
MHz
-
CCLK⁄
4
-
3.0
MHz
see Figure 22
SPI interface
fSPI
SPI operating frequency
slave
master
TSPICYC
SPI cycle time
slave
see Figure 24,
25, 26, 27
6⁄
CCLK
-
500
-
ns
4⁄
CCLK
-
333
-
ns
see Figure 26,
27
250
-
250
-
ns
see Figure 26,
27
250
-
250
-
ns
master
tSPILEAD
SPI enable lead time
tSPILAG
SPI enable lag time
slave
slave
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P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Table 13: Dynamic characteristics (12 MHz) …continued
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2]
Symbol
Parameter
Conditions
Variable clock
Min
tSPICLKH
SPICLK HIGH time
see Figure 24,
25, 26, 27
master
slave
tSPICLKL
SPICLK LOW time
see Figure 24,
25, 26, 27
master
Max
Min
Max
Unit
2⁄
CCLK
-
165
-
ns
3⁄
CCLK
-
250
-
ns
2⁄
CCLK
-
165
-
ns
CCLK
-
250
-
ns
3⁄
slave
fosc = 12 MHz
tSPIDSU
SPI data setup time
see Figure 24,
25, 26, 27
100
-
100
-
ns
tSPIDH
SPI data hold time
see Figure 24,
25, 26, 27
100
-
100
-
ns
tSPIA
SPI access time
see Figure 26,
27
0
120
0
120
ns
see Figure 26,
27
0
240
-
240
ns
see Figure 24,
25, 26, 27
-
240
-
240
ns
slave
tSPIDIS
SPI disable time
slave
tSPIDV
SPI enable to output data valid time
slave
master
tSPIOH
SPI output data hold time
see Figure 24,
25, 26, 27
tSPIR
SPI rise time
see Figure 24,
25, 26, 27
SPI outputs
(SPICLK, MOSI, MISO)
SPI inputs (SPICLK, MOSI, MISO)
tSPIF
SPI fall time
see Figure 24,
25, 26, 27
SPI outputs
(SPICLK, MOSI, MISO)
SPI inputs (SPICLK, MOSI, MISO)
-
167
-
167
ns
0
-
0
-
ns
-
100
-
100
ns
-
2000
-
2000
ns
-
100
-
100
ns
-
2000
-
2000
ns
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
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P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Table 14: Dynamic characteristics (18 MHz)
VDD = 3.0 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2]
Symbol
Parameter
Conditions
fosc(RC)
internal RC oscillator frequency
fosc(WD)
internal watchdog oscillator frequency
fosc
oscillator frequency
Tcy(clk)
clock cycle time
fCLKLP
low-power select clock frequency
Variable clock
fosc = 18 MHz
Unit
Min
Max
Min
7.189
7.557
7.189
320
520
320
520
kHz
see Figure 23
Max
7.557 MHz
0
18
-
-
MHz
55
-
-
-
ns
0
8
-
-
MHz
Glitch filter
tgr
tsa
glitch rejection time
signal acceptance time
P1.5/RST pin
-
50
-
50
ns
any pin except
P1.5/RST
-
15
-
15
ns
P1.5/RST pin
125
-
125
-
ns
any pin except
P1.5/RST
50
-
50
-
ns
-
ns
External clock
tCHCX
clock HIGH time
see Figure 23
22
Tcy(clk) − tCLCX
22
tCLCX
clock LOW time
see Figure 23
22
Tcy(clk) − tCHCX
22
-
ns
tCLCH
clock rise time
see Figure 23
-
5
-
5
ns
tCHCL
clock fall time
see Figure 23
-
5
-
5
ns
Shift register (UART mode 0)
TXLXL
serial port clock cycle time
see Figure 22
16Tcy(clk)
-
888
-
ns
tQVXH
output data setup to clock rising edge see Figure 22
time
13Tcy(clk)
-
722
-
ns
tXHQX
output data hold after clock rising
edge time
see Figure 22
-
Tcy(clk) + 20
-
75
ns
tXHDX
input data hold after clock rising edge see Figure 22
time
-
0
-
0
ns
tXHDV
input data valid to clock rising edge
time
150
-
150
-
ns
0
CCLK⁄
6
0
3.0
MHz
-
CCLK⁄
4
-
4.5
MHz
see Figure 22
SPI interface
fSPI
SPI operating frequency
slave
master
TSPICYC
SPI cycle time
slave
see Figure 24,
25, 26, 27
6⁄
CCLK
-
333
-
ns
4⁄
CCLK
-
222
-
ns
see Figure 26,
27
250
-
250
-
ns
see Figure 26,
27
250
-
250
-
ns
master
tSPILEAD
SPI enable lead time
slave
tSPILAG
SPI enable lag time
slave
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
57 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
Table 14: Dynamic characteristics (18 MHz) …continued
VDD = 3.0 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2]
Symbol
Parameter
Conditions
Variable clock
Min
tSPICLKH
SPICLK HIGH time
see Figure 24,
25, 26, 27
master
slave
tSPICLKL
SPICLK LOW time
see Figure 24,
25, 26, 27
master
Max
Min
Max
Unit
2⁄
CCLK
-
111
-
ns
3⁄
CCLK
-
167
-
ns
2⁄
CCLK
-
111
-
ns
CCLK
-
167
-
ns
3⁄
slave
fosc = 18 MHz
tSPIDSU
SPI data setup time
see Figure 24,
25, 26, 27
100
-
100
-
ns
tSPIDH
SPI data hold time
see Figure 24,
25, 26, 27
100
-
100
-
ns
tSPIA
SPI access time
see Figure 26,
27
0
80
0
80
ns
see Figure 26,
27
0
160
-
160
ns
see Figure 24,
25, 26, 27
-
160
-
160
ns
slave
tSPIDIS
SPI disable time
slave
tSPIDV
SPI enable to output data valid time
slave
master
tSPIOH
SPI output data hold time
see Figure 24,
25, 26, 27
tSPIR
SPI rise time
see Figure 24,
25, 26, 27
SPI outputs (SPICLK, MOSI,
MISO)
SPI inputs (SPICLK, MOSI, MISO,
SS)
tSPIF
SPI fall time
see Figure 24,
25, 26, 27
SPI outputs (SPICLK, MOSI,
MISO)
SPI inputs (SPICLK, MOSI, MISO)
-
111
-
111
ns
0
-
0
-
ns
-
100
-
100
ns
-
2000
-
2000
ns
-
100
-
100
ns
-
2000
-
2000
ns
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
58 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
11.1 Waveforms
TXLXL
clock
tXHQX
tQVXH
output data
0
write to SBUF
input data
1
2
3
4
5
6
7
tXHDX
set TI
tXHDV
valid
valid
valid
valid
valid
valid
valid
valid
clear RI
set RI
002aaa906
Fig 22. Shift register mode timing
VDD − 0.5 V
0.45 V
0.2VDD + 0.9 V
0.2VDD − 0.1 V
tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 23. External clock timing
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
59 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
SS
TSPICYC
tSPIF
tSPICLKH
tSPICLKL
tSPIR
SPICLK
(CPOL = 0)
(output)
tSPIF
tSPIR
tSPICLKL
tSPICLKH
SPICLK
(CPOL = 1)
(output)
tSPIDSU
MISO
(input)
tSPIDH
LSB/MSB in
MSB/LSB in
tSPIDV
MOSI
(output)
tSPIOH
tSPIDV
tSPIR
tSPIF
master MSB/LSB out
master LSB/MSB out
002aaa908
Fig 24. SPI master timing (CPHA = 0)
SS
TSPICYC
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 0)
(output)
tSPIF
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(output)
tSPIDSU
MISO
(input)
tSPIDH
LSB/MSB in
MSB/LSB in
tSPIDV
MOSI
(output)
tSPICLKL
tSPIOH
tSPIDV
tSPIF
tSPIDV
tSPIR
master MSB/LSB out
master LSB/MSB out
002aaa909
Fig 25. SPI master timing (CPHA = 1)
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
60 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
SS
tSPIR
tSPIR
TSPICYC
tSPILEAD
tSPIF
tSPICLKH
tSPICLKL
tSPIR
tSPILAG
SPICLK
(CPOL = 0)
(input)
tSPIF
tSPICLKL
tSPICLKH
SPICLK
(CPOL = 1)
(input)
tSPIA
MISO
(output)
tSPIOH
tSPIOH
tSPIDV
tSPIDV
slave MSB/LSB out
tSPIDSU
MOSI
(input)
tSPIR
tSPIDH
tSPIOH
tSPIDIS
slave LSB/MSB out
tSPIDSU
tSPIDSU
MSB/LSB in
not defined
tSPIDH
LSB/MSB in
002aaa910
Fig 26. SPI slave timing (CPHA = 0)
SS
tSPIR
tSPILEAD
tSPIR
TSPICYC
tSPIF
tSPICLKL
tSPIR
tSPILAG
tSPICLKH
SPICLK
(CPOL = 0)
(input)
tSPIF
tSPICLKL
SPICLK
(CPOL = 1)
(input)
tSPIR
tSPICLKH
tSPIOH
tSPIOH
tSPIDV
tSPIDV
tSPIOH
tSPIDV
tSPIDIS
tSPIA
MISO
(output)
not defined
tSPIDSU
MOSI
(input)
slave LSB/MSB out
slave MSB/LSB out
tSPIDH
tSPIDSU
MSB/LSB in
tSPIDSU
tSPIDH
LSB/MSB in
002aaa911
Fig 27. SPI slave timing (CPHA = 1)
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
61 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
11.2 ISP entry mode
Table 15: Dynamic characteristics, ISP entry mode
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
Parameter
tVR
tRH
tRL
Conditions
Min
Typ
Max
Unit
VDD active to RST active delay time
50
-
-
µs
RST HIGH time
1
-
32
µs
RST LOW time
1
-
-
µs
VDD
tVR
tRH
RST
tRL
002aaa912
Fig 28. ISP entry waveform
12. Other characteristics
12.1 Comparator electrical characteristics
Table 16: Comparator electrical characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
Parameter
VIO
input offset voltage
VIC
common-mode input voltage
CMRR
common-mode rejection ratio
Conditions
[1]
Min
Typ
Max
Unit
-
-
±20
mV
0
-
VDD − 0.3
V
-
-
−50
dB
tres(tot)
total response time
-
250
500
ns
t(CE-OV)
chip enable to output valid time
-
-
10
µs
ILI
input leakage current
-
-
±10
µA
[1]
0 V < VI < VDD
This parameter is characterized, but not tested in production.
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
62 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
13. ADC electrical characteristics
Table 17: ADC electrical characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
All limits valid for an external source impedance of less than 10 kΩ.
Symbol
Parameter
Min
Typ
Max
Unit
VIA
analog input voltage
Conditions
VSS − 0.2
-
VSS + 0.2
V
Cia
analog input capacitance
-
-
15
pF
ED
differential linearity error
-
-
±1
LSB
INL
integral non-linearity
-
-
±1
LSB
Eoffset
offset error
-
-
±2
LSB
EG
gain error
-
-
±1
%
Eu(tot)
total unadjusted error
-
-
±2
LSB
MCTC
channel-to-channel matching
-
-
±1
LSB
αct(port)
crosstalk between port inputs
-
-
−60
dB
SRin
input slew rate
-
-
100
V/ms
Tcy(ADC)
ADC clock cycle time
111
-
3125
ns
tADC
ADC conversion time
-
-
36Tcy(ADC)
µs
0 kHz to 100 kHz
ADC enabled
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
63 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
14. Package outline
LQFP64: plastic low profile quad flat package; 64 leads; body 14 x 14 x 1.4 mm
SOT791-1
c
y
X
A
33
48
49
32
ZE
e
E HE
A
A2
(A 3)
A1
w M
θ
bp
Lp
L
pin 1 index
64
detail X
17
16
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.45
0.30
0.20
0.09
14.1
13.9
14.1
13.9
0.8
HD
HE
16.15 16.15
15.85 15.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.2
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
7o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT791-1
136E18
MS-026
ED-7311EC
EUROPEAN
PROJECTION
ISSUE DATE
02-10-22
Fig 29. Package outline SOT791-1 (LQFP64)
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
64 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
15. Abbreviations
Table 18:
Acronym list
Acronym
Description
ADC
Analog to Digital Converter
CPU
Central Processing Unit
EPROM
Erasable Programmable Read-Only Memory
EEPROM
Electrically Erasable Programmable Read-Only Memory
EMI
Electro-Magnetic Interference
ISP
In-System Programming
LCD
Liquid Crystal Display
LED
Light Emitting Diode
PWM
Pulse Width Modulator
RAM
Random Access Memory
RC
Resistance-Capacitance
SFR
Special Function Register
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver/Transmitter
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
65 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
16. Revision history
Table 19:
Revision history
Document ID
Release date
Data sheet status
Change notice
Doc. number
Supersedes
P89LPC9408_1
20051216
Product data sheet
-
-
-
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
66 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
17. Data sheet status
Level
Data sheet status [1]
Product status [2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
makes no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
20. Trademarks
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I2C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.
19. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: [email protected]
P89LPC9408_1
Product data sheet
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Rev. 01 — 16 December 2005
67 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
22. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1
Principal features . . . . . . . . . . . . . . . . . . . . . . . 1
2.2
Additional features . . . . . . . . . . . . . . . . . . . . . . 1
3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
3.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
Functional description . . . . . . . . . . . . . . . . . . 10
7.1
Special function registers . . . . . . . . . . . . . . . . 10
7.2
Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3.1
Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 19
7.3.2
CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 19
7.3.3
Low speed oscillator option . . . . . . . . . . . . . . 19
7.3.4
Medium speed oscillator option . . . . . . . . . . . 19
7.3.5
High speed oscillator option . . . . . . . . . . . . . . 19
7.3.6
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4
On-chip RC oscillator option . . . . . . . . . . . . . . 20
7.5
Watchdog oscillator option . . . . . . . . . . . . . . . 20
7.6
External clock input option . . . . . . . . . . . . . . . 20
7.7
CPU Clock (CCLK) wake-up delay . . . . . . . . . 21
7.8
CCLK modification: DIVM register . . . . . . . . . 21
7.9
Low power select . . . . . . . . . . . . . . . . . . . . . . 21
7.10
Memory organization . . . . . . . . . . . . . . . . . . . 22
7.11
Data RAM arrangement . . . . . . . . . . . . . . . . . 22
7.12
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.12.1
External interrupt inputs . . . . . . . . . . . . . . . . . 23
7.13
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.13.1
Port configurations . . . . . . . . . . . . . . . . . . . . . 25
7.13.1.1 Quasi-bidirectional output configuration . . . . . 25
7.13.1.2 Open-drain output configuration . . . . . . . . . . . 25
7.13.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 25
7.13.1.4 Push-pull output configuration . . . . . . . . . . . . 26
7.13.2
Port 0 analog functions . . . . . . . . . . . . . . . . . . 26
7.13.3
Additional port features. . . . . . . . . . . . . . . . . . 26
7.14
Power monitoring functions. . . . . . . . . . . . . . . 26
7.14.1
Brownout detection . . . . . . . . . . . . . . . . . . . . . 26
7.14.2
Power-on detection . . . . . . . . . . . . . . . . . . . . . 27
7.15
Power reduction modes . . . . . . . . . . . . . . . . . 27
7.15.1
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.15.2
Power-down mode . . . . . . . . . . . . . . . . . . . . . 27
7.15.3
Total Power-down mode . . . . . . . . . . . . . . . . . 27
7.16
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.16.1
7.17
7.17.1
7.17.2
7.17.3
7.17.4
7.17.5
7.17.6
7.18
7.19
7.19.1
7.19.2
7.19.3
7.19.4
7.19.5
7.19.6
7.19.7
7.19.8
7.19.9
7.20
7.20.1
7.20.2
7.20.3
7.20.4
7.20.5
7.20.6
7.20.7
7.20.8
7.20.9
7.20.10
7.21
7.22
7.22.1
7.23
7.23.1
7.23.2
7.23.3
7.24
7.25
7.26
7.26.1
7.26.2
7.27
7.27.1
7.27.2
7.27.3
Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers/counters 0 and 1 . . . . . . . . . . . . . . . .
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer overflow toggle output . . . . . . . . . . . . .
RTC/system timer. . . . . . . . . . . . . . . . . . . . . .
CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCU Clock (CCUCLK) . . . . . . . . . . . . . . . . . .
CCU clock prescaling . . . . . . . . . . . . . . . . . . .
Basic timer operation . . . . . . . . . . . . . . . . . . .
Output compare . . . . . . . . . . . . . . . . . . . . . . .
Input capture . . . . . . . . . . . . . . . . . . . . . . . . .
PWM operation . . . . . . . . . . . . . . . . . . . . . . .
Alternating output mode . . . . . . . . . . . . . . . . .
PLL operation. . . . . . . . . . . . . . . . . . . . . . . . .
CCU interrupts . . . . . . . . . . . . . . . . . . . . . . . .
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud rate generator and selection . . . . . . . . .
Framing error . . . . . . . . . . . . . . . . . . . . . . . . .
Break detect . . . . . . . . . . . . . . . . . . . . . . . . . .
Double buffering . . . . . . . . . . . . . . . . . . . . . . .
Transmit interrupts with double buffering
enabled (modes 1, 2 and 3) . . . . . . . . . . . . . .
The 9th bit (bit 8) in double buffering
(modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . .
I2C-bus serial interface. . . . . . . . . . . . . . . . . .
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical SPI configurations . . . . . . . . . . . . . . .
Analog comparators . . . . . . . . . . . . . . . . . . . .
Internal reference voltage. . . . . . . . . . . . . . . .
Comparator interrupt . . . . . . . . . . . . . . . . . . .
Comparators and power reduction modes . . .
Keypad Interrupt (KBI) . . . . . . . . . . . . . . . . . .
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . .
Additional features . . . . . . . . . . . . . . . . . . . . .
Software reset . . . . . . . . . . . . . . . . . . . . . . . .
Dual data pointers . . . . . . . . . . . . . . . . . . . . .
LCD controller . . . . . . . . . . . . . . . . . . . . . . . .
General description . . . . . . . . . . . . . . . . . . . .
Functional description . . . . . . . . . . . . . . . . . .
LCD bias voltages . . . . . . . . . . . . . . . . . . . . .
28
28
29
29
29
29
29
29
29
29
30
30
30
30
30
30
32
32
33
33
33
33
34
34
34
34
34
35
35
35
35
38
39
40
41
41
41
42
42
43
43
43
43
43
44
44
continued >>
P89LPC9408_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 16 December 2005
68 of 69
P89LPC9408
Philips Semiconductors
8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC
7.27.4
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27.5
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27.6
Display register . . . . . . . . . . . . . . . . . . . . . . . .
7.27.7
Segment outputs. . . . . . . . . . . . . . . . . . . . . . .
7.27.8
Backplane outputs . . . . . . . . . . . . . . . . . . . . .
7.27.9
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27.10 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27.11 Output bank selector. . . . . . . . . . . . . . . . . . . .
7.27.12 Input bank selector . . . . . . . . . . . . . . . . . . . . .
7.27.13 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27.13.1 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . .
7.27.14 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27.15 I2C-bus slave addresses . . . . . . . . . . . . . . . . .
7.28
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . .
7.29
Flash program memory. . . . . . . . . . . . . . . . . .
7.29.1
General description. . . . . . . . . . . . . . . . . . . . .
7.29.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.29.3
Flash organization . . . . . . . . . . . . . . . . . . . . .
7.29.4
Using flash as data storage . . . . . . . . . . . . . .
7.29.5
Flash programming and erasing . . . . . . . . . . .
7.29.6
In-Circuit Programming. . . . . . . . . . . . . . . . . .
7.29.7
In-Application Programming . . . . . . . . . . . . . .
7.29.8
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.29.9
Power-on reset code execution. . . . . . . . . . . .
7.29.10 Hardware activation of the boot loader . . . . . .
7.30
User configuration bytes . . . . . . . . . . . . . . . . .
7.31
User sector security bytes . . . . . . . . . . . . . . .
8
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1
General description. . . . . . . . . . . . . . . . . . . . .
8.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . .
8.4
ADC operating modes . . . . . . . . . . . . . . . . . .
8.4.1
Fixed channel, single conversion mode . . . . .
8.4.2
Fixed channel, continuous conversion mode .
8.4.3
Auto scan, single conversion mode . . . . . . . .
8.4.4
Auto scan, continuous conversion mode . . . .
8.4.5
Dual channel, continuous conversion mode . .
8.4.6
Single step mode . . . . . . . . . . . . . . . . . . . . . .
8.5
Conversion start modes . . . . . . . . . . . . . . . . .
8.5.1
Timer triggered start . . . . . . . . . . . . . . . . . . . .
8.5.2
Start immediately . . . . . . . . . . . . . . . . . . . . . .
8.5.3
Edge triggered . . . . . . . . . . . . . . . . . . . . . . . .
8.6
Boundary limits interrupt. . . . . . . . . . . . . . . . .
8.7
Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . .
8.8
Power-down and Idle mode . . . . . . . . . . . . . .
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .
10
Static characteristics. . . . . . . . . . . . . . . . . . . .
11
Dynamic characteristics . . . . . . . . . . . . . . . . .
11.1
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2
ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . .
44
44
44
45
45
45
45
45
45
45
46
46
46
46
47
47
47
47
47
48
48
48
48
49
49
49
49
50
50
50
50
51
51
51
51
51
51
52
52
52
52
52
52
52
52
53
53
55
59
62
12
12.1
13
14
15
16
17
18
19
20
21
Other characteristics . . . . . . . . . . . . . . . . . . .
Comparator electrical characteristics . . . . . . .
ADC electrical characteristics . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Data sheet status. . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
62
62
63
64
65
66
67
67
67
67
67
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 16 December 2005
Document number: P89LPC9408_1
Published in the Netherlands