P89LPC915/916/917 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter Rev. 05 — 15 December 2009 Product data sheet 1. General description The P89LPC915/916/917 are single-chip microcontrollers, available in low-cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC915/916/917 in order to reduce component count, board space, and system cost. 2. Features 2.1 Principal features n 2 kB byte-erasable flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. n 256-byte RAM data memory. n Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC917) may be configured to toggle a port output upon timer overflow or to become a PWM output. n 23-bit system timer that can also be used as a Real-Time clock. n 4-input multiplexed 8-bit A/D converter/single DAC output. Two analog comparators with selectable reference. n Enhanced UART with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities. n SPI communication port (P89LPC916). n Internal RC oscillator option allows operation without external oscillator components. The RC oscillator (factory calibrated to ±1 %) option is selectable and fine tunable. n 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). n Up to 14 I/O pins when using internal oscillator and reset options (P89LPC916, P89LPC917). 2.2 Additional features n 14-pin (P89LPC915) and 16-pin (P89LPC916, P89LPC917) TSSOP packages. n A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. n In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage. P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core n Serial Flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. n Watchdog timer with separate on-chip oscillator, requiring no external components. The Watchdog prescaler is selectable from 8 values. n Low voltage brownout detect allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. n Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 µA (total power-down with voltage comparators disabled). n Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. n Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. n Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. n LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip. n Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. n Only power and ground connections are required to operate the P89LPC915/916/917 when internal reset option is selected. n Four interrupt priority levels. n Five (P89LPC916), six (P89LPC915), or seven (P89LPC917) keypad interrupt inputs. n Second data pointer. n Schmitt trigger port inputs. n Emulation support. 3. Product comparison overview Table 1 highlights the differences between these three devices. For a complete list of device features, please see Section 2 “Features”. Table 1. Product comparison overview Type number Comparator 2 output SPI T1 toggle/PWM CLKOUT KBI P89LPC915 X - - - X 6 P89LPC916 - X - - - 5 P89LPC917 X - X X X 7 P89LPC915_916_917_5 Product data sheet INT1 © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 2 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 4. Ordering information Table 2. Ordering information Type number Package Name Description Version P89LPC915FDH TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 P89LPC915FN DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 P89LPC915HDH TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 P89LPC916FDH TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 P89LPC917FDH TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 4.1 Ordering options Table 3. Ordering options[1] Type number Temperature range Frequency P89LPC915FDH −40 °C to +85 °C 0 MHz to 18 MHz P89LPC915FN P89LPC916FDH P89LPC917FDH P89LPC915HDH [1] −40 °C to +125 °C Please contact your local NXP sales office for availability of extended temperature (−40 °C to +125 °C) versions of the P89LPC916 and P89LPC917 devices. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 3 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 5. Block diagram P89LPC915 HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU TXD 2 kB CODE FLASH UART RXD internal bus SCL I2C 256 BYTE DATA RAM SDA P1[5:0] PORT 1 CONFIGURABLE I/O ADC1/DAC1 P0[5:0] PORT 0 CONFIGURABLE I/O REAL TIME CLOCK/ SYSTEM TIMER AD10 AD11 AD12 AD13 DAC1 TIMER 0 TIMER 1 T0 KEYPAD INTERRUPT ANALOG COMPARATORS WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER CMP2 CIN2B CIN2A CIN1A CIN1B CMPREF CPU clock POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) external clock input ON-CHIP RC OSCILLATOR 002aaa822 Fig 1. P89LPC915 block diagram P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 4 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core P89LPC916 HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU TXD 2 kB CODE FLASH UART RXD internal bus SCL I2C 256 BYTE DATA RAM SDA P2[5:2] PORT 2 CONFIGURABLE I/O ADC1/DAC1 P1.5, P1[3:0] PORT 1 CONFIGURABLE I/O SPI P0[5:1] PORT 0 CONFIGURABLE I/O REAL TIME CLOCK/ SYSTEM TIMER AD10 AD11 AD12 AD13 DAC1 SPICLK MOSI MISO SS TIMER 0 TIMER 1 T0 KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER CIN2B CIN2A CIN1A CIN1B CMPREF ANALOG COMPARATORS CPU clock POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) external clock input ON-CHIP RC OSCILLATOR 002aaa823 Fig 2. P89LPC916 block diagram P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 5 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core P89LPC917 HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU TXD 2 kB CODE FLASH UART RXD internal bus SCL I2C 256 BYTE DATA RAM SDA P2.2 PORT 2 CONFIGURABLE I/O ADC1/DAC1 P1[5:0] PORT 1 CONFIGURABLE I/O REAL TIME CLOCK/ SYSTEM TIMER P0.7, P[5:0] PORT 0 CONFIGURABLE I/O TIMER 0 TIMER 1 AD10 AD11 AD12 AD13 DAC1 T0 T1 CMP2 CIN2B CIN2A CIN1A CIN1B CMPREF ANALOG COMPARATORS KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER CPU clock POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) external clock input ON-CHIP RC OSCILLATOR clkout 002aaa824 Fig 3. P89LPC917 block diagram P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 6 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 6. Functional diagram VDD DAC1 VSS KBI0 CMP2 TXD AD10 KBI1 CIN2B RXD AD11 KBI2 CIN2A AD12 KBI3 CIN1B AD13 KBI4 CIN1A INT1 CLKIN KBI5 CMPREF RST PORT 0 P89LPC915 PORT 1 T0 SCL INT0 SDA 002aaa828 Fig 4. P89LPC915 functional diagram VDD VSS TXD DAC1 AD10 KBI1 CIN2B AD11 KBI2 CIN2A AD12 KBI3 CIN1B AD13 KBI4 CIN1A CLKIN KBI5 CMPREF RXD PORT 1 PORT 0 P89LPC916 T0 SCL INT0 SDA RST MOSI MIS0 PORT 2 SS SPICLK 002aaa829 Fig 5. P89LPC916 functional diagram P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 7 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core VDD DAC1 VSS KBI0 CMP2 TXD AD10 KBI1 CIN2B RXD AD11 KBI2 CIN2A AD12 KBI3 CIN1B AD13 KBI4 CIN1A INT1 CLKIN KBI5 CMPREF RST CLKOUT KBI7 T1 PORT 0 PORT 1 P89LPC917 T0 SCL INT0 SDA PORT 2 002aaa830 Fig 6. P89LPC917 functional diagram P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 8 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 7. Pinning information 7.1 Pinning P0.1/CIN2B/KBI1/AD10 1 14 P0.2/CIN2A/KBI2/AD11 P0.0/CMP2/KBI0 2 13 P0.3/CIN1B/KBI3/AD12 P1.5/RST 3 VSS 4 P1.4/INT1 5 10 VDD P1.3/INT0/SDA 6 9 P1.0/TXD P1.2/T0/SCL 7 8 P1.1/RXD 12 P0.4/CIN1A/KBI4/AD13/DAC1 P89LPC915 11 P0.5/CMPREF/KBI5/CLKIN 002aaa825 Fig 7. P89LPC915 TSSOP14 pin configuration P0.1/CIN2B/KBI1/AD10 1 14 P0.2/CIN2A/KBI2/AD11 P0.0/CMP2/KBI0 2 13 P0.3/CIN1B/KBI3/AD12 P1.5/RST 3 12 P0.4/CIN1A/KBI4/AD13/DAC1 VSS 4 P89LPC915 11 P0.5/CMPREF/KBI5/CLKIN 10 VDD P1.4/INT1 5 P1.3/INT0/SDA 6 9 P1.0/TXD P1.2/T0/SCL 7 8 P1.1/RXD 002aaf085 Fig 8. P89LPC915 DIP14 pin configuration P0.1/CIN2B/KBI1/AD10 1 16 P0.2/CIN2A/KBI2/AD11 P2.4/SS 2 15 P0.3/CIN1B/KBI3/AD12 P1.5/RST 3 14 P0.4/CIN1A/KBI4/AD13/DAC1 VSS 4 P2.3/MISO 5 P2.2/MOSI 6 11 P2.5/SPICLK P1.3/INT0/SDA 7 10 P1.0/TXD P1.2/T0/SCL 8 P89LPC916 13 P0.5/CMPREF/KBI5/CLKIN 12 VDD 9 P1.1/RXD 002aaa826 Fig 9. P89LPC916 TSSOP16 pin configuration P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 9 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core P0.1/CIN2B/KBI1/AD10 1 16 P0.2/CIN2A/KBI2/AD11 P0.0/CMP2/KBI0 2 15 P0.3/CIN1B/KBI3/AD12 P1.5/RST 3 14 P0.4/CIN1A/KBI4/AD13/DAC1 VSS 4 P2.2 5 P1.4/INT1 6 11 P0.7/T1/KBI7/CLKOUT P1.3/INT0/SDA 7 10 P1.0/TXD P1.2/T0/SCL 8 P89LPC917 13 P0.5/CMPREF/KBI5/CLKIN 12 VDD 9 P1.1/RXD 002aaa827 Fig 10. P89LPC917 TSSOP16 pin configuration P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 10 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 7.2 Pin description Table 4. P89LPC915 pin description Symbol Pin P0.0 to P0.5 Type Description I/O Port 0: Port 0 is a 6-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P0.0/CMP2/KBI0 P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/AD13/ DAC1 P0.5/CMPREF/KBI5/CLKIN P1.0 to P1.5 2 1 14 13 12 11 I/O P0.0 — Port 0 bit 0. O CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0. I/O P0.1 — Port 0 bit 1. I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD10 — ADC1 channel 0 analog input. I/O P0.2 — Port 0 bit 2. I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — ADC1 channel 1 analog input. I/O P0.3 — Port 0 bit 3. I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — ADC1 channel 2 analog input. I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — ADC1 channel 3 analog input. I DAC1 — DAC1 analog output. I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock input. I/O, I Port 1: Port 1 is a 6-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. [1] All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 11 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 4. P89LPC915 pin description …continued Symbol Pin Type Description P1.0/TXD 9 I/O P1.0 — Port 1 bit 0. O TXD — Transmitter output for serial port. P1.1/RXD 8 I/O P1.1 — Port 1 bit 1. I RXD — Receiver input for serial port. P1.2/T0/SCL 7 I/O P1.2 — Port 1 bit 2 (open-drain when used as output). I/O T0 — Timer/counter 0 external count input or overflow output (open-drain when used as output). I/O SCL — I2C serial clock input/output. I/O P1.3 — Port 1 bit 3 (open-drain when used as output). I INT0 — External interrupt 0 input. I/O SDA — I2C serial data input/output. P1.3/INT0/SDA 6 5 P1.4/INT1 3 P1.5/RST I P1.4 — Port 1 bit 4. I INT1 — External interrupt 1 input. I P1.5 — Port 1 bit 5 (input only). I RST — External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. VSS 4 I Ground: 0 V reference. VDD 10 I Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. [1] Input/output for P1.0 to P1.4. Input for P1.5. Table 5. P89LPC916 pin description Symbol P0.0 to P0.5 Pin Type Description I/O Port 0: Port 0 is an 6-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 12 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 5. P89LPC916 pin description …continued Symbol Pin Type Description P0.1/CIN2B/KBI1/AD10 1 I/O P0.1 — Port 0 bit 1. I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 16 15 P0.4/CIN1A/KBI4/AD13/DAC1 14 P0.5/CMPREF/KBI5/CLKIN 13 I AD10 — ADC1 channel 0 analog input. I/O P0.2 — Port 0 bit 2. I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — ADC1 channel 1 analog input. I/O P0.3 — Port 0 bit 3. I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — ADC1 channel 2 analog input. I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — ADC1 channel 3 analog input. O DAC1 — DAC1 analog output. I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock input. I/O, I Port 1: Port 1 is an 6-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. P1.0 to P1.5 [1] All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: P1.0/TXD P1.1/RXD P1.2/T0/SCL P1.3/INT0/SDA P1.5/RST 10 9 8 7 3 I/O P1.0 — Port 1 bit 0. O TXD — Transmitter output for serial port. I/O P1.1 — Port 1 bit 1. I RXD — Receiver input for serial port. I/O P1.2 — Port 1 bit 2 (open-drain when used as output). I/O T0 — Timer/counter 0 external count input or overflow output (open-drain when used as output). I/O SCL — I2C serial clock input/output. I/O P1.3 — Port 1 bit 3 (open-drain when used as output). I INT0 — External interrupt 0 input. I/O SDA — I2C serial data input/output. I P1.5 — Port 1 bit 5 (input only). P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 13 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 5. P89LPC916 pin description …continued Symbol Pin Type Description I P2.2 to P2.5 RST — External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below: P2.2/MOSI P2.3/MISO P2.4/SS P2.5/SPICLK 6 5 2 11 I/O P2.2 — Port 2 bit 2. I/O MOSI — SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input. I/O P2.3 — Port 2 bit 3. I/O MISO — When configured as master, this pin is input, when configured as slave, this pin is output. I/O P2.4 — Port 2 bit 4. I/O SS — SPI Slave select. I/O P2.5 — Port 2 bit 5. I/O SPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input. VSS 4 I Ground: 0 V reference. VDD 12 I Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. [1] Input/output for P1.0 to P1.3. Input for P1.5. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 14 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 6. P89LPC917 pin description Symbol Pin P0.0 to P0.5, P0.7 Type Description I/O Port 0: Port 0 is a 7-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P0.0/CMP2/KBI0 P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/AD13/ DAC1 P0.5/CMPREF/KBI5 2 1 16 15 14 13 I/O P0.0 — Port 0 bit 0. O CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0. I/O P0.1 — Port 0 bit 1. I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD10 — ADC1 channel 0 analog input. I/O P0.2 — Port 0 bit 2. I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — ADC1 channel 1 analog input. I/O P0.3 — Port 0 bit 3. I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — ADC1 channel 2 analog input. I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — ADC1 channel 3 analog input. O DAC1 — DAC1 analog output. I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock input. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 15 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 6. P89LPC917 pin description …continued Symbol Pin Type Description P0.7/T1/KBI7/CLKOUT 11 I/O P0.7 — Port 0 bit 7. I/O T1 — Timer/counter 1 external count input or overflow output. I KBI7 — Keyboard input 7. O CLKOUT — Clock output. I/O, I Port 1: Port 1 is a 6-bit I/O port with a user-configurable output type, [1] except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. P1.0 to P1.5 All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: P1.0/TXD 10 I/O P1.0 — Port 1 bit 0. O TXD — Transmitter output for serial port. P1.1/RXD 9 I/O P1.1 — Port 1 bit 1. I RXD — Receiver input for serial port. P1.2/T0/SCL 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output). I/O T0 — Timer/counter 0 external count input or overflow output (open-drain when used as output). I/O SCL — I2C serial clock input/output. I/O P1.3 — Port 1 bit 3 (open-drain when used as output). I INT0 — External interrupt 0 input. I/O SDA — I2C serial data input/output. P1.3/INT0/SDA P1.4/INT1 P1.5/RST 7 6 3 I P1.4 — Port 1 bit 4. I INT1 — External interrupt 1 input. I P1.5 — Port 1 bit 5 (input only). I RST — External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 16 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 6. P89LPC917 pin description …continued Symbol Pin P2.2 5 VSS 4 I Ground: 0 V reference. VDD 12 I Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Type Description Port 2: Port 2 is a single bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of this Port 2 pin as an input and output depends upon the port configuration selected. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. This pin has a Schmitt triggered input. [1] Input/output for P1.0 to P1.4. Input for P1.5. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 17 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8. Functional description 8.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. • SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows: – ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. – ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 18 of 75 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 7. P89LPC915 special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 E6 E5 Reset value LSB E4 E3 E2 E1 Hex Binary 00 0000 0000 ADCS10 00 0000 0000 E0 E0H ADCON1 ADC control register 1 97H ENBI1 ENADCI 1 TMM1 EDGE1 ADCI1 ADINS ADC input select A3H ADI13 ADI12 ADI11 ADI10 - - - - 00 0000 0000 ADMODA ADC mode register A C0H BNDI1 BURST1 SCC1 SCAN1 - - - - 00 0000 0000 ADMODB ADC mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x 0000 AD1BH A/D_1 boundary high register C4H FF 1111 1111 AD1BL A/D_1 boundary low register BCH 00 0000 0000 AD1DAT0 A/D_1 data register 0 D5H 00 0000 0000 AD1DAT1 A/D_1 data register 1 D6H 00 0000 0000 AD1DAT2 A/D_1 data register 2 D7H 00 0000 0000 AD1DAT3 A/D_1 data register 3 F5H 00 0000 0000 AUXR1 Auxiliary function register A2H 00 0000 00x0 B* B register F0H 00 0000 0000 BRGR0 Baud rate generator rate low BEH 00 0000 0000 BRGR1 Baud rate generator rate high BFH 00 0000 0000 xxxx xx00 Bit address ENADC1 ADCS11 CLKLP EBRR - ENT0 SRST 0 - DPS F7 F6 F5 F4 F3 F2 F1 F0 BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00[2] CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00[1] xx00 0000 CMF2 00[1] xx00 0000 00 0000 0000 CMP2 Comparator 2 control register ADH DIVM CPU clock divide-by-M control 95H DPTR Data pointer (2 bytes) - - CE2 CP2 CN2 OE2 CO2 19 of 75 © NXP B.V. 2009. All rights reserved. DPH Data pointer high 83H 00 0000 0000 DPL Data pointer low 82H 00 0000 0000 FMADRH Program flash address high E7H 00 0000 0000 FMADRL Program flash address low E6H 00 0000 0000 P89LPC915/916/917 Accumulator 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 ACC* xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name FMCON Description SFR Bit functions and addresses addr. MSB Reset value LSB Program flash control (Read) E4H BUSY - - - HVA HVE SV OI Program flash control (Write) E4H FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 FMCMD. 3 FMCMD. 2 FMCMD. 1 FMCMD. 0 FMDATA Program flash data E5H I2ADR I2C slave address register DBH Bit address I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC DF DE DD DC DB DA D9 D8 - I2EN STA STO SI AA - CRSEL Hex Binary 70 0111 0000 00 0000 0000 00 0000 0000 00 x000 00x0 I2C control register D8H I2DAT I2C DAH I2SCLH Serial clock generator/SCL duty cycle register high DDH 00 0000 0000 I2SCLL Serial clock generator/SCL duty cycle register low DCH 00 0000 0000 I2STAT I2C status register D9H F8 1111 1000 00 0000 0000 00[1] 00x0 0000 IEN0* IEN1* Interrupt enable 0 Interrupt enable 1 STA.3 STA.2 STA.1 STA.0 0 0 0 AF AE AD AC AB AA A9 A8 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 Bit address EF EE ED EC EB EA E9 E8 EAD EST - - - EC EKBI EI2C BF BE BD BC BB BA B9 B8 - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00[1] x000 0000 00[1] x000 0000 E8H Bit address IP0* IP0H Interrupt priority 0 Interrupt priority 0 high B8H B7H Bit address IP1* IP1H Interrupt priority 1 Interrupt priority 1 high F8H F7H 20 of 75 © NXP B.V. 2009. All rights reserved. KBCON Keypad control register 94H KBMASK Keypad interrupt mask register 86H KBPATN Keypad pattern register - PWDRT H PBOH PSH/ PSRH PT1H PX1H PT0H PX0H FF FE FD FC FB FA F9 F8 PAD PST - - - PC PKBI PI2C 00[1] 00x0 0000 PI2CH 00[1] 00x0 0000 KBIF 00[1] xxxx xx00 00 0000 0000 FF 1111 1111 PADH - PSTH - - - - PCH - PKBIH PATN _SEL P89LPC915/916/917 STA.4 Bit address 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 I2CON* data register NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 7. P89LPC915 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Bit address P0* Port 0 80H Bit address P1* Port 1 90H Bit address Reset value LSB 87 86 85 84 83 82 81 80 - - CMPREF /KB5 CIN1A /KB4 CIN1B /KB3 CIN2A /KB2 CIN2B /KB1 CMP2 /KB0 97 96 95 94 93 92 91 90 - - RST INT1 INT0/ SDA T0/SCL RXD TXD B7 B6 B5 B4 B3 B2 B1 B0 Hex Binary [1] [1] Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] 1111 1111 P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1] P1M1 Port 1 output mode 1 91H - - - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1] 11x1 xx11 P1M2 Port 1 output mode 2 92H - - - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00[1] PCON Power control register 87H SMOD1 SMOD0 BOPD Power control register A B5H BOI GF1 GF0 PMOD1 PMOD0 0000 0000 00x0 xx00 00 0000 0000 00[1] 0000 0000 RTCPD - VCPD ADPD I2PD - SPD - Bit address D7 D6 D5 D4 D3 D2 D1 D0 F0 RS1 RS0 OV F1 P 00 0000 0000 - 00 xx00 000x [3] PSW* Program status word D0H CY AC PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60[1][ 011x xx00 6] RTCH RTC register high D2H 00[6] 0000 0000 0000 0000 RTCL RTC register low D3H 00[6] SADDR Serial port address register A9H 00 0000 0000 SADEN Serial port address enable B9H 00 0000 0000 SBUF Serial Port data buffer register 99H xx xxxx xxxx 9F 9E 9D 9C 9B 9A 99 98 SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 SSTAT Serial port extended status register BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 SP Stack pointer 81H 07 0000 0111 TAMOD Timer 0 and 1 auxiliary mode 8FH - - - - - - - T0M2 00 xxx0 xxx0 Bit address 21 of 75 © NXP B.V. 2009. All rights reserved. P89LPC915/916/917 RSTSRC 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 P0M1 PCONA NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 7. P89LPC915 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Bit address Reset value LSB 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Hex Binary 00 0000 0000 TCON* Timer 0 and 1 control 88H TH0 Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TL0 Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1 mode 89H 00 0000 0000 T1GATE T1C/T T1M1 NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 7. P89LPC915 special function registers …continued * indicates SFRs that are bit addressable. T1M0 T0GATE T0C/T T0M1 T0M0 Internal oscillator trim register 96H RCCLK - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [4] [6] WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H FF 1111 1111 All ports are in input only (high-impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. [4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. [5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset. 22 of 75 © NXP B.V. 2009. All rights reserved. P89LPC915/916/917 [1] 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 TRIM [5] [6] xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 8. P89LPC916 special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 E6 E5 Reset value LSB E4 E3 E2 E1 Hex Binary 00 0000 0000 ADCS10 00 0000 0000 E0 E0H ADCON1 ADC control register 1 97H ENBI1 ENADCI 1 TMM1 EDGE1 ADCI1 ADINS ADC input select A3H ADI13 ADI12 ADI11 ADI10 - - - - 00 0000 0000 ADMODA ADC mode register A C0H BNDI1 BURST1 SCC1 SCAN1 - - - - 00 0000 0000 ADMODB ADC mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x 0000 AD1BH A/D_1 boundary high register C4H FF 1111 1111 AD1BL A/D_1 boundary low register BCH 00 0000 0000 AD1DAT0 A/D_1 data register 0 D5H 00 0000 0000 AD1DAT1 A/D_1 data register 1 D6H 00 0000 0000 AD1DAT2 A/D_1 data register 2 D7H 00 0000 0000 AD1DAT3 A/D_1 data register 3 F5H 00 0000 0000 AUXR1 Auxiliary function register A2H 00 0000 00x0 B* B register F0H 00 0000 0000 BRGR0 Baud rate generator rate low BEH 00 0000 0000 BRGR1 Baud rate generator rate high BFH 00 0000 0000 xxxx xx00 Bit address ENADC1 ADCS11 CLKLP EBRR - ENT0 SRST 0 - DPS F7 F6 F5 F4 F3 F2 F1 F0 BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00[2] CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00[1] xx00 0000 CMF2 00[1] xx00 0000 00 0000 0000 CMP2 Comparator 2 control register ADH DIVM CPU clock divide-by-M control 95H DPTR Data pointer (2 bytes) - - CE2 CP2 CN2 OE2 CO2 23 of 75 © NXP B.V. 2009. All rights reserved. DPH Data pointer high 83H 00 0000 0000 DPL Data pointer low 82H 00 0000 0000 FMADRH Program flash address high E7H 00 0000 0000 FMADRL Program flash address low E6H 00 0000 0000 P89LPC915/916/917 Accumulator 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 ACC* xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name FMCON Description SFR Bit functions and addresses addr. MSB Reset value LSB Program flash control (Read) E4H BUSY - - - HVA HVE SV OI Program flash control (Write) E4H FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 FMCMD. 3 FMCMD. 2 FMCMD. 1 FMCMD. 0 FMDATA Program flash data E5H I2ADR I2C slave address register DBH Bit address I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC DF DE DD DC DB DA D9 D8 - I2EN STA STO SI AA - CRSEL Hex Binary 70 0111 0000 00 0000 0000 00 0000 0000 00 x000 00x0 I2C control register D8H I2DAT I2C DAH I2SCLH Serial clock generator/SCL duty cycle register high DDH 00 0000 0000 I2SCLL Serial clock generator/SCL duty cycle register low DCH 00 0000 0000 I2STAT I2C status register D9H F8 1111 1000 00 0000 0000 00[1] 00x0 0000 IEN0* IEN1* Interrupt enable 0 Interrupt enable 1 STA.3 STA.2 STA.1 STA.0 0 0 0 AF AE AD AC AB AA A9 A8 A8H EA EWDRT EBO ES/ESR ET1 - ET0 EX0 Bit address EF EE ED EC EB EA E9 E8 EAD EST - - ESPI EC EKBI EI2C BF BE BD BC BB BA B9 B8 - PWDRT PBO PS/PSR PT1 - PT0 PX0 00[1] x000 0000 00[1] x000 0000 E8H Bit address IP0* IP0H Interrupt priority 0 Interrupt priority 0 high B8H B7H Bit address IP1* IP1H Interrupt priority 1 Interrupt priority 1 high F8H F7H 24 of 75 © NXP B.V. 2009. All rights reserved. KBCON Keypad control register 94H KBMASK Keypad interrupt mask register 86H KBPATN Keypad pattern register - PWDRT H PBOH PSH/ PSRH PT1H - PT0H PX0H FF FE FD FC FB FA F9 F8 PAD PST - - PSPI PC PKBI PI2C 00[1] 00x0 0000 PI2CH 00[1] 00x0 0000 KBIF 00[1] xxxx xx00 00 0000 0000 FF 1111 1111 PADH - PSTH - - - PSPIH - PCH - PKBIH PATN _SEL P89LPC915/916/917 STA.4 Bit address 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 I2CON* data register NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 8. P89LPC916 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Bit address P0* Port 0 80H Bit address P1* Port 1 90H Bit address Reset value LSB 87 86 85 84 83 82 81 80 - - CMPREF /KB5 CIN1A /KB4 CIN1B /KB3 CIN2A /KB2 CIN2B /KB1 - 97 96 95 94 93 92 91 90 - - RST - INT0/ SDA T0/SCL RXD TXD A7 A6 A5 A4 A3 A2 A1 A0 - - SPICLK SS MISO MOSI - - Hex Binary [1] [1] [1] Port 2 A0H P0M1 Port 0 output mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] 1111 1111 P0M2 Port 0 output mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1] 0000 0000 91H (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1] 11x1 xx11 (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00[1] 00x0 xx00 11x1 xx11 P1M2 Port 1 output mode 1 Port 1 output mode 2 92H (P1M1.7) (P1M1.6) (P1M2.7) (P1M2.6) - P2M1 Port 2 output mode 1 A4H - - (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) - - FF[1] P2M2 Port 2 output mode 2 A5H - - (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) - - 00[1] 00x0 xx00 PCON Power control register 87H SMOD1 SMOD0 PMOD1 PMOD0 00 0000 0000 00[1] 0000 0000 Power control register A B5H RTCPD Bit address PSW* Program status word D0H PT0AD Port 0 digital input disable F6H - - BOI - VCPD ADPD D7 D6 D5 D4 CY AC F0 RS1 GF1 I2PD GF0 SPPD SPD - D3 D2 D1 D0 RS0 OV F1 P 00 0000 0000 - 00 xx00 000x [3] PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60[1][ 011x xx00 6] RTCH RTC register high D2H 00[6] 0000 0000 D3H 00[6] 0000 0000 25 of 75 © NXP B.V. 2009. All rights reserved. RTCL RTC register low SADDR Serial port address register A9H 00 0000 0000 SADEN Serial port address enable B9H 00 0000 0000 SBUF Serial Port data buffer register 99H xx xxxx xxxx 00 0000 0000 Bit address SCON* Serial port control 98H 9F 9E 9D 9C 9B 9A 99 98 SM0/FE SM1 SM2 REN TB8 RB8 TI RI P89LPC915/916/917 PCONA BOPD 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 P2* P1M1 NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 8. P89LPC916 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB INTLO CIDIS Reset value LSB SSTAT Serial port extended status register BAH SP Stack pointer 81H SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 SPSTAT SPI status register E1H SPIF WCOL - - - - - - SPDAT SPI data register E3H TAMOD Timer 0 and 1 auxiliary mode 8FH Bit address DBMOD DBISEL FE BR OE STINT - - - - - - - T0M2 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 - - IE0 IT0 Hex Binary 00 0000 0000 07 0000 0111 04 0000 0100 00 00xx xxxx 00 0000 0000 00 xxx0 xxx0 Timer 0 and 1 control 88H 00 0000 0000 TH0 Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TL0 Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1 mode 89H 00 0000 0000 T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 Internal oscillator trim register 96H RCCLK - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [4] [6] WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H FF 1111 1111 26 of 75 © NXP B.V. 2009. All rights reserved. [1] All ports are in input only (high-impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. [4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. [5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset. P89LPC915/916/917 TRIM [5] [6] 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 TCON* T1GATE NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 8. P89LPC916 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 9. P89LPC917 special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 E6 E5 Reset value LSB E4 E3 E2 E1 Hex Binary 00 0000 0000 ADCS10 00 0000 0000 E0 E0H ADCON1 ADC control register 1 97H ENBI1 ENADCI 1 TMM1 EDGE1 ADCI1 ADINS ADC input select A3H ADI13 ADI12 ADI11 ADI10 - - - - 00 0000 0000 ADMODA ADC mode register A C0H BNDI1 BURST1 SCC1 SCAN1 - - - - 00 0000 0000 ADMODB ADC mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x 0000 AD1BH A/D_1 boundary high register C4H FF 1111 1111 AD1BL A/D_1 boundary low register BCH 00 0000 0000 AD1DAT0 A/D_1 data register 0 D5H 00 0000 0000 AD1DAT1 A/D_1 data register 1 D6H 00 0000 0000 AD1DAT2 A/D_1 data register 2 D7H 00 0000 0000 AD1DAT3 A/D_1 data register 3 F5H 00 0000 0000 AUXR1 Auxiliary function register A2H 00 0000 00x0 B* B register F0H 00 0000 0000 BRGR0 Baud rate generator rate low BEH 00 0000 0000 BRGR1 Baud rate generator rate high BFH 00 0000 0000 xxxx xx00 Bit address ENADC1 ADCS11 CLKLP EBRR ENT1 ENT0 SRST 0 - DPS F7 F6 F5 F4 F3 F2 F1 F0 BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00[2] CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00[1] xx00 0000 CMF2 00[1] xx00 0000 00 0000 0000 CMP2 Comparator 2 control register ADH DIVM CPU clock divide-by-M control 95H DPTR Data pointer (2 bytes) - - CE2 CP2 CN2 OE2 CO2 27 of 75 © NXP B.V. 2009. All rights reserved. DPH Data pointer high 83H 00 0000 0000 DPL Data pointer low 82H 00 0000 0000 FMADRH Program flash address high E7H 00 0000 0000 FMADRL Program flash address low E6H 00 0000 0000 P89LPC915/916/917 Accumulator 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 ACC* xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name FMCON Description SFR Bit functions and addresses addr. MSB Reset value LSB Program flash control (Read) E4H BUSY - - - HVA HVE SV OI Program flash control (Write) E4H FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 FMCMD. 3 FMCMD. 2 FMCMD. 1 FMCMD. 0 FMDATA Program flash data E5H I2ADR I2C slave address register DBH Bit address I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC DF DE DD DC DB DA D9 D8 - I2EN STA STO SI AA - CRSEL Hex Binary 70 0111 0000 00 0000 0000 00 0000 0000 00 x000 00x0 I2C control register D8H I2DAT I2C DAH I2SCLH Serial clock generator/SCL duty cycle register high DDH 00 0000 0000 I2SCLL Serial clock generator/SCL duty cycle register low DCH 00 0000 0000 I2STAT I2C status register D9H F8 1111 1000 00 0000 0000 00[1] 00x0 0000 IEN0* IEN1* Interrupt enable 0 Interrupt enable 1 STA.3 STA.2 STA.1 STA.0 0 0 0 AF AE AD AC AB AA A9 A8 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 Bit address EF EE ED EC EB EA E9 E8 EAD EST - - - EC EKBI EI2C BF BE BD BC BB BA B9 B8 - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00[1] x000 0000 00[1] x000 0000 E8H Bit address IP0* IP0H Interrupt priority 0 Interrupt priority 0 high B8H B7H Bit address IP1* IP1H Interrupt priority 1 Interrupt priority 1 high F8H F7H 28 of 75 © NXP B.V. 2009. All rights reserved. KBCON Keypad control register 94H KBMASK Keypad interrupt mask register 86H KBPATN Keypad pattern register - PWDRT H PBOH PSH/ PSRH PT1H PX1H PT0H PX0H FF FE FD FC FB FA F9 F8 PAD PST - - - PC PKBI PI2C 00[1] 00x0 0000 PI2CH 00[1] 00x0 0000 KBIF 00[1] xxxx xx00 00 0000 0000 FF 1111 1111 PADH - PSTH - - - - PCH - PKBIH PATN _SEL P89LPC915/916/917 STA.4 Bit address 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 I2CON* data register NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 9. P89LPC917 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Bit address P0* Port 0 80H Bit address P1* Port 1 90H Bit address Reset value LSB 87 86 85 84 83 82 81 80 T1/KB7/ CLKOUT - CMPREF /KB5 CIN1A /KB4 CIN1B /KB3 CIN2A /KB2 CIN2B /KB1 CMP2 /KB0 97 96 95 94 93 92 91 90 - - RST INT1 INT0/ SDA T0/SCL RXD TXD B7 B6 B5 B4 B3 B2 B1 B0 Hex Binary [1] [1] Port 0 output mode 1 84H (P0M1.7) - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] 1111 1111 P0M2 Port 0 output mode 2 85H (P0M2.7) - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1] P1M1 Port 1 output mode 1 91H - - - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1] 11x1 xx11 P1M2 Port 1 output mode 2 92H - - - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00[1] PCON Power control register 87H SMOD1 SMOD0 BOPD Power control register A B5H BOI GF1 GF0 PMOD1 PMOD0 0000 0000 00x0 xx00 00 0000 0000 00[1] 0000 0000 RTCPD - VCPD ADPD I2PD - SPD - Bit address D7 D6 D5 D4 D3 D2 D1 D0 F0 RS1 RS0 OV F1 P 00 0000 0000 - 00 xx00 000x [3] PSW* Program status word D0H CY AC PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60[1][ 011x xx00 6] RTCH RTC register high D2H 00[6] 0000 0000 0000 0000 RTCL RTC register low D3H 00[6] SADDR Serial port address register A9H 00 0000 0000 SADEN Serial port address enable B9H 00 0000 0000 SBUF Serial Port data buffer register 99H xx xxxx xxxx 9F 9E 9D 9C 9B 9A 99 98 SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 SSTAT Serial port extended status register BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 SP Stack pointer 81H 07 0000 0111 TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0 Bit address 29 of 75 © NXP B.V. 2009. All rights reserved. P89LPC915/916/917 RSTSRC 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 P0M1 PCONA NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 9. P89LPC917 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Bit address Reset value LSB 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Hex Binary 00 0000 0000 TCON* Timer 0 and 1 control 88H TH0 Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TL0 Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1 mode 89H 00 0000 0000 T1GATE T1C/T T1M1 NXP Semiconductors P89LPC915_916_917_5 Product data sheet Table 9. P89LPC917 special function registers …continued * indicates SFRs that are bit addressable. T1M0 T0GATE T0C/T T0M1 T0M0 Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [4] [6] WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H FF 1111 1111 All ports are in input only (high-impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. [4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. [5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset. 30 of 75 © NXP B.V. 2009. All rights reserved. P89LPC915/916/917 [1] 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 05 — 15 December 2009 TRIM [5] [6] P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.2 Enhanced CPU The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 8.3 Clocks 8.3.1 Clock definitions The P89LPC915/916/917 device has several internal clocks as defined below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 11) and can also be optionally divided to a slower frequency (see Section 8.8 “CCLK modification: DIVM register”). Note: fosc is defined as the OSCCLK frequency. CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK — The internal 7.373 MHz RC oscillator output. PCLK — Clock for the various peripheral devices and is CCLK⁄2. 8.3.2 CPU clock (OSCCLK) The P89LPC915/916/917 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock source. 8.3.3 Clock output (P89LPC917) The P89LPC917 supports a user-selectable clock output function on the CLKOUT pin. This allows external devices to synchronize to the P89LPC917. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. 8.4 On-chip RC oscillator option The P89LPC915/916/917 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. 8.5 Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 31 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.6 External clock input option In this configuration, the processor clock is derived from an external source driving the CLKIN pin. The rate may be from 0 Hz up to 18 MHz. When using an external clock input frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an external clock input frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. RTCS1:0 XCLK RTC RCCLK CLKOUT OSCCLK CLKIN CCLK DIVM RC OSCILLATOR CPU RCCLK ADC1/DAC1 (7.3728 MHz) ÷2 PCLK WDT WATCHDOG OSCILLATOR (400 kHz) peripheral clock BAUD RATE GENERATOR UART TIMERS 1 AND 0 I2C SPI (P89LPC916) 002aaa831 Fig 11. Block diagram of oscillator control 8.7 CCLK wake-up delay The P89LPC915/916/917 has an internal wake-up timer that delays the clock until it stabilizes. The delay is 224 OSCCLK cycles plus 60 µs to 100 µs. 8.8 CCLK modification: DIVM register The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 32 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.9 Low power select The P89LPC915/916/917 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. 8.10 Memory organization The various P89LPC915/916/917 memory spaces are as follows: • DATA 128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. • IDATA Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it. • SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing. • CODE 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC915/916/917 devices have 2 kB of on-chip Code memory. 8.11 Data RAM arrangement The 256 bytes of on-chip RAM are organized as shown in Table 10. Table 10. On-chip data memory usages Type Data RAM Size (bytes) DATA Memory that can be addressed directly and indirectly 128 IDATA Memory that can be addressed indirectly 256 8.12 Interrupts The P89LPC915/916/917 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC915 and P89LPC917 support 13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, and ADC completion. The P89LPC916 supports 14 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI, and ADC completion. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 33 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level. 8.12.1 External interrupt inputs The P89LPC915 and P89LPC917 have two external interrupt inputs. The P89LPC916 has one external interrupt input. These external interrupt inputs are identical to those present on the standard 80C51 microcontrollers. All three devices also have the Keypad Interrupt function. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC915/916/917 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 8.15 “Power reduction modes” for details. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 34 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core IE0 EX0 IE1 EX1 BOF EBO RTCF ERTC (RTCCON.1) WDOVF wake-up (if in power-down) KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 TI_0 and RI_0/RI_0 ES/ESR TI_0 EST interrupt to CPU SI EI2C SPIF ESPI TI_1 and RI_1/RI_1 ES1/ESR1 TI_1 EST1 ENADCI0 ADCI0 ENBI0 BNDI0 EADC 002aab408 Fig 12. Interrupt sources, interrupt enables, and power-down wake-up sources P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 35 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.13 I/O ports The P89LPC916 and P89LPC917 devices have three I/O ports: Port 0, Port 1, and Port 2. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 11. Table 11. Number of I/O pins available (P89LPC916 and P89LPC917) Clock source Reset option Number of I/O pins (16-pin package) RC oscillator or watchdog oscillator No external reset (except during power-up) 14 External RST pin supported 13 No external reset (except during power-up) 13 External RST pin supported[1] 12 External clock input [1] Required for operation above 12 MHz. The P89LPC915 has two I/O ports: Port 0 and Port 1. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 12. Table 12. Number of I/O pins available (P89LPC915) Clock source Reset option Number of I/O pins (14-pin package) RC oscillator or watchdog oscillator No external reset (except during power-up) 12 External RST pin supported 11 No external reset (except during power-up) 11 External RST pin supported[1] 10 External clock input [1] Required for operation above 12 MHz. 8.13.1 Port configurations All but three I/O port pins on the P89LPC915/916/917 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. 1. P1.5 (RST) can only be an input and cannot be configured. 2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or open-drain. 8.13.1.1 Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 36 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core The P89LPC915/916/917 is a 3 V device, but the pins are 5 V tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit. 8.13.1.2 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. An open-drain port pin has a Schmitt triggered input that also has a glitch suppression circuit. 8.13.1.3 Input-only configuration The input-only port configuration has no output drivers. It is a Schmitt triggered input that also has a glitch suppression circuit. 8.13.1.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit. 8.13.2 Port 0 analog functions The P89LPC915/916/917 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any reset, PT0AD bits default to ‘0’s to enable digital functions. 8.13.3 Additional port features After power-up, all pins are in Input-Only mode. After power-up, all I/O pins except P1.5, may be configured by software. • Pin P1.5 is input only. • Pins P1.2 and P1.3 are configurable for either input-only or open-drain. Every output on the P89LPC915/916/917 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 15 “Static characteristics” for detailed specifications. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 37 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times. 8.14 Power monitoring functions The P89LPC915/916/917 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect. 8.14.1 Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a brownout detection to cause a processor reset, however it may alternatively be configured to generate an interrupt. Brownout detection may be enabled or disabled in software. If brownout detection is enabled the brownout condition occurs when VDD falls below the brownout trip voltage, Vbo (see Table 15 “Static characteristics”), and is negated when VDD rises above Vbo. If the P89LPC915/916/917 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of brownout detect, the VDD rise and fall times must be observed. Please see Table 15 “Static characteristics” for specifications. 8.14.2 Power-on detection The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software. 8.15 Power reduction modes The P89LPC915/916/917 supports three different power reduction modes: Idle mode, Power-down mode, and total Power-down mode. 8.15.1 Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode. 8.15.2 Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC915/916/917 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention voltage VDDR. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly recommended to wake-up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 38 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. 8.15.3 Total Power-down mode This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down. 8.16 Reset The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin always functions as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. Reset can be triggered from the following sources: • • • • • • External reset pin (during power-up or if user configured via UCFG1); Power-on detect; Brownout detect; Watchdog timer; Software reset; UART break character detect reset. For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit may be set: • During a power-on reset, both POF and BOF are set but the other flag bits are cleared. • For any other reset, previously set flag bits that have not been cleared will remain set. 8.17 Timers/counters 0 and 1 The P89LPC915/916/917 have two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters. An option to automatically toggle the T0 and/or T1 pins upon timer overflow has been added. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 39 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core In the ‘Timer’ function, the register is incremented every machine cycle. In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle. Timer 0 has five operating modes (Modes 0, 1, 2, 3 and 6). Timer 1 has four operating modes (Modes 0, 1, 2, and 3), except on the P89LPC917 where Timer 1 also has Mode 6. Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different. 8.17.1 Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1. 8.17.2 Mode 1 Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used. 8.17.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1. 8.17.4 Mode 3 When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator. 8.17.5 Mode 6 In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks. 8.17.6 Timer overflow toggle output Timer 0 (and Timer 1 on the P89LPC917) can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. 8.18 RTC/system timer The P89LPC915/916/917 have a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down-counter comprised of a 7-bit prescaler and a 16-bit loadable down-counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF flag will be set. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 40 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core The clock source for this counter can be either the CPU clock (CCLK) or the external clock input, provided that the external clock input is not being used as the CPU clock. If the external clock input is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the RTC and its associated SFRs to the default state. 8.19 UART The P89LPC915/916/917 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC915/916/917 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16. 8.19.1 Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock frequency. 8.19.2 Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8_n in Special Function Register SnCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 8.19.5 “Baud rate generator and selection”). 8.19.3 Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of ‘0’ or ‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. The SMOD1 bit controls the Timer 1 output rate available to the UART. 8.19.4 Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 8.19.5 “Baud rate generator and selection”). P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 41 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.19.5 Baud rate generator and selection Each enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or its baud rate generator output (see Figure 13). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses OSCCLK. timer 1 overflow (PCLK-based) SMOD1 = 1 SBRGS = 0 ÷2 baud rate modes 1 and 3 SMOD1 = 0 baud rate generator (CCLK-based) SBRGS = 1 002aaa897 Fig 13. Baud rate sources for UART (Modes 1, 3) 8.19.6 Framing error Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON [7:6]) are set up when SMOD0 is ‘0’. 8.19.7 Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode. 8.19.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0). 8.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) Unlike the conventional UART, in double buffering mode, the TI interrupt is generated when the double buffer is ready to receive new data. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 42 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.19.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3) If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TI interrupt. If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. 8.20 I2C-bus serial interface I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features: • Bidirectional data transfer between masters and slaves • Multi master bus (no central master) • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer • The I2C-bus may be used for test and diagnostic purposes. A typical I2C-bus configuration is shown in Figure 14. The P89LPC915/916/917 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz. RPU RPU SDA I2C-bus SCL P1.3/SDA P1.2/SCL I2C MCU OTHER DEVICE WITH I2C-BUS INTERFACE OTHER DEVICE WITH I2C-BUS INTERFACE 002aab410 Fig 14. I2C-bus configuration P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 43 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8 I2ADR ADDRESS REGISTER P1.3 COMPARATOR INPUT FILTER P1.3/SDA ACK SHIFT REGISTER OUTPUT STAGE I2DAT BIT COUNTER / ARBITRATION AND SYNC LOGIC INPUT FILTER P1.2/SCL SERIAL CLOCK GENERATOR OUTPUT STAGE CCLK TIMING AND CONTROL LOGIC interrupt INTERNAL BUS 8 timer 1 overflow P1.2 I2CON I2SCLH I2SCLL CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS 8 status bus I2STAT STATUS DECODER STATUS REGISTER 8 002aaa899 Fig 15. I2C-bus serial interface block diagram P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 44 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.21 SPI The P89LPC916 provides another high-speed serial communication interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in Master mode or up to 3 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection. S M CPU clock 8-BIT SHIFT REGISTER clock MSTR SPR0 SPICLK P2.5 SS P2.4 SPR0 SPR1 CPOL CPHA MSTR SSIG WCOL DORD MSTR SPEN SPI CONTROL SPEN SPR1 S M CLOCK LOGIC MOSI P2.2 SPEN SPI clock (master) SELECT SPIF PIN CONTROL LOGIC READ DATA BUFFER DIVIDER BY 4, 16, 64, 128 MISO P2.3 M S SPI CONTROL REGISTER SPI STATUS REGISTER SPI interrupt request internal data bus 002aaa900 Fig 16. SPI block diagram The SPI interface has four pins: SPICLK, MOSI, MISO and SS: • SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions. • SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figure 17 through Figure 19. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 45 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.21.1 Typical SPI configurations master slave 8-BIT SHIFT REGISTER MISO MISO MOSI MOSI SPICLK SPI CLOCK GENERATOR PORT 8-BIT SHIFT REGISTER SPICLK SS 002aaa901 Fig 17. SPI single master single slave configuration master 8-BIT SHIFT REGISTER slave MISO MISO MOSI MOSI SPICLK SPI CLOCK GENERATOR SS 8-BIT SHIFT REGISTER SPICLK SS SPI CLOCK GENERATOR 002aaa902 Fig 18. SPI dual device configuration, where either can be a master or a slave P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 46 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core master slave 8-BIT SHIFT REGISTER MISO MISO MOSI MOSI SPICLK SPI CLOCK GENERATOR port 8-BIT SHIFT REGISTER SPICLK SS slave MISO MOSI 8-BIT SHIFT REGISTER SPICLK port SS 002aaa903 Fig 19. SPI single master multiple slaves configuration P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 47 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.22 Analog comparators Two analog comparators are provided on the P89LPC915/916/917. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. Comparator 1 may be output to a port pin. The overall connections to both comparators are shown in Figure 20. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. CP1 OE1 comparator 1 (P0.4) CIN1A (P0.3) CIN1B CO1 CMP1 (P0.6) (P0.5) CMPREF change detect Vref(bg) CMF1 CN1 interrupt change detect EC CP2 CMF2 comparator 2 (P0.2) CIN2A (P0.1) CIN2B CMP2 (P0.0) CO2 OE2 CN2 002aaa904 Fig 20. Comparator input and output connections 8.22.1 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref(bg), is 1.23 V ± 10 %. 8.22.2 Comparator interrupt Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt. 8.22.3 Comparators and power reduction modes Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 48 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode. 8.23 KBI The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 49 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.24 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down-counter. The down-counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 21 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few µs to a few seconds. Please refer to the P89LPC915/916/917 User’s Manual for more details. WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH watchdog oscillator PCLK ÷32 8-BIT DOWN COUNTER PRESCALER reset(1) SHADOW REGISTER WDCON (A7H) PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK 002aaa905 (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 21. Watchdog timer in Watchdog mode (WDTE = 1) 8.25 Additional features 8.25.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets. 8.25.2 Dual data pointers The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 50 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.26 Flash program memory 8.26.1 General description The P89LPC915/916/917 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC915/916/917 flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC915/916/917 uses VDD as the supply voltage to perform the Program/Erase algorithms. 8.26.2 Features • • • • Programming and erase over the full operating voltage range. • • • • • Any flash program/erase operation in 2 ms. Byte erase allows code memory to be used for data storage. Read/Programming/Erase using ICP. Boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing flexibility to the user. Programming with industry-standard commercial programmers. Programmable security for the code in the flash for each sector. 100,000 typical erase/program cycles for each byte. 10 year minimum data retention. 8.26.3 Flash organization The program memory consists of eight 256-byte sectors on the P89LPC915/916/917 devices. Each sector can be further divided into 16-byte pages. In addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. 8.26.4 Using flash as data storage The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage. 8.26.5 Flash programming and erasing Two different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP-Lite) under control of the application’s firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 51 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.26.6 ICP ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC915/916/917 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application—using commercially available programmers—possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC915/916/917 User’s Manual. 8.26.7 IAP-Lite IAP-Lite is performed in the application under the control of the microcontroller’s firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The IAP-Lite operations are accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC915/916/917 User’s Manual. 8.26.8 Power-on reset code execution The P89LPC915/916/917 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89LPC915/916/917 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code. When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to 00H. Table 13 shows the factory default Boot Vector setting for this device. While these devices do not contain a factory bootloader, the Boot Vector and Status bit do provide a mechanism for an alternate code execution at reset. Table 13. Default boot vector and Status bit values Device Default boot vector Default Status bit P89LPC915 00H 0 P89LPC916 00H 0 P89LPC917 00H 0 8.26.9 Hardware activation of the alternate code The alternate code execution address can be forced during a power-on sequence (see the P89LPC915/916/917 User’s Manual for specific information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code starting at address 0000H but can be manually forced into executing from an alternated address using the Boot Vector. After programming the flash, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address 0000H. 8.27 User configuration bytes Some user-configurable features of the P89LPC915/916/917 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1. Please see the P89LPC915/916/917 User’s Manual for additional details. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 52 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 8.28 User sector security bytes There are eight User Sector Security Bytes on the P89LPC915/916/917. Each byte corresponds to one sector. Please see the P89LPC915/916/917 User’s Manual for additional details. 9. A/D converter 9.1 General description The P89LPC915/916/917 devices have a single 8-bit, 4-channel multiplexed analog-to-digital converter with a DAC module. A block diagram of the A/D converter is shown in Figure 22. The A/D consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR. 9.2 Features n Single 8-bit, 4-channel multiplexed input, successive approximation A/D converter. n Four A/D result registers. n Six operating modes: u Fixed channel, single conversion mode. u Fixed channel, continuous conversion mode. u Auto scan, single conversion mode. u Auto scan, continuous conversion mode. u Dual channel, continuous conversion mode. u Single step mode. n Three conversion start modes: u Timer triggered start. u Start immediately. u Edge triggered. n 8-bit conversion time of ≥3.9 µs at an A/D clock of 3.3 MHz. n Interrupt or polled operation. n Boundary limits interrupt. n DAC output to a port pin with high output impedance. n Clock divider. n Power-down mode. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 53 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 9.3 Block diagram comp + INPUT MUX SAR – 8 DAC1 CONTROL LOGIC comp + INPUT MUX SAR – 8 DAC0 CCLK 002aab080 Fig 22. ADC block diagram 9.4 A/D operating modes 9.4.1 Fixed channel, single conversion mode A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes. 9.4.2 Fixed channel, continuous conversion mode A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers. An interrupt, if enabled, will be generated after every four conversions. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user. 9.4.3 Auto scan, single conversion mode Any combination of the four input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 54 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 9.4.4 Auto scan, continuous conversion mode Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the first selected channel. Additional conversion results will again cycle through the four result registers, overwriting the previous results.Continous conversions continue until terminated by the user. 9.4.5 Dual channel, continuous conversion mode This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in result register, AD1DAT0. The result of the conversion of the second channel is placed in result register, AD1DAT1. The first channel is again converted and its result stored in AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel). 9.4.6 Single step mode This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. May be used with any of the start modes. 9.5 Conversion start modes 9.5.1 Timer triggered start An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A/D operating modes. 9.5.2 Start immediately Programming this mode immediately starts a conversion.This start mode is available in all A/D operating modes. 9.5.3 Edge triggered An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all A/D operating modes. 9.6 Boundary limits interrupt The A/D converter has both a high and low boundary limit register. After the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion are outside the limit an interrupt will be generated, if enabled. If the conversion result is within the limits, the boundary limits will again be compared after all 8 bits have been converted. An interrupt will be generated, if enabled, if the result is outside the boundary limits. The boundary limit may be disabled by clearing the boundary limit interrupt enable. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 55 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 9.7 DAC output to a port pin with high output impedance The A/D converter’s DAC block can be output to a port pin. In this mode, the AD1DAT3 register is used to hold the value fed to the DAC. After a value has been written to the DAC (written to AD1DAT3), the DAC output will appear on the channel 3 pin. 9.8 Clock divider The A/D converter requires that its internal clock source be in the range of 500 kHz to 3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose. 9.9 Power-down and Idle mode In Idle mode the A/C converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 56 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 10. Limiting values Table 14. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Tamb(bias) Min Max Unit operating bias ambient temperature −55 +125 °C Tstg storage temperature range −65 +150 °C IOH(I/O) HIGH-level output current per I/O pin - 8 mA IOL(I/O) LOW-level output current per I/O pin - 20 mA II/O(tot)(max) maximum total I/O current - 120 mA Vn voltage on any pin (except VSS) with respect to VDD - 3.5 V Ptot(pack) total power dissipation per package based on package heat transfer, not device power consumption - 1.5 W [1] Conditions The following applies to Table 14: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 57 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 11. Static characteristics Table 15. Static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified. Min Typ[1] Max Unit VDD = 3.6 V; fosc = 12 MHz [2] - 7 13 mA VDD = 3.6 V; fosc = 18 MHz [2] - 11 16 mA VDD = 3.6 V; fosc = 12 MHz [2] - 3.6 4.8 mA VDD = 3.6 V; fosc = 18 MHz [2] - 4 6 mA power supply current, power-down mode, voltage comparators powered-down VDD = 3.6 V, industrial [2] - 45 70 µA VDD = 3.6 V, extended [2] - 150 µA total Power-down mode supply current VDD = 3.6 V, industrial [3] - <0.1 5 µA VDD = 3.6 V, extended [3] - - 50 µA (dV/dt)r rise rate of VDD - - 2 mV/µs (dV/dt)f fall rate of VDD - - 50 mV/µs VPOR power-on reset voltage - - 0.2 V VDDR data retention voltage 1.5 - - V Vth(HL) HIGH-LOW threshold voltage except SCL, SDA 0.22VDD 0.4VDD - V VIL LOW-level input voltage SCL, SDA only −0.5 - 0.3VDD V Vth(LH) LOW-HIGH threshold voltage except SCL, SDA - 0.6VDD 0.7VDD V VIH HIGH-level input voltage SCL, SDA only 0.7VDD - 5.5 V Vhys hysteresis voltage port 1 - 0.2VDD - V - 0.6 1.0 V IOL = 10 mA; all ports except SCL, SDA - 0.2 0.3 V IOL = 3.2 mA; all ports except SCL, SDA - 0.2 0.3 V IOH = −8 mA; push-pull mode; all ports except SCL, SDA VDD − 1 - - V IOH = −3.2 mA; push-pull mode; all ports except SCL, SDA VDD − 0.7 VDD − 0.4 - V IOH = −20 µA; quasi-bidirectional mode; all ports except SCL, SDA VDD − 0.3 VDD − 0.2 - V −0.5 - +4.0 V [5] −0.5 - +5.5 V Symbol IDD(oper) IDD(idle) IDD(pd) IDD(tpd) VOL VOH Parameter operating supply current Idle mode supply current LOW-level output voltage HIGH-level output voltage Conditions IOL = 20 mA; all ports except SCL, SDA [4] Vxtal crystal voltage voltage on XTAL1, XTAL2 pins with respect to VSS Vn voltage on any pin (except XTAL1, XTAL2, VDD) with respect to VSS Ciss input capacitance [6] - - 15 pF logical 0 input current [7] - - −80 µA IIL VI = 0.4 V P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 58 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 15. Static characteristics …continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified. Symbol ILI Parameter input leakage current Min Typ[1] Max Unit VI = VIL, VIH or Vth(HL) [8] - - ±10 µA VI = 1.5 V at VDD = 3.6 V [9] −30 - −450 µA 10 - 30 kΩ 2.40 - 2.70 V Conditions ITL logical 1-to-0 transition current, all ports RRST(int) internal pull-up resistance on pin RST Vbo brownout trip voltage Vref(bg) band gap reference voltage 1.11 1.23 1.34 V TCbg band gap temperature coefficient - 10 20 ppm/°C 2.4 V < VDD < 3.6 V; with BOV = 1, BOPD = 0 [1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. [2] The IDD(oper), IDD(idle), and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators, real-time clock, and watchdog timer. [3] The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer. [4] See Section 10 “Limiting values” for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related specification. [5] This specification can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to VSS. [6] Pin capacitance is characterized but not tested. [7] Measured with port in quasi-bidirectional mode. [8] Measured with port in high-impedance mode. [9] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when VI is approximately 2 V. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 59 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 12. Dynamic characteristics Table 16. Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified.[1][2] Symbol Parameter Conditions Min Max Min fosc(RC) internal RC oscillator frequency industrial 7.189 7.557 7.189 7.557 MHz extended 7.004 7.741 7.004 7.741 MHz 320 520 320 520 kHz 0 8 - - MHz fosc(WD) internal watchdog oscillator frequency fCLKLP low power select clock frequency Variable clock fosc = 12 MHz Unit Max Glitch filter tgr tsa glitch rejection time signal acceptance time P1.5/RST pin - 50 - 50 ns any pin except P1.5/RST - 15 - 15 ns P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns 0 12 - - MHz External clock fosc oscillator frequency Tcy(clk) clock cycle time see Figure 28 83 - - - ns tCHCX clock HIGH time see Figure 28 33 Tcy(CLK) − tCLCX 33 - ns tCLCX clock LOW time see Figure 28 33 Tcy(CLK) − tCHCX 33 - ns tCLCH clock rise time see Figure 28 - 8 - 8 ns tCHCL clock fall time see Figure 28 - 8 - 8 ns Shift register (UART mode 0) TXLXL serial port clock cycle time see Figure 27 16Tcy(CLK) - 1333 - ns tQVXH output data set-up to clock rising see Figure 27 edge time 13Tcy(CLK) - 1083 - ns tXHQX output data hold after clock rising edge time see Figure 27 - Tcy(CLK) + 20 - 103 ns tXHDX input data hold after clock rising edge time see Figure 27 - 0 - 0 ns tXHDV input data valid to clock rising edge time see Figure 27 150 - 150 - ns 0 CCLK⁄ 6 0 2.0 MHz - CCLK⁄ 4 - 3.0 MHz 6⁄ CCLK - 500 - ns 4⁄ CCLK - 333 - ns SPI interface fSPI SPI operating frequency slave master TSPICYC SPI cycle time slave master see Figure 23, 24, 25, 26 P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 60 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 16. Dynamic characteristics (12 MHz) …continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified.[1][2] Symbol tSPILEAD Parameter Conditions Min Max 250 - 250 - ns 250 - 250 - ns 2⁄ CCLK - 165 - ns 3⁄ CCLK - 250 - ns 2⁄ CCLK - 165 - ns 3⁄ CCLK - 250 - ns see Figure 23, 24, 25, 26 100 - 100 - ns see Figure 23, 24, 25, 26 100 - 100 - ns 0 120 0 120 ns 0 240 - 240 ns slave - 240 - 240 ns master - 167 - 167 ns 0 - 0 - ns - 100 - 100 ns - 2000 - 2000 ns - 100 - 100 ns - 2000 - 2000 ns SPI enable lead time SPI enable lag time SPICLK HIGH time master see Figure 25, 26 see Figure 25, 26 see Figure 23, 24, 25, 26 slave tSPICLKL SPICLK LOW time master see Figure 23, 24, 25, 26 slave tSPIDSU SPI data set-up time master or slave tSPIDH SPI data hold time master or slave tSPIA SPI access time see Figure 25, 26 slave tSPIDIS SPI disable time see Figure 25, 26 slave tSPIDV SPI enable to output data valid time see Figure 23, 24, 25, 26 tSPIOH SPI output data hold time see Figure 23, 24, 25, 26 tSPIR SPI rise time see Figure 23, 24, 25, 26 SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF Unit Max slave tSPICLKH fosc = 12 MHz Min slave tSPILAG Variable clock SPI fall time SPI outputs (SPICLK, MOSI, MISO) see Figure 23, 24, 25, 26 SPI inputs (SPICLK, MOSI, MISO, SS) [1] Parameters are valid over ambient temperature range unless otherwise specified. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 61 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 17. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified.[1][2] Symbol fosc(RC) Parameter Conditions Variable clock fosc = 18 MHz Unit Min Max Min internal RC oscillator frequency industrial 7.189 7.557 7.189 7.557 MHz extended 7.004 7.741 7.004 7.741 MHz 320 520 320 520 kHz 0 8 - - MHz P1.5/RST pin - 50 - 50 ns any pin except P1.5/RST - 15 - 15 ns fosc(WD) internal watchdog oscillator frequency fCLKLP low power select clock frequency Max Glitch filter tgr tsa glitch rejection time signal acceptance time P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns External clock fosc oscillator frequency 0 18 - - MHz Tcy(clk) clock cycle time see Figure 28 55 - - - ns tCHCX clock HIGH time see Figure 28 22 Tcy(CLK) − tCLCX 22 - ns tCLCX clock LOW time see Figure 28 22 Tcy(CLK) − tCHCX 22 - ns tCLCH clock rise time see Figure 28 - 5 - 5 ns tCHCL clock fall time see Figure 28 - 5 - 5 ns Shift register (UART mode 0) TXLXL serial port clock cycle time see Figure 27 16Tcy(CLK) - 888 - ns tQVXH output data set-up to clock rising edge time see Figure 27 13Tcy(CLK) - 722 - ns tXHQX output data hold after clock rising edge time see Figure 27 - Tcy(CLK) + 20 - 75 ns tXHDX input data hold after clock rising see Figure 27 edge time - 0 - 0 ns tXHDV input data valid to clock rising edge time 150 - 150 - ns 0 CCLK⁄ 6 0 3.0 MHz - CCLK⁄ 4 - 4.5 MHz see Figure 27 SPI interface fSPI SPI operating frequency slave master TSPICYC SPI cycle time slave see Figure 23, 24, 25, 26 master tSPILEAD SPI enable lead time tSPILAG SPI enable lag time 6⁄ CCLK - 333 - ns 4⁄ CCLK - 222 - ns see Figure 25, 26 slave see Figure 25, 26 250 - 250 - ns 250 - 250 - ns P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 62 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core Table 17. Dynamic characteristics (18 MHz) …continued VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified.[1][2] Symbol Parameter Conditions Variable clock Min tSPICLKH SPICLK HIGH time see Figure 23, 24, 25, 26 - 111 - ns CCLK - 167 - ns 2⁄ CCLK - 111 - ns CCLK - 167 - ns see Figure 23, 24, 25, 26 100 - 100 - ns see Figure 23, 24, 25, 26 100 - 100 - ns 0 80 0 80 ns 0 160 - 160 ns slave - 160 - 160 ns master - 111 - 111 ns 0 - 0 - ns - 100 - 100 ns - 2000 - 2000 ns - 100 - 100 ns - 2000 - 2000 ns SPICLK LOW time see Figure 23, 24, 25, 26 3⁄ slave SPI data set-up time master or slave SPI data hold time master or slave tSPIA SPI access time see Figure 25, 26 slave tSPIDIS SPI disable time see Figure 25, 26 slave tSPIDV SPI enable to output data valid time see Figure 23, 24, 25, 26 tSPIOH SPI output data hold time see Figure 23, 24, 25, 26 tSPIR SPI rise time see Figure 23, 24, 25, 26 SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF Max CCLK master tSPIDH Min 3⁄ slave tSPIDSU Max 2⁄ master tSPICLKL fosc = 18 MHz Unit SPI fall time SPI outputs (SPICLK, MOSI, MISO) see Figure 23, 24, 25, 26 SPI inputs (SPICLK, MOSI, MISO, SS) [1] Parameters are valid over ambient temperature range unless otherwise specified. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 63 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 12.1 Waveforms SS TSPICYC tSPIF tSPICLKH tSPICLKL tSPIR SPICLK (CPOL = 0) (output) tSPIF tSPIR tSPICLKL tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in MSB/LSB in tSPIDV MOSI (output) tSPIOH tSPIDV tSPIF tSPIR master MSB/LSB out master LSB/MSB out 002aaa908 Fig 23. SPI master timing (CPHA = 0) SS TSPICYC tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 0) (output) tSPIF tSPIR tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in MSB/LSB in tSPIDV MOSI (output) tSPICLKL tSPIOH tSPIDV tSPIF tSPIR master MSB/LSB out master LSB/MSB out 002aaa909 Fig 24. SPI master timing (CPHA = 1) P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 64 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core SS tSPIF tSPIR TSPICYC tSPILEAD tSPIF tSPICLKH tSPICLKL tSPIR tSPILAG SPICLK (CPOL = 0) (input) tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (input) tSPIOH tSPIA tSPIOH MISO (output) slave MSB/LSB out tSPIDSU MOSI (input) tSPIOH tSPIDIS tSPIDV tSPIDV tSPIDH slave LSB/MSB out tSPIDSU tSPIDSU MSB/LSB in not defined tSPIDH LSB/MSB in 002aaa910 Fig 25. SPI slave timing (CPHA = 0) SS tSPIF tSPILEAD tSPIR TSPICYC tSPIF tSPICLKL tSPIR tSPILAG tSPICLKH SPICLK (CPOL = 0) (input) tSPIF tSPICLKL SPICLK (CPOL = 1) (input) tSPIR tSPICLKH tSPIOH tSPIOH tSPIDV tSPIDV tSPIOH tSPIDV tSPIDIS tSPIA MISO (output) not defined slave MSB/LSB out tSPIDSU MOSI (input) tSPIDH MSB/LSB in slave LSB/MSB out tSPIDSU tSPIDH LSB/MSB in 002aaa911 Fig 26. SPI slave timing (CPHA = 1) P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 65 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core TXLXL clock tXHQX tQVXH output data 0 write to SBUF input data 1 2 3 4 5 6 tXHDX set TI tXHDV valid 7 valid valid valid valid valid valid valid clear RI set RI 002aaa906 Fig 27. Shift register mode timing tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 28. External clock timing 12.2 ISP entry mode Table 18. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified. Symbol Parameter tVR Conditions Min Typ Max Unit VDD active to RST active delay time 50 - - µs tRH RST HIGH time 1 - 32 µs tRL RST LOW time 1 - - µs VDD tVR tRH RST tRL 002aaa912 Fig 29. ISP entry timing P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 66 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 13. Other characteristics 13.1 Comparator electrical characteristics Table 19. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified. Symbol Parameter VIO input offset voltage VIC common mode input voltage CMRR common mode rejection ratio Conditions [1] Min Typ Max Unit - - ±20 mV 0 - VDD − 0.3 V - - −50 dB tres(tot) total response time - 250 500 ns t(CE-OV) chip enable to output valid time - - 10 µs ILI input leakage current - - ±10 µA Max Unit [1] 0 < VI < VDD This parameter is characterized, but not tested in production. 13.2 ADC electrical characteristics Table 20. ADC electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified. All limits valid for an external source impedance of less than 10 kΩ. Symbol Parameter Conditions VIA analog input voltage VSS − 0.2 - VSS + 0.2 V Cia analog input capacitance - - 15 pF ED differential linearity error - - ±1 LSB EL(adj) integral non-linearity - - ±1 LSB EO offset error - - ±2 LSB EG gain error - - ±1 % Eu(tot) total unadjusted error - - ±2 LSB MCTC channel-to-channel matching - - ±1 LSB αct(port) crosstalk between port inputs - - −60 dB SRin input slew rate - - 100 V/ms Tcy(ADC) ADC clock cycle tADC conversion time 0 kHz to 100 kHz A/D enabled P89LPC915_916_917_5 Product data sheet Min Typ 111 - 2000 ns - - 13Tcy(ADC) ns © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 67 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 14. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 30. Package outline SOT27-1 (DIP14) P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 68 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 31. Package outline SOT402-1 (TSSOP14) P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 69 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 32. Package outline SOT403-1 (TSSOP16) P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 70 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 15. Abbreviations Table 21. Acronym list Acronym Description ADC Analog to Digital Converter CPU Central Processing Unit CCU Capture/Compare Unit DAC Digital to Analog Converter EPROM Erasable Programmable Read-Only Memory EEPROM Electrically Erasable Programmable Read-Only Memory EMI ElectroMagnetic Interference PLL Phase-Locked Loop PWM Pulse Width Modulator RAM Random Access Memory RC Resistance-Capacitance RTC Real-Time Clock SAR Successive Approximation Register SFR Special Function Register SPI Serial Peripheral Interface UART Universal Asynchronous Receiver/Transmitter P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 71 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 16. Revision history Table 22. Revision history Document ID Release date Data sheet status Change notice Supersedes P89LPC915_916_917_5 20091215 Product data sheet - P89LPC915_916_917-04 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate. Added ADC electrical characteristics, Table 20. Added P89LPC915FN. P89LPC915_916_917-04 20041217 Product data - P89LPC915_916_917-03 P89LPC915_916_917-03 20040701 Preliminary data - P89LPC915_916_917-02 P89LPC915_916_917-02 20040512 Preliminary data - P89LPC915_916_917-01 P89LPC915_916_917-01 20040408 Preliminary data - - P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 72 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 73 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 Product comparison overview . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 7 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 9 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Functional description . . . . . . . . . . . . . . . . . . 18 8.1 Special function registers . . . . . . . . . . . . . . . . 18 8.2 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 31 8.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.3.1 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 31 8.3.2 CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 31 8.3.3 Clock output (P89LPC917) . . . . . . . . . . . . . . . 31 8.4 On-chip RC oscillator option . . . . . . . . . . . . . . 31 8.5 Watchdog oscillator option . . . . . . . . . . . . . . . 31 8.6 External clock input option . . . . . . . . . . . . . . . 32 8.7 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 32 8.8 CCLK modification: DIVM register . . . . . . . . . 32 8.9 Low power select . . . . . . . . . . . . . . . . . . . . . . 33 8.10 Memory organization . . . . . . . . . . . . . . . . . . . 33 8.11 Data RAM arrangement . . . . . . . . . . . . . . . . . 33 8.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.12.1 External interrupt inputs . . . . . . . . . . . . . . . . . 34 8.13 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.13.1 Port configurations . . . . . . . . . . . . . . . . . . . . . 36 8.13.1.1 Quasi-bidirectional output configuration . . . . . 36 8.13.1.2 Open-drain output configuration . . . . . . . . . . . 37 8.13.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 37 8.13.1.4 Push-pull output configuration . . . . . . . . . . . . 37 8.13.2 Port 0 analog functions . . . . . . . . . . . . . . . . . . 37 8.13.3 Additional port features. . . . . . . . . . . . . . . . . . 37 8.14 Power monitoring functions. . . . . . . . . . . . . . . 38 8.14.1 Brownout detection . . . . . . . . . . . . . . . . . . . . . 38 8.14.2 Power-on detection . . . . . . . . . . . . . . . . . . . . . 38 8.15 Power reduction modes . . . . . . . . . . . . . . . . . 38 8.15.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.15.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 38 8.15.3 Total Power-down mode . . . . . . . . . . . . . . . . . 39 8.16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.17 Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 39 8.17.1 8.17.2 8.17.3 8.17.4 8.17.5 8.17.6 8.18 8.19 8.19.1 8.19.2 8.19.3 8.19.4 8.19.5 8.19.6 8.19.7 8.19.8 8.19.9 8.19.10 8.20 8.21 8.21.1 8.22 8.22.1 8.22.2 8.22.3 8.23 8.24 8.25 8.25.1 8.25.2 8.26 8.26.1 8.26.2 8.26.3 8.26.4 8.26.5 8.26.6 8.26.7 8.26.8 8.26.9 8.27 8.28 9 9.1 9.2 9.3 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer overflow toggle output . . . . . . . . . . . . . RTC/system timer. . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud rate generator and selection . . . . . . . . . Framing error . . . . . . . . . . . . . . . . . . . . . . . . . Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . Double buffering . . . . . . . . . . . . . . . . . . . . . . . Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . I2C-bus serial interface. . . . . . . . . . . . . . . . . . SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical SPI configurations . . . . . . . . . . . . . . . Analog comparators . . . . . . . . . . . . . . . . . . . . Internal reference voltage. . . . . . . . . . . . . . . . Comparator interrupt . . . . . . . . . . . . . . . . . . . Comparators and power reduction modes . . . KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Additional features . . . . . . . . . . . . . . . . . . . . . Software reset . . . . . . . . . . . . . . . . . . . . . . . . Dual data pointers . . . . . . . . . . . . . . . . . . . . . Flash program memory . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash organization . . . . . . . . . . . . . . . . . . . . . Using flash as data storage . . . . . . . . . . . . . . Flash programming and erasing. . . . . . . . . . . ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IAP-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on reset code execution . . . . . . . . . . . Hardware activation of the alternate code . . . User configuration bytes. . . . . . . . . . . . . . . . . User sector security bytes . . . . . . . . . . . . . . . A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 40 40 40 40 41 41 41 41 41 42 42 42 42 42 43 43 45 46 48 48 48 48 49 50 50 50 50 51 51 51 51 51 51 52 52 52 52 52 53 53 53 53 54 continued >> P89LPC915_916_917_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 15 December 2009 74 of 75 P89LPC915/916/917 NXP Semiconductors 8-bit microcontrollers with accelerated two-clock 80C51 core 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.5 9.5.1 9.5.2 9.5.3 9.6 9.7 9.8 9.9 10 11 12 12.1 12.2 13 13.1 13.2 14 15 16 17 17.1 17.2 17.3 17.4 18 19 A/D operating modes . . . . . . . . . . . . . . . . . . . Fixed channel, single conversion mode . . . . . Fixed channel, continuous conversion mode . Auto scan, single conversion mode . . . . . . . . Auto scan, continuous conversion mode . . . . Dual channel, continuous conversion mode . . Single step mode . . . . . . . . . . . . . . . . . . . . . . Conversion start modes . . . . . . . . . . . . . . . . . Timer triggered start . . . . . . . . . . . . . . . . . . . . Start immediately . . . . . . . . . . . . . . . . . . . . . . Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . Boundary limits interrupt. . . . . . . . . . . . . . . . . DAC output to a port pin with high output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . Power-down and Idle mode . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . Other characteristics . . . . . . . . . . . . . . . . . . . . Comparator electrical characteristics . . . . . . . ADC electrical characteristics . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 54 54 54 55 55 55 55 55 55 55 55 56 56 56 57 58 60 64 66 67 67 67 68 71 72 73 73 73 73 73 73 74 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 December 2009 Document identifier: P89LPC915_916_917_5