PHILIPS HEF4508BP

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4508B
MSI
Dual 4-bit latch
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
data into the latch. A HIGH on the reset line forces the
outputs to a LOW level regardless of the state of the ST
input. The 3-state outputs are controlled by the
output-enable input. A HIGH on EO causes the outputs to
assume a high impedance OFF-state regardless of other
input conditions. This allows the outputs to interface
directly with bus orientated systems. When EO is LOW the
contents of the latches are available at the outputs.
DESCRIPTION
The HEF4508B is a dual 4-bit latch, which consists of two
identical independent 4-bit latches with separate strobe
(ST), master reset (MR), output-enable input (EO) and
3-state outputs (O).
With the ST input in the HIGH state, the data on the D
inputs appear at the corresponding outputs provided EO is
LOW. Changing the ST input to the LOW state locks the
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
Fig.2 Pinning diagram.
HEF4508BP(N):
24-lead DIL; plastic
(SOT101-1)
HEF4508BD(F):
24-lead DIL; ceramic (cerdip)
(SOT94)
HEF4508BT(D):
24-lead SO; plastic
(SOT137-1)
( ): Package Designator North America
PINNING
D0A to D3A, D0B to D3B
data inputs
STA , STB
strobe inputs
MRA, MRB
master reset inputs
EOA, EOB
output enable inputs
O0A to O3A, O0B to O3B
3-state outputs
FUNCTION TABLE
INPUTS
OUTPUT
MR
ST
EO
Dn
On
L
H
L
H
H
L
H
L
L
L
L
L
L
X
latched
H
X
L
X
L
X
X
H
X
Z
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Z = high impedance OFF state
January 1995
3
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
Fig.3 Logic diagram (one 4-bit latch).
January 1995
4
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4.
VDD
V
SYMBOL
MIN.
TYP.
TYPICAL EXTRAPOLATION
FORMULA
MAX.
Propagation delays
ST → On
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
Dn → On
HIGH to LOW
5
10
tPHL
15
HIGH to LOW
Output transition times
HIGH to LOW
LOW to HIGH
ns
88 ns + (0,55 ns/pF) CL
100
ns
39 ns + (0,23 ns/pF) CL
35
70
ns
27 ns + (0,16 ns/pF) CL
115
230
ns
88 ns + (0,55 ns/pF) CL
50
100
ns
39 ns + (0,23 ns/pF) CL
35
70
ns
27 ns + (0,16 ns/pF) CL
95
190
ns
68 ns + (0,55 ns/pF) CL
40
80
ns
29 ns + (0,23 ns/pF) CL
30
60
ns
22 ns + (0,16 ns/pF) CL
95
190
ns
68 ns + (0,55 ns/pF) CL
80
ns
29 ns + (0,23 ns/pF) CL
30
60
ns
22 ns + (0,16 ns/pF) CL
100
200
ns
73 ns + (0,55 ns/pF) CL
40
80
ns
29 ns + (0,23 ns/pF) CL
15
30
60
ns
22 ns + (0,16 ns/pF) CL
5
60
120
ns
10 ns + (1,0 ns/pF) CL
10
tPLH
15
MR → On
230
50
40
5
LOW to HIGH
115
5
10
tPHL
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
5
60
120
ns
10
tTHL
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
5
45
90
ns
10
tTLH
3-state propagation
delays
Output enable times
EO → On
HIGH
LOW
10
tPZH
20
40
ns
15
18
36
ns
5
45
90
ns
10
tPZL
20
40
ns
15
18
36
ns
5
35
70
ns
Output disable times
EO → On
HIGH
LOW
10
tPHZ
20
40
ns
15
18
36
ns
5
45
90
ns
20
40
ns
18
36
ns
10
tPLZ
15
January 1995
10 ns + (1,0 ns/pF) CL
5
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Minimum ST
pulse width; HIGH
Minimum MR pulse
width; HIGH
Recovery time
for MR
SYMBOL
5
MIN. TYP.
MAX.
50
25
ns
30
15
ns
15
20
10
ns
5
40
20
ns
10
10
tWSTH
tWMRH
24
12
ns
15
20
10
ns
5
20
0
ns
10
tRMR
20
0
ns
15
15
0
ns
Set-up times
5
35
10
ns
Dn → ST
10
25
5
ns
15
20
0
ns
Hold times
5
20
0
ns
Dn → ST
10
20
0
ns
15
0
ns
15
VDD
V
Dynamic power
5
tsu
thold
see also waveforms Fig.4
TYPICAL FORMULA FOR P (µW)
2 000 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
dissipation per
10
9 000 fi + ∑ (foCL) ×
package (P)
15
25 000 fi + ∑ (foCL) ×
VDD2
VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
6
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Philips Semiconductors
Dual 4-bit latch
January 1995
7
Product specification
Waveforms showing minimum ST and MR pulse widths, set-up and hold times for Dn to ST, recovery time for MR and propagation
delays from ST to On, to Dn to On and MR to On.
HEF4508B
MSI
Fig.4
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
APPLICATION INFORMATION
Some examples of application for the HEF4508B are:
• Buffer storage
• Holding registers
• Data storage and multiplexing
Fig.5 Example of a bus register using HEF4508B and HEF4015B.
January 1995
8
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Philips Semiconductors
Dual 4-bit latch
January 1995
9
Fig.6 Example of a dual multiplexed bus register with function select using two HEF4508B and one HEF4019B.
FUNCTION SELECT
FUNCTION
L
L
inhibit (all L)
H
L
select A bus
L
H
select B bus
H
H
A1 + B1
Product specification
SB
HEF4508B
MSI
SA