INTEGRATED CIRCUITS 74F132 Quad 2-input NAND Schmitt trigger Product specification IC15 Data Handbook 1991 Jun 26 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74F132 DESCRIPTION PIN CONFIGURATION The 74F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have greater noise margin than conventional NAND gates. Each circuit contains a 2-input Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem-pole output. The Scmitt trigger uses positive feedback to effectively speed-up slow input transitions and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input threshold (typically 800mV) is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations. As long as three inputs remain at a more positive voltage than VT+MAX, the gate will respond in the transition of the other input as shown in Waveform 1. D0a 1 14 VCC D0b 2 13 D3b Q0 3 12 D3a D1a 4 11 Q3 D1b 5 10 D2b Q1 6 9 D2a GND 7 8 Q2 SF00710 TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F132 6.3ns 13mA ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 14-pin plastic DIP N74F132N SOT27-1 14-pin plastic SO N74F132D SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dna, Dnb Data inputs 1.0/1.0 20µA/0.6mA Qn Data output 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 1 & 3 1 2 D0a D0b 4 5 9 10 12 13 D2a D2b D3a D3b 2 4 D1a D1b 6 5 Q0 Q1 Q2 9 Q3 8 10 3 6 8 11 12 11 VCC = Pin 14 GND = Pin 7 1991 Jun 26 13 SF00711 SF00712 2 853–0342 03094 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74F132 LOGIC DIAGRAM D0a D0b D1a D1b D2a D2b VCC = Pin 14 GND = Pin 7 D3a D3b FUNCTION TABLE 1 3 2 4 5 6 9 8 10 12 11 13 INPUTS Q0 Q1 Q2 Q3 SF00002 OUTPUT Dna Dnb Qn L L H L H H H L H H H NOTES: H = High voltage level L = Low voltage level L ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) RATING UNIT VCC Supply voltage PARAMETER –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature SYMBOL –30 to +5 mA –0.5 to VCC V 40 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 4.5 5.0 5.5 V VCC Supply voltage IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range +70 °C 1991 Jun 26 0 3 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74F132 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN TYP2 MAX UNIT VT+ Positive-going threshold VCC = 5.0V 1.5 1.7 2.0 V VT– Negative-going threshold– VCC = 5.0V 0.7 0.9 1.1 V VT Hysteresis (VT+ – VT–) VCC = 5.0V 0.4 0.8 VOH O High level output voltage High-level VOL O Low level output voltage Low-level VIK Input clamp voltage IT+ Input current at positive-going threshold IT– II V VCC = MIN, ±10%VCC 2.5 VI=VT–MAX, IOH = MAX ±5%VCC 2.7 VCC = MIN, ±10%VCC 0.30 0.50 VI=VT+MAX, IOL = MAX ±5%VCC 0.30 0.50 VCC = MIN, II = IIK –0.73 –1.2 VCC = 5.0V, VI=VT+ 0 Input current at negative-going threshold VCC = 5.0V, VI=VT– –350 Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOS Short-circuit output current3 VCC = MAX –150 mA ICC Supply current (total) ICCH ICCL VCC = MAX V 3.4 –60 V V µA µA VI N= GND 8.5 12.0 VIN = 4.5V 13.0 19.5 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1991 Jun 26 4 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74F132 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL TEST CONDITION PARAMETER tPLH tPHL Propagation delay Dna, Dnb to Qn VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω MIN TYP MAX MIN MAX 3.5 4.5 5.5 6.0 7.0 8.5 3.0 4.5 8.5 9.0 Waveform 1 UNIT ns AC WAVEFORMS For all waveforms, VM = 1.5V. Dna, Dnb VM VM tPHL tPLH VM Qn VM SF00005 Waveform 1. For Inverting Outputs TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN tw 90% 10% D.U.T. RT CL RL AMP (V) VM VM VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% POSITIVE PULSE VM VM 10% Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw tTLH tTHL 500ns 2.5ns 2.5ns SF00006 1991 Jun 26 5 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74F132 DIP14: plastic dual in-line package; 14 leads (300 mil) 1991 Jun 26 6 SOT27-1 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74F132 SO14: plastic small outline package; 14 leads; body width 3.9 mm 1991 Jun 26 7 SOT108-1 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74F132 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 8 Date of release: 10-98 9397-750-05074