INTEGRATED CIRCUITS 74LV20 Dual 4-input NAND gate Product specification Supersedes data of 1997 Mar 28 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Product specification Dual 4-input NAND gate 74LV20 FEATURES DESCRIPTION • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, The 74LV20 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT20. The 74LV20 provides the 4–input NAND function. Tamb = 25°C • Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C • Output capability: standard • ICC category: SSI QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf 2.5 ns PARAMETER SYMBOL tPHL/tPLH Propagation delay nA, nB, nC, nD to nY CI Input capacitance CPD Power dissipation capacitance per gate CONDITIONS TYPICAL UNIT 8 ns 3.5 pF 22 pF CL = 15pF VCC = 3.3V Notes 1 and 2 NOTES: 1 CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2 The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL –40°C to +125°C 74LV20 N 74LV20 N SOT27-1 14-Pin Plastic SO –40°C to +125°C 74LV20 D 74LV20 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +125°C 74LV20 DB 74LV20 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +125°C 74LV20 PW 74LV20PW DH SOT402-1 PIN DESCRIPTION PIN NUMBER FUNCTION TABLE SYMBOL INPUTS FUNCTION nA nB nC nD nY L X X X H Data inputs X L X X H No connection X X L X H X L H H H L 1, 9 1A to 2A Data inputs 2, 10 1B to 2B 3, 11 NC 4, 12 1C to 2C Data inputs X X 5, 13 1D to 2D Data inputs H H 6, 8 1Y to 2Y Data outputs 7 GND Ground (0V) 14 VCC Positive supply voltage 1998 Apr 20 OUTPUTS NOTES: H = HIGH voltage level L = LOW voltage level X = Don’t care 2 853–1962 19256 Philips Semiconductors Product specification Dual 4-input NAND gate 74LV20 PIN CONFIGURATION LOGIC SYMBOL 1 1A 1 14 VCC 2 1B 2 13 2D 4 NC 3 12 2C 5 1C 4 11 NC 1D 5 10 2B 1Y 6 9 2A GND 7 8 2Y 9 10 12 13 1A 1B 1Y 1C 1D 2A 2B 2Y 2C 8 2D SV00361 SV00360 LOGIC SYMBOL (IEEE/IEC) 1 6 LOGIC DIAGRAM & A 2 B 6 4 Y C 5 D 9 & SV00363 10 12 8 13 SV00362 1998 Apr 20 3 Philips Semiconductors Product specification Dual 4-input NAND gate 74LV20 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER VI Input voltage VO Output voltage Tamb tr, tf CONDITIONS MIN TYP. MAX UNIT See Note1 1.0 3.3 3.6 V 0 – VCC V 0 – VCC V +85 +125 °C 500 200 100 ns/V DC supply voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V Input rise and fall times –40 –40 – – – – – – – NOTES: 1 The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER VCC DC supply voltage CONDITIONS RATING UNIT –0.5 to +4.6 V ±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA ±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA ±IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 ±IGND, ±ICC Tstg PTOT DC VCC or GND current for types with –standard outputs 50 Storage temperature range Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) –65 to +150 for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mA mA °C mW NOTES: 1 Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 20 4 Philips Semiconductors Product specification Dual 4-input NAND gate 74LV20 DC CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS TYP1 MIN VIH VIL HIGH level Input voltage LOW level Input voltage VOH HIGH level output voltage; all outputs VOH HIGH level output voltage; STANDARD outputs -40°C to +125°C MAX MIN VCC = 1.2V 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 V VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 VCC = 1.2V; VI = VIH or VIL; –IO = 100µA VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 3.0V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 UNIT MAX V 1.2 V V VCC = 1.2V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA VCC = 3.0V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 0 0.2 0.2 0.25 0.40 0.50 V VOL LOW level output voltage; all outputs VOL LOW level output voltage; STANDARD outputs VCC = 3.0V;VI = VIH or VIL; IO = 6mA Input leakage current VCC = 3.6V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; SSI VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 40 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA II V NOTE: 1 All typical values are measured at Tamb = 25°C. AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL tPHL/tPLH PARAMETER Propagation g delay y nA, nB, nC, nD to nY WAVEFORM VCC(V) MIN TYP1 1.2 – 2.0 – 2.7 3.0 to 3.6 Figures 1 1, 2 NOTE: 1 Unless otherwise stated, all typical values are at Tamb = 25°C. 2 Typical value measured at VCC = 3.3V. 1998 Apr 20 LIMITS –40 to +85 °C CONDITION 5 LIMITS –40 to +125 °C MAX MIN 50 – – – 17 32 – 39 – 13 24 – 29 – 102 19 – 23 UNIT MAX ns Philips Semiconductors Product specification Dual 4-input NAND gate 74LV20 AC WAVEFORMS TEST CIRCUIT VM = 1.5V at VCC 2.7V 3.6V VM = 0.5V * VCC at VCC 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VCC VO VI PULSE GENERATOR D.U.T. 50pF VI nA, nB, nC, nD INPUT RT RL = 1k VM Test Circuit for switching times GND tPHL DEFINITIONS tPLH RL = Load resistor VOH nY OUTPUT CL CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VM TEST VCC VI VOL tPLH/tPHL < 2.7V 2.7–3.6V VCC 2.7V SV00364 SV00901 Figure 1.Input (nA, nB, nC, nD) to output (nY) propagation delays. 1998 Apr 20 Figure 2. Load circuitry for switching times 6 Philips Semiconductors Dual 4-input NAND gate DIP14: plastic dual in-line package; 14 leads (300 mil) 1998 Apr 28 Product specification 74LV20 SOT27-1 Philips Semiconductors Dual 4-input NAND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm 1998 Apr 28 Product specification 74LV20 SOT108-1 Philips Semiconductors Dual 4-input NAND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm 1998 Apr 28 Product specification 74LV20 SOT337-1 Philips Semiconductors Dual 4-input NAND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 1998 Apr 28 Product specification 74LV20 SOT402-1 Philips Semiconductors Product specification Dual 4-input NAND gate 74LV20 NOTES 1998 Apr 28 Philips Semiconductors Product specification Dual 4-input NAND gate 74LV20 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. 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Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1998 Apr 28 Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-044011