74AUP1G0832 Low-power 3-input AND-OR gate Rev. 02 — 3 July 2009 Product data sheet 1. General description The 74AUP1G0832 provides the Boolean function: Y = (A × B) + C. The user can choose the logic functions OR, AND and AND-OR. All inputs can be connected to VCC or GND. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features n Wide supply voltage range from 0.8 V to 3.6 V n High noise immunity n Complies with JEDEC standards: u JESD8-12 (0.8 V to 1.3 V) u JESD8-11 (0.9 V to 1.65 V) u JESD8-7 (1.2 V to 1.95 V) u JESD8-5 (1.8 V to 2.7 V) u JESD8-B (2.7 V to 3.6 V) n ESD protection: u HBM JESD22-A114E Class 3A exceeds 5000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Low static power consumption; ICC = 0.9 µA (maximum) n Latch-up performance exceeds 100 mA per JESD 78 Class II n Inputs accept voltages up to 3.6 V n Low noise overshoot and undershoot < 10 % of VCC n IOFF circuitry provides partial Power-down mode operation n Multiple package options n Specified from −40 °C to +85 °C and −40 °C to +125 °C 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G0832GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP1G0832GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74AUP1G0832GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Type number Marking code[1] 74AUP1G0832GW aY 74AUP1G0832GM aY 74AUP1G0832GF aY [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A B C 1 3 6 4 Y 001aad943 Fig 1. Logic symbol 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 2 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate 6. Pinning information 6.1 Pinning 74AUP1G0832 74AUP1G0832 A 1 6 A 1 6 C GND 2 5 VCC C GND 2 5 VCC B 3 4 Y B 3 4 Y 74AUP1G0832 A 1 6 C GND 2 5 VCC B 3 4 Y 001aad941 001aad942 Transparent top view Transparent top view 001aad940 Fig 2. Pin configuration SOT363 (SC-88) Fig 3. Pin configuration SOT886 (XSON6) Fig 4. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Pin description Symbol Pin Description A 1 data input A GND 2 ground (0 V) B 3 data input B Y 4 data output Y VCC 5 supply voltage C 6 data input C 7. Functional description Table 4. Function table[1] Input Output C B A Y L L L L L L H L L H L L L H H H H L L H H L H H H H L H H H H H [1] H = HIGH voltage level; L = LOW voltage level. 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 3 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate 7.1 Logic configurations Table 5. Function selection table Logic function Figure 2-input AND see Figure 5 2-input OR see Figure 6 and 7 3-input gate with the Boolean function: Y = (A × B) + C see Figure 8 VCC A B Y A B 1 2 3 6 5 4 B C VCC Y Y B 1 2 3 001aad944 Y Fig 6. 2-input OR gate VCC Y C 001aad945 Fig 5. 2-input AND gate A C 6 5 4 A 1 2 3 6 5 4 VCC A B C C Y Y A B 1 2 3 6 5 4 001aad946 C Y 001aad947 Fig 7. 2-input OR gate Fig 8. 3-input gate with the Boolean function: Y = (A × B) + C 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current Conditions VI < 0 V [1] VI input voltage IOK output clamping current VO < 0 V [1] Min Max Unit −0.5 +4.6 V −50 - mA −0.5 +4.6 V −50 - mA −0.5 +4.6 V - ±20 mA VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 250 mW Tamb = −40 °C to +125 °C [2] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 4 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V −40 +125 °C 0 200 ns/V Typ Max Unit Tamb ambient temperature ∆t/∆V input transition rise and fall rate VCC = 0.8 V to 3.6 V 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V 0.70 × VCC - - V VCC = 0.9 V to 1.95 V 0.65 × VCC - - V Tamb = 25 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30 × VCC V VCC = 0.9 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V VI = VIH or VIL IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.11 - - V IO = −1.9 mA; VCC = 1.65 V 1.32 - - V IO = −2.3 mA; VCC = 2.3 V 2.05 - - V IO = −3.1 mA; VCC = 2.3 V 1.9 - - V IO = −2.7 mA; VCC = 3.0 V 2.72 - - V IO = −4.0 mA; VCC = 3.0 V 2.6 - - V VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 5 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.2 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 µA CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF VCC = 0.8 V 0.70 × VCC - - V VCC = 0.9 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V V [1] Tamb = −40 °C to +85 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 3.0 V to 3.6 V 2.0 - - VCC = 0.8 V - - 0.30 × VCC V VCC = 0.9 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.03 - - V IO = −1.9 mA; VCC = 1.65 V 1.30 - - V IO = −2.3 mA; VCC = 2.3 V 1.97 - - V IO = −3.1 mA; VCC = 2.3 V 1.85 - - V IO = −2.7 mA; VCC = 3.0 V 2.67 - - V IO = −4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V VI = VIH or VIL VI = VIH or VIL IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 µA II input leakage current IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.6 µA 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 6 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 µA [1] Tamb = −40 °C to +125 °C HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL VCC = 0.8 V 0.75 × VCC - - V VCC = 0.9 V to 1.95 V 0.70 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.25 × VCC V VCC = 0.9 V to 1.95 V - - 0.30 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.11 - - V IO = −1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 0.93 - - V IO = −1.9 mA; VCC = 1.65 V 1.17 - - V IO = −2.3 mA; VCC = 2.3 V 1.77 - - V IO = −3.1 mA; VCC = 2.3 V 1.67 - - V IO = −2.7 mA; VCC = 3.0 V 2.40 - - V IO = −4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 VI = VIH or VIL V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V IO = 4.0 mA; VCC = 3.0 V - - ±0.75 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.75 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 µA [1] [1] One input at VCC − 0.6 V, other input at VCC or GND. 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 7 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) - 19.5 - - - - VCC = 1.1 V to 1.3 V 2.5 5.6 11.1 2.2 11.3 12.4 ns VCC = 1.4 V to 1.6 V 1.9 3.9 6.4 2.0 6.9 7.6 ns VCC = 1.65 V to 1.95 V 1.6 3.1 5.1 1.5 5.7 6.3 ns VCC = 2.3 V to 2.7 V 1.4 2.4 3.7 1.3 4.2 4.6 ns VCC = 3.0 V to 3.6 V 1.3 2.2 3.2 1.2 3.5 3.9 ns - 23.1 - - - - ns VCC = 1.1 V to 1.3 V 2.8 6.5 12.7 2.5 12.9 14.2 ns VCC = 1.4 V to 1.6 V 2.2 4.5 7.4 2.3 8.0 8.8 ns VCC = 1.65 V to 1.95 V 2.0 3.7 5.9 1.8 6.6 7.3 ns VCC = 2.3 V to 2.7 V 1.8 3.0 4.4 1.6 4.9 5.4 ns VCC = 3.0 V to 3.6 V 1.6 2.7 3.9 1.5 4.2 4.6 ns - 26.6 - - - - ns VCC = 1.1 V to 1.3 V 3.2 7.3 14.2 2.8 14.7 16.2 ns VCC = 1.4 V to 1.6 V 2.5 5.1 8.3 2.6 9.1 10.0 ns VCC = 1.65 V to 1.95 V 2.3 4.2 6.7 2.0 7.5 8.3 ns VCC = 2.3 V to 2.7 V 2.1 3.4 5.0 1.9 5.6 6.2 ns VCC = 3.0 V to 3.6 V 1.9 3.2 4.5 1.8 4.8 5.3 ns - 34.8 - - - - ns VCC = 1.1 V to 1.3 V 4.1 9.5 19.0 3.6 19.8 21.8 ns VCC = 1.4 V to 1.6 V 3.3 6.6 11.0 3.3 12.1 13.3 ns VCC = 1.65 V to 1.95 V 3.0 5.5 8.8 2.6 10.0 11.0 ns VCC = 2.3 V to 2.7 V 2.8 4.5 6.6 2.5 7.4 8.3 ns VCC = 3.0 V to 3.6 V 2.6 4.3 5.9 2.4 6.4 7.0 ns CL = 5 pF tpd propagation delay A, B or C to Y; see Figure 9 [2] VCC = 0.8 V ns CL = 10 pF tpd propagation delay A, B or C to Y; see Figure 9 [2] VCC = 0.8 V CL = 15 pF tpd propagation delay A, B or C to Y; see Figure 9 [2] VCC = 0.8 V CL = 30 pF tpd propagation delay A, B or C to Y; see Figure 9 VCC = 0.8 V [2] 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 8 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC = 0.8 V - 2.5 - - - - pF VCC = 1.1 V to 1.3 V - 2.7 - - - - pF Tamb = 25 °C power dissipation capacitance CPD [3] fi = 1 MHz; VI = GND to VCC VCC = 1.4 V to 1.6 V - 2.8 - - - - pF VCC = 1.65 V to 1.95 V - 2.9 - - - - pF VCC = 2.3 V to 2.7 V - 3.4 - - - - pF VCC = 3.0 V to 3.6 V - 4.0 - - - - pF [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 12. Waveforms VI A, B, C input VM VM GND t PHL t PLH VOH VM Y output VM VOL t PLH t PHL VOH Y output VM VOL VM 001aab593 Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Input A, B and C to output Y propagation delay times 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 9 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns VCC VEXT 5 kΩ G VI VO DUT RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Load circuitry for switching times Table 11. Test data Supply voltage Load VEXT VCC CL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ [1] RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 × VCC For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 10 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate 13. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 11. Package outline SOT363 (SC-88) 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 11 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 12. Package outline SOT886 (XSON6) 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 12 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 e1 4 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 13. Package outline SOT891 (XSON6) 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 13 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1G0832_2 20090703 Product data sheet - 74AUP1G0832_1 Modifications: • Section 8 “Limiting values”: Changed: Derating factor of XSON6 packages. • Section 11 “Dynamic characteristics”: Changed: typical power dissipation capacitance. 74AUP1G0832_1 20061108 Product data sheet 74AUP1G0832_2 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 14 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AUP1G0832_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 15 of 16 74AUP1G0832 NXP Semiconductors Low-power 3-input AND-OR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 July 2009 Document identifier: 74AUP1G0832_2