PHILIPS HEF4029B

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4029B
MSI
Synchronous up/down counter,
binary/decade counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Information on P0 to P3 is asynchronously loaded into the
counter while PL is HIGH, independent of CP.
DESCRIPTION
The HEF4029B is a synchronous edge-triggered up/down
4-bit binary/BCD decade counter with a clock input (CP),
an active LOW count enable input (CE), an up/down
control input (UP/DN), a binary/decade control input
(BIN/DEC), an overriding asynchronous active HIGH
parallel load input (PL), four parallel data inputs (P0 to P3),
four parallel buffered outputs (O0 to O3) and an active
LOW terminal count output (TC).
The counter is advanced one count on the LOW to HIGH
transition of CP when CE and PL are LOW. The TC signal
is normally HIGH and goes LOW when the counter
reaches its maximum count in the UP mode, or the
minimum count in the DOWN mode provided CE is LOW.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING
HEF4029BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4029BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4029BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PL
parallel load input
P0 to P3
parallel data inputs
BIN/DEC
binary/decade control input
UP/DN
up/down control input
CE
count enable input (active LOW)
CP
clock input (LOW to HIGH, edge triggered)
O0 to O3
buffered parallel outputs
TC
terminal count output (active LOW)
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.3 Logic diagram (continued in Fig.4).
January 1995
3
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.4 Logic diagram (continued from Fig.3).
January 1995
4
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
FUNCTION TABLE
PL
BIN/DEC
UP/DN
CE
CP
MODE
H
X
X
X
X
parallel load (Pn → On)
L
X
X
H
X
no change
L
L
L
L
count-down, decade
L
L
H
L
count-up, decade
L
H
L
L
count-down, binary
L
H
H
L
count-up, binary
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going clock pulse edge
Fig.5 State diagram; BIN/DEC = LOW.
January 1995
5
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.6 State diagram; BIN/DEC = HIGH.
Logic equation for terminal count:
TC = CE (BIN ⁄ DEC • UP ⁄ DN • O 0 • O 1 • O 2 • O 3 + BIN ⁄ DEC • UP ⁄ DN • O 0 • O 1 • O 2 • O 3 +
BIN ⁄ DEC • UP ⁄ DN • O 0 • O 3 + BIN ⁄ DEC • UP ⁄ DN • O 0 • O 1 • O 2 • O 3 )
January 1995
6
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1000 fi + ∑(foCL) × VDD2
dissipation per
10
package (P)
15
4500 fi + ∑(foCL) × VDD2
11 500 fi + ∑(foCL) × VDD2
Dynamic power
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
TYPICAL EXTRAPOLATION
FORMULA
MAX.
Propagation delays
CP → On
HIGH to LOW
LOW to HIGH
CP → TC
HIGH to LOW
LOW to HIGH
PL → On
HIGH to LOW
LOW to HIGH
CE → TC
HIGH to LOW
LOW to HIGH
5
290
ns
118 ns +
(0,55 ns/pF) CL
55
110
ns
44 ns +
(0,23 ns/pF) CL
15
40
75
ns
32 ns +
(0,16 ns/pF) CL
5
160
315
ns
133 ns +
(0,55 ns/pF) CL
10
tPHL
60
120
ns
49 ns +
(0,23 ns/pF) CL
15
40
80
ns
32 ns +
(0,16 ns/pF) CL
5
280
560
ns
253 ns +
(0,55 ns/pF) CL
10
tPLH
105
205
ns
94 ns +
(0,23 ns/pF) CL
15
70
140
ns
62 ns +
(0,16 ns/pF) CL
5
195
385
ns
168 ns +
(0,55 ns/pF) CL
75
150
ns
64 ns +
(0,23 ns/pF) CL
10
10
tPHL
tPLH
15
55
105
ns
47 ns +
(0,16 ns/pF) CL
5
120
240
ns
93 ns +
(0,55 ns/pF) CL
50
100
ns
39 ns +
(0,23 ns/pF) CL
10
tPHL
15
35
70
ns
27 ns +
(0,16 ns/pF) CL
5
170
335
ns
143 ns +
(0,55 ns/pF) CL
65
130
ns
54 ns +
(0,23 ns/pF) CL
10
tPLH
15
45
90
ns
37 ns +
(0,16 ns/pF) CL
5
180
360
ns
153 ns +
(0,55 ns/pF) CL
70
140
ns
59 ns +
(0,23 ns/pF) CL
10
tPHL
15
50
100
ns
42 ns +
(0,16 ns/pF) CL
5
170
335
ns
143 ns +
(0,55 ns/pF) CL
65
135
ns
54 ns +
(0,23 ns/pF) CL
50
100
ns
42 ns +
(0,16 ns/pF) CL
10
tPLH
15
January 1995
145
7
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
VDD
V
Output transition times
HIGH to LOW
LOW to HIGH
SYMBOL
HEF4029B
MSI
MIN.
TYP.
5
60
120
ns
10 ns +
(1,0 ns/pF) CL
30
60
ns
9 ns +
(0,42 ns/pF) CL
15
20
40
ns
6 ns +
(0,28 ns/pF) CL
5
60
120
ns
10 ns +
(1,0 ns/pF) CL
30
60
ns
9 ns +
(0,42 ns/pF) CL
20
40
ns
6 ns +
(0,28 ns/pF) CL
10
10
tTHL
tTLH
15
January 1995
TYPICAL EXTRAPOLATION
FORMULA
MAX.
8
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Minimum clock
pulse width; LOW
Minimum PL
pulse width; HIGH
Recovery time
for PL
Set-up times
BIN/DEC → CP
UP/DN → CP
CE → CP
Pn → PL
Hold times
BIN/DEC → CP
UP/DN → CP
CE → CP
Pn → PL
SYMBOL
5
pulse frequency
MAX
110
55
ns
35
20
ns
25
15
ns
5
160
80
ns
10
tWCPL
tWPLH
55
25
ns
15
35
15
ns
5
150
75
ns
10
tRPL
50
25
ns
15
35
20
ns
5
270
135
ns
90
45
ns
15
10
60
30
ns
5
300
150
ns
10
tsu
105
55
ns
15
75
35
ns
5
240
120
ns
90
50
ns
15
70
40
ns
5
70
35
ns
20
10
ns
10
10
tsu
tsu
tsu
15
10
5
ns
5
45
−90
ns
15
−30
ns
10
thold
15
10
−20
ns
5
15
−135
ns
0
−50
ns
15
−5
−35
ns
5
30
−30
ns
10
−10
ns
15
5
−10
ns
5
15
−20
ns
0
−10
ns
0
−5
ns
10
10
10
thold
thold
thold
5
10
15
January 1995
TYP
15
10
15
Maximum clock
MIN
fmax
2
4
MHz
5
10
MHz
8
15
MHz
9
see also waveforms
Figs 7 and 8
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.7
Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP, BIN/DEC to CP
and UP/DN to CP. Set-up and hold times are shown as positive values but may be specified as negative
values.
Fig.8
Waveforms showing minimum pulse width for PL, recovery time for PL, and set-up and hold times for Pn
to PL. Set-up and hold times are shown as positive values but may be specified as negative values.
January 1995
10
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Philips Semiconductors
Synchronous up/down counter,
binary/decade counter
January 1995
11
Product specification
HEF4029B
MSI
Fig.9 Timing diagram; decade mode; P0 = LOW; P3 = LOW; BIN/DEC = LOW.
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Philips Semiconductors
Synchronous up/down counter,
binary/decade counter
January 1995
12
Product specification
HEF4029B
MSI
Fig.10 Timing diagram; binary mode; P0 = HIGH; P1 = LOW; BIN/DEC = HIGH.
Philips Semiconductors
Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
APPLICATION INFORMATION
Some examples of applications for the HEF4029B are:
• Programmable binary and decade counting/frequency synthesizers - BCD output.
• Analogue-to-digital and digital-to-analogue conversion.
• Up/down binary counting.
• Magnitude and sign generation.
• Up/down decade counting.
• Difference counting.
January 1995
13
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Philips Semiconductors
Synchronous up/down counter,
binary/decade counter
January 1995
Fig.11 Example of parallel clocking when cascading HEF4029B ICs.
14
Product specification
Fig.12 Example of ripple clocking when cascading HEF4029B ICs. Ripple clocking mode: the up/down control can be changed at any count;
the only restriction on changing the up/down control is that the clock input to the first counting stage must be HIGH.
HEF4029B
MSI
Note
TC lines at all stages after the first may have a negative-going glitch pulse resulting from differential delays of different HEF4029B ICs. These
negative-going glitches do not affect proper HEF4029B operation; however if the TC signals are used to trigger other edge-sensitive logic devices,
such as flip-flops or counters, the TC signals should be gated with the clock signal using a 2-input OR gate such as HEF4071B.