PHILIPS 74AHC1G09

74AHC1G09
2-input AND gate with open-drain output
Rev. 02 — 18 December 2007
Product data sheet
1. General description
The 74AHC1G09 is a high-speed Si-gate CMOS device.
The 74AHC1G09 provides the 2-input AND function with open-drain output.
The output of the 74AHC1G09 is an open drain and can be connected to other open-drain
outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. For
digital operation this device must have a pull-up resistor to establish a logic HIGH level.
2. Features
■
■
■
■
High noise immunity
Low power dissipation
SOT353-1 and SOT753 package options
ESD protection:
◆ HBM JESD22-A114E: exceeds 2000 V
◆ MM JESD22-A115-A: exceeds 200 V
◆ CDM JESD22-C101C: exceeds 1000 V
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC1G09GW
−40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74AHC1G09GV
−40 °C to +125 °C
SC-74A
plastic surface-mounted package; 5 leads
SOT753
4. Marking
Table 2.
Marking
Type number
Marking code
74AHC1G09GW
A9
74AHC1G09GV
A09
74AHC1G09
NXP Semiconductors
2-input AND gate with open-drain output
5. Functional diagram
Y
A
B
A
1
4
2
1
Y
&
2
001aad598
Fig 1. Logic symbol
4
GND
B
001aad599
001aad600
Fig 2. IEC logic symbol
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
B
1
A
2
GND
3
5
VCC
4
Y
09
001aad601
Fig 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
B
1
data input B
A
2
data input A
GND
3
ground (0 V)
Y
4
data output Y
VCC
5
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
A
B
L
L
L
L
H
L
H
L
L
H
H
Z
[1]
Y
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
74AHC1G09_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 18 December 2007
2 of 10
74AHC1G09
NXP Semiconductors
2-input AND gate with open-drain output
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
Min
Max
Unit
−0.5
+7.0
V
[1]
−0.5
+7.0
V
active mode
[1]
−0.5
+7.0
V
high-impedance mode
[1]
−0.5
+7.0
V
input clamping current
VI < −0.5 V
[1]
-
−20
mA
IOK
output clamping current
VO < −0.5 V
[1]
IO
output current
VO > −0.5 V
ICC
VI
input voltage
VO
output voltage
IIK
-
±20
mA
-
25
mA
supply current
-
±75
mA
IGND
GND current
-
±75
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
-
250
mW
Tamb = −40 °C to +125 °C
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating operations
Symbol
Parameter
VCC
VI
VO
output voltage
Conditions
Min
Typ
Max
Unit
supply voltage
2.0
5.0
5.5
V
input voltage
0
-
5.5
V
active mode
0
-
VCC
V
high-impedance mode
0
-
6.0
V
Tamb
ambient temperature
−40
+25
+125
°C
∆t/∆V
input transition rise and fall rate VCC = 3.0 V to 3.6 V
-
-
100
ns/V
VCC = 4.5 V to 5.5 V
-
-
20
ns/V
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
HIGH-level
input voltage
LOW-level
input voltage
25 °C
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
-
-
1.5
-
1.5
-
V
VCC = 3.0 V
2.1
-
-
2.1
-
2.1
-
V
VCC = 5.5 V
3.85
-
-
3.85
-
3.85
-
V
VCC = 2.0 V
-
-
0.5
-
0.5
-
0.5
V
VCC = 3.0 V
-
-
0.9
-
0.9
-
0.9
V
VCC = 5.5 V
-
-
1.65
-
1.65
-
1.65
V
74AHC1G09_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 18 December 2007
3 of 10
74AHC1G09
NXP Semiconductors
2-input AND gate with open-drain output
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOL
25 °C
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
LOW-level
VI = VIH or VIL
output voltage
IO = 50 µA; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 µA; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 µA; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
-
-
±0.1
-
±1.0
-
±2.0
µA
OFF-state
VI = VIH or VIL; VO = VCC or
output current GND; VCC = 5.5 V
-
-
±0.25
±10.0
µA
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
1.0
-
10
-
20
µA
CI
input
capacitance
-
1.5
10
-
10
-
10
pF
II
input leakage
current
IOZ
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
±2.5
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; for test circuit see Figure 6.
Symbol Parameter
25 °C
Conditions
Min
VCC = 3.0 V to 3.6 V
CL = 50 pF
VCC = 4.5 V to 5.5 V
Max
Min
Max
-
4.6
7.5
1.0
8.5
1.0
9.0
ns
-
6.5
11.0
1.5
12.0
1.5
12.5
ns
-
3.2
5.5
1.0
6.5
1.0
7.0
ns
-
4.6
7.5
1.5
8.0
1.5
8.5
ns
-
5
-
-
-
-
-
pF
[3]
CL = 15 pF
CL = 50 pF
power dissipation
capacitance
Min
[2]
CL = 15 pF
CPD
Typ Max
[1]
propagation delay A and B to Y;
see Figure 5
tpd
−40 °C to +85 °C −40 °C to +125 °C Unit
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[4]
[1]
tpd is the same as tPZL and tPLZ.
[2]
Typical values are measured at VCC = 3.3 V.
[3]
Typical values are measured at VCC = 5.0 V.
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL × VCC2 × fo) = dissipation due to the output if the combination of the pull up voltage and resistance results in VCC at the output.
74AHC1G09_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 18 December 2007
4 of 10
74AHC1G09
NXP Semiconductors
2-input AND gate with open-drain output
12. Waveforms
VI
A, B input
VM
GND
t PLZ
t PZL
VCC
Y output
VM
VX
VOL
001aad602
Measurement points are given in Table 9.
VOL is the typical voltage output level that occur with the output load.
Fig 5. The data input (A, B) to output (Y) propagation delays
Table 9.
Measurement points
Input
Output
VM
VM
VX
0.5VCC
0.5VCC
VOL + 0.3 V
S1
VCC
PULSE
GENERATOR
VI
RL =
1000 Ω
VO
VCC
open
GND
D.U.T.
CL
RT
mna232
Test data is given in Table 10.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6. Load circuit for switching times
Table 10.
Test data
Input
Load
S1
VI
tr, tf
RL
CL
tPHZ, tPZH
tPLZ, tPZL
tPLH, tPHL
GND to VCC
≤ 3.0 ns
1000 Ω
15 pF
GND
VCC
open
GND to VCC
≤ 3.0 ns
1000 Ω
50 pF
GND
VCC
open
74AHC1G09_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 18 December 2007
5 of 10
74AHC1G09
NXP Semiconductors
2-input AND gate with open-drain output
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
E
D
SOT353-1
A
X
c
y
HE
v M A
Z
5
4
A2
A
(A3)
A1
θ
1
Lp
3
L
e
w M
bp
detail X
e1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
e1
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.1
0
1.0
0.8
0.15
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
0.65
1.3
2.25
2.0
0.425
0.46
0.21
0.3
0.1
0.1
0.60
0.15
7°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT353-1
REFERENCES
IEC
JEDEC
JEITA
MO-203
SC-88A
EUROPEAN
PROJECTION
ISSUE DATE
00-09-01
03-02-19
Fig 7. Package outline SOT353-1 (TSSOP5)
74AHC1G09_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 18 December 2007
6 of 10
74AHC1G09
NXP Semiconductors
2-input AND gate with open-drain output
Plastic surface-mounted package; 5 leads
SOT753
D
E
B
y
A
X
HE
5
v M A
4
Q
A
A1
c
1
2
3
Lp
detail X
bp
e
w M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
c
D
E
e
HE
Lp
Q
v
w
y
mm
1.1
0.9
0.100
0.013
0.40
0.25
0.26
0.10
3.1
2.7
1.7
1.3
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT753
JEITA
SC-74A
EUROPEAN
PROJECTION
ISSUE DATE
02-04-16
06-03-16
Fig 8. Package outline SOT753 (SC-74A)
74AHC1G09_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 18 December 2007
7 of 10
74AHC1G09
NXP Semiconductors
2-input AND gate with open-drain output
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC1G09_2
20071218
Product data sheet
-
74AHC1G09_1
Modifications:
74AHC1G09_1
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Package SOT753 added to Section 3, Section 4 and Section 13.
Quick reference data section removed.
20050926
Product data sheet
-
74AHC1G09_2
Product data sheet
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 18 December 2007
8 of 10
74AHC1G09
NXP Semiconductors
2-input AND gate with open-drain output
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
74AHC1G09_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 18 December 2007
9 of 10
74AHC1G09
NXP Semiconductors
2-input AND gate with open-drain output
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional description . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 3
Dynamic characteristics . . . . . . . . . . . . . . . . . . 4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 6
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 8
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Contact information. . . . . . . . . . . . . . . . . . . . . . 9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 18 December 2007
Document identifier: 74AHC1G09_2