74ABT544 Octal latched transceiver with dual enable; inverting; 3-state Rev. 03 — 20 April 2005 Product data sheet 1. General description The 74ABT544 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT544 octal latched transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB and LEBA) and output enable (OEAB and OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64 mA. The 74ABT544 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B enable (EAB) input and the A-to-B latch enable (LEAB) input are LOW, the A-to-B path is transparent. A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-state B output buffers are active and invert the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA and OEBA inputs. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Combines 74ABT640 and 74ABT373 type functions in one device 8-bit octal transceiver with D-type latch Back-to-back registers for storage Separate controls for data flow in each direction Output capability: +64 mA and −32 mA Live insertion and extraction permitted Power-up 3-state Power-up reset Latch-up protection: ◆ JESD78: exceeds 500 mA ■ ESD protection: ◆ MIL STD 883 method 3015: exceeds 2000 V ◆ Machine model: exceeds 200 V 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state 3. Quick reference data Table 1: Quick reference data Tamb = 25 °C; GND = 0 V. Symbol Parameter Conditions Min Typ Max Unit tPLH propagation delay An to Bn or Bn to An CL = 50 pF; VCC = 5 V - 3.0 - ns tPHL propagation delay An to Bn or Bn to An CL = 50 pF; VCC = 5 V - 3.6 - ns CI input capacitance VI = 0 V or VCC - 4 - pF CI/O I/O capacitance outputs disabled; VO = 0 V or VCC - 7 - pF ICC quiescent supply current outputs 3-state; VCC = 5.5 V - 110 - µA 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description 74ABT544D −40 °C to +85 °C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 74ABT544N −40 °C to +85 °C DIP24 plastic dual in-line package; 24 leads (300 mil) SOT222-1 74ABT544DB −40 °C to +85 °C SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 74ABT544PW −40 °C to +85 °C Version 5. Functional diagram 3 4 5 6 7 8 9 2 23 1 13 11 14 10 11 A0 A1 A2 A3 A4 A5 A6 A7 EAB 23 EBA OEAB 13 14 LEAB OEBA 2 1 LEBA 3 B0 B1 B2 B3 B4 B5 B6 B7 22 21 20 19 18 17 16 15 001aac756 1EN3 (AB) G1 1C5 2EN4 (BA) G2 2C6 3 5D 5D 4 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 001aac757 Fig 1. Logic symbol Fig 2. IEC logic symbol 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 2 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state OEBA 2 13 EBA LEBA 23 11 1 14 DETAIL A D 22 Q OEAB EAB LEAB B0 LE A0 3 Q D LE 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 21 20 19 18 17 16 15 DETAIL A × 7 B1 B2 B3 B4 B5 B6 B7 001aac758 Fig 3. Logic diagram 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 3 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state 6. Pinning information 6.1 Pinning LEBA 1 24 VCC OEBA 2 23 EBA A0 3 22 B0 A1 4 21 B1 A2 5 20 B2 A3 6 19 B3 544 A4 7 18 B4 A5 8 17 B5 A6 9 16 B6 A7 10 15 B7 EAB 11 14 LEAB GND 12 13 OEAB 001aac755 Fig 4. Pin configuration 6.2 Pin description Table 3: Pin description Symbol Pin Description LEBA 1 B-to-A latch enable input (active LOW) OEBA 2 B-to-A output enable input (active LOW) A0 3 port A, 3-state output 0 A1 4 port A, 3-state output 1 A2 5 port A, 3-state output 2 A3 6 port A, 3-state output 3 A4 7 port A, 3-state output 4 A5 8 port A, 3-state output 5 A6 9 port A, 3-state output 6 A7 10 port A, 3-state output 7 EAB 11 A-to-B enable input (active LOW) GND 12 ground (0 V) OEAB 13 A-to-B output enable input (active LOW) LEAB 14 A-to-B latch enable input (active LOW) B7 15 port B, 3-state output 7 B6 16 port B, 3-state output 6 B5 17 port B, 3-state output 5 B4 18 port B, 3-state output 4 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 4 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state Table 3: Pin description …continued Symbol Pin Description B3 19 port B, 3-state output 3 B2 20 port B, 3-state output 2 B1 21 port B, 3-state output 1 B0 22 port B, 3-state output 0 EBA 23 B-to-A enable input (active LOW) VCC 24 supply voltage 7. Functional description 7.1 Function table Table 4: Function table [1] Status Disabled Disabled + latch Latch + display Transparent Hold [1] Control Input Output OExx Exx LExx An or Bn An or Bn H X X X Z X H X X Z L ↑ L h Z l Z h L l H H L L H X NC L L L L L L L H H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; ↑ = LOW-to-HIGH clock transition; NC = no change; Z = high-impedance OFF-state. 9397 750 14756 Product data sheet ↑ © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 5 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage [1] VO output voltage output in OFF-state or HIGH-state [1] Min Max Unit −0.5 +7.0 V −1.2 +7.0 V −0.5 +5.5 V IIK input diode current VI < 0 V - −18 mA IOK output diode current VO < 0 V - −50 mA IO output current output in LOW-state - 128 mA - 150 °C −65 +150 °C Tj junction temperature Tstg storage temperature [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9. Recommended operating conditions Table 6: Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Typ Max Unit VCC supply voltage 4.5 - 5.5 V VI input voltage 0 - VCC V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level Input voltage - - 0.8 V IOH HIGH-level output current - - −32 mA IOL LOW-level output current - - 64 mA ∆t/∆V input transition rise or fall rate 0 - 10 ns/V Tamb ambient temperature −40 - +85 °C in free air 9397 750 14756 Product data sheet Min © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 6 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit - −0.9 −1.2 V IOH = −3 mA 2.5 3.2 - V IOH = −32 mA 2.0 2.3 - V 3.0 3.7 - V - 0.42 0.55 V - 0.13 0.55 V control pins - ±0.01 ±1.0 µA data pins - ±5 ±100 µA - ±5.0 ±100 µA - ±5.0 ±50 µA - 5.0 50 µA Tamb = 25 °C VIK input diode voltage VCC = 4.5 V; IIK = −18 mA VOH HIGH-level output voltage VCC = 4.5 V; VI = VIL or VIH VCC = 5.0 V; VI = VIL or VIH IOH = −3 mA VOL LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VRST restart LOW-level output voltage VCC = 5.5 V; IO = 1 mA; VI = GND or VCC ILI input leakage current IOFF power-down leakage current [1] VCC = 5.5 V; VI = GND or 5.5 V VCC = 0 V; VI or VO ≤ 4.5 V IPU, IPD power-up or power-down 3-state VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; output current VOExx = don’t care IOZ 3-state output current [2] VCC = 5.5 V; VI = VIL or VIH output HIGH-state at VO = 2.7 V - −5.0 −50 µA - 5.0 50 µA −50 −65 −180 mA outputs HIGH-state - 110 250 µA outputs LOW-state - 20 30 mA - 110 250 µA - 0.3 1.5 mA output LOW-state at VO = 0.5 V ICEX output HIGH-state leakage current VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC IO output current VCC = 5.5 V; VO = 2.5 V ICC quiescent supply current VCC = 5.5 V; VI = GND or VCC [3] outputs 3-state ∆ICC additional supply current per input pin VCC = 5.5 V; one input at 3.4 V and other inputs at VCC or GND; VCC = 5.5 V CI input capacitance VI = 0 V or VCC - 4 - pF CI/O I/O capacitance outputs disabled; VO = 0 V or VCC - 7 - pF - - −1.2 V IOH = −3 mA 2.5 - - V IOH = −32 mA 2.0 - - V 3.0 - - V - - 0.55 V - - 0.55 V [4] Tamb = −40 °C to +85 °C VIK input diode voltage VCC = 4.5 V; IIK = −18 mA VOH HIGH-level output voltage VCC = 4.5 V; VI = VIL or VIH VCC = 5.0 V; VI = VIL or VIH IOH = −3 mA VOL VRST LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH restart LOW-level output voltage VCC = 5.5 V; IO = 1 mA; VI = GND or VCC 9397 750 14756 Product data sheet [1] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 7 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions ILI VCC = 5.5 V; VI = GND or 5.5 V input leakage current Min Typ Max Unit - - ±1.0 µA - - ±100 µA - - ±100 µA - - ±50 µA output HIGH-state at VO = 2.7 V - - 50 µA output LOW-state at VO = 0.5 V - - −50 µA - - 50 µA −50 - −180 mA outputs HIGH-state - - 250 µA outputs LOW-state - - 30 mA outputs 3-state - - 250 µA - - 1.5 mA control pins data pins VCC = 0 V; VI or VO ≤ 4.5 V IOFF power-down leakage current IPU, IPD power-up or power-down 3-state VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; output current VOExx = don’t care IOZ 3-state output current VCC = 5.5 V; VI = VIL or VIH ICEX output HIGH-state leakage current VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC IO output current VCC = 5.5 V; VO = 2.5 V ICC quiescent supply current VCC = 5.5 V; VI = GND or VCC ∆ICC additional supply current per input pin [2] VCC = 5.5 V; one input at 3.4 V and other inputs at VCC or GND; VCC = 5.5 V [3] [4] [1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. [2] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 % a transition time of up to 100 µs is permitted. [3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [4] This is the increase in supply current for each input at 3.4 V. 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; for test circuit see Figure 10. Symbol Parameter Conditions Min Typ Max Unit An to Bn, Bn to An see Figure 5 1.7 3.0 3.8 ns LEBA to An, LEAB to Bn see Figure 5 and 6 2.1 3.5 4.2 ns An to Bn, Bn to An see Figure 5 2.4 3.6 4.5 ns LEBA to An, LEAB to Bn see Figure 5 and 6 3.0 4.4 5.3 ns OEBA to An, OEAB to Bn see Figure 7 1.8 3.0 3.9 ns EBA to An, EAB to Bn see Figure 7 1.9 3.4 4.1 ns OEBA to An, OEAB to Bn see Figure 8 2.9 4.2 5.2 ns EBA to An, EAB to Bn see Figure 8 3.1 4.6 5.5 ns Tamb = 25 °C; VCC = 5.0 V tPLH tPHL tPZH tPZL propagation delay propagation delay output enable time to HIGH-level output enable time to LOW-level 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 8 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state Table 8: Dynamic characteristics …continued GND = 0 V; for test circuit see Figure 10. Symbol Parameter tPHZ output disable time from HIGH-level tPLZ tsu(H) tsu(L) th(H) th(L) twL Conditions Min Typ Max Unit OEBA to An, OEAB to Bn see Figure 7 2.0 3.3 4.3 ns EBA to An, EAB to Bn see Figure 7 2.1 3.4 4.5 ns OEBA to An, OEAB to Bn see Figure 8 2.0 2.8 5.8 ns EBA to An, EAB to Bn see Figure 8 2.0 3.0 6.2 ns An to LEAB, Bn to LEBA see Figure 9 3.0 1.5 - ns An to EAB, Bn to EBA see Figure 9 3.0 1.5 - ns An to LEAB, Bn to LEBA see Figure 9 3.0 0.6 - ns An to EAB, Bn to EBA see Figure 9 3.0 0.6 - ns An to LEAB, Bn to LEBA see Figure 9 0.5 −0.3 - ns An to EAB, Bn to EBA see Figure 9 0.5 −0.2 - ns An to LEAB, Bn to LEBA see Figure 9 0.5 −1.3 - ns An to EAB, Bn to EBA see Figure 9 0.5 −1.3 - ns see Figure 9 3.5 1.8 - ns An to Bn, Bn to An see Figure 5 1.7 - 4.7 ns LEBA to An, LEAB to Bn see Figure 5 and 6 2.1 - 5.2 ns An to Bn, Bn to An see Figure 5 2.4 - 5.2 ns LEBA to An, LEAB to Bn see Figure 5 and 6 3.0 - 6.2 ns OEBA to An, OEAB to Bn see Figure 7 1.8 - 4.7 ns EBA to An, EAB to Bn see Figure 7 1.9 - 5.0 ns OEBA to An, OEAB to Bn see Figure 8 2.9 - 6.1 ns EBA to An, EAB to Bn see Figure 8 3.1 - 6.5 ns OEBA to An, OEAB to Bn see Figure 7 2.0 - 4.9 ns EBA to An, EAB to Bn see Figure 7 2.1 - 5.2 ns OEBA to An, OEAB to Bn see Figure 8 2.0 - 6.3 ns EBA to An, EAB to Bn see Figure 8 2.0 - 6.7 ns output disable time from LOW-level set-up time HIGH set-up time LOW hold time HIGH hold time LOW pulse width LOW LEAB and LEBA Tamb = −40 °C to +85 °C; VCC = 5.0 V ± 0.5 V tPLH tPHL tPZH tPZL tPHZ tPLZ propagation delay propagation delay output enable time to HIGH-level output enable time to LOW-level output disable time from HIGH-level output disable time from LOW-level 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 9 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state Table 8: Dynamic characteristics …continued GND = 0 V; for test circuit see Figure 10. Symbol Parameter tsu(H) set-up time HIGH tsu(L) th(H) th(L) twL Conditions Min Typ Max Unit An to LEAB, Bn to LEBA see Figure 9 3.0 - - ns An to EAB, Bn to EBA see Figure 9 3.0 - - ns An to LEAB, Bn to LEBA see Figure 9 3.0 - - ns An to EAB, Bn to EBA see Figure 9 3.0 - - ns An to LEAB, Bn to LEBA see Figure 9 0.5 - - ns An to EAB, Bn to EBA see Figure 9 0.5 - - ns An to LEAB, Bn to LEBA see Figure 9 0.5 - - ns An to EAB, Bn to EBA see Figure 9 0.5 - - ns see Figure 9 3.5 - - ns set-up time LOW hold time HIGH hold time LOW pulse width LOW LEAB and LEBA 12. Waveforms VI An, Bn, LEBA, LEAB input VM VM GND t PHL t PLH VOH An, Bn output VM VM VOL 001aac759 VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 5. Propagation delay for inverting output VI LEBA, LEAB input VM VM GND t PLH t PHL VOH An, Bn output VM VM VOL 001aac761 VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay for non-inverting output 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 10 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state VI OEAB, OEBA, EAB, EBA input GND VM VM t PZH t PHZ VOH An, Bn output VOH − 0.3 V VM VOL 001aac760 VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. 3-state output enable time to HIGH-level and output disable time from HIGH-level VI OEAB, OEBA, EAB, EBA input GND VM VM t PZL t PLZ VOH An, Bn output VM VOL + 0.3 V VOL 001aac762 VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 8. 3-state output enable time to LOW-level and output disable time from LOW-level VOH LEAB, LEBA input VM VM VOL t wL VI An, Bn input VM VM VM VM GND t su(H) t h(H) t su(L) t h(L) 001aac763 VM = 1.5 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times and latch enable pulse width 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 11 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state 13. Test information tW VI 90 % negative pulse 90 % VM 10 % 0V VI 10 % t THL (t f) t TLH (t r) t TLH (t r) t THL (t f) 90 % positive pulse 0V VM 90 % VM VM 10 % 10 % tW 001aac765 VM = 1.5 V. a. Input pulse definition VEXT VCC PULSE GENERATOR VI RL VO DUT CL RT RL 001aac764 Test data is given in Table 9. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. b. Test circuit for 3-state outputs Fig 10. Load circuitry for switching times Table 9: Test data Input Load VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 Ω open 7.0 V open 9397 750 14756 Product data sheet VEXT © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 12 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state 14. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT137-1 (SO24) 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 13 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1 ME D seating plane A2 L A A1 c e Z w M b1 (e 1) MH b 13 24 pin 1 index E 1 12 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.38 3.94 1.63 1.14 0.56 0.43 0.36 0.25 31.9 31.5 6.73 6.25 2.54 7.62 3.51 3.05 8.13 7.62 10.03 7.62 0.25 2.05 inches 0.185 0.015 0.155 0.064 0.045 0.022 0.017 0.014 0.010 1.256 1.240 0.265 0.246 0.1 0.3 0.138 0.120 0.32 0.30 0.395 0.300 0.01 0.081 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT222-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-03-12 MS-001 Fig 12. Package outline SOT222-1 (DIP24) 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 14 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 13. Package outline SOT340-1 (SSOP24) 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 15 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 14. Package outline SOT355-1 (TSSOP24) 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 16 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state 15. Revision history Table 10: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74ABT544_3 20050420 Product data sheet - 9397 750 14756 74ABT544_2 Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • • Section 2; changed latch-up protection to JESD78. Table 1; changed typical values for propagation delay. Table 8; changed values for propagation delay, output enable time and output disable time. 74ABT544_2 20021118 Product specification - 9397 750 10752 74ABT544 74ABT544 19930701 Product specification - - - 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 17 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state 16. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. Definitions 18. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 14756 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 20 April 2005 18 of 19 74ABT544 Philips Semiconductors Octal latched transceiver with dual enable; inverting; 3-state 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information . . . . . . . . . . . . . . . . . . . . 18 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 20 April 2005 Document number: 9397 750 14756 Published in The Netherlands