PHILIPS LPC4310FET100

LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet;
two High-speed USBs; advanced configurable peripherals
Rev. 2.1 — 23 September 2011
Objective data sheet
1. General description
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embedded
applications which include an ARM Cortex-M0 coprocessor, up to 264 kB of SRAM,
advanced configurable peripherals such as the State Configurable Timer (SCT) and the
Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet,
LCD, an external memory controller, and multiple digital and analog peripherals. The
LPC4350/30/20/10 operate at CPU frequencies of up to 180 MHz.
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements
such as low power consumption, enhanced debug features, and a high level of support
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a
Harvard architecture with separate local instruction and data buses as well as a third bus
for peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core.
The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which
is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor,
designed as a replacement for existing 8/16-bit microcontrollers, offers up to 180 MHz
performance with a simple instruction set and reduced code size.
Remark: This data sheet describes the Rev ‘A’ versions of parts LPC4350/30/20/10.
Compared to previous versions, the following updates apply:
•
•
•
•
•
Operating frequency increased to 180 MHz.
C_CAN1 added.
Pin multiplexing increased to up to 9 levels.
GPIO block updated.
Pads updated.
2. Features and benefits
 Cortex-M4 Processor core
 ARM Cortex-M4 processor, running at frequencies of up to 180 MHz.
 ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
 Hardware floating-point unit.
 Non-maskable Interrupt (NMI) input.
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller





LPC4350_30_20_10
Objective data sheet
 JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch
points.
 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
 System tick timer.
Cortex-M0 Processor core
 ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4
application processor.
 Running at frequencies of up to 180 MHz.
 JTAG, Serial Wire Debug, and built-in NVIC.
On-chip memory
 Up to 264 kB SRAM for code and data use.
 Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
 64 kB ROM containing boot code and on-chip software drivers.
 128 bit general-purpose One-Time Programmable (OTP) memory.
Configurable digital peripherals
 Serial GPIO (SGPIO) interface.
 State Configurable Timer (SCT) subsystem on AHB.
 Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCT, and ADC0/1.
Serial interfaces
 Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB per second.
 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
 One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
 One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
 USB interface electrical test software included in ROM USB stack.
 One 550 UART with DMA support and full modem interface.
 Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
 Two C_CAN 2.0B controllers with one channel each.
 Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
 One SPI controller.
 One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1 Mbit/s.
 One standard I2C-bus interface with monitor mode and with standard I/O pins.
 Two I2S interfaces, each with DMA support and with one input and one output.
Digital peripherals
 External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
2 of 145
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32-bit ARM Cortex-M4/M0 microcontroller
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LPC4350_30_20_10
Objective data sheet
 LCD controller with DMA support and a programmable display resolution of up to
1024H  768V. Supports monochrome and color STN panels and TFT color panels;
supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel
mapping.
 Secure Digital Input Output (SD/MMC) card interface.
 Eight-channel General-Purpose DMA (GPDMA) controller can access all memories
on the AHB and all DMA-capable AHB slaves.
 Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors and open-drain mode.
 GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
 Up to eight GPIO pins can be selected from all GPIO pins as edge and level
sensitive interrupt sources.
 Two GPIO group interrupt modules enable an interrupt based on a programmable
pattern of input states of a group of GPIO pins.
 Four general-purpose timer/counters with capture and match capabilities.
 One motor control Pulse Width Modulator (PWM) for three-phase motor control.
 One Quadrature Encoder Interface (QEI).
 Repetitive Interrupt timer (RI timer).
 Windowed watchdog timer (WWDT).
 Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
 Alarm timer; can be battery powered.
Analog peripherals
 One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
 Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
ADC inputs are shared between the two ADCs.
Security
 AES engine programmable through an on-chip API.
 Two 128-bit secure OTP memories for AES key storage and customer use.
 Unique ID for each device.
Clock generation unit
 Crystal oscillator with an operating range of 1 MHz to 25 MHz.
 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature and
voltage.
 Ultra-low power Real-Time Clock (RTC) crystal oscillator.
 Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
 Clock output.
Power
 Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for the
core supply and the RTC power domain.
 RTC power domain can be powered separately by a 3 V battery supply.
 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
 Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.
 Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
 Brownout detect with four separate thresholds for interrupt and forced reset.
 Power-On Reset (POR).
 Available as 256-pin, 180-pin, and 100-pin LBGA package and as 208-pin, 144-pin.
and 100-pin LQFP packages.
3. Applications




LPC4350_30_20_10
Objective data sheet
Motor control
Power management
White goods
RFID readers
 Embedded audio applications
 Industrial automation
 e-metering
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
4 of 145
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32-bit ARM Cortex-M4/M0 microcontroller
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC4350FET256
LBGA256
Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm
SOT740-2
LPC4350FET180
TFBGA180 Thin fine-pitch ball grid array package; 180 balls
SOT570-3
LPC4350FBD208 LQFP208
Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm
SOT459-1
LPC4330FET256
LBGA256
Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm
SOT740-2
LPC4330FET180
TFBGA180 Thin fine-pitch ball grid array package; 180 balls
LPC4330FET100
TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm
LPC4330FBD144 LQFP144
SOT570-3
Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm
TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm
LPC4320FET100
SOT926-1
SOT486-1
SOT926-1
LPC4320FBD144 LQFP144
Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm
SOT486-1
LPC4320FBD100 LQFP100
Plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm
SOT407-1
TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm
LPC4310FET100
LPC4310FBD144 LQFP144
Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm
SOT926-1
SOT486-1
4.1 Ordering options
Table 2.
Ordering options
Type number
Total
SRAM
LCD Ethernet
USB0
(Host,
Device,
OTG)
USB1
ADC
PWM
(Host,
channels
Device)/
ULPI
interface
QEI
GPIO
Package
LPC4350FET256
264 kB
yes
yes
yes/yes
8
yes
yes
164
LBGA256
LPC4350FET180
yes
264 kB
yes
yes
yes
yes/yes
8
yes
yes
118
TFBGA180
LPC4350FBD208 264 kB
yes
yes
yes
yes/yes
8
yes
yes
142
LQFP208
LPC4330FET256
264 kB
no
yes
yes
yes/yes
8
yes
yes
164
LBGA256
LPC4330FET180
264 kB
no
yes
yes
yes/yes
8
yes
yes
118
TFBGA180
LPC4330FET100
264 kB
no
yes
yes
yes/no
4
no
no
49
TFBGA100
LPC4330FBD144 264 kB
no
yes
yes
yes/no
8
yes
no
83
LQFP144
LPC4320FET100
200 kB
no
no
yes
no
4
no
no
49
TFBGA100
LPC4320FBD144 200 kB
no
no
yes
no
8
yes
no
83
LQFP144
LPC4320FBD100 168 kB
no
no
yes
no
5
no
no
49
LQFP100
LPC4310FET100
168 kB
no
no
no
no
4
no
no
49
TFBGA100
LPC4310FBD144 168 kB
no
no
no
no
8
yes
no
83
LQFP144
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
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32-bit ARM Cortex-M4/M0 microcontroller
5. Block diagram
LPC4350/30/20/10
TEST/DEBUG
INTERFACE
TEST/DEBUG
INTERFACE
ARM
CORTEX-M0
HIGH-SPEED PHY
ARM
CORTEX-M4
system bus
D-code bus
I-code bus
GPDMA
ETHERNET(1)
10/100
MAC
IEEE 1588
HIGH-SPEED
USB0(1)
HOST/
DEVICE/OTG
HIGH-SPEED
USB1(1)
HOST/DEVICE
LCD(1)
SD/
MMC
masters
slaves
AHB MULTILAYER MATRIX
slaves
BRIDGE 0
BRIDGE 1
BRIDGE 2
BRIDGE 3
BRIDGE
BRIDGE
128 kB LOCAL SRAM
72 kB LOCAL SRAM
64 kB ROM
I2C1
RI TIMER
USART0
MOTOR
CONTROL
PWM(1)
USART2
10-bit DAC
CCU1
BACKUP REGISTERS
UART1
I2C0
USART3
C_CAN0
CCU2
POWER MODE CONTROL
SSP0
I2S0
TIMER2
10-bit ADC0
RGU
TIMER0
I2S1
CONFIGURATION
REGISTERS
TIMER3
10-bit ADC1
TIMER1
C_CAN1
WWDT
SCU
GPIO
INTERRUPTS
CGU
ALARM TIMER
32 kB AHB SRAM
16 +16 kB AHB SRAM
EVENT ROUTER
SSP1
OTP MEMORY
QEI(1)
RTC
RTC OSC
GIMA
12 MHz IRC
GPIO GROUP0
INTERRUPT
SCT
EMC
HS GPIO
AES
SPI
SGPIO
SPIFI
RTC POWER DOMAIN
GPIO GROUP1
INTERRUPT
= connected to GPDMA
002aaf772
(1) Not available on all parts (see Table 2).
Fig 1.
LPC4350/30/20/10 Block diagram
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
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32-bit ARM Cortex-M4/M0 microcontroller
6. Pinning information
6.1 Pinning
LPC4350/30FET256
ball A1
index area
2
1
4
3
6
5
8
7
10
9
12
11
14
13
LPC4350/30FET180
ball A1
index area
16
2
1
15
A
4
3
6
5
8
7
10
9
12
11
A
B
B
C
C
D
D
E
E
F
G
F
J
H
L
K
G
H
K
J
M
L
N
M
P
N
R
P
T
002aag374
002aaf813
Transparent top view
Transparent top view
Fig 2.
14
13
Pin configuration LBGA256 package
Fig 3.
ball A1
index area
Pin configuration TFBGA180 package
LPC4330/20/10FET100
1
2
3
4
5
6
7
8
9 10
A
B
C
D
E
F
G
H
J
K
002aag375
Transparent top view
Fig 4.
LPC4350_30_20_10
Objective data sheet
Pin configuration TFBGA100 package
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156
LPC4350FBD208
73
002aag376
Fig 6.
002aag377
Pin configuration LQFP144 package
100
Pin configuration LQFP208 package
72
36
37
53
Fig 5.
108
LPC4330/20/10FBD144
105
104
52
109
1
76
1
144
157
208
32-bit ARM Cortex-M4/M0 microcontroller
1
75
LPC4320FBD100
Fig 7.
50
51
26
25
002aag381
Pin configuration LQFP100 package
6.2 Pin description
On the LPC4350/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA
to PF, with up to 20 pins used per port. Each digital pin may support up to eight different
digital functions, including General Purpose I/O (GPIO), selectable through the System
Configuration Unit (SCU) registers. Note that the pin name is not indicative of the GPIO
port assigned to it.
Not all functions listed in Table 3 are available on all packages. See Table 2 for availability
of USB0, USB1, Ethernet, and LCD functions.
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
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LPC4350/30/20/10
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32-bit ARM Cortex-M4/M0 microcontroller
LQFP100[1]
32
22
Type
LQFP144
47
Description
[2]
LQFP208[1]
G2
Reset state
TFBGA100
LBGA256
Symbol
TFBGA180[1]
Table 3.
Pin description
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Multiplexed digital pins
P0_0
P0_1
L3
M2
x
x
G1
50
34
23
[3]
[3]
I; PU I/O
GPIO0[0] — General purpose digital input/output pin.
I/O
SSP1_MISO — Master In Slave Out for SSP1.
I
ENET_RXD1 — Ethernet receive data 1 (RMII/MII
interface).
I/O
SGPIO0 — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
I2S0_TX_WS — Transmit Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
I/O
I2S1_TX_WS — Transmit Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
I; PU I/O
GPIO0[1] — General purpose digital input/output pin.
I/O
SSP1_MOSI — Master Out Slave in for SSP1.
I
ENET_COL — Ethernet Collision detect (MII
interface).
I/O
SGPIO1 — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).
I/O
P1_0
P2
LPC4350_30_20_10
Objective data sheet
x
H1
54
38
25
[3]
I; PU I/O
I2S1_TX_SDA — I2S1 transmit data. It is driven by
the transmitter and read by the receiver. Corresponds
to the signal SD in the I2S-bus specification.
GPIO0[4] — General purpose digital input/output pin.
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
I/O
EMC_A5 — External memory address line 5.
-
R — Function reserved.
-
R — Function reserved.
I/O
SSP0_SSEL — Slave Select for SSP0.
I/O
SGPIO7 — General purpose digital input/output pin.
-
R — Function reserved.
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32-bit ARM Cortex-M4/M0 microcontroller
LQFP208[1]
LQFP144
LQFP100[1]
x
K2
58
42
28
[3]
Type
TFBGA100
R2
Description
[2]
TFBGA180[1]
P1_1
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
I/O
EMC_A6 — External memory address line 6.
I/O
SGPIO8 — General purpose digital input/output pin.
-
R — Function reserved.
I/O
SSP0_MISO — Master In Slave Out for SSP0.
-
R — Function reserved.
P1_2
P1_3
P1_4
R3
P5
T3
LPC4350_30_20_10
Objective data sheet
x
x
x
K1
J1
J2
60
61
64
43
44
47
29
30
32
[3]
[3]
[3]
GPIO0[8] — General purpose digital input/output pin.
Boot pin (see Table 5).
I; PU I/O
R — Function reserved.
GPIO0[9] — General purpose digital input/output pin.
Boot pin (see Table 5).
O
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
I/O
EMC_A7 — External memory address line 7.
I/O
SGPIO9 — General purpose digital input/output pin.
-
R — Function reserved.
I/O
SSP0_MOSI — Master Out Slave in for SSP0.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO0[10] — General purpose digital input/output
pin.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
I/O
SGPIO10 — General purpose digital input/output pin.
O
EMC_OE — LOW active Output Enable signal.
O
USB0_IND1 — USB0 port indicator LED control
output 1.
I/O
SSP1_MISO — Master In Slave Out for SSP1.
-
R — Function reserved.
O
SD_RST — SD/MMC reset signal for MMC4.4 card.
I; PU I/O
GPIO0[11] — General purpose digital input/output
pin.
O
CTOUT_9 — SCT output 9. Match output 1 of timer 2.
I/O
SGPIO11 — General purpose digital input/output pin.
O
EMC_BLS0 — LOW active Byte Lane select signal 0.
O
USB0_IND0 — USB0 port indicator LED control
output 0.
I/O
SSP1_MOSI — Master Out Slave in for SSP1.
-
R — Function reserved.
O
SD_VOLT1 — SD/MMC bus voltage select output 1.
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32-bit ARM Cortex-M4/M0 microcontroller
P1_6
P1_7
LQFP208[1]
LQFP144
LQFP100[1]
x
J4
65
48
33
T4
T5
LPC4350_30_20_10
Objective data sheet
x
x
K4
G4
67
69
49
50
34
35
[3]
[3]
[3]
Type
TFBGA100
R5
Description
[2]
TFBGA180[1]
P1_5
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO1[8] — General purpose digital input/output pin.
O
CTOUT_10 — SCT output 10. Match output 2 of
timer 2.
-
R — Function reserved.
O
EMC_CS0 — LOW active Chip Select 0 signal.
O
USB0_PWR_FAULT — Port power fault signal
indicating overcurrent condition; this signal monitors
over-current on the USB bus (external circuitry
required to detect over-current condition).
I/O
SSP1_SSEL — Slave Select for SSP1.
I/O
SGPIO15 — General purpose digital input/output pin.
O
SD_POW — <tbd>.
I; PU I/O
GPIO1[9] — General purpose digital input/output pin.
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
-
R — Function reserved.
O
EMC_WE — LOW active Write Enable signal.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO14 — General purpose digital input/output pin.
I/O
SD_CMD — SD/MMC command signal.
I; PU I/O
GPIO1[0] — General purpose digital input/output pin.
I
U1_DSR — Data Set Ready input for UART1.
O
CTOUT_13 — SCT output 13. Match output 1 of
timer 3.
I/O
EMC_D0 — External memory data line 0.
O
USB0_PWR_EN — VBUS drive signal (towards
external charge pump or power management unit);
indicates that Vbus must be driven (active high).
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
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Rev. 2.1 — 23 September 2011
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32-bit ARM Cortex-M4/M0 microcontroller
P1_9
P1_10
P1_11
LQFP208[1]
LQFP144
LQFP100[1]
x
H5
71
51
36
T7
R8
T9
LPC4350_30_20_10
Objective data sheet
x
x
x
J5
H6
J7
73
75
77
52
53
55
37
38
39
[3]
[3]
[3]
[3]
Type
TFBGA100
R7
Description
[2]
TFBGA180[1]
P1_8
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO1[1] — General purpose digital input/output pin.
O
U1_DTR — Data Terminal Ready output for UART1.
O
CTOUT_12 — SCT output 12. Match output 0 of
timer 3.
I/O
EMC_D1 — External memory data line 1.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
SD_VOLT0 — SD/MMC bus voltage select output 0.
I; PU I/O
GPIO1[2] — General purpose digital input/output pin.
O
U1_RTS — Request to Send output for UART1.
O
CTOUT_11 — SCT output 11. Match output 3 of
timer 2.
I/O
EMC_D2 — External memory data line 2.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
SD_DAT0 — SD/MMC data bus line 0.
I; PU I/O
GPIO1[3] — General purpose digital input/output pin.
I
U1_RI — Ring Indicator input for UART1.
O
CTOUT_14 — SCT output 14. Match output 2 of
timer 3.
I/O
EMC_D3 — External memory data line 3.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
SD_DAT1 — SD/MMC data bus line 1.
I; PU I/O
GPIO1[4] — General purpose digital input/output pin.
I
U1_CTS — Clear to Send input for UART1.
O
CTOUT_15 — SCT output 15. Match output 3 of timer
3.
I/O
EMC_D4 — External memory data line 4.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
SD_DAT2 — SD/MMC data bus line 2.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
12 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P1_13
P1_14
P1_15
LQFP208[1]
LQFP144
LQFP100[1]
x
K7
78
56
40
R10
R11
T12
LPC4350_30_20_10
Objective data sheet
x
x
x
H8
J8
K8
83
85
87
60
61
62
41
42
43
[3]
[3]
[3]
[3]
Type
TFBGA100
R9
Description
[2]
TFBGA180[1]
P1_12
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO1[5] — General purpose digital input/output pin.
I
U1_DCD — Data Carrier Detect input for UART1.
-
R — Function reserved.
I/O
EMC_D5 — External memory data line 5.
I
T0_CAP1 — Capture input 1 of timer 0.
-
R — Function reserved.
I/O
SGPIO8 — General purpose digital input/output pin.
I/O
SD_DAT3 — SD/MMC data bus line 3.
I; PU I/O
GPIO1[6] — General purpose digital input/output pin.
O
U1_TXD — Transmitter output for UART1.
-
R — Function reserved.
I/O
EMC_D6 — External memory data line 6.
I
T0_CAP0 — Capture input 0 of timer 0.
-
R — Function reserved.
I/O
SGPIO9 — General purpose digital input/output pin.
I
SD_CD — SD/MMC card detect input.
I; PU I/O
GPIO1[7] — General purpose digital input/output pin.
I
U1_RXD — Receiver input for UART1.
-
R — Function reserved.
I/O
EMC_D7 — External memory data line 7.
O
T0_MAT2 — Match output 2 of timer 0.
-
R — Function reserved.
I/O
SGPIO10 — General purpose digital input/output pin.
-
R — Function reserved.
I; PU I/O
GPIO0[2] — General purpose digital input/output pin.
O
U2_TXD — Transmitter output for USART2.
I/O
SGPIO2 — General purpose digital input/output pin.
I
ENET_RXD0 — Ethernet receive data 0 (RMII/MII
interface).
O
T0_MAT1 — Match output 1 of timer 0.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
13 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P1_17
P1_18
LQFP208[1]
LQFP144
LQFP100[1]
x
H9
90
64
44
M8
N12
LPC4350_30_20_10
Objective data sheet
x
x
H10 93
J10
95
66
67
45
46
[3]
[4]
[3]
Type
TFBGA100
M7
Description
[2]
TFBGA180[1]
P1_16
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO0[3] — General purpose digital input/output pin.
I
U2_RXD — Receiver input for USART2.
I/O
SGPIO3 — General purpose digital input/output pin.
I
ENET_CRS — Ethernet Carrier Sense (MII
interface).
O
T0_MAT0 — Match output 0 of timer 0.
-
R — Function reserved.
-
R — Function reserved.
I
ENET_RX_DV — Ethernet Receive Data Valid
(RMII/MII interface).
I; PU I/O
GPIO0[12] — General purpose digital input/output
pin.
I/O
U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.
-
R — Function reserved.
I/O
ENET_MDIO — Ethernet MIIM data input and output.
I
T0_CAP3 — Capture input 3 of timer 0.
O
CAN1_TD — CAN1 transmitter output.
I/O
SGPIO11 — General purpose digital input/output pin.
-
R — Function reserved.
I; PU I/O
GPIO0[13] — General purpose digital input/output
pin.
I/O
U2_DIR — RS-485/EIA-485 output enable/direction
control for USART2.
-
R — Function reserved.
O
ENET_TXD0 — Ethernet transmit data 0 (RMII/MII
interface).
O
T0_MAT3 — Match output 3 of timer 0.
I
CAN1_RD — CAN1 receiver input.
I/O
SGPIO12 — General purpose digital input/output pin.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
14 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P1_20
P2_0
LQFP208[1]
LQFP144
LQFP100[1]
x
K9
96
68
47
M10
T16
LPC4350_30_20_10
Objective data sheet
x
x
K10 100 70
G10 108 75
48
50
[3]
[3]
[3]
Type
TFBGA100
M11
Description
[2]
TFBGA180[1]
P1_19
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I
ENET_TX_CLK (ENET_REF_CLK) — Ethernet
Transmit Clock (MII interface) or Ethernet Reference
Clock (RMII interface).
I/O
SSP1_SCK — Serial clock for SSP1.
-
R — Function reserved.
-
R — Function reserved.
O
CLKOUT — Clock output pin.
-
R — Function reserved.
O
I2S0_RX_MCLK — I2S receive master clock.
I/O
I2S1_TX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
I; PU I/O
GPIO0[15] — General purpose digital input/output
pin.
I/O
SSP1_SSEL — Slave Select for SSP1.
-
R — Function reserved.
O
ENET_TXD1 — Ethernet transmit data 1 (RMII/MII
interface).
I
T0_CAP2 — Capture input 2 of timer 0.
-
R — Function reserved.
I/O
SGPIO13 — General purpose digital input/output pin.
-
R — Function reserved.
I; PU I/O
SGPIO4 — General purpose digital input/output pin.
O
U0_TXD — Transmitter output for USART0.
I/O
EMC_A13 — External memory address line 13.
O
USB0_PWR_EN — VBUS drive signal (towards
external charge pump or power management unit);
indicates that Vbus must be driven (active high).
I/O
GPIO5[0] — General purpose digital input/output pin.
-
R — Function reserved.
I
T3_CAP0 — Capture input 0 of timer 3.
O
ENET_MDC — Ethernet MIIM clock.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
15 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P2_2
P2_3
LQFP208[1]
LQFP144
LQFP100[1]
x
G7
116 81
54
M15
J12
LPC4350_30_20_10
Objective data sheet
x
x
F5
D8
121 84
127 87
56
57
[3]
[3]
[4]
Type
TFBGA100
N15
Description
[2]
TFBGA180[1]
P2_1
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
SGPIO5 — General purpose digital input/output pin.
I
U0_RXD — Receiver input for USART0.
I/O
EMC_A12 — External memory address line 12.
O
USB0_PWR_FAULT — Port power fault signal
indicating overcurrent condition; this signal monitors
over-current on the USB bus (external circuitry
required to detect over-current condition).
I/O
GPIO5[1] — General purpose digital input/output pin.
-
R — Function reserved.
I
T3_CAP1 — Capture input 1 of timer 3.
-
R — Function reserved.
I; PU I/O
SGPIO6 — General purpose digital input/output pin.
I/O
U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I/O
EMC_A11 — External memory address line 11.
O
USB0_IND1 — USB0 port indicator LED control
output 1.
I/O
GPIO5[2] — General purpose digital input/output pin.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
I
T3_CAP2 — Capture input 2 of timer 3.
-
R — Function reserved.
I; PU I/O
SGPIO12 — General purpose digital input/output pin.
I/O
I2C1_SDA — I2C1 data input/output (this pin does
not use a specialized I2C pad).
O
U3_TXD — Transmitter output for USART3.
I
CTIN_1 — SCT input 1. Capture input 1 of timer 0.
Capture input 1 of timer 2.
I/O
GPIO5[3] — General purpose digital input/output pin.
-
R — Function reserved.
O
T3_MAT0 — Match output 0 of timer 3.
O
USB0_PWR_EN — VBUS drive signal (towards
external charge pump or power management unit);
indicates that Vbus must be driven (active HIGH).
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
16 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P2_5
LQFP208[1]
LQFP144
LQFP100[1]
x
D9
128 88
58
K14
x
D10 131 91
61
[4]
[4]
Type
TFBGA100
K11
Description
[2]
TFBGA180[1]
P2_4
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
SGPIO13 — General purpose digital input/output pin.
I/O
I2C1_SCL — I2C1 clock input/output (this pin does
not use a specialized I2C pad).
I
U3_RXD — Receiver input for USART3.
I
CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1,
2, 3.
I/O
GPIO5[4] — General purpose digital input/output pin.
-
R — Function reserved.
O
T3_MAT1 — Match output 1 of timer 3.
O
USB0_PWR_FAULT — Port power fault signal
indicating overcurrent condition; this signal monitors
over-current on the USB bus (external circuitry
required to detect over-current condition).
I; PU I/O
SGPIO14 — General purpose digital input/output pin.
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
I
USB1_VBUS — Monitors the presence of USB1 bus
power.
Note: This signal must be HIGH for USB reset to
occur.
P2_6
K16
LPC4350_30_20_10
Objective data sheet
x
G9
137 95
64
[3]
I
ADCTRIG1 — ADC trigger input 1.
I/O
GPIO5[5] — General purpose digital input/output pin.
-
R — Function reserved.
O
T3_MAT2 — Match output 2 of timer 3.
O
USB0_IND0 — USB0 port indicator LED control
output 0.
I; PU I/O
SGPIO7 — General purpose digital input/output pin.
I/O
U0_DIR — RS-485/EIA-485 output enable/direction
control for USART0.
I/O
EMC_A10 — External memory address line 10.
O
USB0_IND0 — USB0 port indicator LED control
output 0.
I/O
GPIO5[6] — General purpose digital input/output pin.
I
CTIN_7 — SCT input 7.
I
T3_CAP3 — Capture input 3 of timer 3.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
17 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P2_8
LQFP100[1]
C10 138 96
65
J16
x
C6
140 98
67
[3]
[3]
Type
LQFP144
x
Description
[2]
TFBGA100
H14
LQFP208[1]
TFBGA180[1]
P2_7
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
O
CTOUT_1 — SCT output 1. Match output 1 of timer 0.
I/O
U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.
I/O
EMC_A9 — External memory address line 9.
-
R — Function reserved.
-
R — Function reserved.
O
T3_MAT3 — Match output 3 of timer 3.
-
R — Function reserved.
I; PU I/O
P2_10
H16
G16
LPC4350_30_20_10
Objective data sheet
x
x
B10 144 102 70
E8
146 104 71
[3]
[3]
SGPIO15 — General purpose digital input/output pin.
Boot pin (see Table 5).
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
I/O
U3_DIR — RS-485/EIA-485 output enable/direction
control for USART3.
I/O
EMC_A8 — External memory address line 8.
I/O
GPIO5[7] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
P2_9
GPIO0[7] — General purpose digital input/output pin.
If this pin is pulled LOW at reset, the part enters ISP
mode using USART0.
I; PU I/O
R — Function reserved.
GPIO1[10] — General purpose digital input/output
pin. Boot pin (see Table 5).
O
CTOUT_3 — SCT output 3. Match output 3 of timer 0.
I/O
U3_BAUD — <tbd> for USART3.
I/O
EMC_A0 — External memory address line 0.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO0[14] — General purpose digital input/output
pin.
O
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
O
U2_TXD — Transmitter output for USART2.
I/O
EMC_A1 — External memory address line 1.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
18 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P2_12
P2_13
148 105 72
E15
C16
LPC4350_30_20_10
Objective data sheet
x
x
B9
153 106 73
A10 156 108 75
[3]
[3]
[3]
Type
A9
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
F16
LQFP144
TFBGA180[1]
P2_11
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO1[11] — General purpose digital input/output
pin.
O
CTOUT_5 — SCT output 5. Match output 1 of timer 1.
I
U2_RXD — Receiver input for USART2.
I/O
EMC_A2 — External memory address line 2.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO1[12] — General purpose digital input/output
pin.
O
CTOUT_4 — SCT output 4. Match output 0 of timer 1.
-
R — Function reserved.
I/O
EMC_A3 — External memory address line 3.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.
I; PU I/O
GPIO1[13] — General purpose digital input/output
pin.
I
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
-
R — Function reserved.
I/O
EMC_A4 — External memory address line 4.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
U2_DIR — RS-485/EIA-485 output enable/direction
control for USART2.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
19 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P3_1
161 112
G11
x
F7
163 114
78
79
[3]
[3]
Type
A8
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
F13
LQFP144
TFBGA180[1]
P3_0
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
O
I2S0_RX_MCLK — I2S receive master clock.
I/O
I2S0_TX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
O
I2S0_TX_MCLK — I2S transmit master clock.
I/O
SSP0_SCK — Serial clock for SSP0.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
I2S0_TX_WS — Transmit Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
I/O
I2S0_RX_WS — Receive Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
I
CAN0_RD — CAN receiver input.
O
USB1_IND1 — USB1 Port indicator LED control
output 1.
I/O
GPIO5[8] — General purpose digital input/output pin.
-
R — Function reserved.
O
LCD_VD15 — LCD data.
P3_2
F11
LPC4350_30_20_10
Objective data sheet
x
G6
166 116
80
[3]
I2S0_RX_SCK — I2S transmit clock. It is driven by
the master and received by the slave. Corresponds to
the signal SCK in the I2S-bus specification.
R — Function reserved.
I; PU I/O
I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to
the signal SD in the I2S-bus specification.
I/O
I2S0_RX_SDA — I2S Receive data. It is driven by
the transmitter and read by the receiver. Corresponds
to the signal SD in the I2S-bus specification.
O
CAN0_TD — CAN transmitter output.
O
USB1_IND0 — USB1 Port indicator LED control
output 0.
I/O
GPIO5[9] — General purpose digital input/output pin.
-
R — Function reserved.
O
LCD_VD14 — LCD data.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
20 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P3_4
P3_5
169 118
A15
C12
LPC4350_30_20_10
Objective data sheet
x
x
B8
B7
171 119
81
82
173 121 84
[5]
[3]
[3]
Type
A7
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
B14
LQFP144
TFBGA180[1]
P3_3
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I/O
SPI_SCK — Serial clock for SPI.
I/O
SSP0_SCK — Serial clock for SSP0.
O
SPIFI_SCK — Serial clock for SPIFI.
O
CGU_OUT1 — CGU spare clock output 1.
-
R — Function reserved.
O
I2S0_TX_MCLK — I2S transmit master clock.
I/O
I2S1_TX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
I; PU I/O
GPIO1[14] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SPIFI_SIO3 — I/O lane 3 for SPIFI.
O
U1_TXD — Transmitter output for UART 1.
I/O
I2S0_TX_WS — Transmit Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
I/O
I2S1_RX_SDA — I2S1 Receive data. It is driven by
the transmitter and read by the receiver. Corresponds
to the signal SD in the I2S-bus specification.
O
LCD_VD13 — LCD data.
I; PU I/O
GPIO1[15] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SPIFI_SIO2 — I/O lane 2 for SPIFI.
I
U1_RXD — Receiver input for UART 1.
I/O
I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to
the signal SD in the I2S-bus specification.
I/O
I2S1_RX_WS — Receive Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
O
LCD_VD12 — LCD data.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
21 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P3_7
P3_8
174 122 85
C11
C10
LPC4350_30_20_10
Objective data sheet
x
x
D7
E7
176 123 86
179 124 87
[3]
[3]
[3]
Type
C7
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
B13
LQFP144
TFBGA180[1]
P3_6
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO0[6] — General purpose digital input/output pin.
I/O
SPI_MISO — Master In Slave Out for SPI.
I/O
SSP0_SSEL — Slave Select for SSP0.
I/O
SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI
output IO1.
-
R — Function reserved.
I/O
SSP0_MISO — Master In Slave Out for SSP0.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
I/O
SPI_MOSI — Master Out Slave In for SPI.
I/O
SSP0_MISO — Master In Slave Out for SSP0.
I/O
SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI
output IO0.
I/O
GPIO5[10] — General purpose digital input/output
pin.
I/O
SSP0_MOSI — Master Out Slave in for SSP0.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
I
SPI_SSEL — Slave Select for SPI. Note that this pin
in an input pin only. The SPI in master mode cannot
drive the CS input on the slave. Any GPIO pin can be
used for SPI chip select in master mode.
I/O
SSP0_MOSI — Master Out Slave in for SSP0.
I/O
SPIFI_CS — SPIFI serial flash chip select.
I/O
GPIO5[11] — General purpose digital input/output
pin.
I/O
SSP0_SSEL — Slave Select for SSP0.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
22 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P4_1
P4_2
P4_3
LQFP208[1]
LQFP144
LQFP100[1]
x
-
1
1
-
A1
D3
C2
LPC4350_30_20_10
Objective data sheet
x
x
x
-
-
-
3
12
10
3
8
7
-
-
-
[3]
[6]
[3]
[6]
Type
TFBGA100
D5
Description
[2]
TFBGA180[1]
P4_0
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO2[0] — General purpose digital input/output pin.
O
MCOA0 — Motor control PWM channel 0, output A.
I
NMI — External interrupt input to NMI.
-
R — Function reserved.
-
R — Function reserved.
O
LCD_VD13 — LCD data.
I/O
U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.
-
R — Function reserved.
I; PU I/O
GPIO2[1] — General purpose digital input/output pin.
O
CTOUT_1 — SCT output 1. Match output 1 of timer 0.
O
LCD_VD0 — LCD data.
-
R — Function reserved.
-
R — Function reserved.
O
LCD_VD19 — LCD data.
O
U3_TXD — Transmitter output for USART3.
I
ENET_COL — Ethernet Collision detect (MII
interface).
I
ADC0_1 — ADC0, input channel 1.
I; PU I/O
GPIO2[2] — General purpose digital input/output pin.
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
O
LCD_VD3 — LCD data.
-
R — Function reserved.
-
R — Function reserved.
O
LCD_VD12 — LCD data.
I
U3_RXD — Receiver input for USART3.
I/O
SGPIO8 — General purpose digital input/output pin.
I; PU I/O
GPIO2[3] — General purpose digital input/output pin.
O
CTOUT_3 — SCT output 0. Match output 3 of timer 0.
O
LCD_VD2 — LCD data.
-
R — Function reserved.
-
R — Function reserved.
O
LCD_VD21 — LCD data.
I/O
U3_BAUD — <tbd> for USART3.
I/O
SGPIO9 — General purpose digital input/output pin.
I
ADC0_0 — ADC0, input channel 0.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
23 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P4_5
P4_6
LQFP208[1]
LQFP144
LQFP100[1]
x
-
14
9
-
D2
C1
LPC4350_30_20_10
Objective data sheet
x
x
-
-
15
17
10
11
-
-
[6]
[3]
[3]
Type
TFBGA100
B1
Description
[2]
TFBGA180[1]
P4_4
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO2[4] — General purpose digital input/output pin.
O
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
O
LCD_VD1 — LCD data.
-
R — Function reserved.
-
R — Function reserved.
O
LCD_VD20 — LCD data.
I/O
U3_DIR — RS-485/EIA-485 output enable/direction
control for USART3.
I/O
SGPIO10 — General purpose digital input/output pin.
O
DAC — DAC output.
I; PU I/O
GPIO2[5] — General purpose digital input/output pin.
O
CTOUT_5 — SCT output 5. Match output 1 of timer 1.
O
LCD_FP — Frame pulse (STN). Vertical
synchronization pulse (TFT).
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO11 — General purpose digital input/output pin.
I; PU I/O
GPIO2[6] — General purpose digital input/output pin.
O
CTOUT_4 — SCT output 4. Match output 0 of timer 1.
O
LCD_ENAB/LCDM — STN AC bias drive or TFT
data enable input.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO12 — General purpose digital input/output pin.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
24 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P4_8
P4_9
LQFP208[1]
LQFP144
LQFP100[1]
x
-
21
14
-
E2
L2
LPC4350_30_20_10
Objective data sheet
x
x
-
-
23
48
15
33
-
-
[3]
[3]
[3]
Type
TFBGA100
H4
Description
[2]
TFBGA180[1]
P4_7
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
<tbd O
>
I
LCD_DCLK — LCD panel clock.
GP_CLKIN — General purpose clock input to the
CGU.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
I2S1_TX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
I/O
I2S0_TX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
I; PU -
R — Function reserved.
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
O
LCD_VD9 — LCD data.
-
R — Function reserved.
I/O
GPIO5[12] — General purpose digital input/output
pin.
O
LCD_VD22 — LCD data.
O
CAN1_TD — CAN1 transmitter output.
I/O
SGPIO13 — General purpose digital input/output pin.
I; PU -
R — Function reserved.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
O
LCD_VD11 — LCD data.
-
R — Function reserved.
I/O
GPIO5[13] — General purpose digital input/output
pin.
O
LCD_VD15 — LCD data.
I
CAN1_RD — CAN1 receiver input.
I/O
SGPIO14 — General purpose digital input/output pin.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
25 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P5_0
P5_1
P5_2
LQFP208[1]
LQFP144
LQFP100[1]
x
-
51
35
-
N3
P3
R4
LPC4350_30_20_10
Objective data sheet
x
x
x
-
-
-
53
55
63
37
39
46
-
-
-
[3]
[3]
[3]
[3]
Type
TFBGA100
M3
Description
[2]
TFBGA180[1]
P4_10
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
O
LCD_VD10 — LCD data.
-
R — Function reserved.
I/O
GPIO5[14] — General purpose digital input/output
pin.
O
LCD_VD14 — LCD data.
-
R — Function reserved.
I/O
SGPIO15 — General purpose digital input/output pin.
I; PU I/O
GPIO2[9] — General purpose digital input/output pin.
O
MCOB2 — Motor control PWM channel 2, output B.
I/O
EMC_D12 — External memory data line 12.
-
R — Function reserved.
I
U1_DSR — Data Set Ready input for UART 1.
I
T1_CAP0 — Capture input 0 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO2[10] — General purpose digital input/output
pin.
I
MCI2 — Motor control PWM channel 2, input.
I/O
EMC_D13 — External memory data line 13.
-
R — Function reserved.
O
U1_DTR — Data Terminal Ready output for UART 1.
Can also be configured to be an RS-485/EIA-485
output enable signal for UART 1.
I
T1_CAP1 — Capture input 1 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO2[11] — General purpose digital input/output
pin.
I
MCI1 — Motor control PWM channel 1, input.
I/O
EMC_D14 — External memory data line 14.
-
R — Function reserved.
O
U1_RTS — Request to Send output for UART 1. Can
also be configured to be an RS-485/EIA-485 output
enable signal for UART 1.
I
T1_CAP2 — Capture input 2 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
26 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P5_4
P5_5
P5_6
LQFP208[1]
LQFP144
LQFP100[1]
x
-
76
54
-
P9
P10
T13
LPC4350_30_20_10
Objective data sheet
x
x
x
-
-
-
80
81
89
57
58
63
-
-
-
[3]
[3]
[3]
[3]
Type
TFBGA100
T8
Description
[2]
TFBGA180[1]
P5_3
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO2[12] — General purpose digital input/output
pin.
I
MCI0 — Motor control PWM channel 0, input.
I/O
EMC_D15 — External memory data line 15.
-
R — Function reserved.
I
U1_RI — Ring Indicator input for UART 1.
I
T1_CAP3 — Capture input 3 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO2[13] — General purpose digital input/output
pin.
O
MCOB0 — Motor control PWM channel 0, output B.
I/O
EMC_D8 — External memory data line 8.
-
R — Function reserved.
I
U1_CTS — Clear to Send input for UART 1.
O
T1_MAT0 — Match output 0 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO2[14] — General purpose digital input/output
pin.
O
MCOA1 — Motor control PWM channel 1, output A.
I/O
EMC_D9 — External memory data line 9.
-
R — Function reserved.
I
U1_DCD — Data Carrier Detect input for UART 1.
O
T1_MAT1 — Match output 1 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO2[15] — General purpose digital input/output
pin.
O
MCOB1 — Motor control PWM channel 1, output B.
I/O
EMC_D10 — External memory data line 10.
-
R — Function reserved.
O
U1_TXD — Transmitter output for UART 1.
O
T1_MAT2 — Match output 2 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
27 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P6_0
P6_1
LQFP208[1]
LQFP144
LQFP100[1]
x
-
91
65
-
M12
R15
LPC4350_30_20_10
Objective data sheet
x
x
H7
G5
105 73
107 74
-
-
[3]
[3]
[3]
Type
TFBGA100
R12
Description
[2]
TFBGA180[1]
P5_7
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO2[7] — General purpose digital input/output pin.
O
MCOA2 — Motor control PWM channel 2, output A.
I/O
EMC_D11 — External memory data line 11.
-
R — Function reserved.
I
U1_RXD — Receiver input for UART 1.
O
T1_MAT3 — Match output 3 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
I2S0_RX_MCLK — I2S receive master clock.
-
R — Function reserved.
-
R — Function reserved.
I/O
I2S0_RX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO3[0] — General purpose digital input/output pin.
O
EMC_DYCS1 — SDRAM chip select 1.
I/O
U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I/O
I2S0_RX_WS — Receive Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
-
R — Function reserved.
I
T2_CAP0 — Capture input 2 of timer 2.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
28 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P6_3
P6_4
111 78
P15
R16
LPC4350_30_20_10
Objective data sheet
x
x
-
F6
113 79
114 80
-
-
53
[3]
[3]
[3]
Type
J9
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
L13
LQFP144
TFBGA180[1]
P6_2
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO3[1] — General purpose digital input/output pin.
O
EMC_CKEOUT1 — SDRAM clock enable 1.
I/O
U0_DIR — RS-485/EIA-485 output enable/direction
control for USART0.
I/O
I2S0_RX_SDA — I2S Receive data. It is driven by
the transmitter and read by the receiver. Corresponds
to the signal SD in the I2S-bus specification.
-
R — Function reserved.
I
T2_CAP1 — Capture input 1 of timer 2.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO3[2] — General purpose digital input/output pin.
O
USB0_PWR_EN — VBUS drive signal (towards
external charge pump or power management unit);
indicates that the VBUS signal must be driven (active
HIGH).
I/O
SGPIO4 — General purpose digital input/output pin.
O
EMC_CS1 — LOW active Chip Select 1 signal.
-
R — Function reserved.
I
T2_CAP2 — Capture input 2 of timer 2.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO3[3] — General purpose digital input/output pin.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
O
U0_TXD — Transmitter output for USART0.
O
EMC_CAS — LOW active SDRAM Column Address
Strobe.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
29 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
LQFP208[1]
LQFP144
LQFP100[1]
x
F9
117 82
55
[3]
Type
TFBGA100
P16
Description
[2]
TFBGA180[1]
P6_5
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
I
U0_RXD — Receiver input for USART0.
O
EMC_RAS — LOW active SDRAM Row Address
Strobe.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
P6_6
P6_7
L14
J13
LPC4350_30_20_10
Objective data sheet
x
x
-
-
119 83
123 85
-
-
[3]
[3]
GPIO3[4] — General purpose digital input/output pin.
O
I; PU I/O
R — Function reserved.
GPIO0[5] — General purpose digital input/output pin.
O
EMC_BLS1 — LOW active Byte Lane select signal 1.
I/O
SGPIO5 — General purpose digital input/output pin.
O
USB0_PWR_FAULT — Port power fault signal
indicating overcurrent condition; this signal monitors
over-current on the USB bus (external circuitry
required to detect over-current condition).
-
R — Function reserved.
I
T2_CAP3 — Capture input 3 of timer 2.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
I/O
EMC_A15 — External memory address line 15.
I/O
SGPIO6 — General purpose digital input/output pin.
O
USB0_IND1 — USB0 port indicator LED control
output 1.
I/O
GPIO5[15] — General purpose digital input/output
pin.
O
T2_MAT0 — Match output 0 of timer 2.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
30 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P6_9
P6_10
P6_11
125 86
J15
H15
H12
LPC4350_30_20_10
Objective data sheet
x
x
x
F8
-
C9
139 97
-
66
142 100 -
143 101 69
[3]
[3]
[3]
[3]
Type
-
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
H13
LQFP144
TFBGA180[1]
P6_8
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I/O
EMC_A14 — External memory address line 14.
I/O
SGPIO7 — General purpose digital input/output pin.
O
USB0_IND0 — USB0 port indicator LED control
output 0.
I/O
GPIO5[16] — General purpose digital input/output
pin.
O
T2_MAT1 — Match output 1 of timer 2.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO3[5] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
EMC_DYCS0 — SDRAM chip select 0.
-
R — Function reserved.
O
T2_MAT2 — Match output 2 of timer 2.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO3[6] — General purpose digital input/output pin.
O
MCABORT — Motor control PWM, LOW-active fast
abort.
-
R — Function reserved.
O
EMC_DQMOUT1 — Data mask 1 used with SDRAM
and static devices.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO3[7] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
EMC_CKEOUT0 — SDRAM clock enable 0.
-
R — Function reserved.
O
T2_MAT3 — Match output 2 of timer 3.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
31 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P7_0
P7_1
145 103 -
B16
C14
LPC4350_30_20_10
Objective data sheet
x
x
-
-
158 110
162 113
-
-
[3]
[3]
[3]
Type
-
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
G15
LQFP144
TFBGA180[1]
P6_12
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO2[8] — General purpose digital input/output pin.
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
-
R — Function reserved.
O
EMC_DQMOUT0 — Data mask 0 used with SDRAM
and static devices.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO3[8] — General purpose digital input/output pin.
O
CTOUT_14 — SCT output 14. Match output 2 of
timer 3.
-
R — Function reserved.
O
LCD_LE — Line end signal.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO4 — General purpose digital input/output pin.
I; PU I/O
GPIO3[9] — General purpose digital input/output pin.
O
CTOUT_15 — SCT output 15. Match output 3 of
timer 3.
I/O
I2S0_TX_WS — Transmit Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
O
LCD_VD19 — LCD data.
O
LCD_VD7 — LCD data.
-
R — Function reserved.
O
U2_TXD — Transmitter output for USART2.
I/O
SGPIO5 — General purpose digital input/output pin.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
32 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P7_3
P7_4
165 115
C13
C8
LPC4350_30_20_10
Objective data sheet
x
x
-
-
167 117
-
-
189 132 -
[3]
[3]
[6]
Type
-
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
A16
LQFP144
TFBGA180[1]
P7_2
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO3[10] — General purpose digital input/output
pin.
I
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
I/O
I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to
the signal SD in the I2S-bus specification.
O
LCD_VD18 — LCD data.
O
LCD_VD6 — LCD data.
-
R — Function reserved.
I
U2_RXD — Receiver input for USART2.
I/O
SGPIO6 — General purpose digital input/output pin.
I; PU I/O
GPIO3[11] — General purpose digital input/output
pin.
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
-
R — Function reserved.
O
LCD_VD17 — LCD data.
O
LCD_VD5 — LCD data.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO3[12] — General purpose digital input/output
pin.
O
CTOUT_13 — SCT output 13. Match output 1 of
timer 3.
-
R — Function reserved.
O
LCD_VD16 — LCD data.
O
LCD_VD4 — LCD data.
O
TRACEDATA[0] — Trace data, bit 0.
-
R — Function reserved.
-
R — Function reserved.
I
ADC0_4 — ADC0, input channel 4.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
33 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P7_6
P7_7
191 133 -
C7
B6
LPC4350_30_20_10
Objective data sheet
x
x
-
-
194 134 -
201 140 -
[6]
[3]
[6]
Type
-
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
A7
LQFP144
TFBGA180[1]
P7_5
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO3[13] — General purpose digital input/output
pin.
O
CTOUT_12 — SCT output 12. Match output 0 of timer
3.
-
R — Function reserved.
O
LCD_VD8 — LCD data.
O
LCD_VD23 — LCD data.
O
TRACEDATA[1] — Trace data, bit 1.
-
R — Function reserved.
-
R — Function reserved.
I
ADC0_3 — ADC0, input channel 3.
I; PU I/O
GPIO3[14] — General purpose digital input/output
pin.
O
CTOUT_11 — SCT output 1. Match output 3 of timer
2.
-
R — Function reserved.
O
LCD_LP — Line synchronization pulse (STN).
Horizontal synchronization pulse (TFT).
-
R — Function reserved.
O
TRACEDATA[2] — Trace data, bit 2.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO3[15] — General purpose digital input/output
pin.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
-
R — Function reserved.
O
LCD_PWR — LCD panel power enable.
-
R — Function reserved.
O
TRACEDATA[3] — Trace data, bit 3.
O
ENET_MDC — Ethernet MIIM clock.
I/O
SGPIO7 — General purpose digital input/output pin.
I
ADC1_6 — ADC1, input channel 6.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
34 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P8_1
P8_2
P8_3
LQFP208[1]
LQFP144
LQFP100[1]
x
-
2
-
-
H5
K4
J3
LPC4350_30_20_10
Objective data sheet
x
x
x
-
-
-
34
36
37
-
-
-
-
-
-
[4]
[4]
[4]
[3]
Type
TFBGA100
E5
Description
[2]
TFBGA180[1]
P8_0
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO4[0] — General purpose digital input/output pin.
O
USB0_PWR_FAULT — Port power fault signal
indicating overcurrent condition; this signal monitors
over-current on the USB bus (external circuitry
required to detect over-current condition).
-
R — Function reserved.
I
MCI2 — Motor control PWM channel 2, input.
I/O
SGPIO8 — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
T0_MAT0 — Match output 0 of timer 0.
I; PU I/O
GPIO4[1] — General purpose digital input/output pin.
O
USB0_IND1 — USB0 port indicator LED control
output 1.
-
R — Function reserved.
I
MCI1 — Motor control PWM channel 1, input.
I/O
SGPIO9 — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
T0_MAT1 — Match output 1 of timer 0.
I; PU I/O
GPIO4[2] — General purpose digital input/output pin.
O
USB0_IND0 — USB0 port indicator LED control
output 0.
-
R — Function reserved.
I
MCI0 — Motor control PWM channel 0, input.
I/O
SGPIO10 — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
T0_MAT2 — Match output 2 of timer 0.
I; PU I/O
GPIO4[3] — General purpose digital input/output pin.
I/O
USB1_ULPI_D2 — ULPI link bidirectional data line 2.
-
R — Function reserved.
O
LCD_VD12 — LCD data.
O
LCD_VD19 — LCD data.
-
R — Function reserved.
-
R — Function reserved.
O
T0_MAT3 — Match output 3 of timer 0.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
35 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P8_5
P8_6
P8_7
LQFP208[1]
LQFP144
LQFP100[1]
x
-
39
-
-
J1
K3
K1
LPC4350_30_20_10
Objective data sheet
x
x
x
-
-
-
40
43
45
-
-
-
-
-
-
[3]
[3]
[3]
[3]
Type
TFBGA100
J2
Description
[2]
TFBGA180[1]
P8_4
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO4[4] — General purpose digital input/output pin.
I/O
USB1_ULPI_D1 — ULPI link bidirectional data line 1.
-
R — Function reserved.
O
LCD_VD7 — LCD data.
O
LCD_VD16 — LCD data.
-
R — Function reserved.
-
R — Function reserved.
I
T0_CAP0 — Capture input 0 of timer 0.
I; PU I/O
GPIO4[5] — General purpose digital input/output pin.
I/O
USB1_ULPI_D0 — ULPI link bidirectional data line 0.
-
R — Function reserved.
O
LCD_VD6 — LCD data.
O
LCD_VD8 — LCD data.
-
R — Function reserved.
-
R — Function reserved.
I
T0_CAP1 — Capture input 1 of timer 0.
I; PU I/O
GPIO4[6] — General purpose digital input/output pin.
I
USB1_ULPI_NXT — ULPI link NXT signal. Data flow
control signal from the PHY.
-
R — Function reserved.
O
LCD_VD5 — LCD data.
O
LCD_LP — Line synchronization pulse (STN).
Horizontal synchronization pulse (TFT).
-
R — Function reserved.
-
R — Function reserved.
I
T0_CAP2 — Capture input 2 of timer 0.
I; PU I/O
GPIO4[7] — General purpose digital input/output pin.
O
USB1_ULPI_STP — ULPI link STP signal. Asserted
to end or interrupt transfers to the PHY.
-
R — Function reserved.
O
LCD_VD4 — LCD data.
O
LCD_PWR — LCD panel power enable.
-
R — Function reserved.
-
R — Function reserved.
I
T0_CAP3 — Capture input 3 of timer 0.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
36 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P9_0
P9_1
LQFP208[1]
LQFP144
LQFP100[1]
x
-
49
-
-
T1
N6
LPC4350_30_20_10
Objective data sheet
x
x
-
-
59
66
-
-
-
-
[3]
[3]
[3]
Type
TFBGA100
L1
Description
[2]
TFBGA180[1]
P8_8
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I
USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz
clock generated by the PHY.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
CGU_OUT0 — CGU spare clock output 0.
O
I2S1_TX_MCLK — I2S1 transmit master clock.
I; PU I/O
GPIO4[12] — General purpose digital input/output
pin.
O
MCABORT — Motor control PWM, LOW-active fast
abort.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I
ENET_CRS — Ethernet Carrier Sense (MII
interface).
I/O
SGPIO0 — General purpose digital input/output pin.
I/O
SSP0_SSEL — Slave Select for SSP0.
I; PU I/O
GPIO4[13] — General purpose digital input/output
pin.
O
MCOA2 — Motor control PWM channel 2, output A.
-
R — Function reserved.
-
R — Function reserved.
I/O
I2S0_TX_WS — Transmit Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
I
ENET_RX_ER — Ethernet receive error (MII
interface).
I/O
SGPIO1 — General purpose digital input/output pin.
I/O
SSP0_MISO — Master In Slave Out for SSP0.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
37 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P9_3
P9_4
LQFP208[1]
LQFP144
LQFP100[1]
x
-
70
-
-
M6
N10
LPC4350_30_20_10
Objective data sheet
x
x
-
-
79
92
-
-
-
-
[3]
[3]
[3]
Type
TFBGA100
N8
Description
[2]
TFBGA180[1]
P9_2
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO4[14] — General purpose digital input/output
pin.
O
MCOB2 — Motor control PWM channel 2, output B.
-
R — Function reserved.
-
R — Function reserved.
I/O
I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to
the signal SD in the I2S-bus specification.
I
ENET_RXD3 — Ethernet receive data 3 (MII
interface).
I/O
SGPIO2 — General purpose digital input/output pin.
I/O
SSP0_MOSI — Master Out Slave in for SSP0.
I; PU I/O
GPIO4[15] — General purpose digital input/output
pin.
O
MCOA0 — Motor control PWM channel 0, output A.
O
USB1_IND1 — USB1 Port indicator LED control
output 1.
-
R — Function reserved.
-
R — Function reserved.
I
ENET_RXD2 — Ethernet receive data 2 (MII
interface).
I/O
SGPIO9 — General purpose digital input/output pin.
O
U3_TXD — Transmitter output for USART3.
I; PU -
R — Function reserved.
O
MCOB0 — Motor control PWM channel 0, output B.
O
USB1_IND0 — USB1 Port indicator LED control
output 0.
-
R — Function reserved.
I/O
GPIO5[17] — General purpose digital input/output
pin.
O
ENET_TXD2 — Ethernet transmit data 2 (MII
interface).
I/O
SGPIO4 — General purpose digital input/output pin.
I
U3_RXD — Receiver input for USART3.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
38 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
P9_6
PA_0
LQFP208[1]
LQFP144
LQFP100[1]
x
-
98
69
-
L11
L12
LPC4350_30_20_10
Objective data sheet
x
x
-
-
103 72
126 -
-
-
[3]
[3]
[3]
Type
TFBGA100
M9
Description
[2]
TFBGA180[1]
P9_5
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
O
MCOA1 — Motor control PWM channel 1, output A.
O
USB1_VBUS_EN — USB1 VBUS power enable.
-
R — Function reserved.
I/O
GPIO5[18] — General purpose digital input/output
pin.
O
ENET_TXD3 — Ethernet transmit data 3 (MII
interface).
I/O
SGPIO3 — General purpose digital input/output pin.
O
U0_TXD — Transmitter output for USART0.
I; PU I/O
GPIO4[11] — General purpose digital input/output
pin.
O
MCOB1 — Motor control PWM channel 1, output B.
O
USB1_PWR_FAULT — USB1 Port power fault signal
indicating over-current condition; this signal monitors
over-current on the USB1 bus (external circuitry
required to detect over-current condition).
-
R — Function reserved.
-
R — Function reserved.
I
ENET_COL — Ethernet Collision detect (MII
interface).
I/O
SGPIO8 — General purpose digital input/output pin.
I
U0_RXD — Receiver input for USART0.
I; PU -
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
I2S1_RX_MCLK — I2S1 receive master clock.
O
CGU_OUT1 — CGU spare clock output 1.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
39 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PA_2
PA_3
PA_4
134 -
K15
H11
G13
LPC4350_30_20_10
Objective data sheet
x
x
x
-
-
-
136 -
147 -
151 -
-
-
-
-
[4]
[4]
[4]
[3]
Type
-
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
J14
LQFP144
TFBGA180[1]
PA_1
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
GPIO4[8] — General purpose digital input/output pin.
I
QEI_IDX — Quadrature Encoder Interface INDEX
input.
-
R — Function reserved.
O
U2_TXD — Transmitter output for USART2.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO4[9] — General purpose digital input/output pin.
I
QEI_PHB — Quadrature Encoder Interface PHB
input.
-
R — Function reserved.
I
U2_RXD — Receiver input for USART2.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU I/O
GPIO4[10] — General purpose digital input/output
pin.
I
QEI_PHA — Quadrature Encoder Interface PHA
input.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
CTOUT_9 — SCT output 9. Match output 1 of timer 2.
-
R — Function reserved.
I/O
EMC_A23 — External memory address line 23.
I/O
GPIO5[19] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
40 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PB_1
PB_2
PB_3
164 -
A14
B12
A13
LPC4350_30_20_10
Objective data sheet
x
x
x
-
-
-
175 -
177 -
178 -
-
-
-
-
[3]
[3]
[3]
[3]
Type
-
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
B15
LQFP144
TFBGA180[1]
PB_0
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
O
CTOUT_10 — SCT output 10. Match output 2 of
timer 2.
O
LCD_VD23 — LCD data.
-
R — Function reserved.
I/O
GPIO5[20] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
I
USB1_ULPI_DIR — ULPI link DIR signal. Controls
the ULP data line direction.
O
LCD_VD22 — LCD data.
-
R — Function reserved.
I/O
GPIO5[21] — General purpose digital input/output
pin.
O
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D7 — ULPI link bidirectional data line 7.
O
LCD_VD21 — LCD data.
-
R — Function reserved.
I/O
GPIO5[22] — General purpose digital input/output
pin.
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D6 — ULPI link bidirectional data line 6.
O
LCD_VD20 — LCD data.
-
R — Function reserved.
I/O
GPIO5[23] — General purpose digital input/output
pin.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
41 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PB_5
PB_6
180 -
A12
A6
LPC4350_30_20_10
Objective data sheet
x
x
-
-
181 -
-
-
-
-
-
[3]
[3]
[6]
Type
-
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
B11
LQFP144
TFBGA180[1]
PB_4
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D5 — ULPI link bidirectional data line 5.
O
LCD_VD15 — LCD data.
-
R — Function reserved.
I/O
GPIO5[24] — General purpose digital input/output
pin.
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D4 — ULPI link bidirectional data line 4.
O
LCD_VD14 — LCD data.
-
R — Function reserved.
I/O
GPIO5[25] — General purpose digital input/output
pin.
I
CTIN_7 — SCT input 7.
O
LCD_PWR — LCD panel power enable.
-
R — Function reserved.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D3 — ULPI link bidirectional data line 3.
O
LCD_VD13 — LCD data.
-
R — Function reserved.
I/O
GPIO5[26] — General purpose digital input/output
pin.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
O
LCD_VD19 — LCD data.
-
R — Function reserved.
I
ADC0_6 — ADC0, input channel 6.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
42 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PC_1
PC_2
LQFP208[1]
LQFP144
LQFP100[1]
x
-
7
-
-
E4
F6
LPC4350_30_20_10
Objective data sheet
-
-
-
-
9
13
-
-
-
-
[6]
[3]
[3]
Type
TFBGA100
D4
Description
[2]
TFBGA180[1]
PC_0
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I
USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz
clock generated by the PHY.
-
R — Function reserved.
I/O
ENET_RX_CLK — Ethernet Receive Clock (MII
interface).
O
LCD_DCLK — LCD panel clock.
-
R — Function reserved.
-
R — Function reserved.
I/O
SD_CLK — SD/MMC card clock.
I
ADC1_1 — ADC1, input channel 1.
I; PU I/O
USB1_ULPI_D7 — ULPI link bidirectional data line 7.
-
R — Function reserved.
I
U1_RI — Ring Indicator input for UART 1.
O
ENET_MDC — Ethernet MIIM clock.
I/O
GPIO6[0] — General purpose digital input/output pin.
-
R — Function reserved.
I
T3_CAP0 — Capture input 0 of timer 3.
O
SD_VOLT0 — SD/MMC bus voltage select output 0.
I; PU I/O
USB1_ULPI_D6 — ULPI link bidirectional data line 6.
-
R — Function reserved.
I
U1_CTS — Clear to Send input for UART 1.
O
ENET_TXD2 — Ethernet transmit data 2 (MII
interface).
I/O
GPIO6[1] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
SD_RST — SD/MMC reset signal for MMC4.4 card.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
43 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PC_4
LQFP208[1]
LQFP144
LQFP100[1]
-
-
11
-
-
F4
-
-
16
-
-
[6]
[3]
Type
TFBGA100
F5
Description
[2]
TFBGA180[1]
PC_3
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU I/O
USB1_ULPI_D5 — ULPI link bidirectional data line 5.
-
R — Function reserved.
O
U1_RTS — Request to Send output for UART 1. Can
also be configured to be an RS-485/EIA-485 output
enable signal for UART 1.
O
ENET_TXD3 — Ethernet transmit data 3 (MII
interface).
I/O
GPIO6[2] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
SD_VOLT1 — SD/MMC bus voltage select output 1.
I
ADC1_0 — ADC1, input channel 0.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D4 — ULPI link bidirectional data line 4.
-
R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).
PC_5
PC_6
G4
H6
LPC4350_30_20_10
Objective data sheet
-
-
-
-
20
22
-
-
-
-
[3]
[3]
I/O
GPIO6[3] — General purpose digital input/output pin.
-
R — Function reserved.
I
T3_CAP1 — Capture input 1 of timer 3.
I/O
SD_DAT0 — SD/MMC data bus line 0.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D3 — ULPI link bidirectional data line 3.
-
R — Function reserved.
O
ENET_TX_ER — Ethernet Transmit Error (MII
interface).
I/O
GPIO6[4] — General purpose digital input/output pin.
-
R — Function reserved.
I
T3_CAP2 — Capture input 2 of timer 3.
I/O
SD_DAT1 — SD/MMC data bus line 1.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D2 — ULPI link bidirectional data line 2.
-
R — Function reserved.
I
ENET_RXD2 — Ethernet receive data 2 (MII
interface).
I/O
GPIO6[5] — General purpose digital input/output pin.
-
R — Function reserved.
I
T3_CAP3 — Capture input 3 of timer 3.
I/O
SD_DAT2 — SD/MMC data bus line 2.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
44 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PC_8
PC_9
PC_10
LQFP208[1]
LQFP144
LQFP100[1]
-
-
-
-
-
N4
K2
M5
LPC4350_30_20_10
Objective data sheet
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
[3]
[3]
[3]
[3]
Type
TFBGA100
G5
Description
[2]
TFBGA180[1]
PC_7
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D1 — ULPI link bidirectional data line 1.
-
R — Function reserved.
I
ENET_RXD3 — Ethernet receive data 3 (MII
interface).
I/O
GPIO6[6] — General purpose digital input/output pin.
-
R — Function reserved.
O
T3_MAT0 — Match output 0 of timer 3.
I/O
SD_DAT3 — SD/MMC data bus line 3.
I; PU -
R — Function reserved.
I/O
USB1_ULPI_D0 — ULPI link bidirectional data line 0.
-
R — Function reserved.
I
ENET_RX_DV — Ethernet Receive Data Valid
(RMII/MII interface).
I/O
GPIO6[7] — General purpose digital input/output pin.
-
R — Function reserved.
O
T3_MAT1 — Match output 1 of timer 3.
I
SD_CD — SD/MMC card detect input.
I; PU -
R — Function reserved.
I
USB1_ULPI_NXT — ULPI link NXT signal. Data flow
control signal from the PHY.
-
R — Function reserved.
I
ENET_RX_ER — Ethernet receive error (MII
interface).
I/O
GPIO6[8] — General purpose digital input/output pin.
-
R — Function reserved.
O
T3_MAT2 — Match output 2 of timer 3.
O
SD_POW — <tbd>.
I; PU -
R — Function reserved.
O
USB1_ULPI_STP — ULPI link STP signal. Asserted
to end or interrupt transfers to the PHY.
I
U1_DSR — Data Set Ready input for UART 1.
-
R — Function reserved.
I/O
GPIO6[9] — General purpose digital input/output pin.
-
R — Function reserved.
O
T3_MAT3 — Match output 3 of timer 3.
I/O
SD_CMD — SD/MMC command signal.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
45 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PC_12
PC_13
LQFP208[1]
LQFP144
LQFP100[1]
-
-
-
-
-
L6
M1
LPC4350_30_20_10
Objective data sheet
-
-
-
-
-
-
-
-
-
-
[3]
[3]
[3]
Type
TFBGA100
L5
Description
[2]
TFBGA180[1]
PC_11
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I
USB1_ULPI_DIR — ULPI link DIR signal. Controls
the ULP data line direction.
I
U1_DCD — Data Carrier Detect input for UART 1.
-
R — Function reserved.
I/O
GPIO6[10] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SD_DAT4 — SD/MMC data bus line 4.
I; PU -
R — Function reserved.
-
R — Function reserved.
O
U1_DTR — Data Terminal Ready output for UART 1.
Can also be configured to be an RS-485/EIA-485
output enable signal for UART 1.
-
R — Function reserved.
I/O
GPIO6[11] — General purpose digital input/output
pin.
I/O
SGPIO11 — General purpose digital input/output pin.
I/O
I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to
the signal SD in the I2S-bus specification.
I/O
SD_DAT5 — SD/MMC data bus line 5.
I; PU -
R — Function reserved.
-
R — Function reserved.
O
U1_TXD — Transmitter output for UART 1.
-
R — Function reserved.
I/O
GPIO6[12] — General purpose digital input/output
pin.
I/O
SGPIO12 — General purpose digital input/output pin.
I/O
I2S0_TX_WS — Transmit Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
I/O
SD_DAT6 — SD/MMC data bus line 6.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
46 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PD_0
PD_1
PD_2
LQFP208[1]
LQFP144
LQFP100[1]
-
-
-
-
-
N2
P1
R1
LPC4350_30_20_10
Objective data sheet
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
[3]
[3]
[3]
[3]
Type
TFBGA100
N1
Description
[2]
TFBGA180[1]
PC_14
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
-
R — Function reserved.
I
U1_RXD — Receiver input for UART 1.
-
R — Function reserved.
I/O
GPIO6[13] — General purpose digital input/output
pin.
I/O
SGPIO13 — General purpose digital input/output pin.
O
ENET_TX_ER — Ethernet Transmit Error (MII
interface).
I/O
SD_DAT7 — SD/MMC data bus line 7.
I; PU -
R — Function reserved.
O
CTOUT_15 — SCT output 15. Match output 3 of timer
3.
O
EMC_DQMOUT2 — Data mask 2 used with SDRAM
and static devices.
-
R — Function reserved.
I/O
GPIO6[14] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO4 — General purpose digital input/output pin.
I; PU -
R — Function reserved.
-
R — Function reserved.
O
EMC_CKEOUT2 — SDRAM clock enable 2.
-
R — Function reserved.
I/O
GPIO6[15] — General purpose digital input/output
pin.
O
SD_POW — <tbd>.
-
R — Function reserved.
I/O
SGPIO5 — General purpose digital input/output pin.
I; PU -
R — Function reserved.
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
I/O
EMC_D16 — External memory data line 16.
-
R — Function reserved.
I/O
GPIO6[16] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO6 — General purpose digital input/output pin.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
47 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PD_4
PD_5
PD_6
LQFP208[1]
LQFP144
LQFP100[1]
-
-
-
-
-
T2
P6
R6
LPC4350_30_20_10
Objective data sheet
-
-
-
-
-
-
-
-
68
-
-
-
-
-
-
[3]
[3]
[3]
[3]
Type
TFBGA100
P4
Description
[2]
TFBGA180[1]
PD_3
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
O
CTOUT_6 — SCT output 7. Match output 2 of timer 1.
I/O
EMC_D17 — External memory data line 17.
-
R — Function reserved.
I/O
GPIO6[17] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO7 — General purpose digital input/output pin.
I; PU -
R — Function reserved.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
I/O
EMC_D18 — External memory data line 18.
-
R — Function reserved.
I/O
GPIO6[18] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO8 — General purpose digital input/output pin.
I; PU -
R — Function reserved.
O
CTOUT_9 — SCT output 9. Match output 1 of timer 2.
I/O
EMC_D19 — External memory data line 19.
-
R — Function reserved.
I/O
GPIO6[19] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO9 — General purpose digital input/output pin.
I; PU -
R — Function reserved.
O
CTOUT_10 — SCT output 10. Match output 2 of
timer 2.
I/O
EMC_D20 — External memory data line 20.
-
R — Function reserved.
I/O
GPIO6[20] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO10 — General purpose digital input/output pin.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
48 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PD_8
PD_9
PD_10
LQFP208[1]
LQFP144
LQFP100[1]
-
-
72
-
-
P8
T11
P11
LPC4350_30_20_10
Objective data sheet
-
-
-
-
-
-
74
84
86
-
-
-
-
-
-
[3]
[3]
[3]
[3]
Type
TFBGA100
T6
Description
[2]
TFBGA180[1]
PD_7
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
I/O
EMC_D21 — External memory data line 21.
-
R — Function reserved.
I/O
GPIO6[21] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO11 — General purpose digital input/output pin.
I; PU -
R — Function reserved.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
I/O
EMC_D22 — External memory data line 22.
-
R — Function reserved.
I/O
GPIO6[22] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO12 — General purpose digital input/output pin.
I; PU -
R — Function reserved.
O
CTOUT_13 — SCT output 13. Match output 1 of
timer 3.
I/O
EMC_D23 — External memory data line 23.
-
R — Function reserved.
I/O
GPIO6[23] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SGPIO13 — General purpose digital input/output pin.
I; PU -
R — Function reserved.
I
CTIN_1 — SCT input 1. Capture input 1 of timer 0.
Capture input 1 of timer 2.
O
EMC_BLS3 — LOW active Byte Lane select signal 3.
-
R — Function reserved.
I/O
GPIO6[24] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
49 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PD_12
PD_13
LQFP208[1]
LQFP144
LQFP100[1]
x
-
88
-
-
N11
T14
LPC4350_30_20_10
Objective data sheet
x
x
-
-
94
97
-
-
-
-
[3]
[3]
[3]
Type
TFBGA100
N9
Description
[2]
TFBGA180[1]
PD_11
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
-
R — Function reserved.
O
EMC_CS3 — LOW active Chip Select 3 signal.
-
R — Function reserved.
I/O
GPIO6[25] — General purpose digital input/output
pin.
I/O
USB1_ULPI_D0 — ULPI link bidirectional data line 0.
O
CTOUT_14 — SCT output 14. Match output 2 of timer
3.
-
R — Function reserved.
I; PU -
R — Function reserved.
-
R — Function reserved.
O
EMC_CS2 — LOW active Chip Select 2 signal.
-
R — Function reserved.
I/O
GPIO6[26] — General purpose digital input/output
pin.
-
R — Function reserved.
O
CTOUT_10 — SCT output 10. Match output 2 of
timer 2.
-
R — Function reserved.
I; PU -
R — Function reserved.
I
CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1,
2, 3.
O
EMC_BLS2 — LOW active Byte Lane select signal 2.
-
R — Function reserved.
I/O
GPIO6[27] — General purpose digital input/output
pin.
-
R — Function reserved.
O
CTOUT_13 — SCT output 13. Match output 1 of
timer 3.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
50 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PD_15
PD_16
PE_0
LQFP208[1]
LQFP144
LQFP100[1]
x
-
99
-
-
T15
R14
P14
LPC4350_30_20_10
Objective data sheet
x
x
x
-
-
-
101 -
104 -
106 -
-
-
-
[3]
[3]
[3]
[3]
Type
TFBGA100
R13
Description
[2]
TFBGA180[1]
PD_14
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
-
R — Function reserved.
O
EMC_DYCS2 — SDRAM chip select 2.
-
R — Function reserved.
I/O
GPIO6[28] — General purpose digital input/output
pin.
-
R — Function reserved.
O
CTOUT_11 — SCT output 11. Match output 3 of
timer 2.
-
R — Function reserved.
I; PU -
R — Function reserved.
-
R — Function reserved.
I/O
EMC_A17 — External memory address line 17.
-
R — Function reserved.
I/O
GPIO6[29] — General purpose digital input/output
pin.
I
SD_WP — SD/MMC card write protect input.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
-
R — Function reserved.
I; PU -
R — Function reserved.
-
R — Function reserved.
I/O
EMC_A16 — External memory address line 16.
-
R — Function reserved.
I/O
GPIO6[30] — General purpose digital input/output
pin.
O
SD_VOLT2 — SD/MMC bus voltage select output 2.
O
CTOUT_12 — SCT output 12. Match output 0 of
timer 3.
-
R — Function reserved.
I; PU -
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
EMC_A18 — External memory address line 18.
I/O
GPIO7[0] — General purpose digital input/output pin.
O
CAN1_TD — CAN1 transmitter output.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
51 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PE_2
PE_3
PE_4
112 -
M14
K12
K13
LPC4350_30_20_10
Objective data sheet
x
x
x
-
-
-
115 -
118 -
120 -
-
-
-
-
[3]
[3]
[3]
[3]
Type
-
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
N14
LQFP144
TFBGA180[1]
PE_1
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O
EMC_A19 — External memory address line 19.
I/O
GPIO7[1] — General purpose digital input/output pin.
I
CAN1_RD — CAN1 receiver input.
-
R — Function reserved.
-
R — Function reserved.
I; PU I
ADCTRIG0 — ADC trigger input 0.
I
CAN0_RD — CAN receiver input.
-
R — Function reserved.
I/O
EMC_A20 — External memory address line 20.
I/O
GPIO7[2] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
CAN0_TD — CAN transmitter output.
I
ADCTRIG1 — ADC trigger input 1.
I/O
EMC_A21 — External memory address line 21.
I/O
GPIO7[3] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
I
NMI — External interrupt input to NMI.
-
R — Function reserved.
I/O
EMC_A22 — External memory address line 22.
I/O
GPIO7[4] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
52 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PE_6
PE_7
122 -
M16
F15
-
-
-
-
124 -
149 -
-
-
-
[3]
[3]
[3]
Type
-
Description
[2]
LQFP208[1]
-
LQFP100[1]
TFBGA100
N16
LQFP144
TFBGA180[1]
PE_5
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
CTOUT_3 — SCT output 3. Match output 3 of timer 0.
O
U1_RTS — Request to Send output for UART 1. Can
also be configured to be an RS-485/EIA-485 output
enable signal for UART 1.
I/O
EMC_D24 — External memory data line 24.
I/O
GPIO7[5] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
I
U1_RI — Ring Indicator input for UART 1.
I/O
EMC_D25 — External memory data line 25.
I/O
GPIO7[6] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
PE_8
F14
LPC4350_30_20_10
Objective data sheet
-
-
150 -
-
[3]
R — Function reserved.
O
CTOUT_5 — SCT output 5. Match output 1 of timer 1.
I
U1_CTS — Clear to Send input for UART1.
I/O
EMC_D26 — External memory data line 26.
I/O
GPIO7[7] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
CTOUT_4 — SCT output 4. Match output 0 of timer 0.
I
U1_DSR — Data Set Ready input for UART 1.
I/O
EMC_D27 — External memory data line 27.
I/O
GPIO7[8] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
53 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PE_10
PE_11
PE_12
152 -
E14
D16
D15
LPC4350_30_20_10
Objective data sheet
-
-
-
-
-
-
154 -
-
-
-
-
-
-
-
-
[3]
[3]
[3]
[3]
Type
-
Description
[2]
LQFP208[1]
-
LQFP100[1]
TFBGA100
E16
LQFP144
TFBGA180[1]
PE_9
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
I
U1_DCD — Data Carrier Detect input for UART 1.
I/O
EMC_D28 — External memory data line 28.
I/O
GPIO7[9] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
O
U1_DTR — Data Terminal Ready output for UART 1.
Can also be configured to be an RS-485/EIA-485
output enable signal for UART 1.
I/O
EMC_D29 — External memory data line 29.
I/O
GPIO7[10] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
CTOUT_12 — SCT output 12. Match output 0 of
timer 3.
O
U1_TXD — Transmitter output for UART 1.
I/O
EMC_D30 — External memory data line 30.
I/O
GPIO7[11] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
CTOUT_11 — SCT output 11. Match output 3 of
timer 2.
I
U1_RXD — Receiver input for UART 1.
I/O
EMC_D31 — External memory data line 31.
I/O
GPIO7[12] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
54 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PE_14
PE_15
LQFP208[1]
LQFP144
LQFP100[1]
-
-
-
-
-
C15
E13
LPC4350_30_20_10
Objective data sheet
-
-
-
-
-
-
-
-
-
-
[3]
[3]
[3]
Type
TFBGA100
G14
Description
[2]
TFBGA180[1]
PE_13
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
O
CTOUT_14 — SCT output 14. Match output 2 of
timer 3.
I/O
I2C1_SDA — I2C1 data input/output (this pin does
not use a specialized I2C pad).
O
EMC_DQMOUT3 — Data mask 3 used with SDRAM
and static devices.
I/O
GPIO7[13] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
EMC_DYCS3 — SDRAM chip select 3.
I/O
GPIO7[14] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
I/O
I2C1_SCL — I2C1 clock input/output (this pin does
not use a specialized I2C pad).
O
EMC_CKEOUT3 — SDRAM clock enable 3.
I/O
GPIO7[15] — General purpose digital input/output
pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
55 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PF_1
PF_2
PF_3
159 -
E11
D11
E10
LPC4350_30_20_10
Objective data sheet
-
-
-
-
-
-
-
-
168 -
170 -
-
-
-
-
[3]
[3]
[3]
[3]
I;IA
Type
-
Description
[2]
LQFP208[1]
-
LQFP100[1]
TFBGA100
D12
LQFP144
TFBGA180[1]
PF_0
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I/O
SSP0_SCK — Serial clock for SSP0.
I
GP_CLKIN — General purpose clock input to the
CGU.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
I2S1_TX_MCLK — I2S1 transmit master clock.
I; PU -
R — Function reserved.
-
R — Function reserved.
I/O
SSP0_SSEL — Slave Select for SSP0.
-
R — Function reserved.
I/O
GPIO7[16] — General purpose digital input/output
pin.
-
R — Function reserved.
I/O
SGPIO0 — General purpose digital input/output pin.
-
R — Function reserved.
I; PU -
R — Function reserved.
O
U3_TXD — Transmitter output for USART3.
I/O
SSP0_MISO — Master In Slave Out for SSP0.
-
R — Function reserved.
I/O
GPIO7[17] — General purpose digital input/output
pin.
-
R — Function reserved.
I/O
SGPIO1 — General purpose digital input/output pin.
-
R — Function reserved.
I; PU -
R — Function reserved.
I
U3_RXD — Receiver input for USART3.
I/O
SSP0_MOSI — Master Out Slave in for SSP0.
-
R — Function reserved.
I/O
GPIO7[18] — General purpose digital input/output
pin.
-
R — Function reserved.
I/O
SGPIO2 — General purpose digital input/output pin.
-
R — Function reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
56 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PF_5
PF_6
172 120 83
E9
E7
LPC4350_30_20_10
Objective data sheet
-
-
-
-
190 -
192 -
-
-
[3]
[6]
[6]
I;IA
Type
H4
Description
[2]
LQFP208[1]
x
LQFP100[1]
TFBGA100
D10
LQFP144
TFBGA180[1]
PF_4
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I/O
SSP1_SCK — Serial clock for SSP1.
I
GP_CLKIN — General purpose clock input to the
CGU.
O
TRACECLK — Trace clock.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
I2S0_TX_MCLK — I2S transmit master clock.
I/O
I2S0_RX_SCK — I2S transmit clock. It is driven by
the master and received by the slave. Corresponds to
the signal SCK in the I2S-bus specification.
I; PU -
R — Function reserved.
I/O
U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.
I/O
SSP1_SSEL — Slave Select for SSP1.
O
TRACEDATA[0] — Trace data, bit 0.
I/O
GPIO7[19] — General purpose digital input/output
pin.
-
R — Function reserved.
I/O
SGPIO4 — General purpose digital input/output pin.
-
R — Function reserved.
I
ADC1_4 — ADC1, input channel 4.
I; PU -
R — Function reserved.
I/O
U3_DIR — RS-485/EIA-485 output enable/direction
control for USART3.
I/O
SSP1_MISO — Master In Slave Out for SSP1.
O
TRACEDATA[1] — Trace data, bit 1.
I/O
GPIO7[20] — General purpose digital input/output
pin.
-
R — Function reserved.
I/O
SGPIO5 — General purpose digital input/output pin.
I/O
I2S1_TX_SDA — I2S1 transmit data. It is driven by
the transmitter and read by the receiver. Corresponds
to the signal SD in the I2S-bus specification.
I
ADC1_3 — ADC1, input channel 3.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
57 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PF_8
PF_9
193 -
E6
D6
LPC4350_30_20_10
Objective data sheet
-
-
-
-
-
-
203 -
-
-
-
[6]
[6]
[6]
Type
-
Description
[2]
LQFP208[1]
-
LQFP100[1]
TFBGA100
B7
LQFP144
TFBGA180[1]
PF_7
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
I/O
U3_BAUD — <tbd> for USART3.
I/O
SSP1_MOSI — Master Out Slave in for SSP1.
O
TRACEDATA[2] — Trace data, bit 2.
I/O
GPIO7[21] — General purpose digital input/output
pin.
-
R — Function reserved.
I/O
SGPIO6 — General purpose digital input/output pin.
I/O
I2S1_TX_WS — Transmit Word Select. It is driven by
the master and received by the slave. Corresponds to
the signal WS in the I2S-bus specification.
I/O
ADC1_7 — ADC1, input channel 7 or band gap
output.
I; PU -
R — Function reserved.
I/O
U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
O
TRACEDATA[3] — Trace data, bit 3.
I/O
GPIO7[22] — General purpose digital input/output
pin.
-
R — Function reserved.
I/O
SGPIO7 — General purpose digital input/output pin.
-
R — Function reserved.
I
ADC0_2 — ADC0, input channel 2.
I; PU -
R — Function reserved.
I/O
U0_DIR — RS-485/EIA-485 output enable/direction
control for USART0.
O
CTOUT_1 — SCT output 1. Match output 1 of timer 0.
-
R — Function reserved.
I/O
GPIO7[23] — General purpose digital input/output
pin.
-
R — Function reserved.
I/O
SGPIO3 — General purpose digital input/output pin.
-
R — Function reserved.
I
ADC1_2 — ADC1, input channel 2.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
58 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
PF_11
205 -
A2
-
-
207 -
98
100
[6]
[6]
Type
-
Description
[2]
LQFP208[1]
-
LQFP100[1]
TFBGA100
A3
LQFP144
TFBGA180[1]
PF_10
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
I; PU -
R — Function reserved.
O
U0_TXD — Transmitter output for USART0.
-
R — Function reserved.
-
R — Function reserved.
I/O
GPIO7[24] — General purpose digital input/output
pin.
-
R — Function reserved.
I
SD_WP — SD/MMC card write protect input.
-
R — Function reserved.
I
ADC0_5 — ADC0, input channel 5.
I; PU -
R — Function reserved.
I
U0_RXD — Receiver input for USART0.
-
R — Function reserved.
-
R — Function reserved.
I/O
GPIO7[25] — General purpose digital input/output
pin.
-
R — Function reserved.
O
SD_VOLT2 — SD/MMC bus voltage select output 2.
-
R — Function reserved.
I
ADC1_5 — ADC1, input channel 5.
O
EMC_CLK0 — SDRAM clock 0.
O
CLKOUT — Clock output pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SD_CLK — SD/MMC card clock.
O
EMC_CLK01 — SDRAM clock 0 and clock 1
combined.
I/O
SSP1_SCK — Serial clock for SSP1.
I
ENET_TX_CLK (ENET_REF_CLK) — Ethernet
Transmit Clock (MII interface) or Ethernet Reference
Clock (RMII interface).
Clock pins
CLK0
N5
LPC4350_30_20_10
Objective data sheet
x
K3
62
45
31
[5]
O;
PU
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
59 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
CLK2
CLK3
LQFP208[1]
LQFP144
LQFP100[1]
x
-
-
-
-
D14
P12
x
x
K6
-
141 99
-
-
68
-
[5]
[5]
[5]
O;
PU
O;
PU
O;
PU
Type
TFBGA100
T10
Description
[2]
TFBGA180[1]
CLK1
LBGA256
Symbol
Reset state
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
O
EMC_CLK1 — SDRAM clock 1.
O
CLKOUT — Clock output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
CGU_OUT0 — CGU spare clock output 0.
-
R — Function reserved.
O
I2S1_TX_MCLK — I2S1 transmit master clock.
O
EMC_CLK3 — SDRAM clock 3.
O
CLKOUT — Clock output pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SD_CLK — SD/MMC card clock.
O
EMC_CLK23 — SDRAM clock 2 and clock 3
combined.
O
I2S0_TX_MCLK — I2S transmit master clock.
I/O
I2S1_RX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
O
EMC_CLK2 — SDRAM clock 2.
O
CLKOUT — Clock output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
CGU_OUT1 — CGU spare clock output 1.
-
R — Function reserved.
I/O
I2S1_RX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
Debug pins
DBGEN
L4
x
A6
41
28
18
[3]
I; PD I
JTAG interface control signal. Also used for boundary
scan.
TCK/SWDCLK
J5
x
H2
38
27
17
[3]
I; F
Test Clock for JTAG interface (default) or Serial Wire
(SW) clock.
TRST
M4
x
B4
42
29
19
[3]
I; PU I
Test Reset for JTAG interface.
I; PU I
Test Mode Select for JTAG interface (default) or SW
debug data input/output.
O;
PU
Test Data Out for JTAG interface (default) or SW trace
output.
TMS/SWDIO
K6
x
C4
44
30
20
[3]
TDO/SWO
K5
x
H3
46
31
21
[3]
LPC4350_30_20_10
Objective data sheet
I
O
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
60 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
LQFP144
LQFP100[1]
G3
35
26
16
[3]
I; PU I
Test Data In for JTAG interface.
F2
x
E1
26
18
9
[7]
-
I/O
USB0 bidirectional D+ line.
11
[7]
-
I/O
USB0 bidirectional D line.
Type
LQFP208[1]
x
[2]
TFBGA100
J4
Reset state
TFBGA180[1]
TDI
Description
LBGA256
Symbol
USB0 pins
USB0_DP
USB0_DM
G2
x
E2
28
20
USB0_VBUS
F1
x
E3
29
21
12
[7]
-
I/O
VBUS pin (power on USB cable).
USB0_ID
H2
x
F1
30
22
13
[8]
-
I
Indicates to the transceiver whether connected to an
A-device (LOW) or a B-device (HIGH).
USB0_RREF
H1
x
F3
32
24
15
[8]
-
F12
x
E9
129 89
59
[9]
-
I/O
USB1 bidirectional D+ line.
-
I/O
USB1 bidirectional D line.
12.0 k (accuracy 1 %) on-board resistor to ground
for current reference.
USB1 pins
USB1_DP
G12
x
E10 130 90
60
[9]
I2C0_SCL
L15
x
D6
132 92
62
[10]
I; F
I/O
I2C clock input/output. Open-drain output (for I2C-bus
compliance).
I2C0_SDA
L16
x
E6
133 93
63
[10]
I; F
I/O
I2C data input/output. Open-drain output (for I2C-bus
compliance).
USB1_DM
I2C-bus
pins
Reset and wake-up pins
RESET
D9
x
B6
185 128 91
[11]
I; IA
I
External reset input: A LOW on this pin resets the
device, causing I/O ports and peripherals to take on
their default states, and processor execution to begin
at address 0.
WAKEUP0
A9
x
A4
187 130 93
[11]
I; IA
I
External wake-up input; can raise an interrupt and
can cause wake-up from any of the low power modes.
WAKEUP1
A10
x
-
-
-
-
[11]
I; IA
I
External wake-up input; can raise an interrupt and
can cause wake-up from any of the low power modes.
WAKEUP2
C9
x
-
-
-
-
[11]
I; IA
I
External wake-up input; can raise an interrupt and
can cause wake-up from any of the low power modes.
WAKEUP3
D8
x
-
-
-
-
[11]
I; IA
I
External wake-up input; can raise an interrupt and
can cause wake-up from any of the low power modes.
ADC0_0/
ADC1_0/DAC
E3
x
A2
8
6
4
[8]
I; IA
I
ADC input channel 0. Shared between 10-bit ADC0/1
and DAC.
ADC0_1/
ADC1_1
C3
x
A1
4
2
1
[8]
I; IA
I
ADC input channel 1. Shared between 10-bit ADC0/1.
ADC0_2/
ADC1_2
A4
x
B3
206 143 99
[8]
I; IA
I
ADC input channel 2. Shared between 10-bit ADC0/1.
ADC0_3/
ADC1_3
B5
x
A3
200 139 96
[8]
I; IA
I
ADC input channel 3. Shared between 10-bit ADC0/1.
ADC0_4/
ADC1_4
C6
x
-
199 138 -
[8]
I; IA
I
ADC input channel 4. Shared between 10-bit ADC0/1.
ADC pins
LPC4350_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
61 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
-
208 144 -
[8]
I; IA
I
ADC input channel 5. Shared between 10-bit ADC0/1.
ADC0_6/
ADC1_6
A5
x
-
204 142 -
[8]
I; IA
I
ADC input channel 6. Shared between 10-bit ADC0/1.
ADC0_7/
ADC1_7
C5
x
-
197 136 -
[8]
I; IA
I
ADC input channel 7. Shared between 10-bit ADC0/1.
A11
x
C3
186 129 92
[11]
-
O
RTC controlled output.
-
I
Input to the RTC 32 kHz ultra-low power oscillator
circuit.
LQFP100[1]
Type
x
[2]
LQFP208[1]
B3
Reset state
TFBGA100
ADC0_5/
ADC1_5
LQFP144
TFBGA180[1]
Description
LBGA256
Symbol
RTC
RTC_ALARM
RTCX1
A8
x
A5
182 125 88
[8]
RTCX2
B8
x
B5
183 126 89
[8]
-
O
Output from the RTC 32 kHz ultra-low power
oscillator circuit.
Crystal oscillator pins
XTAL1
D1
x
B1
18
12
5
[8]
-
I
Input to the oscillator circuit and internal clock
generator circuits.
XTAL2
E1
x
C1
19
13
6
[8]
-
O
Output from the oscillator amplifier.
Power and ground pins
USB0_VDDA
3V3_DRIVER
F3
x
D1
24
16
7
-
-
Separate analog 3.3 V power supply for driver.
USB0
_VDDA3V3
G3
x
D2
25
17
8
-
-
USB 3.3 V separate power supply voltage.
USB0_VSSA
_TERM
H3
x
D3
27
19
10
-
-
Dedicated analog ground for clean reference for
termination resistors.
USB0_VSSA
_REF
G1
x
F2
31
23
14
-
-
Dedicated clean analog ground for generation of
reference currents and voltages.
VDDA
B4
x
B2
198 137 95
-
-
Analog power supply and ADC reference voltage.
VBAT
B10
x
C5
184 127 90
-
-
RTC power supply: 3.3 V on this pin supplies power
to the RTC.
VDDREG
F10,
F9,
L8,
L7
x
E4,
E5,
F4
135
,
188
,
195
,
82,
33
94, 131,
59,
25
-
Main regulator power supply.
VPP
E8
-
-
-
-
-
OTP programming voltage.
LPC4350_30_20_10
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[12]
-
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VDDIO
D7,
x
E12,
F7,
F8,
G10,
H10,
J6,
J7,
K7,
L9,
L10,
N7,
N13
F10, 6,
K5
52,
57,
102
,
110
,
155
,
160
,
202
5,
36,
41,
71,
77,
107,
111,
141
VDD
-
-
-
-
-
3,
24,
27,
49,
52,
74,
77,
97
VSS
G9,
H7,
J10,
J11,
K8
x
-
-
-
2,
26,
51,
76
VSSIO
[12]
-
Type
Description
[2]
Reset state
LQFP100[1]
LQFP144
LQFP208[1]
TFBGA100
LBGA256
Symbol
TFBGA180[1]
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
-
I/O power supply.
Power supply for main regulator, I/O, and OTP.
[13]
-
-
Ground.
-
-
Ground.
[14]
[13]
C4,
x
D13,
G6,
G7,
G8,
H8,
H9,
J8,
J9,
K9,
K10,
M13,
P7,
P13
C8,
D4,
D5,
G8,
J3,
J6
5,
56,
109
,
157
B2
x
C2
196 135 94
-
-
Analog ground.
-
B9
-
-
-
-
-
n.c.
[1]
x = available; - = not pinned out.
VSSA
4,
40,
76,
109
[14]
Not connected
-
-
[2]
I = input, O = output, IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDD(IO)); F = floating
[3]
5 V tolerant pad with 15 ns glitch filter; provides digital I/O functions with TTL levels and hysteresis; normal drive strength.
[4]
5 V tolerant pad with 15 ns glitch filter providing digital I/O functions with TTL levels, and hysteresis; high drive strength.
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[5]
5 V tolerant pad with 15 ns glitch filter providing high-speed digital I/O functions with TTL levels and hysteresis.
[6]
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output. When configured as a ADC
input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function
and disabling the pull-up resistor through the pin’s SFSP register.
[7]
5 V tolerant transparent analog pad.
[8]
Transparent analog pad. Not 5 V tolerant.
[9]
Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide
output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.
Open-drain configuration applies to all functions on this pin.
[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.
[12] On the TFBGA100 and LQFP208 packages, VPP is internally connected to VDDIO.
[13] On the LQFP144 package, VSSIO and VSS are connected to a common ground plane.
[14] On the TFBGA100 and LQFP100/208 packages, VSS is internally connected to VSSIO.
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7. Functional description
7.1 Architectural overview
The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus. The I-code and D-code core buses allow for concurrent code and data
accesses from different slave ports.
The LPC4350/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M4
buses and other bus masters to peripherals in a flexible manner that optimizes
performance by allowing peripherals that are on different slaves ports of the matrix to be
accessed simultaneously by different bus masters.
An ARM Cortex-M0 co-processor is included in the LPC4350/30/20/10, capable of
off-loading the main ARM Cortex-M4 application processor. Most peripheral interrupts are
connected to both processors. The processors communicate with each other via an
interprocessor communication protocol.
7.2 ARM Cortex-M4 processor
The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture
with separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated in the core. The processor includes a
NVIC with up to 53 interrupts.
7.3 ARM Cortex-M0 co-processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M0 co-processor uses a
3-stage pipeline von Neumann architecture and a small but powerful instruction set
providing high-end processing hardware. The co-processor incorporates a NVIC with 32
interrupts.
7.4 Interprocessor communication
The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on
using shared SRAM as mailbox and one processor raising an interrupt on the other
processor's NVIC, for example after it has delivered a new message in the mailbox. The
receiving processor can reply by raising an interrupt on the sending processor's NVIC to
acknowledge the message.
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7.5 AHB multilayer matrix
HIGH-SPEED PHY
TEST/DEBUG
INTERFACE
TEST/DEBUG
INTERFACE
ARM
CORTEX-M4
ARM
CORTEX-M0
System
IDbus code code
bus bus
DMA
0
ETHERNET
USB0
USB1
LCD
SD/
MMC
masters
1
slaves
64 kB ROM
128 kB LOCAL SRAM
72 kB LOCAL SRAM
32 kB AHB SRAM
16 kB + 16 kB
AHB SRAM
EXTERNAL
MEMORY
CONTROLLER
AHB PERIPHERALS
REGISTER
INTERFACES
APB, RTC
DOMAIN
PERIPHERALS
AHB MULTILAYER MATRIX
= master-slave connection
Fig 8.
002aaf873
AHB multilayer matrix master and slave connections
7.6 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most
peripheral interrupts are shared between the Cortex-M0 and Cortex-M4 NVICs.
7.6.1 Features
•
•
•
•
•
LPC4350_30_20_10
Objective data sheet
Controls system exceptions and peripheral interrupts.
In the LPC4350/30/20/10, the Cortex-M4 NVIC supports up to 53 vectored interrupts.
<tbd> programmable interrupt priority levels with hardware priority level masking.
Relocatable vector table.
Non-Maskable Interrupt (NMI).
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• Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
7.7 Event router
The event router combines various internal signals, interrupts, and the external interrupt
pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up
signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down,
and Deep power-down modes. Individual events can be configured as edge or level
sensitive and can be enabled or disabled in the event router. The event router can be
battery powered.
The following events if enabled in the event router can create a wake-up signal and/or an
interrupt:
•
•
•
•
•
External pins WAKEUP0/1/2/3 and RESET
Alarm timer, RTC, WWDT, BOD interrupts
C_CAN and QEI interrupts
Ethernet, USB0, USB1 signals
Selected outputs of combined timers (SCT and timer0/1/3)
7.8 Global Input Multiplexer Array (GIMA)
The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers,
event router, or the ADCs.
7.8.1 Features
•
•
•
•
•
Single selection of a source.
Signal inversion.
Can capture a pulse if the input event source is faster than the target clock.
Synchronization of input event and target clock.
Single-cycle pulse generation for target.
7.9 System Tick timer (SysTick)
The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval.
7.10 On-chip static RAM
The LPC4350/30/20/10 support up to 200 kB local SRAM and an additional 64 kB AHB
SRAM with separate bus master access for higher throughput and individual power
control for low power operation.
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7.11 In-System Programming (ISP)
In-System programming (ISP) is programming or reprogramming the on-chip SRAM
memory, using the boot loader software and the USART0 serial port. This can be done
when the part resides in the end-user board. ISP allows to load data into on-chip SRAM
and execute code from on-chip SRAM.
7.12 Boot ROM
The internal ROM memory is used to store the boot code of the LPC4350/30/20/10. After
a reset, the ARM processor will start its code execution from this memory.
The boot ROM memory includes the following features:
• ROM memory size is 64 kB.
• Supports booting from UART interfaces and external static memory such as NOR
flash, SPI flash, quad SPI flash.
• Includes APIs for power control and OTP programming.
• Includes SPIFI drivers.
• Includes a flexible USB device stack that supports Human Interface Device (HID),
Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.
AES capable parts also support:
• CMAC authentication on the boot image.
• Secure booting from an encrypted image. In development mode booting from a plain
text image is possible. Development mode is terminated by programming the AES
key.
• API for AES programming.
Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If
the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is
determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1.
Table 4.
Boot mode when OTP BOOT_SRC bits are programmed
Boot mode BOOT_SRC BOOT_SRC BOOT_SRC
bit 3
bit 2
bit 1
BOOT_SRC Description
bit 0
Pin state
0
0
0
0
Boot source is defined by the reset state of P1_1,
P1_2, P2_8 pins, and P2_9. See Table 5.
UART
0
0
0
1
Boot from device connected to USART0 using pins
P2_0 and P2_1.
SPIFI
0
0
1
0
Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
EMC 8-bit
0
0
1
1
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
EMC 16-bit
0
1
0
0
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit
0
1
0
1
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB0
0
1
1
0
Boot from USB0.
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Table 4.
Boot mode when OTP BOOT_SRC bits are programmed
Boot mode BOOT_SRC BOOT_SRC BOOT_SRC
bit 3
bit 2
bit 1
BOOT_SRC Description
bit 0
USB1
0
1
1
1
Boot from USB1.
SPI (SSP)
1
0
0
0
Boot from SPI flash connected to the SSP0
interface on P3_3, P3_6, P3_7 and P3_8[1].
USART3
1
0
0
1
Boot from device connected to USART3 using pins
P2_3 and P2_4.
[1]
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Table 5.
Boot mode when OPT BOOT_SRC bits are zero
Boot mode
Pins
Description
P2_9
P2_8
P1_2
P1_1
UART
LOW
LOW
LOW
LOW
Boot from device connected to USART0 using pins
P2_0 and P2_1.
SPIFI
LOW
LOW
LOW
HIGH
Boot from Quad SPI flash connected to the SPIFI
interface on P3_3 to P3_8[1].
EMC 8-bit
LOW
LOW
HIGH
LOW
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
EMC 16-bit
LOW
LOW
HIGH
HIGH
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit
LOW
HIGH
LOW
LOW
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB0
LOW
HIGH
LOW
HIGH
Boot from USB0
USB1
LOW
HIGH
HIGH
LOW
Boot from USB1.
SPI (SSP)
LOW
HIGH
HIGH
HIGH
Boot from SPI flash connected to the SSP0
interface on P3_3, P3_6, P3_7 and P3_8[1].
USART3
HIGH
LOW
LOW
LOW
Boot from device connected to USART3 using pins
P2_3 and P2_4.
[1]
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
7.13 Memory mapping
The memory map shown in Figure 9 and Figure 10 is global to both the Cortex-M4 and
the Cortex-M0 processors and all SRAM is shared between both processors. Each
processor uses its own ARM private bus memory map for the NVIC and other system
functions.
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LPC4350/30/20/10
4 GB
0xFFFF FFFF
reserved
0xE010 0000
ARM private bus
reserved
SPIFI data
256 MB dynamic external memory DYCS3
256 MB dynamic external memory DYCS2
reserved
peripheral bit band alias region
reserved
0xE000 0000
0x8800 0000
0x8000 0000
0x7000 0000
0x6000 0000
0x4400 0000
0x4200 0000
0x4010 2000
SGPIO
SPI
reserved
high-speed GPIO
reserved
AES
reserved
APB peripherals #3
reserved
APB peripherals #2
reserved
0x2000 0000
0x1F00 0000
0x1E00 0000
0x1D00 0000
0x1C00 0000
16 MB static external memory CS3
APB peripherals #1
16 MB static external memory CS2
reserved
16 MB static external memory CS1
APB peripherals #0
16 MB static external memory CS0
reserved
RTC domain peripherals
0x1800 0000
0x1008 A000
0x1008 0000
0x1002 0000
0x1001 8000
0x400F 4000
0x400F 2000
0x400F 1000
0x400F 0000
0x400E 0000
0x400D 0000
0x400C 0000
0x400B 0000
0x400A 0000
0x4009 0000
0x4008 0000
0x4005 0000
0x4004 0000
0x4001 2000
AHB peripherals
1 GB
reserved
0x1009 2000
0x400F 8000
reserved
SPIFI data
256 MB dynamic external memory DYCS1
0x1041 0000
0x1040 0000
0x4010 0000
0x4006 0000
clocking/reset peripherals
reserved
0x1400 0000
0x4010 1000
64 kB ROM
128 MB dynamic external memory DYCS0
reserved
0x4000 0000
0x3000 0000
0x2800 0000
reserved
32 kB local SRAM
(LPC4350/30)
32 MB AHB SRAM bit banding
32 kB + 8 kB local SRAM
(LPC4350/30/20/10)
reserved
reserved
16 kB AHB SRAM (LPC4350/30/20/10)
32 kB local SRAM (LPC4350/30/20)
16 kB AHB SRAM (LPC4350/30)
0x2400 0000
0x2200 0000
0x2001 0000
16 kB AHB SRAM (LPC4350/30)
96 kB local SRAM
(LPC4350/30/20/10)
16 kB AHB SRAM (LPC4350/30/20/10)
0x1000 0000
local SRAM/
external static memory banks
0 GB
256 MB shadow area
0x2000 C000
0x2000 8000
0x2000 4000
0x2000 0000
0x1000 0000
0x0000 0000
002aaf774
Fig 9.
LPC4350/30/20/10 Memory mapping (overview)
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
0x400E 5000
reserved
0x400E 4000
ADC1
0x400E 3000
ADC0
0x400E 2000
C_CAN0
0x400E 1000
DAC
0x400E 0000
0x400C 8000
I2C1
0x400C 7000
0x400C 6000
QEI
timer2
0x400C 2000
USART3
0x400C 1000
USART2
0x400C 0000
0x400B 0000
RI timer
APB2
peripherals
C_CAN1
I2S1
I2S0
I2C0
AES
reserved
APB3 peripherals
reserved
APB2 peripherals
reserved
APB1 peripherals
reserved
motor control PWM
APB0 peripherals
GPIO GROUP1 interrupt
reserved
GPIO GROUP0 interrupt
GPIO interrupts
clocking/reset peripherals
SCU
0x4008 5000
timer1
0x4008 4000
timer0
0x4008 3000
SSP0
0x4008 2000
UART1 w/ modem
0x4008 1000
USART0
0x4008 0000
WWDT
RTC domain peripherals
APB0
peripherals
0x4010 1000
RGU
0x4005 3000
CCU2
0x4005 2000
CCU1
0x4005 1000
CGU
0x4005 0000
0x4010 0000
reserved
0x400F 4000
0x4004 7000
RTC
0x4004 6000
0x400F 2000
OTP controller
0x4004 5000
event router
0x4004 4000
CREG
0x4004 3000
power mode control
0x4004 2000
backup registers
0x4004 1000
alarm timer
0x4004 0000
0x400A 0000
ethernet
0x4001 2000
0x4001 0000
0x4009 0000
reserved
0x4000 9000
0x4008 0000
LCD
0x4000 8000
USB1
0x4000 7000
USB0
0x4000 6000
EMC
0x4000 5000
SD/MMC
0x4000 4000
SPIFI
0x4000 3000
DMA
0x4000 2000
reserved
0x4000 1000
SCT
0x4000 0000
0x400F 1000
0x400F 0000
RTC domain
peripherals
0x400E 0000
0x400D 0000
0x400C 0000
0x400B 0000
0x4006 0000
0x4005 0000
0x4004 0000
reserved
0x4001 2000
AHB peripherals
0x4000 0000
SRAM memories
external memory banks
AHB
peripherals
0x0000 0000
71 of 145
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002aaf775
Fig 10. LPC4350/30/20/10 Memory mapping (peripherals)
LPC4350/30/20/10
0x4008 6000
0x4010 2000
clocking
reset control
peripherals
0x400F 8000
reserved
APB1
peripherals
0x4200 0000
0x4006 0000
0x4005 4000
reserved
high-speed GPIO
reserved
0x4400 0000
reserved
32-bit ARM Cortex-M4/M0 microcontroller
Rev. 2.1 — 23 September 2011
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0x400C 3000
0x4008 A000
0x4008 9000
0x4008 8000
0x4008 7000
peripheral bit band alias region
SPI
SSP1
0x400A 0000
0x6000 0000
reserved
SGPIO
timer3
0x400A 1000
external memories and
ARM private bus
GIMA
0x400C 4000
0x400A 4000
0x400A 3000
0x400A 2000
0xFFFF FFFF
APB3
peripherals
reserved
0x400C 5000
0x400A 5000
NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
LPC4350/30/20/10
0x400F 0000
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
7.14 Security features
7.14.1 AES decryption engine
The hardware AES engine can decode data using the AES algorithm.
7.14.1.1
Features
• Decoding of external flash data connected to the quad SPI Flash Interface (SPIFI)
and other external boot sources.
• Secure storage of decryption keys.
• Support for CMAC hash calculation to authenticate encrypted data.
• Data is processed in little endian mode. This means that the first byte read from flash
is integrated into the AES codeword as least significant byte. The 16th byte read from
flash is the most significant byte of the first AES codeword.
• AES engine performance of 1 byte/clock cycle.
• Programmable through an on-chip API.
• DMA transfers supported through the GPDMA.
7.14.2 One-Time Programmable (OTP) memory
The OTP provides 128 bit of memory for general purpose use and two 128-bit non-volatile
memories to store AES keys or other custom data.
7.15 General Purpose I/O (GPIO)
The LPC4350/30/20/10 provide 8 GPIO ports with up to 31 GPIO pins each.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
All GPIO pins default to inputs with pull-up resistors enabled on reset.
7.15.1 Features
• Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
be achieved.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
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• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request (GPIO interrupts).
• Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO
group0 and group1 interrupts).
7.16 Configurable digital peripherals
7.16.1 State Configurable Timer (SCT) subsystem
The SCT allows a wide variety of timing, counting, output modulation, and input capture
operations. The inputs and outputs of the SCT are shared with the capture and match
inputs/outputs of the 32-bit general purpose counter/timers.
The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the
two-counter case, in addition to the counter value the following operational elements are
independent for each half:
• State variable
• Limit, halt, stop, and start conditions
• Values of Match/Capture registers, plus reload or capture control values
In the two-counter case, the following operational elements are global to the SCT, but the
last three can use match conditions from either counter:
•
•
•
•
•
7.16.1.1
Clock selection
Inputs
Events
Outputs
Interrupts
Features
•
•
•
•
•
•
•
•
Two 16-bit counters or one 32-bit counter.
Counter(s) clocked by bus clock or selected input.
Up counter(s) or up-down counter(s).
State variable allows sequencing across multiple counter cycles.
Event combines input or output condition and/or counter match in a specified state.
Events control outputs and interrupts.
Selected event(s) can limit, halt, start, or stop a counter.
Supports:
– 8 inputs (one input connected internally)
– 16 outputs
– 16 match/capture registers
– 16 events
– 32 states
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7.16.2 Serial GPIO (SGPIO)
The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate
serial stream processing.
7.16.2.1
Features
• Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to
serial data conversion.
• 16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value
from a pin or an output value to a pin with every cycle of a shift clock.
•
•
•
•
Each slice is double-buffered.
Interrupt is generated on a full FIFO, shift clock, or pattern match.
Slices can be concatenated to increase buffer size.
Each slice has a 32-bit pattern match filter.
7.17 AHB peripherals
7.17.1 General Purpose DMA (GPDMA)
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral for
master 1, but only memory for master 0.
7.17.1.1
Features
• Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
• Two AHB bus masters for transferring data. These interfaces transfer data when a
DMA request goes active. Master 1 can access memories and peripherals, master 0
can access memories only.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
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• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.17.2 SPI Flash Interface (SPIFI)
The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM
Cortex-M4 processor with little performance penalty compared to parallel flash devices
with higher pin count.
After a few commands configure the interface at startup, the entire flash content is
accessible as normal memory using byte, halfword, and word accesses by the processor
and/or DMA channels. Erasure and programming are handled by simple sequences of
commands.
Many serial flash devices use a half-duplex command-driven SPI protocol for device setup
and initialization and then move to a half-duplex, command-driven 4-bit protocol for
normal operation. Different serial flash vendors and devices accept or require different
commands and command formats. SPIFI provides sufficient flexibility to be compatible
with common flash devices and includes extensions to help insure compatibility with future
devices.
7.17.2.1
Features
•
•
•
•
•
Interfaces to serial flash memory in the main memory map.
Supports classic and 4-bit bidirectional serial protocols.
Half-duplex protocol compatible with various vendors and devices.
Data rates of up to 40 MB per second.
Supports DMA access.
7.17.3 SD/MMC card interface
The SD/MMC card interface supports the following modes to control:
•
•
•
•
Secure Digital memory (SD version 3.0)
Secure Digital I/O (SDIO version 2.0)
Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)
MultiMedia Cards (MMC version 4.4)
7.17.4 External Memory Controller (EMC)
The LPC4350/30/20/10 EMC is a Memory Controller peripheral offering support for
asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be
used as an interface with off-chip memory-mapped devices and peripherals.
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7.17.4.1
Features
• Dynamic memory interface support including single data rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
•
•
•
•
•
Low transaction latency.
Read and write buffers to reduce latency and to improve performance.
8/16/32 data and 24 address lines wide static memory support.
16 bit and 32 bit wide chip select SDRAM memory support.
Static memory features include:
– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK signals to
SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, 16, or 32 data bits per device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
7.17.5 High-speed USB Host/Device/OTG interface (USB0)
Remark: The USB0 controller is available on parts LPC4350/30/20. See Table 2.
The USB OTG module allows the LPC4350/30/20/10 to connect directly to a USB Host
such as a PC (in device mode) or to a USB Device in host mode.
7.17.5.1
Features
•
•
•
•
•
•
•
Complies with Universal Serial Bus specification 2.0.
Complies with USB On-The-Go supplement.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals.
Supports all full-speed USB-compliant peripherals.
Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
• Contains UTMI+ compliant transceiver (PHY).
• Supports interrupts.
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• This module has its own, integrated DMA engine.
• USB interface electrical test software included in ROM USB stack.
7.17.6 High-speed USB Host/Device interface with ULPI (USB1)
Remark: The USB1 controller is available on parts LPC4350/30. See Table 2.
The USB1 interface can operate as a full-speed USB Host/Device interface or can
connect to an external ULPI PHY for High-speed operation.
7.17.6.1
Features
•
•
•
•
Complies with Universal Serial Bus specification 2.0.
•
•
•
•
Supports all full-speed USB-compliant peripherals.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals if connected to external ULPI
PHY.
Supports interrupts.
This module has its own, integrated DMA engine.
USB interface electrical test software included in ROM USB stack.
7.17.7 LCD controller
Remark: The LCD controller is available on the LPC4350 parts. See Table 2.
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024  768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
7.17.7.1
Features
•
•
•
•
AHB master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320  200, 320  240,
640  200, 640  240, 640  480, 800  600, and 1024  768.
• Hardware cursor support for single-panel displays.
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•
•
•
•
•
•
•
•
•
•
•
15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized for color STN and TFT.
24 bpp true-color non-palettized for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM.
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.
LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
7.17.8 Ethernet
Remark: The Ethernet peripheral is available on parts LPC4350/30. See Table 2.
7.17.8.1
Features
•
•
•
•
•
•
10/100 Mbit/s
TCP/IP hardware checksum
IP checksum
DMA support
Power management remote wake-up frame and magic packet detection
Supports both full-duplex and half-duplex operation
– Supports CSMA/CD Protocol for half-duplex operation.
– Supports IEEE 802.3x flow control for full-duplex operation.
– Optional forwarding of received pause control frames to the user application in
full-duplex operation.
– Back-pressure support for half-duplex operation.
– Automatic transmission of zero-quanta pause frame on deassertion of flow control
input in full-duplex operation.
• Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE
1588-2008 v2).
7.18 Digital serial peripherals
7.18.1 UART1
The LPC4350/30/20/10 contain one UART with standard transmit and receive data lines,
UART1 also provides a full modem control handshake interface and support for
RS-485/9-bit mode allowing both software address detection and automatic address
detection using 9-bit mode.
UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd
can be achieved with any crystal frequency above 2 MHz.
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7.18.1.1
Features
•
•
•
•
•
Maximum UART data bit rate of <tbd> MBit/s.
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
• Equipped with standard modem interface signals. This module also provides full
support for hardware flow control.
• Support for RS-485/9-bit/EIA-485 mode (UART1).
• DMA support.
7.18.2 USART0/2/3
The LPC4350/30/20/10 contain three USARTs. In addition to standard transmit and
receive data lines, the USARTs support a synchronous mode.
The USARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.18.2.1
Features
•
•
•
•
•
Maximum UART data bit rate of <tbd> MBit/s.
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
•
•
•
•
•
Support for RS-485/9-bit/EIA-485 mode.
USART3 includes an IrDA mode to support infrared communication.
All USARTs have DMA support.
Support for synchronous mode.
Smart card mode conforming to ISO7816 specification
7.18.3 SPI serial I/O controller
The LPC4350/30/20/10 contain one SPI controller. SPI is a full duplex serial interface
designed to handle multiple masters and slaves connected to a given bus. Only a single
master and a single slave can communicate on the interface during a given data transfer.
During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and
the slave always sends 8 bits to 16 bits of data to the master.
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7.18.3.1
Features
•
•
•
•
•
•
Maximum SPI data bit rate <tbd>
Compliant with SPI specification
Synchronous, serial, full duplex communication
Combined SPI master and slave
Maximum data bit rate of one eighth of the input clock rate
8 bits to 16 bits per transfer
7.18.4 SSP serial I/O controller
Remark: The LPC4350/30/20/10 contain two SSP controllers.
The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SSP supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.18.4.1
Features
• Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
•
•
•
•
•
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
7.18.5 I2C-bus interface
Remark: The LPC4350/30/20/10 each contain two I2C-bus interfaces.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.18.5.1
Features
• I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
• I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
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• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• All I2C-bus controllers support multiple address recognition and a bus monitor mode.
7.18.6 I2S interface
Remark: The LPC4350/30/20/10 each contain two I2S-bus interfaces.
The I2S-bus provides a standard communication interface for digital audio applications.
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S-bus connection has one master, which is
always the master, and one slave. The I2S-bus interface provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
7.18.6.1
Features
• Both I2S interfaces have separate input/output channels, each of which can operate in
master or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,
96, 192) kHz.
• Support for an audio master clock.
• Configurable word select period in master mode (separately for I2S-bus input and
output).
• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests for each I2S interface, controlled by programmable buffer levels.
These are connected to the GPDMA block.
• Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus
output.
7.18.7 C_CAN
Remark: The LPC4350/30/20/10 each contain two C_CAN controllers.
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of reliability.
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7.18.7.1
Features
•
•
•
•
•
•
•
Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
• Provides programmable loop-back mode for self-test operation.
7.19 Counter/timers and motor control
7.19.1 General purpose 32-bit timers/external event counters
The LPC4350/30/20/10 include four 32-bit timer/counters. The timer/counter is designed
to count cycles of the system derived clock or an externally-supplied clock. It can
optionally generate interrupts, generate timed DMA requests, or perform other actions at
specified timer values, based on four match registers. Each timer/counter also includes
two capture inputs to trap the timer value when an input signal transitions, optionally
generating an interrupt.
7.19.1.1
Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
7.19.2 Motor control PWM
The motor control PWM is a specialized PWM supporting 3-phase motors and other
combinations. Feedback inputs are provided to automatically sense rotor position and use
that information to ramp speed up or down. An abort input is also provided that causes the
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PWM to immediately release all motor drive outputs. At the same time, the motor control
PWM is highly configurable for other generalized timing, counting, capture, and compare
applications.
7.19.3 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
7.19.3.1
Features
•
•
•
•
•
•
•
•
•
•
Tracks encoder position.
Increments/decrements depending on direction.
Programmable for 2 or 4 position counting.
Velocity capture using built-in timer.
Velocity compare function with “less than” interrupt.
Uses 32-bit registers for position and velocity.
Three position compare registers with interrupts.
Index counter for revolution counting.
Index compare register with interrupts.
Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clk and direction).
7.19.4 Repetitive Interrupt (RI) timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare can be masked such that they do not contribute to the match detection.
The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
7.19.4.1
Features
• 32-bit counter. Counter can be free-running or be reset by a generated interrupt.
• 32-bit compare value.
• 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
7.19.5 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
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7.19.5.1
Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•
•
•
•
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in
multiples of Tcy(WDCLK)  4.
7.20 Analog peripherals
7.20.1 Analog-to-Digital Converter (ADC0/1)
7.20.1.1
Features
•
•
•
•
•
•
•
10-bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to VDDA.
Sampling frequency up to 400 kSamples/s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer
outputs 8 or 15, or the PWM output MCOA2.
• Individual result registers for each A/D channel to reduce interrupt overhead.
• DMA support.
7.20.2 Digital-to-Analog Converter (DAC)
7.20.2.1
Features
•
•
•
•
•
•
LPC4350_30_20_10
Objective data sheet
10-bit resolution
Integral Non-Linearity (INL) <tbd>
Differential Non-Linearity (DNL) <tbd>
Monotonic by design (resistor string architecture)
Controllable conversion speed
Low power consumption
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7.21 Peripherals in the RTC power domain
7.21.1 RTC
The Real Time Clock (RTC) is a set of counters for measuring time when system power is
on, and optionally when it is off. It uses very little power when its registers are not being
accessed by the CPU, especially reduced power modes. The RTC is clocked by a
separate 32 kHz oscillator that produces a 1 Hz internal time reference. The RTC is
powered by its own power supply pin, VBAT.
7.21.1.1
Features
• Measures the passage of time to maintain a calendar and clock. Provides seconds,
minutes, hours, day of month, month, year, day of week, and day of year.
• Ultra-low power design to support battery powered systems. Less than <tbd> required
for battery operation. Uses power from the CPU power supply when it is present.
•
•
•
•
•
Dedicated battery power supply pin.
RTC power supply is isolated from the rest of the chip.
Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution.
Periodic interrupts can be generated from increments of any field of the time registers.
Alarm interrupt can be generated for a specific date/time.
7.21.2 Alarm timer
The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating
alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00
and asserts an interrupt if enabled.
The alarm timer is part of the RTC power domain and can be battery powered.
7.22 System control
7.22.1 Configuration registers (CREG)
The following settings are controlled in the configuration register block:
•
•
•
•
•
•
•
BOD trip settings
Oscillator output
DMA-to-peripheral muxing
Ethernet mode
Memory mapping
Timer/USART inputs
Enabling the USB controllers
In addition, the CREG block contains the part identification and part configuration
information.
7.22.2 System Control Unit (SCU)
The system control unit determines the function and electrical mode of the digital pins and
allows switching between analog and digital modes of pads that are capable of both
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modes. By default function 0 is selected for all pins with pull-up enabled.
Analog I/Os like one set of the ADC and the DAC pins as well as most USB functions
reside on separate pins and are not controlled through the SCU.
7.22.3 Clock Generation Unit (CGU)
The Clock Generator Unit (CGU) generates several base clocks. The CGU outputs are
unrelated in frequency and phase and can have different clock sources within the CGU.
One CGU output is routed to the CLKOUT pins.
Within each clock area there may be multiple branch clocks, which offers very flexible
control for power-management purposes. All branch clocks are outputs of one of two
Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase.
7.22.4 Internal RC oscillator (IRC)
The IRC is used as the clock source for the WWDT and/or as the clock that drives the
PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
Upon power-up or any chip reset, the LPC4350/30/20/10 use the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.22.5 PLL0USB (for USB0)
PLL0 is a dedicated PLL for the USB0 High-speed controller.
PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz
to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.
7.22.6 PLL0AUDIO (for audio)
The audio PLL PLL0AUDIO is a general purpose PLL with a very small step size. This
PLL accepts an input clock frequency derived from an external oscillator or internal IRC.
The input frequency is multiplied up to a high frequency with a Current Controlled
Oscillator (CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the
desired output frequency. The output frequency can be set as a multiple of the sampling
frequency fs to 32fs, 64fs, 128  fs, 256  fs, 384  fs and the sampling frequency fs
can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz.
7.22.7 System PLL1
The PLL1 accepts an input clock frequency from an external oscillator in the range of
10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO
operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop
to keep the CCO within its frequency range while the PLL is providing the desired output
frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output
clock. Since the minimum output divider value is 2, it is insured that the PLL output has a
50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be
enabled by software. The program must configure and activate the PLL, wait for the PLL
to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s.
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7.22.8 Reset Generation Unit (RGU)
The RGU allows generation of independent reset signals for individual blocks and
peripherals on the LPC4350/30/20/10.
7.22.9 Power control
The LPC4350/30/20/10 feature several independent power domains to control power to
the core and the peripherals (see Figure 11). The RTC and its associated peripherals (the
alarm timer, the CREG block, the OTP controller, the back-up registers, and the event
router) are located in the RTC power-domain which can be powered by a battery supply or
the main regulator. A power selector switch ensures that the RTC block is always powered
on.
LPC43xx
VDDIO
to I/O pads
to cores
VSS
REGULATOR
to memories,
peripherals,
oscillators,
PLLs
VDDREG
MAIN POWER DOMAIN
VBAT
POWER
SELECTOR
ULTRA LOW-POWER
REGULATOR
to RTC
domain
peripherals
RESET/WAKE-UP
CONTROL
to RTC I/O
pads
RESET
WAKEUP0/1/2/3
BACKUP REGISTERS
RTCX1
RTCX2
32 kHz
OSCILLATOR
REAL-TIME CLOCK
ALARM
ALWAYS-ON/RTC POWER DOMAIN
DAC
VDDA
VSSA
ADC
ADC POWER DOMAIN
OTP
VPP
OTP POWER DOMAIN
USB0_VDDA3V_DRIVER
USB0_VDDA3V3
USB0
USB0 POWER DOMAIN
002aag378
Fig 11. Power domains
The LPC4350/30/20/10 support four reduced power modes: Sleep, Deep-sleep,
Power-down, and Deep power-down.
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The LPC4350/30/20/10 can wake up from Deep-sleep, Power-down, and Deep
power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery
powered blocks in the RTC power domain.
7.23 Serial Wire Debug/JTAG
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four
watch points.
The ARM Cortex-M0 coprocessor supports JTAG boundary scan and serial wire debug.
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8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
on pin VDD_REG
2.2[2]
3.6
V
VDD(REG)(3V3)
regulator supply voltage (3.3 V)
VDD(IO)
input/output supply voltage
on pin VDDIO
2.2
3.6
V
VDDA(3V3)
analog supply voltage (3.3 V)
on pin VDDA
2.0
3.6
V
VBAT
battery supply voltage
for the RTC
2.2
3.6
V
Vprog(pf)
polyfuse programming voltage
on pin VPP
2.7
3.6
V
0.5
5.5
V
ADC/DAC pins and
digital I/O pins
configured for an
analog function (see
Table 3)
<tbd>
VDDA(3V3)
V
USB1 pins USB1_DP
and USB1_DM (see
Table 3)
<tbd>
<tbd>
V
input voltage
VI
only valid when the
VDD(IO) supply voltage is
present
[3]
5 V tolerant I/O pins
(see Table 3)
IDD
supply current
per supply pin
[4]
-
<tbd>
mA
[4]
-
<tbd>
mA
-
<tbd>
mA
<tbd>
<tbd>
C
-
<tbd>
W
<tbd>
<tbd>
V
ISS
ground current
per ground pin
Ilatch
I/O latch-up current
(0.5VDD(IO)) < VI <
(1.5VDD(IO));
Tj < 125 C
[5]
Tstg
storage temperature
Ptot(pack)
total power dissipation (per
package)
based on package heat
transfer, not device power
consumption
VESD
electrostatic discharge voltage
human body model; all
pins
[1]
[6]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2]
2.0 V if VBAT  2.2 V.
[3]
Including voltage on outputs in 3-state mode; at 2.0 V the speed will be reduced.
[4]
The peak current is limited to 25 times the corresponding maximum current.
[5]
Dependent on package type.
[6]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
T j = T amb +  P D  R th  j – a  
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 7.
Thermal characteristics
VDD = 2.2 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified;
Symbol
Parameter
Tj(max)
maximum junction
temperature
LPC4350_30_20_10
Objective data sheet
Conditions
Min
Typ
Max
Unit
-
-
<tbd>
C
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10. Static characteristics
Table 8.
Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
2.2
-
3.6
V
Supply pins
[2]
VDD(IO)
input/output supply
voltage
VDD(REG)(3V3)
regulator supply voltage
(3.3 V)
2.2
-
3.6
V
VDDA(3V3)
analog supply voltage
(3.3 V)
2.0
-
3.6
V
VBAT
battery supply voltage
[3]
2.2
-
3.6
V
IDD(REG)(3V3)
regulator supply current active mode; code
(3.3 V)
while(1){}
CCLK = 12 MHz; PLL
disabled
[4]
-
<tbd>
-
mA
CCLK = 100 MHz; PLL
enabled
[4]
-
<tbd>
-
mA
CCLK = 150 MHz; PLL
enabled
[4]
-
<tbd>
-
mA
[4]
-
<tbd>
-
mA
deep sleep mode
[4][6]
-
<tbd>
-
A
power-down mode
[4][6]
-
<tbd>
-
A
[4]
-
<tbd>
-
nA
VDD(REG)(3V3) present
[7]
-
<tbd>
-
nA
VDD(REG)(3V3) not
present
[8]
<tbd>
-
nA
executed from <tbd>; all
peripherals disabled
sleep mode
deep power-down mode;
RTC not running
IBAT
IDD(IO)
IDD(ADC)
battery supply current
I/O supply current
ADC supply current
LPC4350_30_20_10
Objective data sheet
deep power-down mode;
RTC running
<tbd>
deep sleep mode
[9]
-
<tbd>
-
nA
power-down mode
[9]
-
<tbd>
-
nA
deep power-down mode
[9]
-
<tbd>
-
nA
deep sleep mode
[10]
-
<tbd>
-
nA
power-down mode
[10]
-
<tbd>
-
nA
deep power-down mode
[10]
-
<tbd>
-
nA
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Table 8.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Digital pins - normal drive strength
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
-
<tbd>
A
IIH
HIGH-level input
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
-
<tbd>
A
IOZ
OFF-state output
current
VO = 0 V; VO = VDD(IO);
on-chip pull-up/down
resistors disabled
-
-
<tbd>
A
VI
input voltage
pin configured to provide
a digital function
<tbd>
-
<tbd>
V
<tbd>
-
VDD(IO)
V
V
[11][12]
[13]
VO
output voltage
VIH
HIGH-level input
voltage
<tbd>
-
-
output active
VIL
LOW-level input voltage
-
-
<tbd>
V
Vhys
hysteresis voltage
<tbd>
-
-
V
VOH
HIGH-level output
voltage
IOH = 4 mA
VDD(IO) 
0.4
-
-
V
VOL
LOW-level output
voltage
IOL = 4 mA
-
-
<tbd>
V
IOH
HIGH-level output
current
VOH = VDD(IO)  0.4 V
<tbd>
-
-
mA
IOL
LOW-level output
current
VOL = 0.4 V
<tbd>
-
-
mA
IOHS
HIGH-level short-circuit VOH = 0 V
output current
[14]
-
-
<tbd>
mA
IOLS
LOW-level short-circuit
output current
VOL = VDD(IO)
[14]
-
-
<tbd>
mA
Ipd
pull-down current
VI = 3.6 V
<tbd>
<tbd>
<tbd>
A
Ipu
pull-up current
VI = 0 V
<tbd>
<tbd>
<tbd>
A
VDD(IO) < VI < 3.6 V
<tbd>
<tbd>
<tbd>
A
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Table 8.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Digital pins - high drive strength
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
-
<tbd>
A
IIH
HIGH-level input
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
-
<tbd>
A
IOZ
OFF-state output
current
VO = 0 V; VO = VDD(IO);
on-chip pull-up/down
resistors disabled
-
-
<tbd>
A
VI
input voltage
pin configured to provide
a digital function
<tbd>
-
<tbd>
V
<tbd>
-
VDD(IO)
V
V
[11][12]
[13]
VO
output voltage
VIH
HIGH-level input
voltage
<tbd>
-
-
output active
VIL
LOW-level input voltage
-
-
<tbd>
V
Vhys
hysteresis voltage
<tbd>
-
-
V
VOH
HIGH-level output
voltage
IOH = 4 mA
VDD(IO) 
0.4
-
-
V
VOL
LOW-level output
voltage
IOL = 4 mA
-
-
<tbd>
V
IOH
HIGH-level output
current
VOH = VDD(IO)  0.4 V
<tbd>
-
-
mA
IOL
LOW-level output
current
VOL = 0.4 V
<tbd>
-
-
mA
IOHS
HIGH-level short-circuit VOH = 0 V
output current
[14]
-
-
<tbd>
mA
IOLS
LOW-level short-circuit
output current
VOL = VDD(IO)
[14]
-
-
<tbd>
mA
Ipd
pull-down current
VI = 3.6 V
<tbd>
<tbd>
<tbd>
A
Ipu
pull-up current
VI = 0 V
<tbd>
<tbd>
<tbd>
A
VDD(IO) < VI < 3.6 V
<tbd>
<tbd>
<tbd>
A
<tbd>
-
-
V
Open-drain I2C0-bus pins
VIH
HIGH-level input
voltage
VIL
LOW-level input voltage
-
-
<tbd>
V
Vhys
hysteresis voltage
-
<tbd>
-
V
VOL
LOW-level output
voltage
IOLS = <tbd> mA
-
-
<tbd>
V
ILI
input leakage current
VI = VDD(IO)
-
<tbd>
<tbd>
A
-
<tbd>
<tbd>
A
[15]
VI = 5 V
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Table 8.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Oscillator pins
Vi(XTAL1)
input voltage on pin
XTAL1
0.5
-
1.2
V
Vo(XTAL2)
output voltage on pin
XTAL2
0.5
-
1.2
V
high-speed mode
<tbd>
<tbd>
<tbd>
mV
full-speed/low-speed
mode
<tbd>
-
<tbd>
mV
chirp mode
<tbd>
-
<tbd>
mV
<tbd>
<tbd>
<tbd>
mV
USB pins
common-mode input
voltage
VIC
Vi(dif)
differential input voltage
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2]
Minimum value is 2.0 V if VBAT  2.2 V.
[3]
The RTC typically fails when VBAT drops below 2.2 V and VDD(REG)(3V3) is less than 2.2 V.
[4]
VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements.
[5]
IRC running at 12 MHz; <tbd>.
[6]
BOD disabled.
[7]
On pin VBAT; IDD(REG)(3V3) = <tbd> nA; VDD(REG)(3V3) = 3.3 V; VBAT < VDD(REG)(3V3); Tamb = 25 C.
[8]
On pin VBAT; VBAT = 3.3 V; Tamb = 25 C.
[9]
All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(REG)(3V3) = 3.3 V; Tamb = 25 C.
[10] VDDA(3V3) = 3.3 V; Tamb = 25 C.
[11] Including voltage on outputs in 3-state mode.
[12] VDD(REG)(3V3) supply voltages must be present.
[13] 3-state outputs go into 3-state mode in Deep power-down mode.
[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[15] To VSS.
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10.1 Electrical pin characteristics
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins.
Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins.
Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL
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001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins.
Fig 14. Typical pull-up current Ipu versus input voltage VI
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins.
Fig 15. Typical pull-down current Ipd versus input voltage VI
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10.2 Power consumption
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: <tbd>.
Fig 16. Typical supply current versus regulator supply voltage VDD(REEG)(3V3) in active
mode
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: <tbd>.
Fig 17. Typical supply current versus temperature in active mode
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001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: <tbd>
Fig 18. Typical supply current versus temperature in Sleep mode
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: <tbd>
Fig 19. Typical supply current versus temperature in Deep-sleep mode
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001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Fig 20. Typical supply current versus temperature in Power-down mode
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Fig 21. Typical supply current versus temperature in Deep power-down mode
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Table 9.
Power consumption for individual peripherals
Tamb = 25 C; VDD(REEG)(3V3) = 3.3 V.
Peripheral
Conditions
<tbd>
<tbd>
[1]
LPC4350_30_20_10
Objective data sheet
Typical IDD[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
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11. Dynamic characteristics
11.1 Digital I/O and CLKOUT pins, oscillator, PLL, and C_CAN
Table 10. Dynamic characteristics: Digital I/O and CLKOUT pins, oscillator, PLL, and C_CAN
VDD(IO) , VDD(REG)(3V3) over specified ranges; all voltages are measured with respect to ground; positive currents flow into the
IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Digital I/O pins
tTHL
HIGH to LOW transition CL = 30 pF
time
<tbd>
-
<tbd>
ns
tTLH
LOW to HIGH transition CL = 30 pF
time
<tbd>
-
<tbd>
ns
clock frequency
on pin CLKOUT
-
-
<tbd>
MHz
start-up time
at maximum frequency
-
<tbd>
-
s
0.014
-
25
MHz
CLKOUT pin
fclk
Oscillator
tstartup
[1]
PLL0
fi(PLL)
PLL input frequency
fo(PLL)
PLL output frequency
CCO; direct mode
4.3
-
550
MHz
275
-
550
MHz
10
-
25
MHz
PLL1
fi(PLL)
PLL input frequency
fo(PLL)
PLL output frequency
10
-
160
MHz
CCO; direct mode
156
-
320
MHz
on CAN TD1 pin
-
<tbd>
<tbd>
ns
Jitter specification for C_CAN
tjit(cc)(p-p)
[1]
cycle to cycle jitter
(peak-to-peak value)
Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully
stable.
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001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Fig 22. I/O delay versus VDD(IO) for digital I/O pins
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Fig 23. I/O delay versus VDD(IO) for CLKOUT pin
11.2 External clock
Table 11. Dynamic characteristic: external clock
Tamb = 40 C to +85 C; VDD(IO) over specified ranges.[1]
Symbol Parameter
LPC4350_30_20_10
Objective data sheet
Conditions
Min
Typ[2]
Max
Unit
fosc
oscillator frequency
1
-
25
MHz
Tcy(clk)
clock cycle time
40
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk)  0.4
-
-
ns
tCLCX
clock LOW time
Tcy(clk)  0.4
-
-
ns
tCLCH
clock rise time
-
-
5
ns
tCHCL
clock fall time
-
-
5
ns
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[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 24. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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11.3 IRC and RTC oscillators
Table 12. Dynamic characteristic: IRC and RTC oscillators
Tamb = 40 C to +85 C; <tbd>  VDD(IO)  <tbd>.[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc(RC)
internal RC oscillator
frequency
-
<tbd>
12.00
<tbd>
MHz
fi(RTC)
RTC input frequency
-
-
32.768
-
kHz
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for
2.7 V  VDD(IO)  3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC
to fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 25. Internal RC oscillator frequency versus temperature
11.4 I2C-bus
Table 13. Dynamic characteristic: I2C-bus pins
Tamb = 40 C to +85 C.[1]
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
of both SDA and
SCL signals
-
300
ns
Fast-mode
20 + 0.1  Cb
300
ns
Fast-mode Plus
-
120
ns
tf
fall time
[3][4][5][6]
Standard-mode
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Table 13. Dynamic characteristic: I2C-bus pins
Tamb = 40 C to +85 C.[1]
Symbol
Parameter
Conditions
Min
Max
Unit
tLOW
LOW period of the SCL clock
Standard-mode
4.7
-
s
Fast-mode
1.3
-
s
tHIGH
tHD;DAT
tSU;DAT
[1]
HIGH period of the SCL clock
[2][3][7]
data hold time
[8][9]
data set-up time
Fast-mode Plus
0.5
-
s
Standard-mode
4.0
-
s
Fast-mode
0.6
-
s
Fast-mode Plus
0.26
-
s
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus
0
-
s
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
Parameters are valid over operating temperature range unless otherwise specified.
[2]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4]
Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[6]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[7]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[8]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[9]
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
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tf
SDA
tSU;DAT
70 %
30 %
70 %
30 %
tHD;DAT
tf
70 %
30 %
SCL
tVD;DAT
tHIGH
70 %
30 %
70 %
30 %
70 %
30 %
tLOW
1 / fSCL
S
002aaf425
Fig 26. I2C-bus pins clock timing
11.5 I2S-bus interface
Table 14. Dynamic characteristics: I2S-bus interface pins
Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>. Conditions and data refer to I2S0 and I2S1 pins.
Symbol
Parameter
Conditions
Min
Max
Unit
common to input and output
rise time
[1]
-
<tbd>
ns
fall time
[1]
-
<tbd>
ns
tWH
pulse width HIGH
on pins I2S_TX_SCK and
I2S_RX_SCK
[1]
<tbd>
-
-
tWL
pulse width LOW
on pins I2S_TX_SCK and
I2S_RX_SCK
[1]
-
<tbd>
ns
data output valid time
on pin I2S_TX_SDA
[1]
-
<tbd>
ns
data input set-up time
on pin I2S_RX_SDA
[1]
<tbd>
-
ns
on pin I2S_RX_SDA
[1]
<tbd>
-
ns
tr
tf
output
tv(Q)
input
tsu(D)
th(D)
[1]
LPC4350_30_20_10
Objective data sheet
data input hold time
CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time Tcy(clk) =
1600 ns, corresponds to the SCK signal in the I2S-bus specification.
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Tcy(clk)
tf
tr
I2S_TX_SCK
tWH
tWL
I2S_TX_SDA
tv(Q)
I2S_TX_WS
002aag202
tv(Q)
Fig 27. I2S-bus timing (transmit)
Tcy(clk)
tf
tr
I2S_RX_SCK
tWH
tWL
I2S_RX_SDA
tsu(D)
th(D)
I2S_RX_WS
tsu(D)
tsu(D)
002aag203
Fig 28. I2S-bus timing (receive)
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11.6 SSP interface
Table 15.
Dynamic characteristics: SSP pins in SPI mode
Symbol
Parameter
Tcy(PCLK)
PCLK cycle time
Tcy(clk)
clock cycle time
Conditions
full-duplex mode
[1]
when only
transmitting
Min
Max
Unit
<tbd>
-
ns
<tbd>
-
ns
<tbd>
-
ns
SSP master
data set-up time
tDS
in SPI mode
[2]
<tbd>
Tcy(clk)
ns
tDH
data hold time
in SPI mode
[2]
-
<tbd>
ns
tv(Q)
data output valid time
in SPI mode
[2]
-
<tbd>
ns
data output hold time
in SPI mode
[2]
-
<tbd>
ns
tDS
data set-up time
in SPI mode
[3][4]
<tbd>
-
ns
tDH
data hold time
in SPI mode
[3][4]
<tbd>  Tcy(PCLK) +
<tbd>
-
ns
tv(Q)
data output valid time
in SPI mode
[3][4]
-
<tbd>  Tcy(PCLK) +
<tbd>
ns
th(Q)
data output hold time
in SPI mode
[3][4]
-
<tbd>  Tcy(PCLK) +
<tbd>
ns
th(Q)
SSP slave
[1]
Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
Tamb = 40 C to 85 C; VDD(REG)(3V3) = 2.0 V to 3.6 V; VDD(IO) = 2.0 V to 3.6 V.
[3]
Tcy(clk) = 12  Tcy(PCLK).
[4]
Tamb = 25 C; VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V.
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Tcy(clk)
tclk(H)
tclk(L)
SCK (CPOL = 0)
SCK (CPOL = 1)
tv(Q)
th(Q)
DATA VALID
MOSI
DATA VALID
tDS
DATA VALID
MISO
tDH
DATA VALID
tv(Q)
MOSI
th(Q)
DATA VALID
DATA VALID
tDH
tDS
MISO
CPHA = 1
DATA VALID
CPHA = 0
DATA VALID
002aae829
Fig 29. SSP master timing in SPI mode
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Tcy(clk)
tclk(H)
tclk(L)
tDS
tDH
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
DATA VALID
DATA VALID
tv(Q)
MISO
th(Q)
DATA VALID
tDH
tDS
MOSI
DATA VALID
DATA VALID
tv(Q)
MISO
CPHA = 1
DATA VALID
th(Q)
DATA VALID
CPHA = 0
DATA VALID
002aae830
Fig 30. SSP slave timing in SPI mode
11.7 USART3 IrDA
Table 16.
Dynamic characteristics: USART3 IrDA
Symbol
Parameter
tr(tx)
tf(tx)
Conditions
Min
Max
Unit
transmit rise time
<tbd>
<tbd>
ns
transmit fall time
-
<tbd>
ns
UART frame
start
TX data
0
data bits
1
0
1
0
stop
0
1
1
0
1
IrDA TX data
1/ bit time
2
bit
time
3/ bit time
16
002aaa212
Fig 31. USART3 IrDA transmit timing
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IrDA RX data
bit
time
RX data
0 to 1 16× clock delay
0
1
0
1
start
0
0
data bits
1
1
0
1
stop
UART frame
002aaa213
Fig 32. USART3 IrDA receive timing
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11.8 External memory interface
Table 17. Dynamic characteristics: Static external memory interface
CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.
Symbol
Parameter[1]
Conditions[1]
Read cycle
parameters[2]
Min
Typ
Max
Unit
tCSLAV
CS LOW to address valid
time
RD1
<tbd>
<tbd>
<tbd>
ns
tCSLOEL
CS LOW to OE LOW time
RD2
<tbd> + Tcy(clk) 
WAITOEN
<tbd> + Tcy(clk) 
WAITOEN
<tbd> + Tcy(clk) 
WAITOEN
ns
tCSLBLSL
CS LOW to BLS LOW time
RD3; PB = 1
<tbd>
<tbd>
<tbd>
ns
tOELOEH
OE LOW to OE HIGH time
RD4
(WAITRD 
(WAITRD 
WAITOEN + 1)  WAITOEN + 1) 
Tcy(clk)  <tbd>
Tcy(clk)  <tbd>
tam
memory access time
RD5
[3]
(WAITRD 
WAITOEN +1) 
Tcy(clk)  <tbd>
(WAITRD 
WAITOEN +1) 
Tcy(clk)  <tbd>
(WAITRD 
WAITOEN +1) 
Tcy(clk)  <tbd>
ns
th(D)
data input hold time
RD6
[4]
<tbd>
<tbd>
<tbd>
ns
(WAITRD 
ns
WAITOEN + 1) 
Tcy(clk)  <tbd>
tCSHBLSH
CS HIGH to BLS HIGH time PB = 1
<tbd>
<tbd>
<tbd>
ns
tCSHOEH
CS HIGH to OE HIGH time
<tbd>
<tbd>
<tbd>
ns
tOEHANV
OE HIGH to address invalid
time
<tbd>
<tbd>
<tbd>
ns
tdeact
deactivation time
RD7
<tbd>
<tbd>
<tbd>
ns
Write cycle parameters[2]
tCSLAV
CS LOW to address valid
time
WR1
<tbd>
<tbd>
<tbd>
ns
tCSLDV
CS LOW to data valid time
WR2
<tbd>
<tbd>
<tbd>
ns
tCSLWEL
CS LOW to WE LOW time
WR3; PB =1
<tbd> + Tcy(clk) 
(1 + WAITWEN)
<tbd> + Tcy(clk) 
(1 + WAITWEN)
<tbd> + Tcy(clk) 
(1 + WAITWEN)
ns
tCSLBLSL
CS LOW to BLS LOW time
WR4; PB = 1
<tbd>
<tbd>
<tbd>
ns
tWELWEH
WE LOW to WE HIGH time
WR5; PB =1
(WAITWR 
(WAITWR 
ns
(WAITWR 
WAITWEN + 1)  WAITWEN + 1)  WAITWEN + 1) 
Tcy(clk)  <tbd>
Tcy(clk)  <tbd>
Tcy(clk)  <tbd>
tBLSLBLSH
BLS LOW to BLS HIGH time PB = 1
(WAITWR 
(WAITWR 
ns
(WAITWR 
WAITWEN + 3)  WAITWEN + 3)  WAITWEN + 3) 
Tcy(clk)  <tbd>
Tcy(clk)  <tbd>
Tcy(clk)  <tbd>
tWEHDNV
WE HIGH to data invalid
time
WR6; PB =1
<tbd> + Tcy(clk)
<tbd> + Tcy(clk)
<tbd> + Tcy(clk)
ns
tWEHEOW
WE HIGH to end of write
time
WR7; PB = 1
<tbd> + Tcy(clk)
<tbd> + Tcy(clk)
<tbd> + Tcy(clk)
ns
tBLSHDNV
BLS HIGH to data invalid
time
PB = 1
<tbd>
<tbd>
<tbd>
ns
tWEHANV
WE HIGH to address invalid PB = 1
time
<tbd> + Tcy(clk)
<tbd> + Tcy(clk)
<tbd> + Tcy(clk)
ns
tdeact
deactivation time
WR8; PB = 0;
PB = 1
<tbd>
<tbd>
<tbd>
ns
tCSLBLSL
CS LOW to BLS LOW
WR9; PB = 0
<tbd>
<tbd>
<tbd>
ns
LPC4350_30_20_10
Objective data sheet
[5]
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32-bit ARM Cortex-M4/M0 microcontroller
Table 17. Dynamic characteristics: Static external memory interface …continued
CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.
Symbol
Parameter[1]
Conditions[1]
tBLSLBLSH
BLS LOW to BLS HIGH time WR10; PB = 0
tBLSHEOW
BLS HIGH to end of write
time
WR11; PB = 0
tBLSHDNV
BLS HIGH to data invalid
time
WR12;
PB = 0
Min
Typ
Max
Unit
(WAITWR 
(WAITWR 
(WAITWR 
ns
WAITWEN + 1)  WAITWEN + 1)  WAITWEN + 1) 
Tcy(clk) + <tbd>
Tcy(clk) + <tbd>
Tcy(clk) + <tbd>
[5]
<tbd>
<tbd>
<tbd>
ns
<tbd>
<tbd>
<tbd>
ns
[1]
Parameters are shown as RDn or WDn in Figure 33 as indicated in the Conditions column.
[2]
Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges.
[3]
Latest of address valid, CS LOW, OE LOW, BLSx LOW (PB = 1).
[4]
After End Of Read (EOR): Earliest of CS HIGH, OE HIGH, BLSx HIGH (PB = 1), address invalid.
[5]
End Of Write (EOW): Earliest of address invalid, CS HIGH, BLSx HIGH (PB = 1).
EMC_Ax
RD1
WR1
EMC_CSx
WR8
RD2
RD4
EMC_OE
RD7
WR9
WR10
WR11
EMC_BLSx
EMC_WE
RD5
RD5
RD5
RD6
WR2
WR12
EMC_Dx
EOR
EOW
002aag214
Fig 33. External static memory read/write access (PB = 0)
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EMC_Ax
RD1
WR1
EMC_CSx
WR8
RD2
RD4
EMC_OE
RD3
WR4
RD7
EMC_BLSx
WR8
RD7
WR3
WR5
WR7
EMC_WE
RD5
RD5
RD5
RD6
RD5
WR2
WR6
EMC_Dx
EOR
EOW
002aag215
Fig 34. External static memory read/write access (PB = 1)
EMC_Ax
EMC_CSx
EMC_OE
EMC_BLSx
EMC_WE
RD5
RD5
RD5
RD5
EMC_Dx
002aag216
Fig 35. External static memory burst read cycle
Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00
CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Common to read and write cycles
Tcy(clk)
clock cycle time
<tbd>
-
-
ns
td(SV)
chip select valid delay time
<tbd>
<tbd>
<tbd>
ns
th(S)
chip select hold time
<tbd>
<tbd>
<tbd>
ns
td(RASV)
row address strobe valid delay time
<tbd>
<tbd>
<tbd>
ns
th(RAS)
row address strobe hold time
<tbd>
<tbd>
<tbd>
ns
td(CASV)
column address strobe valid delay time
<tbd>
<tbd>
<tbd>
ns
th(CAS)
column address strobe hold time
<tbd>
<tbd>
<tbd>
ns
LPC4350_30_20_10
Objective data sheet
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32-bit ARM Cortex-M4/M0 microcontroller
Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 …continued
CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.
Symbol
Parameter
td(WV)
Conditions
Min
Typ
Max
Unit
write valid delay time
<tbd>
<tbd>
<tbd>
ns
th(W)
write hold time
<tbd>
<tbd>
<tbd>
ns
td(GV)
output enable valid delay time
<tbd>
<tbd>
<tbd>
ns
th(G)
output enable hold time
<tbd>
<tbd>
<tbd>
ns
td(AV)
address valid delay time
<tbd>
<tbd>
<tbd>
ns
th(A)
address hold time
<tbd>
<tbd>
<tbd>
ns
Read cycle parameters
tsu(D)
data input set-up time
<tbd>
<tbd>
<tbd>
ns
th(D)
data input hold time
<tbd>
<tbd>
<tbd>
ns
Write cycle parameters
td(QV)
data output valid delay time
<tbd>
<tbd>
<tbd>
ns
th(Q)
data output hold time
<tbd>
<tbd>
<tbd>
ns
Table 19. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01
CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Common to read and write cycles
Tcy(clk)
clock cycle time
<tbd>
-
-
ns
td(SV)
chip select valid delay time
<tbd>
<tbd>
<tbd>
ns
th(S)
chip select hold time
<tbd>
<tbd>
<tbd>
ns
td(RASV)
row address strobe valid delay time
<tbd>
<tbd>
<tbd>
ns
th(RAS)
row address strobe hold time
<tbd>
<tbd>
<tbd>
ns
td(CASV)
column address strobe valid delay time
<tbd>
<tbd>
<tbd>
ns
th(CAS)
column address strobe hold time
<tbd>
<tbd>
<tbd>
ns
td(WV)
write valid delay time
<tbd>
<tbd>
<tbd>
ns
th(W)
write hold time
<tbd>
<tbd>
<tbd>
ns
td(GV)
output enable valid delay time
-
-
-
ns
th(G)
output enable hold time
-
-
-
ns
td(AV)
address valid delay time
<tbd>
<tbd>
<tbd>
ns
th(A)
address hold time
<tbd>
<tbd>
<tbd>
ns
Read cycle parameters
tsu(D)
data input set-up time
<tbd>
<tbd>
<tbd>
ns
th(D)
data input hold time
<tbd>
<tbd>
<tbd>
ns
Write cycle parameters
td(QV)
data output valid delay time
<tbd>
<tbd>
<tbd>
ns
th(Q)
data output hold time
<tbd>
<tbd>
<tbd>
ns
LPC4350_30_20_10
Objective data sheet
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32-bit ARM Cortex-M4/M0 microcontroller
Tcy(clk)
EMC_CLKx
EMC_DYCSx
td(CS)
th(CS)
td(RAS)
th(RAS)
EMC_RAS
td(CAS)
th(CAS)
EMC_CAS
EMC_WE
td(DQM)
th(DQM)
EMC_DQMOUTx
td(A)
th(A)
EMC_Ax
tsu(D)
th(D)
EMC_Dx
002aag205
Fig 36. Dynamic external memory interface signal timing (read access)
11.9 Ethernet
Table 20. Dynamic characteristics: Ethernet
Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.
Symbol Parameter
Conditions
Min
Max
Unit
[1]
-
<tbd>
MHz
clock duty cycle
[1]
<tbd>
<tbd>
%
tsu
set-up time
for ENET_TXDn, ENET_TX_EN,
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
<tbd>
-
ns
th
hold time
for ENET_TXDn, ENET_TX_EN,
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
<tbd>
-
ns
clock frequency
for ENET_TX_CLK
[1]
-
<tbd>
MHz
[1]
RMII mode
fclk
clk
clock frequency
for ENET_RX_CLK
MII mode
fclk
LPC4350_30_20_10
Objective data sheet
clk
clock duty cycle
<tbd>
<tbd>
%
tsu
set-up time
for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
[1][2]
<tbd>
-
ns
th
hold time
for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
[1][2]
<tbd>
-
ns
fclk
clock frequency
for ENET_RX_CLK
[1]
-
<tbd>
MHz
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32-bit ARM Cortex-M4/M0 microcontroller
Table 20. Dynamic characteristics: Ethernet
Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.
Symbol Parameter
Min
Max
Unit
clock duty cycle
[1]
<tbd>
<tbd>
%
tsu
set-up time
for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
<tbd>
-
ns
th
hold time
for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
<tbd>
-
ns
clk
Conditions
[1]
Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input
capacitance of the receiving device.
[2]
Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or
output level.
ENET_RX_CLK
ENET_TX_CLK
tsu
ENET_RXD[n]
ENET_RX_DV
ENET_RX_ER
ENET_TXD[n]
ENET_TX_EN
ENET_TX_ER
th
002aag210
Fig 37. Ethernet timing
11.10 SD/MMC
Table 21. Dynamic characteristics: SD/MMC
Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
LPC4350_30_20_10
Objective data sheet
Symbol
Parameter
Conditions
Min
Max
Unit
fclk
clock frequency
on pin SD_CLK; data transfer mode
-
25
MHz
tsu(D)
data input set-up
time
on pin SD_CLK; identification mode
-
25
MHz
on pins SD_CMD, SD_DATn as
inputs
6
-
ns
th(D)
data input hold time on pins SD_CMD, SD_DATn as
inputs
6
-
ns
td(QV)
data output valid
delay time
on pins SD_CMD, SD_DATn as
outputs
-
23
ns
th(Q)
data output hold
time
on pins SD_CMD, SD_DATn as
outputs
3.5
-
ns
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32-bit ARM Cortex-M4/M0 microcontroller
Tcy(clk)
SD_CLK
td(QV)
th(Q)
SD_CMD (O)
SD_DATn (O)
tsu(D)
th(D)
SD_CMD (I)
SD_DATn (I)
002aag204
Fig 38. SD/MMC timing
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32-bit ARM Cortex-M4/M0 microcontroller
12. ADC/DAC electrical characteristics
Table 22. ADC characteristics
VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; ADC frequency 4.5 MHz; unless otherwise specified.
Symbol
Parameter
VIA
Cia
ED
differential linearity error
Min
Typ
Max
analog input voltage
0
-
VDDA(3V3)
V
analog input capacitance
-
-
<tbd>
pF
[1][2][3]
-
-
<tbd>
LSB
integral non-linearity
[1][4]
-
-
<tbd>
LSB
EO
offset error
[1][5]
-

<tbd>
LSB
EG
gain error
[1][6]
-
-
<tbd>
%
ET
absolute error
[1][7]
-
-
<tbd>
LSB
[8]
-
-
<tbd>
k
[9][10]
-
-
<tbd>
M
EL(adj)
Conditions
Unit
Rvsi
voltage source interface
resistance
Ri
input resistance
fclk(ADC)
ADC clock frequency
-
-
<tbd>
MHz
fc(ADC)
ADC conversion frequency
-
-
<tbd>
kSamples/s
[1]
Conditions: VSSA = 0 V, VDDA(3V3) = 3.3 V.
[2]
The ADC is monotonic, there are no missing codes.
[3]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 39.
[4]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 39.
[5]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 39.
[6]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 39.
[7]
The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 39.
[8]
See <tbd>.
[9]
Tamb = 25 C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1pF.
[10] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia).
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32-bit ARM Cortex-M4/M0 microcontroller
offset
error
EO
gain
error
EG
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
(5)
4
(4)
3
(3)
2
1 LSB
(ideal)
1
0
1
2
3
4
5
6
7
1018
1019
1020
1021
1022
1023
1024
VIA (LSBideal)
offset error
EO
1 LSB =
VDDA − VSSA
1024
002aac046
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
(6) VDDA refers to VDDA(3V3) on pin VDDA and VSSA to analog ground on pin VSSA.
Fig 39. 10-bit ADC characteristics
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Table 23. DAC electrical characteristics
VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified
Symbol
Parameter
ED
Min
Typ
Max
Unit
differential linearity error
-
<tbd>
-
LSB
EL(adj)
integral non-linearity
-
<tbd>
-
LSB
EO
offset error
-
<tbd>
-
%
EG
gain error
-
<tbd>
-
%
CL
load capacitance
-
<tbd>
-
pF
RL
load resistance
<tbd>
-
-
k
LPC4350_30_20_10
Objective data sheet
Conditions
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32-bit ARM Cortex-M4/M0 microcontroller
13. Application information
13.1 LCD panel signal usage
Table 24.
LCD panel connections for STN single panel mode
External pin
4-bit mono STN single panel
8-bit mono STN single panel
Color STN single panel
LPC43xx pin
used
LCD function
LPC43xx pin
used
LCD function
LPC43xx pin
used
LCD function
LCD_VD[23:8]
-
-
-
-
-
-
LCD_VD7
-
-
P8_4
UD[7]
P8_4
UD[7]
LCD_VD6
-
-
P8_5
UD[6]
P8_5
UD[6]
LCD_VD5
-
-
P8_6
UD[5]
P8_6
UD[5]
LCD_VD4
-
-
P8_7
UD[4]
P8_7
UD[4]
LCD_VD3
P4_2
UD[3]
P4_2
UD[3]
P4_2
UD[3]
LCD_VD2
P4_3
UD[2]
P4_3
UD[2]
P4_3
UD[2]
LCD_VD1
P4_4
UD[1]
P4_4
UD[1]
P4_4
UD[1]
LCD_VD0
P4_1
UD[0]
P4_1
UD[0]
P4_1
UD[0]
LCD_LP
P7_6
LCDLP
P7_6
LCDLP
P7_6
LCDLP
LCD_ENAB/
LCDM
P4_6
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
LCD_FP
P4_5
LCDFP
P4_5
LCDFP
P4_5
LCDFP
LCD_DCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
LCD_LE
P7_0
LCDLE
P7_0
LCDLE
P7_0
LCDLE
LCD_PWR
P7_7
CDPWR
P7_7
LCDPWR
P7_7
LCDPWR
GP_CLKIN
PF_4
LCDCLKIN
PF_4
LCDCLKIN
PF_4
LCDCLKIN
Table 25.
LCD panel connections for STN dual panel mode
External pin
4-bit mono STN dual panel
8-bit mono STN dual panel
Color STN dual panel
LPC43xx pin
used
LCD function
LPC43xx pin
used
LCD function
LPC43xx pin
used
LCD function
LCD_VD[23:16] -
-
-
-
-
-
LCD_VD15
-
-
PB_4
LD[7]
PB_4
LD[7]
LCD_VD14
-
-
PB_5
LD[6]
PB_5
LD[6]
LCD_VD13
-
-
PB_6
LD[5]
PB_6
LD[5]
LCD_VD12
-
-
P8_3
LD[4]
P8_3
LD[4]
LCD_VD11
P4_9
LD[3]
P4_9
LD[3]
P4_9
LD[3]
LCD_VD10
P4_10
LD[2]
P4_10
LD[2]
P4_10
LD[2]
LCD_VD9
P4_8
LD[1]
P4_8
LD[1]
P4_8
LD[1]
LCD_VD8
P7_5
LD[0]
P7_5
LD[0]
P7_5
LD[0]
LCD_VD7
-
-
UD[7]
P8_4
UD[7]
LCD_VD6
-
-
P8_5
UD[6]
P8_5
UD[6]
LCD_VD5
-
-
P8_6
UD[5]
P8_6
UD[5]
LCD_VD4
-
-
P8_7
UD[4]
P8_7
UD[4]
LCD_VD3
P4_2
UD[3]
P4_2
UD[3]
P4_2
UD[3]
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32-bit ARM Cortex-M4/M0 microcontroller
Table 25.
LCD panel connections for STN dual panel mode
External pin
4-bit mono STN dual panel
8-bit mono STN dual panel
Color STN dual panel
LPC43xx pin
used
LCD function
LPC43xx pin
used
LCD function
LPC43xx pin
used
LCD function
LCD_VD2
P4_3
UD[2]
P4_3
UD[2]
P4_3
UD[2]
LCD_VD1
P4_4
UD[1]
P4_4
UD[1]
P4_4
UD[1]
LCD_VD0
P4_1
UD[0]
P4_1
UD[0]
P4_1
UD[0]
LCD_LP
P7_6
LCDLP
P7_6
LCDLP
P7_6
LCDLP
LCD_ENAB/
LCDM
P4_6
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
LCD_FP
P4_5
LCDFP
P4_5
LCDFP
P4_5
LCDFP
LCD_DCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
LCD_LE
P7_0
LCDLE
P7_0
LCDLE
P7_0
LCDLE
LCD_PWR
P7_7
LCDPWR
P7_7
LCDPWR
P7_7
LCDPWR
GP_CLKIN
PF_4
LCDCLKIN
PF_4
LCDCLKIN
PF_4
LCDCLKIN
Table 26.
External
pin
LCD panel connections for TFT panels
TFT 12 bit (4:4:4
mode)
TFT 16 bit (5:6:5 mode)
TFT 16 bit (1:5:5:5 mode) TFT 24 bit
LPC43xx
pin used
LCD
function
LPC43xx
pin used
LCD
function
LPC43xx pin LCD
used
function
LCD_VD23 PB_0
BLUE3
PB_0
BLUE4
PB_0
BLUE4
BLUE7
LCD_VD22 PB_1
BLUE2
PB_1
BLUE3
PB_1
BLUE3
BLUE6
LCD_VD21 PB_2
BLUE1
PB_2
BLUE2
PB_2
BLUE2
BLUE5
LCD_VD20 PB_3
BLUE0
PB_3
BLUE1
PB_3
BLUE1
BLUE4
LCD_VD19 -
-
P7_1
BLUE0
P7_1
BLUE0
BLUE3
LPC43xx
pin used
LCD
function
LCD_VD18 -
-
-
-
P7_2
intensity
LCD_VD17 -
-
-
-
-
-
P7_3
BLUE1
LCD_VD16 -
-
-
-
-
-
P7_4
BLUE0
LCD_VD15 PB_4
GREEN3
PB_4
GREEN5
PB_4
GREEN4
PB_4
GREEN7
LCD_VD14 PB_5
GREEN2
PB_5
GREEN4
PB_5
GREEN3
PB_5
GREEN6
LCD_VD13 PB_6
GREEN1
PB_6
GREEN3
PB_6
GREEN2
PB_6
GREEN5
LCD_VD12 P8_3
GREEN0
P8_3
GREEN2
P8_3
GREEN1
P8_3
GREEN4
LCD_VD11
-
P4_9
GREEN1
P4_9
GREEN0
P4_9
GREEN3
-
BLUE2
LCD_VD10 -
-
P4_10
GREEN0
P4_10
intensity
P4_10
GREEN2
LCD_VD9
-
-
-
-
-
-
P4_8
GREEN1
LCD_VD8
-
-
-
-
-
-
P7_5
GREEN0
LCD_VD7
P8_4
RED3
P8_4
RED4
P8_4
RED4
P8_4
RED7
LCD_VD6
P8_5
RED2
P8_5
RED3
P8_5
RED3
P8_5
RED6
LCD_VD5
P8_6
RED1
P8_6
RED2
P8_6
RED2
P8_6
RED5
LCD_VD4
P8_7
RED0
P8_7
RED1
P8_7
RED1
P8_7
RED4
LCD_VD3
-
-
P4_2
RED0
P4_2
RED0
P4_2
RED3
LCD_VD2
-
-
-
-
P4_3
intensity
P4_3
RED2
LCD_VD1
-
-
-
-
-
-
P4_4
RED1
LPC4350_30_20_10
Objective data sheet
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123 of 145
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NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 26.
External
pin
LCD panel connections for TFT panels
TFT 12 bit (4:4:4
mode)
TFT 16 bit (5:6:5 mode)
TFT 16 bit (1:5:5:5 mode) TFT 24 bit
LPC43xx
pin used
LPC43xx
pin used
LPC43xx pin LCD
used
function
LCD
function
LCD
function
LPC43xx
pin used
LCD
function
LCD_VD0
-
-
-
-
-
-
P4_1
RED0
LCD_LP
P7_6
LCDLP
P7_6
LCDLP
P7_6
LCDLP
P7_6
LCDLP
LCDENAB/
LCDM
P4_6
LCDENAB/ P4_6
LCDM
LCD_ENAB P4_6
/LCDM
LCDENAB/ P4_6
LCDM
LCD_FP
P4_5
LCDENAB/
LCDM
LCDFP
P4_5
LCDFP
P4_5
LCDFP
P4_5
LCDFP
LCD_DCLK P4_7
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
LCD_LE
P7_0
LCDLE
P7_0
LCDLE
P7_0
LCDLE
P7_0
LCDLE
LCD_PWR
P7_7
LCDPWR
P7_7
LCDPWR
P7_7
LCDPWR
P7_7
LCDPWR
GP_CLKIN
PF_4
LCDCLKIN PF_4
LCDCLKIN
PF_4
LCDCLKIN PF_4
LCDCLKIN
13.2 Crystal oscillator
The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see
LPC43xx user manual).
The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL.
The oscillator can operate in one of two modes: slave mode and oscillation mode.
• In slave mode the input clock signal should be coupled by means of a capacitor of
100 pF (CC in Figure 40), with an amplitude of at least 200 mV (rms). The XTAL2 pin
in this configuration can be left unconnected.
• External components and models used in oscillation mode are shown in Figure 41,
and in Table 27 and Table 28. Since the feedback resistance is integrated on chip,
only a crystal and the capacitances CX1 and CX2 need to be connected externally in
case of fundamental mode oscillation (the fundamental frequency is represented by L,
CL and RS). Capacitance CP in Figure 41 represents the parallel package capacitance
and should not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the
crystal manufacturer.
Table 27.
Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency
2 MHz
4 MHz
8 MHz
LPC4350_30_20_10
Objective data sheet
Maximum crystal series
resistance RS
External load capacitors
CX1, CX2
< 200 
33 pF, 33 pF
< 200 
39 pF, 39 pF
< 200 
56 pF, 56 pF
< 200 
18 pF, 18 pF
< 200 
39 pF, 39 pF
< 200 
56 pF, 56 pF
< 200 
18 pF, 18 pF
< 200 
39 pF, 39 pF
All information provided in this document is subject to legal disclaimers.
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NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 27.
Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency
Maximum crystal series
resistance RS
External load capacitors
CX1, CX2
12 MHz
< 160 
18 pF, 18 pF
< 160 
39 pF, 39 pF
16 MHz
< 120 
18 pF, 18 pF
< 80 
33 pF, 33 pF
<100 
18 pF, 18 pF
< 80 
33 pF, 33 pF
20 MHz
Table 28.
Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation
frequency
Maximum crystal series
resistance RS
External load capacitors CX1,
Cx2
15 MHz
< 80 
18 pF, 18 pF
20 MHz
< 80 
39 pF, 39 pF
< 100 
47 pF, 47 pF
LPC43xx
XTAL1
Ci
100 pF
Cg
002aag379
Fig 40. Slave mode operation of the on-chip oscillator
LPC43xx
L
XTAL1
XTAL2
=
CL
CP
XTAL
RS
CX1
CX2
002aag380
Fig 41. Oscillator modes with external crystal model used for CX1/CX2 evaluation
LPC4350_30_20_10
Objective data sheet
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125 of 145
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NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
13.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
LPC4350_30_20_10
Objective data sheet
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126 of 145
LPC4350/30/20/10
NXP Semiconductors
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14. Package outline
LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm
A
B
D
SOT740-2
ball A1
index area
A2
A
E
A1
detail X
C
e1
e
y
y1 C
∅v M C A B
b
1/2 e
∅w M C
T
R
e
P
N
M
L
K
J
e2
H
G
1/2 e
F
E
D
C
B
A
ball A1
index area
1
3
2
5
4
7
6
9
8
11
10
13
12
15
14
16
X
5
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.55
0.45
0.35
1.1
0.9
0.55
0.45
17.2
16.8
17.2
16.8
1
15
15
0.25
0.1
0.12
0.35
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT740-2
---
MO-192
---
EUROPEAN
PROJECTION
ISSUE DATE
05-06-16
05-08-04
Fig 42. Package outline LBGA256 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
127 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
TFBGA180: thin fine-pitch ball grid array package; 180 balls
SOT570-3
A
B
D
ball A1
index area
E
A2
A
A1
detail X
e1
e
1/2 e
∅v
∅w
b
M
M
C
C A B
C
y
y1 C
P
N
M
L
K
J
H
G
F
E
D
C
B
A
ball A1
index area
e
e2
1/2 e
1
2
3
4
5
6
7
8
9
10
11
12
13
X
14
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
max
nom
min
A
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
1.20
1.06
0.95
0.40
0.35
0.30
0.80
0.71
0.65
0.50
0.45
0.40
12.1
12.0
11.9
12.1
12.0
11.9
0.8
10.4
10.4
0.15
0.05
0.12
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
08-07-09
10-04-15
SOT570-3
Fig 43. Package outline of the TFBGA180 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
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128 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm
SOT459-1
c
y
X
A
105
156
157
104
ZE
e
E HE
(A 3)
A A2 A1
wM
θ
Lp
bp
L
detail X
pin 1 index
208
53
1
52
v M A
ZD
wM
bp
e
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
28.1
27.9
28.1
27.9
0.5
HD
HE
30.15 30.15
29.85 29.85
L
Lp
v
w
y
ZD
ZE
θ
1
0.75
0.45
0.12
0.08
0.08
1.43
1.08
1.43
1.08
7o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT459-1
136E30
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-02-06
03-02-20
Fig 44. Package outline of the LQFP208 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
129 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm
B
D
SOT926-1
A
ball A1
index area
A2
E
A
A1
detail X
e1
e
∅v
∅w
b
1/2 e
C
M
M
C A B
C
y
y1 C
K
J
e
H
G
F
e2
E
D
1/2 e
C
B
A
ball A1
index area
1
2
3
4
5
6
7
8
9
10
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.2
0.4
0.3
0.8
0.65
0.5
0.4
9.1
8.9
9.1
8.9
0.8
7.2
7.2
0.15
0.05
0.08
0.1
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT926-1
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
05-12-09
05-12-22
Fig 45. Package outline of the TFBGA100 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
130 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
SOT486-1
c
y
X
A
73
72
108
109
ZE
e
E HE
A A2
(A 3)
A1
θ
wM
Lp
bp
L
pin 1 index
detail X
37
144
1
36
v M A
ZD
wM
bp
e
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
20.1
19.9
20.1
19.9
0.5
HD
HE
22.15 22.15
21.85 21.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.08
0.08
Z D(1) Z E(1)
1.4
1.1
1.4
1.1
θ
7o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT486-1
136E23
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-03-14
03-02-20
Fig 46. Package outline for the LQFP144 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
131 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
c
y
X
A
51
75
50
76
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
Lp
pin 1 index
L
100
detail X
26
1
25
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
14.1
13.9
14.1
13.9
0.5
HD
HE
16.25 16.25
15.75 15.75
L
Lp
v
w
y
1
0.75
0.45
0.2
0.08
0.08
Z D (1) Z E (1)
1.15
0.85
1.15
0.85
θ
7o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT407-1
136E20
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-02-01
03-02-20
Fig 47. Package outline for the LQFP100 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
132 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
15. Soldering
Footprint information for reflow soldering of LBGA256 package
SOT740-2
Hx
P
P
Hy
see detail X
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
SL
SP
occupied area
SR
solder resist
detail X
DIMENSIONS in mm
P
SL
SP
SR
1.00
0.450
0.450
0.600
Hx
Hy
17.500 17.500
sot740-2_fr
Fig 48. Reflow soldering of the LBGA256 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
133 of 145
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32-bit ARM Cortex-M4/M0 microcontroller
Footprint information for reflow soldering of TFBGA180 package
SOT570-3
Hx
P
P
Hy
see detail X
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
SL
SP
occupied area
SR
solder resist
detail X
DIMENSIONS in mm
P
SL
SP
SR
0.80
0.400
0.400
0.550
Hx
Hy
12.575 12.575
sot570-3_fr
Fig 49. Reflow soldering of the TFBGA180 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
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134 of 145
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32-bit ARM Cortex-M4/M0 microcontroller
Footprint information for reflow soldering of LQFP208 package
SOT459-1
Hx
Gx
P2
Hy
(0.125)
P1
Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
0.500
P2
Ax
Ay
Bx
By
0.560 31.300 31.300 28.300 28.300
C
D1
D2
1.500
0.280
0.400
Gx
Gy
Hx
Hy
28.500 28.500 31.550 31.550
sot459-1_fr
Fig 50. Reflow soldering of the LQFP208 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
135 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Footprint information for reflow soldering of LQFP144 package
SOT486-1
Hx
Gx
P2
Hy
(0.125)
P1
Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
0.500
P2
Ax
Ay
Bx
By
0.560 23.300 23.300 20.300 20.300
C
D1
D2
1.500
0.280
0.400
Gx
Gy
Hx
Hy
20.500 20.500 23.550 23.550
sot486-1_fr
Fig 51. Reflow soldering of the LQFP144 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
136 of 145
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32-bit ARM Cortex-M4/M0 microcontroller
Footprint information for reflow soldering of TFBGA100 package
SOT926-1
Hx
P
P
Hy
see detail X
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
SL
SP
occupied area
SR
solder resist
detail X
DIMENSIONS in mm
P
SL
SP
SR
Hx
Hy
0.80
0.330
0.400
0.480
9.400
9.400
sot926-1_fr
Fig 52. Reflow soldering of the TFBGA100 package
LPC4350_30_20_10
Objective data sheet
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Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
137 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Footprint information for reflow soldering of LQFP100 package
SOT407-1
Hx
Gx
P2
Hy
(0.125)
P1
Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
0.500
P2
Ax
Ay
Bx
By
0.560 17.300 17.300 14.300 14.300
C
D1
D2
1.500
0.280
0.400
Gx
Gy
Hx
Hy
14.500 14.500 17.550 17.550
sot407-1
Fig 53. Reflow soldering of the LQFP100 package
LPC4350_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
138 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
16. Abbreviations
Table 29.
LPC4350_30_20_10
Objective data sheet
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
AES
Advanced Encryption Standard
AHB
Advanced High-performance Bus
APB
Advanced Peripheral Bus
API
Application Programming Interface
BOD
BrownOut Detection
CAN
Controller Area Network
CMAC
Cipher-based Message Authentication Code
CSMA/CD
Carrier Sense Multiple Access with Collision Detection
DAC
Digital-to-Analog Converter
DC-DC
Direct Current-to-Direct Current
DMA
Direct Memory Access
GPIO
General Purpose Input/Output
IRC
Internal RC
IrDA
Infrared Data Association
JTAG
Joint Test Action Group
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MAC
Media Access Control
MCU
MicroController Unit
MIIM
Media Independent Interface Management
n.c.
not connected
OHCI
Open Host Controller Interface
OTG
On-The-Go
PHY
Physical Layer
PLL
Phase-Locked Loop
PMC
Power Mode Control
PWM
Pulse Width Modulator
RIT
Repetitive Interrupt Timer
RMII
Reduced Media Independent Interface
SDRAM
Synchronous Dynamic Random Access Memory
SIMD
Single Instruction Multiple Data
SPI
Serial Peripheral Interface
SSI
Serial Synchronous Interface
SSP
Synchronous Serial Port
TCP/IP
Transmission Control Protocol/Internet Protocol
TTL
Transistor-Transistor Logic
UART
Universal Asynchronous Receiver/Transmitter
ULPI
UTMI+ Low Pin Interface
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
139 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 29.
LPC4350_30_20_10
Objective data sheet
Abbreviations …continued
Acronym
Description
USART
Universal Synchronous Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
UTMI
USB2.0 Transceiver Macrocell Interface
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
140 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
17. Revision history
Table 30.
Revision history
Document ID
Release date Data sheet status
LPC4350_30_20_10 v.2.1
20110923
Modifications:
Objective data sheet
LQFP100 package added in Table 3.
•
•
•
•
•
USART3 boot mode added in Table 5.
•
Pin description of Pin PF_9 updated: Function SGPIO7 changed to
SGPIO3.
•
•
•
•
LQFP208 package added in Table 3.
Pin P2_7 designated as ISP entry pin.
Boot pins corrected in Table 3 and Table 5: Pin P2_7 replaced by pin
P2_9 as boot pin. Pin level corrected for 4th boot pin (pin P2_9) in
Table 5.
Description of ISP mode added (Section 7.11).
VI updated for I/O pins (see Table 6).
Table 2 updated.
Pin description of Pin P2_2 updated: Function CTOUT_6 changed to
CTIN_6.
SPIFI memory added in Figure 9.
AHB multilayer matrix connections updated in Figure 8.
Pin P7_2, column LQFP144: replaced 113 by 115 in Table 3.
20110714
Objective data sheet
LPC4350_30_20_10 v.1
20101029
Objective data sheet
Objective data sheet
LPC4350_30_20_10 v.2
•
•
•
LPC4350_30_20_10 v.2
LPC4350_30_20_10
Change notice Supersedes
LPC4350_30_20_10 v.1
-
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
-
© NXP B.V. 2011. All rights reserved.
141 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
LPC4350_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
142 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
LPC4350_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
143 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
20. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 5
4.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 7
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
7
Functional description . . . . . . . . . . . . . . . . . . 65
7.1
Architectural overview . . . . . . . . . . . . . . . . . . 65
7.2
ARM Cortex-M4 processor . . . . . . . . . . . . . . . 65
7.3
ARM Cortex-M0 co-processor . . . . . . . . . . . . 65
7.4
Interprocessor communication . . . . . . . . . . . . 65
7.5
AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 66
7.6
Nested Vectored Interrupt Controller (NVIC) . 66
7.6.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.6.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 67
7.7
Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.8
Global Input Multiplexer Array (GIMA) . . . . . . 67
7.8.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.9
System Tick timer (SysTick) . . . . . . . . . . . . . . 67
7.10
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 67
7.11
In-System Programming (ISP) . . . . . . . . . . . . 68
7.12
Boot ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.13
Memory mapping . . . . . . . . . . . . . . . . . . . . . . 69
7.14
Security features. . . . . . . . . . . . . . . . . . . . . . . 72
7.14.1
AES decryption engine . . . . . . . . . . . . . . . . . . 72
7.14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.14.2
One-Time Programmable (OTP) memory . . . 72
7.15
General Purpose I/O (GPIO) . . . . . . . . . . . . . 72
7.15.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.16
Configurable digital peripherals . . . . . . . . . . . 73
7.16.1
State Configurable Timer (SCT) subsystem . . 73
7.16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.16.2
Serial GPIO (SGPIO) . . . . . . . . . . . . . . . . . . . 74
7.16.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.17
AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 74
7.17.1
General Purpose DMA (GPDMA) . . . . . . . . . . 74
7.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.17.2
SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 75
7.17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.17.3
SD/MMC card interface . . . . . . . . . . . . . . . . . 75
7.17.4
External Memory Controller (EMC). . . . . . . . . 75
7.17.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.17.5
High-speed USB Host/Device/OTG interface
(USB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.17.5.1
7.17.6
7.17.6.1
7.17.7
7.17.7.1
7.17.8
7.17.8.1
7.18
7.18.1
7.18.1.1
7.18.2
7.18.2.1
7.18.3
7.18.3.1
7.18.4
7.18.4.1
7.18.5
7.18.5.1
7.18.6
7.18.6.1
7.18.7
7.18.7.1
7.19
7.19.1
7.19.1.1
7.19.2
7.19.3
7.19.3.1
7.19.4
7.19.4.1
7.19.5
7.19.5.1
7.20
7.20.1
7.20.1.1
7.20.2
7.20.2.1
7.21
7.21.1
7.21.1.1
7.21.2
7.22
7.22.1
7.22.2
7.22.3
7.22.4
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-speed USB Host/Device interface with
ULPI (USB1) . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD controller . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital serial peripherals. . . . . . . . . . . . . . . . .
UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USART0/2/3 . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI serial I/O controller . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSP serial I/O controller. . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/timers and motor control . . . . . . . . .
General purpose 32-bit timers/external
event counters . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Motor control PWM . . . . . . . . . . . . . . . . . . . .
Quadrature Encoder Interface (QEI) . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Repetitive Interrupt (RI) timer. . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Windowed WatchDog Timer (WWDT) . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog peripherals . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC0/1) . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-Analog Converter (DAC). . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripherals in the RTC power domain . . . . . .
RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . .
System control . . . . . . . . . . . . . . . . . . . . . . . .
Configuration registers (CREG) . . . . . . . . . . .
System Control Unit (SCU) . . . . . . . . . . . . . .
Clock Generation Unit (CGU) . . . . . . . . . . . .
Internal RC oscillator (IRC) . . . . . . . . . . . . . .
76
77
77
77
77
78
78
78
78
79
79
79
79
80
80
80
80
80
81
81
81
82
82
82
82
82
83
83
83
83
83
84
84
84
84
84
84
85
85
85
85
85
85
85
86
86
continued >>
LPC4350_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
© NXP B.V. 2011. All rights reserved.
144 of 145
LPC4350/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
7.22.5
PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 86
7.22.6
PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . 86
7.22.7
System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.22.8
Reset Generation Unit (RGU). . . . . . . . . . . . . 87
7.22.9
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.23
Serial Wire Debug/JTAG. . . . . . . . . . . . . . . . . 88
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 89
9
Thermal characteristics . . . . . . . . . . . . . . . . . 90
10
Static characteristics. . . . . . . . . . . . . . . . . . . . 91
10.1
Electrical pin characteristics . . . . . . . . . . . . . . 95
10.2
Power consumption . . . . . . . . . . . . . . . . . . . . 97
11
Dynamic characteristics . . . . . . . . . . . . . . . . 101
11.1
Digital I/O and CLKOUT pins, oscillator,
PLL, and C_CAN . . . . . . . . . . . . . . . . . . . . . 101
11.2
External clock . . . . . . . . . . . . . . . . . . . . . . . . 102
11.3
IRC and RTC oscillators . . . . . . . . . . . . . . . . 104
11.4
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.5
I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 106
11.6
SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 108
11.7
USART3 IrDA . . . . . . . . . . . . . . . . . . . . . . . . 110
11.8
External memory interface . . . . . . . . . . . . . . 112
11.9
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.10
SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12
ADC/DAC electrical characteristics . . . . . . . 119
13
Application information. . . . . . . . . . . . . . . . . 122
13.1
LCD panel signal usage . . . . . . . . . . . . . . . . 122
13.2
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 124
13.3
XTAL and RTCX Printed Circuit Board
(PCB) layout guidelines . . . . . . . . . . . . . . . . 126
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . 127
15
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 139
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . 141
18
Legal information. . . . . . . . . . . . . . . . . . . . . . 142
18.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . 142
18.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
18.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 142
18.4
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 143
19
Contact information. . . . . . . . . . . . . . . . . . . . 143
20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 23 September 2011
Document identifier: LPC4350_30_20_10