PHILIPS 74AUP1T97GW

74AUP1T97
Low-power configurable gate with voltage-level translator
Rev. 01 — 25 October 2007
Product data sheet
1. General description
The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to
VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 2.3 V to 3.6 V.
The 74AUP1T97 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire VCC range.
2. Features
■ Wide supply voltage range from 2.3 V to 3.6 V
■ High noise immunity
■ ESD protection:
◆ HBM JESD22-A114E Class 3A exceeds 5000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101C exceeds 1000 V
■ Low static power consumption; ICC = 1.5 µA (maximum)
■ Latch-up performance exceeds 100 mA per JESD 78 Class II
■ Inputs accept voltages up to 3.6 V
■ Low noise overshoot and undershoot < 10 % of VCC
■ IOFF circuitry provides partial Power-down mode operation
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1T97GW
−40 °C to +125 °C
SC-88
plastic surface-mounted package; 6 leads
SOT363
74AUP1T97GM
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
74AUP1T97GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code
74AUP1T97GW
59
74AUP1T97GM
59
74AUP1T97GF
59
5. Functional diagram
A
3
4
B
C
Y
1
6
001aad998
Fig 1. Logic symbol
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
2 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
6. Pinning information
6.1 Pinning
74AUP1T97
74AUP1T97
B
1
6
B
1
6
C
GND
2
5
VCC
C
GND
2
5
VCC
A
3
4
Y
A
3
4
Y
74AUP1T97
B
1
6
C
GND
2
5
VCC
A
3
4
Y
001aag501
001aag502
Transparent top view
Transparent top view
001aag500
Fig 2. Pin configuration SOT363
(SC-88)
Fig 3. Pin configuration SOT886
(XSON6)
Fig 4. Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
B
1
data input
GND
2
ground (0 V)
A
3
data input
Y
4
data output
VCC
5
supply voltage
C
6
data input
7. Functional description
Table 4.
Function table[1]
Input
Output
C
B
A
Y
L
L
L
L
L
L
H
L
L
H
L
H
L
H
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
3 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input MUX
see Figure 5
2-input AND
see Figure 6
2-input OR with one input inverted
see Figure 7
2-input NAND with one input inverted
see Figure 7
2-input AND with one input inverted
see Figure 8
2-input NOR with one input inverted
see Figure 8
2-input OR
see Figure 9
Inverter
see Figure 10
Buffer
see Figure 11
VCC
B
1
C
6
B
Y
2
5
3
4
A
C
A
A
VCC
Y
A
Y
1
6
2
5
3
4
C
Y
C
001aae002
Fig 5. 2-input MUX
001aae003
Fig 6. 2-input AND gate
VCC
A
C
A
C
Y
Y
A
1
6
2
5
3
4
VCC
C
B
C
Y
B
C
Y
B
Y
1
6
2
5
3
4
001aae004
Fig 7. 2-input NAND gate with input A inverted or
2-input OR gate with input C inverted
C
Y
001aae005
Fig 8. 2-input NOR gate with input B inverted or
2-input AND gate with input C inverted
VCC
VCC
B
B
C
Y
1
6
2
5
3
4
C
C
2
5
3
4
C
Y
001aae007
Fig 10. Inverter
74AUP1T97_1
Product data sheet
6
Y
001aae006
Fig 9. 2-input OR gate
Y
1
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
4 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
VCC
B
B
Y
1
6
2
5
3
4
Y
001aae008
Fig 11. Buffer
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
Min
−0.5
+4.6
V
VI < 0 V
−50
-
mA
−0.5
+4.6
V
−50
-
mA
[1]
VO > VCC or VO < 0 V
Max
Unit
−0.5
+4.6
V
-
±20
mA
supply current
-
50
mA
IGND
ground current
−50
-
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
-
250
mW
VO
output voltage
Active mode and Power-down mode
IO
output current
VO = 0 V to VCC
ICC
Tamb = −40 °C to +125 °C
[1]
[2]
[1]
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SC-88 package: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 7.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
2.3
3.6
V
VI
input voltage
0
3.6
V
VO
output voltage
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
−40
+125
°C
Tamb
ambient temperature
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
5 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VT+
VT−
VH
VOH
VOL
positive-going threshold
voltage
negative-going threshold
voltage
hysteresis voltage
HIGH-level output voltage
LOW-level output voltage
II
input leakage current
VCC = 2.3 V to 2.7 V
0.60
-
1.10
V
VCC = 3.0 V to 3.6 V
0.75
-
1.16
V
VCC = 2.3 V to 2.7 V
0.35
-
0.60
V
VCC = 3.0 V to 3.6 V
0.50
-
0.85
V
VCC = 2.3 V to 2.7 V
0.23
-
0.60
V
VCC = 3.0 V to 3.6 V
0.25
-
0.56
V
IO = −20 µA; VCC = 2.3 V to 3.6 V
VCC − 0.1
-
-
V
IO = −2.3 mA; VCC = 2.3 V
2.05
-
-
V
IO = −3.1 mA; VCC = 2.3 V
1.9
-
-
V
IO = −2.7 mA; VCC = 3.0 V
2.72
-
-
V
IO = −4.0 mA; VCC = 3.0 V
2.6
-
-
V
IO = 20 µA; VCC = 2.3 V to 3.6 V
-
-
0.10
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
±0.1
µA
(VH = VT+ − VT−)
VI = VIH or VIL
VI = VIH or VIL
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
±0.1
µA
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
±0.2
µA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
1.2
µA
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
0.8
-
pF
CO
output capacitance
VO = GND; VCC = 0 V
-
1.7
-
pF
Tamb = −40 °C to +85 °C
VT+
VT−
VH
positive-going threshold
voltage
negative-going threshold
voltage
hysteresis voltage
VCC = 2.3 V to 2.7 V
0.60
-
1.10
V
VCC = 3.0 V to 3.6 V
0.75
-
1.19
V
VCC = 2.3 V to 2.7 V
0.35
-
0.60
V
VCC = 3.0 V to 3.6 V
0.50
-
0.85
V
VCC = 2.3 V to 2.7 V
0.10
-
0.60
V
VCC = 3.0 V to 3.6 V
0.15
-
0.56
V
(VH = VT+ − VT−)
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
6 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOH
VI = VIH or VIL
VOL
HIGH-level output voltage
LOW-level output voltage
Min
Typ
Max
Unit
IO = −20 µA; VCC = 2.3 V to 3.6 V
VCC − 0.1
-
-
V
IO = −2.3 mA; VCC = 2.3 V
1.97
-
-
V
IO = −3.1 mA; VCC = 2.3 V
1.85
-
-
V
IO = −2.7 mA; VCC = 3.0 V
2.67
-
-
V
IO = −4.0 mA; VCC = 3.0 V
2.55
-
-
V
IO = 20 µA; VCC = 2.3 V to 3.6 V
-
-
0.1
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
VI = VIH or VIL
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
±0.5
µA
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
±0.5
µA
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
±0.5
µA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
1.5
µA
∆ICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
[1]
-
-
4
µA
VCC = 3.0 V to 3.6 V; IO = 0 A
[2]
-
-
12
µA
VCC = 2.3 V to 2.7 V
0.60
-
1.10
V
VCC = 3.0 V to 3.6 V
0.75
-
1.19
V
VCC = 2.3 V to 2.7 V
0.33
-
0.64
V
VCC = 3.0 V to 3.6 V
0.46
-
0.85
V
VCC = 2.3 V to 2.7 V
0.10
-
0.60
V
VCC = 3.0 V to 3.6 V
0.15
-
0.56
V
Tamb = −40 °C to +125 °C
VT+
positive-going threshold
voltage
VT−
negative-going threshold
voltage
VH
VOH
VOL
II
hysteresis voltage
HIGH-level output voltage
LOW-level output voltage
input leakage current
(VH = VT+ − VT−)
VI = VIH or VIL
IO = −20 µA; VCC = 2.3 V to 3.6 V
VCC − 0.11 -
-
V
IO = −2.3 mA; VCC = 2.3 V
1.77
-
-
V
IO = −3.1 mA; VCC = 2.3 V
1.67
-
-
V
IO = −2.7 mA; VCC = 3.0 V
2.40
-
-
V
IO = −4.0 mA; VCC = 3.0 V
2.30
-
-
V
IO = 20 µA; VCC = 2.3 V to 3.6 V
-
-
0.11
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
-
-
±0.75
µA
VI = VIH or VIL
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
7 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
±0.75
µA
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
±0.75
µA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
3.5
µA
∆ICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
[1]
-
-
7
µA
VCC = 3.0 V to 3.6 V; IO = 0 A
[2]
-
-
22
µA
[1]
One input at 0.3 V or 1.1 V, other input at VCC or GND.
[2]
One input at 0.45 V or 1.2 V, other input at VCC or GND.
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
25 °C
Conditions
−40 °C to +125 °C
Min
Typ[1]
Max
Min
Max
(85 °C)
Max
(125 °C)
Unit
VCC = 2.3 V to 2.7 V; VI = 1.65 V to 1.95 V
tpd
propagation delay A, B, C to Y; see Figure 12
[2]
CL = 5 pF
2.2
3.5
5.5
0.5
6.8
7.5
ns
CL = 10 pF
2.6
4.1
6.3
1.0
7.9
8.7
ns
CL = 15 pF
2.9
4.6
6.9
1.0
8.7
9.6
ns
CL = 30 pF
3.7
5.8
8.4
1.5
10.8
11.9
ns
CL = 5 pF
1.8
3.4
5.5
0.5
6.0
6.6
ns
CL = 10 pF
2.2
4.0
6.2
1.0
7.1
7.9
ns
CL = 15 pF
2.5
4.4
6.8
1.0
7.9
8.7
ns
CL = 30 pF
3.2
5.6
8.3
1.5
10.0
11.0
ns
VCC = 2.3 V to 2.7 V; VI = 2.3 V to 2.7 V
tpd
propagation delay A, B, C to Y; see Figure 12
[2]
VCC = 2.3 V to 2.7 V; VI = 3.0 V to 3.6 V
tpd
propagation delay A, B, C to Y; see Figure 12
[2]
CL = 5 pF
1.4
3.1
5.0
0.5
5.5
6.1
ns
CL = 10 pF
1.8
3.7
5.7
1.0
6.5
7.2
ns
CL = 15 pF
2.2
4.2
6.3
1.0
7.4
8.2
ns
CL = 30 pF
2.9
5.3
7.9
1.5
9.5
10.5
ns
CL = 5 pF
2.1
2.9
3.9
0.5
8.0
8.8
ns
CL = 10 pF
2.5
3.4
4.6
1.0
8.5
9.4
ns
CL = 15 pF
2.9
3.9
5.2
1.0
9.1
10.1
ns
CL = 30 pF
3.6
5.0
6.7
1.5
9.8
10.8
ns
VCC = 3.0 V to 3.6 V; VI = 1.65 V to 1.95 V
tpd
propagation delay A, B, C to Y; see Figure 12
[2]
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
8 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
25 °C
Conditions
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
(85 °C)
Max
(125 °C)
CL = 5 pF
1.7
2.8
4.2
0.5
5.3
5.9
ns
CL = 10 pF
2.1
3.4
5.0
1.0
6.1
6.8
ns
CL = 15 pF
2.4
3.8
5.6
1.0
6.8
7.5
ns
CL = 30 pF
3.2
5.0
7.1
1.5
8.5
9.4
ns
VCC = 3.0 V to 3.6 V; VI = 2.3 V to 2.7 V
propagation delay A, B, C to Y; see Figure 12
tpd
[2]
VCC = 3.0 V to 3.6 V; VI = 3.0 V to 3.6 V
propagation delay A, B, C to Y; see Figure 12
tpd
[2]
CL = 5 pF
1.4
2.7
4.2
0.5
4.7
5.2
ns
CL = 10 pF
1.8
3.3
5.0
1.0
5.7
6.3
ns
CL = 15 pF
2.1
3.8
5.6
1.0
6.2
6.9
ns
CL = 30 pF
2.9
4.9
7.1
1.5
7.8
8.6
ns
VCC = 2.3 V to 2.7 V
-
3.6
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
4.3
-
-
-
-
pF
Tamb = 25 °C
power dissipation
capacitance
CPD
fi = 1 MHz; VI = GND to VCC
[3]
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL
[3]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
9 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
12. Waveforms
VI
A, B, C input
VM
VM
GND
t PHL
t PLH
VOH
VM
Y output
VM
VOL
t PLH
t PHL
VOH
Y output
VM
VM
VOL
001aab593
Measurement points are given in Table 10.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 12. Input A, B and C to output Y propagation delay times.
Table 10.
Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
2.3 V to 3.6 V
0.5VCC
0.5VI
1.65 V to 3.6 V
≤ 3.0 ns
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
10 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
VCC
VEXT
5 kΩ
G
VI
VO
DUT
RT
CL
RL
001aac521
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Load circuitry for switching times
Table 11.
Test data
Supply voltage
Load
VEXT
VCC
CL
RL[1]
2.3 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 kΩ or 1 MΩ
[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2 × VCC
For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
11 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
13. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
5
v M A
4
Q
pin 1
index
A
A1
1
2
e1
3
c
bp
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
SOT363
JEDEC
JEITA
SC-88
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
Fig 14. Package outline SOT363 (SC-88)
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
12 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L1
e
6
5
4
e1
e1
6×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
1.5
1.4
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE
VERSION
SOT886
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-07-15
04-07-22
MO-252
Fig 15. Package outline SOT886 (XSON6)
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
13 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
1
SOT891
b
3
2
4×
(1)
L
L1
e
6
5
4
e1
e1
6×
A
(1)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.20
0.12
1.05
0.95
1.05
0.95
0.55
0.35
0.35
0.27
0.40
0.32
Note
1. Can be visible in some manufacturing processes.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-04-06
07-05-15
SOT891
Fig 16. Package outline SOT891 (XSON6)
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
14 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
14. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP1T97_1
20071025
Product data sheet
-
-
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
15 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
74AUP1T97_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 25 October 2007
16 of 17
74AUP1T97
NXP Semiconductors
Low-power configurable gate with voltage-level translator
18. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 October 2007
Document identifier: 74AUP1T97_1