74HC258 Quad 2-input multiplexer; 3-state; inverting Rev. 04 — 14 April 2008 Product data sheet 1. General description The 74HC258 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC258 is specified in compliance with JEDEC standard no. 7A. The 74HC258 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and is controlled by a common data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the outputs (1Y to 4Y) in inverted form from the select inputs. The 74HC258 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high-impedance OFF-state when OE is HIGH. The logic equations for the outputs are: 1Y = OE × ( 1I1 × S + 1I0 × S ) 2Y = OE × ( 2I1 × S + 2I0 × S ) 3Y = OE × ( 3I1 × S + 3I0 × S ) 4Y = OE × ( 4I1 × S + 4I0 × S ) The 74HC258 is identical to the 74HC257 but has inverting outputs. 2. Features n n n n n 3-state outputs interface directly with system bus Low-power dissipation Inverting data path Complies with JEDEC standard no. 7A ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C. 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC258N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HC258D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm 74HC258DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT109-1 SOT338-1 4. Functional diagram 1 3 5 6 11 10 14 13 2 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 2 3 5 1 S SELECTOR 6 11 15 OE 10 3-STATE MULTIPLEXER OUTPUTS 14 13 2Y 7 1Y 4 3Y 9 4Y 12 15 S 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 Functional diagram 2Y 3Y 4Y 4 7 9 12 OE 001aab968 Fig 1. 1Y 001aab966 Fig 2. Logic symbol 1I0 1Y 1I1 1 15 G1 2I0 EN 2Y 2 3 1 MUX 2I1 4 1 3I0 5 7 6 3Y 3I1 11 9 10 4I0 4Y 14 12 4I1 13 001aab967 OE S Fig 3. IEC logic symbol Fig 4. 001aab969 Logic diagram 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 2 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 5. Pinning information 5.1 Pinning S 1 16 VCC 1I0 2 15 OE 1I1 3 14 4I0 1Y 4 13 4I1 258 2I0 5 12 4Y 2I1 6 11 3I0 2Y 7 10 3I1 GND 8 9 3Y 001aab904 Fig 5. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description S 1 common data select input 1I0 2 data input 1 from source 0 1I1 3 data input 1 from source 1 1Y 4 3-state multiplexer output 1; inverted 2I0 5 data input 2 from source 0 2I1 6 data input 2 from source 1 2Y 7 3-state multiplexer output 2; inverted GND 8 ground (0 V) 3Y 9 3-state multiplexer output 3; inverted 3I1 10 data input 3 from source 1 3I0 11 data input 3 from source 0 4Y 12 3-state multiplexer output 4; inverted 4I1 13 data input 4 from source 1 4I0 14 data input 4 from source 0 OE 15 output enable input (active LOW) VCC 16 positive supply voltage 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 3 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 6. Functional description Table 3. Function table[1] Control Input Output OE S nl0 nI1 nY H X X X Z L L L X H L L H X L L H X L H L H X H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +7.0 V - ±20 mA - ±20 mA - ±35 mA IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to VCC + 0.5 V ICC supply current - 70 mA IGND ground current −70 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation [1] Tamb = −40 °C to +125 °C DIP16 package [2] - 750 mW SO16 package [3] - 500 mW SSOP16 package [4] - 500 mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 °C. [3] Ptot derates linearly with 8 mW/K above 70 °C. [4] Ptot derates linearly with 5.5 mW/K above 60 °C. 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 4 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 - +125 °C ∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 ns VCC = 4.5 V - 1.67 139 ns VCC = 6.0 V - - 83 ns 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = −6 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = −7.8 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V HIGH-level input voltage LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 6 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 µA IOZ OFF-state output current VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND; IO = 0 A - - ±0.5 - ±5.0 - ±10 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8 - 80 - 160 µA CI input capacitance - 3.5 - - - - - pF 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 5 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit see Figure 8. Symbol Parameter 25 °C Conditions Min Typ Max Max (85 °C) Max (125 °C) VCC = 2.0 V - 30 95 120 145 ns VCC = 4.5 V - 11 19 24 29 ns propagation delay nl0, nI1to nY; see Figure 6 tpd −40 °C to +125 °C Unit [1] VCC = 6.0 V - 9 16 20 25 ns VCC = 5.0 V; CL = 15 pF - 9 - - - ns VCC = 2.0 V - 47 140 175 210 ns VCC = 4.5 V - 17 28 35 42 ns VCC = 6.0 V - 14 24 30 36 ns - 14 - - - ns VCC = 2.0 V - 39 140 175 210 ns VCC = 4.5 V - 14 28 35 42 ns - 11 24 30 36 ns VCC = 2.0 V - 55 150 190 225 ns VCC = 4.5 V - 20 30 38 45 ns - 16 26 33 38 ns VCC = 2.0 V - 14 60 75 90 ns VCC = 4.5 V - 5 12 15 18 ns - 4 10 13 15 ns - 55 - - - pF S to nY; see Figure 6 VCC = 5.0 V; CL = 15 pF enable time ten OE to nY; see Figure 7 [2] VCC = 6.0 V disable time tdis OE to nY; see Figure 7 [3] VCC = 6.0 V transition time tt see Figure 6 [4] VCC = 6.0 V power dissipation capacitance CPD per multiplexer; VI = GND to VCC [5] [1] tpd is the same as tPHL and tPLH. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPHZ and tPLZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 6 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 11. Waveforms VI S, nI0, nI1 input VM GND tPHL tPLH VOH nY output VM VOL tTHL tTLH 001aab970 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Input (nI0, nI1 and S) to output (nY) propagation delays and output transition times tr tf VI OE input VM GND tPLZ output LOW to OFF OFF to LOW output HIGH to OFF OFF to HIGH tPZL VCC VOH VM VX VOL tPHZ tPZH VY VM GND outputs enabled outputs disabled outputs enabled 001aab971 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Table 8. Enable and disable times Measurement points Input Output VM VM VX VY 0.5 × VCC 0.5 × VCC 0.1 × VCC 0.9 × VCC 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 7 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Table 9. Test circuit for measuring switching times Test data Supply voltage Input Load S1 VCC VI tr = tf CL RL tPZL, tPLZ tPZH, tPHZ tPHL, tPLH 2.0 V VCC 6 ns 50 pF 1 kΩ VCC GND open 4.5 V VCC 6 ns 50 pF 1 kΩ VCC GND open 6.0 V VCC 6 ns 50 pF 1 kΩ VCC GND open 5.0 V VCC 6 ns 15 pF 1 kΩ VCC GND open 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 8 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 9. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 9 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT109-1 (SO16) 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 10 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 11. Package outline SOT338-1 (SSOP16) 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 11 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC258_4 20080414 Product data sheet - 74HC258_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Pin assignment corrected for pins 10, 11, 13 and 14 in Figure 1, Figure 2, Figure 5 and Table 2. 74HC258_3 20041112 Product data sheet - 74HC_HCT258_CNV_2 74HC_HCT258_CNV_2 19990902 Product specification - 74HC_HCT258_1 74HC_HCT258_1 19901201 Product specification - - 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 12 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC258_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 April 2008 13 of 14 74HC258 NXP Semiconductors Quad 2-input multiplexer; 3-state; inverting 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 April 2008 Document identifier: 74HC258_4