DAC1405D750 Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating Rev. 4 — 7 June 2011 Product data sheet 1. General description The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 4 or 8 interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1405D750 allows the complex I and Q inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. A 4 and 8 clock multiplier enables the DAC1405D750 to provide the appropriate internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use of an external high frequency clock. The voltage regulator enables adjustment of the output full-scale current. 2. Features and benefits Dual 14-bit resolution IMD3: 74 dBc; fs = 737.28 Msps; fo = 140 MHz 750 Msps maximum update rate ACPR: 72 dBc; 2-carrier WCDMA; fs = 737.28 Msps; fo = 153.6 MHz Selectable 4 or 8 interpolation filters Typical 1.2 W power dissipation at 4 interpolation, PLL off and 740 Msps Input data rate up to 185 Msps Power-down and Sleep modes Very low noise cap-free integrated PLL Differential scalable output current from 1.6 mA to 22 mA 32-bit programmable NCO frequency On-chip 1.25 V reference Dual port or Interleaved data modes External analog offset control (10-bit auxiliary DACs) 1.8 V and 3.3 V power supplies Internal digital offset control LVDS compatible clock Inverse x / (sin x) function Two’s complement or binary offset Fully compatible SPI port data format 1.8 V/3.3 V CMOS input data buffers Industrial temperature range from 40 C to +85 C DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 3. Applications Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: LMDS/MMDS, point-to-point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE) 4. Ordering information Table 1. Ordering information Type number DAC1405D750HW DAC1405D750 Product data sheet Package Name Description Version HTQFP100 plastic thermal enhanced thin quad flat package; 100 leads; body 14 14 1 mm; exposed die pad SOT638-1 All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 2 of 42 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SDO NXP Semiconductors DAC1405D750 Product data sheet 5. Block diagram SCS_N SDIO 62 SCLK 63 65 64 10-BIT OFFSET CONTROL NCO SPI cos sin AUXILIARY DAC 2 3 AUXAP AUXAN mixer 10-BIT GAIN CONTROL DAC1405D750 + I0 to I13 14 FIR1 FIR2 FIR3 2× 2× 2× LATCH I 90 A x sin x − DAC A 91 IOUTAP IOUTAN + mixer 68 OFFSET CONTROL dual port/ interleaved data modes 41, 42, 45 to 48, 51 to 58 Q0 to Q13 FIR1 FIR2 FIR3 2× 2× 2× LATCH Q REFERENCE BANDGAP 69 CLKN + + B 14 8 9 GAPOUT mixer x sin x 86 DAC B 85 + CLKP VIRES IOUTBP IOUTBN 10-BIT GAIN CONTROL CLOCK GENERATOR/PLL mixer COMPLEX MODULATOR RESET_N 3 of 42 © NXP B.V. 2011. All rights reserved. Fig 1. Block diagram 12 13 SYNCP SYNCN 74 AUXILIARY DAC 73 AUXBP AUXBN 001aal377 DAC1405D750 66 10-BIT OFFSET CONTROL Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Rev. 4 — 7 June 2011 All information provided in this document is subject to legal disclaimers. 18 to 25, 28 to 31, 34, 35 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 6. Pinning information 77 VDDA(1V8) 76 AGND 78 AGND 79 VDDA(1V8) 80 AGND 81 VDDA(1V8) 82 AGND 83 VDDA(1V8) 84 AGND 85 IOUTBN 86 IOUTBP 87 AGND 88 n.c. 89 AGND 90 IOUTAP 91 IOUTAN 92 AGND 93 VDDA(1V8) 94 AGND 95 VDDA(1V8) 96 AGND 97 VDDA(1V8) 98 AGND 99 VDDA(1V8) 100 AGND 6.1 Pinning VDDA(3V3) 1 75 VDDA(3V3) AUXAP 2 74 AUXBP AUXAN 3 73 AUXBN AGND 4 72 AGND VDDA(1V8) 5 71 VDDA(1V8) VDDA(1V8) 6 70 VDDA(1V8) AGND 7 69 GAPOUT CLKP 8 68 VIRES CLKN 9 67 d.n.c. AGND 10 66 RESET_N VDDA(1V8) 11 65 SCS_N SYNCP 12 64 SCLK DAC1405D750HW SYNCN 13 63 SDIO TM1 14 62 SDO TM0 15 61 TM3 VDD(IO)(3V3) 16 60 VDD(IO)(3V3) GNDIO 17 59 GNDIO I13 18 58 Q0 AGND I12 19 56 Q2 I10 21 55 Q3 I9 22 54 Q4 VDDD(1V8) 50 DGND 49 Q8 48 Q9 47 Q10 46 Q11 45 VDDD(1V8) 44 DGND 43 Q12 42 Q13/SELIQ 41 VDDD(1V8) 40 DGND 39 TM2 38 DGND 37 VDDD(1V8) 36 I0 35 I1 34 DGND 33 VDDD(1V8) 32 I2 31 51 Q7 I3 30 I6 25 I4 29 52 Q6 I5 28 53 Q5 I7 24 DGND 27 I8 23 VDDD(1V8) 26 Fig 2. 57 Q1 I11 20 001aal378 Pin configuration DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 4 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 6.2 Pin description Table 2. DAC1405D750 Product data sheet Pin description Symbol Pin Type[1] Description VDDA(3V3) 1 P analog supply voltage 3.3 V AUXAP 2 O auxiliary DAC B output current AUXAN 3 O complementary auxiliary DAC B output current AGND 4 G analog ground VDDA(1V8) 5 P analog supply voltage 1.8 V VDDA(1V8) 6 P analog supply voltage 1.8 V AGND 7 G analog ground CLKP 8 I clock input CLKN 9 I complementary clock input AGND 10 G analog ground VDDA(1V8) 11 P analog supply voltage 1.8 V SYNCP 12 O synchronous clock output SYNCN 13 O complementary synchronous clock output TM1 14 I/O test mode 1 (connected to DGND) TM0 15 I/O test mode 0 (connected to DGND) VDD(IO)(3V3) 16 P input/output buffers supply voltage 3.3 V GNDIO 17 G input/output buffers ground I13 18 I I data input bit 13 (MSB) I12 19 I I data input bit 12 I11 20 I I data input bit 11 I10 21 I I data input bit 10 I9 22 I I data input bit 9 I8 23 I I data input bit 8 I7 24 I I data input bit 7 I6 25 I I data input bit 6 VDDD(1V8) 26 P digital supply voltage 1.8 V DGND 27 G digital ground I5 28 I I data input bit 5 I4 29 I I data input bit 4 I3 30 I I data input bit 3 I2 31 I I data input bit 2 VDDD(1V8) 32 P digital supply voltage 1.8 V DGND 33 G digital ground I1 34 I I data input bit 1 I0 35 I I data input bit 0 (LSB) VDDD(1V8) 36 P digital supply voltage 1.8 V DGND 37 G digital ground TM2 38 - test mode 2 (to connect to DGND) DGND 39 G digital ground All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 5 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 2. DAC1405D750 Product data sheet Pin description …continued Symbol Pin Type[1] Description VDDD(1V8) 40 P digital supply voltage 1.8 V Q13/SELIQ 41 I Q data input bit 13 (MSB)/select IQ in Interleaved mode Q12 42 I Q data input bit 12 DGND 43 G digital ground VDDD(1V8) 44 P digital supply voltage 1.8 V Q11 45 I Q data input bit 11 Q10 46 I Q data input bit 10 Q9 47 I Q data input bit 9 Q8 48 I Q data input bit 8 DGND 49 G digital ground VDDD(1V8) 50 P digital supply voltage 1.8 V Q7 51 I Q data input bit 7 Q6 52 I Q data input bit 6 Q5 53 I Q data input bit 5 Q4 54 I Q data input bit 4 Q3 55 I Q data input bit 3 Q2 56 I Q data input bit 2 Q1 57 I Q data input bit 1 Q0 58 I Q data input bit 0 (LSB) GNDIO 59 G input/output buffers ground VDD(IO)(3V3) 60 P input/output buffers supply voltage 3.3 V TM3 61 I/O test mode 3 (to connect to DGND) SDO 62 O SPI data output SDIO 63 I/O SPI data input/output SCLK 64 I SPI clock input SCS_N 65 I SPI chip select (active LOW) RESET_N 66 I general reset (active LOW) d.n.c. 67 - do not connect VIRES 68 I/O DAC biasing resistor GAPOUT 69 I/O bandgap input/output voltage VDDA(1V8) 70 P analog supply voltage 1.8 V VDDA(1V8) 71 P analog supply voltage 1.8 V AGND 72 G analog ground AUXBN 73 O auxiliary DAC B output current AUXBP 74 O complementary auxiliary DAC B output current VDDA(3V3) 75 P analog supply voltage 3.3 V AGND 76 G analog ground VDDA(1V8) 77 P analog supply voltage 1.8 V AGND 78 G analog ground VDDA(1V8) 79 P analog supply voltage 1.8 V AGND 80 G analog ground All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 6 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 2. Pin description …continued Symbol Pin Type[1] Description VDDA(1V8) 81 P analog supply voltage 1.8 V AGND 82 G analog ground VDDA(1V8) 83 P analog supply voltage 1.8 V AGND 84 G analog ground IOUTBN 85 O complementary DAC B output current IOUTBP 86 O DAC B output current AGND 87 G analog ground n.c. 88 - not connected AGND 89 G analog ground IOUTAP 90 O DAC A output current IOUTAN 91 O complementary DAC A output current AGND 92 G analog ground VDDA(1V8) 93 P analog supply voltage 1.8 V AGND 94 G analog ground VDDA(1V8) 95 P analog supply voltage 1.8 V AGND 96 G analog ground VDDA(1V8) 97 P analog supply voltage 1.8 V AGND 98 G analog ground VDDA(1V8) 99 P analog supply voltage 1.8 V AGND 100 G analog ground AGND H[2] G analog ground [1] P = power supply G = ground I = input O = output [2] DAC1405D750 Product data sheet H = heatsink (exposed die pad to be soldered) All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 7 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD(IO)(3V3) input/output supply voltage (3.3 V) Min Max Unit 0.5 +4.6 V VDDA(3V3) analog supply voltage (3.3 V) 0.5 +4.6 V VDDA(1V8) analog supply voltage (1.8 V) 0.5 +3.0 V VDDD(1V8) digital supply voltage (1.8 V) 0.5 +3.0 V VI input voltage pins CLKP, CLKN, VIRES and GAPOUT referenced to pin AGND 0.5 +3.0 V pins I13 to I0, Q13 to Q0, SDO, SDIO, SCLK, SCS_N and RESET_N referenced to GNDIO 0.5 +4.6 V pins IOUTAP, IOUTAN, IOUTBP, IOUTBN, AUXAP, AUXAN, AUXBP and AUXBN referenced to pin AGND 0.5 +4.6 V pins SYNCP and SYNCN referenced to pin AGND 0.5 +3.0 V VO output voltage Tstg storage temperature 55 +150 C Tamb ambient temperature 40 +85 C Tj junction temperature - 125 C 8. Thermal characteristics Table 4. Symbol Rth(j-a) Rth(j-c) [1] Thermal characteristics Parameter Conditions Typ Unit thermal resistance from junction to ambient [1] 19.8 K/W thermal resistance from junction to case [1] 7.7 K/W In compliance with JEDEC test board, in free air. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 8 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 9. Characteristics Table 5. Characteristics VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Test[1] Min Typ Max Unit input/output supply voltage (3.3 V) I 3.0 3.3 3.6 V VDDA(3V3) analog supply voltage (3.3 V) I 3.0 3.3 3.6 V VDDA(1V8) analog supply voltage (1.8 V) I 1.7 1.8 1.9 V VDDD(1V8) digital supply voltage (1.8 V) I 1.7 1.8 1.9 V IDD(IO)(3V3) input/output supply current (3.3 V) fo = 19 MHz; fs = 740 Msps; 4 interpolation; NCO on I - 0.5 0.7 mA IDDA(3V3) analog supply current (3.3 V) fo = 19 MHz; fs = 740 Msps; 4 interpolation; NCO on I - 44 50 mA IDDD(1V8) digital supply current (1.8 V) fo = 19 MHz; fs = 740 Msps; 4 interpolation; NCO on I - 181 210 mA IDDA(1V8) analog supply current (1.8 V) fo = 19 MHz; fs = 740 Msps; 4 interpolation; NCO on I - 360 391 mA IDDD digital supply current for x / (sin x) function only I - 70 - mA Ptot total power dissipation fo = 19 MHz; fs = 740 Msps NCO off; DAC B off C - 0.74 - W NCO off C - 0.89 - W NCO on; all VDD C - 1.12 1.32 W I - 1.11 - W I - 0.03 0.06 W DAC A and DAC B I Sleep mode; NCO on - 0.63 - W Symbol Parameter VDD(IO)(3V3) Conditions 4 interpolation 8 interpolation NCO on Power-down mode: full power-down; all VDD DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 9 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Symbol Parameter Clock inputs (CLKP and Conditions Test[1] Min Typ Max Unit CLKN)[2] Vi input voltage CLKN Vgpd < 50 mV or C CLKP [3] 825 - 1575 mV Vidth input differential threshold voltage Vgpd < 50 mV [3] 100 - +100 mV Ri input resistance D - 10 - M Ci input capacitance D - 0.5 - pF C Clock outputs (SYNCP and SYNCN) Vo(cm) common-mode output voltage C - VDDA(1V8) 0.3 V VO(dif) differential output voltage C - 1.2 - V Ro output resistance D - 80 - V Digital inputs (I0 to I13, Q0 to Q13) VIL LOW-level input voltage C GNDIO - 0.8 VIH HIGH-level input voltage C 1.6 - VDD(IO)(3V3) V IIL LOW-level input current VIL = 0.8 V I - 60 - A IIH HIGH-level input current VIH = 2.3 V I - 80 - A V Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N) VIL LOW-level input voltage C GNDIO - 1.0 VIH HIGH-level input voltage C 2.3 - VDD(IO)(3V3) V IIL LOW-level input current VIL = 1.0 V I - 20 - nA IIH HIGH-level input current VIH = 2.3 V I - 20 - nA register value = 00h C - 1.6 - mA default register C - 20 - mA compliance range C 1.8 - VDDA(3V3) V Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN) IO(fs) full-scale output current VO output voltage Ro output resistance D - 250 - k Co output capacitance D - 3 - pF EO offset error variation C - 6 - ppm/C EG gain error variation C - 18 - ppm/C I 1.2 1.25 1.30 V Reference voltage output (GAPOUT) Tamb = 25 C VO(ref) reference output voltage VO(ref) reference output voltage variation C - 117 - ppm/C IO(ref) reference output current external voltage 1.25 V D - 40 - A Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN) IO(aux) auxiliary output current differential outputs I - 2.2 - mA VO(aux) auxiliary output voltage compliance range C 0 - 2 V D - 10 - bit NDAC(aux)mono auxiliary DAC monotonicity guaranteed DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 10 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Symbol Parameter Conditions Test[1] Min Typ Max Unit Dual-port mode input C - - 185 MHz Input timing (see Figure 10) fdata data rate tw(CLK) CLK pulse width C 40 - 60 % th(i) input hold time C 1.6 - - ns tsu(i) input set-up time C 0.8 - - ns fSYNC = fs / 4 C - 0.21 - ns fSYNC = fs / 8 C - 0.3 - ns variation C - 0.27 - ps/C C - - 750 Msps D - 20 - ns 00000000h D - 0 - MHz FFFFFFFFh D - 740 - MHz D - 0.172 - Hz 00000000h D - 0 - MHz F8000000h D - 716.875 - MHz D - 23.125 - MHz - 77 - dBc SYNC signal td delay time Output timing fs sampling frequency ts settling time to 0.5 LSB NCO frequency range fNCO fstep NCO frequency register values step frequency Low-power NCO frequency range fNCO fstep NCO frequency register values step frequency Dynamic performance SFDR spurious-free dynamic range fs = 737.28 Msps fdata = 92.16 MHz; B = fdata / 2 fo = 4 MHz; 0 dBFS C fdata = 184.32 MHz; B = fdata / 2 SFDRRBW restricted bandwidth spurious-free dynamic range DAC1405D750 Product data sheet fo = 19 MHz; 0 dBFS I - 74 - dBc fo = 70 MHz; 0 dBFS C - 86 - dBc fo = 153.6 MHz; 0 dBFS; fdata = 184.32 MHz; fs = 737.28 Msps B = 20 MHz C - 86 B = 100 MHz C - 80.5 - dBc B = 20 MHz; 8-tone; 500 kHz spacing C - 76 - dBc All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 - dBc © NXP B.V. 2011. All rights reserved. 11 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Symbol Parameter IMD3 third-order intermodulation distortion ACPR adjacent channel power ratio Conditions Test[1] Min Typ Max Unit fdata = 184.32 MHz; fs = 737.28 Msps fo1 = 95 MHz; fo2 = 97 MHz C [4] - 77 - dBc fo1 = 137 MHz; fo2 = 143 MHz C [4] - 74 - dBc fo1 = 152.5 MHz; fo2 = 153.5 MHz I [4] - 74 - dBc fdata = 184.32 MHz; fs = 737.28 Msps; fo = 96 MHz 1-carrier; B = 5 MHz I - 75 - dBc 2-carrier; B = 10 MHz C - 72 - dBc 4-carrier; B = 20 MHz C - 68.5 - dBc fdata = 184.32 MHz; fs = 737.28 Msps; fo = 153.6 MHz NSD 1-carrier; B = 5 MHz C - 73 - dBc 2-carrier; B = 10 MHz C - 71 - dBc 4-carrier; B = 20 MHz C - 67 - dBc noise spectral density fdata = 184.32 MHz; fs = 737.28 Msps fo = 19 MHz; 0 dBFS C - 161 - dBFS/Hz fo = 153.6 MHz; 0 dBFS; C - 156 - dBFS/Hz fo = 153.6 MHz; 10 dBFS C - 158 - dBFS/Hz [1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. [2] CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 and 120 should be connected across the pins (see Figure 8). [3] Vgpd represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance and the inductance between the receiver and the driver circuit ground voltages. [4] IMD3 rejection with 6 dBFS/tone. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 12 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10. Application information 10.1 General description The DAC1405D750 is a dual 14-bit DAC which operates at up to 750 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC. The input data rate of up to 185 MHz combined with the maximum output sampling rate of 750 Msps make the DAC1405D750 extremely flexible in wide bandwidth and multi-carrier systems. The device’s quadrature modulator and 32-bit NCO simplifies system frequency selection. This is also possible because the 4 and 8 interpolation filters remove undesired images. A SYNC signal is provided to synchronize data when the PLL is in the off state. Two modes are available for the digital input. In Dual-port mode, each DAC uses its own data input line. In Interleaved mode, both DACs use the same data input line. The on-chip PLL enables generation of the internal clock signals for the digital circuitry and the DAC from a low speed clock. The PLL can be bypassed enabling the use of an external, high-speed clock. Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN. This provides a full-scale output current (IO(fs)) up to 22 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. There are also some embedded features to provide an analog offset correction (auxiliary DACs) and digital offset control as well as for gain adjustment. All the functions can be set using the SPI. The DAC1405D750 operates at both 3.3 V and 1.8 V each of which has separate digital and analog power supplies. The digital input is 1.8 V and 3.3 V compliant and the clock input is LVDS compliant. 10.2 Serial peripheral interface 10.2.1 Protocol description The DAC1405D750 Serial Peripheral Interface (SPI) is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both write and read modes. This interface can be configured as a 3-wire type (SDIO as a bidirectional pin) or a 4-wire type (SDIO and SDO as unidirectional pins, input and output port respectively). In both configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select bar. Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW assertion to drive the chip with 1 to 4 bytes, depending on the content of the instruction byte (see Table 7). DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 13 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating RESET_N SCS_N SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 SDO (optional) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 001aaj812 R/W indicates the mode access, (see Table 6) Fig 3. SPI protocol Table 6. Read or Write mode access description R/W Description 0 Write mode operation 1 Read mode operation In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte. Table 7. Number of bytes transferred N1 N0 Number of bytes 0 0 1 byte transferred 0 1 2 bytes transferred 1 0 3 bytes transferred 1 1 4 bytes transferred A0 to A4: indicate which register is being addressed. In the case of a multiple transfer, this address concerns the first register after which the next registers follow directly in a decreasing order according to Table 9 “Register allocation map”. 10.2.2 SPI timing description The interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in Figure 4. tw(RESET_N) RESET_N 50 % th(SCS_N) tsu(SCS_N) SCS_N 50 % tw(SCLK) SCLK SDIO 50 % 50 % th(SDIO) tsu(SDIO) Fig 4. DAC1405D750 Product data sheet 001aaj813 SPI timing diagram All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 14 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating The SPI timing characteristics are given in Table 8. Table 8. SPI timing characteristics Symbol Parameter Min Typ Max Unit fSCLK SCLK frequency - - 15 MHz tw(SCLK) SCLK pulse width 30 - - ns tsu(SCS_N) SCS_N set-up time 20 - - ns th(SCS_N) SCS_N hold time 20 - - ns tsu(SDIO) SDIO set-up time 10 - - ns th(SDIO) SDIO hold time 5 - - ns tw(RESET_N) RESET_N pulse width 30 - - ns 10.2.3 Detailed descriptions of registers An overview of the details for all registers is provided in Table 9. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 15 of 42 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Address NXP Semiconductors DAC1405D750 Product data sheet Table 9. Register allocation map Register name R/W Bit definition Dec Hex Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Dec Hex 0 00h COMMon R/W 3W_SPI SPI_RST CLK_SEL - MODE_ SEL CODING IC_PD GAP_PD 10000000 128 80 1 01h TXCFG R/W NCO_ON NCO_LP_ SEL INV_SIN_ SEL INTERPOLATION[1:0] 10000111 135 87 2 02h PLLCFG R/W PLL_PD - PLL_DIV_ PD 3 03h FREQNCO_LSB R/W MODULATION[2:0] PLL_DIV[1:0] DAC_CLK_DELAY[1:0] DAC_CLK 00010000 _POL 16 10 FREQ_NCO[7:0] 01100110 102 66 04h FREQNCO_LISB R/W FREQ_NCO[15:8] 01100110 102 66 05h FREQNCO_UISB R/W FREQ_NCO[23:16] 01100110 102 66 6 06h FREQNCO_MSB R/W FREQ_NCO[31:24] 00100110 38 26 7 07h PHINCO_LSB R/W PH_NCO[7:0] 00000000 0 00 PH_NCO[15:8] 08h PHINCO_MSB R/W 9 09h DAC_A_Cfg_1 R/W DAC_A_PD 00000000 0 00 DAC_A_OFFSET[5:0] 00000000 0 00 10 0Ah DAC_A_Cfg_2 R/W DAC_A_GAIN_ COARSE[1:0] DAC_A_GAIN_FINE[5:0] 01000000 64 40 11 0Bh DAC_A_Cfg_3 R/W DAC_A_GAIN_ COARSE[3:2] DAC_A_OFFSET[11:6] 11000000 192 C0 12 0Ch DAC_B_Cfg_1 R/W DAC_B_PD DAC_B_OFFSET[5:0] 00000000 0 00 13 0Dh DAC_B_Cfg_2 R/W DAC_B_GAIN_ COARSE[1:0] DAC_B_GAIN_FINE[5:0] 01000000 64 40 14 0Eh DAC_B_Cfg_3 R/W DAC_B_GAIN_ COARSE[3:2] DAC_B_OFFSET[11:6] 11000000 192 C0 15 0Fh DAC_Cfg R/W 00000000 0 00 16 10h SYNC_Cfg R/W SYNC_DIV 00000000 0 00 DAC_A_ SLEEP DAC_B_ SLEEP - MINUS_ 3DB SYNC_SEL NOISE_ SHPER - 16 of 42 © NXP B.V. 2011. All rights reserved. 26 1Ah DAC_A_Aux_MSB R/W AUX_A[9:2] 27 1Bh DAC_A_Aux_LSB R/W AUX_A_PD - 28 1Ch DAC_B_Aux_MSB R/W AUX_B[9:2] 29 1Dh DAC_B_Aux_LSB R/W AUX_B_PD - AUX_A[1:0] AUX_B[1:0] 10000000 128 80 00000000 0 10000000 128 80 00000000 0 00 00 DAC1405D750 8 Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Rev. 4 — 7 June 2011 All information provided in this document is subject to legal disclaimers. 4 5 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.2.4 Detailed register descriptions Please refer to Table 9 for the register overview and relevant default values. In the following tables, all the values shown in bold are the default values. Table 10. COMMon register (address 00h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 3W_SPI R/W serial interface bus type 0 1 6 5 SPI_RST CLK_SEL R/W - - 3 MODE_SEL R/W 2 1 0 CODING 0 no reset 1 performs a reset on all registers except 00h data input latch 0 at CLK rising edge 1 at CLK falling edge - input data mode dual port 1 interleaved coding 0 binary 1 two’s compliment R/W GAP_PD reserved 0 R/W IC_PD 3 wire SPI serial interface reset R/W 4 4 wire SPI power-down 0 disabled 1 all circuits (digital and analog, except SPI) are switched off R/W internal bandgap power-down 0 power-down disabled 1 internal bandgap references are switched off Table 11. TXCFG register (address 01h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 NCO_ON R/W 6 5 DAC1405D750 Product data sheet NCO_LP_SEL INV_SIN_SEL NCO 0 disabled (the NCO phase is reset to 0) 1 enabled R/W low-power NCO 0 disabled 1 NCO frequency and phase given by the five MSBs of the registers 06h and 08h respectively R/W x / (sin x) function 0 disabled 1 enabled All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 17 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 11. TXCFG register (address 01h) bit description …continued Default settings are shown highlighted. Bit Symbol Access Value Description 4 to 2 MODULATION[2:0] 1 to 0 INTERPOLATION[1:0] R/W modulation 000 dual DAC: no modulation 001 positive upper single sideband up-conversion 010 positive lower single sideband up-conversion 011 negative upper single sideband up-conversion 100 negative lower single sideband up-conversion R/W interpolation 01 reserved 10 4 11 8 Table 12. PLLCFG register (address 02h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 PLL_PD R/W PLL ON 6 - - 5 PLL_DIV_PD R/W 4 to 3 PLL_DIV[1:0] 0 switched on 1 switched off reserved PLL divider switched on X 1 switched off X R/W PLL divider factor 2 130 ps 01 4 280 ps 10 8 430 ps Table 13. DAC1405D750 Product data sheet X phase shift (fs) DAC_CLK_DELAY[1:0] R/W DAC_CLK_POL Digital clock delay 00 580 ps undefined 00 0 X 01 120 X 10 0 undefined 0 11 2 to 1 PLL OFF PLL 240 clock edge of DAC (fs) R/W X undefined 0 normal X 1 inverted X FREQNCO_LSB register (address 03h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[7:0] R/W - lower 8 bits for the NCO frequency setting All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 18 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 14. FREQNCO_LISB register (address 04h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[15:8] R/W Table 15. - lower intermediate 8 bits for the NCO frequency setting FREQNCO_UISB register (address 05h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[23:16] R/W Table 16. - upper intermediate 8 bits for the NCO frequency setting FREQNCO_MSB register (address 06h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[31:24] R/W Table 17. - most significant 8 bits for the NCO frequency setting PHINCO_LSB register (address 07h) bit description Bit Symbol Access Value Description 7 to 0 PH_NCO[7:0] R/W Table 18. - lower 8 bits for the NCO phase setting PHINCO_MSB register (address 08h) bit description Bit Symbol Access Value Description 7 to 0 PH_NCO[15:8] R/W - most significant 8 bits for the NCO phase setting Table 19. DAC_A_Cfg_1 register (address 09h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 DAC_A_PD R/W 6 DAC_A_SLEEP DAC A power 0 on 1 off R/W DAC A Sleep mode 0 1 5 to 0 DAC_A_OFFSET[5:0] Table 20. DAC1405D750 Product data sheet R/W - disabled enabled lower 6 bits for the DAC A offset DAC_A_Cfg_2 register (address 0Ah) bit description Bit Symbol Access Value Description 7 to 6 DAC_A_GAIN_ COARSE[1:0] R/W - lower 2 bits for the DAC A gain setting for coarse adjustment 5 to 0 DAC_A_GAIN_ FINE[5:0] R/W - lower 6 bits for the DAC A gain setting for fine adjustment All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 19 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 21. DAC_A_Cfg_3 register (address 0Bh) bit description Bit Symbol Access Value Description 7 to 6 DAC_A_GAIN_ COARSE[3:2] R/W - most significant 2 bits for the DAC A gain setting for coarse adjustment 5 to 0 DAC_A_ OFFSET[11:6] R/W - most significant 6 bits for the DAC A offset Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 DAC_B_PD R/W DAC B power 0 on 1 6 5 to 0 DAC_B_SLEEP DAC_B_OFFSET[5:0] Table 23. off R/W R/W DAC B Sleep mode 0 disabled 1 enabled - lower 6 bits for the DAC B offset DAC_B_Cfg_2 register (address 0Dh) bit description Bit Symbol Access Value Description 7 to 6 DAC_B_GAIN_ COARSE[1:0] R/W - less significant 2 bits for the DAC B gain setting for coarse adjustment 5 to 0 DAC_B_GAIN_ FINE[5:0] R/W - the 6 bits for the DAC B gain setting for fine adjustment Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description Bit Symbol Access Value Description 7 to 6 DAC_B_GAIN_ COARSE[3:2] R/W - most significant 2 bits for the DAC B gain setting for coarse adjustment 5 to 0 DAC_B_ OFFSET[11:6] R/W - most significant 6 bits for the DAC B offset Table 25. DAC_Cfg register (address 0Fh) bit description Default settings are shown highlighted. Bit Product data sheet Access Value 7 to 2 - - 1 R/W 0 DAC1405D750 Symbol MINUS_3DB NOISE_SHPER - Description reserved NCO gain 0 unity 1 3 dB R/W noise shaper 0 disabled 1 enabled All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 20 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 26. SYNC_Cfg register (address 10h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 SYNC_DIV R/W fs divided by 6 SYNC_SEL 5 to 0 - Bit 4 1 8 R/W SYNC selection - Table 27. 0 0 disabled 1 enabled - reserved DAC_A_Aux_MSB register (address 1Ah) bit description Symbol 7 to 0 AUX_A[9:2] Access Value Description R/W most significant 8 bits for the auxiliary DAC A - Table 28. DAC_A_Aux_LSB register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 AUX_A_PD R/W auxiliary DAC A power 6 to 1 - - 1 to 0 AUX_A[1:0] R/W Table 29. Bit 0 on 1 off - reserved lower 2 bits for the auxiliary DAC A DAC_B_Aux_MSB register (address 1Ch) bit description Symbol 7 to 0 AUX_B[9:2] Access Value Description R/W most significant 8 bits for the auxiliary DAC B - Table 30. DAC_B_Aux_LSB register (address 1Dh) bit description Default settings are shown highlighted. DAC1405D750 Product data sheet Bit Symbol Access Value Description 7 AUX_B_PD R/W auxiliary DAC B power 6 to 1 - - 1 to 0 AUX_B[1:0] R/W 0 on 1 off - All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 reserved lower 2-bits for the auxiliary DAC B © NXP B.V. 2011. All rights reserved. 21 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.2.5 Recommended configuration It is recommended that the following additional settings are used to obtain optimum performance at up to 750 Msps. Table 31. Recommended configuration Address Value Dec Hex Bin Dec Hex 17 11h 00001010 10 0Ah 19 13h 01101100 108 6Ch 20 14h 01101100 108 6Ch 10.3 Input data The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) defines whether the DAC1405D750 operates in the Dual-port mode or in Interleaved mode (see Table 32). Table 32. Mode selection Bit 3 setting Function I13 to I0 Q13 to Q0 Pin 41 0 Dual port mode active active Q13 1 Interleaved mode active off SELIQ 10.3.1 Dual-port mode The data input for Dual-port mode operation is shown in Figure 5 “Dual-port mode”. Each DAC has its own independent data input. The data enters the input latch on the rising edge of the internal clock signal and is transferred to the DAC latch. FIR 1 I13 to I0 LATCH I Q13 to Q0 LATCH Q 2× FIR 1 2× FIR 2 2× FIR 2 2× FIR 3 2× FIR 3 2× 001aal653 Fig 5. Dual-port mode 10.3.2 Interleaved mode The data input for the Interleaved mode operation is illustrated in Figure 6. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 22 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating FIR 1 LATCH I FIR 2 2× FIR 3 2× 2× I13 to I0 FIR 1 LATCH Q Q13/SELIQ FIR 2 2× FIR 3 2× 2× 001aal654 Fig 6. Interleaved mode operation In Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch I or latch Q, depending on the SELIQ signal. The SELIQ input (pin 41) allows the synchronization of the internally demultiplexed I and Q channels; see Figure 7. In N N+1 N+2 N+3 N+4 N+5 SELIQ (synchronous alternative) SELIQ (asynchronous alternative 1) SELIQ (asynchronous alternative 2) CLKdig Latch I output XX N N+2 Latch Q output XX N+1 N+3 001aaj814 CLKdig = internal digital clock Fig 7. Interleaved mode timing (8x interpolation, latch on rising edge) The SELIQ signal can be either synchronous or asynchronous (single rising edge, single pulse). The first data following the SELIQ rising edge is sent in channel I and following data is sent in channel Q. After this, data is distributed alternately between these channels. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 23 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.4 Input clock The DAC1405D750 can operate at the following clock frequencies: PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode PLL off: up to 750 MHz The input clock is LVDS compliant (see Figure 8) but it can also be interfaced with CML differential sine wave signal (see Figure 9). CLKINP LVDS LVDS Zdiff = 100 Ω 100 Ω CLKINN 001aah021 Fig 8. LVDS clock configuration VDDA(1V8) 1.1 kΩ 100 nF CLKINP 55 Ω CML Zdiff = 100 Ω LVDS 1 kΩ 55 Ω 100 nF CLKINN 2.2 kΩ AGND Fig 9. 100 nF 001aah020 Interfacing CML to LVDS 10.5 Timing The DAC1405D750 can operate at a sampling frequency (fs) up to 750 Msps with an input data rate (fdata) up to 185 MHz. When using the internal PLL, the input data is referenced to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a reference. The input timing in the second case is shown in Figure 10. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 24 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating tsu(i) I13 to I0/ Q13 to Q0 90 % SYNC (SYNCP − SYNCN) th(i) 90 % N N+1 N+2 50 % 001aal384 Fig 10. Input timing diagram when internal PLL bypassed (off) 10.5.1 Timing when using the internal PLL (PLL on) In Table 33 the links between internal and external clocking are defined. The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 9 “Register allocation map”) allows the frequency between the digital part and the DAC core to be adjusted. Table 33. Frequencies Mode CLK input Input data rate (MHz) (MHz) Interpolation Update rate (Msps) PLL_DIV[1:0] Dual Port 185 185 4 740 01 (/ 4) Dual Port 92.5 92.5 8 740 10 (/ 8) Interleaved 370 370 4 740 00 (/ 2) Interleaved 185 185 8 740 01 (/ 4) The settings applied to DAC_CLK_DELAY[1:0] (register 02h[2:1]) and DAC_CLK_POL (register 02h[0]), allow adjustment of the phase and polarity of the sampling clock. This occurs at the input of the DAC core and depends mainly on the sampling frequency. Some examples are given in Table 34. Table 34. Sample clock phase and polarity examples Mode Input data rate (MHz) Interpolation Update rate (Msps) DAC_CLK_ DELAY [1:0] DAC_CLK_ POL Dual Port 92.5 4 370 01 0 Dual Port 92.5 8 740 01 0 10.5.2 Timing when using an external PLL (PLL off) It is recommended that a delay of 280 ps is used on the internal digital clock (CLKdig) to obtain optimum device performance up to750 Msps. Table 35. Optimum external PLL timing settings Address Register name Dec Hex 2 02h PLLCFG Value Digital clock delay Bin Dec Hex 280 ps 136 88h 10001000 10.6 FIR filters The DAC1405D750 integrates three selectable Finite Impulse Response (FIR) filters which enables the device to use 4 or 8 interpolation rates. All three interpolation filters have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than 0.0005 dB. The coefficients of the interpolation filters are given in Table 36. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 25 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 36. Interpolation filter coefficients First interpolation filter Second interpolation filter Third interpolation filter Lower Upper Lower Lower Upper H(1) H(55) 4 H(1) H(23) 2 H(1) H(15) 39 H(2) H(54) 0 H(2) H(22) 0 H(2) H(14) 0 H(3) H(53) 13 H(3) H(21) 17 H(3) H(13) 273 H(4) H(52) 0 H(4) H(20) 0 H(4) H(12) 0 H(5) H(51) 34 H(5) H(19) 75 H(5) H(11) 1102 H(6) H(50) 0 H(6) H(18) 0 H(6) H(10) 0 H(7) H(49) 72 H(7) H(17) 238 H(7) H(9) 4964 H(8) H(48) 0 H(8) H(16) 0 H(8) - 8192 Value Upper Value Value H(9) H(47) 138 H(9) H(15) 660 - - - H(10) H(46) 0 H(10) H(14) 0 - - - H(11) H(45) 245 H(11) H(13) 2530 - - - H(12) H(44) 0 H(12) - 4096 - - - H(13) H(43) 408 - - - - - - H(14) H(42) 0 - - - - - - H(15) H(41) 650 - - - - - - H(16) H(40) 0 - - - - - - H(17) H(39) 1003 - - - - - - H(18) H(38) 0 - - - - - - H(19) H(37) 1521 - - - - - - H(20) H(36) 0 - - - - - - H(21) H(35) 2315 - - - - - - H(22) H(34) 0 - - - - - - H(23) H(33) 3671 - - - - - - H(24) H(32) 0 - - - - - - H(25) H(31) 6642 - - - - - - H(26) H(30) 0 - - - - - - H(27) H(29) 20756 - - - - - - H(28) - 32768 - - - - - - 10.7 Quadrature modulator and Numerically Controlled Oscillator (NCO) The quadrature modulator allows the 14-bit I and Q-data to be mixed with the carrier signal generated by the NCO. The frequency of the Numerically Controlled Oscillator (NCO) is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 26 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.7.1 NCO in 32-bit When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: M fs f NCO = -------------32 2 (1) where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and PHINCO_MSB over 16 bits. 10.7.2 Low-power NCO When using the low-power NCO, the frequency can be set by the 5 MSB of register FREQNCO_MSB. The frequency for the low-power NCO is calculated as follows: M fs f NCO = -------------5 2 (2) where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB. 10.7.3 Minus_3dB function During normal use, a full-scale pattern will also be full scale at the output of the DAC. Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping can occur and the Minus_3dB function can be used to reduce the gain by 3 dB in the modulator. This is to keep a full-scale range at the output of the DAC without added interferers. 10.8 x / (sin x) Due to the roll-off effect of the DAC, a selectable FIR filter is inserted to compensate for the x / (sin x) effect. This filter introduces a DC loss of 3.4 dB. The coefficients are represented in Table 37. Table 37. Inversion filter coefficients First interpolation filter DAC1405D750 Product data sheet Lower Upper Value H(1) H(9) 2 H(2) H(8) 4 H(3) H(7) 10 H(4) H(6) 35 H(5) - 401 All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 27 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.9 DAC transfer function The full-scale output current for each DAC is the sum of the two complementary current outputs: (3) I O fs = I IOUTP + I IOUTN The output current depends on the digital input data: DATA I IOUTP = I O fs ---------------- 16383 (4) 16383 – DATA I IOUTN = I O fs ------------------------------------- 16383 (5) The setting applied to CODING (register 00h[2]; see Table 9 “Register allocation map”) defines whether the DAC1405D750 operates with a binary input or a two’s complement input. Table 38 shows the output current as a function of the input data, when IO(fs) = 20 mA. Table 38. Data DAC transfer function I13 to I0 and Q13 to Q0 IOUTP (mA) IOUTN (mA) 10 0000 0000 0000 0 20 ... ... ... ... 8192 10 0000 0000 0000 00 0000 0000 0000 10 10 ... ... ... ... ... 16383 11 1111 1111 1111 01 1111 1111 1111 20 0 Binary Two’s complement 0 00 0000 0000 0000 ... 10.10 Full-scale current 10.10.1 Regulation The DAC1405D750 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 V reference to the GAPOUT pin. It is recommended to decouple pin GAPOUT using a 100 nF capacitor. The reference current is generated via an external resistor of 910 (1 %) connected to pin VIRES. A control amplifier sets the appropriate full-scale output current (IO(fs)) for both DACs (see Figure 11). DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 28 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating REF. BANDGAP 100 nF AGND 909 Ω (1 %) AGND GAPOUT VIRES DAC CURRENT SOURCES ARRAY 001aaj816 Fig 11. Internal reference configuration This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. The DAC current can also be set by applying an external reference voltage to the non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage with GAP_PD (register 00h[0]; see Table 10 “COMMon register (address 00h) bit description”). 10.10.2 Full-scale current adjustment The default full-scale current (IO(fs)) is 20 mA but further adjustments can be made by the user to both DACs independently via the serial interface from 1.6 mA to 22 mA, 10 %. The settings applied to DAC_A_GAIN_COARSE[3:0] (see Table 20 “DAC_A_Cfg_2 register (address 0Ah) bit description” and Table 21 “DAC_A_Cfg_3 register (address 0Bh) bit description”) and to DAC_B_GAIN COARSE[3:0] (see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit description” and Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit description”) define the coarse variation of the full-scale current (see Table 39). Table 39. IO(fs) coarse adjustment Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] DAC1405D750 Product data sheet IO(fs) (mA) Decimal Binary 0 0000 1.6 1 0001 3.0 2 0010 4.4 3 0011 5.8 4 0100 7.2 5 0101 8.6 6 0110 10.0 7 0111 11.4 8 1000 12.8 9 1001 14.2 10 1010 15.6 11 1011 17.0 12 1100 18.5 All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 29 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 39. IO(fs) coarse adjustment …continued Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] IO(fs) (mA) Decimal Binary 13 1101 20.0 14 1110 21.0 15 1111 22.0 The settings applied to DAC_A_GAIN_FINE[5:0] (see Table 20 “DAC_A_Cfg_2 register (address 0Ah) bit description”) and to DAC_B_GAIN_FINE[5:0] (see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit description”) define the fine variation of the full-scale current (see Table 40). Table 40. IO(fs) fine adjustment Default settings are shown highlighted. DAC_GAIN_FINE[5:0] Delta IO(fs) Decimal Two’s complement 32 10 0000 10.3 % ... ... ... 0 00 0000 0 ... ... ... 31 01 1111 +10 % The coding of the fine gain adjustment is two’s complement. 10.11 Digital offset adjustment When the DAC1405D750 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common-mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. The settings applied to DAC_A_OFFSET[11:0] (see Table 19 “DAC_A_Cfg_1 register (address 09h) bit description” and Table 21 “DAC_A_Cfg_3 register (address 0Bh) bit description”) and to “DAC_B_OFFSET[11:0]” (see Table 22 “DAC_B_Cfg_1 register (address 0Ch) bit description” and Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit description”) define the range of variation of the digital offset (see Table 41). DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 30 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 41. Digital offset adjustment Default settings are shown highlighted. DAC_OFFSET[11:0] Offset applied Decimal Two’s complement 2048 1000 0000 0000 4096 2047 1000 0000 0001 4094 ... ... ... 1 1111 1111 1111 2 0 0000 0000 0000 0 +1 0000 0000 0001 +2 ... ... ... +2046 0111 1111 1110 +4092 +2047 0111 1111 1111 +4094 10.12 Analog output The DAC1405D750 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN, respectively and need to be connected via a load resistor RL to the 3.3 V analog power supply (VDDA(3V3)). Refer to Figure 12 for the equivalent analog output circuit of one DAC. This circuit consists of a parallel combination of NMOS current sources, and their associated switches, for each segment. VDDA(3V3) RL RL IOUTAP/IOUTBP IOUTAN/IOUTBN AGND AGND 001aah019 Fig 12. Equivalent analog output circuit (one DAC) The cascode source configuration increases the output impedance of the source, thus improving the dynamic performance of the DAC by introducing less distortion. The device can provide an output level of up to 2 Vo(p-p) depending on the application, the following stages and the targeted performances. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 31 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.13 Auxiliary DACs The DAC1405D750 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground). (6) I O AUX = I AUXP + I AUXN The output current depends on the auxiliary DAC data: AUX 9:0 AUXP = I O AUX ------------------------- 1023 (7) (1023 – A UX 9:0 AUXN = I O AUX --------------------------------------------- 1023 (8) Table 42 shows the output current as a function of the auxiliary DAC data. Table 42. Auxiliary DAC transfer function Default settings are shown highlighted. Data AUX[9:0] (binary) IAUXP (mA) IAUXN (mA) 0 00 0000 0000 0 2.2 ... ... ... ... 512 10 0000 0000 1.1 1.1 ... ... ... ... 1023 11 1111 1111 2.2 0 10.14 Output configuration 10.14.1 Basic output configuration The use of a differentially-coupled transformer output provides optimum distortion performance (see Figure 13). In addition, it helps to match the impedance and provides electrical isolation. VDDA(3V3) 0 mA to 20 mA 50 Ω 2:1 IOUTnP 50 Ω 0 mA to 20 mA IOUTnN 50 Ω VDDA(3V3) IOUTnP/IOUTnN; Vo(cm) = 2.8 V; Vo(dif)(p-p) = 1 V 001aaj817 Fig 13. 1 Vo(p-p) differential output with transformer DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 32 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating The DAC1405D750 differential outputs can operate up to 2 Vo(p-p). In this configuration, it is recommended to connect the center tap of the transformer to a 62 resistor connected to the 3.3 V analog power supply, in order to adjust the DC common-mode to approximately 2.7 V (see Figure 14). VDDA(3V3) VDDA(3V3) 100 Ω 62 Ω 0 mA to 20 mA 4:1 IOUTnP 50 Ω 0 mA to 20 mA IOUTnN 100 Ω VDDA(3V3) IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V 001aaj818 Fig 14. 2 Vo(p-p) differential output with transformer 10.14.2 DC interface to an Analog Quadrature Modulator (AQM) When the system operation requires to keep the DC component of the spectrum, the DAC1405D750 can use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. Figure 15 provides an example of a connection to an AQM with a 1.7 VI(cm) common-mode input level. AQM (Vi(cm) = 1.7 V) VDDA(3V3) 51.1 Ω (1) 51.1 Ω (2) 442 Ω IOUTnP BBP 442 Ω BBN IOUTnN 0 mA to 20 mA 768 Ω 768 Ω (1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V 001aaj541 Fig 15. An example of a DC interface to a 1.7 VI(cm) AQM Figure 16 provides an example of a connection to an AQM with a 3.3 VI(cm) common-mode input level. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 33 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating VDDA(3V3) (1) 54.9 Ω 5V 54.9 Ω 750 Ω AQM (Vi(cm) = 3.3 V) (2) 750 Ω 237 Ω IOUTnP BBP 237 Ω IOUTnN BBN 1.27 kΩ 1.27 kΩ (1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.97 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V 001aaj542 Fig 16. An example of a DC interface to a 3.3 VI(cm) AQM The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Figure 17 provides an example of a DC interface with the auxiliary DACs to an AQM with a 1.7 VI(cm) common-mode input level. VDDA(3V3) 51.1 Ω (1) AQM (Vi(cm) = 1.7 V) 51.1 Ω (2) 442 Ω IOUTnP BBP 442 Ω IOUTnN BBN 0 mA to 20 mA 698 Ω 698 Ω 51.1 Ω 51.1 Ω AUXnP AUXnN 1.1 mA (typ.) (1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.94 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.23 V; offset correction up to 50 mV 001aal655 Fig 17. An example of a DC interface to a 1.7 VI(cm) AQM using auxiliary DACs Figure 18 provides an example of a DC interface with the auxiliary DACs to an AQM with a 3.3 VI(cm) common-mode input level. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 34 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 3.3 V 54.9 Ω (1) AQM (Vi(cm) = 3.3 V) 5V 54.9 Ω 750 Ω 750 Ω (2) 237 Ω IOUTnP BBP 237 Ω IOUTnN BBN 634 Ω 634 Ω 442 Ω 442 Ω AUXnP AUXnN (1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V; offset correction up to 36 mV 001aaj544 Fig 18. An example of a DC interface to a 3.3 VI(cm) AQM using auxiliary DACs The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common-mode level of the AQM, and the range of offset correction. 10.14.3 AC interface to an Analog Quadrature Modulator (AQM) When the AQM common-mode voltage is close to ground, the DAC1405D750 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 19 provides an example of a connection to an AQM with a 0.5 VI(cm) common-mode input level using auxiliary DACs. VDDA(3V3) 66.5 Ω (1) 5V 66.5 Ω 2 kΩ AQM (Vi(cm) = 0.5 V) (2) 2 kΩ 10 nF IOUTnP BBP 10 nF IOUTnN BBN 0 mA to 20 mA 174 Ω 174 Ω 34 Ω 34 Ω AUXnP AUXnN 1.1 mA (typ.) (1) IOUTnP/IOUTnN; V o(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV 001aaj589 Fig 19. An example of an AC interface to a 0.5 VI(cm) AQM using auxiliary DACs DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 35 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.15 Power and grounding In order to obtain optimum performance, it is recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with the ones on pins 6, 70, 79, 81, 83, 93, 95 and 97 on the top layer. To optimize the decoupling, the power supplies should be decoupled with the following ground pins: • VDDD(1V8): pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43 and pin 50 with 49. • VDD(IO)(3V3): pin 16 with 17 and pin 60 with 59. • VDDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins 79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98. • VDDA(3V3): pin 1 with 100 and pin 75 with 76. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 36 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 11. Package outline HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad SOT638-1 c y exposed die pad side X Dh A 75 51 76 50 ZE e E HE Eh A A2 (A3) A1 w M θ bp Lp pin 1 index L detail X 26 100 1 25 bp e w M ZD v M A D B HD v M B 0 10 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 A2 A3 bp c D(1) Dh E(1) Eh e 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 7.1 6.1 14.1 13.9 7.1 6.1 0.5 HD HE 16.15 16.15 15.85 15.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) θ 1.15 0.85 7° 0° 1.15 0.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 05-02-02 MS-026 Fig 20. Package outline SOT638-1 (HTQFP100) DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 37 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 12. Abbreviations Table 43. DAC1405D750 Product data sheet Abbreviations Acronym Description B Bandwidth CDMA Code Division Multiple Access CML Current Mode Logic CMOS Complementary Metal-Oxide Semiconductor DAC Digital-to-Analog Converter FIR Finite Impulse Response GSM Global System for Mobile communications IF Intermediate Frequency IMD3 Third-order InterModulation Distortion LISB Lower Intermediate Significant Byte LMDS Local Multipoint Distribution Service LSB Least Significant Bit LTE Long Term Evolution LVDS Low-Voltage Differential Signaling MMDS Multichannel Multipoint Distribution Service MSB Most Significant Bit NCO Numerically Controlled Oscillator NMOS Negative Metal-Oxide Semiconductor PLL Phase-Locked Loop SFDR Spurious-Free Dynamic Range SPI Serial Peripheral Interface TD-SCDMA Time Division-Synchronous Code Division Multiple Access UISB Upper Intermediate Significant Byte WCDMA Wideband Code Division Multiple Access WiMAX Worldwide Interoperability for Microwave Access All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 38 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 13. Glossary Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products IMD2 and IMD3 (respectively, second and third-order components) are defined below. IMD2 — The ratio of the RMS value of either tone to the RMS value of the worst second order intermodulation product. IMD3 — The ratio of the RMS value of either tone to the RMS value of the worst third order intermodulation product. Restricted Bandwidth Spurious Free Dynamic Range — The ratio of the RMS value of the reconstructed output sine wave to the RMS value of the noise, including the harmonics, in a given bandwidth centered around foffset. 14. Revision history Table 44. Revision history Document ID Release date Data sheet status Change notice Supersedes DAC1405D750 v.4 20110607 Product data sheet - DAC1405D750 v.3 Modifications: • • Section 2 “Features and benefits” has been updated. LOW-level input voltage and HIGH-level input voltage values for Digital inputs (I0 to I13, Q0 to Q13) in Table 5 “Characteristics” have been updated. DAC1405D750 v.3 20100907 Product data sheet - DAC1405D750 v.2 DAC1405D750 v.2 20100727 Product data sheet - DAC1405D750 v.1 DAC1405D750 v.1 20100310 Preliminary data sheet - - DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 39 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 40 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] DAC1405D750 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 7 June 2011 © NXP B.V. 2011. All rights reserved. 41 of 42 DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.3 10.3.1 10.3.2 10.4 10.5 10.5.1 10.5.2 10.6 10.7 10.7.1 10.7.2 10.7.3 10.8 10.9 10.10 10.10.1 10.10.2 10.11 10.12 10.13 10.14 10.14.1 10.14.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics . . . . . . . . . . . . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 13 General description . . . . . . . . . . . . . . . . . . . . 13 Serial peripheral interface. . . . . . . . . . . . . . . . 13 Protocol description . . . . . . . . . . . . . . . . . . . . 13 SPI timing description . . . . . . . . . . . . . . . . . . . 14 Detailed descriptions of registers . . . . . . . . . . 15 Detailed register descriptions . . . . . . . . . . . . . 17 Recommended configuration . . . . . . . . . . . . . 22 Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . 22 Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 22 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timing when using the internal PLL (PLL on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timing when using an external PLL (PLL off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Quadrature modulator and Numerically Controlled Oscillator (NCO) . . . . . . . . . . . . . . 26 NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 27 Low-power NCO . . . . . . . . . . . . . . . . . . . . . . . 27 Minus_3dB function . . . . . . . . . . . . . . . . . . . . 27 x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DAC transfer function . . . . . . . . . . . . . . . . . . . 28 Full-scale current . . . . . . . . . . . . . . . . . . . . . . 28 Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Full-scale current adjustment . . . . . . . . . . . . . 29 Digital offset adjustment . . . . . . . . . . . . . . . . . 30 Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 31 Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 32 Output configuration . . . . . . . . . . . . . . . . . . . . 32 Basic output configuration . . . . . . . . . . . . . . . 32 DC interface to an Analog Quadrature Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 33 10.14.3 10.15 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 AC interface to an Analog Quadrature Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . Power and grounding. . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 37 38 39 39 40 40 40 40 41 41 42 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 June 2011 Document identifier: DAC1405D750